repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/decoder.vhd | 1 | 51,378 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity InstrDecoder is generic (
async_reset : boolean;
fpu_ena : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_any_hold : in std_logic; -- Hold pipeline by any reason
i_f_valid : in std_logic; -- Fetch input valid
i_f_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Fetched pc
i_f_instr : in std_logic_vector(31 downto 0); -- Fetched instruction value
i_instr_load_fault : in std_logic; -- Instruction fetched from fault address
i_instr_executable : in std_logic; -- MPU flag
o_radr1 : out std_logic_vector(5 downto 0); -- register bank address 1 (rs1)
o_radr2 : out std_logic_vector(5 downto 0); -- register bank address 2 (rs2)
o_waddr : out std_logic_vector(5 downto 0); -- register bank output (rd)
o_csr_addr : out std_logic_vector(11 downto 0); -- CSR bank output
o_imm : out std_logic_vector(RISCV_ARCH-1 downto 0); -- immediate constant decoded from instruction
i_e_ready : in std_logic; -- execute stage ready to accept next instruction
i_flush_pipeline : in std_logic; -- reset pipeline and cache
i_progbuf_ena : in std_logic; -- executing from progbuf
o_valid : out std_logic; -- Current output values are valid
o_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Current instruction pointer value
o_instr : out std_logic_vector(31 downto 0); -- Current instruction value
o_memop_store : out std_logic; -- Store to memory operation
o_memop_load : out std_logic; -- Load from memoru operation
o_memop_sign_ext : out std_logic; -- Load memory value with sign extending
o_memop_size : out std_logic_vector(1 downto 0); -- Memory transaction size
o_rv32 : out std_logic; -- 32-bits instruction
o_compressed : out std_logic; -- 16-bits opcode (C-extension)
o_f64 : out std_logic; -- 64-bits FPU (D-extension)
o_unsigned_op : out std_logic; -- Unsigned operands
o_isa_type : out std_logic_vector(ISA_Total-1 downto 0); -- Instruction format accordingly with ISA
o_instr_vec : out std_logic_vector(Instr_Total-1 downto 0); -- One bit per decoded instruction bus
o_exception : out std_logic; -- Unimplemented instruction
o_instr_load_fault : out std_logic; -- Instruction fetched from fault address
o_instr_executable : out std_logic; -- MPU flag
o_progbuf_ena : out std_logic
);
end;
architecture arch_InstrDecoder of InstrDecoder is
-- LB, LH, LW, LD, LBU, LHU, LWU
constant OPCODE_LB : std_logic_vector(4 downto 0) := "00000";
-- FLD
constant OPCODE_FPU_LD : std_logic_vector(4 downto 0) := "00001";
-- FENCE, FENCE_I
constant OPCODE_FENCE : std_logic_vector(4 downto 0) := "00011";
-- ADDI, ANDI, ORI, SLLI, SLTI, SLTIU, SRAI, SRLI, XORI
constant OPCODE_ADDI : std_logic_vector(4 downto 0) := "00100";
-- AUIPC
constant OPCODE_AUIPC : std_logic_vector(4 downto 0) := "00101";
-- ADDIW, SLLIW, SRAIW, SRLIW
constant OPCODE_ADDIW : std_logic_vector(4 downto 0) := "00110";
-- SB, SH, SW, SD
constant OPCODE_SB : std_logic_vector(4 downto 0) := "01000";
-- FSD
constant OPCODE_FPU_SD : std_logic_vector(4 downto 0) := "01001";
-- ADD, AND, OR, SLT, SLTU, SLL, SRA, SRL, SUB, XOR, DIV, DIVU, MUL, REM, REMU
constant OPCODE_ADD : std_logic_vector(4 downto 0) := "01100";
-- LUI
constant OPCODE_LUI : std_logic_vector(4 downto 0) := "01101";
-- ADDW, SLLW, SRAW, SRLW, SUBW, DIVW, DIVUW, MULW, REMW, REMUW
constant OPCODE_ADDW : std_logic_vector(4 downto 0) := "01110";
-- FPU operations
constant OPCODE_FPU_OP : std_logic_vector(4 downto 0) := "10100";
-- BEQ, BNE, BLT, BGE, BLTU, BGEU
constant OPCODE_BEQ : std_logic_vector(4 downto 0) := "11000";
-- JALR
constant OPCODE_JALR : std_logic_vector(4 downto 0) := "11001";
-- JAL
constant OPCODE_JAL : std_logic_vector(4 downto 0) := "11011";
-- CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI, URET, SRET, HRET, MRET
constant OPCODE_CSRR : std_logic_vector(4 downto 0) := "11100";
-- Compressed instruction set
constant OPCODE_C_ADDI4SPN : std_logic_vector(4 downto 0) := "00000";
constant OPCODE_C_NOP_ADDI : std_logic_vector(4 downto 0) := "00001";
constant OPCODE_C_SLLI : std_logic_vector(4 downto 0) := "00010";
constant OPCODE_C_JAL_ADDIW : std_logic_vector(4 downto 0) := "00101";
constant OPCODE_C_LW : std_logic_vector(4 downto 0) := "01000";
constant OPCODE_C_LI : std_logic_vector(4 downto 0) := "01001";
constant OPCODE_C_LWSP : std_logic_vector(4 downto 0) := "01010";
constant OPCODE_C_LD : std_logic_vector(4 downto 0) := "01100";
constant OPCODE_C_ADDI16SP_LUI : std_logic_vector(4 downto 0) := "01101";
constant OPCODE_C_LDSP : std_logic_vector(4 downto 0) := "01110";
constant OPCODE_C_MATH : std_logic_vector(4 downto 0) := "10001";
constant OPCODE_C_JR_MV_EBREAK_JALR_ADD : std_logic_vector(4 downto 0) := "10010";
constant OPCODE_C_J : std_logic_vector(4 downto 0) := "10101";
constant OPCODE_C_SW : std_logic_vector(4 downto 0) := "11000";
constant OPCODE_C_BEQZ : std_logic_vector(4 downto 0) := "11001";
constant OPCODE_C_SWSP : std_logic_vector(4 downto 0) := "11010";
constant OPCODE_C_SD : std_logic_vector(4 downto 0) := "11100";
constant OPCODE_C_BNEZ : std_logic_vector(4 downto 0) := "11101";
constant OPCODE_C_SDSP : std_logic_vector(4 downto 0) := "11110";
constant INSTR_NONE : std_logic_vector(Instr_Total-1 downto 0) := (others => '0');
type RegistersType is record
valid : std_logic;
pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
isa_type : std_logic_vector(ISA_Total-1 downto 0);
instr_vec : std_logic_vector(Instr_Total-1 downto 0);
instr : std_logic_vector(31 downto 0);
memop_store : std_logic;
memop_load : std_logic;
memop_sign_ext : std_logic;
memop_size : std_logic_vector(1 downto 0);
unsigned_op : std_logic;
rv32 : std_logic;
f64 : std_logic;
compressed : std_logic;
instr_load_fault : std_logic;
instr_executable : std_logic;
instr_unimplemented : std_logic;
radr1 : std_logic_vector(5 downto 0);
radr2 : std_logic_vector(5 downto 0);
waddr : std_logic_vector(5 downto 0);
csr_addr : std_logic_vector(11 downto 0);
imm : std_logic_vector(RISCV_ARCH-1 downto 0);
progbuf_ena : std_logic;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), (others => '0'), -- valid, pc, isa_type
(others => '0'), (others => '0'), '0', -- instr_vec, instr, memop_store
'0', '0', "00", -- memop_load, memop_sign_ext, memop_size
'0', '0', '0', -- unsigned_op, rv32, f64
'0', '0', '0', -- compressed, instr_load_fault, instr_executable
'0', -- instr_unimpl
(others => '0'), -- radr1
(others => '0'), -- radr2
(others => '0'), -- waddr
(others => '0'), -- csr_addr
(others => '0'), -- imm
'0' -- progbuf_ena
);
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_any_hold, i_f_valid, i_f_pc, i_f_instr, i_instr_load_fault,
i_instr_executable, i_e_ready, i_flush_pipeline, i_progbuf_ena, r)
variable v : RegistersType;
variable w_o_valid : std_logic;
variable w_error : std_logic;
variable w_compressed : std_logic;
variable wb_instr : std_logic_vector(31 downto 0);
variable wb_instr_out : std_logic_vector(31 downto 0);
variable wb_opcode1 : std_logic_vector(4 downto 0);
variable wb_opcode2 : std_logic_vector(2 downto 0);
variable wb_dec : std_logic_vector(Instr_Total-1 downto 0);
variable wb_isa_type : std_logic_vector(ISA_Total-1 downto 0);
variable vb_radr1 : std_logic_vector(5 downto 0);
variable vb_radr2 : std_logic_vector(5 downto 0);
variable vb_waddr : std_logic_vector(5 downto 0);
variable vb_csr_addr : std_logic_vector(11 downto 0);
variable vb_imm : std_logic_vector(RISCV_ARCH-1 downto 0);
begin
v := r;
w_error := '0';
w_compressed := '0';
wb_instr := i_f_instr;
wb_opcode1 := wb_instr(6 downto 2);
wb_opcode2 := wb_instr(14 downto 12);
wb_dec := (others => '0');
wb_isa_type := (others => '0');
vb_radr1 := (others => '0');
vb_radr2 := (others => '0');
vb_waddr := (others => '0');
vb_csr_addr := (others => '0');
vb_imm := (others => '0');
if wb_instr(1 downto 0) /= "11" then
w_compressed := '1';
wb_opcode1 := wb_instr(15 downto 13) & wb_instr(1 downto 0);
wb_instr_out := X"00000003";
case wb_opcode1 is
when OPCODE_C_ADDI4SPN =>
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_ADDI) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(4 downto 2); -- rd
wb_instr_out(19 downto 15) := "00010"; -- rs1 = sp
wb_instr_out(29 downto 22) :=
wb_instr(10 downto 7) & wb_instr(12 downto 11) & wb_instr(5) & wb_instr(6);
vb_radr1 := "000010"; -- rs1 = sp
vb_waddr := "001" & wb_instr(4 downto 2); -- rd
vb_imm(9 downto 2) := wb_instr(10 downto 7) & wb_instr(12 downto 11)
& wb_instr(5) & wb_instr(6);
when OPCODE_C_NOP_ADDI =>
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_ADDI) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(19 downto 15) := wb_instr(11 downto 7); -- rs1
wb_instr_out(24 downto 20) := wb_instr(6 downto 2); -- imm
if wb_instr(12) = '1' then
wb_instr_out(31 downto 25) := (others => '1');
end if;
vb_radr1 := '0' & wb_instr(11 downto 7); -- rs1
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(4 downto 0) := wb_instr(6 downto 2);
vb_imm(RISCV_ARCH-1 downto 5) := (others => wb_instr(12));
when OPCODE_C_SLLI =>
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_SLLI) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(19 downto 15) := wb_instr(11 downto 7); -- rs1
wb_instr_out(25 downto 20) := wb_instr(12) & wb_instr(6 downto 2); -- shamt
vb_radr1 := '0' & wb_instr(11 downto 7); -- rs1
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(5 downto 0) := wb_instr(12) & wb_instr(6 downto 2);
when OPCODE_C_JAL_ADDIW =>
-- JAL is the RV32C only instruction
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_ADDIW) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(19 downto 15) := wb_instr(11 downto 7); -- rs1
wb_instr_out(24 downto 20) := wb_instr(6 downto 2); -- imm
if wb_instr(12) = '1' then
wb_instr_out(31 downto 25) := (others => '1');
end if;
vb_radr1 := '0' & wb_instr(11 downto 7); -- rs1
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(4 downto 0) := wb_instr(6 downto 2);
vb_imm(RISCV_ARCH-1 downto 5) := (others => wb_instr(12));
when OPCODE_C_LW =>
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_LW) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(4 downto 2); -- rd
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(26 downto 22) :=
wb_instr(5) & wb_instr(12 downto 10) & wb_instr(6);
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_waddr := "001" & wb_instr(4 downto 2); -- rd
vb_imm(6 downto 2) := wb_instr(5) & wb_instr(12 downto 10) & wb_instr(6);
when OPCODE_C_LI => -- ADDI rd = r0 + imm
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_ADDI) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(24 downto 20) := wb_instr(6 downto 2); -- imm
if wb_instr(12) = '1' then
wb_instr_out(31 downto 25) := (others => '1');
end if;
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(4 downto 0) := wb_instr(6 downto 2);
vb_imm(RISCV_ARCH-1 downto 5) := (others => wb_instr(12));
when OPCODE_C_LWSP =>
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_LW) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(19 downto 15) := "00010"; -- rs1 = sp
wb_instr_out(27 downto 22) :=
wb_instr(3 downto 2) & wb_instr(12) & wb_instr(6 downto 4);
vb_radr1 := "000010"; -- rs1 = sp
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(7 downto 2) := wb_instr(3 downto 2) & wb_instr(12) & wb_instr(6 downto 4);
when OPCODE_C_LD =>
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_LD) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(4 downto 2); -- rd
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(27 downto 23) :=
wb_instr(6) & wb_instr(5) & wb_instr(12 downto 10);
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_waddr := "001" & wb_instr(4 downto 2); -- rd
vb_imm(7 downto 3) := wb_instr(6) & wb_instr(5) & wb_instr(12 downto 10);
when OPCODE_C_ADDI16SP_LUI =>
if wb_instr(11 downto 7) = "00010" then
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_ADDI) := '1';
wb_instr_out(11 downto 7) := "00010"; -- rd = sp
wb_instr_out(19 downto 15) := "00010"; -- rs1 = sp
wb_instr_out(28 downto 24) :=
wb_instr(4 downto 3) & wb_instr(5) & wb_instr(2) & wb_instr(6);
if wb_instr(12) = '1' then
wb_instr_out(31 downto 29) := (others => '1');
end if;
vb_radr1 := "000010"; -- rs1 = sp
vb_waddr := "000010"; -- rd = sp
vb_imm(8 downto 4) := wb_instr(4 downto 3) & wb_instr(5) & wb_instr(2) & wb_instr(6);
vb_imm(RISCV_ARCH-1 downto 9) := (others => wb_instr(12));
else
wb_isa_type(ISA_U_type) := '1';
wb_dec(Instr_LUI) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(16 downto 12) := wb_instr(6 downto 2);
if wb_instr(12) = '1' then
wb_instr_out(31 downto 17) := (others => '1');
end if;
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(16 downto 12) := wb_instr(6 downto 2);
vb_imm(RISCV_ARCH-1 downto 17) := (others => wb_instr(12));
end if;
when OPCODE_C_LDSP =>
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_LD) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(19 downto 15) := "00010"; -- rs1 = sp
wb_instr_out(28 downto 23) :=
wb_instr(4 downto 2) & wb_instr(12) & wb_instr(6 downto 5);
vb_radr1 := "000010"; -- rs1 = sp
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(8 downto 3) := wb_instr(4 downto 2) & wb_instr(12) & wb_instr(6 downto 5);
when OPCODE_C_MATH =>
if wb_instr(11 downto 10) = "00" then
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_SRLI) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(9 downto 7); -- rd
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(25 downto 20) := wb_instr(12) & wb_instr(6 downto 2); -- shamt
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_waddr := "001" & wb_instr(9 downto 7); -- rd
vb_imm(5 downto 0) := wb_instr(12) & wb_instr(6 downto 2); -- shamt
elsif wb_instr(11 downto 10) = "01" then
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_SRAI) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(9 downto 7); -- rd
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(25 downto 20) := wb_instr(12) & wb_instr(6 downto 2); -- shamt
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_waddr := "001" & wb_instr(9 downto 7); -- rd
vb_imm(5 downto 0) := wb_instr(12) & wb_instr(6 downto 2); -- shamt
elsif wb_instr(11 downto 10) = "10" then
wb_isa_type(ISA_I_type) := '1';
wb_dec(Instr_ANDI) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(9 downto 7); -- rd
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(24 downto 20) := wb_instr(6 downto 2); -- imm
if wb_instr(12) = '1' then
wb_instr_out(31 downto 25) := (others => '1');
end if;
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_waddr := "001" & wb_instr(9 downto 7); -- rd
vb_imm(4 downto 0) := wb_instr(6 downto 2);
vb_imm(RISCV_ARCH-1 downto 5) := (others => wb_instr(12));
elsif wb_instr(12) = '0' then
wb_isa_type(ISA_R_type) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(9 downto 7); -- rd
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(24 downto 20) := "01" & wb_instr(4 downto 2); -- rs2
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_radr2 := "001" & wb_instr(4 downto 2); -- rs2
vb_waddr := "001" & wb_instr(9 downto 7); -- rd
case wb_instr(6 downto 5) is
when "00" =>
wb_dec(Instr_SUB) := '1';
when "01" =>
wb_dec(Instr_XOR) := '1';
when "10" =>
wb_dec(Instr_OR) := '1';
when others =>
wb_dec(Instr_AND) := '1';
end case;
else
wb_isa_type(ISA_R_type) := '1';
wb_instr_out(11 downto 7) := "01" & wb_instr(9 downto 7); -- rd
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(24 downto 20) := "01" & wb_instr(4 downto 2); -- rs2
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_radr2 := "001" & wb_instr(4 downto 2); -- rs2
vb_waddr := "001" & wb_instr(9 downto 7); -- rd
case wb_instr(6 downto 5) is
when "00" =>
wb_dec(Instr_SUBW) := '1';
when "01" =>
wb_dec(Instr_ADDW) := '1';
when others =>
w_error := '1';
end case;
end if;
when OPCODE_C_JR_MV_EBREAK_JALR_ADD =>
wb_isa_type(ISA_I_type) := '1';
if wb_instr(12) = '0' then
if wb_instr(6 downto 2) = "00000" then
wb_dec(Instr_JALR) := '1';
wb_instr_out(19 downto 15) := wb_instr(11 downto 7); -- rs1
vb_radr1 := '0' & wb_instr(11 downto 7); -- rs1
else
wb_dec(Instr_ADDI) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(19 downto 15) := wb_instr(6 downto 2); -- rs1
vb_radr1 := '0' & wb_instr(6 downto 2); -- rs1
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
end if;
else
if wb_instr(11 downto 7) = "00000" and wb_instr(6 downto 2) = "00000" then
wb_dec(Instr_EBREAK) := '1';
elsif wb_instr(6 downto 2) = "00000" then
wb_dec(Instr_JALR) := '1';
wb_instr_out(11 downto 7) := "00001"; -- rd = ra
wb_instr_out(19 downto 15) := wb_instr(11 downto 7); -- rs1
vb_radr1 := '0' & wb_instr(11 downto 7); -- rs1;
vb_waddr := "000001";
else
wb_dec(Instr_ADD) := '1';
wb_isa_type(ISA_R_type) := '1';
wb_instr_out(11 downto 7) := wb_instr(11 downto 7); -- rd
wb_instr_out(19 downto 15) := wb_instr(11 downto 7); -- rs1
wb_instr_out(24 downto 20) := wb_instr(6 downto 2); -- rs2
vb_radr1 := '0' & wb_instr(11 downto 7); -- rs1
vb_radr2 := '0' & wb_instr(6 downto 2); -- rs2
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
end if;
end if;
when OPCODE_C_J => -- JAL with rd = 0
wb_isa_type(ISA_UJ_type) := '1';
wb_dec(Instr_JAL) := '1';
wb_instr_out(20) := wb_instr(12); -- imm11
wb_instr_out(23 downto 21) := wb_instr(5 downto 3); -- imm10_1(3:1)
wb_instr_out(24) := wb_instr(11); -- imm10_1(4)
wb_instr_out(25) := wb_instr(2); -- imm10_1(5)
wb_instr_out(26) := wb_instr(7); -- imm10_1(6)
wb_instr_out(27) := wb_instr(6); -- imm10_1(7)
wb_instr_out(29 downto 28) := wb_instr(10 downto 9); -- imm10_1(9:8)
wb_instr_out(30) := wb_instr(8); -- imm10_1(10)
if wb_instr(12) = '1' then
wb_instr_out(19 downto 12) := (others => '1'); -- imm19_12
wb_instr_out(31) := '1'; -- imm20
end if;
vb_imm(10 downto 1) := wb_instr(8) & wb_instr(10 downto 9) & wb_instr(6) & wb_instr(7)
& wb_instr(2) & wb_instr(11) & wb_instr(5 downto 3);
vb_imm(RISCV_ARCH-1 downto 11) := (others => wb_instr(12));
when OPCODE_C_SW =>
wb_isa_type(ISA_S_type) := '1';
wb_dec(Instr_SW) := '1';
wb_instr_out(24 downto 20) := "01" & wb_instr(4 downto 2); -- rs2
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(11 downto 9) := wb_instr(11 downto 10) & wb_instr(6);
wb_instr_out(26 downto 25) := wb_instr(5) & wb_instr(12);
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_radr2 := "001" & wb_instr(4 downto 2); -- rs2
vb_imm(6 downto 2) := wb_instr(5) & wb_instr(12) & wb_instr(11 downto 10) & wb_instr(6);
when OPCODE_C_BEQZ =>
wb_isa_type(ISA_SB_type) := '1';
wb_dec(Instr_BEQ) := '1';
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(11 downto 8) := wb_instr(11 downto 10) & wb_instr(4 downto 3);
wb_instr_out(27 downto 25) := wb_instr(6 downto 5) & wb_instr(2);
if wb_instr(12) = '1' then
wb_instr_out(30 downto 28) := (others => '1');
wb_instr_out(7) := '1';
wb_instr_out(31) := '1';
end if;
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_imm(7 downto 1) := wb_instr(6 downto 5) & wb_instr(2)
& wb_instr(11 downto 10) & wb_instr(4 downto 3);
vb_imm(RISCV_ARCH-1 downto 8) := (others => wb_instr(12));
when OPCODE_C_SWSP =>
wb_isa_type(ISA_S_type) := '1';
wb_dec(Instr_SW) := '1';
wb_instr_out(24 downto 20) := wb_instr(6 downto 2); -- rs2
wb_instr_out(19 downto 15) := "00010"; -- rs1 = sp
wb_instr_out(11 downto 9) := wb_instr(11 downto 9);
wb_instr_out(27 downto 25) := wb_instr(8 downto 7) & wb_instr(12);
vb_radr1 := "000010"; -- rs1 = sp
vb_radr2 := '0' & wb_instr(6 downto 2); -- rs2
vb_imm(7 downto 2) := wb_instr(8 downto 7) & wb_instr(12) & wb_instr(11 downto 9);
when OPCODE_C_SD =>
wb_isa_type(ISA_S_type) := '1';
wb_dec(Instr_SD) := '1';
wb_instr_out(24 downto 20) := "01" & wb_instr(4 downto 2); -- rs2
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(11 downto 10) := wb_instr(11 downto 10);
wb_instr_out(27 downto 25) := wb_instr(6 downto 5) & wb_instr(12);
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_radr2 := "001" & wb_instr(4 downto 2); -- rs2
vb_imm(7 downto 3) := wb_instr(6 downto 5) & wb_instr(12) & wb_instr(11 downto 10);
when OPCODE_C_BNEZ =>
wb_isa_type(ISA_SB_type) := '1';
wb_dec(Instr_BNE) := '1';
wb_instr_out(19 downto 15) := "01" & wb_instr(9 downto 7); -- rs1
wb_instr_out(11 downto 8) := wb_instr(11 downto 10) & wb_instr(4 downto 3);
wb_instr_out(27 downto 25) := wb_instr(6 downto 5) & wb_instr(2);
if wb_instr(12) = '1' then
wb_instr_out(30 downto 28) := (others => '1');
wb_instr_out(7) := '1';
wb_instr_out(31) := '1';
end if;
vb_radr1 := "001" & wb_instr(9 downto 7); -- rs1
vb_imm(7 downto 1) := wb_instr(6 downto 5) & wb_instr(2)
& wb_instr(11 downto 10) & wb_instr(4 downto 3);
vb_imm(RISCV_ARCH-1 downto 8) := (others => wb_instr(12));
when OPCODE_C_SDSP =>
wb_isa_type(ISA_S_type) := '1';
wb_dec(Instr_SD) := '1';
wb_instr_out(24 downto 20) := wb_instr(6 downto 2); -- rs2
wb_instr_out(19 downto 15) := "00010"; -- rs1 = sp
wb_instr_out(11 downto 10) := wb_instr(11 downto 10);
wb_instr_out(28 downto 25) := wb_instr(9 downto 7) & wb_instr(12);
vb_radr1 := "000010"; -- rs1 = sp
vb_radr2 := '0' & wb_instr(6 downto 2); -- rs2
vb_imm(8 downto 3) := wb_instr(9 downto 7) & wb_instr(12) & wb_instr(11 downto 10);
when others =>
w_error := '1';
end case;
else -- compressed/!not compressed
case wb_opcode1 is
when OPCODE_ADD =>
wb_isa_type(ISA_R_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_radr2 := '0' & wb_instr(24 downto 20);
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
case wb_opcode2 is
when "000" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_ADD) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_MUL) := '1';
elsif wb_instr(31 downto 25) = "0100000" then
wb_dec(Instr_SUB) := '1';
else
w_error := '1';
end if;
when "001" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_SLL) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_MULH) := '1';
else
w_error := '1';
end if;
when "010" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_SLT) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_MULHSU) := '1';
else
w_error := '1';
end if;
when "011" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_SLTU) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_MULHU) := '1';
else
w_error := '1';
end if;
when "100" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_XOR) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_DIV) := '1';
else
w_error := '1';
end if;
when "101" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_SRL) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_DIVU) := '1';
elsif wb_instr(31 downto 25) = "0100000" then
wb_dec(Instr_SRA) := '1';
else
w_error := '1';
end if;
when "110" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_OR) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_REM) := '1';
else
w_error := '1';
end if;
when "111" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_AND) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_REMU) := '1';
else
w_error := '1';
end if;
when others =>
w_error := '1';
end case;
when OPCODE_ADDI =>
wb_isa_type(ISA_I_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(11 downto 0) := wb_instr(31 downto 20);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
case wb_opcode2 is
when "000" =>
wb_dec(Instr_ADDI) := '1';
when "001" =>
wb_dec(Instr_SLLI) := '1';
when "010" =>
wb_dec(Instr_SLTI) := '1';
when "011" =>
wb_dec(Instr_SLTIU) := '1';
when "100" =>
wb_dec(Instr_XORI) := '1';
when "101" =>
if wb_instr(31 downto 26) = "000000" then
wb_dec(Instr_SRLI) := '1';
elsif wb_instr(31 downto 26) = "010000" then
wb_dec(Instr_SRAI) := '1';
else
w_error := '1';
end if;
when "110" =>
wb_dec(Instr_ORI) := '1';
when "111" =>
wb_dec(Instr_ANDI) := '1';
when others =>
w_error := '1';
end case;
when OPCODE_ADDIW =>
wb_isa_type(ISA_I_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(11 downto 0) := wb_instr(31 downto 20);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
case wb_opcode2 is
when "000" =>
wb_dec(Instr_ADDIW) := '1';
when "001" =>
wb_dec(Instr_SLLIW) := '1';
when "101" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_SRLIW) := '1';
elsif wb_instr(31 downto 25) = "0100000" then
wb_dec(Instr_SRAIW) := '1';
else
w_error := '1';
end if;
when others =>
w_error := '1';
end case;
when OPCODE_ADDW =>
wb_isa_type(ISA_R_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_radr2 := '0' & wb_instr(24 downto 20);
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
case wb_opcode2 is
when "000" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_ADDW) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_MULW) := '1';
elsif wb_instr(31 downto 25) = "0100000" then
wb_dec(Instr_SUBW) := '1';
else
w_error := '1';
end if;
when "001" =>
wb_dec(Instr_SLLW) := '1';
when "100" =>
if wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_DIVW) := '1';
else
w_error := '1';
end if;
when "101" =>
if wb_instr(31 downto 25) = "0000000" then
wb_dec(Instr_SRLW) := '1';
elsif wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_DIVUW) := '1';
elsif wb_instr(31 downto 25) = "0100000" then
wb_dec(Instr_SRAW) := '1';
else
w_error := '1';
end if;
when "110" =>
if wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_REMW) := '1';
else
w_error := '1';
end if;
when "111" =>
if wb_instr(31 downto 25) = "0000001" then
wb_dec(Instr_REMUW) := '1';
else
w_error := '1';
end if;
when others =>
w_error := '1';
end case;
when OPCODE_AUIPC =>
wb_isa_type(ISA_U_type) := '1';
wb_dec(Instr_AUIPC) := '1';
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(31 downto 12) := wb_instr(31 downto 12);
vb_imm(RISCV_ARCH-1 downto 32) := (others => wb_instr(31));
when OPCODE_BEQ =>
wb_isa_type(ISA_SB_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_radr2 := '0' & wb_instr(24 downto 20);
vb_imm(11 downto 1) := wb_instr(7) & wb_instr(30 downto 25) & wb_instr(11 downto 8);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
case wb_opcode2 is
when "000" =>
wb_dec(Instr_BEQ) := '1';
when "001" =>
wb_dec(Instr_BNE) := '1';
when "100" =>
wb_dec(Instr_BLT) := '1';
when "101" =>
wb_dec(Instr_BGE) := '1';
when "110" =>
wb_dec(Instr_BLTU) := '1';
when "111" =>
wb_dec(Instr_BGEU) := '1';
when others =>
w_error := '1';
end case;
when OPCODE_JAL =>
wb_isa_type(ISA_UJ_type) := '1';
wb_dec(Instr_JAL) := '1';
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(19 downto 1) := wb_instr(19 downto 12) & wb_instr(20) & wb_instr(30 downto 21);
vb_imm(RISCV_ARCH-1 downto 20) := (others => wb_instr(31));
when OPCODE_JALR =>
wb_isa_type(ISA_I_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(11 downto 0) := wb_instr(31 downto 20);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
case wb_opcode2 is
when "000" =>
wb_dec(Instr_JALR) := '1';
when others =>
w_error := '1';
end case;
when OPCODE_LB =>
wb_isa_type(ISA_I_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(11 downto 0) := wb_instr(31 downto 20);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
case wb_opcode2 is
when "000" =>
wb_dec(Instr_LB) := '1';
when "001" =>
wb_dec(Instr_LH) := '1';
when "010" =>
wb_dec(Instr_LW) := '1';
when "011" =>
wb_dec(Instr_LD) := '1';
when "100" =>
wb_dec(Instr_LBU) := '1';
when "101" =>
wb_dec(Instr_LHU) := '1';
when "110" =>
wb_dec(Instr_LWU) := '1';
when others =>
w_error := '1';
end case;
when OPCODE_LUI =>
wb_isa_type(ISA_U_type) := '1';
wb_dec(Instr_LUI) := '1';
vb_waddr := '0' & wb_instr(11 downto 7); -- rd
vb_imm(31 downto 12) := wb_instr(31 downto 12);
vb_imm(RISCV_ARCH-1 downto 32) := (others => wb_instr(31));
when OPCODE_SB =>
wb_isa_type(ISA_S_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_radr2 := '0' & wb_instr(24 downto 20);
vb_imm(11 downto 0) := wb_instr(31 downto 25) & wb_instr(11 downto 7);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
case wb_opcode2 is
when "000" =>
wb_dec(Instr_SB) := '1';
when "001" =>
wb_dec(Instr_SH) := '1';
when "010" =>
wb_dec(Instr_SW) := '1';
when "011" =>
wb_dec(Instr_SD) := '1';
when others =>
w_error := '1';
end case;
when OPCODE_CSRR =>
wb_isa_type(ISA_I_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_waddr := '0' & wb_instr(11 downto 7);
vb_csr_addr(11 downto 0) := wb_instr(31 downto 20);
vb_imm(11 downto 0) := wb_instr(31 downto 20);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
case wb_opcode2 is
when "000" =>
if wb_instr = X"00000073" then
wb_dec(Instr_ECALL) := '1';
elsif wb_instr = X"00100073" then
wb_dec(Instr_EBREAK) := '1';
elsif wb_instr = X"00200073" then
wb_dec(Instr_URET) := '1';
elsif wb_instr = X"10200073" then
wb_dec(Instr_SRET) := '1';
elsif wb_instr = X"20200073" then
wb_dec(Instr_HRET) := '1';
elsif wb_instr = X"30200073" then
wb_dec(Instr_MRET) := '1';
else
w_error := '1';
end if;
when "001" =>
wb_dec(Instr_CSRRW) := '1';
when "010" =>
wb_dec(Instr_CSRRS) := '1';
when "011" =>
wb_dec(Instr_CSRRC) := '1';
when "101" =>
wb_dec(Instr_CSRRWI) := '1';
when "110" =>
wb_dec(Instr_CSRRSI) := '1';
when "111" =>
wb_dec(Instr_CSRRCI) := '1';
when others =>
w_error := '1';
end case;
when OPCODE_FENCE =>
case wb_opcode2 is
when "000" =>
wb_dec(Instr_FENCE) := '1';
when "001" =>
wb_dec(Instr_FENCE_I) := '1';
when others =>
w_error := '1';
end case;
when others =>
if fpu_ena then
case wb_opcode1 is
when OPCODE_FPU_LD =>
wb_isa_type(ISA_I_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_waddr := '1' & wb_instr(11 downto 7);
vb_imm(11 downto 0) := wb_instr(31 downto 20);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
if wb_opcode2 = "011" then
wb_dec(Instr_FLD) := '1';
else
w_error := '1';
end if;
when OPCODE_FPU_SD =>
wb_isa_type(ISA_S_type) := '1';
vb_radr1 := '0' & wb_instr(19 downto 15);
vb_radr2 := '1' & wb_instr(24 downto 20);
vb_imm(11 downto 0) := wb_instr(31 downto 25) & wb_instr(11 downto 7);
vb_imm(RISCV_ARCH-1 downto 12) := (others => wb_instr(31));
if wb_opcode2 = "011" then
wb_dec(Instr_FSD) := '1';
else
w_error := '1';
end if;
when OPCODE_FPU_OP =>
wb_isa_type(ISA_R_type) := '1';
vb_radr1 := '1' & wb_instr(19 downto 15);
vb_radr2 := '1' & wb_instr(24 downto 20);
vb_waddr := '1' & wb_instr(11 downto 7);
case wb_instr(31 downto 25) is
when "0000001" =>
wb_dec(Instr_FADD_D) := '1';
when "0000101" =>
wb_dec(Instr_FSUB_D) := '1';
when "0001001" =>
wb_dec(Instr_FMUL_D) := '1';
when "0001101" =>
wb_dec(Instr_FDIV_D) := '1';
when "0010101" =>
if wb_opcode2 = "000" then
wb_dec(Instr_FMIN_D) := '1';
elsif wb_opcode2 = "001" then
wb_dec(Instr_FMAX_D) := '1';
else
w_error := '1';
end if;
when "1010001" =>
vb_waddr(5) := '0';
if wb_opcode2 = "000" then
wb_dec(Instr_FLE_D) := '1';
elsif wb_opcode2 = "001" then
wb_dec(Instr_FLT_D) := '1';
elsif wb_opcode2 = "010" then
wb_dec(Instr_FEQ_D) := '1';
else
w_error := '1';
end if;
when "1100001" =>
vb_waddr(5) := '0';
if wb_instr(24 downto 20) = "00000" then
wb_dec(Instr_FCVT_W_D) := '1';
elsif wb_instr(24 downto 20) = "00001" then
wb_dec(Instr_FCVT_WU_D) := '1';
elsif wb_instr(24 downto 20) = "00010" then
wb_dec(Instr_FCVT_L_D) := '1';
elsif wb_instr(24 downto 20) = "00011" then
wb_dec(Instr_FCVT_LU_D) := '1';
else
w_error := '1';
end if;
when "1101001" =>
vb_radr1(5) := '0';
if wb_instr(24 downto 20) = "00000" then
wb_dec(Instr_FCVT_D_W) := '1';
elsif wb_instr(24 downto 20) = "00001" then
wb_dec(Instr_FCVT_D_WU) := '1';
elsif wb_instr(24 downto 20) = "00010" then
wb_dec(Instr_FCVT_D_L) := '1';
elsif wb_instr(24 downto 20) = "00011" then
wb_dec(Instr_FCVT_D_LU) := '1';
else
w_error := '1';
end if;
when "1110001" =>
vb_waddr(5) := '0';
if wb_instr(24 downto 20) = "00000" and wb_opcode2 = "000" then
wb_dec(Instr_FMOV_X_D) := '1';
else
w_error := '1';
end if;
when "1111001" =>
vb_radr1(5) := '0';
if wb_instr(24 downto 20) = "00000" and wb_opcode2 = "000" then
wb_dec(Instr_FMOV_D_X) := '1';
else
w_error := '1';
end if;
when others =>
w_error := '1';
end case;
when others =>
w_error := '1';
end case;
else
w_error := '1';
end if;
end case;
wb_instr_out := wb_instr;
end if;
if i_flush_pipeline = '1' and i_progbuf_ena = '0' then
v.pc := (others => '1');
v.valid := '0';
elsif i_e_ready = '1' and i_f_valid = '1' then
v.valid := '1';
v.pc := i_f_pc;
v.instr := i_f_instr;
v.compressed := w_compressed;
v.instr_load_fault := i_instr_load_fault;
v.instr_executable := i_instr_executable;
v.progbuf_ena := i_progbuf_ena;
v.isa_type := wb_isa_type;
v.instr_vec := wb_dec;
v.memop_store := wb_dec(Instr_SD) or wb_dec(Instr_SW)
or wb_dec(Instr_SH) or wb_dec(Instr_SB)
or wb_dec(Instr_FSD);
v.memop_load := wb_dec(Instr_LD) or wb_dec(Instr_LW)
or wb_dec(Instr_LH) or wb_dec(Instr_LB)
or wb_dec(Instr_LWU) or wb_dec(Instr_LHU)
or wb_dec(Instr_LBU) or wb_dec(Instr_FLD);
v.memop_sign_ext := wb_dec(Instr_LD) or wb_dec(Instr_LW)
or wb_dec(Instr_LH) or wb_dec(Instr_LB);
if (wb_dec(Instr_LD) or wb_dec(Instr_SD) or
wb_dec(Instr_FLD) or wb_dec(Instr_FSD)) = '1' then
v.memop_size := MEMOP_8B;
elsif (wb_dec(Instr_LW) or wb_dec(Instr_LWU) or wb_dec(Instr_SW)) = '1' then
v.memop_size := MEMOP_4B;
elsif (wb_dec(Instr_LH) or wb_dec(Instr_LHU) or wb_dec(Instr_SH)) = '1' then
v.memop_size := MEMOP_2B;
else
v.memop_size := MEMOP_1B;
end if;
v.unsigned_op := wb_dec(Instr_DIVU) or wb_dec(Instr_REMU) or
wb_dec(Instr_DIVUW) or wb_dec(Instr_REMUW) or
wb_dec(Instr_MULHU) or
wb_dec(Instr_FCVT_WU_D) or
wb_dec(Instr_FCVT_LU_D);
v.rv32 := wb_dec(Instr_ADDW) or wb_dec(Instr_ADDIW)
or wb_dec(Instr_SLLW) or wb_dec(Instr_SLLIW) or wb_dec(Instr_SRAW)
or wb_dec(Instr_SRAIW)
or wb_dec(Instr_SRLW) or wb_dec(Instr_SRLIW) or wb_dec(Instr_SUBW)
or wb_dec(Instr_DIVW) or wb_dec(Instr_DIVUW) or wb_dec(Instr_MULW)
or wb_dec(Instr_REMW) or wb_dec(Instr_REMUW);
v.f64 := wb_dec(Instr_FADD_D) or wb_dec(Instr_FSUB_D)
or wb_dec(Instr_FMUL_D) or wb_dec(Instr_FDIV_D)
or wb_dec(Instr_FMIN_D) or wb_dec(Instr_FMAX_D)
or wb_dec(Instr_FLE_D) or wb_dec(Instr_FLT_D)
or wb_dec(Instr_FEQ_D) or wb_dec(Instr_FCVT_W_D)
or wb_dec(Instr_FCVT_WU_D) or wb_dec(Instr_FCVT_L_D)
or wb_dec(Instr_FCVT_LU_D) or wb_dec(Instr_FMOV_X_D)
or wb_dec(Instr_FCVT_D_W) or wb_dec(Instr_FCVT_D_WU)
or wb_dec(Instr_FCVT_D_L) or wb_dec(Instr_FCVT_D_LU)
or wb_dec(Instr_FMOV_D_X) or wb_dec(Instr_FLD)
or wb_dec(Instr_FSD);
v.instr_unimplemented := w_error;
v.radr1 := vb_radr1;
v.radr2 := vb_radr2;
v.waddr := vb_waddr;
v.csr_addr := vb_csr_addr;
v.imm := vb_imm;
elsif i_any_hold = '0' then
v.valid := '0';
end if;
w_o_valid := r.valid;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
o_valid <= w_o_valid;
o_pc <= r.pc;
o_instr <= r.instr;
o_memop_load <= r.memop_load;
o_memop_store <= r.memop_store;
o_memop_sign_ext <= r.memop_sign_ext;
o_memop_size <= r.memop_size;
o_unsigned_op <= r.unsigned_op;
o_rv32 <= r.rv32;
o_f64 <= r.f64;
o_compressed <= r.compressed;
o_isa_type <= r.isa_type;
o_instr_vec <= r.instr_vec;
o_exception <= r.instr_unimplemented;
o_instr_load_fault <= r.instr_load_fault;
o_instr_executable <= r.instr_executable;
o_radr1 <= r.radr1;
o_radr2 <= r.radr2;
o_waddr <= r.waddr;
o_csr_addr <= r.csr_addr;
o_imm <= r.imm;
o_progbuf_ena <= r.progbuf_ena;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 2c995702a123d5303be4493e7be5fa2b | 0.449901 | 3.42383 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/clk_x_pntrs.vhd | 19 | 35,009 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
VHfaMJ2jDU0R2eAkOntfC5B4/6MobpZ0NSnc7trviKzQU5KHakm896MNUQ/U/XUDUOQl1Ix9hEug
uFcdFGHOlA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jZ28dq+cqatvP/oWT0j+kbhevax+rcvgcOVET6FHORIxsClPAe5EiSXk6mDgtoieHOJgnr3iO4zI
pViSw9QXhHwC7nkjQzCL5GNnIAYREubhi50JKwxrsTofbyKzT/U5b+jDP0girnK+nPIjwrQv3vvD
PHropUlOeQU1eg5rEJo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
wyTaR+5BBK3PMm+GuCvq0Bco7y5f/oiFqNMyoEJ+yA7qA21Rc24sV0Xv3v9W4doHSIdeeP0oUNh7
9I5Dbu7bsdY24p4a6rVQlpW5VOJjg7abnoTszev3jaBtBOpAM+FQDIkOj6hl9ZK+eUTOGH08ap1P
3rtu9S06fVXB15p5GUL4qJ+pbX9as7bXZJVw8JMDVFn1WsdJ/zMn5PNvL5qC5jZb/F7Sf9m7DkwY
x8I3vpZz7RsD6/RmMhT4lv1FkcH4MpJegB1J0hL5KoGG72FOKCqONCLsZdmnqz5BmJzgYmphlYZC
jJckdSX4yOLEg+jbosSObzMclIjrm9gORAOhKg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
qekQcsRlt2+SE3/eW9XQwKmx/wWWvcG3c3jSLvuGiy4GIetXM6PaXqKAuGTMI8b+mux4A6dEdodI
mIX5ojnf5ZA1jyISA9q0jKtn/LDbiV/JtKzm0pK23fPqh9/IUaTz+oirXN82WQzZFKQ5TKpwrFn6
ZmImSJcOKVgUcM/iG2U=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tlEZl/v6lEdJp5aVMLYyANJmLh8DNrpNnDhyEkIUHbeTfiozIDqQ3eefGpJHd1yUjxDr+M7d69UI
c7u5loKJo9CP6qAEjMhB9NE50dWkO/cRVvdlBQSlpGD8Asrd28oTNAHTTge+6t1TRCmYfvMKOt+b
zBqmGPTyIDG3LI8DiLXNfUjWjl16n5IRikeD/e8FsFJjAF/a0Kjal/N8CzCmRiQPdsZhdMiruSdi
vpIRkNPRNpCK4J6asTfuTemt2JkEkG10IvEYhZ/qTCco9PECc5G9y0loOf9owc6R54o3iALi9D4Q
T0iTW1tROVF1jLbRTIe753z7r02QD4PyC+02yQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24176)
`protect data_block
9uPgVvwI6RrrfFMtIq/SVSsHOE+nm05nS7PyyAHLch2CLIurm+XjDM/qD4/zNTuwYK+vMixdEPy9
r6/YroN3BA8QaoG9xTEyNkMBeQynuYgfxwipFH4GZw2nR1EKSom5L+ZL1RSiUI12KGEs5YirgWE3
9unGUEq6jhaSGvTxTbGU2a4XxC3p2eZhZCMDGApV13D8q7BlMfknZHAOFPUmU92u5tfQfCGsM/Ko
YY4B7hw3J2My/0fZUn1wBNTzrNTlXaG+OP5V+QK6e3Hkzui3G/FzaaSxfRxo88+th3SkWFi1RQ9R
+DfaT7N3GiKxZBbsLBBu+H+Aa08HKsSp1Wda5ILpT0RKHW1xFxPZDW7vLjahFKBqquyfRnPsvnU0
0rOyZVpI+4hVzpjjXgAVayFZEo1wSQyKbjN39s1nhs4l4i4rhLMshlhBQzIakbV19OWRohyQvpNT
1RJTqNO09c7QKQP0vqTKwNtA0dXeRy+2lXl5t0Rozc3t1L/RIEchUC1Bd4zaVkcfEKBFP9HV8y8V
X40AsHn1y7mqsSZGioltL+LBe9XHm8dhSO8a933sSlUwELFU2HfvvmjXYLIt/ovj/g+ixn+TDUm6
XZco9O6hXO/UEJkm8vwIIiYpgioXgNsBX5pfvhE642i2A4ACWtQacGlbYZf0kO7AYGTrX4D9B0xS
cebusFkSWFvpIUDEmF5fHj29Xtyqv4PF0dCcDaSrzR+iA5yaK+TbN0n48e5EUthf2kxRjWzw0BSj
kx7W0pvMPMJ1E0A9Gouw2WWvElH39cEdtjWi30sjfnT3IZm5geQwbRYxZvbDWGM6lgfcdZlOdmdx
KVIxmnWgFrbqSVIuRhmLmGskNTEHv8QZrdaSQHG9zcPBgnQxNjiT62+mxr13mXbYww9+/NOLnA/w
ysU0VEo3gDRrLY8NDxoclm/WWLqflzmeUesKgdu2VXNg7hrm6j5Dm0HfMjI7baSZuZm2ckUVbIG3
BLCCsC1XNsea7UwxBYbI+kd1NIDhhjJiA3TeOCtuYBnwzhsETPZGGPMR/32dOMPUL9mRnxP8+ooM
TNQKirBNwZN02C58lQhr5EVDFqwaB/lrwhKzH8vd+SxmjtH6HiPVoqJr8DyQo5vhFFT/g67QV2Hj
vGGVEinIL2MWRZ9HBix4YflxYlAfLPFH5qi7woXp/jU2b5ixeCoLEXXwXvn4AGpn6OWYPw8xwFgp
Hhqw2Uz/qqUm+b7Z7QnmlveGJp7iXiuDMpFS/hGwlp1gfEp7FqlXDyUMSXvaWljjJybJaQ5qenR5
6/3dVlFo7hguKSfMUx/vRcgNUfIytnWzLYpyeD8/n8AYjesqsu0QS+z7hoB//oT6kczH+uomWCFz
m1cxn77z/UQAWdPENPVLWNJ/dg14jU3onMp2iKOmhumx+J2mzmV5ZBQy+6nvnjvlae/aU+JuFxHJ
sHRItxkSFqmsYk/jbuLJv/6Gyqm4DUw9cBtRpmfRbLKN9OJ4Fm+88iwIr95DJ+pJhrzgEDLH/oKK
1Cle7mcYpiy8ma37Dg/8RuH7vjU+9V0oRSZobVaAVJCGZ/aCqSFTQafOGNXcBnvxsD9u47UeSu+w
egLAYPhuUZ7M9UZGfW3V54XgquLinsN22f1C5ayQvyPPYWqJ+uVhnGXQnvWY+grSosd/Fy5em5zs
K1XT1pOVwFrAtdRlkdB96fVIVaZOTAwTl07Vt59njjDj35eqQStsq5c4alD5D/mQ/dcE1//zabBo
4cqbWBm0Jf0je63V4MxzT0RGFM8JZ9d7NB9vZlbkrfPCI91DcqDtMOuC4U6WdYHayArXfpWvmVIi
77pqJeAvBrNjsjs0wyUIn90ULZtsCx0vaxv/p/yNcar5X3BpJ5yKe9QcbJR2ZfH6VHUMwa/HE5Xg
EaN1y3rOIl6d3e0+Z+/6gI2a4JvIlHyN6gucCWnDsHKUn7opPS4u8f3LkNfqZTwV+k80DKLfZhzc
Tx8pPZJ/fabWdTB3fAPBAr1owaH7tT7MiKZ5dXvFmGHs//uaaGMr2CthCCuPOOtAGRIMU97Sk4BE
5Z2twvXJKCvM+VztnLXtkKE0SDKexf+b1SHfCkOzK2sYQDTmYMfvNmgEVB83eeXIue/Vab7PAwCg
mqmvk4wm1zlTK3p9SdzFaC6tEVu0odNrBkRjXmtNcRjnJ61gPUEwf2pGz946/J7gTey2ViofKKm/
9BndNa0XK8uIB6bjAPl++5xvJxUqSiH6D1pwnuqivyu3zZ6tYT8PdJ/+lOfrAEem7rjI3aBNnhaf
2q6mG6HstLZdHFwxiCr49SpLwVSPxl4NhJNwmLZLYRo0EBctfpyHtTHUVGhlMgiFDRmYbXYDhZCX
81Lh+Ob+sNwkHQtaSO4N4MNPICb6P6OYHPRvfZA5qpTYy7J7zlhEfmfoyEERDyuZ/Xg5D01UH4LO
1vJ+RbOxmmkjdt+CHIGmxyS3me8hOvruourYkw5U0pr5dhWtBGA5J2pil5a8YOBuOUkD+xI0ApzN
dhu0vqsykCl/W1P7j6+QppNmGjfwpiex3xbJtTmHzfFt9PzXW/ylAAos4M61R7zbUx2XB+T+3lgc
6bVr/WKukftSD5+ZX7+3hd7DmD+g5D/M9aKFDKM55idvgcHnC2Blp+g8TLV8HfxslsOwJAWcnmu+
iVxy0XoNKIaBPMMoBGJWOffs+QrPN8Jheia1jC9yellc+ZEW3VYWAvQY3wxG8gkxd356GK+Z5ViC
uBjwqJp9FQGGNTAwMdwxmWKf4OVU7Lw6Ow0999wogokRp2lbR9MOBX6SY9sresZ/9KaCc9RZuCya
GYEul/mZd0Od+YWDNpVRGqyOwA23hPKM1L34g85XJpcIjW7/FgndHtDWs9XlYhj/PCz8pPCH2jtK
Wv2V3zSPPH3U928MocKsrI6DUZU8+ZQFfQvwabo0bLCrFyo21+w+L568VRMi6Egcv9Z/0CLKpcM8
L+5svwZD3k/mFB4H7UZJLn19TFrdlSWu/Se4hgyoa889UZrItcgKKyuNiu44T3aFD4p1SqHFats6
Qwr/KjhCRWKCuD8UZoVjIxCyi96YO2HgFJapNpAmgfNkbjZT9fVX6EnSl9ENpdW/8pI5Xq2OvrnW
icYijNJul4hqFou7YynBWJSWeE6yWKaSLFz7aOZj05ELvtD5k5q13JMnETgDjDOR/DsdSkJk/KhO
SmKq0/n24IEHaAid/41TAdHG1/Ya67Nz/2eocnCeVpWEb4ydQvBaG3cjcbRE4SRoPjVpKy76uOOO
uIpPLpCWvAPU652qxFSygA+83kUu8yux/ofnU52WW8NVQIrcmvKduat2ubUoLgxS9VbueDKCBDGO
FmlYEj3yaRhf1G1/7zgT7GcQ1oBYIkYKKiCBpzEp3X5ndmPCWY48fsn1O+RmY9SHMwxanjNkl4vm
dvpnkR18RXtjtqcr9oYtLQk6hu8CflQFUGQTUGi1o2axAR2EM0j+gxzOedcXW5xss3wAqYgmRIAc
VrIdn4gmQ7qtJ3h3tOCKOf3traSDXt4RdYQArdq3glXyOKzS6ugS/XI2zwWCRur7kk5g7nuevV4l
lRMOZRgDiwBdbvvq98FfoASqaa9kPsOp2ACp9M2lIv2vGKVheLyKIGzF76G0RmLo3FtOL7/bOIOC
MdXAwL0W6b03lCUwLtnJGNAyZZzY8xgE2obkOCxCzgltZ12QZF1yQFeyr7tjagNZGycgYgm4Lrut
LHKcNpu4cMZID5KIBc3fBBflev78gMlVf2OqZcqsLq3+/7umqmtxTvcCRIQsrRmNjLuOeb0uz9eD
KaiAjw6qwiQbfH2sFPsf8hGDCOVz2phKhV8bJehuCisHRZxQQviithp37jHWW/f/vVqNjQ0KWOTl
4mCIoUzVyl1nVG69ig1sgoJuiHSA12B55oVtHaz9+ZCdS1PrU7pyZQOGnU+19YMcWO5YXDHcNj66
38fzegCiYLi98RlkyycEO6mAlqtxzCGkhUnKjbVramL+p1Z6HRBvVzOBu7y2n9DGiXT+PS9vAABJ
GGVJiCVaXxZm15302rY0goWkJUMufZBmL/G2AT3oXWdUn00UbbBcf9YDWM1e19mVMeLFvCGvv4s4
sgYzFPQQemH/bh25jC4QzmbYcXReSfKZ2y9eh3NlE/2jhfRmT0hi3KllVEvscZGukBQQhW5iN6qD
VKqRMx6Zjz5/LEkPY92yFSXh1EiUJLIzkwCuKTeqIlIsMZRdQ0zuwE5Kfw3XrNBDcVWS+728zr9E
ZwpUcQNBlqFzdlgM1sHCfxIo/M0P99Ydu1hWwFq0qjQEBHVz2zvD4//r2oLRJfRcUR7MWVlUoD6u
0wiGU6C0Bx9xjEEIX4EKqmhinz8oNToDq19MRBj8XfkGnLgxqyYbMT23b+OXuqAhHZb6CWu/6jDt
Tzfh9OM0hLe0BSdxfplS1rHV9oR8lfDxiJjUw/yqNZ3rIJV2CKBtQjNc7p8ohx8SgGJPAdzyVeTU
6AysHulDvPdg3xc0Yl+aULakeVEBLthbUe+iNiFRGsqOKAiBlZMZ+zvRgD3C2RUgilWQ7idXXcRc
YEVkXOessjQ82WEBaNqivHct4EbMGIeMhdg0luaUHo3rCORCT8j2EBTCBtsb3SubSPOFA4xqoDCM
OC+Sbeo7tFUjHvYcjVYHhKlzD96kEMy+yTU9a4pSmPRlUDJhPHW8UREjP4KNIsG3gJJB9+6D5Gqx
B+DPwPOYqUOifglGzyuRYVp9frL4ezccNTP+LKFUNA9qN9L2/imO9ddW5okFI2TofI7LR581DNpr
jJwVHcytw1VAYqe+g7PfgUfDKqTERCERpZ37R3eolITjN0ciQlZcTyIv3ufzSEp3aaC+4u/XAh/d
ZOl946Ip9HkOuCchH6iwZRB8NXTuxb8Au6imApcMYa4E1r/uY//GCxGPbRU4QsxVdwI+V2aLIdyx
7x5vMBqqGnxjujvgr8H1/P/X6so7+eH7Ql8bn28ofisWD0sfQhEuhW3m+sqAywSGiDfP5BOZIkfT
coU6h9jNFjJ2Z6UMoTQOW8/ZGSeOLnMP95Ndy44oFIn9iXYYmHnEIX4vO8CknAVVTi22Z6pdKv/4
U+DRjY/14jOk5ryQ7fgbChlZjWCS9VletSdASi+tBbiykeuqYdKmSFM2na2+DsUr51qAfaomq+ce
smR+cQn241/q+K0nqAY3uPKhPYyhA0YvRybcW7NmW8lYpiM6FbgmtwNl9CCio7CF5ecUw4ofaa0w
+tUVBNHCk9xWjB8ZUoHCUYgCigyjy+5Yhn5pH7vJ2rPyXaubdtgQme8fHJ/BEnRhaZup5zeGKYtr
ehivf4Z+F4PHnbywPcDmWZBZssu4wxCXTScjTdR378ucMshOHHywvqE5thAWKCA1uDxNDc2uehtT
6JNBI5k8ach8Phq1vU54CO7G4y8FfK3UpwNtnCKYS4g0ZC4DO6O2aw0dsF32dc3e01dPClSlEOgU
x30Lbs7nNTEG0RSnhY+9nic3vhMfDQH2fJxr4UE3LhiczADaH+FZ8AXQbysUbA5nHutN7faQYPXD
41Jo6QFQX+o+T+e+TlJRSZMSrQ2LjL3PRuGahT6ii2xzJUr+HRHGiw9XOABvXJKXzesWCYR0CQMs
P9d9XKGXRfzkhCkhi5RGxKd4Q8CnCiNunAx3x8rdDjbh48Yw8zWGKNJyiu3802yqV529nvuD/wa3
VE6Y6W4X4A/MjVblMsq/EsIHLSyNo9l1FnbkElCahqcVoHbQf5pV4u/bCfmsIR99tqUu87d5IauH
/Ew1mnHO9K3jKlyAFr2XALocTBtW89PpwaTxEEzXAteT7FjmPazAWAcykS+su0YNr9t2oE9sV07W
aAHPpHIz5FxDg0RVlQ6798AEv1DRwYzlrSQjbrpHmWaRTGnfvS5xOngkFlnLpSNNI61bHaa/qSKE
Jsc5yOSs48T31TMvpIk2YT58h2XtTWhRsQ0M+T42HPPAwkf8gLyijiGLKWRJB9YDnZZW9JXLTfgC
3er1Fq0jrts0ppLQ3nYrTECQ7Vx6+llvuF9pDgpfp0+cC0XtKRZ0xdUusjS8GB4Kb9rAvRK3XaVv
ikDMs9QrjoTE7FVpd0nfplLmKvD4vwccP2fjX4ERCrpp6iNFSkz3hFfJeW3Yedcz59y3zYsClndK
+cUu9Ts739Kp2ucZJGZD9YdEDi03pjMS44hxRQw08XxJ6wHO/1qJDjLjrjp5xxIzTp4JX1dOMcgM
gVpush06RjeXahWXvzSni1wZBfuPNR2qB0dzJGRV0iLGbsEHYcLzTkec3cqitCoimO3CLxfAp3f2
Fs97RyOZyGKcMNnWe1RyVePc6/5jlgb1UU9a6gFVTB2X5rLZX+rsOYxHo/OfRUj7IuWNAGto29yp
xqw1IyV28EAwNETZ/D6KKpvwIezkOzJ03+5nht095uMvPOk5AGo6piXdjPG1X6HudZtAjwTgFkzt
Ml/qDsfwSFa7AKhAJO3QMKteD7V+UEs6US1vZY8H1qPEnSROtoqXQiEForUbpRvAesS5/umrhE11
EkyaXOcZv0pUwSm6gslOvvYORUcjq2X+TxBxhHtFsQ1FLmZ/b5tZaMtMvtPuK0miw0ToZgMnscr5
1AA3OqPvXDxfk+4REulCHvOSPxAftObxbeRERvWqakLMlXzbcx/ePZOI+5xEbcy2+JB7UK5zMk0b
eOI3cgylUoI4u9ymbgV5FNPjGQWa/21iqO+19t9/lfZAr+sbX9/Tqhuet0/6iU3xXMWyfZ4Fyhus
sAyNSPS9Ce3rL9dDkuUtGJ8HW7fVuiw2O7Fjyn50b79QffSF352a4AlchGDBJIaUa2K/IqF6Yna3
xvPj2MyI4kpoDyad9wI9dGDBR8oXdq2BPUlhVXowRo3Ouew1b6HXDWF5jvQiu5BIgl4ATZvlKeKQ
9rTkgoUguCuKuwcpE5cqoZdUWP4PhCnFyOOgFH0PJCq4nRZwLIUW5VpEViKi6sMzDJP8Th7OFvc0
Ix/tSsy96a0LXmCwWOBH0JEiDIQUUxpgZdor+bOM2kIc6gne7Gfiwp8LWlQ2MQl20HuDQ9Sdtksn
T2PvswDJJaHNlVGUsnMuJ9dBxwCo6EUsNdLf6nE9u7kDXXrzy6wYdq22KJylMUuhfOSlmp8ADbiL
sj1+LOE0NdRe30H6zbBpDrVMBcHnDHTQT8yzru8/g9vCPEd7GfrZBAc0aWkughwkeCBtDMyRjPfu
GH6V3YPRbnHD4fW85QwnH9FEQgMXl4dTx8xG1tdEmwW5WBuMd02H6Ty5h5e47B1kDSsCiLdEV+sy
RFUI2dhMDX3tY5184hSYO6TPuOQDRi8AHKTwevP6qObAg4suqLbfKzpNg7tKjYeRHWpGwglxF/Qa
DLgvEJXMd1oQS03IYanpw3bSP5WHLGsSGfN618e/6dkhx+Oq0euSawoeWPnznDmOwx9tEn/zmOlD
SHUmhcTfKu3HNK65Dzegal1ejzczGeCqlAr1nMhU2H4yTHBRUVR9/5q/ARrRV6jEPPlY6EBeJYUA
t2D3NwN52+b88SThSZMtjXdjkKxe2AhpGeCMPchtdWXxjDBCWz7O79lK85qJbMXl0bNFWNmx8+dL
y508B8nP7rbVyAmw78grqckYm3KCBFbDe+F1JLI2ida8Fm9/MlPvWo88k0rTf4/hEXKPIwEb3ulF
XKQ9gmOfEwH8KVpMKsmB8ruEd0EDgwh0hDaFBUwDexc828wKHgO26NVI/cKKif+1kp/7Pa3blW4w
RBGZ5uCZgDssqwHpdGPESUjMIYmFM6rvi4kS99uiWUdkmc2+D9Vu5laPtYxAlIoDs434cvecqw6s
u/3/+kW4VOfReHEJf1wy3lAjpXif2LuZCumwZ1y4mYrCYZVGrVwdO3sx+Gtg8GOypDLgyRQxUWuG
3/e/QXdvXNoPxrggUwrOo8BErDBZ/miHmU+xWcQP/+HeiUIf9iWZmagcuupHDXXt0orHYl3yrZHJ
Y4oaFiuX+z41RA1LbH6GL70FXI0PgVvajdGpG2/xwxYaBGIOV8SltM7+dyPXJkpte6Brt3bB6x1V
BShgmGdNrT2hLSuq7vHwSyD5oCDUoFViHXsHfMXIG4kKPyEmpIpMuN/kdAosL3m2NuWfU7e9GZY5
RRNRjF8K0AddO7KrmfZI9Tde7CM0eRFUTGMJkzR9aYd6+BB+i7cpwp1I51pm58YRlJfRv0U8Z9Gq
kkZrMEai165JW+ru069MZqZjyWo6LSIq50jFIMbir+JrbQc9DrliZk0syRUo3aYeLqUosjaLButz
KEsPc5sQoaJT7EMLe7waGq8MD7ShZQGdEmN5TQ4KlscZjpZtR4J3LoxfSie+RCRtRMvzMgp2q4VL
Zfujp17J2t03WYUUw2Dr1CcVf3yZx7/BHI//6wLbkCqingZHa0zpNwdWmOhpwrXs/AyM6CRVimTm
ATM688rsPxY0QAF5NIK6slnc2V6xKLB+4+5AwVIbdirPHJT+aydoM91sMnGC/3P+Ty4puoVvJ72o
Vdbm+NX8CGfT7BsKCrfG63ZL45caRhKBguACLF40yCNoyVKPoBlJqfAuf37d02UPXQobev6IbNyX
7ghqtrKbPF+J6ImfbYDg/qGuhOhVP1vXgPPQ91u7PkdP3BxbFeeoqWIbeuEO4VOxJoKiPTfpAzDn
Fya5Yd9hv7k0gVHZkff5Y6PT4gckjXaXE8LLQkpRLcvZ6/QpcASBWTra7XJFMGscYoByV0WAp0No
9Jwe7g1lhVni8OwU86pNQqw+GkkvTOriSszPQM2NkCbYNytGr2JCgrIYjwaNOisrzmpADuVrak0z
w45VuXfoHLAbS6XVU4uZzwgBkkWnFOt4YVKlebBauZe+0QA0RkPNv09bJBDAwIoEHwEoN15pmvjX
YMXyN5F08M3sbyNHamY1Ap9i/wR9nw2YkWjOb8ajfu88QDy425BNE9LispNqyDXryogCE80K82I2
ktuvZ5+q7puWxKrw5peao9G/s4KFQ/DX7t7pXxAzPGDrBCqXtGBP/KOa/VOClUGVj/Z8WqwgW2B/
FXS0FbzJh3eMCV2NWo2x3uy3NG/XcKJ1QOfhfEWIRcl+zlezt2Xc14nuPBa7CsanYKRsrdDfTjoJ
21HeMZiaMiMe+1BH5fGTRBy+GNIdjr+BcsvfqpuvWlhJ8tZORgCKPApcZosOUNY+98i2Iowq1EBF
Ijhk9X+Y+Sy4w3xaBUtALl5R5tWP+HvygbwnJdgWbAsd6asVV7w43KjTlVHz3HdDnoLZC5XM9RmM
4y+EgRFmdEpmU4jEQBEm4VOwEqqdTy/qRxuFuO0KlqbHtN1mclgsknX0rGIKZnjz2sHLiF8E/sRG
DaDb8CpT5orIrxzL8BG+PnWu9zi7wYRqKy8TwsNmCduO2iAVJBq7uP+pgPAAd8d5NPGpuF65t6yo
RcJMoGTgczglJ8GpKLKhzB/3P6TA7QVs1w1SgT1INC12WtB6Xtm/wK48DRywxzyAYZgdzW10VHzZ
Dj6EnsOe1/nja6vq0z9lWw7L9hynhAmsHkmhTXacgfDIR0g8KNkysLYvlkr2s/quBg0n92iVE6HS
dZfRs1W0OCDcyf6ZGCE2JJbOwGdGVFwpI7UZRKXrnsrTS4gwC/czdQcdkQuX6v4Z4lzr27aLXFg5
yeu3nu6TriicSmhL2Ihs2jcSw6WA3hhJ9PEKikOStN6a6SaBpsA1NhNdYenNzWm/Thms37SBkBdj
juJ7vFJ4e6+0I6y8NwjaDsQJHxk3d7QgMHX3nACHNVRZeT+HDkmlU8RdNwCjgs6SVqSM771PX93U
3FdTb2UApsuqUlTOBM1DZ2Xd1GS5PxMRJn9FGiLZoPPRAaO5L0OZl9LWKa71pmpnC1paQ5mqsHBs
AzZzBHToxihGFICUVSYlHup8+uQnIVmckdSXLXJNEi4LCkVgXFXdpaE34C+xquq8RqWtURca/Q+Q
fr3lC8PZxOuTzm6cO9HKD669Sr2yxt9A2AiNmCMNOrzRrsqwsr9u2wn4mKfL6lz4UnJGEl0vISkO
cTLYLFFGxMJaNUf8IiPCQ8kfRbLPbM9ZZx4M045NX4Iqb96qId6ra/t78ags5sjTtF/bfeVWvmk9
3oU4CWO3CjMUaC7uuniY6jIVK27fziQGh6/Xh8JNwEKPNu0i2dqDLcoko1lUrAtwzbckRanzfxn8
n8j3mzDd5sd50SK8jHlgbfa8I+dEmmx81N+aJUVT9QPV26Ssb5RQuxTbG+baNhyyGBKIBDYbXy//
4ZpDT9d/bGl4wZylLr+WNnh/TYyvjj44j7F1JtZs4NM4CT0A0hvtDuht9I2o35FYX3sy9t20hN+4
D5W3w75862TGInXt8hyT85VcSCUsy3daoDmhG5tVOEVxdsHgePqKJqv79BV79WX1/gQIgRqkKTSY
1lz5GA8Hj/mJjF8GgYFzWm/Va4EYnoGwJxuZn6k0TQVr27znGZo64L/aaR/naHC/GsINs8eIXGyR
e+FbiVN90nd9awnIq3pFuEpMXdUyrNf3phfbfCrColGCnLZvEpDctoL/1gOqxlP1gKdqxziQQCCI
LPOiMASPkz7/ksmiSbxIHKuq9hdfAhQmt2FCBQkHc9asnbMlxWm1jvIADME4dqoENZ+AO0ElbWmh
r65c1+d2fpUUsKsvmWhgkWjth3/yuQSj22A5N/GHQ8lnMEiMmyOo8YgPbv7DxhKjfKtKOsEIsaRJ
rLSnSrGtwTPPRwXwadV2tt5Sd1iZPFiI3sB7J/Mu8wod0Mfa1nLBYTRs2+SXbbe2nyd9ESZFKCfC
vFrg7qS2y8ZpFlToh/CuV5aqQzqAIjMhADOxv5gVaParKfuTmPca+ehyYu9oKwzbqb9cx2b7MarK
M7853GtfVZZvG1WYUjJipoY8ZhdNQCwooTi49Qe1dHU9D79gMifFIcuLjNznfl5QsgVpPhCpG3Bh
lMCfGSvW8Gz3MhN6RTrnjAebOD6GNOzSlPJwDbZvxvlfVVNmN0y/LCKo9uQlqeIoRuSEkTo1eT+P
NbeJJCnTy7JhYO55xeBk1bnFh51WZ8bws6yWx8/3WDIfk47VV8r7uBhjedI+1pAa8lHm77c83iE7
4wXC24BPuQnHlmDEi93B/tVRlI28CZu970EsIsegjbN0DpGMbkyzoTrIZXJpwVNT7yn+XoM533Hl
rEbsbjvwf90Nq0XWf/URqVUeTVZuolHxkYiucfr6vWnPdKsPFC1USEZ95XTaNJZNDpiZM7mNgq0f
VQqNISjks5XX2OmXMPFWvNi1Y1wl/0DzLvjdn6ToXLq8ZegYKA0maIGxIZsKiZ8arLU80IL4R83E
dT2Y+pZvXcq6AnY7nP+700rGEuvUT3FB5L3y/DUUPIIbxVEnR7ArRauwPZTXiGdR2yqp2kdcjVcy
t9TLEqX4Z103yfnpUCYD59vbFdovf9QMBYD5d0q8JUe1sEnW2dK1StvTKcZAon4E7kFtgiSGBrNO
JmO6vrbPoNOL3Jvy0owalx9ieAY2pUmdlAy+VX/b8LdNKV6Kb9rFOcE+CIBTJ3W1cZHP0K81jxLU
GLxxo2wS5I3rHSdBI9yYzn11ml4/OiLsObri1fODyA6O5KKr55Fvx5m2B6FHrAn3/qQXu0NJqplH
/wyytWnL6KXqgvLk3vst/h/uF/BtmVooGUorcIbAYKvNViQYR0WgIvStCjArVbASdwOTumLaRNQm
4tylO0Sic+nYG9LWkL1HZg4oSRm9IJQAONLh1aqkoCrj09mWNG19EaQ7eUkFSh1EGbDRroz7VVq5
LO9zOxUus4mZV3TVPdZVYHtsmTLlKlRmIoq71v6pEYwkGr6Dkaw9U8aNm0d6nQV4/0Pm8ymkJQOD
VqMX4YpP2Wwqf3D84IGt/ajqGTYzs6whbQaBrKO0bGsMQHHDNFuEG/3o+vt8zOdAaiBDJwtjBDyO
OvVeDDL1IEb8eW+n4PZ0Fzmbvk72nFs//bRnOl6ktcd7/TOwCLkf8RJoJEknCN0c+fO2f6JH+8I5
Ef5vbeokOH8Cgu4KWOXP+3L0sA7rQQc4n4LUnPbXrt9ngfnLsAOaTAbCnBOIF+wDzmzzKp7TIFvz
yFedZ8yFMLQ0hsaBck8EnVTJ+2rw0258V8jxdBipok1szkykH6DM/NQzvBwdWMJiJs50AN9V90aP
DTeqHhpYoSYZFSxvhgtoAWdmtZKHVXEfJyJO5unQnk0z9s8Zhursx5LExEl8lntj2fEUy0IRvvRe
HlaCEM06mlcic47hfs47LswXkvjDQojm0E94Al37s9J5te8/KnHlROodeOEOFRosGV4Fp9jL8Ic2
IPWqKax310XK4vh9GaCBMh6/r6WYsfGiU02CbSRn1BKfuXZPhGWt1PbURJ/UcQODbeAPXLHp3UY0
KOPtNRhz4TaAqeBoNkxDWmQ5CyNjtWiK5Hh6LLJLonWczKXJA3Lu3H43+CCXYOv/3X/uVnecSiq6
ODT8RFVeere0BsVY75U5+MSs8kyw5IA3WHcWuBUDQ+PKlqB7V91JRzwa7lEst6xenvVHmNc9jvJS
1VsYUAkoRvvxKW6G5Ogn32Ao//YBePFfYGK3VboaZMhvrwz0pJ4//h76jF1bP0FRvmr+4GU9ogwb
QLpchVnIxWV/yejqslgWr3t0SjmHRym+tyrYSl+49nMMaBAdDvKWROI3eejf7PmhkysC+jMY8xAc
WeaCJnamwPlNLBiogqoA8Piou81T5L105Nr6PXmr5u6lnnJlIt94ISGf8olL9fzqRt3LkR4zqTIW
xcCXN3Ulk4RNFYwQKPJ+8tWCpTGYwuENyCuekW5AC3Ut2VGjpvg4F+ehoFOZJS3/Oo8KPwwYMMJ+
iBf2XGv2yqvMOwlAKnBoDWLImImHRpwU3GTg3lZzw6kl70iS/ScfKk/sFhh44G+SxmHdLRtyOrCO
FFFohG9lgIxcWEMma+40KXugf4lbhuy5Mgt3ZSQsunqGLk7UKc7PsA4yvYapEr3WaM7o3saJwJBc
QfI06f+PpZZE2Qxt22M7Ex6cZ9XQTZUSq99I8kCfZSbhYLPInd3srhgqs92M1oYh+C4VYM0Z2Xrg
j/GhKYgeJ9SPpD1X6ApsB8GzoUxTSBvmWb+1jb10YY4CaBLu80LbRNbutmQ0/nsNubStCbkzddW0
JUgmmECknyhllJLNgX7AgpssCHwz2gE5Km4FCe7cBb666DeokirW0koBJ1J5uic7CE51mS8oc5i5
U5NJNUntkK8fFrYBMSWvdVLdHdPCarXN5jlmACW+9RJ7GnOSDZtrBIp+eSrCzip3BRcC1efYP4Ue
tUIqQyb+egXrHsVXxW6/YOBgPjiUVCnis362l7RzEV5iw0l+s7mu8f+IciA/528Xm4o0GQ6Bytsy
qbvEU2mNvm4o9jEVBWW+KM/uo6f3w+p3+rjceJZMkSMoFU7fw1HgWboTnlX8LZoho4AqqKMpmP3t
IZVjL+2Cftj/8Z8LEV3kJn2LqA2JU5Dlh2jnpocJaanSfgaU2C5DVXq0hWmK3Eoc0zWXg2mGxi/x
sTo2b5L2jf2aVg51Jvedkn13TXpDHBjgyWmVukrwveAyTQrA2QrDfmLqz09aFZas1A14fEDzJ/+f
zp/omzKISlTbC7ZR9c3qww5rRW26Fje7Pu8BciOKjdH3B5J4hEMUWECcMA5IZWV1Qd+L04VnS/nL
l3i5x32oEwmmb+icGmTk1k/fSZ+NO2tdUj24e8FJZpAuG1NUq+4ap2RvEQVhY32c+8h0yduFZpWP
YQlEu+Pu1qo2ikOlDaPIGCd+jxxxCe47qvatwe1JZiZSeQuFrK4+YmuQs8NETJQLH5gGNq/vGA4M
TZKfoNVG8Nv6qdcGEoep2V9bz2xwaISMuUicNl8GBEEC3qbK3HF/wjAiZ/nVHrSUCKlwldGuCDvp
MTp31AleRQvyXqDWLP4Cg38koVlnEUue7omT+/6gUGa0yr0a8zyuElxVF22zbEwS8T1MNI+Io0L1
V6s6XEoDwJmMi32NfrrgOp/UgSX55SBA0mU9xFLEszV9fc2GvD979i1PoIK/+fAiLtMZUVZQjTvU
nranZK1oKGBKBF0+A+/tCP/8heIeYs83cWOSIzWOebfWucpS6+0G87DnH03UymEczbNfquaFVMGF
9TJnMOpwstOR0nJO9C8AwZneGeKyJ75MjLMhqtIuRFjcRA7KtGuPN+TeOMIWDhvSpcphubCayRq4
DXcwE6MuopBSHdw/H+p226QNy/S6Nglb1RcDxKGYDc0/Df/B3sQxtDT7y/yw6OC1tq3Es4dJC/gR
ou1f4jMd8oknsmIm3D1Gs4dMo2D0p/DP1s/BhsNciC4h8Y3jTUDes+ufzTiHYLSQ75CbsznMzM1c
J6+h71UAl2aUUTt3SFc8WsFAi67u+03ijwFJ8AVz7t0qVNkmYWyV4uN1MLOAUZdRSddcWJMSwlWt
NofGodOZyMniR/VfufmlMf1gdaaTtUvlCk9EktsrDjEZdTto9CJovb4ZdqscWufMt2ZTHmoPEDIY
1MQcwa1zinkMdg6Ix+aad2kf6pMR1c3lsBTAQIKYTQuuELBBDyDlVjq3h2j2GVcjoqYSeFlIIwSA
iRPG8jHncGt2/sTVi8XfP9wnV9PygDVNmu0BhTC5+P4nwuK5qAjESwtnAAqCAjEQkZr370r6EW2F
iaABl169gZNhVfTUUmeK89FiEIrwToBo3mZ0X6TcPIa7oY8RuFBwAyQDiI3HUIeG5Dr4JzBlAmlF
PWQfbrBYYbsyteKBUYjqrJsDedMxIOBpih8fymB00Kh8sbm63pT1VTowUvxs6spI27D072zgsyHm
AtMrwu52zLhOsLAOBmai+noXyUyl3nYX/dzxCxIIRt86dBdpOkthpIkwU4CTuPethNgW2jpZ9R1O
KgAPH5iUn6kR+VHNbZTyhPuN3ygugzlMQLJaVFnHB/AOlMk4NTq5UO6JOzv9eoljBs5w2A2O8JVx
BxhbcZBvfq04nvoFzhw1ua/mAvyzGijKSixIPysoyugndWcYZFlq1NpgnUjl39e93B27K1zPvmTt
L9rPdQiIuCWiObaz6w4CLq01vrScV4TiMUXFrlwPo77l1CNbpaQnbdpHJsD5OAsKxGxtVm8kV9Ac
typr5+nmDts7b/rH5D9qUoxDGbsfiFZKBBYoneS7qI+7XalspVjqAA98CkyBAFHV+sm407nxthgi
+tICIyuT89zgL/9bmfpgvepjjqtYG/zT5dG2R5gjOgYVSawsvbSdG7fxF5Kw4dkMSt6g5rKihgDg
XAoFlM2JTH+xFXyUQathsmhh9CiNKVpRWE94OrtOX1FAci3gGBnMlylDS+ILr+zOJwFG8Yav9hkw
6Pp7OG5SQ6dy3kbnuxnrzM2Ni8d9fyDbbRRRk3nff4YEPXKMnZWm/4LYL+FnpB109N5twwtt0yVt
gIMf0gdH0LSliDLfCY0PrzMu2CsEzNmKJF2/16LEV6fgeUQkrl+9skAi0o3ef0J3RAXolIjyVxG2
GdsbYRzxmVssYmxO27NDUnLcg3NfcNjmQZ5Kuzoo8kOZy+siSUsifE9rr0UOJENFmbThZEeOKUNN
811spYEKP75e65WITuhaYifnafBGxjiwcCxJzmnozvEbfiAZlWnioPEKqpz6RtplHgfzNPcg545J
kWB6nz4mbfs6IQJRDyYM4g5nPr8i8iAHmiWXmqC5MAHXv+I8xiRoQ34wn2f2gn/ydKnr8ZuTc01/
ICP8tQXgSQKh+IcxXXv11Sq2ImxbssBWi5jpp/n9GQHmDoy1lAPDPys+pYqveXdfedd1FSQ8zfZi
8EP7Zg0Nct/teH3mwaPOpESs32M7sRaJsAmYSTTTyTgxJjvjVqiiE+CY+QtHZ4c7KkSKZ1Mv6jQ4
VVDWw45/IYaohuORPUpKuzP/oWu0Xy3f1rwGcbJYTwp6LyHrK9mfLdDi+LZvSipa3uZ1BH0UCN1m
XNYlYsOg0jY3bUxFdIyJi9nDyUATC0LrVWp1vw6+IEdIlvV0YDwnbLDn5xq5Pn7otxZJJFw2Df2b
426RXlxLkzLGxUCAOWb5QJR6JFgAQP/HybSr/NQ/TasnCXOmSv8h50bBWAflqFX3xBLSIaKg6QtC
mxACxRl4TeCSp6hiRSD4K7q43zpoMgRCSkWtHwZXooFxUo2E82WovNBdjJE/bxSA5CYlYEZLps4H
oPsjIG8y+m3NkYvyo2ztkEm7lbegxB8nnKfsPjYh/yNKkWU2V20dDus6PPXbEsRvS0SDOoeYaeoE
9GhqynJux82LPNcbApH1bJbnTJHBdWxA5i2mFK81G87xjO/G6JxMptGjLygqOiUcLPLkoIi+s+dz
TSfGsnsSgQ5hpT/GxoKoSHM0cjKhs7i94XHuQv1gsQtNs/fhpFZEFw1HH7bYUjZw7QbugCoL60kv
GF6VMD1zEtT3prnoZg7gOIYrH9aG8GHt856q7Pop0v/XEt8GEnmkmhOUYv0FTsB+tJ2jjt7vREl5
YwGqmK0CZJUIPuSAloxcKakiJXBA5hA0Z6itKNTEjfh6FXeDrNSO2qH61o9Q8mNEtUAPtp1NQp5m
A3XRb3PveNxet+ANf/hnLj40jch+rOAWY3r9AXu9WhF14+z2vkFTJFjwkmA23trKydJhONHBf+Gj
FyXrM76JVZoYIo9liaDsLsF2XaMw0F5PpS4HEblOYryZd2q8onvDsiMKRdHGH7Yv6mmvisUaMGBl
p3w8Xn7kXnrm0T55gKRgZ/HBOEJ+ZQKEniRbcEsRAkBc1yCUX7CBF4vt4aSTIbx5xuYLbEKIcvKZ
TUWK3qwe9fSrcttRGpOCVsNY6jXX4XYM4sS6ufDlt4IlEPLXAVkF7IgHL8sIdEPKIrmNWBGpp5I+
0soUXo3rkvbFak6g9DAoKDbw3hDG+SQ2gNh+MoYnieFI3DbeSHBhcqXOdcYERS46EOQ5PEheLd7W
mRoe3z/wpEEltWOh5CB8+FQesuAK15ixHWN4z2ydGjYCEC/XLlFSCaEwiL868ZaGyuLaC4nQjsHh
kq4zptGnruCurkA82mm5+2dHFMIlnou3hzgnYzwIWY64vAipygCpybLqUZxK6GNGkyU3h/ZsD2NH
FtfG1e18oCpi005BdE4MZ5w9QabgJyQMnr2msvawVcpqTmSFNrqH8XUV6Po6t9+bicg2sThfTRjD
MtXWt43Jgx1YQFs78hmSU5NXVjke9AcK006HUI6feGw+j3FnziqNsuMwWMTbYdAw6g4AGvKVcsem
u+Dnb1RJ36S6EyhvAaEFNm90fTMXAbqoNYM6+gDDBc4bsNNXXq72mNudh4k9ck7VZLWxMel7+W0b
kZri3j13C1Vx7kqw+Y3AVw6CWfzyk89QURTBA7mj5QhYA3w+seb2iXJPrOanH7lu+Kw/esNiQAF2
tSqAPK5juNQyd645+EGAfccvzGTNDLJ+QXM00PyK2VJ8juDpzL0xBPDSLE05WiFhcXdobbTkfnEC
HX0Dq67vD2BLPam18sBtk+AquqDJw4zsKxUwJipmKULtxi7f6Yat1SYKpBhA/lyreaoHKTZtc7kB
lAoNlNoyXQklcJCtGQGv6UqQzUB66yAT+FZBLFLEn4pEYsycDmSuOgB1p9JnehDpWCTvaZBIV/Fs
HN1coNPRC7Pk+JL7hdYyKfp3w7wg3LxXusAoarZ2yNDU889RnyJRJNVEbIzO5mzB0OiLWqVIs46k
xWy8TVULTtpw56bdHgeUcSlk4eqSwxmjrouCUVTqVRMiKqqkbjmtLAT23CsJNoMpnv18fq4M79E9
wQY5OKamQcOoPMaOf8J6nOOFLStFB5wGs9S/G36dKNChmRtYaLOiNAP5ta6/6HAiVJJVzy3DW/nr
jJBG137Xs3EkoRRHxfLHJgF3qX4SFyqvarBtmvjCdGHHm1jDY1A7MnZJkpfJTFTW77KYEC7ffQHY
RndFJiOz1vZyO6l4HmGzVNlbG9PL17o7nL9YFr3biteliEdFgetEuaaQWBxSydtL91y3GJPEaucX
nP3nxJQb6Oz0e/URwWGI0DAa8hg0ztSoDQpkNmQudm1eJ3XPbFshS+kzJ8Ri1wEx9wveu/+ZkNQL
OlspmulAa5AQvLsKlSDy9UwM+HJkXV2rqfxkay8EtNODqdwO0cJaQg8FlJktx95qnmWaJeOfbU5y
/T49Y+1M7+0KZd23ajgasb0+re001RiUjSl1b5KouUgO4OCUmMAl5NHc+PT0jJREmEzWvxW9/ns7
XCwedAGZ5T0jx+viAZkx3+IbHdGBppr4KoeN4cGzjS6Y6sB9dYUHaKwWA1+bNpK/ptAzBSwdLtO2
XAkitzHngbJXwFjsX0p7HQElFjy+2HUTf0KB+x6wUHRQoI/tSEU0ZzCFQ78YnIFNc7US4MF5BHuO
ZnZo0NQ5QQ+LL0am8j/KPSwrvHV9wvCAfSVsGyWAVu+FdTbnlAQZxzFpFHTlaoRXqE2kn38VNvAm
Yl2axLm+lfYZi/+LtN/Ug4DOn2EWosy/lSg769r7yhjMBe31ah3rPHYPN/F5KY4rzcKjsN60GiaN
GKB3hZ5rkn0QolKAVQ8dVnMU8M+Mj34loyK7J55wYlY83HHIH+Yj/4FMRhr0+t52qx5NIIG7eelf
VWqzbEFVwLiY4d3NE0ixHZfAoeHV7q/WxoyLf/wKPq+sXlVWXTRCSmbjmtKwRIHx+ef8J787g+5f
6r1eABagNi4cs1Cx1Sc7JuRXyfzMaw+y2q5arroxI0nnWw+3LuqMbuaBbOikthsNsAbwmek9WU3m
xWpc/P4SBQWp0NGAUL+ggq36uOOY9XfUUyfiMNMs4zDTTHvm5B5ERxx07u+gluXt42kKQAVwg8Qn
nue1Vk/zhI9+sDIuxtEPQf7aFSss4hFB74T2o/Y+mLsNUE5WSxSwFpiI9UljY3E3Vb4Wdhm0cmZh
u6xaU7K1bnvNDx86UwSrH9c8XqpoWVoWuejWx0LWkRehQ3q41016dso9okNBic3WLN0MHtFvC399
dmTydr3U2JjnVwUc1xAI5lSu0x2hao/MWPufB/RHRjbi+3lPrRzNcuRUK0t7zeTRJOrNNehOlBbF
HhJ6J93PLWcLEvcx4ZgdmxxZRqSQKpd/HYlWYmOxOLCbMeDF+vpYbiuvHENtc6rYzZA/hRwhln0j
WdZHNmFaKieYCXOUsFsN/tu30rv26T83oJ2PiXR95OPmlzeVjuOc75H0OQGle3hv1jj3SxZfNbAX
mAbOLg5a9jiF27+EZLTiPoKs5n0biNC4v2TtunC1QIvf+qxaRZnAqNHXKdWk7UPxTmgPpsvNkJmt
1Lytfd8iiiWN2XSRy9Pd2ohqBDOm/1b/mXVQdbfrDDmxLSzlgAFqAy8lxcDkOMPomYsxhru90ZGn
D0TmHKZWQT705y8f57lQufIv/1XKHfLFm3pNXXY5jYrJMwJJg9iAAHiaiP7IkOc3sdkPTfyKlr3X
zRei37HCQ2+MouZzAlaVUoJRvFC4u/0tSxFo7XlINCG0/vd9X1UXYc/CCDhrtAqntwAnx4fD5goB
TDI0uPLjcF05DbQdI3FXg4mBUTwLtxI8BVTW7jZokho5DGJ3qqq69m4Zxm1rjXaMnrMzIucDzPT4
OTb468xFRIjJSBboIeTTWQycLzcWlFAqFjdaCzVSPvl2csvSo3aG3OkUwGfwevAw9iO4RrtmkGRY
sUFnQvxcv34yHks3ZULITFGBs+oa5yxMMBw1v9/iQyODCsDsDy8TReRggcp2WfbjjdjnDvfPHX16
5dmFV1FaKj1E7ndN5mmTgaF9OD+FVVCEp6ZfN9YqAd4MrXHl+Cbo0eGwNspG57H4f6w6Z8ukSf7x
kIsMEr+ZV4kaxik/hrRJ2D+wywAcH8LY31O5HSofW4rjzY0Tpsze4B9E9d/B5cemH9tXe9x9gTWW
38rgA+unVERe2fcBdpgGSelrjWAuDcM8RBWI71Q2kAFLyOP8QGBEb42JX14/jNla5gtYdb5wyQuL
rndbJVS+MMWdKDrBARO2sEVXPqBiqXrf3Ekj2jpucRr2FgwEx+R+k+PwmOg6Def/ISqbujjnbf4s
JLQXBFSwjqdihoyX1xdyfponN/YPNVE1hUys3tdrHHDWr5dH8hqQVa9DV6wwu5XLg/ZOrJPL1O/y
8Yg2a9nt6yujVDRCzvuT0fKmEGLjueGSRVEcLsGaFrA5MtkpwCUcGQ2LZg/fjrTedPHktl4VrEDW
unhaw+T+iLehVmzaAgK9HE2KStk91fO3yczdbVsoednlsQKLSplmi/Z1K4sBL+cK1r6ZDMm3ivHc
tB9ij0Ah8pyFPk0HEBSHJSgdhRN4/2/YuCQO2VDGWnO0cv01jJVIKV1+j+h+ZIhw+KNtGqTUJ4J6
OmAx127ddG4N1w+IJvsQ5PDscNd+jUlivEBhkQ0EKVo6W+xq1zcdGl0lXnS1Ss52XSp/EBx1z+Mk
WLroELj1B2maAE8DwdGZ2/PC80SYSqa08BrImJSvfkI+D5eyPIAGXH3HC2fzQePladcRUPmV1Ttn
ox8CYGFkCtHVHiCaCCl40wziNgjH9pMiZ/G8TJWrtclhIIOcaes4qlakNLjm/PwcTzSPww5TWqhR
Rn0VfnA3cJXCh5hOgl3OQVh20J13pDiM/LJJmsdV071WgSJm5Vr6aLF8V/ptWWss337sTcSgoD0u
y57XfPw4H85ifd/dBmMBOpwQQnwG4ikkXAm3Cp5vG0Oe1zMqY0Lokoi7RySeMJpT202K9LkcvwDf
Wx0N8oUNFsJV+lwD/yLTpGQ/l83WV2ox4NijaZKUOrYcSAUc1vmkxzCoxmVq2MTqZ3reKzQBXQgB
WT1WIbVnBHy3m4a8V0lIPTPTUaaS/wEweIrclzqAXa956JWsuUJ7LaOi9Mg/6NHVH3DVFmmlUFB+
tmJKybrPhI0QuIYPapG6XkFyl3tFtMeIn6dwVA2UjgliyLYfXokDmcADE2BjDVfKlB/Q14e/qhJB
UQr0mYHURGr9dz7oS35X0HRxY5DBpkdEz6x3LTaL8q0yDj05F7jwREOO2riYJwl9sUQUI9sTNao2
I73R9u6t3V5/2QI87RsIJqNltVUV9B+nq0RggiyA0mqMS1yTpdQQs30o5GXH50a/de1eUBkgUEEx
z1v9xzxZdGbyZnr9lCO+ATdKcSS5eropl0HJxEdygVEaU3RZTOaRaeoK8T5ykwL+QzxFdCfwFDYk
XGREOpG/yda2sX4fqha+a9ojtL0oIZCzJSRD4EIi+y5Mv7KKiYYkAfx2UPUxGzZYVzW+YC7Hnv/c
cTfoaHqApktHD+6dkyts7AWVqxB8SQANCNg1ZeggkRl797yxCxf5dAwmqLUG7uGlkG6ETyyPqWMs
YxI1GVJzDvhonkdG/hDJGg+TLr1ZcylQmRZq9mkIPdRN0DRLRTwgKQ0JbZ9ek9Gc952PLFCrJ/nh
b+exizLlhBsu8RQJen+YlOB8xM87srWhVqyMjmIAoLuJOe0MJ4siNItZ43h0zUSswgeL/wTpQAAf
z2TQCJ9VntPUSTgIROZH1hxdF5e82jXyn+h++AvuiXJ+W9QCvmYkYZIVfaZlLcx4L9Th4hwjT3+D
nEgUZLNoXJkLVk+xKgFR+Whho1Ms0vDQi/aW47hJxPOr1usbdfd7VRHE/1OEMjhM3FK76NoninM8
8qx+Yji7GZWMlCOQVhBYzWggcuejppywqdPaS8UBx+26XOzjIXnTCllK4ZMmNL5md9FBY33mS5YO
wU7O9e3xZMVfOdshS45c4kT0Gffih0J+zJl+QMJukUZLKeaX2C9Yxln8YcR1q0Ptq4vUV3QorHl3
R7QzY/RHRkbVxVbhraUw7EPkYOADQ6LzgYJVnuZgyH5YEDVqSlKlHTqq1NXqaGFNGs+DAgQd2IOY
WHzUytpZkg2PL+tg4JD7mS/IQpGVTCkWAKZO5LmIL36M11hLlu6V5yq/9OQQ7mzBA70pdWp2JbUp
r5qf57boZoG5OckpvPYh8LD/hp8qebRcfL2ZFCi0qur61P8RjupzuNCpDnwzpGXd+Qm5mO8EZsZz
LNvlghDIvOwsBKJ4f0M2kRNQCp+VMNNnOvEitq2h0W4rIJeKiaXSAqP5gIvMTx/MDy23fq7V+Ju/
zLWeD0/9/Esz9POE9Ae/+U8yO35InDK7wpnM8VjfLQ/L8muJ7Wf4a8CA5ZjRtbYbrOcjU0JSRs+5
Tkrg9SdNjFikUGpBoRq+HytzXOPqbcEKxHGXFefps6VTzAhw/MzaPst2EyiFYgAJXzjSPSPBsB5m
VzB1d6gpqafhEV1XDQxWpde2W3xFLebD1rmE3VWIHjwI7VTapOqOtJyEL16p4yxDSLs+zOzEoTQE
zIBkDV2UrN5FSYKwaukJBXu/XMlk4hxCrPuYq/YyMLQElK9os200HvRARMFa8Jv+ylZShsEuw/Ox
B+k1BwjWfZ5WHu5CKDPw1ExYg8VkXGb0/7B/P9agezX9k/jyAhoBoVbvvUxNF2HXmb5iECjcUlyd
CmLbRe8qyr5ynZY9d7TuZN/I4BUVUPtP8C8CqPCM7wHo0gyvtvMMmgCsTr6ZuUOIMd+y8zwtCsEc
J/D50lw83WdN6lEScacPjd/Sq8sTFYTVr/zTZIq7jjMcqfEJTY+71npRTOJ1YzC6660TawhF/Sz/
xJhIffoLvs4Tt6dktgahxfhYdk9iPko+DAT4H52WPADbxsFzRKFKgcQqp/zO6RdNqQGZOg7cw9ZH
hs1LMAQDPHY9NZJG7SA0biREOhcRddMiU31t5Y6zzyujISXPxKClX34MYsj+PeeqZ45KJwfz1rV5
vo/NZ5rehVEP0s+1tK3wbrOt5ui2g7qRJ9LWRTxIWt2uUSPC40zS+LjMueFH6DB8DUAgCTwkyPuT
EKUkkjcGINjU08mV5U8FgFseeTM2rfPtoS9NU73vZ9LpqPrx5obvbgVbxGresbC1dks4mPLRBLk2
JO6h1YTzX8qMHvNywtlX+lLqwJ6+Jb/qWWvrYS2NAVgF+TQgF4tqDpSadfBJDs0gnp2EXnZfpHmW
0giHmbZHVvWll+/STb1VOC9ics8a0qu90kKfvG6wEH42fIj9DywYJk+g8/EK1jXgiO05q1PAHAN5
2tBYxxY9YmNOSr+jnLXlZj22EquLFfazuig3x/WaoDFBwmr7DLEmErj3vOgoBXbM38zg0L4Q8Z2y
Nl1V/SSVXIgMQY96BHiutEDiHwnATNH9V8vM0y2yorlv3XQrJzMT4uviN1PMsQRiZ2BBUIAMBzQ/
J5Oestg1awZVMP7tFHSesAqTdy8LlUwuuTAX5jkB64KD4Y7QoKdtoApf2orgESpKHrDs1uMYGQne
Fk/q5yLY+j1wk0rh5s9VKZDJ1Yvf0vVdqNsFOQlLjVd5HQuspvwtT5I4dkAJXuiGssnI+PIrlaVX
ntrURccnIn51vBPCEdmlp1TbqtIXZDtHSLwtRm/jHZLEDsOFVkL3XulclhySoPKHsWT1yrIOxJ8B
ZfBE4dYqYzglo6lIrkzEyEGUYjV+N2DbnJCfIhW2mxLZoilUEftlSThknssPqwT/0t/cHLhcxT0B
rhP2d+T5ZRnC60D4rKv4prUacFGYDy0J/ebPzFDEU1WCl9Wm79fzlKY2ymNnas2ubxPHHxFbvuo1
Rba04SRy5grn15At3cOW4GoMgKpUOpceBkx7lzVwj5CiiAJWjlf8ke/wKrVhv8AuTN9smpB7RrVx
N7Iowku6ZHs3uif9f7yWSft8IBIsfYiWm8geAVGcE8DI6cyyTO7VftSPR5/J71hxxsL6+2EyTV9S
5Nsf47G8tqiICsCxqPf4HwFo3ZkRHtN35+ow1UgQdo7yyVr5e3RZkkgGnfeRnKv/XxXb4G6nlweY
oTfKNvKibOKnhSn78mKvaolFN1NyypRyv2MBSDfU2LayUC6PkAoMyUQVqyTYj0+AgGXMxfkBwNno
SPDB49J4fGDBvj/gikQz2dS5Etjuy6WQ34zDlJD8Tg36h1lc60MyvtLXYy8ZwtgA4AWYEycLKWM1
AkFeLWmuDBESD3MtPFxpev5MBD2tPmxB1cEfq5CcoPVIW8KDuPPiV1Hz/DzKx3CzsLMtw9+eHaX+
cRhw5Vl3tNVkWkqCjDdR+ch/+xWBosCR2y9/p/Ms8fSsFimvko9IGElfr7jg3Q8GbwcmxhSXPfXX
OntMyXQOwm9DI7dNUgdDy9jXmAzP/KlhtdSelyZIjDXHJt9KyJUMauK4h/Jrlq99eIVbn2sVQ/is
6E55fDt6ONzUJaPtpMOnYkj9oIyVkGxghXalsmMn2anjdeXK+BDIVxs27u+dX68JXG7snCd6Q5GO
sxVXb5ij8kJMWis5dwKNyxKzWl9bvn43h77d+PG8uVEtsR+Ofkhg7eQiWnWiy0uD9nTTg65UL1F2
1Lm6/+5I0g1hfIk8EVFVuMOckhZMWU31T7I04m883C8PRdwHnIOjpVpHD3fTpb7Ks5Q6szRHCEnx
gx/cxplJE2mJG7deZhrAQQiARU4XCfelaJizFlKTdd42Xwux3ZjFO76N6jnyGZjmiOnWyOAEMzLb
1CHVaY+iU5HFN8thrKwQ+zibv/q6sNuJAciRG0SfAAg2zBQhFn0H/i7fI89Qi6MoK4qPQkzF4/fA
O/2UR/98UnSe/mIA+kp4z3QJEeDrdihEtRmrl7bzkUEbrac0Z9/5BSecBPilyFSAjNAabuOpH3VN
U8DOZov4EUJm0UcMLe1+44ncenjo1RafCDI5Io1qq+0O1k99nO6U1GN4mWvOxGljlP8PGnYV7W83
6KhYcCzA3dAwCfUCWuabRE/OLpKhEF3qjwSnruI95FwZH8ZXUBWtUUC4pbrzOTu32iIL9V3dz0YE
cPP9WMh8WwnCJz1prUyeHVuwRMvZUUeY388v3i9G/00NCp206d7+rVaGweJS6B1QVgiyfffBoc5J
aXtbFsK0eIzwMSz2wjEE6NpkztZCGeUlIheoXHREMx1jO+23JcsN2c73I398xWIyG3uhstNF9lEV
FrQ4iGUJYpivJzqHbxag5A37iKiaXmkZ61+/6FHNUcEnYkH7BbQEl1FojE7yxA++8crj3domdQjS
bxsuPTnPzXxfV79JtCzyIVYx6liq/OV+y2bgZBVk9AXwDRZF/sCTroyH+KVnWWR0AFuHHGyOCazM
cYEAowrK5kt6ggZ2ze+Lu54whV3O94VWg2OknXZqWVWbp5kep3hqTdhqCddfJL3FgAjCUKigsuRC
Wh2d8vnXZ3f6oMe5kBxotO0czLUxZyrcY/9HuyVWO96KqQH7kvzwIkhGQhSqTKh2f5VGHh96SMcG
IG62HcAJnS1bkFgPqSi1yMMaBh4Wolz5r8ffBwVZF/Ouf16NhZU0+ZGNiK0PnB5q8rybL+0x3AtX
dfQRiQ+I3vXjsqaa04iCjgiWzxrI26WLn13520SZjJ0HloEW728zfBnaBBf6MpFWECSe35PSZ/0N
TRhxIvovJR40J2An1gsDgTJcwm8kcKjq4nri3o04BauRzOKD2rKve2Re75C5BHEMR0Uhq2yUJs3A
mT76PHZN3R+/YB8Yr9ff2pZg6p00bnzsqmVnO2sNmp98pQuQvp0HvZlmR2PQL/HBNmqz2fUcGlFO
8+O1qcU3OVyEE5cDYZGdPlA5Fk2bPiE9PZ6oAIwgBls76eZSbKEItJbqPrqxcixCSSWSN5Qpy5Zb
Xo0fMiPXDVxzV2NBhjGduIpy1dldtFzUIlsZ/HmOtqqjvKYt5l51K3fANen34D5xXBCOYYdECkzh
XxsMj+hcgROoOfeb1mZeiJUHJnD+hKdpvCmGOKQhZgdTfo9np0vpo1nSsOnguyJ7nxn2TPnt7W9b
Hx8hiLZ5IGe7IU/fZktZ+0IUbZ6UIWxge040hgZ/A3tSGkBifFuMk9jvU54RxffoaF0Go62FSjem
HzeGAtHrXelg6aRicR6+/slQQgtm/FyrRlqe87maBR85wZQUBVB1EQnMn1yKwi7eiT69d8LV6PtJ
eFqytCZKQWoHfOjH5xENRORMEJjtqWoT0rZTgW8/TZZkgM1f8bENQfGqoI97vANRGMqe3cCua+Mi
Frkx8Ba7qrVthbxOLlPVZdTdY2JnfthoqKBAJAmhcpQXKS9CFMGD+FTE8TBzMcF5V3CAglUq7fRM
a4WbqpOjeBHZn07rFaFQr3eaE7KoMieFslHyPl2XeNEbIbYlLmFoXoYjSP/KRMsYmSmz8oOOJCtr
Mwj2JPGZIh5qqc0dcHk4RqiiLsRweKgPK6vbIfMyMM+esNH2SaI4Hr7SD7bPoT7FSt4JG8fRZFhg
nWa8SmTwLHa8akyLkeHjwWbgLBmvElRSnlKMvP0/2NYm1g1OinWXLK+TbtR0XiDg5Kpnqo1dN6ys
cfFgPg8Tb5kNpvSiL4cXO0GULMKl1DQaA3poSPB2kAKyNErtgifBpplzoQrPxWv4whpoogqNH2XX
j++gIU1Fx+XU/2YtPXm0VJ/E+euCBlt7I7EgQBgKLXs7X7a69Q8+M5JKZAj6s0Fx4J0r/o9RFfW9
v0RNZqXoSFjlujAw6vmbGn70cjDCW2I4AspTZcNyVPAobwddJ+lywhH7qwqeBq1rVGB+WD6AEQm/
m7UUeLZuC8lpKouMPQ4HrtmJ7sWjzAU7pnPbwd1Q+IDqnMCvuhpSfohXl44DDnKyOd2ACsdRt0Ws
t2ua8h77k6lU43YpxnR59DBgvWtGniHJ7Wvu/5DBpkroNIUhNCITfsHszgBPxdv6v/z/CzPcmHSP
zgri5aSC5aBPIhMe0dazXJzpsRANBCTfnnedEw6eQakaT2qKgHPIjO4hiEc8aa2qCj8oCqsxefDK
1UxYSyrXLjxV7SJQRUDpeQRGczNHS/WLrRIFIpc6bIse1w6c/plLB+AU0GqmXoubiXkSfaCu6EjE
C9fA1RZ5v2yi4YPtY+MJ9CZ2VAPICZgMPS0uHD2PUbSDWQm9xqnH9SZt2DPVXPFQ1ThYeCK7tmgI
tva2FBZ4y23NRdszdrobcD/mE3fCkhcSPqhYpv4K30Oo3LJ7+E7ih7iXgJpcdhLeNIM+nEvdk0oe
OJjYSZWGa+zYAPOcR5sPilakBuj/uWiYa9l90yPwUICS1f4khKkCZDScn7aXFW1rCnhKKJU82axN
nAdJNYrrMVbCtr9WsyVEbaq7w90/TZUHganGuqCLJ8qBN1UoYSnLbtYY3XHxpNwXpCWyfaHs/YDJ
By6Zir/1yEKahIPdicHEz7LS3goYM+qv13hSjb9L9zLBS4IAZR1MC1v1uYKjO/vldcjzrkzI6o6q
t9lwxHq74u2ncQaspg91fnRtW7Vx15UgoDesQ88YylMFw68XayYuQ7K47gopVoYDIG3PbdgE4eLm
uaICR0SNlQAULlJM02fYc4DErHm7mVTR4bDXxuRIwm42sYlg7EYQf4m8kKCMrPelqBr4igeoKTu9
mNLQw+RsIAugbQ+mzktMmP1rWZ8Fxv11URW2VmETtWGO4oS20c1gPKN+5NDWhoRGbdj1yPhn7Qa6
T/plvUV9Wl88DqNlH1nLr5jsXr1p9sTjJ9GOVLrHUhoOAEQ9ezDHxVP5rjFu9o8lQBFrKULQO9j5
KGhdAhCjBGzI2Bz/YsnOudtri+kiyacKsrRfj7YqIs84g8SD7Py42cKqmQahI4zSLqA50/Aqzrvb
iZ6zgzh6t2mWbzwzdFQqlWKUGjtxdAFC9/EpLB6632WZ+rlx8HGZfGa15azLa7YlAj4k2qgCASHU
S2AH1khGdnTi3UTJ0XmTix23h3lTGhlwPLxRjh7H6rqEaesj3/m5zRE2sBE22NylzzHk017GcaTI
D3vn0e9PGtyCeQFlD1PJCPVppPxZN3o93K3O+79u7XqbBteWQROsEAQVKVcDLwcSic6KQ3Szv9AF
RLTfClbVKGUYsB4eYGBk0zA5QbfXBaYxWUAi6yCiUJwD7v/S1MqCc3GwWaZF9wNg+LbBfFAFHTca
VCpXUVuz/8DzpOSjnQbGADKj2Z6mV81It9HARMixX/Ih9/I0VBslRu9ffKnhNORBEUCTIlc2aZdY
T+CIQoe4e83KcDnLb8StR+UPf24qKWRibpGzimqCvFK2I9EK1nCN6bKlvsF5cwK2c8HiosSPgz16
ws0OX4Mbh2NQsfjT3hYZU2NQ8MQluCJ0vMZtZlS9+58kaPCKJFvTbw9K4EXUyxI1Hw+qqYyjJ1SR
Ex5Yf1ykZM/na9gouyoCG5Um2ucdV1YOHa/BH4wT8h42smzM0y2cmEkx9NwWIH1mXGlAatxxaYDN
l3jKoEc7SWYpqQC/12CsKViTyHr18OVPxqPUO7zatcjFoYVWykPR3VglqD69jpWYVstVJbcj+Vsl
vj8rT5jj7pNVxzbu3iD376h++hRq4MULdqGuawf/cp3/ThF7Yrta50UnaigPDKlnLEcXQdG0a4t8
RrwgBs54cQEyC5fWH4wwbA5Fwo19ljAFJXhQT1nV7uHhQmkuUceTmq8I6r/NYgOICHhcNZhTi8xz
ldFoQrM5aimKx+N3i5O9Q2R/Mm/8dus0bRdrqvSGBwzuXN6GTIVIWzYwInwFduVsSSnEk4mmY3lD
abPwqJ7vAtoiJ7lUg8h/SLTeBl6u+OzYIm4s3VpQj6176I/BCQCMuz0WpeKbYxu337Vi3yL4eogt
0Ui0/kOIfLxnDRta1dR5DYvlvlHXoJkjGrVUcAQRtVTXXP5RNmurOQWsA7baMXvjGvYk3WMo0/85
e6qAtpoW0Iz4Wfc1ylKe/KvdD1LwfcJEdwsDN8chC3sVzXkzxZ/WT5NmsG93GY3kiWEXsAakS0xK
fBvGk4UztlgB2MYyc7PtXntkBsAcUVPslMYIir86MtQfi9+J03tcD1yfUHPmA+7RB3ObfOZK0VUR
6ljnQwdIEy+Ci5zHUCAuemKTfZ0IBUtsqKvNB/nuNXEZCix2hFIED1kNxZ3j1TqJIX8qcw3WeAp3
E+jnRPw6gQgVUlyDCpY7ED4tzKdsLGJacgYxDgwVHVcs3AR4NAIMGBPvpP572Ta1mgwn7Ugryq0l
U7ziDlgp7x5tuNXKWIWo876NtiFaN3SU8luZuxmsoc8t5gIqDr9GtysT6AiWStwcg1BM0CtcVFJL
8jT76XvbiMqoJOFeCuIcdEsE0VfJ28z/ESJA2/KYJBTXNHLLP0EGjdgOW44rfF9buYBVDnZSNm9W
8DbQCtSPX3hqCd1/kko865drd3Y9QeCu3GhkZticZbBKw7VacdZ1BySt9WKwTgm8AsMrVegkm4fI
TjzONxpvUiv07rmtrrFPOifSmGts8I68OswFDgcF/KQaVqf3fe7nLdXGevJaKt4KslXi7wN5bnrt
H2806CASWvHpZW22k2jwIGMVoAlvs+/sFHlksuZai94h0EZXGX6J2pngnflePlnuh1I2U8XoE/FH
jSG5fAyglEYw4TqY+RfSrnweQQKBWx1faR+4OESTCskHwIOSPPJQoSOC+1YPvtreneCshi3FFdGP
vRMtJiR0ZH9qxMl3lBxe2DJ7k8lXvT3f9vc2RMR6b7L9QRG3pIfVOXXwYFApv97Wk4iHltpsps5E
ZY/yvHQHvEg4MpBTm31jMN2qWo9zgV5Dip0ygCP3v4xdkuYLO1tQw/+yvC3YpiHQLUcQRmPx+90U
43oVlDwlAs5H0bkD5Z6UhHpAno99hZmZ1m52bc8+jSj+9mf74K5jqZ+Iy/nuy63kN5+iSStT4J5m
lL9nEs+U8WIao78huP/QKzeCIFVxbwZ4WEyT+EfuohGOY5E3MbWKsK1KhLNaWfr6Z1oz0uIHm6Nj
5Chj/kQE11L61eD7iBR8J9TJXEzziBfFdHArlJ2awfioSUmxRdYqbgZBeLWn7dq5ao7zlUqiZAx1
JhEAHO4oXkYv2cxFv8I5oL18XrwIr0DIU3Sq+xyDsbabmVkfIZ/hHt3UE8slq/7PyTqFEzVmeCWn
uWW9UpLitHQdIQp1VjQOx8UxuN7prAQGbkwFCIrB7B8sk1Fxpw9JCxZugkOcljCP5e0T+XkG3mop
vaam9px/UqSB5TWSuhYHk9jUhGxvzatnc7zknbJkx10vgpmYoBF7zm44w21z5coqAsiufQ3YFB9C
5/PlOBWM5t9NtwgHCvM22HUFM53jz/N9OTPDUcjTcSBW9/Xmj7FH1IHwapOeRD0EpRvRsywbbkyM
U2/UpwR35Rz87NRWGH6zmt7Zz1aaqIYM2hFnWhgnlr6191w8SLi4R+1P4WOHZhk3Ik2fzuYmhROr
QAb1wLzpio76V3/5crhh353FcSDX8aX5Tlwp4v3KOQG8nRAh8FsY4b13Ok76v6Agq0mHKQVLdjKJ
v8ugk2q8T6JIQE0iNgFILj5rUN6ce2nc6jI8JKSSOrjItFolgW7ZL1mtzHOE2g8Hr8tImWHOzFRo
rEytDSjidLyrZ4GtWTfUou2KOH2lQTyJLxO3n0902bXDLehW4kMEsA47m/+dUa+C2TFpFULWoKYP
v1ZSgz9SKKZJcuswyuEzv7UZD1tSP2aNgT5Zdm/wC5K48motXr+lQm0hCblNYNfMkIskznjqPHCH
EHhpuCS9b/RGdk7BgwSOyyq3QYUyQcj3mphaOUTBXCwGXF6kxjgqMFgsnE8NpQZYR52YibpyYmvI
VtUT37e2LdNhrDowVwW08d1bR+7OlevSpNllP0a5ZU2BfHkejLj8K5PtV09l11sq12/y7TWc/jK7
DLFJcgd9Z1BQVwTYAAKz3Ch3HFEtL9kYLJv8+KQ7wcS5Xq9cgiSM6nmq4BkxajvT3Nn+JA0shKAi
eyq773pXIFAz97HNQt8IZYVubP63rAsFJuqfDutdwwnn8YyhSuI6wD/e4rP1p93gbDDYMUCgIVvq
BivX1A0esHV3UyIo3fZWwzwHBOqD7fX5l8d2DMmm+V9kxLBuddqLIGYOKZqn38Nn7eJDNwwO4Jrc
ruILMZSgFMovft9zShXQGeHlk+iUl4QOoC6HuRFoUm8e/0NlxVTLuSmlhqQQJrsctXNrHFo6iQok
KrOGaCM+IJmfj035EVWM+/eXeL88kE3azsVs2DSenTyzpXMfkP7249yYMID6qiNskexzcOCIBOEo
QHExEpjdf5PLTt4BKjQhGPa9SoeUuHE3s+aAuBU31vrXyBoDtFhwDkowm32q3g2yMnaQ1WkkaT2o
lTgzSfiyAw2s3a+fRhF7lzLpoKPHgkulpRF7cVadLXhSi1hruSou1ntt55yplhx/jpSe5YdoxfUC
cXkrGKh0yUblTIYjtc8qX3C94QFCwm9HLslHlp1H+HzSAOhKGpoql1mKuF/pakFMpJOBHxz8u779
jch5RsE6eeyja2VKxz7rnjE+g78PzMgVSk1+0uXrLSYHdAHTVJDQOOYTKI2Wnxh/TY8K4j0fsw0P
4W+H23xZIJOMZplq99lKDxOu+IHokeVwYVpvg8RAERTYUCvO3OmUG+giY4D9BXAtzjWkfGUAnvH1
hFBbF7Agl+/U/bAnrb4+Ezjp1qmxSYSgCmotIVpzWwR4QHKv8OBcEt8h7ImDvF1iUMJvQkZlBnfu
dPZ8lMUIdd7vJSI5yr3NRDL4f9ZqyGGMttzwxuaceRwkubNdLOF46vyny3P/4aOjzshPKnkddVsy
gv+VgGV+U3tdGsTdDxsqM5/zHSg0122RZgyREqypg8Wc31mWHnXiYZUKjQQKqtf5cqL5Fj+XWRAa
V9kJbpLouHdBGI0G0yeyZaF5xys+9ICxiLgd//zmxx21fdVvRMnZFNikzYhMdx3hT4fOXjRdzlv0
/+Z5mnVjS5b8wCSMzqD7P03/YFenczhloMKHVADoWbVWa51Pw6yOagZjIeK/v3Ce+lw2GFD0IkVi
Oo0tx7Mc3HsJu68Wrg4z1A4ePf7hISqby7mR6xZDyubipnzBQL/dB0oUmD2fDIJC6Gzp/MWhOsr8
S7ERUOIyfuoFNp5QyvdABW7lt44xqe7c+hi6SWvyoCROqNTC/nxLJaGEv8+y+3Dwnv6iTQFBujR8
WTiEvSlducMx5DQzkR8c7kqVTKhFJMTyB3ijwPWo8V9W/DDe2kprRYvVf9r6qcrV6ty0dSxxWiP3
Rd7hWfRR8yTH2KEHY/SYz3z97XiiGLpFrznIm38YtNtTdzgnXGFa8XE0+pksPIzF1to7y0d3GWm/
YwHBLkjH2JkhRzAkotrZgb2cDdPtuKLMOBUIh+Pt6faq9OwBWBEBH2uRv1VpCVPXGlus2NvjA1rG
nPgLeh3YD2s=
`protect end_protected
| bsd-2-clause | c1c68f584e498759367df93006d08318 | 0.947328 | 1.83322 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_fwft.vhd | 19 | 38,466 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PpoeUczC12+YQ6zcBW/hk7KVg+x7UTioMUTG7QSkaE8DKLm5OzMFnRnSP2RdM8C+WL55mLvLDYfA
5lOC4Ruqpw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
K3yZ7/h8XZC4VnxKqSX+X1dWQEKELq4EziAIjvSKKzex+MM5ch0NyAGabLWybM0VZcnyA2IuBQRw
LXtEZmU52Vw900CqGAC8j1ob1JJokunlfDgROKOp9VekmhrNu0zlywHl+eh6CQ/t5W76EWfCnLXS
TKcvUxKzMPqBkiVg3Y8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NSAGB2MTAPfuv2AfQtQrWIP89UNTneL4Bk6/B2TdOO+6mmG5j3iveazvIvg7qIHwAqHfCGACbbAp
fGS79Be+x6ilLMPgwgbPlwYl5oARsjb29GILZJJbq65kaBdWWJCFrRmIDIFHXq65c5qChGV/7EF5
BRY2p2sjUe67cd7MFOLVO0mKHurU5wiieT+wdpbGs9uEgt/pGFeQKlj4ch2XzN03R8Lg3KmqOC6w
j6pa6lYe8j+sQMdh+WMN3EmYurAN2aA01NOtdnD7EoaLrP3ByXrwCKFB06hQfAMKudCun+42nXbW
17uiY727vjm9PIB2xOmQazUdPEZbwz2Eeua7KQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NPiHNhu2YI6wz7attBCDx15tEqFL81ie9/7cRUJzlr+aO842fU7+GGF/JOlqWsuQg2RB92onmIR9
gKmj6xIVPN77wRnezyej9aQsYy3bBfOSvbf7a7d2lZQT1pTZcYMfp3xveVQ5gTGk/1BN6rnnT8J4
QRALHC2oqPHhQZ427wg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aHttOHUQP+m+tZmSEhqIMk3Jbc86fWQ1/2LKPbbHBoOHb+XyETCjDqnDo9IWfpo+m+LC80obW4Zd
cXgM5NoQ9F1AYdG2ggcdGNXeaparpheOz+XWEe8nirOAN+Ks5VYo+yRWYwO3R0Y+0V6Yw8r7cd48
CXttfKVhu2QOlKTiKegYDKMRGhVyrdNkx/KDldRFk70rkBceBbiSjdBniOrozyhG2imBoMkKkCmI
8TwlLhPf5Ra+r8wceN6j4BjOnyQ3EtzJgw91ujnHo20MZFiaPiqLQIavDgBT1y7leXT7TIK9Z2uu
L3Oj5XHzPc1v3FMsMkjnu8xWqC9pP05Ha8xR1w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26736)
`protect data_block
Lw3ntSlrCokmfZtclotQk75wzvGS8NAVbfW40Ny0M3qGBUgwlKBkocOK4usgGsCHzLcvJEWmwBj1
3wfmeMovQ6E1L9p0zv5fHQAI3pbG1yrQ5Pb1RchCkOLmGsOWkL4hI8Ky5pymEJV1Gy/67VFKPPHp
STpFio7hukOaG6yOfVLFz3BjqWEdbVfaa9tRGugyO+5FcqZfTxEa4Si03udjzcqO/H35KmceoELJ
CVHDK/c/EMXh6yS70PdLGd7LXJrWz9BaflTPsqg0SsBoypFIhqc0Akrc6Kfn7npE84ChKUB4GlGU
vUH+XOAK6WZPYMBbzSFb2EyB4R0MDSlk6yQ7bouMsCbdpYezi8JoXVkuvdBh8eAVMDcTUpO+zHOG
cOhyf2+W/j2t4Rh6DPo6Z7SQW+ZD5XKHwTANc3xKbL5GImmKo65uLWHhs8yeUBgjO7ez9gSK9ImO
TXfAwYByaTC96hkCbSVgknq1RpqhWgk7oqBSVuVVqqhPaXvMQT5WlE9ztefbtuw8ZR+KnU+Uqy5O
JJkSpS8ZMay7i5oG3XwXhDgjmrvEnj8zjpyY32Xi3vfWU6pKwGxia+3B95RJhTv9ClBA54bT8zyn
U6mU0a8h6xBr8FxQ9eJysWb9Nv5iWvzi8gdfy2MV6utnvncbYWX8Fk2rhNw2f/AktfVi8tMpALIt
bxb8I2ZUMW0W+WltnNR87F5nSLBowjwjsMwTWxfpUuY/YP5S0670UjEkm1+47MHIZBqku1kyACFP
k9BkHGzAiMYJRg99p2SRFHgz7hT1RjKIV63TDKmuGyNxCxNCkr2Cwr3bbvBfiG8OszPfP+ysR3Q4
TFS1vrC00M1tevsr3RKo5v+s/ovLj6NHEk6qwKfHxuRCcwZkzF7cIeSEHQnxikAkVdqFsfC2B+YC
vcJ8p/3cu3a9TGi1sRbsSy66u1WDHPtO5BiRYtsSsgomPsPCrD5QSVQFy196L/XxJiJoQgvyrJxJ
VoM5Eu4fLnoDPTJQlWEm8ZFxKYOWGilL0jBLq+2A2HRn6DfPTbzzYQ5gPbuhOcoXKhgj836wPGQF
LYoKMxERfnDJPDheayMnhe1OG/yb0VfkicRPAqDZ/LQtZ/aqSAJzt6wVQSEU+y/45UM+sfJ1C/ax
E0sgloo0mQjB3Ge2WPuZBXkL8NC7fqBaaDAznRlwPR8e+E5S9ShyZNxXvOqFUCyRYQqPJAn+qxfb
rdaHg5saIk3JlY0bKk3AQR86bCmRQUw0UtJDcI6LPYVXSp9Z67HTWKCeT0Z1bEb2jJnj3DFzG9aK
1mP6KXkgXiGamu1TZlDfezhuHNc7vZufwldz6XmnipHBg4sZIxcJbNqP1GIquwbz4hpCK58WsSla
JYl464gMCafm22GcbZ+fhcPqzjM5NytZOkhaeGsZU9LLxcBxs50J76MuNbI3BW+n2nlJiHDNrHJk
1GY00lltSVFIe/BeK/m7GHHH/WSloyiLGSTX7DqndwaltYCkLSvtam+prvHLOrmkZg+Nh9XDR0y7
xzXHbjq4DSC0FGKJSsb1AmbqNDlcHyLaCxhWlYEWUPrVyqEozMKlFmf+PSz385P9HAbbOdqMFoz5
qJLPdc42fgT/S49tB4mn5iX9jC0flJ4VfoT3HRu6EN93FreG4iqGIIjf0caLMMhxn9aBJFdygvCZ
jCviqiwiDLMsbAqzezwNRcpMrbv1cb5LuQCzOFJOckCv+HI7kRsZSa68sfVe7FyWS2gc4DCJCB00
JEUoMtzJVvGKYd08xQS4c3B4GTvKhdUY7mYIT/HWri+psziRwLykLQP/O9ajxz0Qt+9eeJAEERaW
/nQFXhuXiaWgBMVlusuhvkE7RNk0N6dvFXQazYsCDbPk6UbKS0W319a4zh4brl5bEa5d7WbLHG6H
8ut/H8gJG7GvYleoc39l7tExXA7K1jc5SbOsey7ZqwtffKnm5L6ZnKMCnWXMxRcbajQfpuyEVry7
I2VkzhoI/A7fMaGK3fTMQ1PHeurlQ8JIFKRnc+IxGcUjlzdk3UV18Ym8NasQe5mah8YpL/YvEdTc
+jXmBOOcfk8iXefsTsy9pYy512a8G67Q5AMRi7yszcz4V6O/CiRieoyMS6FRljneBOF9Q6e1R3Ch
Rvh3hANMssokfb+YDaU/rTn0G+CGzMo6jY8HbH+xzJcYozxBqw+AfNmEefSJmpWcE7hkRtptmyEB
VlJKtTwZYOtDLat1vyzp+ED91waawyn06GO76JUuogC4FuNpr4vFQQMmcn+A/S06UzHmRS2ao0yw
mHgOKp1mVXg75qdKYRXkPqV2wcfDB4/XDp/D+fCIRFE2DZ5TxIAwVM2fdQ6PtID+ddt2Q2Q6flFv
P6vpj/r6Gm/O5U/JpHuCqeLLLdIbQmQKWYKfPaYHPlLTjcLXjuFgdS6hhTtgoaUWOR6MNBBkdcNT
MZPBu+NZPt6E2alYtBmRE33wKFznrtKa6thViDReJiHfqdZjU15OdG98JXO1stHbdfN/hqpwQFvA
Jx5vInTvHLhfMTDybDsT+ACrnKGOOOXGGB2Ri3HRwELiPoWlGpjXEPTcfvwz3714B4x79nRMyNSw
zey2GPL2cEbYmATOXXTAKAqW86h1yqqV/kGJ6eN42IlOBgK2jXw/l3ieazFfa5Hosw6IyvLPkaDK
Zaq0eR/ok9uzGU/3NxLo7wKxjLxcxU2ZK/4ECTJrcded8Lnw4yEJjUxQ4jGOJ2TjnjIFD9MvimB3
wDSN0kUsnwqd6HVX3pa804dFSm3TZWdfUh4iOzK/BAuVt8ZYfqpTiS44DSvcRAfxmQEjlsMH0RUI
/mMU6i4GND5Z/SXqDywA21y5ODYfFIMT9sDgv+PRyym22+CMVnxZh2kXlQAlBnN/dXKo4AKAjiQ9
E8X67Y7OkJmw2Em/7QmPTkg24nsx7mEewtZ1B56MdwFXNFs3ZrA2b8BqLeJHswdRsTlthGYcZkAT
uZaW9B9eDy0UbL4/bqv0N0JqHBD/ndg4Z6ceZXJRykGEm0GU3dYJxCdw4CO6ca5scsyNtCB8ovQR
KB8wyIuexIfPvxTxqF5PDuWQEi0CWipY8UHu7ZT3S+TCB3cusDj9X1zeR1HQpiaWK1GQeyPSsMu9
QNM5z9qbNfqADWdgWrH6+fIm5UD3sGD38lDVceO2TjiGpnqlfS3W5BltJ1rtm3sANUNl7HNkZvrY
fJqDp9j4pcDWOBbDsGZe0crIkERuFXNPmfWHYc7vFvLrNxPDWOC3DckbiNb34RSQnYFDTVFJWZs0
KNmXnwFGigPbNYuyexyWQ+D427YtA3CT9l7DsGvLZbu3NMfB0PoH2xslyp/uhf940tyOekpWdAPN
9qtZI5jmyRt4JT2Hz1O9Jrfdqbd3rXyRh71k6bmNVQpK1vQVQirsDi5z2n3MZOx7PfZpBxWsgIOo
PrckF6FUdeE4dRFrNo2eNTOH+DtZ1KOB3UhD1tMu2PoZTLy/wT3arR62+eDmdG2mvfUC9+B/IHxF
K0HZXFJ7UVC83T1u+iBh/3/ggH2tttccOCC/tnxqnc9yIJ9eGkUgjUs4UcP3lL+FTn6/QNxdEccr
EFJcLEZ8c+lCjG1By+omLwkI7pp7dS6b9YH4thdSuXCCGQErgeq4oLNj5jMUtz9mJOtGGtbrv0vH
W8IrAhVEM+VtJEQSW6U/4K6a6GMM8f3wK0zk/U7SD52ioV6lmHZ0jb8vTN/ProLgEuoudfyd38cI
1mD5ljwoaYHdXz3uZ8iIG411D+7lHjZ/WETTu4zWM4XbF4JUlKPpgqgvJhFRo/glaciAQICq4LoT
KA63mC4AlH+bh4Y3Sw6/V7Fa4nWfobUqZOXBaHpGZ1OZ3YAN+7jZqfHjYIyTCq5ugV6dX5787TkF
HGJizTdNtlQfPoxBjTQNRLu+mCLJaMaylv7GFIPDRBO/5V9KHQvKGFoG5HDjF+J3z/FIUr3jguCu
9yWUoqz8pEz2yC+pr9vWblKM544Q5No9kWQkc6wmP/mPrx9V08O3KX4YtlusbUiTIC4RpQADjrNC
7rMCq3mnt9kzCX/8HGEcrCh+0LVEf1PlGzCVrxC7JovzEeoqcu4ioeftuYrRhRfTSWVTebZUwXqp
Ur9lzR5L6f7sT0n7Bu3sDC0eHZ2C5fr8KmrXKuDTrjlPtpFk+AW//Y0+wY4feCNFZwMeKvRXZ7p1
GQH4n1j9J8ROPfWVvnpqP6eDuMA2hLgjKFeL4mCWk+iQC36hmKFU6E3nyNfazdoH3as8ufwNQDNQ
qtqiUytBNkcieqcyh+fuKZ7tmSmldj0ZPqCC5SwmxHMwhtE7/6T1uMUr9kFyXFAeJnlQRiBuQE8Y
Lw9BkAlhhH2QeFHaw4m73iN8EZAxqvjrf4obRT3xuwoOvgedGAhdztlHfedlyOCPITMYJNa63JTL
NvdNVYd7bIjKs8uK3r/LgPE82b+pgr0IEDPdKWHnqYtuKhN27KFEYPZ6NTFzi9Bltupvaeh6GnYH
QAJ+KaA/OWfVyFfMMUZbDAoFuEUp2CCyyltaeVVv6rxTHvlO4cliqBLmzSG+UD5m16eoNc9vsvGX
pfQlCGfvX43mjbL7YD9NQmaIJC5kMAF0NrLEEi0LfrO/F9ju12O0bq56igJSsLestY7cEqxWJCcM
WgcEs/DYbdTQFjBhBSp58ZbUH8awJYgVc+dBmlFT5nbuxKaDCY69FN3okAoZSAzoNa6djAnhtcc0
gC5bI3gYwkX4QdJGYTAY0+kCzlyynES44iJBfc+aFlyOhBsCQfXMFH569pKknjvRb4So4hbrnc9I
3e/0C4b/XdlrOsooZt1N3Be4H93+MADHdwR6cvVYXRbQ7ThSZx7jo/FzoUXPLTyLRK/8HW8M9quy
mvOWzJOcn36uHbrSm3Er8aA1aGToYtXXyw29HTFcUvGsk2/7IDtJ2k/h4SANe6cTpbXbyFUBdif2
4hX9/5hOaPRU2eoxiKExILa2O7x13CWZ2OAcAWjf/KZ0X8kMEJks8WFEVdflHLkLn/Z7OIWpXjO1
rc7x95D98U/2dNX5604RRqSEnsbKVASNF04dYsiQL6ijON6rVKC6WyMHLTVIwwpAGnmYHLYCdJAF
SV/cdCTP/CeXFs9T4HP3JiSpjeCtWzyd2scUM2TYSaaqQ4mutitqrtqUtLawz7DxfkIUwShpXlLf
1v6CLFAnzn32J/LobO4q1w7qFjBUfny4CPn0qlhxyp2l1wRxyDQZ2J0+jctygeAVv9cOlaWUYjsM
MrKvYc5urUnJPNmLfH5+cVHa9NHpowUv85QOT4nYSFrRinaJuG9V9WCrXMFJyIXx/0rI2oO+Ikqo
7GUHPV63fC32gzPNDiIap007yeb2lfxU39RWTMYwpkuoBqGR2y45sBgHR+jNqnEPuDCoZFQlCKq9
gWRH97PBdNdRHEuwzaiOQ1Wu8xeFtJnCuqS2TcaVZEKtffmRc1mA9reUBEhxl7hPhMTW75k2pL4k
wNK/NFVIfMcjNP3QDuoblGYqNI6PC3EUmTM/DqeOIp904HMAn/Ke2pLUgCladI4dVKUeEtbsgWp8
xQGvn95RAZazqo9C/xeVeboyPhzUszpbA2NBduuKb5usRw9VM8K+LTqzipUecNvxjP/OQtqwkvna
kM32DH9/Ej19uVZuHb3tzJmJvsjWA5O9ZQYrZlwpvK0uHNi3upfdo7DkCJvn/1LYHMBVupLUGfyt
/dGLEug1PP1yiwREeV3lrytLAy6OKwY/XT5Ov8tBIpO/kNbTIQ79KOKVm46yuvBWoDvy8kHtiCWz
/i/cAQZQslWd+2rFt0uSk+t5PdIDxMkpz0FWaxZZ2Qf5JzBQ1P1q96HD3V6FQwc3Xl8KtIFUkRQU
hpSGgSTxSc/J2PsT+1z/sRFbALESLAu8InYOUstooK0gUCOlUpU3w4Q9xrzEuY1Z0Uxq0IPFOe4+
mhESdybX1xpq9kEZXniPBFiIeKyN66/eFeZaiAra4wQLjfDhytle+j8F/B1dCFeGt/0bTaUvae1Y
wlxdRrkLTdkKby9CjZBKUX9TIgcS3D0GYjixUKtIWo3Axk7ZTGEvU5pBrXaB/iGnd9HYdW6mWzz8
H22hWbJ0YctA5dedBGvfyPA5DAhSdTlYk0iYcnY9aIjvQwPZSQ4LxeOJCMpgLeUVM0Lm/o+avmwT
I8c4s081KdkH8wHD1etb4hnx5Pz/SszlXMMjFhC+vFQg8bEhXmib67GtCSPbe6mk9NQ6bOIlnn2L
JoN2Lbgdp/KVSFwIyQs63o6GIQiiylU+Oq+LkFIjqtutzIaH2aG32bRcdAiAQ18fitq8YXmdz1po
0N7gFYNzXjTRnnRx+7uvgW4cMsovSTSivavYsJOH8imKLHeYqNs7CmQWxnIMDrtX36XPjK2IcJG1
EJ7Q9UeKwUvk3kVLUo545OJvf2shAv+e8/kwHwAXiiGpHt7ekEgR9wydPBpS3D4xRSrDz9ecqGTZ
XCoAiN+cGi82aAwoVCG9PssXL73n8amozvxEVDEIntMma3UMtzVrXAseC14SjgK5fi+Nf0weLidc
/iSRc+CWDYpFb5tOVjXWZVk/swW0yZ2NK0gbJJLPRVpGlqLeeJenXF/G6R15m1yIgWFwXjdCIHr7
KCgiayIQqC51JKL3Mj1I7FmsotXuX69+esp1qo55s3DnfF7vvbud5Sjgesb0nsYpJlcfRVx2lvb1
SK29UPVa1em+lTPmZioE+R8hChU7ZAH80XNP5XdUjDmE0r3qf16x+lHDcB3TyDwvxmlR5nGnHC/4
eseu22nWxUj1r2aecSY0PIldYjDq97E7CG7/FDxuFm08hgL3/oMiBxff1KzGOvJlsSLbMtesg5sQ
4dAZp+2uNJu0WU5PuKBVRsxRpY6fYGhqdGsHUzJPylsM0+dRP46L+DSPmniHSrY/yyW3mc/1Q5NJ
mu9KcRfexlWwbj1V2yjVSKkuNEFOYbr2IkBNTP8fKW5sFiPVYGywYMhCDwcfyRK+f6ZEf3ijQnpO
P2AxHwIRfj2tzD2Ub+FBtOBB0OrOsJHL5rF1070YFaDdCqNyiU0oObZkzDz3SfsOrEeTm5Xz2zni
48uZWqRUGLFYaSsY0mo6K3Fki+36Buqqq69X67ghss6+XCeH2Zz5xOxUt2o624SU/L8WplBkVZ51
XqUsmshngRZxXEJw/S2wsoVprmXtByLf2UwilMp4NF6wfP+xfd+OKvwflceHaASKA6seNn5bsw8j
32kPAHChGF4HyHBUH8CIwOTNHtq47WPEJ2HciS69bV33HCBsd72DZqSuG90dFPRVsdnVK5ulxS2G
qZyQhSeP5uAJA4Bd4phbyCaaO3FTR+ySim38emCA4sbK3/47tBsA/N5gRUP6pezpPflLUpbanIeQ
ZpCDzSV9RYgoY4H/sGl17eBl4q9G6FNm9eOvz5zk8OOz/VSItbiAymMPtkPlKPaMHUTHLb85Ubw+
K6BNYgZmfjJMeMlpaK756Ik1WPM6n5lwjStREKYJ5f0fuSFBORfMYfFZzgDkn9eZPVrsXT0y6HDG
bAe8Ov8ZU2boLIaQj7iLaAmYOVSauhihKocfIAXq2llCxX5uFFy/uEsi7Hrdzu/4gC/HPOlnRmjN
kzH3ckFwEiaKQXwcshIjlQy5hfSE3Ubz1OlD04/pyIN3lypzK/CM6qSx7JJZPPMhzuk+QnxY62WR
62xlz8YDTuXadJHWFr22kwNnKpkFRr/Yy0HXZ/16idN5UmBu3c9bjq3LuxJoolpf9dG8srziMxkZ
xgti3rTYaRZmrG1EUNvjbQCPdS8LDkPJAox+lkIMuHzAMd+/2KiqcZwpSNJRQo0N6Pa2MmkUWOj9
jN5Dj+mRDWz/CNQplmX3TBTlhKJ1CuTeQeyRZk5VgSZpf6GKvjQ48+6/bu4jRrVxK6Bm3GBaji4s
qMB4c7yxy5C3gGN8A2IhiseGtywpg3DHOF4fd0f7QEuZid037zqZmLCIgteIKGneq5XSUpKiadVm
gXEhD2/Y/Lq6YNr0CB92TUoEf2SRavepT/kSXqTpZJRiUTS/wHPkiys7KCjDOYpvuZerwIPePFAn
jsZpk8cOxhveIG3QevMoDm3OEWMy9NJJkCBzvhuFRieqnz4dzyAOf8BWCpcJ7byxU79+3hyWXODI
wBaDr6SSUgxBqej5BofbG2a9ztxWQLPnxBvoIj+56mR1HRgjPlke9KtQSlRkwottVs22CzcoXmg7
cI/QKF9v4kBM6iZ9ZHE2a4ayvon8yzFAb+N8bnQn5kLgZj1KKuYul2zxw56iHepRUs2G8vGBS1gf
8kgow14QTBaPh8qBgairIrtkuB12qg3daoBdvH96MySHZVM/VexuhRbTlNual4a4ch6Ee1tfaiVh
2qsyLRlGsdz5UfGdElwBcgsmgPyF6wDaEprDcyo/eW5pGv6/m0N5fUDJ8swXvJtTT5ew0bc4XWG9
c+S9S3+y4QxWVvA2PWAgUUhqt1sYInAlwhSkl6XkesHLD9M1YplPvJDmov2O70sRQt8pO/FjIHh4
mGSWz5S9tq0b5yrPX/UruWCfIP4zt7p0W9Iiu6E4Vc+q9wZiVMEBuD7hOVSbltZDn0cb5ol+a+S4
mBKxx21M6Ak1qjNbc+bw8WAZdx6u8gs6E/fTAVEn90Z+Kr5VfIubb/HBOrfL4760Jk/IPaWtebED
6STx/YTc+u003dYWEP+2QdRTSXF8JdXcPf8p3kpxx14B2AZjoP5U6ZOT3CVmEJI69iGESwiupftz
KZK5bByE1TGqnFOTeoGvfn4KPxAIKgjVRBgDR7uFQjUFrr8f7x3QGwWMacytQMw1eeza0ha32K9b
DM26nybZuU0by51DX/Ji6mooALTWVqc7NYqXVoU03PjkrAW5zzlHULbuJTbET0awZoB1jIQ4wyNs
Btr4fjF+1tLTsj4vY2R1PphD9XxpJ+S0odaotskCVC0HP/FcnsYa+O04BQSHwVww3fxJ6dHN3xxt
mINi0RogqeD9qti6BJfsYMBLR3gUrh1+KY0bP5EIQyPZlvybTI0HhZgSbOTWo8DpHQCVQDcqZS0x
mbB+HQlJwUxvXVRSNj/3pdvkG96tRU+qznfLRUJe9j79aBuksDEcEPNwx0VAE4xD9LwPh9VdW9jC
SRbbhYHcX2OVQ2AZSSJEhf5BvNPrzDglNlHcVeqQVtzs8PogzJ++vr8PF+TlzNP7CxRIPjd4yQjG
8MXz97wzr5xto2W6mnCg7XFkhK+Tyx2+UJrZnQ2Bw5t0GcJikn8kLnjVwEQl2ByjFO5msIpbmGtf
1c2qjEQNcGuCNocSVCVFcY5o6CqZ16w4iTIn2pcnBVW6likUMK7hjj2m6+oIHfMT31V3X+5xYKWb
47Yt8e2GaePgLGShMsuuxkaeKlO76rGa20Xn4zlvf0yG8kDsufPt+OZgSxQEnMAynrnUqAISov9a
fKk8u0f/lizi0jKvuYP/mMXVNmexwMbY5YEXcG4CBjt9SFrmnQmQWUOgKBWmDi/JdZMfp2FXGDXD
vOtfWhcTjRF7/cEgaPRAGRP63yap0KUG3ThtG8mUPAk5akGwTHdAGL8tiVaR83duT/AXDJLnetMW
yJgk6FZqQpPDKgHuWclrWGJiom7o+1Q6CYsxQFcgQEtbWpPktba2pgGJoBxBbOHYlgiFC+g5HoII
i86DH6rDJ6d2uHBfqffXCqomigEmpDkPkL3hRjHajorvfS39lvuc/s9VLBq0AnDPFz9m9xEX1I2Y
1KnSGdWaxDOVHf/050U8NMDz7abagg44SCSTOyTR8YJub0vWfmYyy1NZF9c466njfN+sEk8KCSeZ
RvX42SC4U4MJAanFOQSzun6hF8jniTbkHYVmzj2dX0NS4ayGjODaFJPfywT3Dkj2QPZbKuTprAbL
WjsgiSnPgwRftXywPU7PuU4x299CUz6ywyn5TDmSl9N8jSdd062TtZ84PATISVVZ9kEAigO861tk
sgsyrCPWvkCKr9poZZTciL/uP+EINRQuf3uG0J4IOS+SvAC6EvYd9dpwqUqOr7SKbtx4CEwC7JYQ
8VABySrRmoatZ8vb9r3CZ/8Vx0soTEwwJroNlT1fBc752xwFNAkxr+xEJe0Kl1Iu1KUljT7Q287o
V0sfNvtYMgWg3q1tbscV/tp59qzCD3qJdxIR4uv/IeRlDJkq2qR7VZtGgNr3iJSvS+8naM1slJJk
Z0uhhPD5oy03fQ/TJbZkVj/Dxpn/KqN4S1iHK+8NhH+s+S+5LlmiyLM5B9smSyWwQHS0FPHCsCBm
IC3UToAEWw6UMf3kcSjAMLgN1IspxJCVAGVVkKb9o8suiYq0RwhN/efH0gUDyxXV/Nifa0JEDn6m
ZyY2nvIofZpq0FBueDZDbismkwoWRtD8Wqz+rPOcXjgHWWRUcI6rvNtOV25a+SgkpZmZW14Z9xed
Q+LTNpdwZcIS0SipIRl5/cCFxn4cYnlCzHEo+jVSMQUT7/v8+bRxhuVb7CHMI/WC8o1itIPbvpxy
Oml7Juy3vdKpWEmqW/zzBI3eIxhSzZgTugYoStSSY9HQP3l1Hva/c+KC9LQyC9F8NSBiD2bMvkDC
8ZDmWofngPiu+N3C1nbwndEHphdrc6GtgYyCsx3ma3h85hrmfDqdLjMJW4lcIcxJKhA3SiV+5+me
Ek8xb9PV5RuXgKfhUK3MUa63LcWV2z5wb53XbEPRvtp408TyG+blePGJTya0kvoFq017UivioHZ1
fSuK55Gqhr7UogaAm+nwS9UL1IZyNmPDvmthUmclG/fcntqK58A4ObS9s4VZDzLqenaI/4Mm2iJS
JDrdizUsIR9wwqx/coTaRR1gOH7Pa19cjNgWctfA7+wRsT4cluSPz1d1ygleVuiF2nz7+e/274ql
s/FzOhbLORmGe1u7ifPEcmfR2FX/5y8XkfzaQjzpd+bc2tWRhyQ1HIQMNIfRM95GQt8kr68bmSwX
0RhwndVfsERpwFJo7R8uxNyYdGCVno+UZc6nTsBZi4RDi6dx5jOKtD86DT2oQQOiaGkHWfTzutct
BzAkw1sN4d8AKEux8YlSIgqoqGFvghTn8H2F4y4nfquDDKPIsiuGmtw9JMG0pciXw3x223gCFadh
ZCx5fk5Oy4LuvR3EseBwROWwYCs41AhyQEOkNaDtp23I/GZqGsRbgK78PMyb8TV/n4f1o681x0yA
DtFeRT+b29Xej3TzbpIxW4JI5EpFKRlG5XUi2wz76NI7HWv6HKj+q0nr67uPihhOy7KpHfHiJk12
MuVL6kOZ0tKd+bcS2iLuc9vpQG5QOiRi++SPzkWCj9OTPJVKzBU77Tr3MPk2ybbiQQCGPTYVTsWx
h1nKC3He1IDtOzYBm7xkHbSWlsKoymAGgezUHlxNbzin96sEtlqA+eBGqyeqUKbE2+n5WnXwzf2+
OBZ0Wo30CsKFKDceV/izLfLXGVNaqGos1nImVEfy8j1Q2pvlW1K0nRjhm3Q+T1yDaH+JDSPg+MRl
QY9cZWurmrmw0bTcGA3GFtk+kYZ1dsQT41epNYh96eN9XitKlhOSiV4bmpd0q2iRflqxsrpjzO+U
dScO/PsEnSY2f0LqOcHGKPtYK74GXXwtVBY8JWC5L62+Azou2zkckYRtKV638hWYm/WJ81MUUMac
EIWG6pRHiE53G7weZwv+jrazsL+Jz1LziMHiMtKYWNW5pKCfmYE4/7SBX/ZjaP6D/NvhKe0jbPPN
yjKS8cLtOH4Z1z7D5zE1o6NR6ORxgBaCSgmX294sFYObYsrQTRW9ZzKCX13Xka4sdTaitoDgcMYR
2Ax6CYbp3a8MTsNRglw6/Z2tGThN1NGQJhtHeLTU5YwNbt27cqru5AfhHMml/7bRWxVT8CvL3dqY
KkdGlH0xeZ1zxvuy6pgpKUmWJ5J9G+VUgpxa4f0CeHmuIo8M8c8g0mZ3C/vf/SNNJ78hpXQm18Rz
4rXZE/OLzRBbKTV8o4KN/iQcLOAPjF99N5ElhShQHeTOcfe+Utt8A9HVHXdlCNMPZqZXA8eZ6/lT
Lbv+4bCUoZ+HFjG/jnez/2sSbpKp2QhN1AER89mdQbLI4kCi1lQKK04sMJr9iTo3anPg9YQzaHR8
1+kRHEg5h7U1uExMxcVyiiY2rWQLc3mDp37Cfzs9YCpsQAQ8VbnhaC3uef33svl0UW74/fAKyhda
PSq8bGE6grAlKon3odOzoVLoRIO0i37F8biDmhwfe/w7AcK0JNaN7aRS3eekDy4w9Pp6G6u7C0E+
xdq++l/TbwLhpOWj2Ogt9sjuqMD3L1yZCUIcf9EEh5YTlHX4GNzeOGKbypzQItopPZl7LceF7Vqw
Qq7601wLQy6kmJCIfZjVusZ98brePrFjx/qy+cnwIzmPf4QofyefPYoD/tK0JBaK/9QzTKtCwtG7
z7CHiz3rxfeC05KTnIzYtsNZZjrWEKNYPm6TeLUoKUIJ5ypUlO9fdlMXh9OKfGebrBev0HedgN2F
qDIswDYhJAXwS3CySlUK0tSNgkv0Wxcmg2fgzYJV0DIIemhuwOlZl5nDv7gINtpehHCbz1Vy4tA6
1bXARXo6qKtFhkI0og4Qnz8hLdoOCmTwDZF+QizHhAssp48cwZAg68xKuYIXLr1KjEhGKtw9YvaB
ebLYNbScUydoZbOBM3Xl/q6DVWW7nQfvxdpcv7DvVHIRBvtxrEbaH8APBrhKiTE1jSenWi3dQTk6
8WWtqF2kFNPixzFgeYrCDQhBMEW30l7g8YzWpkM+basAkEGuQXdHyWDH/Zyyy8lqzmTN+Owd77xY
/icgU9j0gf4K8a2tVAiE7jEZHPuyGRje63RygWHy7DOmrlMHcO9JBwVNoU9LOHMxbTwxbo7iCMnn
En9ys2zgvOfgLNwqW7pYmLY0rIeB/Laek67DEwPPW6V1bNb4OxCjrxQqwejdLdS2nWM42DcgNqen
Pcjka+qTlEFNOzY1ZvxUX6IEb8tbJ6wsbtuawwnFX6pxbOIx7Sb1ywczKh07+b0BRNWys3zCXJN/
Oug9iWdV5knBmTnh5U6pJemVj9jftQGRNCmgkkFrV93F+g8UHCVEpJ7/9T2NN8xzK26gF6BtDXzs
zmOMZZbrN/q6atj++AyM6OKlNPc8iUpV8550duLbcEemAoPOnu094W6uPAumLRUUvrlsyj8fdHz4
N6GPc7O53tfI2u3bvQJ26Lu+6hkkkagH88Kq5DjqrPwmrwIGacerIyiURruYx8frWiAss7jnAoN/
PuId8nI352XK5b2WOpvX2yEbRvrC8NPfvkTTypHMgm+cwEjDGHAz9D6BFTfwD0Q5jfzE3KnjXQjY
mHWFD1wl64k6TNY4Be9yYIFWE4x6Q2WLg0e8Mp+ZdUhIkDvNL/m6ZMmcNknKhFTMWisMdF0b7oLm
EEmTzpMd3qj4Oaw/G3+Oacm3a1WlIepMA+ev9aZIFIOvPoncpF8hjbPW5JP8CupXOgyXiIKgyu/M
X+I9yEuA/+TxSdFWYUyvzusOoBGQKWPcn97R/tKGLRDpb2tTE2ZA0X/zjtaWZ6BicRZ7CzSJX4Ct
bCQ11l3g8kwpNwWNMw4jNpGCebwk85fXpFdqGyqTDY1dp3Em0783k4rv7giYVFhpa+qyAOqakpvR
lz0OmQV76yygXG3EwO2E/7lXUdhsNSO0CzYvNsjryW2Cd/7hg6XQR4NIOezyxYmM7rvBrrF3hJrn
tr7AA8+Ye8xiljZ+8XEIZESKE4Jrq+qXDkmpb9rMEZHEZ73qTtPU7FrGrnZzdp1ZPG5myK8CE94O
VfTe3Dxs7ECFt+DGMhWSkSVql3j9mrlqUIj6HPNu0NkyysFIiGke7Ef6kIIJQWJaVZj0R8Kfcl65
CvsNxLh5+bBJOJQx5gnR3gBNczxxmu9NuSDXmVXc4sohECHYndGulH9U02n7I/Awk2yHOsmyN+vb
az6yKn6jz1zDtqq0Q4+aln5tTJNYQ+ArYAUG5dhOR50XYMNY4VMNln9dDknE53E10pGGTPEvt7G0
GsoTKAK46bv/MuAzXsUshDSUsn6yWsn2Vam9btjkgmWHCSxVmR4RQsiu5rZhthFY5WW3U1zhliiJ
aT4+ZuADWNz/cZVdmS4lxaT6JxugAs7VBMCbT4FA0WcmqmptiWEDgYfTAHOLVStHDU52KWdbER7+
JDU2d9+Pk1wjnDW/jCgVNQ8wM7MEVYDJIVT7WbzLemlA/zbjNRLjZo3zePVwFi00FKFsYP8hIU8e
ta2RK5vqED5cLXd1VolQsJUzkw65EsUlHMo2hAsub3UuxdIk5aBlocu2OWlERafcpmlZeb95+9+Y
z6In4Ob1sl9L80c8zRmdSARiEpw0Z4cWojpjjseJ5fRtwIU704i93egLSdIfBwUIePrjwWeO8Hk5
GsKriQHbEzDmhwEktQKDyLjTyY5ia6GaaYtg62LiX7016m9jYqZ1xVm2JkKj1UR5d9WXF6Ehu7a6
DyginRrF42CfuqJSw+JxVeL50KfC++9Pl8TA55qxsXFq94rJtOphAeAGG771B9946w0Qk5DUfj4f
w60KSj9zXIlubH37uOyLLwgn3c9TVMkIoy7Ue7tAXbXR16rc8/F7Y4I7ry+7tU9KUAbGpTOlJxR4
azdC06e9VKNDK2YFI/8xnZmRwEmOsFGneDPCnq02s61y73Bgh1AiFwzrPg4YcuYBAAdkWups7Jf0
+mpALaacmO6uYI+LHCjfeOR4rsR/t45Pi4wUJWrL/EYHojENJWlTF06TtlcUbyQvzr7jGMfbx1DM
IaFgeg1hcgp0XuIwTcEjdw+W7yt8MUn2zFi7VX2+PIfzY+XJKynsX2g2e9guZ2vj6A4OAPMDxmxo
k+S0Mt1zp4sAMKWiXZcgGnJqOl+EkyymKh7j+A3+gyQUlfhquIq1ljZEemFQ+DZkTE4drZ01gG93
VmJEuaf4zYljOqu0+BUZEQOE4pUriU4/7+VKqTGxXW6DHG6M726yL28nbulOPRKLcqV/x4UzX815
4hAnfFxU5L+IOnN5Xm70K1Ui4R2u9XPnMwHVI4h1nW2zUEgyGDMcWRc16ry4TaDxlGNQ26VpO1V7
1ikwqqNSWcpmc4u9L/CPX/bR084u+lUUzYhgPeVfP8F8VcbhmT23m1ENv2X55VAk+pp1KrJI1VDa
XtJtUjC013WRv0iNOiTuHzG8SXYK7h9uvf1vP/LUzuF2n1awWpoAQHorYO9zVcN+e2SV2F0mKlH7
2uhjk71xcqzID9HSBRutAJMTjgU0RGGp10sKN3a9ynkE5Q01MIrp0dRKuD5ro3hQtQdkdPrXKZgi
JWe8QBPM08mOWeXjy1AACqkFt1THu+7MjClxdopu39k9oG9HCALL2HAmq7qnsbVVobhbUcyx6lD0
SI12AOmB3g27fJcgzdlUQw6w7dRIH0YzK43cYyHLnC9sbbRqe5eG/2p3l4lHWpsohoqmDeBDuJ4R
vBeJspUxgW342DZ5bk4FFOv2XFZtPnlEPdcl485Wxy7oIKB8bHPPyd0QofuyKSU7x5AJLwIsB9aT
jqdb1FGFIyNJ2N5ucEHCUaTfRO0PgFTO3mYwXqe7di6gRFHxZtLD0ogBxfaQ8/jFdqQCMLFmETvP
HSl1WFzDTl3RiE8zwbhMvtbt0l1Eqeht4caJbrYHeLXIUrAaAktjEqal5rVVwlxhXc8K3n5Kraxi
O2s+6GWkR8v5MHKj4cp8+y574HfBHTAxTQDPqcpOTFkFxE8XLLXaudd2vmPaQauoeJPnJAjQwFXG
bDq3d+ockHiB6tJatYio9nP+1zK2JzVza2V37H9Qbk+04+EbOxPEouQ6qmmdGY0HoeP0h4w6GLa+
Ae36r6hm3w1En5d2AKm4CL7Ir08/aqnY9iFB8QGBEsupGYAZHwRBEvvfhaQ+Y9n4TQop2jvDy7SH
2Dwa39L4EywRCNsrcMQKPreJcA9T6bJfxrdmW9pe9XJ0GmPEr49v6oCXiJuY21/sDzAUd6ca1zJB
uyr7QZ80xjG6rOznLtDhPggSS+jz5wickB1tKHorBLCAM+2pnbhxQw/gm73+KozL7LcdeQKCfrdb
F+L3CScadTF2ndkL7pcbDpWTS8mFCf5mT4+UQpq5AtPKDp/ImfrjhmnKaBTxj/T0NBNpkttzZn+P
I/NqBx9kEIAAMJW/ID7km3v3QOhO8H/I5SKikOD3UO1FMg5vMdi0R+r8NiSrZ7XzBko3rmOFJUMP
JEDPmktp7TVLsYxp9qfkOhkQPcVWWomTkTPaR3PHGp1iW47Pw97DIMCyPPWXoJrZSkjp9wvNTJqw
CocPAhRffkfu1XVQ74GOw8NOYq7R8CBG9Ps0ETWvprDOJ9y7jUxz7rmpAOewDmfSsktOWs+rTr9i
wvQfNp39JW1+C75INnTQjslFKjpwlIqbfmbXmVU/Vf0BEENllYzjMtryaVNADObEnf3zA0gwDPjt
yWkfeWsEYiLZKyIcjSy1HITc6PCZ0+9aBUlAg6sk2cs31D5BJu+MYOxaqC/iDirFTbLU1cfAsSpz
mX1gO+1FAducj9nwRfQBn1RfqLiIody8juZqTwo7w/Nq+hZ6J5YFP8oamw0Sxn0TiNeIn0esvIv9
q266ZMHylQC5qeSQHALej3AJqmDwbMEa7ZcMc6js+KSiDAW2QCqyewvjLKIfHCdkdlNDdgBrmC8E
1i7dDcopUP7RZ86w3A5kcG3p8EZEENkJ8SIQKlCyVbBCMQK4LWD0lITGhAOdKQGTAmehyGapyu22
/0FHGcpLlqE2GPeAaNRXUsUik5RqcleyuhVMiO5nHWV/vsUutd2Qob71+k/9wnGlKCDvGoUqNBv8
SQ38FhNSF3lCwizFHKpPeZFK2Ms5Ir5VM9snWEXvNwMmXcu+/9bVfFAMeuYAQc6YpekFDpt7CfCO
jbGKRowMsNT1KkhoGXz/L9LWwUblkXPDgKmBU4YA/8ceatLV0I86CBq4QQFtvX2UWH/YK9aCk07C
jvnvTRoDqReDPxXlLGIW/DcXlyPldzKM20xt/ko10FY7kIokwZ4n9HC4+C35p989KJvzwUoMnoBb
BcUERTrNUh6hLbc5/hPTlrdUGhMEf5W1KTs6L9xBG1c8Kvlp3O9iDt30H8SXnS7pCrCtg6Pc0cxr
Am63Cfv+IT2BXqUz/elv7Su53fsci3mjo+fmWU2SWOksvGYgAwJ+ff+r6Vv4+U3XI0qWP7mWEqcY
wT8B/Ei9RABEPKsT6MSxiGCY2LrCb9l+fZhoDBJVH0lBg/Aad2A5DoLgysG3WpC0a97pyIz5gUR8
udP/Ro0yWKln4iBdlkcIkBe9zjxhWtKWmPxavC9Nn6Cof20qsjNSQY2EM4IA7xM4Kok073BQWF5l
ldVSAGw+fk55ugzeO6KLlrE904XQLcyRUf/ZRrnCfBNz5ENaFno0dPduobYBo6sXT3jvNla2vaiF
E5bU9/6OqtgYjDQewGcy2Kx1IsVQTeg8tmIoKRv9BXIdP2QzN4Z1oONaZeLrrR8JeO3iuEjObI7A
CxevMZmLG7eNG1Q3WSB3eI3iiH8JfDQb6EnQ5/N/asi4E4HOHS4gC/Aor+gTZe7Dr9sXkhtBl0Dk
+tSEFKWgDwkF0kSv26oE46KxEwTMUh1dh32H0SE/7XBZ05HdLFpzWKmWOcx9c6BR+ByQaJpRt1yQ
cgTzqDNvDE98Olf6zgVTyTH8NizzlIjueqgZh7OG90/poTrqE2kMuG41sOaHQxj4T1jHmhvQwgSw
EW5I5Nh5r0hulXj09EiKzRfDmmqJVV7V9QRhePx8kCZ6vMx8H+CRTKRjcBCKyMY/oLt0mh/5nNW7
Q1H36JpvacFMvDK8fTfQF5nt/fyv53+dCmDHbW4VSYc/ov5h9YPxPcO/jtaNl1JJRmp9N32kawEg
9/Tc8DteuPrrHcWcyerl6fQzDrw9txx+6Cf+5+gUx6vdQ+O02zfAYRUVul126FCNEjHBy5MBAGBP
f8N/u1LC8VU+CM1Mm3e5RE7YkqgDmV/AguocCkPWPxzLfpghTWLU7nANahYrl9MluatM3Pb/sRVZ
s8AgHnSZ58wGG91EE6D7zil7f4ovyaBlgg02TufpQKvuwOFXCpF1kmwsmdvSMQ3j1dS2UN4neKJ8
gNf9LefbfIG61dYHQisKSP8dsYfJyA+KL6cKUh7ENY1fVHxKKAvXGy3S3tK8l00u1Fyi3nNnY3gk
5CMy49b3cBg8qDjmsIbr6YEtWPN3z0Zo8jxrCL/7JXo0Rx5l4KvrK9INza1bOhpaBtIfHwYFDBlE
IleY2I/LvYeYF6H0NpAypkTks+kH9aKhK9R+HumfL3WdbNi5NRqYzlg8Q1E/pmO20e+vra9unF5b
vDGjjtb42nTx1emnnvqXqHK0wOpdxMyiux3PWAQafouDru1ctOQOX8h6y5jMNrP2Et5jCUagfuEB
/gs1heduLisb+fWvwEy0oD6UhO8TggkaFynCzinI8xV9zItGMQCCb3tLDlmWKTL9KMPY83xPOXG3
j0HddnRhGRGKRa6jbtLnDzoNburhltzdeeth+sBOqFX1gZz21Ks6NIOJm9I31HtRbGmRJ54kwfz5
ZtI45Qef0jruvjruXalCOtRL/WDMx86xh5qRipO/9K0nzryUbPjDl0FXqlRYUV5vr3IF5nvt9E1T
ofZvQi/djdlmxnEfwIxOmNcNitnv7Jb8XSGwsstdvB7P6ChFMZ5QIqSpIfnxHD14Ed/X500HWWRP
hh7quDb8cedxvPGjSAM58sfQ7BSJGTKRlJEB3RvhpZfQbZNlHilKyjsbAdN/ctcdqhOQldFUgQaK
NzxEIO7xOi+22kRyGcCbEmPZENw98bB8FC0AajvyN4ev5+9yJRACfK+huayLcT0I9ZvZkQ2FlinK
WurXR9WJ1L/YNsptbiX60ivgqk/dZzpbIDf1/bAB9bmBaDN/37qSHDkW4u2XtSEFhZ9BHzi/gYh5
gNzCzV24RIjA88pTHZguyChCrA6Ma9fJWPAZCI55+7dd2P3El8+jXodANbfkVRH1TVZ7T/cnUt8G
/Ke9v4X8aUQToW+G2dlKZsnqyVjqa/EduWrWcOKTy3IqnHiZ9NRXFo4dSQoJzadVzu01+rx6pSJz
1Jk/d/2RbuLaRLNzWxBjEPbsgeW/kLwIABsGJX+i2thVRYly+215ITYz+PSbHDodP0JCgJGOwDVu
woiBZPRyJ0oC8UqnJ+pnD2MEUNk2lZjmz9zzQZ3s3eLoh5Ur/Ymszb9qzFzZl0PcgN3bGX9+Dapk
erN0KFM4ORIoXBa8R71i7lZL8ZeRuoiIrCQhhdlfzTwwaEv0kxZAnMWPHXJe2SXV3K/kqR61sv4f
kpaw9R6WL0BBQuNiE1GunO8zYqUXX18g6h8c+VrkZOlJnhoTyMr4J22lKvDHlhjAEXA25EQ0E5lv
ZD5zk2/QdbWTo+OYo8uGQ0MBeXRW/8A00ZrWMivosQWM1Vtc0DsjVEa0HC9krTWvJeGutNeXfb3C
Yo4Iv5k7BwcZCRVhGuXrUHhBOx7+c2X8dBewOXEWiLeYGQ4lEqU9l/SmZHjWpqYDUe0OjWNhyZtd
apv05T66JhzNXf3tatFazZojaqGwpax5EopQGkc7GtFXf6SNV7U+r5ZCF5xjzXwnUJQ9uW9s/YEJ
kD3lsiUoofZW7IGyS5V5xT0Vq6a5M8NipcL8AcJXP8UMVHYvkSIv6Fw9mfAHTxG7j/I0eBa3fXyk
yBHqTefw0GT1lUyBWcmrlrduEopz5ff3x1bDhEj4IWE0fv8VEdIA3u+8sMmPbMvcMzQFQMAmColG
KntcvVhAkrGNFu/wz9glT9hDOz/YOL1nN4twkUqH2D5n/+CyGfYRGzC91YETD3wRprsChCBNOIIK
LeoCgrJv4XwCWuOk5b9h4W1m41svN+VHtrxCRmUuH8JXAMgMgtwNoqynQy3edWwj85MB4WCK9/fj
UsU3/AnznjxNB4kyge621o4qO7+/dnnxaIcxKEqyj5FPAQ+lIO0r2pmeNyIajX9FyC7sjV2Jk/pF
aZqR7x5THuRgXiPvoI93Gn/OYiU3oCzSDMsRrZczAGtkFGEndj00IvLRMm9CIbvrD16d/Y3CtNjM
MDG45/J1uj6lEaWn0lEzIvCQM7PJM7uliYv2O7MR7Ljult9FYakBMlLUg8sj+CCyj4l12Z5KibN/
uehUtKRgpDkEWJy7hZWnRl3iydzZSVJjRXpjlcgd862Atw4lel1oYL0dvqi7nUDgbhZ/CQsxbzuP
VgssNZXQ74fQXNFA32ES1mtU7m/ItcuNXw40WbE8PuIx623lOqdugn106FQZN6R6/+gtTdQxM3Lq
7eA122Ur4I2bfkbfLCMBjDPaG9jCDzuDJdacOVYKiiSLEzabZGUKsEo6wvIfjuIZVQ9YIlg76RFL
KRlQDtotRHGkdG0/GcpqVQrEkAbXFpios4yh+mAvJc1u8V7FFRtsJBZRnoR6a+0OsL3rcLxoxeZU
8YUiaFxhW0Lujd0bbmOd+efFzvVDznhcVUNcSOWw/oMwJakna/GtvmLxYvmV77xlua+l2yVLLUVT
AToQsU62zFAqVklDTIaXhvSS0FuwqWJb6A/PBo2nOIF9hhrsaveo6WtdKDdYmpKOJscgBb3sgWoe
9q8u5EbIh9sKNMxjRKjnirHi2E/NY1Xlt790SAMweLS85glL8qtoMG/aZwEgnids8a3JdeV6Wg2i
dto5EAQ2nTQVA4qk/ZxL4BmMUlpKOWnjd4NRZYgWtQGk2pQPT5QKDA/KqVhKmoX7X4Did6e7wtPN
yhJBYglsDAzNCD72iKoBpzjIrPfLqvr5t7PmK++mmkqiPkMkRdW2XmdwVn46MPmnA7jn5azmtuLY
MGLBZyzov2KHih9KqDGfEhyfpmdXS7ouflITOdT0IVdCE4gdfnUuxuJ0bPN7/p4UdAbmfdaYjO5T
x+9AC1E1VOGeRy1rFJw4w6oGyqe1N6KNtTapQpawYJx8QKG1JrNz/+sp9cXKhU7crsidJztp+DVA
YRbxT1izS7518NWbIU8t6dbMQ0UFpUpQmscJY/OC2yafL0RGGrp8JTe9g5kkURrNcSbkMharcgDO
Dl0T/k6o2cFiHhVqiAoTSICbDIEQex+HNf/JqGGcL5D5Wr/XCQiFarhSQtjbuO4D0XZ0qipOUfoh
2ZU8y4iH9Q190hIbB/CHyUrT1TaqJpb6ZM+6fVhU7O0EHGWqAr7pfG/iKCQvFSRYcBVizTrBsJ8C
zvvRKnaT9az155sVXsA5v700rntM4nIJKf9MkjrGVXx+/pIDM6kD9CN32wl0FXT8mGluMNaJRN6o
iu0MvyP/gO/tBCxMNvG9q8ZJh8clRrt300QN5j0GdZx6/3JN/CRrquhhau+zQguAYiLkuKbuQf6G
mfhHjUAikhW40EgEVk6V9JxgQWOufISgpkLwjYuePEaBKBupJVuiF24bD+XSof+G7UC41LCpWkGV
jxYoG1ltW92ew94Qmc+ausrMDVjCL+IP1XDB9K+LmjMSDa8KdkKcg77rLZZQTw1xP6g4SvELaQvI
f5S8M/W8ae8aoS/JzdswDi0IFm6TDdYa6TZWXBX+bFxb56pSycxAVCHJL4QdZv/E1glFTm/DEKFU
FCAYx2h0K2h/nYYcKP2sM+61dhxU3ouhR5LnWWfkD+RXEZu0fVgqNroMKbZNIkGbjdvgJCcU9o4Y
1pbv7xjub7F9/znZblZNE1Q9C+b+u2gQI1zhf+RNXYWOHQhGMi1o9AFABhknmTRi9FEqJXUaDh94
Srk+KRHwRRB2tY7hLZAny2kOlkZQu+Fw1HU5Wxxjc2zh3x4oFma7aqWmy4MKpSNRbex6dqvxwjHU
313wbC78Cq39qSHHDHod/ARjhBScK5vUvae/ft1JXkpvMF+s4VPpZ+WnwP8xQAeqig+eyKA3gmAH
8S3deXf8GmToM65erw9ixbpH2iE2m72Q87Yl1l5Qp5YPffbedw+kdRdEP+guXxTzr5zMdxkXDJ+2
n27Prio5yKTdvMPEy/6vNwlM1+Nd06M2QiDnP31ng0ZLAGkMc0rVlzkGjTwmvp4kkRa8y+9Ljb/U
31AB2isWMCpWDXuX+WVfFLpTjBuek+KvrLnAP2i1LLE9SBVo88EMEAhE6F/4cM7nD+Vq0OBIXiXs
E2TU0OyN3q1LATBJqRlEmeG/w+Dk6hjg4SQWr2qWuGppaGENEmOuKOkAMQ5Bu7+WUzNtrYbGknht
u9MJc6vc2a2blZPi+8GYnhdMNICvfPs+SqmxE+zusSl9f36hFsB1YjbZogYIw3f1pFl5ygdTvzMl
GXfPBlfF2u55zpDe3Rq+d1Ci6zK2dfuXm04gLDFGszAKMW/dVV7Dp3UYedmIkVP/5p115BUx/4/k
aC3HqFiPVpMR5vOy1h3DmtAlCjVsgtp9WQHNIanH21pPZksPdR4Nw8c/1ZYGCiGReqG4m2OvU751
k3hT2dyCcurh6WkAcOJ3PYvg/Oc6uC7WYgd6xfi5cqEBTRtaQcsByzNeyjsCClA6OFSoyhlj96C/
oRqGynUW5mbM20i9fq+XGjObKNyM0tLHmCeUZcotKX2PEXDf2v702gMmoi8YnPpN0NV5FxMUvf2o
hwyC/AX4q2ScU1ph3/exI2BnBOj3keIqjX+jNxst4YdC6KJ2ewbKIdyi5qIlaD5oLvn9j281sZrm
fyk/gnjIX5H3Hw2MZG8B8AOhD/BBmCm9MMvk32ozWuhq2EtyVzQ40PpK5M5Q/zxuWiGENmH+/1Cf
zuph6ViLg55M1ofmF3zlPQLmMRMAd45dr6qj1/+mw+FDpQgxBZoniRamR0RKQUzXJ/mpXwANrGLg
nR+iLFYUPk/9gPoXcRsl5juw/AoGEHAUFhYFOGH2VSz2bKWVRFlOJ/yEMuWd5XbX+DN4KKLMgHfq
ngCSEXuOhTpLszK5b41DSTEwyf85Sz9WoHC6z4UTjY38uz0/rGyLkxETSVxzN9B8tgCcKkmuj/rF
U71Uqk3PJl2E53HZTLemaw2s4erXZd+TZ/s+abTi1H19gHKCxXGwmhsFZm/ke8m1Vaz7feQibx0F
J5/v0ucrcV1pvSr49CHBdkhC6NzgpHPab1ts/TXPziVgmAV5VWi6Q63O+2SjSR6YOE/1QGB8BdyB
xZRiCNjWWRDq8cw32d3j0q4sXcXTKt6rj0zwvT0YgsIx2jJOR7b+x6E5HdWscONR7GKpaool0lnx
zUdNNl38OXypp3q3ktT5wpVsGpdNL6sl/Ebix0PlepT6XbsOlaqzIi5RAro8auFcL8Mh1ulQHYBr
G1iozRUcVVG0fjLL/U/bJGkwYxNLBlFOt3NtNvcufPJh0HfDdFRrJWxKUmkgL4N77ig4gmVywORz
j53MojfAR6B5GAuALgvh3LR+gtI6dC26SKJdTu7rOQZWYLZJDbq6j/x5nu7YuFze82ENn/QSM1Qn
bJ7Mrcx8CbtWwA64jsUgofdAF+HCcew8u/HTL1ibZFNbHTWVTOOl0luq3ebtTTcEtd26OoFwnUQz
4uOVlsK2WN4QpyuULabU40I+2pTC/kfEbSEVVNN7CHOagRW1mYXH+uEOK6k50sm9YSg2a40fazC6
ij48T/PMobr3w7hIm+78Nq99dzRxBsMFZZASknBqK393yllm6ynUO/XOT9kezsd1meIZxVEI2SJY
I4J/Zclj8Q1ejJ4tfr+MhbuQ8UmpJDSGDdG+k7ytGCVsTSSFqUJxxCnp/BMnu218aL9Ij1x0Y0kO
boaMM+zlLYPs6poVQZZ0URHoU03+hx0/N/mlk78fYVNQ3oPRBu40TLqNDZGJM7PEcVU+e7G07XgR
FoNwjepkKZTzW009KYiMoBemv64X/oCKwYhDVq3OGIzsqdT6ZDyadYNecTX9Q3D5Yei80G+VFht7
9NJR/c2RBXjVVG/WEOknfMVxfMvYx3aiyMdNHz7wxudgOgcjKDtTGnxJcEFwJp6ZmZeARwhj05FO
3xj7Bsg+8OAHwODqwI7XGdOGVGDq2HDJpQe8k3dXSodQ06NmNULUOteX+gzuB/m5CSO9Fu9i5mCh
Hgkc3ttEN/xmAdUKfRpgCuq7DDvkVbMP+mwK3FVL8Qzs/nNpWbij8c3PKnki5RQRKEIbYbBIS8OV
OjqZ+iXaVRGkrfriTnSjdqtPErJCuZksvI4XGWgo1sGiw7AF6fIDOqSN7yX1u3eg/B4Zch3ojhP7
GithoxFaFoEeFXg9z63oySD8F8VxFjJFvDWJ55oUDJl3FirxDZGh1byjA2o78SoCxtv21wn2JnZc
WlGpfkED1vlm/tBZrG4Rty9B6pDu88iN1dGuTqF25p4X0uSLWbvVh6O41jUSeBsyDz/ZIJ9xfw4J
aBMVOB9Z+fqatUra2QiyDHMOzHHa8H5PBFZWjbLp1C/rlljvusYo3qBOGnyJbspe2hCvp1uMM/Ci
1GbGQNGQk9ZxvJT5qX93/CQi3Ds1PFpIDCE5mqmwLzdH4BKzs+n04B2fa2BRfTx5a8hmp9sga4W7
iP4zkvq13b6dPnUtGyTX+Qb8yfZHSkB/L1yDrszWtCCam6Aeu4nPbsLAHvsK/Qn/gzHRvp9VoHOr
YyKQTzXroB2XPY+KSO+n7t+se7oNzv36bnRG1g/dw0Rl9JHPIZRgBm1mWrzs2gYeQibhnnqNIJG8
kPqn447JmLAkeOr8RipEo4E198O3qmG+0box7Chm6kv4+K1v6CoFp3Cq58dqO6pFqN69cmrNrMm2
0HpYOkC0ZS/fxjKgoXT+j7kUiNew0bjdyBGThdcac2aQJEyztqe+sdzWkol2cb2Xe3gdqFdtFuHP
8p4LJwWzhds5tDl23wgMItt+GY3rlOds+SKBvlE0VSuueoqx1I10YXjasBDIgrpqldE5sG8F9JRK
DX/7Ub7Qnxr372ytvHGd8J9jGPAymCdZKSEm29bIfZ1FjNUVp10wlbYkRr2QIjoT4MmhIC7LvTSp
GWbxdtCBNYtj1ovTOXgpvefZAFSuPeO/8e+JI4j/aj8p6YlH0daBD7MEW0lZCa47g0q/08UDxtaG
HJKIfA7qEg3/MyyxQ76bnOIhEyWcWSZB7gxm4D1NXlzogQTkThlNKYx26BCDdfbDaOIw5Epq0lMH
ZKZWbKb7l2bAyTkhFdnse3uRF7h3/70MG6iBZ9Cow2dk0gpx6lwbH8N1UHVk7WgDxCKYONkMlVHm
SbUwFq7NQHdgg7Z0H2eQGGHRZE3VIplXav22dCX9K8js0gZGWolDjbIxbfRQK+6sg8Yx5XYhDuor
2OkB31WSvN2bXpuOHd6vUcWPRXZhx3hkyMiSMjXVIXtr3LtZryiD15TTV5HMt/w8vKhnUTB8MmRI
SPIlpE/Y1uQBKDlkXCH9IofoDST1wgFIWwKLsY1Lmna2BxKFeUFx5kEJUSJIRMGCRenakP8SpAll
oDOA61YWnhCOP93mVxOPwaIcMUDPXlM+166Hl/HM1eraDy47iEaEuHVbitS1aVvzKlFnvteZEMUJ
VJV5+RuahPljAxNQTgTs4E2MsbrcQfeM47Q0nETMp/KkftU9dRab8TUFZL72/GUAPLDqjNmE/1Ny
IdZwM8bzCon3XdM+gTDIINzlRKStuJMGmJdboCm5ELDsMFpt6/lkBmByYAGDNvoqeobBvAPBymU9
zSqo0Er4KUPA5NVlHcVroZoaMjO3F6sUf21LIkSTFTcftFSlpeugRFgFpQ7rfGrjkKqAiFhEAh+9
1U6eeda5kwlsx3kmki8478c/VHHEN87VUo3KSGwdGEopey9YKruBRdMJgsesUVAyrmXX1uTj8+5Y
Ea/psoJJYj2kVdSaEOQOVLwlAGR379U0zAvDme66IINbbBxqxiYSjFceeOXezs9rST02zfB2HQa0
HUojaFiWKsGSaquR/pXCSahRqkYls1ikXBeSl8OV2nTb6CplBoBhXAVSaMBtJc4ayUfpJwpxfxzz
U9L+PQSOIuYx1GgbSc9gxadPLJGcklDs7rbVrn8mPXRK8bNBd8VRVlVuIkenrumMR4qztNQpQ0Ft
53EArDuZRTGPYNhlaJqhpvpKn35evmrjClMEd9TMPnCTFtQpUbBrZSAEgc4EBWqPodYKy/3NkuYZ
5X07iyzxb50y8Gjd8UsBKK/nokqSfD7Xi4NCst/GvjPjUX12N6gb2ck+1NGaW4+4jNnoWpQR0Olz
+17TZcUen9/S6kf6NSMnkot/EzpRzBG7rzo/3rREk3hJoz39mUd/dT013Ii2+L4qOoT/mQsUkobJ
ExvyAh5Gs/VubpSaq5COFC1LtUN9TpLLNhuPV7hiTPlMcexJFS4D4iHwloDVMR2famqGDa4SvmHQ
xN2ziPbNxG6fobXpK/9bqTwn58D/FgX7l0bc23eN9X7xiSYhYtllxVbQ6Ya9SPDN3U5xTiV8e9r0
FGMWVFJh50vGW/Ug6dPK417UP3d2GNmZW4MLeUWxSBngDwbo06iTNTMdwH8IAm7R1Vvz2Yep3gwh
EFCNWAIfCj8B9Zi1kpbfodKH2DlNw7LcmLIUoKm/TYHlt3TooymCb10x8by5eB8rbI4wiZZidyFI
6uU+9MBAlFb/bFESiMUGlNmXkdWiTaNkrqKJnfHuZCD5YhJ/2GxFJUduuntsdUef1RN4fT5Tk5mt
8SlCloFh1mtYX20IGvhSRJzCDytLd5ydJMVzruw6RVgt6cmi9BOM3sqSsIuiQPYBJVHQgd4aR3uv
DC8gVE0apAsmn6ZN1nlZEVv+dYg60+X7JrebhIxbQ2QCIZku90ebw+xobP+oldvQpHJLxpIMApC1
CGZn4WY1uPXeQbIBrhANIz6XZW0Q+G4xxxRkCkxcPihrz+j3hkmsclgEG07knCfbNFOysULlh310
TrNzXMdWrNaL/I0OdM52LKUcT268Vc5m7f8IuyX/YmNHfM6I+/ZM8C2dCuh0f6dySwUj3iNtIwGs
macxgIJqTiaMxDVyLOZbYieh4y8Om5WVRuBPuPK7W9lGU+ja9sBB5wEdRzEI7AkmeKWvFLg9KMw7
BwapDp0AiQZsLEFrvVsLkDuLU7v7d+/To0EAb1jtHAQm3znZ0/dDnyZJd70Lm7aZ8qMrMotBbQ6G
nxQ+IdeQQZXX9fau3I+SjDuazCn6xhaDv/DaFmSWyze/KZJCLSvTbnV+MGs4nevfCv598apEE3Po
90zaQMHGaOlowo+p/yEMyjFFGX1xinWYiRKyjK6k7cYozskd0RvVi4sPA+qhCmhc0Z0DVuVhz/wH
ImPWEnP3PQMAt6ZTmaQbpDseZ9sJEzhm3hITuewI6/fzG0i9TPNvAkQuUnWrBwe60AAHbOo9qt9C
PT5SZXk5u/1iwkGeUEiC2fw71zKxjksSx+GUg21SaOZTriudJeCka0h8Y6Up0L4pZv8MdqpEyCxH
wB6ZKDpYfgiiwn/zpCbzHD+SIkG4DoCaITSyY1KXJuEtyLfzjEa8VI0+xCg78pCtsXtYf6D2b+or
5n/qPtF5wZVNOpVySTfJEDQpstROCCGGf5O9NobHPWenLDxZFzBGKZZuvHKnBGkrL8BZrzoJFBi6
BdwHfElG4jH8jRWITn7AYIpPhJgC731WnqG7drW0+XXNnzRfMOPYb+MeAIgm3dNP00sE/2jwfRoo
+POx1GBWnQWXr504efi5Si9czzAZo9B3cOxCaoWy0RQ4XmBr3e+XvstBGFnlqNPQqKBDPE8KFy9C
oEQ38qwFFJ5V9GpDXG4XoAd3IcEgqNzzuGNc8drpfHXn5IjeszwSqGu08n022LdGfKQp1QgPchTy
ZgNFr5cUjmErZmykm46ltTXPQ1D0gcjskh6djbdwrjuohJCyl8GZcYoeOpjJRSf9zb3QZRfrmvpp
jc0uVraPEE/HNfctOtRu528NQoKHf+2ElD3FAhwQ1HZArT5s/qrm/4BClcWfjsSgmgNos+JmTP9U
4EUq+F80PhOElSgChm2s4O2I2vwSuP43iMPu1OD8x2TJlooCUVUeUgTTQakIbKX+NfN7fwMawgGU
XJgvnLWyIPF5R/1g6SvmAVI5L/rsGuIJdXluR1dxah434NO7flgGEuh8yRbsxKtxdKVv5RDOK95A
FuDFsonXSXfTuNMaEJ2YNg7h3vcOzeLVZWTxu0NElfjqYCZ5QqYOKLVMhfTTWdDG3LacOymcTJS8
3e0rkp9jq139qWlVxaoGu2vh+8N6/+W/NyTS+/L/z/KXGphN5u0RuvPGIZZeY6jK1ert6IOQ28N8
yH9Mz70yfe+CRdCJgIYFRaUEDU4eIX92aVXbD2Vrhc1+FYJXHdjoIts110FKy86XI+zyAQxhTI9p
v2r0vfzgRCkkUoK6Czg43aJCFyEE+RIzXhlR+jiUJOMq1jyk+XX6Oj+pSy6Rp2WBDVHqkZAp9Sns
AkApXG/ajA85sgBLg94J94AzJJEtBW0uUlkPHIh9ZfXByNFF6MN3Zs54D17VaKn9G273UrR9rCyz
UFpsyr4s6sCpLgL+xsWTcMqoxva/NhguzXhfP8ERJqlSvkBt4R8GMUpDCzqlpAlMsQaE4tdTIA9e
P101Yy9qa/Uo0CB6infhmSH3ODBw9G0/0tWgqbr3EytEVcDhYAMt/E2vpHJZv7aVnq+z34eN78HS
NN9aAxuvz3eLBVzn0sRK/PdvZ20ApAA4uXH+c3zOIhzNF1W1K7EqzAlYkNaghx3rgLGw8cIdeE05
5BJXKPTX66x4oHP2+rrkUDw9FDHvbaLvlxYg0AdouEE2ZSStoASF+jWrpJv4EmedHxGCPtFumC1M
+/XEmM/oF9gr1giJSzm6k0HqP4Q+eBb/6hgQShOujLpSAnBwvK1j7RhJp+ExkrNMxqsZCJ0wmSzh
tHWscF+HqD7sMeemopvghBQ3uJfL7F6ELWc8Axjfx3yoR+RikJ5RvTwaDZLdHzy1hF9SaKDqwL69
vqfFDMnlIUp3gCH9nhhFOpecppt95dVGL1QXvcnni4AEjfejLNmwXk/N0UvUw+oHOxp7EEK6NyVI
D+xIGzq2hYSbLh6NSr8XMDeDq9nyK4FhpLV7b7LA0bsscN4n0lFRcgM6a5nH9YZOxC2JOs2p+IeE
ux5N4byAXShNtJiAr8TRetlmY4Ppe2DBr2Wi1MLKJ91Wkx5gEqewI2mk0tQCckvM4hWE5cocalZt
dXZo3wxg3lhsCH6jsxDK5jfCacDtlfxNjFs8rhXaMEUUDhB1tHxxTt54wnYL7pLBLcKBJ63kgSUf
qLCmpmBgUlMRLaPJ8gOjf9MhZqBlQt367FUJ00unk84llHm6zm1+H7oCSby8j75vwQICU9QhZKZI
1dfmLXL9fxQSI5zfVnJj1HEomw1p6JcE2lT3z0SgMh9nKa2p9AxZA0yhNVfXIqIMwCFTb6ReG997
B1eImeW2/iFskmEETYJVA5mTCi/OwOZkjp1RJ+QiMrg3Z6y0Fq47TcFhKDzTtGOE82koI6lsL/Ww
oEUwFQVCXbNGMjv2sFVK9SQ2S+y7uSJnqUBIuSFm/rt4dkrAiixiNZ+cCis+Zrn90EG3SzWXKRRM
lrUNuYIlX0onfVpQ6RI+fBlnjuCuoSKrOesvDXh+kgjOezTHztoXD6wwZvF/GFTB/Bvl3ebBmHel
NlKZqSEryVCgezgdbnHRrXD3fr8T0EjRKM0fWUhDnrlCuqgaNfZla+7upFivwtqYAnAFTjR9gWtD
fGKMUoAbDqyTaqMWouVEbcJ1xxuOICs2CS9VL65qUcmhKV9aZMil7PeMnyxH1QIPBbKjLeZDeOzB
QSzVxKu0m64+FklhvC7DUCqSxC2iHcuYbiE+XAfsB3lcsD26kAoACSJYcaoT8o59WakNoQ2XHMCf
3XnVUbuOHqK7bSUSMCFxi6PyEehvTN6Aajk2EKJTv706GxPUqHArw7f+bhVQFkBKFL9LJVh0xJFj
LR8WCCZMi/4bEUIkwKdKPAk1q4e8LT8foxPVYv5r3K8DjetzX1bCAtzugmaIlFJhVJcuhdXQ1fw5
twEz6GbYOjtDMsW1Ls33S+fk7RguUrumYxKnLfBNBrmz0f0BAD8vHHCv7FQD3c/LgfpirWp1gUUn
XYMSqc52XkSLuJr1KsopMSNFYNsojiYJbSdvPRxRli/DtV2gyFcorWiOhzdg2Dm0YLhbDoKjBPyx
w2cap7upbIjZBMj0Oa4etRJR4ZZQxAaCnJ8bxabaLZSlVQ6tssiIjb/NfkgqiiA8WsPBwr4/eKMT
j5XRvikDCA7jTGwnl9pVutABhU9SoSg6ufQZeHjKXxINANygDYtXQ3P/1zZhgmz/jkpzOsHMht5N
xW22bGnsF8jmBU111J4MchpsOUSCmd3lVXrYMAOW5Ji6+Adn62dQJK6YIVHnFCAL1iefyjmiU4zb
aC3zoTuP9JSMAU7s+/6IKpumN/NcjlLkfFyIiZJXkSzk38syUZPPY+uH4LbPhaUFHpymY5J6tfvQ
0fLk6elsLsxHQVbq4zMg9QdOs185UV3u08fZAXxe9NthmUseVdySQdii2kcJh4oVZxmGIHCj8fz5
n4FYUDUQOzsxl6WlZCKO1Dj9kOmswbYhbQMwi44LFTmBmzp1Fp1dOR/LSxc1CPN6oMJHgHql2soY
nG/AtmUsJOHgofh/FRQMEwJuk8bDfbFHQDVRLOWLq8Eu+fDvJw61jjDpAfxqD1WrDN7q/itL1RR6
bfSVBFrWXBgcXNexlCYAFdjLkGj0Hp9TbiyNmTf8obKxnOqxtI+EXAoTysxIgWK2DPIohyxkNeiO
1TxX3XKcTk4rsJwcRE80vR1CQ39f3S15akzm3HyhxH1lrIdsF2FaFe1fosUla4+YccU1/UeEaZRe
eMe2jTXKTKahtJVQfKIePRQPVvMVr2JU4e21N7cSXUdrhbDoODc/MhbrlDz+IyGN/n37kIeEwsVf
b+eEIRGo22fRCkcG18BxACsaKoLefDBRJMq+N+mAK6E1KaBumuG5ZmkZPPocyHtw+irOEUQwqM2e
iCKoE32oe4kBTNJ3S6dg/aOFs44kNazih0cF1QDt/LQ5FNbZMYGN7vaV5lPyAdOeOxvWssEkI6i+
Wyns9LejizpZsTEG2f4jZXKaHOlBkCNJ9hBneUZZBDyKht8CQdYNjEq4E409YLGUVLXKaqi0oF7w
DO3g51YM4CaYy9RhbC0HaQ3P24pCY5IR5k9fRIJXpfpuf/3V7cSjN2AzdE6hwI9NJY+AtBEH5UqP
Y0NVlFfPKt8WDY5oEw1XXZSaCoJPdwt7Ccdkk5q1XZmNRglIYGi/CSXMkym2Wakx/5eRufH3yAbV
mdyWphPj5r/F365iCVhZkSVR3vz9O3Ajn4IEJZLIHjZwP3FQMAtykL80lgJxe0Kj4SNPEhD6Zd5C
CCWYE7qvt6rEHjHwZF7SISkvtAUV7OoqvRisAWhyVNfcrahDUPZfXgkRXPxsWTTVs4oYFXUMjjeE
pdCvBo/A+mbi9vGnAkvR7Y3w2QzKpyLAb/CLhdpNB5r11BZaNt+/qTemWRZ2K4mVwypE6eGGr81c
tGTyar8qarmeL2vKZ/6dRom256TFgStoCrC+UE/colUxvOaPNE0aj6M/yw4vxkGxzrT08scJvkbQ
IC8OniPI81pg/CtfUmKS9PThK+kuHpp8lWeil6fNvWWE/RbemHmQPKt7/w0oIjkaa6KI/HmcXuhc
NFyQIeHJiyatYLbq5MGL3BHYDJPCdp+pOUqnSQWlIapQ2L2B2DhUHtmkhaIQOf6uenSqdPuFqqhA
+i6HJzjmzPNpOfr44cWXhNTcffWSGGUTerT6/8R0PUDHMQaWOaUM+O8x3bXskaglxou2HkV7o1wy
mSOriigVK2y/ar4rp6ULcGCXD3yooZRMlY+/JzYkCKa3IydmXJSm0JKntAA5jnbrsgsM2l1XY1MZ
h4U+wq+kjY87cR6C17weiHKZ4kQR4cQwNwkHg2aBiEhTSus7hE0KBQAmoIv8oLzvyTWAVL5BJ4vy
eGLy4QNgs5It6PHm+upmCjBDo6vklaSAmhED+gYTe2AWnnZlHKdCU/l6YyAxD2LobU+9ChUT+6MH
YMbmgib8SggIukwtFkI+iqPhFY3NJoZ6QX7BDq2nER6bii7AUh92hLwXY3G7hUYWwIxJu2tIkEyj
RemT/Yh9nJ5SRI90LXP9/C8KS6clYvKqj+8rofpP5bvHwImbDfYsrh0dLmHthQBJqBVPSnMXKtYT
qt6wBb597Dy460ghzeeV8AvV23p/zAVHhMvqzZZntnNBhlrNFvdzkrBdxU2DMzefHKcgjL3rAJ8G
MTi4C7XTX8oWdjpIIZJS0UW3kAiVlW+4cYO0U1RtY5t/vjMhHuuPEx/v3xufCidvc7mBA/X7Ec/5
f8mXEvXvBnEMwJqKrGy3SbdZUKFbk2IB8JsLFFHT7f1woObMQBFryV1PUzK1eNHhfoU5j93ESHTP
zfwwawc7/zfg6mte0Hg7j6dKmVsuQ5uyaAgbmfmUCDwkZm6USPaVSssctEEQyMffYl3TxjY+5LtZ
EpNUfw84eglQvW7G1n3c9vSnk4Vmax2fezp7NQh4MwBP32jA7/cFntC9o4BJoPjXW/YLQhzGd7WH
mCq1yVyEEzi4vEIGQTeYIbM6V5ss0YTlaEaSymJTaPrpNgvEUQ/DsKoSv/1Ti7lsh9MYoD/CN9LY
PajB7kN3Ga7pRs069WK5aDoOW7KuIv0rpgOzQ2MQl9yBbn+9WxuzT5P4GkF6FmlEiX/MCj47qtz9
atFkgXiWsU4xyQLQSG7WaQosNBeE4kR1BmXv8B9C3E+izjV5kYZ0065m64IUniFy16tW0xXop+/l
Ikx4QjXEnzSDJ08ar1+o+8ak32Bt4QC+974DUz0Xn5wPN94qUhFehNX8U/KbTJTI0Mde1d9sWclq
RDGq8yIF4cX3lvH6wYtYFcailL9QWioaINjMRF90wYwD6dDub+8feqpSGTiYDTUaqgtw9+wqtpAd
Wzy9zPfD0dQpZb6v1Tl7sL8kZVYxBbn1pjNsP2Oz9W9PxW1Kf7RB3hjjiPsyudZoTCGpJqZrTBy2
tehA+autgvMmi06UHE4gEJ8HWHFdrhjBZCmLzRdTi7V9NuO2X5OUCE8cw2RVJ9screAOrJez1z3c
UhjBn4ILycbI/IATR/g6K3SS1SRp+Gd5VtwnckgmWo6eZQctkRp4EsDfVLM3tilMOnLg3qRrd0o2
gvnAZ1yKkINYw6QjdC0F02U188McHDXnok5OOkYcofFfPv7yvx3AlgiScpYQje6WTlBwKFHSvp1n
gvA1Qs4QzPbriV1TowrglhpgUUgM8dxtlAFqgL5iKM8t0KZpi+a1Bo8KQmmpOfsXETfbKV95rhf1
sjdQlHHplEO3V+WfI/hPVyNi4nuB16EBOw6fVD4PqM6K7TmOwPUf49gNUyYH7Tq36LEn7xjD1Aps
5PQeBKjWPYhOcNBLipoia3+0Mi6SHSTN2ryOPn4+77FcjTHRXI9JhtUZZKRtTipgSCiuPGUwgCrv
05XnGfUAQCq6eUdL1MeFfQQe5WZj5rVJl1hp5jEpj7Qr0eohUGdSpa8o2Ue27R1S0tCTM8nhDRD3
S5G/uG+7dL56L+kQUe2t6+OGtV42ZCYn4OHcp8LAvQt6JyIzJisYBHTR5Gu75QlRzhU9oRiVLnOu
AutOCQ7C9N7sr73DMcbfqds7vw8jFZBfgwf+vlrpVDHwMdMLixecEXP2dMwMDNr7qSU3eXpU1d+3
rg9PtoABuuLyf5h7gLTUr1EvkKI9KxPzuU3NC9vZQrvad8oeQ2DfKKg8pdaZR6XteZSHfvluWUhw
2NL14LGH/Holc7q1s6ZZb2aEvUADCesf1+SdxQC2LigEbBEAxC9P8c64qE3TVH8+dI1QifMP6kaC
IUCDW4QNeLp4+6XIj4O18QE2GfMxK96VOk+U1TRjD8SO1YVZwP42TScGNfxw0Wnz8CzTiygN4cFw
Y5fGmtn6337DBtUJXHG5GEmKZBwQe5MuH4rvlMgaea6ldFcF9N2RQMzM79YHIxKvlpu54Y5LPA6K
nhO2W1TMfxxxF/Fun/R9aIs47CIzbYr45DrCFh9BY5sokSE9/JO4GSn7EJ++7BhL7pskZCu1ClxX
vgGYcqoZyhMWTVGyqdI9ViDVjMDFbDicQ2va4KOyDI6qeNk8l0E9vOr/2FlTunSelN/z/pDXt5hf
JcT9aW58I2vil42qQbh0sDwbjyK8VZ6TwCb5hzbm+cFNdILl9vwOnFwSZmFqmVT0j0fcNlER8sBh
a+9XorUGbZSyyss7KdlHHcLEDfViS8cJ9diZX95RdRA0IcOb8ReZAC/firfS/RrNOGU/X63+huYM
XY4Zo5SaSjYKiWQVabdeSSWKt4N3ujMDRBQiuBszerhzYqIGUjTemWTM7GtqfNNX1SpIbtMIUoN3
6nawiL19A4qdOcsA8htVmk4xxBwOistAuZlLbliVXofJTS89fs9i02EgcZMWj829NC9GAjzAq9+F
a/cihxWO2OPul2TKFsQ+7xlIZ5KFFSRnnYGlxLfIq+TAY3fpf3QUBLGNSLFV3wlsAM3NOieRsBsv
GujtiO6vcqo9B+V5nYeeBR6/n+5p+0xSUoscusRQNKSOYTgESDQ/I9MvT+xYsTYMF+347Dp9BIWI
OxZvjfhjYz5+DShWHtNM7+Y/fswy4l1Ec6qtWH4FJPJKJXNkyGbIaMdi0clPVCy9/c2cgEJNNsnU
Xt+Byxjrs4Yt+ORhcN6iPQvY98tFq56EL6yYD8S9ZhqSIJ2Ix+A8n9emyzhEFJzrhiajTj0vIEmE
eJ1j2r853a4PTTcssrBiR2FHN4MAZS0oD5EyxfMi3TAbNelYY5gDeYyRLhVixopcndnKmNzMT94g
IWDQ/BiXF4HBpQ/22aYyDaI8JZDlCq4FJAOdH7CfdcVxqmP/06SnlrUGCbySpk4WbC6JiU/GLTnr
MISlLVan9YKNhSQUaSaT9/z+gi96oVyyLCOg5J8LHUqpAuDkUAUpIjAQ+Gy2LX0KiCTCBkunAkQQ
qSrOlBRwm1NG3L91YM4icqJ7LyCRTqo9NXoLVlgrI+VoWRuOcOczU9tYx/3SkiG+8eubizBiw0qP
07Jb98P+SPWI388Qwl2KsIKOlXRcznpVvNEY6kap552Ex7a/WvpBeQwXTasoi0PV3AZUfYIF7hAg
6vg/+kklM3bnYo4b/H4b2aYA3Sj+zBCVtawCMX+5YLitqVOl4uWgH5gYnPg+mGURoN2dq8Lh/fTA
Q5VaYf9LZ1nqNtb80vtCbSSbi1Ob6KQbZDlGCGN0OKKLtyWbMAGpTarbcx1nIR/VSTE9HunN0vwd
jwxJCw4qLbeU9eJqqxuN2DSWSeaaGaPfTKZ6+ywJ9NFNuueJdy1NRF0wZ4hsc+c3a/wuN2sMeNgp
vBsvH7o17wS82JNQok6IGCCfbrIdOkhnuEdtbIEq7VHjoLwEgtgzsPZ4TsZ7GINnEC8c6R4RxNmm
Dl09wAUBehCU3Yw1KLqZNqDkvUemvUeyX3QCuLEYLhEaK/NbqJRNJbl+yFVmm3nR9+waBiVbeWpY
5taWNCkJh16EkuACDkmc4aeM7MowLkC11omcJdNumaZXZ8QOHVe+i7WYDi0jZy+nIPHzd/Jr2VQx
b1sRRHGgYWw9vHfk/JTJIx26x0QIdzP2VHY3lVl0ZIiLBeiViNPE8d0LOKBTk5mCwkk8iL/xqoOF
dfAy
`protect end_protected
| bsd-2-clause | 7a1f72a9a48535c346be1a17e4382c5f | 0.948214 | 1.825629 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/types_misc.vhd | 1 | 9,731 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
use techmap.gencomp.all;
--! CPU, System Bus and common peripheries library.
library ambalib;
use ambalib.types_amba4.all;
use ambalib.types_bus0.all;
--! @brief Declaration of components visible on SoC top level.
package types_misc is
--! @defgroup irq_id_group AXI4 interrupt generic IDs.
--! @ingroup axi4_config_generic_group
--! @details Unique indentificator of the interrupt pin also used
--! as an index in the interrupts bus.
--! @{
--! Zero interrupt index must be unused.
constant CFG_IRQ_UNUSED : integer := 0;
--! UART_A interrupt pin.
constant CFG_IRQ_UART1 : integer := 1;
--! Ethernet MAC interrupt pin.
constant CFG_IRQ_ETHMAC : integer := 2;
--! GP Timers interrupt pin
constant CFG_IRQ_GPTIMERS : integer := 3;
--! GNSS Engine IRQ pin that generates 1 msec pulses.
constant CFG_IRQ_GNSSENGINE : integer := 4;
--! Total number of used interrupts in a system
constant CFG_IRQ_TOTAL : integer := 5;
--! @}
--! @brief SOC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
component reset_global
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
outReset : out std_ulogic );
end component;
--! Boot ROM with AXI4 interface declaration.
component axi4_rom is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! Internal RAM with AXI4 interface declaration.
component axi4_sram is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
abits : integer := 17;
init_file : string := "" -- only for 'inferred'
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! AXI4 to SPI brdige for external Flash IC Micron M25AA1024
type spi_in_type is record
SDI : std_logic;
end record;
type spi_out_type is record
SDO : std_logic;
SCK : std_logic;
nCS : std_logic;
nWP : std_logic;
nHOLD : std_logic;
RESET : std_logic;
end record;
constant spi_out_none : spi_out_type := (
'0', '0', '1', '1', '1', '0'
);
component axi4_flashspi is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
wait_while_write : boolean := true -- hold AXI bus response until end of write cycle
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_spi : in spi_in_type;
o_spi : out spi_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type );
end component;
--! @brief AXI4 GPIO controller
component axi4_gpio is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
width : integer := 12
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
i_gpio : in std_logic_vector(width-1 downto 0);
o_gpio : out std_logic_vector(width-1 downto 0);
o_gpio_dir : out std_logic_vector(width-1 downto 0)
);
end component;
type uart_in_type is record
rd : std_ulogic;
cts : std_ulogic;
end record;
type uart_out_type is record
td : std_ulogic;
rts : std_ulogic;
end record;
--! UART with the AXI4 interface declaration.
component axi4_uart is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq : out std_logic);
end component;
--! Test Access Point via UART (debug access)
component uart_tap is
port (
nrst : in std_logic;
clk : in std_logic;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type
);
end component;
-- JTAG TAP
component tap_jtag is
port (
nrst : in std_logic;
clk : in std_logic;
i_tck : in std_logic; -- in: Test Clock
i_ntrst : in std_logic; -- in:
i_tms : in std_logic; -- in: Test Mode State
i_tdi : in std_logic; -- in: Test Data Input
o_tdo : out std_logic; -- out: Test Data Output
o_jtag_vref : out std_logic;
-- DMI interface
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0)
);
end component;
--! @brief Interrupt controller with the AXI4 interface declaration.
--! @details To rise interrupt on certain CPU HostIO interface is used.
component axi4_irqctrl is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq_meip : out std_logic
);
end component;
--! @brief General Purpose Timers with the AXI interface.
--! @details This module provides high precision counter and
--! generic number of GP timers.
component axi4_gptimers is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_pwm : out std_logic_vector(tmr_total-1 downto 0);
o_irq : out std_logic
);
end component;
--! @brief Plug-n-Play support module with AXI4 interface declaration.
--! @details Each device in a system hase to implements sideband signal
--! structure 'nasti_slave_config_type' that allows FW to
--! detect Hardware configuration in a run-time.
--! @todo Implements PnP signals for all Masters devices.
component axi4_pnp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tech : integer := 0;
hw_id : std_logic_vector(31 downto 0) := X"20170101"
);
port (
sys_clk : in std_logic;
adc_clk : in std_logic;
nrst : in std_logic;
mstcfg : in bus0_xmst_cfg_vector;
slvcfg : in bus0_xslv_cfg_vector;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
-- OTP Timing control
i_otp_busy : in std_logic;
o_otp_cfg_rsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wadrsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wactive : out std_logic_vector(31 downto 0);
o_otp_cfg_whold : out std_logic_vector(3 downto 0)
);
end component;
component axi4_otp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#ffffe#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_otp_we : out std_ulogic;
o_otp_re : out std_ulogic;
o_otp_addr : out std_logic_vector(11 downto 0);
o_otp_wdata : out std_logic_vector(15 downto 0);
i_otp_rdata : in std_logic_vector(15 downto 0);
i_cfg_rsetup : in std_logic_vector(3 downto 0);
i_cfg_wadrsetup : in std_logic_vector(3 downto 0);
i_cfg_wactive : in std_logic_vector(31 downto 0);
i_cfg_whold : in std_logic_vector(3 downto 0);
o_busy : out std_logic
);
end component;
end; -- package declaration
| apache-2.0 | 776904a08b9486e79cc6bab9c449d217 | 0.625527 | 3.237192 | false | false | false | false |
szanni/aeshw | aes-core/types.vhd | 1 | 2,443 | library ieee;
use ieee.std_logic_1164.all;
package types is
type aes_mode is (ENCRYPT, DECRYPT, EXPAND_KEY);
attribute enum_encoding : string;
attribute enum_encoding of aes_mode : type is "00 01 10";
subtype byte is std_logic_vector(7 downto 0);
subtype state is std_logic_vector(127 downto 0);
subtype word is std_logic_vector(31 downto 0);
type s_list is array(0 to 15) of byte;
type w_list is array(0 to 3) of byte;
type matrix is array(0 to 3, 0 to 3) of byte;
type lut is array(0 to 255) of byte;
function to_state(din : s_list) return state;
function to_state(din : matrix) return state;
function state_column(din : state; i : integer) return word;
function to_word(din : w_list) return word;
function to_s_list(din : state) return s_list;
function to_w_list(din : word) return w_list;
function to_matrix(din : state) return matrix;
end types;
package body types is
function to_state(din : s_list) return state is
variable ret : state;
begin
for i in 0 to 15 loop
ret(128-i*8-1 downto 128-(i+1)*8) := din(i);
end loop;
return ret;
end to_state;
function to_state(din : matrix) return state is
variable ret : state;
variable i : integer;
begin
for row in 0 to 3 loop
for col in 0 to 3 loop
i := row + col * 4;
ret(128-i*8-1 downto 128-(i+1)*8) := din(row, col);
end loop;
end loop;
return ret;
end to_state;
function state_column(din : state; i : integer) return word is
variable ret : word;
begin
ret := din(128-i*32-1 downto 128-(i+1)*32);
return ret;
end state_column;
function to_s_list(din : state) return s_list is
variable ret : s_list;
begin
for i in 0 to 15 loop
ret(i) := din(128-i*8-1 downto 128-(i+1)*8);
end loop;
return ret;
end to_s_list;
function to_word(din : w_list) return word is
variable ret : word;
begin
for i in 0 to 3 loop
ret(32-i*8-1 downto 32-(i+1)*8) := din(i);
end loop;
return ret;
end to_word;
function to_w_list(din : word) return w_list is
variable ret : w_list;
begin
for i in 0 to 3 loop
ret(i) := din(32-i*8-1 downto 32-(i+1)*8);
end loop;
return ret;
end to_w_list;
function to_matrix(din : state) return matrix is
variable ret : matrix;
variable i : integer;
begin
for row in 0 to 3 loop
for col in 0 to 3 loop
i := row + col * 4;
ret(row, col) := din(128-i*8-1 downto 128-(i+1)*8);
end loop;
end loop;
return ret;
end to_matrix;
end types;
| bsd-2-clause | ece5464f242de92e7abce0e1e3facaa1 | 0.658207 | 2.717464 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/bin_cntr.vhd | 19 | 8,597 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
CJc8rmbxQK7PiD9FE9h/V8z28Q2yjtwOLUGOHj92X0D4bGhAiTKxH6Gs6WbTk3x8dF6WKWHXW0Xd
imaqryWs/A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
KUGgnJN/sGLwh1pfD6BBRkJkdz3qYXsMmFAG0D8TIT3kvn1DM/WYFdJfNjuI3TZJ+GjJhgQt/TQj
vszszvccproNtKL+iK2kDAI+dODbmK/3dk8pZpjNIY8iqG+SZd4LOHkCbGnDn8J5L1SCb1FbgOpc
lYLzGKyKMfpMp2H5zrU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QPilQnlZ7SkqHJ+uQKxasOWlKPf9SmSQp0r8PPqOPGeQK2aUl+9gzicjiy17/DdQAM7rwf++nyUV
Yi5HrcGStcw9bK+k96zmiNT/NPvXPX5xeKvpNagObga/il62MarkWpibvt8B7D5IQi80Rp8/xMyy
QM6+TtOf7NVahw7dZAUwr3krfROulZTDfEY3oalO/PlnwAGr4Z3udXzac9NTOUWxkjpW4cmTbWcJ
unHhHJbyMO341XtwkTUgKReezgKFOpi+gREeBT80YOKcPQyjGyGuc28HYVmxKisVh5P7BYL5neLX
P5GVK+HA7MCB8DsbsorDqal6rxwDeaIF/kJcyg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZE3LPHWjt8FXIcLXD6pONgldgtzqHVcVbUx4Qj9ztf/3D9DwoYFB/m8dT7Cv2OabvKVMu13QC5lB
rxR5Jhd+fouVouDNKYwIESeS4DEkgnwfSJpsmeVaPW2tqCd21tzGTVfcw3Igam9PcTjnI1q1568h
X1Tcmu9paLkGRwvQeII=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EV5YorhH0risCTPPpyQGO+wsA9egdTVjrRAwQuEDG89jVsb2NsTih5Y+XoLrashGMO3AtQzajDhF
KB2YGM3JfNSzKu3jU5R247s9Goe6ZA8J4KFFzdwq4blriCHlPX0eNqXwJaOF7SeF++njAnDs0TkW
tSOb3VJRRI43LgFv/CHX80X62oIhRm2LIRAjPrPj7KevSjFw7diU9sSURAffWyrhgq3XZsUY6ovy
nAWzeDeWY3xrRDkxjxQAN8xOlyfUxlNsf7am6Prp3DCG9ANkw/MCyfCVBJXBbghP4T6GS/pNjySW
+j4cMtiThQqIcJCHVcAXQA0FAf6PbH456gYJfg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4624)
`protect data_block
RXPikW0YhBHIyjBLgfeGh2IqgFUmnNzQD9M01KF9fhoxYQTApGUtdOugGk+dMd2dTqpPeKH6HDoM
tobHifvqN8ZUiU33zgE4tOwty5usYFEpx8LFD6mdardO5za3sGfc3NY4Hqe9yTIdASzQsm/ymrf2
Im0ysvjaMr73w3iU1ZR0oYkHIJwHTMDnP2zLXFhUt8Pe0kQPO3yOCu6hAbMcLyQr2huM/8mzQssa
DQbCPCpnPzcVRNQrNy24cU8Kba2CLJHgApprqkUK1BykqHKP5OszujPq0anex24iCcp8k+bB97Ly
vwb+AproX/Ehv0QjHmCBBNC6L9sNKarHlumGyqgo/YcQBnCxaWQNMxh6yHn9tSHskdeha7ZHDcm3
2CrtwLmtE+UVSJtR9M7LZiiE28A2Bsxzz4uZZNCQVDK/gzg6pvll6Y3/Vx52AGsYWuhAbebKrUun
CIhtzCpoDIRjBRDirSlwfka3lHWdUW/SFh/s2QTbhDN5rKXQr4xZCarRIWmbbD/K9oUiA4JISYVx
2xqSJ7oFCnHKTEfDKfEkNRG5gPjyTI3V8U5k8ykhVBgL3CtjlI+DNQboQfWTzYki2BZTyFxOyYlu
pxOPnnruNgdJOsd5N2A59xrFGw/XMpblUfOmt0IQTqkPF+2PF+VJk2iuOkCdbonihCKfamCVypMG
st7OpKsWBYkPq0UisEncpulJlmRaAy7daCtGOjirhl8FCw65vc6pR9avZFjSqPkQJrfaU6oJPzMF
HqNIDH3qYAJ/vEfF3P0ryZF0wtXHEIgWzvrhgAoGJro04P12UsBSo59WCGSWeTtFGOmNpDaPS6yA
11Y2v9n7kaalg6cK29miafwWnZBdFavNWWPRdxSfZMZEvoPZN08164xYeQZhiVysWnsmCkQFj3Uc
wTB8CVNiwUkPqsNokpfPsAlBmdfemUUI+StCPzYn5c+sRSizJYbFXquCkp2yErJtqkZS+1zwsKbE
20ZlOKpz/qcfsaStxm/MA9lQZM2FlEGwkZyvnweAcPNCzW0h5bAlDY6XrmUFwxic3YCmKfmysrcB
wQn/hucBMPBWxoufOS1NNWXMNMpz9Iyhs44HwOnXNdBgFUtPrIdNfGS3bB8YVYD51BBx7BwNoeEz
jGseu6GyOQODuAixtYjZspiqWMwyuBkH3K/I7h0DYtU0dnHjuSc6z3HD4VtsSbWim67CvczUlQYC
bDPeIlIARTzwn9NgnjgyAH7V6m01vgfUeeGvyFiFSl33bTAvrCPiERvMp6GIaAuxP9sagSXPircJ
LoMS1WMZuEfgCN5VkOLAH6DRCbOU9Xer9S+w+vrrSINf49TjVDfh38lW6/2tJ7oVQ/ESqGhtMQrt
a7m/nFq4RN0n0vTd/wfpi2otKfgNaMeR7rxkR4B5+8NXKFQDAZPqZoJ9RPfsGblwnXoDEa0sM/eh
BGe0DtTLB6lrfBRUwHjR4PTwFq4syYLjP2m2dGaEg3ZLxbQMzVFO25O2NhAnvCTfAFuLKRDMV7LV
E1QYOsviEYKnaY3mioohxnwnS7C+WJHF1DViXV2co5q9kGIcnhn6LxRHkHUjkZRqBiOTMb+KJMFE
bxcK9uHpb2mjKjEwplMGIsIkla/h1ebbJUgbfoDNk+PulVmbzNJJ5aO1tPU/0HDE5qOzuKhsNCfY
GkYjWH8z5RsENDNoQXY13IoJpfy/VPg9Mez96kplyrwbYB2I3nftZB8J2jWGnqObLHOo3jJAmNi7
PAiXTUqFwx6Jh1vD4laA2DsqP2dAGB9GNk9EITClMdgDVZwxgbll0mQQH6YSHrBcjIF+asU1BMvz
TVGntUVYCgJN1tM3iQ+ss5lvw1Q2SZc0FrZXnq7VvHJ4myP1VRUp/AdZuj9+wy/2p3COps+lu0ah
PQx1EvcXbWY5tVt9ab2lVeSp3E2jgUGDND0OUo0Mr393HXgsj/orVupeFjze1S3APA8iOVnzMnxx
sdPI5C1PSJIH4XcG7djpUUQVmpVNXp1cZoNInphe4cYXQG/LYCXjWvl9G5xjR3t0vTdLIzzfLBYQ
Mh6pjuQLXJ3KSLeClg3N+RaiQAGVRLDeshskIBuM7osGSODdO0rl9N3lfr+f5oBAmcg35hQ+qvH3
ms7oHAKnhCewmxlmEFxZz8faxnnNTrl8m1yaE1MwZac+W/YQD/tzNBvDfbXTR62wRtaOlGoFr6vr
jS4JjvUVc3Yn8zUYt5dPKq6p8S+mt5XZvRF0eW/n3mnIYkTSWHyGkMQtK4NbYrMIuai+fplHUH3W
4V8SN54yQujoBCIo7lPLKtYYOmE1B/NOtj7/HGg00hXHtmFwhIeh88Bw+BF84DBBM0AyQ+wQeMP+
cFKD4fubkuWb0YDyTgWRKGdzRHdeZOGTu+tg73eVJYZKkcNA3mHNLRsX5jCBxCdxBVJM1TSPegbF
ujYtDpUeTbDwVQchLqq0RLj7zLdssuCrUtlrdblbdJUMCEgtcLIjvsYwCu4tv0xcO1d5ob6Jn5A9
2zHe3tdmAbjw5C/no99cNuPIw0IGPU2NR4stTd9JM7TzvRB0V/mlaci+FYcu27ClFkMRersDpKp7
10tCRUIw1x32uw82d3DFNGb6X7yQdySxsQXZs0rGW4sTbbA/E03oSjuhZCWtfBGQaJ06IA5DOllW
XjwaA44eZwKgvR5ysvDMQygMr47AucFlZKO4pyIoP0v94myK8oYXgP+uiMVsM11NPW8hb2Stx8aU
bbwHTAJqWQrfiFHE6Akv9IByR2zVKo3iMg/LuL8ot5mDWOJd5OAit0MBlFLEAsNVDgAeOtLmMuAs
iKByuwQInalwPwy8iiVb76LiVYf3WbHXY+UWLcd+OG0p4VKk4o23nshsiXeJJNjXB3efukMfLyiI
EiudbNgrN6glhZRzl4UY7gjMIOyDSl7b/r6YX6qGg5RNQzjrlMPp6o6gd95OfWAT/HD/Y/W+v5xX
ei55OxRtMMj3g13mQSqTYUaNNZ+X0O93BqNZit+DHI74HHylw3qeJyTj7X9D5vwyyaO2CvNzyP88
kIcjvh6RrgTf9iiUifVvM9SeghO59kgp6SOq1/sRxjRtOHFV3NZ/PW8BABrZPKJl4Ja8fBt2l+1J
L+mAbGqzNMwCAF4YThSid/9vKJKBCmp9abnYf/X26BujzP9/uLN3sfpbNjPf/5uyrf4ZP0wdtNaA
ymXBcHoTF0Aao9w4I9txa/6P9Y7M/Kou+qoDWhjrH9Mfz6g6+YSqwktFR83GIvuYaBYfTwQ2kDLr
q/q/6ACotgXihWRllL3w32OqGHzKNgmyhegcuT9+U4WBxjtQP+EmoWqEm4VP26rmwxR1SJpxNSTh
QzFtgIOl5o/wD7e43idnLA0Hizv0sek2btng8O80ymQIF8RPMn8cxKtzfPmDMKEq/mERN5n+GKlg
KBZnwZgbj9XOhY64DzwsInzKE9PbwITxUGQdD7ae0mZVhk0LTgIEQhZfKYmT+KbQ5yJW22Dy+PEA
MbD7c/fUOeaoqCpLeRvEaMWdPVG7NVUUnkn5pvrMPtrZVEtLgEKXhlHCRKiVNNfC5KLL5llzhSFT
fT/EYc7TvzCmxrZ/7nxsgnAAqqRufPvVmtoMURd+le7HwyQEzKRTmbgEes7iaFV84TCMQZZzUgOt
Q2LoByZhMK2St8FJC2XYXHgd6QniUYCszqFAmwbe6FJ+L1DKVLZncl4bzGdXQCtJ3fC9691KGuId
skWX3zXXa6ukXNfFpb9wGArnrsjpclYqQTfmEWojshxZWLpCJ8BGdI6C76xgYskQH2yh55fyGPgD
gcyL9B/iapFr2UVJeDw70cs74l+DNyWD56hpb9v6W1vEjYzjm1DBGbkn5mAjG3OlaQ1g2vHOk/8o
7hueZZrlue23oLRgESRDIqwWsE1leB1NkhHbuqLqSkT9tzAbFouJ0YEmwHCFtJtYQpUy0EXLGmGW
y8WlTbdfUHGOySt0ko4QsJwnUQrP0Xci+Wm/rFCDhKTLbK7D5ZzdQz3dhoctb1aiQa2at6R/u6v4
K8wItLuvhajdtrKXPitNFflQdLgzclUMmsa/+kUl0DiWbYbtr8WIUUbJOxAMMGP3H+jM5MR/Dzkz
SJrnWF18OsWy6wllvpXcTHf7m18m1umpCfWIv+pzCwgUUaW+f6QzPZ4WxoD0tS+FPW0sGZftp5Vz
N+iluVt/WaSsIxt3AjVCU30UHMdPf7wWyhwI6z2yqXpCNT5ZC42+8ytYBqwufT41nZGUZE3NeShm
Kffw/xM9X6WtRK9Dt+w+O0AvcNTtbgT36bebM6R2tfFwvQ8jj4Dxu0zY18wdz2ON9EcqcAzcS8Gn
bVTSVMWrw2qKqvL39Xmj38kkJ/SrNhSwAGkVp2KmL/AoBBpkGGfL5R+cI2WGQoLwj1OZJbLKkX17
eztuUfZi4sddfkUJ2t/3IHDa+1Frlium419JEn7mCiwvkA78SiDN8qKuinIWaEr1IgRhqSePPeOM
ypui3nDBGJP7tK0v5f+3HlpjQ0eF0by8d+WqNsmW+mENYoV7paXfvhp0G7lEy6kA/0qSlPQgBePf
hBHWyVTziIbmd2YAT213mzhUte3urVU2Csh/hHdOktyUCato0/RSp/NECSo4P67HD884yqcY+zs6
pvIUZ6jRiVnmXZlfKzSGhCqnTmt34DPxr7jVqumL1YI4T2EX1+Pm016KEXFLjQIVDfZfhw7U000W
Ew+f+j4N+6R9VwoJs084HNd/OYuRDO6grq2w53x/PbieIM4OjpikJQLK0rPhUIgIw7iNwq22asIF
TJUA4cTVeuvNbs0RkfUCjLpvu9b4dMwgEXcnw4jPAPdUSKayWgGD4yfyW1wL0uP+0K5R8qRtnV1H
DZHUTHMczbAWNb2Ghbzv/E78Vzn2RgSiDwxw1G/XL/BbkHtqL/snfXPVK4DtE3BlO5LvvOWg9X4Z
UCQ8ug4avRbhbnNvrm3r1QN+ayPF4Q8JRkwETTp63Yld1CaR8g/2k/0uGJBmf9GUm4vtqc8dBVSs
AwlZmVIRSVDlXRrPsMYQuAzMetBaOFwgQ47ht0tzeh0e9x30xguqAoR5spJk38QCkSQtJ2k9PTj1
p0xuN6CcTHNgk6PWMAqGvxRyQRecr9O/AsCLOnhm73xYfhdg78LRN+ousoQvP84PHMGSXHOfeW/3
wsBrTuh7XiCOnCLiGEzDoxBzyZ6z6PG2f2zSHdPcQJTZlS2pUg+tzrBPF4XboDT2N5b57dgThrDy
dFrKeBEdcRBOvwK7iR9McHFY0+qRCJHe/SEpCIP7nUqOZzUDvPcST6N74MKkKrXu0gEtMBQTahLd
CmRUTJhSMO2yM8vKGMHxv+SEl9Rar99rtNer+3FLM9rU+IqqSfuSqwLAE4P+kFCO/euc5pt8JZDc
RZwhRFoLhUrg2wJVXe4Cmq2Ru6ujwvpeQUUC6WLaHk2GIfpnT8Wu8/BaAQ2Lr1Q6B53YLjG9Fl9K
k9QZbXT1X1boYu738RciPeNg+BitoeI2W2aJQ+PCFWCNGk6DAUNNoxhOImJeYXhlC4Tj1fpL28f3
8Xg+Se09iDsWOrCwP5qVUlnkf1ceLLRraQfZQdxZcvYc5ESIyqyCtPGZ9U1/IKFgYNugBB5vm+lC
8dabV0fk8IHSS2JEDtIHZ03TQKTUZonvMW+Q9kQ/XceChpPKwxio5cLjgchSZ361Jvt3XgJtJFxa
zagPxkL2RjesLKcTXFSJBHBRqstzkKKVTw07pfzDebS/gOQnfRfUS87eZ2Q43Iq2IjYRNrr3PXcS
AXGRqOZ+XR2uzii61WNOgluPe+457Byv14PaStW+HpSl8uItzy+9SMlodYy/1S2Z1o6/bLdMrQKZ
/R6XDWqngE05KDdYS11FIgFf+gAUV8BXgDs9WHAb+/k1Dg/CFJkjBU9NRPtlS/D7YIeOKmdZH8pX
32+9kMez4Vf26vrwfeD86sYNs6q5b0l/OwZsqq6Lw7ZOrtqPEcl6DHT2LiymY0S4y5vqPJjMRq4s
T3WazHXzsmc3ANEjLNPMhfC3SMJ0j0wG7ZbjcNeOLse75EtJSIRNNR6j+4vrk3FKvjXhM31AsREw
5IyqKc4jL6km8DVJRF3/Zw5tNCAfrCe4ekeLysLtWTzswhX0WlZXJ0lCNg6wYoAjHa2s8T0uxpyD
2+v7eWmAZQ==
`protect end_protected
| bsd-2-clause | eaba199828ead1c3bc15b853235e0a98 | 0.920088 | 1.931042 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/queue.vhd | 1 | 3,787 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity queue is generic (
async_reset : boolean := false;
szbits : integer := 2;
dbits : integer := 32
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_re : in std_logic;
i_we : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
o_full : out std_logic;
o_nempty : out std_logic
);
end;
architecture arch_queue of queue is
constant QUEUE_DEPTH : integer := 2**szbits;
constant QUEUE_FULL : std_logic_vector(szbits downto 0) :=
conv_std_logic_vector(QUEUE_DEPTH, szbits+1);
constant QUEUE_ALMOST_FULL : std_logic_vector(szbits downto 0) :=
conv_std_logic_vector(QUEUE_DEPTH-1, szbits+1);
constant cnt_zero : std_logic_vector(szbits downto 0) := (others => '0');
type MemoryType is array (0 to QUEUE_DEPTH-1)
of std_logic_vector(dbits-1 downto 0);
type RegistersType is record
wcnt : std_logic_vector(szbits downto 0);
mem : MemoryType;
end record;
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_we, i_re, i_wdata, r)
variable v : RegistersType;
variable vb_data_o : std_logic_vector(dbits-1 downto 0);
variable nempty : std_logic;
variable full : std_logic;
variable show_full : std_logic;
begin
v := r;
full := '0';
show_full := '0';
if r.wcnt = QUEUE_FULL then
full := '1';
end if;
if r.wcnt >= QUEUE_ALMOST_FULL then
show_full := '1';
end if;
if i_re = '1' and i_we = '1' then
for i in 1 to QUEUE_DEPTH-1 loop
v.mem(i-1) := r.mem(i);
end loop;
if r.wcnt /= cnt_zero then
v.mem(conv_integer(r.wcnt) - 1) := i_wdata;
else
-- do nothing, it will directly pass to output
end if;
elsif i_re = '0' and i_we = '1' then
if full = '0' then
v.wcnt := r.wcnt + 1;
v.mem(conv_integer(r.wcnt)) := i_wdata;
end if;
elsif i_re = '1' and i_we = '0' then
if r.wcnt /= cnt_zero then
v.wcnt := r.wcnt - 1;
end if;
for i in 1 to QUEUE_DEPTH-1 loop
v.mem(i-1) := r.mem(i);
end loop;
end if;
if r.wcnt = cnt_zero then
vb_data_o := i_wdata;
else
vb_data_o := r.mem(0);
end if;
nempty := '0';
if i_we = '1' or r.wcnt /= cnt_zero then
nempty := '1';
end if;
if not async_reset and i_nrst = '0' then
v.wcnt := (others => '0');
for i in 0 to QUEUE_DEPTH-1 loop
v.mem(i) := (others => '0');
end loop;
end if;
rin <= v;
o_nempty <= nempty;
o_full <= show_full;
o_rdata <= vb_data_o;
end process;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r.wcnt <= (others => '0');
for i in 0 to QUEUE_DEPTH-1 loop
r.mem(i) <= (others => '0');
end loop;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | aa465d0d69a067ced80c840fc48c9291 | 0.577238 | 3.225724 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_sfifo_autord.vhd | 1 | 20,294 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| mit | 31d69d640b1c1596d219c49e2202925e | 0.426136 | 4.959433 | false | false | false | false |
szanni/aeshw | aes-core/cipher.vhd | 1 | 2,738 | library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
use work.math.all;
use work.sbox.all;
entity cipher is
port (
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
din : in state;
rkey_in : in state;
dout : out state
);
function sub_bytes (din : state) return state is
variable tin : s_list;
variable tout : s_list;
begin
tin := to_s_list(din);
for i in 0 to 15 loop
tout(i) := sbox(tin(i));
end loop;
return to_state(tout);
end sub_bytes;
function shift_rows (din : state) return state is
variable tin : matrix;
variable tout : matrix;
begin
tin := to_matrix(din);
tout(0, 0) := tin(0, 0);
tout(0, 1) := tin(0, 1);
tout(0, 2) := tin(0, 2);
tout(0, 3) := tin(0, 3);
tout(1, 0) := tin(1, 1);
tout(1, 1) := tin(1, 2);
tout(1, 2) := tin(1, 3);
tout(1, 3) := tin(1, 0);
tout(2, 0) := tin(2, 2);
tout(2, 1) := tin(2, 3);
tout(2, 2) := tin(2, 0);
tout(2, 3) := tin(2, 1);
tout(3, 0) := tin(3, 3);
tout(3, 1) := tin(3, 0);
tout(3, 2) := tin(3, 1);
tout(3, 3) := tin(3, 2);
return to_state(tout);
end shift_rows;
function mix_columns (din : state) return state is
variable tin : matrix;
variable tout : matrix;
begin
tin := to_matrix(din);
for col in 0 to 3 loop
tout(0, col) := mul2(tin(0, col)) xor mul3(tin(1, col)) xor tin(2, col) xor tin(3, col);
tout(1, col) := tin(0, col) xor mul2(tin(1, col)) xor mul3(tin(2, col)) xor tin(3, col);
tout(2, col) := tin(0, col) xor tin(1, col) xor mul2(tin(2, col)) xor mul3(tin(3, col));
tout(3, col) := mul3(tin(0, col)) xor tin(1, col) xor tin(2, col) xor mul2(tin(3, col));
end loop;
return to_state(tout);
end mix_columns;
function add_round_key (din : state; key : state) return state is
variable tout : state;
begin
tout := din xor key;
return tout;
end add_round_key;
end cipher;
architecture behavioral of cipher is
signal reg_D, reg_Q : state;
signal sub_bytes_out, shift_rows_out, mix_columns_out, add_round_key_out, add_round_key_in : state;
begin
shift_rows_out <= shift_rows(sub_bytes(reg_Q));
mix_columns_out <= mix_columns(shift_rows_out);
mux_3_1 : process(y, din, shift_rows_out, mix_columns_out)
begin
case y is
when "00" => add_round_key_in <= din;
when "01" => add_round_key_in <= mix_columns_out;
when others => add_round_key_in <= shift_rows_out;
end case;
end process mux_3_1;
add_round_key_out <= add_round_key(add_round_key_in, rkey_in);
reg_D <= add_round_key_out;
reg : entity work.state_reg port map(clk => clk,
reset => reset,
D => reg_D,
Q => reg_Q
);
dout <= reg_Q;
end behavioral;
| bsd-2-clause | 080a70cb06d131eeaaf7a6b887b18b7d | 0.585464 | 2.489091 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_top.vhd | 27 | 71,839 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
UXXDHK9d3YtwspCksVg3cn1OQkWFk3QQ1bnN8kcpv130B5dMgVD8+qx+9EwjTR0JFb8FYrcL/7dg
lIwdmlKGHQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lGlirTrah5ntgtsTqcFN8kWYeCxRHbehSLZqyiEvescJE+ORKShYIOu42/ExCc8hSawNVl9qCirT
UlThiM+Fc1evKMQYzaFIzbKiio/Xw8rjRfhTJKjaxdK3T87LnrHcsuSrci+tl+anpBCM3X47tPxD
oNmgZzATBY/NVtZsbvA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UAOAU0ylQuQrszr15mLZsCg4shnqFlxQBAKcqwUoJfM+lTESkAcOosPqKsRH4IbbLlaKiP2HCFU1
aKEFZccPWIgd9WlvneNU3oFbpPCOyV9eZTCX4e5jNTf/7OwRRATKc0mjpd4lxBL9xFrSwNaUKgs1
3vjH77tdesEDAIn5GZ1C/7l3wjwnB4tAiaRNqLY90lB834tlc4mPcP6x8L3rhv5EXfqU4jyJC8B1
4zsO/vH5+VVa1595cRZ3xWXEGVMvmWhY+6TDUJCMhztjp+p4kbQ87UqJz9ddvZWB4hRfjo99Os6I
PqyD9P7zikHIa7jafFMtZu0Vj7u4HDelVYnPyw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
qRFhWXCy25iIpt8SG9Mt+xW3HRp/MFye1jJpn72azeuP+g/A4uHCFxvcKVhzcuE8lYDqFZ9IBM4P
ZjcyPOhURivBaWk0KosUyfzbkORd8yS5XcayTSj5/d+90PPk5PXVCLjTrcMbg0+NO3tiyKtPpLQJ
f+Ih38e2az80fHBgiqo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tjh0p4bhQQ++Enuq/zxHJnIk+bY5nNzFWlWKnTVXUtnLIlVGko6ShpeQRaCrGzeMC58aHThmj0Rv
eUmPmT2uqc307TRbbuUeFDYMANj1kcC6Ygs+bdXnSkWnOQFu5reSEq5SE7OMIvzdCIaR/FDvSj26
cuj56WGV7WVTg7EZvTcQQsjBPGe7MBQPj6gVbjkHGUTFOQ09cS9h1BaC9UWWfJNQjyJE48PH9w0J
tqmbE8H5AkyiSVZzE1dyYA/E3WjYX0ib/4FRIxCW96Qs02ypuSbfnvJpIyeRwyQL7ko2qezd2p0h
VgIw3omrmALcnzzjpdcOgkkF7sgouCeIApSqBQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51440)
`protect data_block
vQtH4oMHZ4bBCPj1gFnbdifTPurL1oPi2vztMhzu+UrVva+d9wgwcmLro0ds3O0u2lhxnLVkFLN2
xIb3SeehXcSu7Dwh4suLCm23q9r+OTM2ojsFnTTKIn6R2/j1HVi8JF53aYH4yFjAlqGu77m+xk3a
0hyHrkzwmCQAfH7lriGRuJhOmYPzHRiI9sedqyEyEQWT2Yjq6z4OJlDgcjXm5iYYlj93XTc2eO2j
5dVsJtmj4ZhsjtVIetqhx12ab//TLn5y+7BMTvfArqMBTqCce9MbBEQcdYHgyXLEPS+bdH5pDJ0e
TqdkJYeyuUQTtzH/OBaGre1vilAsTJL0Zq9UojYrvQ0qB7MZt4krC5MnUJZUTSEVG1a5vepBPaE3
e7RZ+IAo4xSOchd8YUYsYg5ChGIhR9EZtWqiSflmRMi0/lmUoBWTAp8epIpmPZq5hGhNP1jBqHwg
MlrQD4VIpoVHJDQjlWKbNxZIm4lM23HIR1yRvPD7kdL68PVQfK6xYAFgzFpEQH1OOA08orH1ZF2K
GIQDXzoWqFcJFR2VlzhHZN/ZJFIHO4M7j6CMeEyM+m+hzPkYQnMB3faKzhs/i9u7971Tr7RbL8fo
g4VSKrQqtktHJLUCNqPzWpHwpJmvnv9rJQ1xvALEcaJQI9wQ8Dv1GXHs1oAyqPLvcI20szbw/2+y
Z+mJK6s40z3I3Z6viDfam2ryRjkCIppDSrEpFBIJHIyrN0hSfoyIbWnrh+77UOyLHot/fYxv/Fqh
bil+mvG4Ver3huPFPDHu8rxiBJBJCGFcYpHocOicrwxV7CWtmqK9hbWr+NhAuTf+OjjVi5zK6VCV
nOaOQ8OxGz8tBYOXpr821R83aMU6ATYpe36Rgf17xWC0HMkwYQu54R4ofXsNuWgZVOgXWlvkpgR8
muipkkdqsHs94K6XAb6FEPZE8tHzZOQewcFj1vFCC4kBi0Hc9cQxzOJxdGCCaxHq1onVzzQiDXuo
CPu8PYZbKrDBshTkaIK1sCwCi8uoxA+mcq4/cnZ+LA54XYJY8deu3SeibYTa38rvLvWdMqLOi39n
xBpaVp+ZH698GSRJB3Ad8gKIzgUdaTq0PFVYTwFsi/ktpzKCM5P26G9tNIQpCROEt48xKhnTp9mY
YWoOnOIzxynXqibjT3GrUVl8I4BAidMIelBCzFvA4hGhOqU322IYr8Gn+njEpIoBUMdyTdNuLYFK
IOe6SkMd5Q36edHPuaqBKt6tYOnv+9d4+aUK8i1SprAysQ0NwWpW8LnujNA13JBbSvjz11xZLmpB
k9q8E+DNT+81kUz6Iw9nSeCP8sEaVC29ymVBXEOnnxjZ9ZfZYOEl2CjL0J1U5MVU6H5agVI9hQll
bWoCdxBr8Y14H+F7asf+rMTmcllbGq+/CSdhDVQ0cXtkj4uDEfXKLCeaNvFq5P/vV6r1twIfr+u8
KgVIYjMx5dDi/0Z9D6nLGnyq+v195iJ8DWV49CaYe4F49X/xmWBDGdvvFCoAjK4xl92tRy25BTlI
DtIkcqPaIbdl7oJLrLNC7JjWaSSwIOy4m3FFcGbdiH8VWAqFHpeM36ChkUkZDgIv01b6ZrV5FVmc
ao9BaoFH8B+1IDIsLm8z9ckK9JK23VgEfhZD22tOELDJ61V+GPS3EI3I/UpKPsG2ThiRTn6OCiZp
FAvSx5Ca6OesmtXvSaH/ZPr4LIwBU+24bsJiLD2SZe7hvnDiGUQR0Zx6szIgLjmqX2mz33XuWvO1
CMR4EU7RTMu0KvUM0nLaorEkodJXNB8FoizIrDpGu5wEKoCf4lKJfpC/nTNdy35cZPVk2gmsagll
7YH4iAjuoxROvabAoVsWDRDqdWP1e95TkqWK+wTr3W/ozw0SUhF6Htl0rP97/BRNo1xsJLbXpKtz
CYnq6DlBrq7Y8BiyALzi/PXVzpfOb8DnttPbGLl9fwlCaIK1c7RBecZYIT/XTF4ojjXXUxBTuWQB
hQbL+T2VBHihmIsGCsyqZvjivAEX6X1lpgfHK7cxnU+eOlsJ1o/MF7u0ezhNkdgYmfmcmXjDd3b3
dsJSz/7K30DNqLBp6OAZdnopzYaNggE+v9Gu4dQtm7vYM9T5R/MY0e5WSKJDtArLlATHNyjCWpZE
rlftsj0PnjsHQqPYPe9rpTdL9JBpZslKg7u05uWjOYbTqAbQ/NtklqOfCi1/oS3JmasxMEkwKwk/
TqUb7xbLh3Mq4VlqBrbwHF4SRHjyQVBcpeufsF/9K1ENlSTavAD3/MtAjiigYInHsNPQ7QTE1Qea
oGkU3cid1WH43XM7k5X+C3Ghe1zNhlQUDszJNHTt86QLiXASC8IvoHfY2AeUNw7jSo2TNhJElv7A
WyD+Hw8sJB0bhIJKYNdln86sqUIJiKjozrHMDpDhc/vmcbaCp1kmw8iE2f9yemtVX/sThlrPeysT
+SbEHMgBoOXmbPpRrnuIsJ/Tl7x/XqqIr5iG+s9BXueFLNVbrcZjVrW3tN3EGbWPXG8xY27hyfbZ
6hcj9YLOzhEBXF6Ha9P3Y7rhWg/vi8rZvtnFvAoI85O4IEpmo1RnmwFZmslU5V9RCrNk1rMchcji
2VGwQfeuS+wduVC0CptVSYlleJ1mh/Hx/enh33vOBTOAyIF1Qqaae5UrTIRTDB4vrAiz/7V8JszJ
Dj8rXSIeJuCdrg1BWU9rkgvprNpNjSWcqe5EE5OEyBh/Wb6m+bm7wSE6+7H7o20qIl1wgFniWQaG
nhNeXnt6T4i22lhxx4rWzgmDlKy0g2aV2mJn+b8wQSViu4rFEDKGrQhJAocE5jhJXirHysyAhw1D
Y1pNu3SxfvXoMmTvNpX47S5VxPhYs7IgVLQJGYWZu3jdUhQagrTP2N27HOEoMdcPt7xih3PHPhYe
/lHFAkmkdbXTARsG8RaEnRkGU9u/doGxIpsdblwd5mbTBvwE8YNS+hu4KPYwVU/5rl4IxVJ/N5iW
G3d2VQRr+zXXa9ihaNvoqZC1Bv1P0D7gY0Up0CxgDaJER/NoAZ7lK62HB+UZhQmfRTNiMeqRVRcH
nbjDTrqo9HvI9z5w4Tq0DyyRMI/44Z6IiuRyjGPJCLgf/+E1cEx2qp+DnXbeW2KZ2AcFB35bSguX
hhrROzPQ/Pj5rFr4nxBGhB0UQbmxHoCqyt2mqFnQ4mpCu6eQFIVox3j8dmbcoNpAGDaILdeEZxwt
Db4AzgFvJ0mBquSCOHlcjz0wtz22MsRjl4NMG5HAUX7kUHtSG6VLJHuXa8sotBdeCeBkrrkExR1i
EBs0K2rrkQaSX+HuvZ/DTmkygUXVBidONV3X+CB9vfgnAaxCe3ysA3wKyQYIWAwr4DRUj5kmFUhE
bnO0jk6/prC4tLn2U9yHQV6uuUXvVz4e1G1J28ZsT0uqKnDg8Z2vnuOJhcz/Wg8BDLkMDhOWOMfa
pMD2bjX2qs7KSCC4862ecCDbowyEvXS88AnmHpYO+Xw4b1QHF8WqHABwAEnOKzZ+VpcbAwE7P2Ou
CxpSskjrQbblXaJ5EOEkReqG+eJYAiTCoz7RZeOEl0yQp2ISnYI8JC952F4BWLDVE6WIJ9a3e2HS
26IggLqqAhbEfzsuCh3sib80FTk/+Pw04iZSt9idY3Pbf3W7I2uIq6s8T9QCUNY9+4hLB+X/m7RL
5sYV6ZafkG6k9dsYgerLB0l1UlF+/dDEiD3rtnj5Hrb/OSDSYyNk19UD1xQJz5kFjISF7xZ4LpiA
xfz9rSkPOh2YMupdSB+nZTD6Cak86Rc6iNpegsp2UgeUbVxxjjcoXEiXuL8EUv+I/1V1lLHdeNP1
N0vjC2Cr+wj63re/xBfUYEYcaWte9BssVdUJ68GWbVr44GeOR1ZJYpG4dfM+D3v2PFvSl1j7AQh8
E8NvhbJ2P5rJGHgjdovYCU9WnrPmMrwRit6+y9aCn1LrqxpUWLE8CX5Jh53I7AZ8lDqCSqtbEPu5
vGqqSfjj0B+6BsxwZkbS2Ur2+b/zMmPT/iOwjmW9ar7dnN3PS40qW3vMWxq1uOjP57Rm3M3KfdUB
4gPxfxNwXVHcQ33pP0X6gx9GT5Xu/I3QsWyZ9l6dQdkMi+M+ezq3yKG+WD0Hr/CLEbrpdHeoPQlm
VLEsQJMRFGFCyRkN8brBVRLjqgj+oQP/Gs9AnzHhOTj+ISOpOnyyAF6dvP7Y3hnIqH7aOdVhI7Yf
nVgIVCxHuF6dJ0cU1kEZD0ABXw12pzzwzGsjtf5imLbdTRQLJIrZ7ZYJEMWMYzgTUdVOsxFW23hG
/eGioe+kP1rlnun6+wLzt97Ot0JM6usdirCOOEMHqE2gHOAotQ9F64YmTClNEP3yNKLLn510WGt4
aUORRACYqQKxJwiMGiVggPpWssQ5d5HOo/NNcqpbPIe7QH+Hva3MZa9wHpvkKkaMdDHXuoPHOTL5
RHAQXcdlA0v8/+PeC9ck0TglN/Le+ae68de1boSc8WQmXc9gzCcajhfh32uoEI79qI32cWq6nS+v
Zt+uR770y06HWRzfH7W2UjRU37gQU8zOLPdV/4F3wjFd/YpPIiFwf3ESwtELuHxKaAq86X9fhpUL
9whGnQH42ifRHXo/tL9vX6TLjjV+OtLirUUhL2lMRyiEJFoc1B+EGIQgzpXDrtLYKexS4K3ryP5s
BkIZbdruWhf1f4u//jv5qZ7m8/69hC2s4G4OcujzRkknP2cr7LwRmvG3a3WGeu0yM5nDWjYE9qOA
K9VrjAwa016bYmTRCE7Wd+V7narBQmlEvcuBPaD0+uKyb8RR7C+nxI9nP01mJ7peTQcGMQn7ngkp
TOuv7+3FYghL/Ym8QFOimB9q3LoWIL6imwArHE399l+emFezj1681g7VXIfFGmjz4K7Kn3feNcTL
m0/LwXDNJBl/aTWwtkb5gILBw50Xw9AnHkCvB0HK/Xi4RqAErILW4I3VbtFSFilj9PStI78kjZtD
0L7aW5MfZDFWyIFwdQqF7gwQVUxAVI/acUzXQ6ISQfPVEGhC3jxLoScp973aM0on9stc6kNQj+WH
8ggYBw9woHIEUFSC7w4tVRuzzw56q4+g9m2JDBCEpmmb/LSeh42EMEnQD9KrvUgt5KCEIcGXsCQ2
6cSchcpzy+derS20QW02Ip38R0BGgf83/FuJ58lnO3HBEtk5Cb3yh0qQjRJeuTJYP8htVtAykEEo
ghTZG9ZZvkDXiWubSUII6NXLmQPdKNUu/Pj3XFdSliXxxvtazRGNorABV7PtD4e1W4SCrjCr2o4h
iloAWeL8qSxKOd5oer1tr3sJ2GCxz3ylI5OnO9Zb+IrRTfDHmKvv0+Ub5WgOIZQ4svADBrFUWEmT
+jMXEiDNLse6kcgJsZoKlh3Ly6fiXTuJyM9cgKaH5/WaotTh5/8uJ3pn9nL/nXz9mKuFgcpPs9Da
E5m9G2L8C7e4SG3wsCco8Q8ZZb6EC8xf37luyDDb6GYTkojw1kcGppYCKIecNAGwk+NRCUJ3rHOg
WXDPwhnt3JPoSjqaspGIyHtEckF90ieDenI5v9gwRivtKriuH7LAHCW0E9/5nFQQob4elHrKGdn4
RrkzkDqNXC/6i9sHeE3c73cfh5h8Mf/AHXMXjsz5CI7HdhRCkLcaK0TkmzJSsZG3FRpJJAE4BoVh
3mOLIu0Y/0OS4Fh0HOERWqGPetIzTXXDXN257TIi515D9UQ0F0pexRPBVBNJUWggB8Dr1D2Lnpg5
wU6vDgTMLD3quiAtFfJNLf4NOoCh9RGC+Tm5J5McJAMDFF49g+3qTEdN54GlBwsqhks50GgOzE1r
pcElCEZZt1gHQmViyxfzaXMnuU+m7wt1u1oHMGOlDNqT26bXPt2vS4LkjZU250irAThA/58DI2NC
IgpzJGEJbbG+SHat38AjJb+3D9dce0CKdiYqaP0DFF77mYdj75aNW08oepNPEmrlAJwDm87NSnLD
TP9AbN+Z8Q+mr4OTIDcijwbXpjJbpSPvHp+D4S569R5mNLEf4+b31pVR8aU0T/0AmJHfY5vqtw3r
HFGSHmz2D6Qzt5RojW08kb5HZirG9q5ThxYw0rSqrtSY+2gKrXABZgKhd/KoLCeOAE/DK1xZmWwW
8d3zfkEZjabhu1abdSpgM6WepOmhCYw6DRfMfNMj+bUKEqT8gCnnWYLCeTr67u2GfiOK/3eeVaMr
7dV/8oqvindKxXzcfKt/mW/+CN5OXq7h5NX6uTmTa6pRe1lQYFhik94G4VnEbPbXM/ZuFnxfqt2o
vnqB67WMU5SKorOyIgrVXqHp9DSgbbwwiCpFADcB1yzMDxdzhfVohK9sSM39qSypreaND9Mr3rP8
NZnf5+lcNsU7aXY4Chre5nhaS3fBygPr8wLyqXkgxBs1FGpKGaqvHrJkLd0pmU9p0XxuXxqk/jZm
BKNu68Zf5gv64lYz4oPWVGQZ4/Vocc8O6TTw0xA/negZaNk+5GsPCrtrCrmuw8+YXmy5pwXf9+3R
b08pdk2TQYcwnNzkXLZyGo5jGxtdew6eq+nVRDy6JlSen6NZ2i1IaA0oS+K6F+/MFs+lgfcn49BX
vcuMUCiRGFCSHs6lvCsaEPkWOhv+vp6ZVp0soJxfcaMOpTi8A8805dBOhHePi5o6yjOz2OAUVBVd
3EM8nmBVIxs6alHr1agOe503yGhK8c7An2QcOmmpRoNT5zqzBj0WZ0ZZQ4XzO1xKnc3jo1DArJWX
X2zVrg/0TzD0o/rsPvI0PLHbE9yx0PFaMbvYb44xacT8FTi9Q/gqczGQ6w1bEe305PQBtzt5hOog
8S6vjYnFqPejd2G/zAIfAIUaiy+2/6WpD4yq4ZABUkwyYneKcGWX50Hre2++4xxcBxZTGOM22S//
aiFEXozy3KgRGYtumiFuR12l8hDGOxjJnugvaa9/6YjIvX0GqX39jmvLo29gmBGI16+3x8Twx26P
C+cazV68qfja0wB7EJj4NRB9j95gmjFDYrm753qb0MrUjw3mcWkiqDcMiS8yEjqQ5bs8JpdFbmJo
sVFn/fJalnnZbWFJ5zfreg88Af8Yn9nZKIfDoQV40WVGAzHLOvZ2OoKIf3jatj8LnwWhnAVJCKzY
j3k794bBm1778D0g2L0FvPdtpyrUNaEh5OYcKPYFqbvpspimhhpUH5t5+8SeephG9k/GWsTNQkl0
NounpvIY0wdN3VQH6sz0EbaOGi4bSpYHs0md810lEEWt9xCmWvvC0VaQSovmqE60K+DSK3H55xDm
Y0n9iYA7dnxs/xW5i6uFfsr1JPDHuIgoYgI0vR6iWzTFXKfDJUFrVF8tHDBcVgolRn2ZoJ+Fd+Qk
FicY8BRZp6JOeSRIU7ESn5zR1GZgLMlz/kTd6RYhIpUWGt19ZT7japsgEZQnXz1heu/sgcUL1MG+
S8zVWGWFTg9URKbaWcGMl2+IOZmXSbEWaGUwAnfJlF+kHpLpIa/BiBgEyjHAeESyKPW7H3PbkETM
d/shJBjCRHZjkc7PKiDGhOgy6k9+D6zUssaIErvpc8y+OKl6cXTSiSJzAit+URIgWCwaA/CJBBIH
vSOvNLQPiZh6Bz1LhPfBLhhZalxKPsR8p/mwpr8kCNcpfxkcfurBSi6aBeKCl2UgLwoxx7yKCXPb
VqgwHpK83+bvq9VDlQ63EtyXd60njfiJnZT0pf/2i9+BZxJPtmEEXJcSnfnujZi1aasXAZb7UEsa
7PeZwHPOM5VasBlQ8QJh0Ex4zcfLT9M/21NI2xudCUdNA21yc2Gawn+fozNOZNxOPGhkSWhlBIyp
8wF56Pk4I5Gzg5IhTkmiq211OoRLPvbaP/ga6Jgg7J3BD7HB3NPTKBjWPhcjlOabCVd/Rslisrd0
2TYPCWRLcd+VH9vqDo9Prcg+KJ/VSFtfxq6HQMh2riBMNofElwgsHtpQkjuYz4c8/jefqfR3YfT4
GJolY33rqnR2mfN16UWipgX1MItdhqU+8m0hi3mT8HE67slw3wK4rANs1VCdqDFy2GqPjyWCBSep
2C24k1yVYe7Q7oN9XKHzjk7J0af2nq23XlWhG4GW37SX6vlGUOdjAjpbOZ4twz82EZuZGDCWuozV
qxCi4cqhUZ2nDlFhCOG/Ktcx0BZ92cHSDHyHxYniojQui2VTIyWrnkXWUZAzmCNIvdzOvsMECK4m
2/D5KP93CGUmgKEX10IF3K7pkwMy/XldU8P1xib1USvkBi4W9HqirQoFx64TdNh7LMzPANVWMyCz
vYgU7wSAdo+NysWKRH2PI3sKuBR90pMsj33hhaR6EZPDLWcGk7BBpFblUS3TAz5VZOf5IBKUgamN
q9FRH6IQUxtEw4hMAMeNs0vqZBwUiWdKmIRFaAOUM/mF/2jaeO7BFJ/VQy05AloAMxT6f3n+I+IJ
sKcmCnLW9JXBCTdD0g7n2XjTcBvuCO2KavuDeqnIEv3nkv+oeteXPQSXHlSmfEx9AuGCdblw+Zda
Otmyq4YCBRvJAtcdrOvCO4QIsn38x/ac4FFNFbJhgdLvw82oZt6YzzrjTWyTNu6XCvBAymyqzqqy
HYH4kMQ2B4IaHlgNxiYyHyZTIUq8N4pMS8d2DqlGePkagkxUIaFgca0Uoqpv4cgIeAZ7ywQgx42u
PmXJP49DVVt8DhcBxvmehzU++RU8ILpFdlKeHvleCeIUQk6sM57vJUW9kr4n0g7euJPOQpmGklTD
Vv1n/FfyWYzRP6XSX2YdVw97CKv1jjMcTh2E9lEW20ORH4mOAgocp+u5DpZSDjF23TdrkwUouvji
47M5EpU90BOwpGKLbCyTV7459YqryGILkWpPwGdZVZGCDo5w3Ny+lEhyfk1Zoux90S311nxzz6tz
R9oVdiroEWeGs6gZMuKUvEYCsDkV+86X+GKAO2wG6MaHOY6r73tRRvt6TYl/6qJNavm3h3Gi2Sfg
0vNwdw/nnq1aTX/4nsTaMiBKh0Utlz9NpfzTAmzSm6A2Sbne0snc8h0UI+I2c1+Y/9RXZeA8fRdK
f0j7NCpwbP6JtaX7o7WKikjmrVUcX7ZnJstKTG7IDSAtqV2tHQwR34QAhRD/DNW4F1v6FO5bpMTC
HSdfKdtwR2yivcLaxlLyFJ6G8ahd5HMK1ux6NSHEuos5GujLByAyNhwNbc0a7kIfdhZRoJyAHdVR
DcZvlFWbGa/1B8/OE7khUsyu5kjQxfwzdm6jooSdJh075BZVByHIJ2ASw7W8GXO9bbi6sYY10YSX
nsncdAXOpfFVBfik7ElFvMcnDNmb8taFl9euN0Oc2l5s9bYQ5T7VCa2JDGeskL1Q2VVKaChttPEL
2NJv0vj11Ll/TjRPeeO8QWMFjKBnMWoTdKG61QhHjTfZy5iOeh7PgMTU5lWQq8EmpAuqcsPT8Krj
zgG7n4Ik6fYFFLCkZTGfIWuY1y+wLRbGi7XKWBD8wM8u+9HYMf2rHtUuV+yWJFVNTvVNJRIqK3dU
/9gjaKq0B1l/Ekhg1MxbrRCymOUeS4dpkQFaaUTmU/YMDUAPV2N+nArUkQgyK/TKrLZNnrycuuwH
riDcwc2sEwhRtZOev94qQCDdvKtOyYOf8W3nqSVgG8kdlavVj63fvJ6HOHrlWUdWt8/xAztssrQZ
U8ggIA8tvVBZJ5oFIwZ/gemLbv1aNWFtExsQpSF6tDgVw0x8O1k/k13HrzZx52I2qTVBXjhy409/
dgr1YApeX/5iiF8/O10u+bjCsC4fkaAD2Fo+kRbcyDYEUcYTpDE11raSsKIVqHAGCnKFygn33gq2
N05dPWjcO8spzVu4a2G9ZpMh154bdo1bwegYsUZK8ZTaBgyy+l0FGwUEgjSOkxXbgZE5pMGcQxtR
KQ1RBBU73SRR0xRpscO5OLOwkTs6aDY68Is9pbT0YPkRpliEP3VIcnLrv9KroG34gf29VaBuM1bo
t6cL0Glu5A6DgisXuCoGCSkuuOdg2fcdeRENwqWdGVB94X++pSwhRoK6zSYZfrfTuUVh0+rtT2dC
drAi48vQ7K5sfNC7yaknkiYUWUZ/KeMhPIeP2dYB5T/ELPyK4R/ATvmuptlAvMxNMXVi3l393Ntg
OwU1j+b3GuTHbAYIvZoAPpG39icz7XZjHDVKFuhvpSxc3igltu5JN0CYZtkRaSQfUR8Gz7jJ45DC
mA157aathSjVOny0ZxoCjKAYLVTkQ84Wa6zh78dTtxw1K5UtoVcWSgdWXH0sDQqzuVrNCNHoZBdG
/NyVH3tiAo0OXJP/6f8hggVkwH8Pa/0Ld7zIfMRnPsmVW2SAnQzqrlDcsyzxfpBldpm4cTnb0vqq
+ZK3vqUDaxnBl6B6pQdZm+b7wUFMjwiFh5GGIJTTNEHXFdMM9kHYPhfi+aVKyh8oNqwswASJd416
EXb4lATcChj3U5ppzGm1pUCvijhf2wwsBszAsxCoB1C6mWy5d5U4jyH+VAutAF/9juYzB3q/yKZ/
PNFJF/OkwEHKD6ueghhRnWhe5ZuzPZK0e4KVrQM8RqiLDccBGtxguWMzDKlKa4et+/kYCj1F12mx
d2SB/GJ1yQZ1oAcLDrK05TGNPRYGW7Q8TvH+gLT17AUhKSejOf+4XeuUXHcyzGAwJ3bE30MI6FwN
X8aSTALq0hK+1+CP7IOJoe8i4Ln/aJDrdM27P0XD48zUuWbDEihZ1ywJ/9dUyQIzHN4mNkgXtceY
+eUB6UNFY5bMcFMeQSPp2gDWlOY3sXxqExFC8KbTa/EP/qbQaaXyXgPN2K2xZxoWnCzC50NSo7Ul
yjnuDD1INM64OOWSPP4k2rFzQu7FB5WG8cgMrV1J6+Oq5AdHVjMdMtoLPH71F5I6ChTuhpQTCVt6
/CvZQYQQU4L/pWZxPKwduBJpWCbQ1jpu1ojGfoekzGG+Xizdjn93kfn6HE0LL/9Kqs7MPtsKdi2/
wW5/Wz/aaEz7zCgbNr0gNvmenO0LJLeU+VwzPWEQvIZpZRdFDfKr4XSEK7Y+IBsPdvUMLgNlRxgD
CtQOWU3j/8afMoHrShRcj0MaXqsZ6U4QdnLzuVxiXSsbuqNXACKsCZrcjb5ke4356nghY5HyWtrv
pDuleOCxWOCiZJEijcssmUHV0gDbYM39VDcSWxnNwjOf6FOXpCWJsJJNCYmR+IuS5QKqHUslso45
08a5boOeeYHGR4gfkLvgOklSOih66RYeYPL8yF/pTpxVSll6b6RPCirHqXTSrFs3mJM0jK9SJxmf
JFqhOyVqCU7JRK0DydaFg6i3mJCJOvaIRIfpzFdk/QxgmVTrhE8wZKk8BPu2SBSTnZIZdbXc2FB2
joOiet/f+uYTu2NItwKeXYBrMAPlWzvtmxo3KHwJRW9AmU2TDtY1i7Jvi9Wp4m2o0HFJH+XTSkOC
K0veI9B3foxJWi7cwuR6bE3eqt72h3GkNdPypnyFK9rSJBR/tVus6iD6W3+KLVBr5sSrdjXbgAyO
jcz9SK/VqtBRDk2Qrjsh+ni35kSfGoBwS6UlXn9x7G4fqXFy0u2Po+bd6Jit0FGlGRuy+nclwvI1
6rYtHbAS/PNDDPX6XQsMIEP5aQsn1W+XQ6sQieZDi5Mum2sMFxwHnga2TsQ47OlVBhsFVJKQ6Iws
U6cqQX3TpqlV/i1NEXT3H0V4hEKayRsT9cLgUw7oNj4i0OS/f4cTvOfOA65UbI4vO8R5ErNP0WLn
B521wZ9+IUHpUvFG9Vbao7KkAqnOS0nAlecUD7rRknrkfHs6wczrRO5xX+c2atTygtmCx6LnmxLN
IAukwB6nvcBqLi9UMxa5euMx/ZSyI2RBUrIpM8vf3F/YP4kySWtTJrCHaCgHwLzn/ol7OcKZkhMy
QND8ze+ZIssR57MlIGfflhmJ2vpY4xulWvRql9CIxDp8k8UatMNwdd6B01w5DrqUfsnng6qv8jMS
oHvnjOjxVAI8gwKBB1j1QdUAI5tOAFgKbDaxZ0quPs+ubLm5c+7SCEoemsi5M6aBZOByxibSuaPa
LwdZTBxH6l6aEw61GCZhcnhRGAmZGK5Oe+o1yUvVLYpfo6wD48hRoZs2fXdBAQiBHKijMroMM7Z/
FpWOJKUdbRoKlEtnr5HZELruSxD0y61eXyBpkF6TDluiZn1w0619Xq6dO7XtTeLxx9PZpyYntoUm
M+/ncd7kqYUy+zI0bt9CYzF8iSk0VOWVPueV9XaPkhLPFfQSZ8dIfenAvjh8VvBh5xUXcbSlrV65
iMXyY6GDYXBBm4MFQx4ZG5YcL2pe86ad8jR6RzJxPNaA7lddn1ZaodJHeB74oWTTkjJKM5Hu3nx5
NFoLZPImCN1+rlNGIAarV2xmRC4jMiOP+pKMhRQBKUJiwMOmggV51FG0rcVJZGECecUko9cVIpBo
CFHxAmHJzplvxry23JrE54nGRotei55OmeHVgNeOaiKbTt9DyXkO3aV/SnEMTaXOZ2usonTG3jBN
MWgWY4kFn5DyM287ZookEMcbgmQMF6MpvLaOfAgDhkK2TFj63Z/3MOD5jTkjSmK2K5DbuwX4r99C
FguTg0cUnISFWxENXQhzNaD/MNXmAoPuamfCB2mvRQZXhNjgtYqFxPiAeEaivgnyg9RoSKmKBpkv
OSy51xcHsPJdXf7s5n5EFLjX6xkD4fbh/2xBR//h6k+ehvdRtALKDEzKGtJTUTdCkkOCHAD0uvA4
DB9doOiCqgOldPV94mW+an6O00Q9Hinz7x21+CbTjxizAx4mY86swFYdpBwMmrJvV089IQbHO8EX
jWnE8pjev7v9GFYggmgTiAlD9QeQtjvH70jN02kUGbyFrirQVZ96GJtogVSwyH9vcdowQeMTYaPx
jx2kfqmaYi/yHNnl56KmOWZhT9qAjXV2yrtlqoZbUIA5X4zWnOoK9JsL1Z6Yb5/0L4qynOFvSiLn
E9xABDHfKyS4c+P7RGy4IA+lF0nxABX9VABqAReK2b7VZ2/5g91VCdvMkTuPf5Z0AzDyBj4wFdHx
OwCVXhe5RZkCdcBxsoLDRv9Vw5N7cpICHx5N/DGh+qwGkQSVBDu42G2jh8F6/Mn2UpEvog78koGb
XKMPieuE4DaFgrJJUDG3Ez1bIxFJT+BbMD7miEkGAe5Ak5lAfkBWviVBrqiheFm5PZGuLp+NNP0T
d2J+oPexn9DmmbbiOojhzXc7m3Kn4TSthiXAcpSdhMDmKt+SYbHB/EoisDDzOoEd9xabDPCLGugv
qmoqHTQQQWKo5iF8bVbnG09RbEplHro5oaJvWT+KnSAqA22EaZDDQCWVeDxSFsN4UDk+UeOEBeoM
ZDn7zGUlCptmnbqc1OTJW3VUwpaR2OLWUOLqqtmVOYykCXE9QfS1gApafh9CGeWNK8d1oM/Eu42e
TkGV9Ms93FBKlR3oEnoOqQqgICCDuf5vT+rSBHOlPgedXbysn83CFMAWvemlFodO4RVsq5Agqd0h
zsgEAEwFb4MpD4fLrFo/f9JQzWjpVRLiaUMq07/HChQY+VRhX/zCn88QO0KgquZOVtUaz0dPfNFv
4v4MXXV4fTGO9aq7qeWmclBYrVYp4ARXlnBPPe4I856Cl2ypwrcLMK1tXwEu/ziA7tP2tpJY9fIX
uMNkeyjnDkTG8M3VABqpzZAWZYI5pZ7N4kNoW/GWGK/qJy6dE0X4y4lviUtETGljm5HyEb3T/5Ni
KJ8u96BXkxfckEgggzoprmYuZDNEdKZh5GSwIHB3om+Ve32PBAMshCGY9l27hhCMIt3/Bo9LQv27
ZrT+0O9G34xwG9CvKjVGLMO9yBvZ9ss0Cig2qp07XiZ7sMir55aNgpWVk8JmaR7Oz3C8VVeh6Hdl
qAcpRR3ctMYuxRqhLs6xsN9rtLuMfOxeiC/iRe83AVOt8yCChLCBVSx9sl+Wa5XvTEbRMZOPkFDr
eGx3JgmeyxbQZF+nrUtYRtcN0k0GcK9oZJ6Q6gRU6dUoX2hVu4TDPKizw0AcAWtj9JhyE9odwv72
EPKEmuIBVFCa3PuC1dGB+p2Upx2sNXNgekrMsQFv4h5azncQvRy8Zg0Xl8ur7hX/IFpc+QJoNSIJ
JbPv9KRLmTcd5n5pnGMxneyIUXroc7b/IPvlzT74M1dBy/e1/yoRZwBSpm2QrSBuaLMS7Vw4rQM1
f8SOkmLYFKUaXeatzM1Jjco0YUNtdyFMmfxONOvfvOmPFUp7PtTKQi5ipg+be+kZBzD1+fD9Nwgm
lnMgJXsjXb8xjuCgVvP0T0liGTA2MPlNJuRgiDfqSZQdMgfUfv9yEym9w3wJmYMVs46NjGNjdLsm
/kJ7MVy792Kgz525lA/Mfp6DHB7lnRz8TD3dOHEXy+HXKXuHOlqzk7htoJTweOeGqltFW11sAXa6
tG0kmFXoC6YqkwTx7ZkxUzBx+4EHtYWpUD06o9EsQVrJWj/zPIBLXCxvRwsKKaJAMr3KUiY3AfhE
H6qz38H/TKzssP9iWTK0rRbdSOKE1H9Jw6pS0v5D5/oP/t5UxT8tgF++c0El0QNVSWq7kubp4Tkv
Z/Q8FiysB97rE03WwuhRkFvLLgW+VT8qpWwt2re42ihBQk+yIgYIei5apWlGWIjbnGzjYW+oZk7e
TU87Q4sjialzpXqwBZqFWizrl24PL2HeBTbMUTYdZPN/v0fXsh3i1Fp/CpstO2+acVyoI9H9PxHG
WdJBA6tHeTfFghfdSG9yrR/tutXvYCkwuiSJsZ0B75Lyy33a3DWkkh6lixrdsRcl2+kQZHzXkAjx
3Mr7Rb9StGWsCYtOzhu8OZQxo+MGruav4oGJTs/l5ywXoqYYfy2YiM3uroEHiIf6PHDLzy86kMIa
iYbkWE2JwlttdRNilPSZlTR725VwBw9z1AIL26N3Q4dV8klhI9mDFaBzJNOjWoxQg6dkVHq8u76T
DogTWqgTSVb9ydf5IpXSN4cUL2jj0Zf5TfwGpn3cOd7e/clA1WLr1aomZb90GGGh8wCJt0SVW2xw
OU+BKaUkA7ykGEO0T7QVAMTsuofOKX3Wfoewka6wMGLaOdw1Z+alM6sZZbS4jC68ugE3RpjQ9yyT
huMTBb5S6PEO3sUwbzwU6xCgXGH8Mk3ZWiwlgz33WV14aZbi93nsDGqSTOb4iIbd9hEibrACo/64
FRlbH4bn/jidWLWdIvRtqP9mun21/kS3EhSz4ZWLqLOwSnd3dBH3GvNoBuStc+f/CGvB/IL8SJ9G
OYsIamnfOcgzuEJ9YZT0G97fCBRhEhGmLy77vVsWmys0pzF/C6dx7xBPjdnG8+EU5XeKpIAuUt0Y
urWdXmy6IO8beo3TBNs350Pi9u8TLiSl13r6f8+YNKmj0vYoikWavMP6RygYhL+QkXvYFNZRrxuM
czXEjfDEhc3BEjV+2PUB4SjhVfXs4DGyTDcpt7ubokYv7jSWYZDWihRcN1o91ly6WFbTnpfDG8sX
G6kVPkIGTFvwWzrWewgZMOGnKfpXAP/ZtZ8iZk6KXC+2kweuQLPlP43o4gocxjuc+J+JNYv4fa3V
0DlMVUUvpRYFGa2Cc86MVjSHq3ZiVAsJoBiUetbRNaGHQSi/C5Y+22dvFDqWJ3WlNN82Qgfe7KZH
ewyIc6yYTLa2Yf7tKKZTU7+lSlXTgzKuvuE79Eh9GKhn08aVWKSerpoQf02I2QDEIqkMdKW0OYTW
7g4Jb1pBkyVcVVITM4YIoBW16F8rSI2/f3zt8IsOLe8mgpy38ySLl7Cen0bJF/MM2ULwY16WpPu2
/V7sQBsj8P9bonXUzZ2g7BYSHHm6Igp36ME2FBvoISD02F5aCt9blDVuTrp77kXLsYe9B4DBwSft
yTMGWQhOKH8V8e5iKY/HPwz7bC9XymqzcsQXbNq/KNJ95CIsqjX0Sd4IrLs+9+E+6VzZNZoVcIvX
AAVePum4E2OWYUpxAbMkysDcx6LkRrVit1dURriQgYhlx2ReqsHgRi4ZmgpDqJH+2DXtIn879eXX
SUTL+7u1ShKYz/wv7SOvvmD6Oa96BoyzIiY/no/APAtuuMhJ5TZVIy0dArAaXNnNYmcCGZy21ybx
6ni2pM1crFLKkmEvB+2+vrhl8Qw5XnVcGL/mTj+HmcRnrsnrcJOyFpt9v8tF/DVF04EUqTnLf/Z4
LOB6ZhHDkzwBeSeIDY6mD83e5x0D8EeZquowkpvBUKqHw6quYfm5BGgle68ZPAdEz6s3452Ji+TR
IOfXtZMr+vFlCZkD7h14Bp7w2QP1grw05hhk8sKUKOxHKfkZ8pwj0rqNX8Q5b9EYLN1IfRDi95T1
6Za9asyNudsuZpbszwLgs1kKCSseNgVOcsGKs8ewbFMEIaEUyn83MShZK3bn5JJl38uYX785Dr/s
XgI3xSktBLVQcCQd+gRUzy0cwPT8KPJQPzfKOxjy4pE+ksmK2Nuioa+PxN9NHit57q+107B7N8m7
TcpzqwDFMFQRFUTnzPWOSY0XcUbu8IaWdwXhzJIKyc2lCR9v4vf7BdLXNoBByehzNDuJrOCG0kxo
tV6sSw44BzQFVsfMopeqn4/WUtwaOuj6+IKwKezkDmMnRqFeu2hM1bdIBn6VgLC81O671FwSOoj+
yJbEMRJ07Lh09Uh51/V5My08EWtfqMCD59nv1M8xtsfk43IzVK7hexrFEQ6FXBD7pRsng3HV5kXo
ls9x0ZAh4d0pdATsFGshBxODwpqRvn/3P4PHJlfnBuJjWGvBaq9vLGrHdjTCtPo1l75ENss7tRza
8JU0Fse9WHAnglHqiX3nhlEwSwMfam3S1AR1YgKVnw30Qta5PSpFCqBDqmbR2Bd5I1CkjpXUfnVG
+vQccXYrCACgFgutiSoE65Vjgg+trlqlaN8In5LVM1Fgs5BmQkc1oGfIe8A9IgY+J0CPsCa4jKS7
LYQ2ftAJr/keoxAO7UL4nKOb+p1MsIx9pPynMrCX7oCcgxu0UDy/RexVPvPyy3FIrlMHFrm6uhFr
7Ky1WQFAHQJLMde2+D8mf+Ufg73SVCrNXDxjhYlnNSIniIss6du8fEOZbKmmFR5UFDEbY8Xp3NB7
p+uV1O4z2K/pZOCHmpnwFBjAB4tRplAWviItOTCvlj55ADE5TXYa8sj0VNt3GdxHPKms1nbI1Soa
U1983jLLODg4blH0xY76p0nMVlfdlx2HmQ0WCxX6qXM7KrPrbbb/c4eNN5ddMAoE1/cHj44OyOJk
Ok1LsAXqG+qHteIeRjEYbNwqEVKTrHnfGitkeg27IvfRIwqjCX3brArFdhI+Nz3Ul1XLqv+uZuYm
doa2j/rAYS9HzUT8SkYbfTPERY5SLt+m41C6CFaYleUKgbZHrq8r1UojuVyZT2YxJwjp/TOTeYS8
nyc67qDWwg1/zO2SxgJRgG2LxLdLwMmHsDaQhxv0PVFr5gxwu3Cg9T6WwwIsOmJDjUyIk5K1bLKG
VQpgcxBS2HHA2yqMmTd6Hr/NTbIXKbN/EAEB/8XWu8U1bwvfNYlPA0SVFh9wbhR9JD5zaWj3xn5U
RKNZa0jVbtFKQB9UpSI31bDCfwVyMDyHiRLKWIFix36aE/4UJSBEkBLPALOWE3ikSi0xFQkjozkk
L2Tg3ZTwOXYYf8MlQAyRK5U7OBqKReZgsH0YEGH3bPqTY25OrR+q4oKUkkXiibZwFdCCEgLHcmdf
fVv3VNgv1K8bT1rbM/co1Vu9PGbwJLzAyJ2Bag5iYTtEqXjr5fmby/MGrzYr3F8EK5NAw7yA68y6
11RxrKXv7rxUc19g+SxHRnu8b/Bu53w+xctLDV9yx8eXPYcnGZ+tuYKD9Dij/bNspf3fAF9hRrLD
q0Ifd82w4i0gwqzf6LUs7OmtgqqEGT0HaoDBbli6W/C47TfFOHkLwNhe80pSLlYnIMdWZgJ+oKmz
/Jhy+ruMcsAdlMz6hx8/gu6bsQdLL2CgHnWq/+JzDVM3a06tw8Nci12FO9TO1sNwMh9C/RCBkw9Q
VdK4SeobMEVeqDcCD8iWMHyi3NjLCmswfUgKwu0kFHFgnJ/DeupoPgFMw/sy/NAyV0P1cK1dntUp
PY3105qbKWvkd+haV8Ca5nt8HR1CwZK8otDaCj+wHaj3qp2DLEUn0XKNqqPLUmeTKxshlgccZGk3
oQvBoC8KxSEolIrCYd0rImOax9h13Yq3SUylZA4LDt6KfKys/qBGZtVfGq9clZpxtPpdCFPm274w
jVmzEmIBwSfm/qHHvQKB+pg3FMB7MDJS69Mjz0Wr2yAzTewKy9B3FYJMDJy8tNXmzRvauUFUgP7E
YIeZB3laPMGdsfLM5xVCHzeZG2UhMuRMykPb7ozHxbT9z4aKUp4gFq2VFY50jgyu3YUvxAe9x4nG
IiXcJz/sQ9TZlJt/+uRVVP9yH+3/+jzYCK0mN4Ou79TV5FI1DFKDrE6B4UszztSD7ZnyzyQwjE/a
4u8arvnqQJPLdHV6KsuRdFX5676lzptB4951T1bA8NX3K2I0KA+5PRrjd4K7NV2PzDnmuP2JMAmb
4oqOJnVeSu+g14akhs+k+D9NjKfKBPe4y7YuPdu9ry7cl0Bq6lOYIf9zbhbk2gMVSwrv48JfCljS
udnFtAQ0P+aoV4nON4SI8BUXR41kq1QgL+8Vhzc3CqAyBoFdpIVIa7Q2xnp4cx2zJyXq7O/uHnHf
cV3AHx1SXWU2nf66dEiz+M7QbwcaKJ8CtmGs+cBY4kkIQfOaf8dieOx4Ma0DfuoJrk4N28BlWGdg
jX+AMC0Fp87EgXXtU91Y/lzJ2tmADiJVi0vxOfWM9QkWcsp/h25ZlT1LYSlF/c981GplEPisasEJ
Wg8bUu666iEAswbM6qgKx3OFIqtmsgPvUiDIk+wxg9wvbUNWvKsI9rR8cwHkzDdfY9/SVZL7X2m0
EfzoL2Ir3qVD1Wj7kdAUQQnbXIH9hHEPHuZQSjLYQWoeKNTGnVWEntgoOJDMvHb4jLxMwYFsKycI
MHdMkyGVl5BqgIQuAa48wAb6M6mpwVSiW9CSYQFnUYYWo3qdAFYkp2L3AQhQiRfsomnqgemPJiL8
LoJKt+rrsKN0dKsC4+z+rnTzMp9Xpatw4N7ktNzNVSjJv0SP8I1BBeaZVym+mYwWBXGrslnAnLQL
z9/FDvIhDZVYaNcPy7hN5syyKJl/sM7fjcAUUvyopHyd9uAy2J7QW/umeHXxWpooxmMcw/F9pNs8
FgjncqBTppIbVPWd870mOrr09eTKa0Qq6SUCUQK7/YUGEG7QB0LKYeRsHYVDD/jzmjty6Clofbcs
dDMjWk26NnFZCtkY7bD1o80H9/LAvcLrbfTC1CEpgvhZI74cBWsE3acTYv/S65CWTg3esCfyxmlh
QUbKD00YXTTt7pEmJKXg3VP2tJZHuhZEpJBa544Mb6jaHNoQZaoa6D2zRbpA2qZwuEatMndCq3Aw
BwZfHzIVjw5f0KxWk7TFXEn5aPadaTWC3xe+G4rjIwgHMLJAguD+MvFCm7K7Y+Ew4UN1kJSb09UQ
/lOohyxGu92HU0vn1SAuhQB2+AqfBLXh+WkIaDS8tawzyRBztMyWiWUVE0PH3qr+Ja3UONaQqINo
pH5Rghq3ss7VrsyghCGXmbCQ9c/zgSe2Fo9eFakchBBsVgSz7VHTWn1ncrW21Ogneyp7DLcBvIZq
k2z36KMBmgplh2DU4iH+FXVW+I8NYwSxTfDV5UTQtfXcgbq04GdMPaFjTH9QvZROMoyXC61T7Mwr
yLjZb0EDQV+ZkVAyVOLgoG6xHDVBTQ6ALoL+9R2EoHpNRB8GYDRowWTQZJoidvuq+oFjulTcGwLI
L8wVDbUr3at2pCnB9ENHhV4xWD/Pq/rAezI0amHMfBat7+71ibRPPUPIEFb/UKuDiPWDFM7bi9pz
++Qr4OiT3fvkXDB8hEYHagljIOnk5GekKS7j0aQf4cbYlEjv2n6L+zJgagjIs6uctih7CushiOio
ZN5jPV/jhkTR3jfQwveYG2RIrZrskMBjFekUnLkeGfOEBpkrQPz7knW5zBRwZsypdgEaLhHWvkXz
EHjZt/EAmIfwSY4c/5fCBh0R0OTHaIzlDO4VsuhhDlonUQ9Cx9Wfx8px1sUL7WixrGYzSOYcvuyS
jO/dXRFoJu2ABtZq16IcWYxwmli/p2ZoimmG4I7DeGlwGPo9iZRBoSDh7COX5G3mPxRf6ceqHjI0
1uyhP5gRgfezHyXxFQfIQD/VAuhjGhes7iDeM/eUCBqC9xEGOlwG5pvUfUG2iacCSzI0l8h4KIeL
2buu1hUkJ3CtfGu28AxSBwapECMIwLKsNspSrLQikLx0/USYu/CyBAVp3v5hBuGGSjDioVAc8fn+
vsLNanoKBTGYWbf3+JDH7UGr5uKU2UqMOGiYoUYHOgMpSkrrE+KzofEj7NmJH1FOzSBJcC8tVS/y
HvZ9UaadPkm+LfoMfmfy1fagrbwZCBe1j/a4gSZdn2FOMXCCj40qOJXXnQJhTGyxSJIN3TGRfVdQ
ygqr3JpTnGLMp4eKCWogwBBO50yiJ+BggT5w5hpK0z8QVVukPO7OlqWAC+jahuHKU0oCoxwKbnqW
NZP29hEQv1whXGlTm1jm5qclLl1AeM62tTOeDPdKreUJ3TADhrf+uCWm46P6v3JmckRiACm7yvny
EVTQZ+onJxChA3Jw3Cys5zqgu2/vpf5tiqRe+829WcVw9UsOY2haxw55xpdGc1jOSEdVQZ/jjeII
BtiEUN74t5007Q1zb0nJBJ6LKIJQ7NN+/xoxq9h3cQTVYHiJHdCFaV/KS3OuVJFXblHHxwrU4dQ5
nfEwvP0huT5cjQ0r+nYh5fMhoNSgI03H6R4B6hrf2v044q02k4w7dSJIlPrxg2/xm2RT8RsiXajS
LRmalm6397hW0Avykqd5UbFBTHDIvl8fodl/EQdAllH7NCYen9BKm7FbgnVOpO8yNarPiP4HeLVc
rJtyZ8fCcamHyzQ5iYERpnP5fn2vVtmVhwxz3sW5hPVU5gbri7Abo+Raehc7B/FsFHrBeyPK7tw1
FoEcdBt8Tb2HoPKiK5oRzbj3C+GcnJnC2kaIBqF/42p6qnBVw2s81vLC1o7EFTn8B3NBtbqxKFbM
nTB8pavP/mDbi2fQHynUStXZ5FiRz3qtaIDMqjE7jnMIdWxc+TWpafK1kdxzzKjfDsEWJMmwEx5y
GmqveVZgjUN58PB5GmDmvHqFdHPRVHJfOzbUVHFcfqCeBd0ILFJ3wgp6nxN0TsOowxpYINFdfCT8
jKod7eCvQxw3mBXsmBJjSv+o4IFbAL0zuAb6Ep232iDqZO8caBZaDxMUeU6XeuLhj48NeHpr/sWX
tdpuEXsjaI/5vrJFkQ8ufw05/dUeXbnanT03V2F0JaHaarjkym4lTplI8/Z7wqEiP/uPz2wgFwT8
ENCvW/OJR0CYXRtbCNEUzVFduCshILeYaGidnlCFhkUNIi+fd1u0lvlRM6F0p279ziWoRdosazz5
HUaR97kX1EyyFNlcufbm2/AasbXfPxt/tTAi/pRwO/JbruktONsPPxk9EOOCaX/pG5O75VYABt1p
ne3sj4Xjx51s4A4KAS5XGAKkam+zUCGdLY7WHVfobjwPmWaI7uOcMpSp3eOagtDI8A51or+kbbaZ
/pTsGxBsy8tHOu31/JTLcIP8l8Tir8jIdJKGgKN+UYs4f0opAHvMxn1TGZA9eLb/FdOpEkgL58RZ
mfsAN6eyviPyo+OMLke0tRQxiEF4/N63bH3l3e0V7i24jX3wpsolfcYdlz307jRTWgCvAWMQmbDA
FVZn9ndfeCGTZ9k8kyB9HPFUodLr9K56vGL/JsKw4RWUkfa6x93M7hvbiNZ2QJA5JB8jp0eXu1ET
Q732F8kwuj1eHo7TgMl/0e1AMVzs18/5qZ5ZrGFpcEB+FM/5YjzVQ6zfxj1XotwOcy7dZeeDVeo/
QK8+DZ/znnyiWQjbCzv8VRjFQ/K2xD7cSfPUNIZgJnozBJ5DNvJnteV/oaKFQo2h5NWZOrxqei6k
fIx/jOEG3BafUupnVrWHhsEXyEXtznT3lACNoBPkJoObLuROakoioyPAJeCbEd4pbJLax/8I5oTX
EBXHmslJck/PjJGjUZU2jf/bwGLRLzZuSk16CJyyKLH7fw0FeGrbYUP9yyrstugSM5A5r1nAJxq+
cq1X4086tqPbSkeHvxRYl91D0OT/264/DQRhLBWRei1A9a6Ct9vkqIC6APFI7fVB3ooQi5pArmII
nt9mVNu4B7qHysru/GoQ8lBhemz1fxl6rEJFVv1aTxahSlYWMcM+NfgYhdm9urcl8gpv1BAYIKj0
bdtDvS42rMSdbZCakAU3vrCWVULZrlXEJn0GdGnpzAj05T/QFFKa7374EBfCulZXPYiWjcXuDyFJ
R1zsLiM824B2JtGw54ZOGQkbbp1/WO3dRw9+In5d52sbq0VKlyhYsS9TUDo99C0WUXSY6dgcDMuw
kb3/bfv0YPJJmhzcSBuIa0ekFdVomf5Kdzzs8KKdJxDINYxzfKlOv4e49o2pf8Q7MSR50SOR+/n9
NaMcCQLfncghLakbfBdNld1bXMgqOs0AhzZdcpEg/lXeqB5BPN9jWp3Fs3e4N283u3reimAVMtfA
BLQKbQRyxZ9D5K7GKwBewxO8wLPdV9P531eqvUy3ppnU7iqv4H/Mw3+ZeQ2MYjLuCHObfsrfufxg
4CEwgkFsjlqCxMeDoXcBoDTsEdCY3lzqXa7fkAsCtSz1YZyv3UaYI6PeI+FR25nfU28mSYvcd8jj
+aIROkC/QVblarUCO4VEBTBy9xx2vtpM5/yKNgvb4YzCFDrkqni/KyylRq6Dc7lxSEh48q705Jbk
ACARuCq64cHa0T/9nKtKMugluaTlKyBRHmUWNILCrf0ffRz9XngsddOkYdsI0hKXpA+pHi/RSSL5
C2Bp2oN57PJOAk2v5YSx3Ku56iH9VQXQFDOanVWo6I2B6V7hrL9Kyj96Yy12kb+98lEbMamuj/Eh
eILvSlJO3fqnMERsTsg8gyZhphDuYhRnwPRzXEpF0VE857v1dZRjinj6blZPakt/2fwyHtT9lv/5
9kXAucDfSsBvZHRYcItX0IlYMWgEtTwFUj4c1BsPB5ka4I/4PzC4a2cFw3SeoOAVvPxYa4m3DKNy
4kjXbjG3L+goipS8CquRsaei/GpB1o/Hc249iiWfmCD283boGtu+GF2DhbM6ruGdIzUBkL6JdtHj
dQywCoDJdZtcQC7K2OCR9zvvr7HDTI+/FbqbeEdlFA4OxkbASPuE3LPBAZnQvN5jpEkHofPHmHNk
FiaEIybwUSJnfCaNKhfXHrJmRtSQuCon3FW+VwT7fSgQaS2aIyEXP+jex+MsJUNG0bs8pftiepsk
FBG5pTUnXjfC7CJxv5+yP75aYhcKmneAocJN/ynH07yBa5jkymVXKLUc1d9fu1HsetCKMRiMYg47
NEl4XwxKVYxa8Pr6Pn6B4+KrodRqSJqqNW2lX7zrN+XNkyvqFbZ0RwuULiw3xDAn9v5zFQebphJQ
HrAfMop68336ZNLKfbX533XLKdTRsykUDIL9NydDNmpNYffSylfSrTNhOWjAxtN9q2WhcNVt4y4O
oljQ5/CX23RRDkp5DqqVD2pq2M/ZfhzJt6yVTvUZp2L0eyNLCNp7SSy1Q2XSeg+In4KhL545At0K
D98NX3ZBnJ+cEBnevcdeewfwzWfxHSM3gsnnxsLSs0g4xtWYH5QTLRo4Pr8vCAA0cGsl2KHiNeuZ
L10C38E7LOIQJzSDGaGw6Q387rty8I9YPTau8apSCPvbfUB/ueh/ibwYxPDmfkh84j8ksQCf1zHg
ZGfeeDM7bVHQA7k6nclYgJIRtJsxO1NEBNuzwdigPvYlSlP6Gr1a8j0fDbJl/EF+R0g4EPi22Ksd
1tq0N+nA6i29EXsUYNnDQtCmMmpVX5+B0ySpf9HGuhFhJLxZvi+0Jow3vA6DFI//Q2vfgOzKjuFL
PdbgwIQL5qbkhYpXS81OB9oZEXdbd1u1V6Y6cxN1Iv9oSidFyByHrQYzE/LNL70ZgVpbl5vK1mwC
delg/jA8nkkB8QPRf7EyTA9Blt6Uy50arKFgmvNsZMflQOu1xw+kuuvBU3oK0UvIVl1tzswNx7tm
H+Z9vBZw7IPYKU59nY73WG+YmXktdCd8LkQqmURxf6mBJsKCAWpngCW5NkZQeiTpZgrsIp7kY2bf
gkuNOhsbuEALk7+jZLf4O9Sovob82vFor5CMfHeoEK8wk2wPt4io4cW3eTfoDu9tlAu/YUgKWGnN
0xjoSTFv300PKY2SYVPEc8qyMyu2owtG6YpVb10KT2MsxUECPENv14S4f1A4BTM+FA7+rXtprBta
1Ku6gqqx/CjliWA6MbW1mME1A/CMANDpNansrfKtk5lmNKZ3tgbSWBjH1/Oe0nOaOXdprXy4I/uP
BCIsC3IyHln8hzMEOt11hVsM51E19ru7FFHg9c7SXGMKXNzE97Bquos3ZtPlH0uH6vLQSsDQgmZ5
1nTbjXH3rVSqYRhlFglsnx/QXN9WhsTelSrKCMiIVuroiKTtHumKBnXe/UEza+fj78qbkmR0YTEO
wK+n/hCh/9ryK9IO5kHOkr+Nn1tli7Nlv+LiQ030K01g92g1o4xYQQSL6F9WJLBklQbgq8yfzNE5
VS4Xqlh/8Y1rC75XIfC++P1MO48xfykOm+cxz1oOwi2vStgEDz1MZ17inf4hcgWAA/h6Nvii5H+2
R+dXZ4OHoJJy24nFb/zWJe5BboIa7KjsGjoB+hPBAhqNfpQ6vnYCCtBLOHqWuULVFirGnZp9wwZM
f6F1q6l/QVrPFUvLHBGAepANQKHGx7Eh2u1nJjYWOkXgjaLdQc/btnz3FCS7yxu/Zz6iVbOHmMrL
EnTD5X5RibIfrZYoCWI3TO6OvSMzssLrDY2VSxq1SFpEVyZSTgOB62zgTtKUtQ2J062PRwfY66RP
o9wYryO6aN3pXdhupulN/OeFGTKqk3jUayHtv+jKf5iPRXr4bUXCli84iHN+KTTNYkN6lACY506K
75B6ZydB58FE2nPPitcSAc6bsmARNZXm95nSVzarrHV7yuyAEhgJaNCnReLbEaRhDLEIRRaPlcz7
FBYqN3vfvDlA21OodBDUR2TXe1ZGiHFr6XmvoTpMom8DPVWTUUuZI0g5Jg0g40EPhjhzOk8Zz1Ph
xGKzJZX73xABbM1ij0OB1kk12cdb1B3j1lm8lpnjDVd+0lWmsBAZW0ojdRvzh0p3QV7leD7nkeMQ
fbu3uV1PreP0f8l2TPV9USJTf6Oqu+3HQ2KOlxMrQwfjy74WNJH5psIlZHf8QbZNSL7gTXf9aVuS
KdNaLU9exzdPgQyBTodB5eRmvOBW+pevrCunpe9jUhR33o73eNnLkvzMwqCG7brRRsLxGzGR20Yt
wRrIjdpZLJj5OB/VWf8nh6C/Rtqu7RXaISirZTe4CggpkktcarRC/FpDSxlqxq+4PoQiIGdDwgvg
xv5YSPd8xgw93ja0CbrxKrix8PVrKRbSgKslvQjQwYls3ctNJnPba99298aXhI3gQClCbruO6ORc
rhvXVL+nBmdoWv4dKRAUtUnotcVy2A9jfbiwCn7btPgh5OACu25HgboFrPsz/XpHWOdp4ioQEtrX
c4ZXavcEOkdlUmFNmmcfvocX4XjPj3sA+//7twiemDNo9KW45jEsBenrIk63X+xsmBHcADcY4r4n
HH+rQTk2BquAOtmjQCxRRfUkasbm34IqiXLSnRrFUz1MmpDBSKCLQgD1OqJ0WtQhaf/BxgNa42Kt
IE8TbA0DE8HD4xpZkDnBuXWFF2HRbjJ5Iv9TQF3Emhb05oNuuOkrAGI7UWFWS4/wjLzxbglNJV3z
7PzHlB+3D5Z0kNzZYCVf7b7gQ8ZioanFRTPh5L6mtCMmg2XNsvuFVUVhKfrX5zxLT3goOkROU9IP
3Yx0+2SNgrAKscrKfTwbkvy/Yvup9695KjNhDBrLEDYBVy5lZPCCf2Lm65ZkDriclSKaDS+Y5ErQ
XhH0vVegNVCYqA97tiF3LecUE/Fipn95yTT7Ja9qMf5glM6Q+OqdzhJFgIP01OiZR6x+nIe3TwK/
5O8TKPf/fgeywKs7siMjjtkF6v0UFD5CQSKnn/Tp4oP+MjFsrtgswlOENK56EeXRDkLyOGSFf9a6
c60k9TVQK0PpG5tkXxIQpIe5d9BeR0W54Tg1/dAhxwc09nfAhRYDeT2PkL5dW897XY9RXMlVjfon
if421oNrdKFaKenoFXYXN6wuS8h1LYdUCA8ZAUybmSvBu0cigjGrIXpacRr5if8ip4MuXbBrg479
DAF/SFgXItNc9plU7BPY2Z9F3HXUz+l9NxyGkZfuDNN1C8GhjMnvt0c9hT1+Hfaa4k9ylrOaJJF7
wtf2NGgSx/xd2cVH73k9sbw+iDhraOZTYfdh46UcglXm+i4w6sdDHC9CX6kPAAoTNT1MThiJDlCj
fUkSnbN84P3ci3xCi42RfHqzAnCIRgrojBTMev1LCAqTS5AWWqjaCzAyNhiTJ4guiF4jMPkp66P9
qi08BgxzcYJYk52lIkGHQS2mxIxH7wKyVw7H9g2KCE0pdAjXYuVZ2yJen/nL4o0cq1gdqIolUjBp
xYuZAHxrymZIHCjdyKpIJ9geVQpEqtX1IVTgC1eTC+lz3Gvt5AW6gOmdnejFF9zB4+l/eSf6HfwR
UIOQom4TkLMq2VjylYtJjfC7/x1iCwQ/YShRgZPTDGe3YMkb3xmRO6XTBrKhLwb8cWhCuba5y+zw
C/NnWjbwaLyL2BCznR7lZR7mnk/PvSa3Z+m+Q2xUnrK+a2ulYOScxTCrHky7j9ejBvUaPy1ExLic
JXQPuawzD0A0YP1RAHAwFPDnRAAlzb2jOb/QzkhkCdySh7+RLbfYqQO0gk5K6reKHQ1C/uqRBfHs
EbqtmueI/c3j9r6PQgzIgrdASsSZjmxnAgMbmtJHLef0/LJqCEa4iAhhgF/vigyQJVZ/ov0LfTgR
MSSDvgqQURX5cTtVZnhihL/sD/IZs0nWwmVIkAjPcG4dI5BjNwFo4ZPQMMxalCaP+5cORl0Javfh
iUgyDxBbg12zFM5zNgXol0F6ChKNYBMXdHcmHbjEZpKk/sdsXkCl9OLc34NjyaLRCNUGNqDABGkL
sRWzEZbgfVXyYWYjYXpGfn5P69B3E1zXQ05J0DsWyFiEiAwknsRA6tPde7dZ/gTDOXEtbzdpHyS0
OamIsI/Minb5bgYZ2Hg+ZL3XXlX0GqTMvndpheXQdXS7edGxA+3dXmJWmWHtNCnF3LKhwUQHe/ar
jUgzTrnjfCAhRU27jtok03BbMptnRxaBWf3sYdKw30jBUFh+0TyqwGGCn47DQ0vNwnwsS/6Xeo35
imGfKC8UEDI+mzuGZ692DpC6c/LVoTcrvtl+dHCY3u3Wk5GEjhSH3SoCLXg9+cT5/OKo2s9lsxMc
OWgIkMv9f97uh0fYLSEWFc57zB7wSLXS+dP2d87lJYvQ8glub4EI9ObuHbDbpIrxPDgbWXtOE3kZ
G1RyYXJoC1OStJSGbtB02BPKzXi/Sd3IPCsm30JA7hWS4QTnh12HcacfZmkPy46EVsEF1tpAUN9z
h1yESw454zSMw62YCP2Sd0/RG6eoonpXyEfzVD2zWiASBSTzTn8Rjh9+UTeywLIvKNg4Rq5QZ1NH
H/OaHZO/CqeKNr+WLl1+TplRUR4zcDGMpJqcW2BdmU50kit1jNm4ieI8p87sB1v4avlYmljP1l6H
Q0TTYcKGJbdDb4fXTHr71Bw60M9dGzAhdg2L5IdRT8DTCsZQgJGOF8+Ljdn3qQ2YQE4I2LVu7xep
guLYja7GzqZYCNPxiRNtZvw41oyUCsJHryWcgBs+5KzezH6/oQgPX7bQ+rl7XC13TVAHnPZLy47L
15JfqlJOVvaDO2daihFF1s9V2eKnzu8u6P10MQBgMAbdmxQsinI3vZ4DiKofHyC8xJ6uo7j0g+tc
FvdQKXEm4awMWwb8fD/5WEq3oZvN+IhnJIKZ/AeZNcbq9KOMzXpte7woDO74MV4NzwcDuZZMIcQG
ayx2m1sYAQvnENA9orF+iT9PQo3bwHMwrBLLAzcPn6rUDRAHoiTACPE0IL8n7ZNKPapY3cP4eA2a
WrYVrr9A54NG9e3Gqd3ww1tZB2WVOtU0FlfGzesijrHCR2Ww9BAb7P1apT+XoAfQEj6UZUQA9YIi
K0jvxUCNrg5z6rci5czsEVuwN4ZEHgL9uP/pSqDdOQ0auOqIUwv6oBPyfaeAmC9UpzgRixHzPkkk
wvYaN936kH5SpsX0pOHO2GIgOHcPEtPQ5lzzTzTImgjZwFsjTnXDEVmLgVCr3jcLcYO95EzJzRIc
0+HfYY+eTNmZiP+4n3kIQMZlARX/Q5w0XbtysE2Ox1RIG75AOasOjsDgUzWD1BosWMXLyu1kjgfx
QZ5RK/aL4nDBS7BeS9AAbyir2iWzZV8U+RlmNqKTHEzs6yhcKDQ579jnmAYFBblbc2f5uaeVZbkZ
RRJp2QLugxYBQRAJKxGn1EouJpjhptaJ0Uc5DAv3bzgOLhr8P1V9boDrn5x2cW+3lKGPG4WOvCmv
K1Yde2Y1Oc+1R1CqJ+EZDhytj3oQ8t3qSWWZKSWpDR+kTsmyNyd8Q631DamqTkdyvLgYYloeP1jM
ka3BWHjLf5rTfIEY/h9Qi4qL6stpcA88KWU8aCgxIelGIJbm123LXoJ4gQxvwL37sR+ymG11Q3mU
A5kA7wpL1wjvVniLwla82hLMJanb/2+6bzArEukAl2yao0K7mlrO+YOA7DsSGXGEGIwEfIhSOVoS
NhrHFswnfAf0rWuiOyxyG0Tj9NIWKHbcThzVNqMOf4MSW/baz9VBOHfycguq5i+q8NxQLetJKTCe
9AY5HtGsvOmjn8FtZc9YaMGQf68Uy2s4OcfAaEhm4Kvo/5aPDni5J/6WxxLGcqJ612H0WG5ZwPJu
/c73R6nZUg5nOP8Ndqw5sWdAPDjAbwL22CBq/3aUFCzoOEIc+BEUaG5A6c1sCLAJunQAkCxQ3UwS
hGIHK5iDYfKuQ0Sj+K4RfpKt2jxgwg5tC2ghAHgPyQcsYRUh2kpyn9tmoG7BrOIWTQbOM7KXRHX2
y7IHmo1jtZWkUky2e12Lf58E0jOBLVvEVE9MYBRkjhUUzvy2CsI9l081+y3w2qvsjbq3cBXlzZfl
0ATEyJCo8//gqX4z7dEUoKPJc7ZaG5CpPtRslllQGjBhRYGDw1Rv8fiDrowUC8NzlXAHnRD4WcHQ
7i398I1XWdDO9NLbeeQVa10LgPXHgOge9YJqRRaIZ4LcG5PVJgGPAeOSos6b61r2gxjpgK2R7emf
65w1z1/1qYJCcAU3X+WwJKFj5T35YvN2bJyYgiNbmNcPxRpWaf3RlbuM1TFk5wCSY6LoVvhOQfth
brTUiWniVRLeDzkPUFZ7GjG7rWkbOrOEnTGkeyZhD7w4Evylg6zwJxde2/jReUI0+wkJegvwvaCP
GCLhcbpDaIFgt7e0qDOk/poEnHNm/L+MAGiHQP5GRS3KZceoEX/2t6byQwPMikk/9p0VouYUSTvw
o+NW2Pdx0i19rhy3pGAoVPRLMoXXkl9AtmB6BKgm7GsWQJEsIWjzWiYTm1Lad5n0wxpO4zZ6ZmFi
Wwz3sEuN5QCgmFGXQZMWzchjvGI8fqyCj1lg1hRrn53rAFbF8qXbtsW+5Weo1JnboG0oBfP9Qt8V
RW/VUqrlz651AAyZV3HZGEz1sS4lAr4jaDkb14jWdtNOO4PYRnzpPBrdeCBOhQoMUBl9hWqM1ywn
JuFOmEUJcsOlGWAQj9fqVnkt+essdO4vRtsahLorA4dm3QdcDaHXjata2YX+dVLNr7r0owufPo4I
kOeoVg01mhMv3Rfr94DvpDxKUps99M5GB7QXGWpSS8p3RETKu4FFsue1BsBRFTUaDcOb5mjNwe1E
fR3EuhHZjadYVNUkCf8poqSoXTcYGwUm00LPVpVw8HAL3I70QzH3EbwESnM4ulhx4gC1sAF/4YKc
QJdapG27Xtw+e95+Rx2nqqKCoeZpOhHgNkyAqg4w/I/1+hQYWXh94kQXWxNvAkCzrlaqTpd81qXC
D80OfaoFjzWYdqdIjPr9r5uxh3mPxLCy7h71fmKBs83Qs7z2waf0wQSGL9/Nk9pm/PvX/0q8O38g
Hduph/5ngP5k1adyghQlbi16oF2sg0rwrzY8qHrjZFmnuIlzWUiNQdo6XeWJl704owgUqeLUDus8
pAZF+VSanEW+pQQKxi4+iX3Kh4AjwvpMs8H2SzVdwvoDdB10EdibsKq3eXiMjSCgiL8Vud8BVwaC
AMD/zNIQQMuVjXaRmOmJu38snSvIURbWSj38Wb9GH+HJCiYnP3Fjn5exweRjgGKb4I1Qvk1RyCwx
QuLlDvlc2c5YIfuP/ZmN1MaOYS0fsNH5FlS0CZWw6udZSJ5NRBHb+Ed3tObue7WE8n4Qz5ShF6n7
9qN9J+OJitbGJTtvdh8G8mjV7WhuqJpJ76ihfJUYmtuOrbd0vtQpnKvBcIPsUV5gNKsY/ONv6nUe
klmZqKGm5MD6D6lvyE9vkYn2r/Dpr26lhaUJJfYr5A5QJD79ugsLSU+1lOax0S+2Z0dQdjnp9Ylj
N75T5Xoq7niqJ1ZCeW0u4w4UKNnkOEyNgd0cAVsqJFyRo9L0Vks76ZT1W+WmcREgPRpGhfOS7uog
R3phYRQJuylyR+Zx/TBgj1bWt0gLk4hYXWnLSRmmFkfeu9njWQbHYNNoZsb0odfTRIZGR1dLcBpL
bz3Yq1sIKkgGh/novRRxe7ZyT9t5ONYfMQ1CyT8YkRAufwyJxrwNdBsz0+jX9guWQ86JxOBaioLB
SGWetXQ4UQMtqGjcwv+gC0+iF9sKyunUTPShq7l75Rx3YurpeL1RIY1xiyhnt31RIuT/rWuUvU5D
MqBMeHTDC3OhHylE7UV/HQ79WRLMoL2L71Aemkm+7ITB5+JS1ccSN/njDfM59s8N6otbblkCdF1t
+sB3MO9Ue/VNM3f1jxADJ91uNR/W40h63IrTSGMxBeNyQP89wg/GRSZ5wwCFgYulYdroLMMUuKRW
i5u2SxN34Sd4PRI/Eue+5vosbiw2vt6AHyAgybYRDeoOS3WXz6U4GyL/CsmM24iUzcOD7tYSowfJ
de/NZX40zt2F6cnvG/v71+sA9axEx6HCxU0SWG8aL+eoBpbEA6+90EEtBZCwZM6gL0t4Idt819Uo
wsiYr87L0KinYJy8RPNiTaB0MYxuHgLZA8Q2k70/ZmYoj0q6R1xZV4vju99E7S8htq2UNcZzymue
kd/672NOrKV50rGNQI/5WtKkjMQyk183QeeRZsZKEYTQWO1rYBHvWPTpjSQ855W91uG0p7v7vrqp
ycWmnxU1zVmhJ3IK4rO+7P7n6IA8uE59sMO2CQXGJhvbxDmlbKGlk+52jscxPnvWF+7BVuwwTG9k
WylVe8Y8EAt0CLD3tBUfPwNoITomS2zsmnJdsnSHCrQWZjcAfvHa62+fjtcbdmgZNS/H+frPmTNV
Lcix30bIes9faKuE39sKpvYjrYYstwasnqUHDlNkFMBkInN37uqT9UirrIYt9Rvk7YYzrm2qNEYH
QJKERVRtc2zEtbNT8sbD0KFHrZf+lve337kAGlUWN532aZ63s758eRJfAAFCHW8BodEaAo8iuiwf
KNUzsgZ5F1tZ1PdDZt7G6nvIYpV47DUXQ3FgoXNaji6BNIdmaS1SUYTjTEAuzHd69jR8uua+59gi
Q5XXeXtImOusTrCzE3oDsXdhReZBZlLLyXb3s+MuNuLZ4aJj+zf3V7nOogoXPDod33Jwhrp1l/Og
tO3jiX2XTpHFwdvA/MvpKqMQjnLsJkKqs703tDxPSm23K19JhAp4iGEqOUZuUjD3skr19sN8i06l
7X4v6MmR+n5ddNlwB/dNgNTbEIapPx4VKBNoddLDZz0jHL4A5zaJJKsa1zs/bi4CWji/yApS3Y3S
EDUwgY4I6YjB6+rVQzcK8BQ3ABxXaaF8zjZfmXXDbKflEtx4OyVoHr/TN0W8nc61cmj73YaAF1iK
jd6eKLZIsWfRujgr3Oq6zDv+M45QCuJiGN/ZjEIaHBCdl2hAsB+ewIrRlScKEJqNp2djw9uSHN5+
znZbUhtaZfdewD7Amv+XJ5i4Ymil92gt6Cvg6Gf/sMxqGOnJ42Ml3zQadSu54YHq8Hzk2Yju4aa4
LouZYXGXYYRXVRS5BZxuxS9AmN9uraewMKyGDm0cspExun0FPo6B/KMRIU4ivViy6+Enc8wn5PVY
yxpRobnKFdkcxKe0sqQSPRbp/XycqZ3ahITJ+iCuGe+svbbqPhkqHFi5/s9oaDr9zv/R+40914Im
IT2qGjOgEqlHOvkkTi/RoMQlNCsJh18A1YxUWRWk1Q5r2sGg6k1FoA3XI0nwKt81t1C1LsOo9nv+
aOm3LuYdgdCrrFx1TFES2Eu1tkph3VwBgGR9vJBLsqnOIWMj7JqPs1JTf/+60d0Sb3wUXQKQ5ha8
XIUEJXDSPeN4EbNvAdHwfq3+3WhEV/ps1CU3UCfgoCkb+D77fKa2P8V4YFLVCq1jdUbLIM6jyEAQ
hfRZt24qn68D6aW0blvwBOg2AcdVMIz/yJAVd1gUgDRSbeJKMEF34HSc04cj4f4gWo7/kHa8hPtZ
mhjh+BR8E0VH54DOtlIlLG148fO6w6M8Ukkoj3pbFSV/quAyX1leM/YGICRoI8KTn+lM3Ulc4zyf
CbRitVZ51ZNWcSHpjZvg43OULcvuPswi5CX2rbBjgQvXIaAgrw4rk7T5paEg0hAc8M0swLAX4AJI
8PaVkAPLdYXk8KzU5LnszB3B7OBTZrbAV0nWw0c7kP80iUO0t+kvAWfcBAOPjaehYI3EXcSASK82
5RcaaTUuWFo/yT6YF0De6rP7+4g8JoLnVzpbgsVhNqrmtMWFX2M7fZBi0i6xoRqPNwn6vmi9dnFC
vpJgWNYy3MObkkpTaMfe9D4sanP/mQz9kJ7hK9gCokEJP+i/NvBrLkA0rjYEDqojoOlpxkhmUw1q
7WoPIRuklI5b/9X0mEhfyWM6ZuvKo+1brekAvXIgqEoSPHcKycm17oQUj3HQKY8SNEEXDZQF6pZ5
fRhHgnf5JTJQ3JNG8q1IEfMI7pzG22QDrht/DwSRjfhZpshWXgCl4E08azXuuIWzmt6Ht2DXClB3
dqf2z6s23xp9eHCIu1OEJbtZTFhVUlVxN0Qa+jCeYE0HZga8UG4TLquBrasd4YlqziD+oHn+UKMF
PLkHgqVeA76MV6Aa10pR7yaxHsJ+DEiuzZ7/6DARDxWHHDhcuGzQMYfX8ByZP71uKevT1T7F7zJJ
Vq0SMxc+iaRWDMzi/L3JzWiUodxg1Sj+hXXYXUQFGRmVQkZuUtFtsIR1wGiEj5QW+5CanbXEEhXa
E9+CjFrGNHRmEoRhtVSQTKOHZxn8bRi7GXs0S8+XTyhY0Br7jZhTCFIHEfvwYh9CFSZJAWXMZv4U
WSjC+pw8jQtUDWwBcOKJtvT6Lxa/ynPhkAcCZU3fyPTzTZcKVNE1xV11+gpQXN+9HKXQLVjbysyX
Q0b01NWpefXr9c7k5ig9sgcRb1eJzXHjGeWDTEJ/gIS1iJeEfkKiaKVnEEAFw/ljn0KfrGLeOowW
rJzmw3DLVLh+wdfR1Euumc2OkAxmIxaH+Zc16bjp74MY7O5pOoQ2ICTkrAqx0syRrj2PWObyJixj
Bo0xetTzlN+DWeJr4sAPb4875uwoR1Rlh97eRPH9xlQMGy1D9nzeuhetzNbN+CPFKJpVxcPGuEtu
Qj00cEZ+WW52mZxFiQcUZxx6aSlcWyZd2QUZghrO9u6J7tmSsOF2pQCPvh32zOzeO7HAl6zCQ2It
5bVj9EcmPKhIpWpcXgATtmGlT1oWUAPRxmfHw7AExBtDDqT4f07W8p89faTFVMFJRSRMPdFD54CS
EmuruKALstWUZpKrvRZUD48MGBHvb9xK1IQdGhX+UeLj5O+v11m0am6LWSyLkIxvEKIkN41v3Vfc
RstdyX1cG3jETYoHriBRpAwTFDlzcAtRJKNo/3hpJ0ClC+AtONx+NNjsTQktSWp+U3UM7kuB6mSR
b5kHnHGyxtb0NFV9Ntks6o3TeZkJDlBfjgV6sS778qqVOjm3J7qpq0Ft+FT4OsN8foPFty9seDKa
ynP8omcmWQPGQpv0ysqmbu+lWdPGnCJi9VjMh9QpkbFB6zxDxHgCTLAVD9ePHM2czxk94EIp+yaZ
TBk1I4XptWGdvrB0zfjkANLtP+Mz9xAI+9t17sotclXcrWoq1kOsthzkfFElf59sN1thhkLA1RmO
aXAn0v31YxaMaNYTFwGRmSBK7FCv+7jeXjDSLgkjabKGkg7VulWrYLdb7OGLTkDGxX6NEFXFFszP
m/lmlqUal8PTTGiAO0y630XpyZ5BiCW1rUkP8GuOK9wgrm7nPKtZ/DhM3Hh6YwFj6PUD7d2QVA7v
iEyslfKeGI/CkQ/DLUr78cR13C5KJUCDRGsD2VMQ/C6UT933NTxDVYyzDg5hni47NQKCnLO5AC0z
UHdYb6WSFqnU3SYdxTVlMGpsfpzcySiwQ/fDU/KTaXqXm8rzyfV55kjmv6/KDXFXODCVDiuda+pP
qCMrMRuuDdxX9A5FriltInsHMTaKE5cftwP1+SVe3hD9ReavKkZed4qyqMqPtJfwhN7DL7N4A6pa
mDeQIyGHvpiKHhaLuBrQr27qSxISnz1MeUnfhghMRVOeG9RRkEVnFF7g4CxgFV0+wMNVznoPgWgN
c2wxyOZTc1nAAS0l55IYk4rrQ2Cs6RN994huyuuKWhTaAKsS3WCXO+cG3SMxj80a1zxjfXmhOr27
RJblan12Btg1MU1JsaINEmb/QxFze0D7Z5u6+RsYRLXBJk0MBP3pEWYDG2AwkTCkiALtmi0oqOim
fdFopn+/YZUwYE5ckUpNZ7uWJDuW6Fb/xiY5Jj9A9OIpKLmf6ELOj9tQFso5vcCprBZR1T/tLK4a
JZwgwzDJ8LNSQAdqiZtfFSCS/lEkG1GxSINFsLymxTuc7YxW0MqjjxziONMIDgTPF4Lp3MTq6O1S
EcN9mOtq2A/Iph/IhvPKhhXZ9frORBR4Qf1p2HVVHbwVdDImRrk/lSB8HJe8OBecUcMXfsuO3H9P
taBwGFB0Lx5ij9CWDm6y8Ni9kRSNxB7ioo8YHwo2K+MKMH9ijimstViSVi03FnZ9eoM87nTRT48D
X1RdemPB/CbEpHqEBo1TYJVT2x5uH2UdQeWUoZuh8qQNGnV5ln1Fclwy7opQ7tq/cwJdj/eS3sgs
qRedYUkvEIEVAQqb/Prd3Oh5FJvXn5KjpFfj1ZCnkqp8BpQdXtusB1Wv495Drrn0Mz8LrurHLDDd
G8Jjio7TZsOwkOKf2DUsuxbWgN2lXhy/2HQAvGiH+V8U6FABUd8etvRh9sBE9yDyeTNyuftdaccL
hhK2F/h7fo4dgeaJN/GNvNrowRduIufSELp55RBu3bUxxxIedAoRyDivG8SIR3daHmLaZtxncj5X
8G1hEa+puK2wYG2235QYuNheI3MnKxhcvLiqsQb65p0ZtZrROsYVWeCjU+RoHmCfgyxpUuz7zLpQ
UAXgZd4i7FLne5wQIxWUph0rvziqUVSu/ei9cPJWkcrogZLId8aSBmaS+18R6SCDlmpyOXB07DCu
cmfUHgL6XmwunPR+gXgmRZjmpac2+t688lQBMK0Gd3k6d9lc2jcLpRQ6mLvJBOR+QTK1NikR7aKD
XCSLuXWN3jurH6Gc6hc362rX5j2vvAb+pCTyV+m4qWN0o/mrqOlbKAkTH4tWA2Q1CjRsGu6qkdiH
C6Jb8pWFLXp4TsWDzX8QwIblUHbpitu55K5BF4zO0+66vXhCOjcE4vnX/XEBqcw0O42PXzmSpAic
lnb5xpMWGcgRQ4BMpWfjA3A6KDvbvpD4zZ/L3EZGGErsnzygh4a1Aivwz0DIHQptEV/ZqsAknzNW
2s4wuvuhacZ+ZCjwxnliSRh+v31oicW6mMytj+uw9N1/gQXwe7DH06vKF/xf6eNIpTzcAP4uWInA
t9LLRdrgumaShykeYZpIy1hvLjkPCCseqkfi7fvYbsA1elnIaXK/x1JLk4+9Kk67jq5QB0WqJ6BX
SRAD5OPpS2ZvKPslysLjeFZdXMcB7kzDWC6Yg0HBEHxoRR24w4YXyRzYETyeq17BH31vkExvDomf
Nzf16c4nG37EUQ6u5kWaK7TCSIlnyf+HCGDufyVU8/wCMZxU6vKw11lqyqoakGZkRP0IHKGywxbH
e1NbASHw7df74t2MGo0d22kndIbXHyJuXbSVbAoMTxkF5/xpLpNQUnjiuKP+eGEA9czvLdOcdK+R
pFVcBF8CxU33TG7Yrd4zFo/i/BgT3VUOKEPDiU6YgRpznhOBPDDrnmvLykNBLzy0RatV32lUyAxs
YO9B836FL7hVLvfM/xdPczs2i0O9tFhNXpGXK042j/H/jOh2tF5O98M7Z5x6MMlt1qbrHBDUB0Ef
pz8uchFdTy1iiNcCvRPmZ1wVRxx+Nujj5Qp+MaJCmxgxyI8nhuj/2vCbORtXk34QYtsQ92/HYmws
d8UPH87ZVgj8QtcfM9InJyfpObAqxb5a/aj0xtR2VCQbLOv2tIev1RmPf/SoefXzc49F3HgWi2T3
0SGKiH/hP6jzuGLizJoXCVu2VCekFUvDwCA3DI5RLSOsDUcPDyAZJLdba3jlxzbxSqxIPknEX+PX
ajs/R+ubWP+3MUioLhDENZGzbpq8/kAKTkv110SxGNpYEWzsEtkDLM/HwmxetWT20//GYr5N5ToQ
xYhGWOyY9DzWmrAvHL2TkKywnpmkXfYf6xl6L+w2tXsHClMvk0q8qSPRLYYHjUgocrHONxPRH2l6
JFw+k9xpm3mmkqPERb8a6wKiqhaI02UZ/sW+wglh5qW5CVIWhiVxOuAnJuy1jzxgfkiKzMENT4B3
GnKTKVnyLBXg/yWOLWQW8qMME6TPynfFqN4G3VLoNvc9WRCcgfGEZymn9P8xrzln25feDe0BViFp
VC1uwdL2WMqNONCfy6e8tlryc+esatnM7reZYMg0nfwKkGTmFc+Wm7Nvtp+kOYMNnxdjmmSYpAuq
iwjsLN/VFariz3DL4W0FnW6sQvwaurIcKk6OFaFAAwc287QJiZWoe5c1tm4DpfZa4rx72cmPWHXv
iNxEwDDe+KGcFcYTQpcQ5zBN/3b7BzMnPjnRRrE8B2+p0VDsabsQ6mpcdNOQRin5RkXEK++8RD6p
0smCODz5Wtu0iPKo4/gDU+7HDQVPz4xXB5OqNnucG4Zei/G6uXiBj0hHIwtn9ZW4AqbglDn/Ze+6
vRtjCNGpAmQkMgsNLq+XRuXBDZbCgvj0QcYsQfN6phA89EBwlhgLd2HIuiiqpFvthvN16XJR6ubd
1f8p+Kfi/PVfq9PUWzOyFTJIn1Xt3XuowzprrzHFVjxev+kQp6WnlG/4o0bhqYp0WjCw7K5mIc2o
Yw4SsJZHZuRUYrUK/oVVX8ZbmMRNnhPIGMyTTlpMnGUi4F0xbyFdA/G1swMGQl4QfEgqTv92IwKl
jmZjB6UB9TxqGudzShV9xjZUVz6cy6tpobKGXxTZ7YKQ0v4rQIs5KMIVJzS93aHfWFZ6lK6sQCCm
+mbKxrEcvkMHqo4GZZcvsLeqCKyQhGzlB3cmOqdDX7VyuAaI85zQmODr78MEyOrxG8aAwxOGnviq
7YDxC+qv+FHQHg7rxa2nnPRAufs//UtH32qXaHts/gUAijOnInXSgH7aL/kbjx4CiFywEarWE1Jx
sY0DFgSyAOfJFFRJtrIHtf+yhhbUmvA6PfnXBJ++N/4dtL+xqte4ma1OYmpLgcZcf2MPM06/Fg3Q
mYX63J36XHClLW+Iwia/7VKGfJHIUz7VArx3v9Iganuxzig/c91+yLFD0ugczv6/jFgubOcdW2PH
is1aJxZDBv0ovhz864nau8Q6F9cDiV0wZBZqbE8ARdR1S3bRYL6BVNcYoEDCuW8lSMdoqPvz3Xgw
tBLYpfpDOiLqrgCUcC0VZtSbLTA803ApOqk/5tIRp7ap5PB9/1NyoILPCFUeY0nXzYQnKAiE3V67
9z6reEiKgvRTJtXgS4J3lnt+TmO49Hvx1hmRrv52ohwskoo+SME+yAA9kUQIKqi8IzC/84rUpPWN
40iwNTvIjKgFDe/wyaTP19nF+3RghwCQUYrNg9nPpgjZYzt5E5EL+Iq++Y5wICbM461LVMA1Vf0o
xACBPS09/FD4Iy7feX9POxBSODA/+GFPDShDvrsDHc1rQ7L9AWqfI81cjxYmMr/9HM6ajNBpdtSE
d7VAs1oam6wfp7jyQAv7uHAyVNnJ8GgO3NdXwdq//kzQYJVxINJKIst6sMCvtRs/aJwxf4dnoLYy
Fye5pKUs7RuyAeyjI8WPcGQvuZPPr9w53M0BB57iuQ71bvuJA1iCiB3pf9Kv1iJW1IaS48YZxrnh
Va5Ka57tog5hZArwqAQ4Ob+ifIjZahL+dZjY7ghQ6/QmsqsXJgh0tTmBecAeFhHs1v8e6Jk9sTvx
+9z7nYAM3MBzCoffWMaPAxF2exxq2AoLOZsfL/eQclvIwWLBbuPb/xvGxJ+j2HXF0zuo34mIAkq4
nNfv7OS4azkfWjWD+7iSEsB6ULHHucd2qnASkHEL2i2lvubMRMyre85RMNTkIdlhIZejxBJ5a5Xd
ZQ3YIEog38bIhLLA8LwuzATbm9vn0CcXvY2KPhtLJec3yqHCfDZpxpHUhmjyH734Q54XFRnmagAg
mpBUxVtVNHv1xcjjTSQAqIbTqEHYpYD84xvVVYO060dCGlKMb2HzVjq7T7yZIp9peUzk1k7h7+XW
F4TSQpUdDw+lx6ywKuVyDTK9X26GPx040h1vX+P0IXOH9PI5Ingm1vt3b2OmwBHcvhtibT4iQ2HY
NG2NM0gi9P0I2Sc30wMLUMldBNXO2tVln4Rbofy98CG8D30NTYXnrD5pgLg5v0urweVi6nvdWkrL
wIdWL9j91uDStVOzdDrBP8sDU2UCuGz73t8shSxJIYhLDdGoZLjpllM4HCyExWi5VrJ7JS/seJCr
AfrHnbGD6IBNaHcwLGoP19CzPRYVnkVrp+qJV0scfZKq/AZZv9vU/KrtNwZPpS7Zc5R1OeBWI4lF
kN1pfcU2IZk3q4mJEKhBlqiiMhDpUFvQZAnY5KFq1VfDuBq/T9wKA5QGGnGdioQRvMGHBC6v2w+o
MPDvPYy1V4OgNQaCuLHr7aE+oILHoGz3NDsaIq9OkDaBySdF23YCVwKSJ/EAJMI8Kl21Vg2xC6QZ
IYUcMKnxWPWT2PMhQXfjLlcF/88UEFLEfRpYYvFPO73iLxJr3BAHSqy6OpHhA0uUlI37cXLNLPXR
EC4wVYIiCTQQuE9i/7IcIBOYkHk4Ij3j6Iazb4O1BczQob76ZHH0EvQtRyiNfy7u0mtDBsSQo2NX
/NMdewS8snpDEu6wIXxQ/VPCGnpqqDIoPfVJprm+pHEfOm+K9Bl+lwSL3WU6FyBIgB6gsE5CrTZj
LqvkZM8p2vwoUGPxupIK2S6vo9fZsPgDOItNbVOiQRdp5YiwEc4M4XTwHIoBgW4H8l1YYhZZdqhi
OiLaToYBLvGLHf6qJSvqjoYpEykWlMTDgRehxyx7Bk/wOVzZ+sq/v1SoFD9q05Y4QnjPxxIUYgx8
OFm4qRxV9/hziX92F9tcPAQH6pOtGzfmRuddb1+NiWJd2bBLSeWStx5KAC62KheLjdD79okq6D7+
rEVS/KkvaeJ/tnhOVND34xAiHfpU5fYqtBPn49X2L7B5M2HxRNUB5/Lxr4iM9/u7TXGW0jccB5NC
sXjHj7dFdPxi/uM4/wyFS35tSP60/P5GyrRZfI5PQcfNt4TAVMjpBJiswgK7Kacn5I9egpA2OTkM
vIvVTDJHyPh9nXi4QmRDRExX17zDAlc6tZRUL7NWMLqn39VqkvIekdZVFq14EUgLmpK4U6qR/cBt
CK70cNSROaoQ5Pubu+y5j1DxArIac12rDXHrKixdqF3flwE3ooCSu0gF11kfmyxuYDKnK7P7qz8F
vIcEP/9RVOn95pzMgYYR9x3TL6t/4VA5HRJdr/OW10V9tpS7ahnPWmvBx1Lb8942Mu4lPy0dHTE+
Uzzz5uWeY+zn4XE+ej/ioT2Ls/48OXRzbdsgKLQoB2YY6XBBeXnTy3lTpB9JszKwIJRVb2YebQfa
Rg1VIuTq4kxtfY6Y5HokLtHNhFVEeSOjpA8c5fOxEFi6iFzd7arAdI4z6I0Mfcq+CVq+oUEIkgyw
Wj6cjNorE4WkxeFJ0t0bHElqa0xseMSjRhjqtkrHDKJ7wVBZM7I5eYtIuEYP63ZpHYQ6qmeMgLjK
ZU46GBjLyyRuIHQi4txHZ9Cg+CFmd6bOEJ/eVzaI+yEMjracBbUzLcapOsW59Xuk+R16wD+B8KZ9
/tsitacpaL+/EYMtmipw1SIaYukE+XxiFtWhvHzJD+DRsB0h0sezv9N+NtdOVLCTaY+7kUVP6pbT
b0lVbGcXdBbUlTjBFHDgWi0pDy0pRLuLqMnvmTJrLxQCUUbrBNFNrQjnF8HB5QplI7RuwA7OTZE9
WoBTOPFnY0M1D4ki/WJAtL87772H7XCgNV5nv/LN0oUCfHDmoe3QhGhFoDj0aqsx7ThWocjz8nXn
Ya//pMOH5MU6h/bOjchdWLjdKwU1Oxbk9j8XmMvyHbn4sdASb8MvaBuwwQLsmIb8Y0PjurGtDdgA
s/s0EiyukJxSpkerm8cSFCwdu4+0uGdIro7GL3Y+4uPX+hWvBTLqwUsl+XHGBAU4LvjmimUfNsfq
VVTMTQLi0LDPD7hmuYOGveR9I45GZTJ1HSeTo348nfaaw10DzEsSRiBA3vwzfuLg9BR+vhoDerA+
1T/tvaYZ5orx6aH3wWNVLo/Bo4oZQet7I+fB8GjTpsj88NH1qwTWZR5jOMGaEaJgUp6IMyIUMBUb
7Ry5Nw6iDUUPPwqSTlFbP+/l24sY3pdcD07FT6Rg04zQZGVj6whvOpA8OLoFPnfbjwPbjxzlBE3o
4pQe6NvdT/ETevM3QGlYZZPPkUsZAQgrAyYtIYKoxISCFemIsg5ZGCN5fJOGR5V2MEbOGRBAtf3C
u/tdd/ryohSWBIg9C144B2TAxN9wFhFQRhjKqMULh89cFy58UezXPc0vP9uSwxy6785dcRMYGYAq
IRa/F5pYTsmnQlRqrapkVWE5d4bMzKS72yqniDU5Zx5dRXzz1bjiZggiNnxjpKZ3P4aYczc55eaL
2UphDspUE6ZUHaRE8Pgbzw/JDJmjjlXh0ZFer36La6hUq2R8vXDojM7MqFqYd8/HIpWy1C+HiQSP
gopaj1o9OKrleQDOodAlPowkHxS42+6pMSsPuK1f+OwV/82YoUIKDg6a8reG8vwB+iV3rRTx3m/+
fDHvv3my5xyUot030qQFPN6wMzPsGoq4eyo3YKw6XPg7h/v8+96irWS08VpLv8Q6VheYlf/39E67
E7mrLL3delLqmhpicEM0jDuZDJM9+rboo/tY6F0BwWOKfv7iFhHnWqKhAQp6Qg8QNri7p2hqm2V+
ZUCSuNoa1rgecEz1nDP9qymEWFGn/zC6Ndoc5/q2aCiU+d1JLF56G4S2pQQIAJX9IEDrNjqcPnsN
p0w0zkaBe4Zgx40pxAUpWxevxyWwMA+agSyA5Nnm5pCJ2pp6KSHdoDu2uCVv0Iza7VL1xHBPQEN7
igQ0UvymHDH2m1dJys00u3LQJQrY1nfdooAEOELLZaVwLtjzkI//kbeiussTc1Zg90QAtOsDi6S4
YQd0FSPjvEhfySyaT6a0SbtLQAERPBeOaGEtKcFHbFdLD4VmT7DZuNwXWvpDdu54I7/3bfQDog+4
10d4yL0ESnAAm/KCzSNPRboWOMp51fAi0FJXrAfMEj9toqGSMCH6YPK4k6iCJhlEkdcOjvRVz7Bw
H75aROhslV3FLZ9gJUE4TODXmfUkuhCg6Rjaw8MT5fW94oFfUwAFlSPTRrV/bVzMwjX/oE0vY9oX
q33J8at7+iMaWZRgdPv4wXl2lnHVWChmy3W2FN2FJmuiDl9W7tUmWHW/DWSuZCf4TqfTu9aAC81b
wtcRq6UA7/YW2cl9YMo8MPvWpKBJX7WQA9QiTTUDWrvQ3Axo4O+9yBRsvfsfs8MwozSfJikNHbel
RgLknfeFvxgmJe5T3m9zG53VSWIy+nYs7KdWMNFwizA99ZuG9O0Qk8x2iIIDZuLwBsdgTEaHaKjm
xUzm+OWn/bTU22p3PmprVc6Lgil8P+N3L6w/ZP6M0Im+iO3eeLgsN6+2Pv6VBC3Avjpfu/ZeTvYh
dGC5202MHY2Sb+8xCudGsZcfgyOFLqq8yKf0XMuZ45iHPlKXiZrAkJ4oHfBoEuCaKUMFgx/fe5Wg
jp2s7iwrQUcv3vbbFDebKf92C39flbEiCteNOJTXHO/J71di7vLcHss9TjDO10U63rkXgEoqwcZ1
nLFRJ4PLoDN4ico082Hrd7Axqf/HCqdBNbD4NbP8Xm19Mjvl3vZ74Z0RcJsICZ2g90oy2Tscew3K
8M8bUgDgJL0YLRt62Xh2YljuFNjF38XrSOj8bXyZRVHtdM6VAHoevNLUCGrICxWP23DFvmO6oLTU
JFQtqf2BFvLJUnzoIZMYcbG2kfJ9Zv2WS7WGzt1dXHlGQXOBxVZnGalxSoNuoLjw2dXt3bjFuHJr
I1Yv3nuogZovAKAW4/h4BgwQ7nlSDy3gbCVP4LGKwF1P/5y4SvwniBVObR7hClbmZS2ajW86juSG
oA4TT9/53E2I27ys/TClttZf8A9KPXCaOreQEVDkJUjC/lI6uvK82B1CwPn3/0tWhawQRLTFQTao
iBoyPYwcPouwy5NLsleGnxisH8pL1MlW7x0NUe6mn6pSRFkwU/8wokWt9QCW3fciBrNjiMkoA90V
Is/uKKUxDXSBkROEXk1NsejW+f182ipJHmpVbddTvhbYpXFlCVoh5vRNF+/oVJyv6bM0YrGRxux4
iZCtDOU9Ro1TiD/y/ZZGEccq/AeoFSOEPEOMKfJTjQjKJWGCiKYQPWfaeMQg6E/4WRr/ErO4hyja
dSfbuGlhJu0d3g1vE8igUgrqbVDhg1K72bP3bhgRWJqWIv+PyDOLWOG41O2XsrfAcAAg2vOiQ6jv
0orIgWedPw88sqPRbrfDNSEVZ0UMSuVajWHg4s0WJHd4b5IpJMagC2WtR62/thm1lsWbHy+7sH5S
Z4dHKYPQOmCz2+0LpRhzIH8BlpL9XY49zPOUEcucidx/5ejxq0ShL93NiMxG4AMiiX14Fcym1ZRY
+oOuM3lFapXWuLR5ZWUrk4LbP1UGz10gfTslNIawm/H114nHPdflXR+YF/9L7HO5rluZNoerW03s
CSCFFVhGyHxPQkKCvKkgrYHLMpOe7odpdttVaeTsLgsoPE61ZsUXbO5bKEM67SjunGttsOvson8I
w+kx8M3spdL/syQzPkTF/n7g2g2kPw2Ob3JSlKwc/ZpU6ajq3B+BBE7MRT7WL15cqi2/kh4ccYlC
+h4uKlxIiIge8iMNBSwSC5yHkWLKQ/jPGcjWszIWkMqpUYT9QVTcA+axJ5OVfLmb+rRYrR/DV4fT
tYLO3g+xYbnsvZZfa79NKz31m0I/TC3QXBP3G8p+i64IcFVLhDZmK7v97SSBXKlLYDLvbTl7C+7Q
gkRQu4tKnKT1Q52ou/w6HwHdSXf+8YYZDADIaw+feHihk7DdzyHrbpBxYW9zdtzIQH7PlWVXCTsO
AgwpJgF/JQvO63LfO7zFSX+I31g3P7M3N7v09woEBxdmEchPP+lJP+XDhBCJ5QqBGO8r+AVGii+Z
ZaufBjoiItxLonqANLdIA7dZmd+wxdb0W5AUt0eYX7bRaqJyTjobNR9ua+c5IgbvCkpFy3WzdD8S
BSeZUsjEYbN6RgPhFi5wH6x4Nef7geFNpFtFX4mxi6TETFJES2Thwb8ukyzIK+kyaV0FtVTVq7Jn
W6RgZ0caRsPQhoSXbWAsjkz/Bx3cNPRFUOpkPYJOrb4LG2T3j57FySMSFlx4l6EMnZnfAzlV3Slo
gblRiCEKEgSW8M3mROP3fw8ViA6VPOqjdmTP04hwvatGkX5liXCKUVjwDM3mMmH1zAwWRa57Qvvq
nZl7XSUBF2J6e0k68fNPXS1/US1kHL5RrPl68CTVizluHf63/vZjQJo+OxhVY9PxgfwnplmVMX+W
1HkkmibPBpuiAVo9pMyQ7wwqqwmph7LGFmeGc2JpZc3HH4nC+K9/yW/C2Ut+bgsABi/2PuUDwKaD
6fKKJyd5H2KL2aBlx84QdrVgojyYfmQiiKfTGr2FWkTZqRzqSvM/+MTdBV1hZhseKHdjr8yAGpzI
vk05+mqa0r71FqE81WAWc/8krSj6InncX3q9kuBC/kUu1jrkj8EUB57g1Vq4xIba+8MonNWuN4S6
HPyzwVGG9VtDtTm52DinA0RxDCSTGzsuQzrUzq3wB4tdb2D3NmmjF4YZr/Epc0DVMO3tH9Kl617B
7kq5Q8H4vQjwEqT/zfDwT+ajyW9bP64CiuJERWt6mlsWef/aZjnVcY9rBAqlyktwWxR9nZALAbJi
6Q2VlWWH9mksD4aIXAmVdlsyPgW+i+CUKlb3wkF0/6BjBfej0hmIuDVdP4c+F+oc4Xv39NDCBM0x
hIZeWt2oNNrNcWaliFMN7yveVU0d+jBYcuFn4lnUalzzoklf5oEdv+pP0mjW1wrSd8VZIKBgBZay
V3Fwuan8Gq/cRh8T3QmMem4fFp8CoE7Z8NimGqPZCCbdoUSsrTv2cv8rFXRpmP74KxVf4pmAwCLS
tKbD8WzUrN1lOEM5jyt9AXBXz2QYhQiXIw5L4KchUaV+TBVwamVSUbdCS1vgCklLuCapbn/D17ch
4evdFTLITmFlgy14p1/dflyQg7GA/Ic3lHACGiK+e6B7XFilRK1kdyo9h2n7hpY2nNjalAnJsmfJ
H3GbhuB3ytyW9EnzDFjtEyXJdedpHFWl8K4nEd1z8mAeOdNHyDNSrviwq6dITIlBy1QqECxuHhiZ
PcN1+2/oJVVvAOwBGFjAGLGfVtfxgSMQDoxJBYWJQXpy6h4EJ+t1SWan9QmcoclCpvwR5sKiMQBd
z2ZZGMtQWf3mHw+vOSfd8lLvoY9J48lsUTWno+0YqofetRj0xFr6Qthfm734a5FlBhCZCBxdRhjU
xaVJUiVjpY2WgdxXfnUZghPtJc2+vJ9p95IbPkmq7ePMI8jUrbsGwTWC2Ul6V6b9jDyD6nQyq9Jf
+f0CGAY9lmCjKPA+miDdSCTHQxEqqqLpFIzb/l8aEms1pVPnZAY8QQh7J1VWY7apbdD4TBzoVeVa
iYyTkpk/RlREyvAaT475qpsyM59b32si9uZ1xuUzWoYZhe2mi0g4k4eL/3GzoGuQ90xfMLKQ45dB
E25S4ncU8xt3gijHS3th9HmBocew0V9KmQ96RNW99UUc1HX2qk53MC+0KxwvUjtYo/ZMn98v8fvx
83H+fLFJm5kr/AimOPrkxb+EK6rch3XnGDAtprHZQMl9OJl3HYtnlcU0DemiBI5Hm23Xj+OMhhWH
9cv/7sso/FXMOY49SddxwVzipmJUVfy7zW9vp/7u/sARTU7SqezX5hSj8oe/P1gDZGlMSAbpmQuh
PqHkrqsHVgbbQST/FzoZTwHMdEW7N3iVrOwkIYzxIeYux4Y4IBuf2AX9GMFry/hhovajAZ1Od4KJ
BgI9gU3hKiUnjoYX5lG55MhTNNu9Se1gWSgkAfNZpldi0Ler2mFL3BQ+4PTmCh9/W8ulUYmKvQGU
rC6PSoRm8EmVypuuQqs1wfK1AOos27tqprgjAolwwBVO/DwrTjdUpo/d5H9tZXMxV7Bv5xTalDvY
J27T4kl/1tHBtFPxrSRDIDrPcCCnG/lDPdS8nFhFdgun2BJDwS/FUPve5+2kqfsoUiwv7YTw2s4A
cI95lTxp5kvQZ4Yc5yJuusgU1k0Nyx9bF3a2xuvhuueahhiAlZSu0U4hPMdR7m7CC/GwAGU6w+7H
d5akIen0CV1ppLvo+1evU+lz3sHHKbsHN2ZBMGr9Qho+ZBwoBJFwbHeWWlrD7ODUrmjI9+YVbmfH
hXyuFjR4h5pzgOuVaIBKn9eQLrnLauGpvmFHMkVVyAVF4/WKcCLK7rt7WA+XJet2iQ6S+3JQsMX/
MQ5v8AL8qKG85z70XBKn9smYvqohxJqZeJzdC0VYmeFB4mCyZVKJR9Z+s76MvxGtZHJ1QELMZ+Hm
qu/MSdIOgP8sgQs52xgFbq36PvIuVgEDkW8cRoldIw335GzH1GU6pQiGUQVHXLYj/Jl4aMaz2F3F
7FEiU2xc5hN7Tk0Z86dzSFItG12tUBpuegKm75ofqSEwCSwR/SSMf+mF5F27Tnktij6A5GaZtBGr
4jkbcT7QlB4qFmd+WIS6Aivn+g3PKrDo9YJ/+uiTKFN47mZMiiwtZl2fmNCMQZYzkm/u2wHwiXbd
mn8OVSfSf+q8lEcaamdDtzBjPPdGGzeqUxJQlBCVa393J6Px/vJBZ7cHAAc9DEZAo0V0hl9f5H9u
VRK4e209/Rf9ikarKwzbIs5xUtcCd6+sC8wpMgDAaoxMfquMt1YkgmD4yekoD6lPq2myY7h7US+4
pUfECJZSH886SOT2tIMEVgygHvlZ8RZJWT/iTQc98ulOT9ofRvPfYpYADdws96Wf+4/zXuAMflzS
FdZAsLfs1pWg3/v1X1skuuKc/hrNOviZmC5qbC0AXoKHV41zbSU8e/cqQDoGseds+kYX/9uBmTBL
ifJKaa+klhYGdn0qr1JLIhpKulEYDArueidKDnr9EgfOSLqKShairttLS+iQkMMNWrgQXmcBTn/Q
xMpzszV00+lrs5YRRue7pmUaXNGEXngF/mUTumP/eDXKII7E5Lt42Ruym9BtU0XYJbxRk56bnbdg
GXzNTVgMDaeLzBH7+svZi2Drlii1D1p2tZkI2DG9D2d0AkdHqdzbDeEqtLJL6f89tFcKqVylvVrb
68ar21O5shIHqb+sP88AWUNPRWjEXIHMge95U/qUNtOkWfOcDsRNhdSdDVwXspIDEkuG0xIUI3Oa
/zox724uI30MlUk0cfUdtmB/2Y4ccPZkH1HcA47Bl52F9h1DBjxeDL9TFLGwR8mB4/baakprXgng
nhsxPl3AlO5oZr2t2YgpVz3G/3OWxvBxsWLFYz5H9BMMcG87yxgB7kSTfoxrkGiJMM89LeFttMgB
ezTO9FM4I1gyIu6v2YiEf2DUzY6psqFDYK7JRTTOhwizKFAuIkxlOWq0M9v66UFbk8owL23eSVv9
o4ncj/yIAW5OJ8DWerdUSh8ajd3+jslxiKlEQU7UgnopxuoOBPXwKYS1y8Sf7N1WltZVjyAg/7yc
qdNbVCWnB8nSonHNS/fbSIaPDwY0Nqyd4bU1skbN9AX77Xd9V6SrBEcfZF4+O3mHwB3eHEKh+c3g
u+9LNERiYXR5ovIh6V5FsBV7vp1PYdLd2sfb7HAA5ZSFY6C26tBGtHFra6vDhZMtX3fH1udHTNo5
8t9KO+8e38oDr6yF+SH8KeQOj9rP9wByWMF25ab8WbCJeNNtMEOxLoq/Yhx4UDmEUivl/wIxfTSg
7X137SrfeQJ9CcoACX+xTWTf6OKy60+0R9CWuEJicyXhysTMRvmMujnjw888Q3kfVh2nA2pkrjlr
r5VWuhge5s/adb7lBA+f3RCFVFKIFYdycP9AKghc54uMyq2iTPNjiWwDC/XlWxz0muYmZRnfJt2k
NqJ4FODyciwyT79Dw/lhDNp7dh+28AfGkrxOu7xiu20BRNqI0zWPujFAvG8kddeiuqMe9b7xA+ib
Qh6MIkZisfiaeaRXr8K2n/OdYl6nlVHhDqePPV7qrDhGj6i+jO/xkWTYac5d0LAvJvQS0L3+Jmxk
76qBmx8446oYfXVeQSfva6rgpQdvFR3uyqb2WMbKmnW9jbed72NQAORMoXcpkCfDp/yZGQ0tfSGz
UGZf62csBP2WItogi1wABvTbe97uyr8rs2oEGPPxHZdNEd2EdYKrQumEgxSqpVMoZV5l4mQNNYpn
fkGMAGbLhLuRj5pVij0xtkkDTiSUybENcCmAcFIeXNLd9/qv3sMe96gguopWeSgHaLDur//NixCI
iAZsh2HLU/Jb8sWWSu+sX/8t3QECfULoCEPO2WvB7PoZV8c8DKUJVd90SUDdEkpvI+mtY0vwDYCV
vXXhlkK5bSb6lomgvsIYgJdZ7rammYUPeJZi90lxb3sD2+EOAE/6KtWpchWXRayasrREp9t0CPTP
bp8TXtmNsOwmsQcB6OFS2APX5Q0f6+NtyD+0HoZGrDripAXe76ybDNAXKaWK1tozlDYs9Mded+Jp
+BKqxVqCHkNYmPXFO8DduKv2BE4bqCrIIrXKluo9UDNWcimKeEFWIaN4jMDaxUAlE74SoWjORYB3
VXJI7n1LKaSjXBEG+jetcGN4IK/bPuTMu0tdHT5vFcp+lOEtdPwcSUSF0NYVZqp0hTUQHxVvFncU
Ib5ha9BQcY6q7V+9cGcD1ijYDNZb+OEl4VB541d1daXyNVY3zVMpOhNJ3nveEB5RbNl7iQPyCrHK
N53Vu6nito+29oe16azz8S+WVUWCWXlbtAjMD8NOi9cHUay7a49E9kuJigvqwNMGqVmYNNu8rhYE
WmfJitZOR3izQE/NEmjHhDT3E8eGYGt2zwo7BXFM5+WSd71oNoD6jcVDzdGmXTkAymNMIUwLiJMA
12MnyudbYNJ+/9KtQCf4ZxPbMh0utoX/QQhgUvrzniC55vpI7ndq2dM7NTK5JHDrRA3GLjnmyrDw
63kmlCmfwwi1dKuWQTqVs0eEPH/cEmJhrRe065TUuU+t4xbVgukLwSXl74FatMh/Vf/R/3SKd2Xo
5mBOwEaP1dJkAHbZoL9ZZ6AqlwhJAwIvGPZsivPAwjGNAjHKfCPto/6U6WWA/iOwPIw7ZBWRc4Ip
4wGg6uVpuHJxkNHA6BQaprVLGEE55CKMOW9XaFZx2yMgLZZ+5EKagUz+2L0Uf8LQ9OJWG3aAK+QK
qO2OrUu3NBse4wjls6SjTk5aODQrGB6mIV6BrAKO6EvD9OiHApwwt4jP0fwIQiSWsL6PBLg+Vgha
EunKCONBn4zVNQA1hHTKoJ1VtyShGZzzkSbweNPVb+0ZXrhLa/sqjalAzAIjcsG6lLYi84qlDdnu
FUmlHaEYmfaxLlU72zLZmVJ538hB1CgFwI/RtPPxvAs9Dq7oO9xp6urx8XAP1Yh6yO8PYiUlSyek
yZJXula6dqaEjs8J159arcCJFSlNmAYPWhUz6dKVK75wHfa64NMX3bvbO0DUqtdnXu7M/+AcbDTI
1b5tFzKR0CvA6X1wXiFkCGY0+t3cBuifnwS8YMYYS5a5zPwVtG5WuIR1g9K2wuOAcbeXzPNeTwI8
LnHIj3uGlSViXuQedblgDMN/V0EH/+pHedwAZMitS9hrWLLvkUW2sMTYLxsseXDbNGMW8y5eaw2r
M3zP4tdAWTpmQ7h6zr1kLzHMzpiQgHfiShCl3fD0pCkIDr7eKnBHzhjleW2LUfuPRxT+/c6y4rDU
3RxzpFwB+LSrM/VnO1OEtJNc5o5efW5pwX/gCShTmUUmK7tpAV3NuJm7FgaGnkZBkl96X8no1I+O
/2SSrh1Hr0nTcbBrJe1yJBpU29OJNhS50Le7jSkC84EFKrXUa7GCaR/lgdAd5oAPCCXDhUZExX3O
yfQFJ4rslSgpuICp79qh27Pti1YRBMMRZKdygUzvkoXUBaHrvCCNXu1svtRjjok5nH0luFDhmrWy
zZ/SPojInNx5ceMkNOcUGnHgTvtiXzO94mk9n6Bc0/E541UbGoqk+7D2VY40LkQZhFECY8GH/E6s
qIgT6JJI0x1jbIJOOC/FQ/ggmA5CWMVJa2Tl6A9P9yadTTv0SQqFNDMoDNNLeluiXyLoOVfybI+j
ezTCErGAc+ZuQe3NKJMkPOlz1nFQ87jLnRfksDnTTrNRKduFp5QMWKViNF+32t4rVuZMFnbjBrOX
TrjQlUSOdkLtSHQM1WRFyDBTJfh1vT8bG8wMrB3M0++M7O1Ws5h7x7CmcFi82hWslU7+tfEQnW+1
o6FnsQXC28H4Tb+ActufanQlnFSi8+4brPVZ1XZqOmJwc1DAZp39f5ORQu+z6JkVDeyqyrtY8JyC
fZ3g7DTT9ixK5Gw2ciNH/NHXgJoDp101M1T3FQg/sCSH67nfPPwCHb3X77/xf2yzxMaCF20YVwrr
n647lrK/L1lvSakyR6OmMlHK9Lx84DHRFnUn7zNksF3JokCi6BTrSdpxsVIquKWDLRuH5+LGgFRu
vuGzXh35E5COXiz/D1lna5CDYPJxlts6F/OQMif/yXv1HYqmyAqjdgAvBmUqnK2SIOUhMNWfP2DO
tZ7c/l59IyfSyMDJJJGJ9QGseNPsXF3urV11zm6JdCiixoZY8wTN3UVdXiSz26EZNjQNl/q06mAi
XcCgTckcLbNE/iaNoLYY2+xl+ontjXN+ituvb6cWJ8dVtjgUqcWw7sKel3Dexdc8RlQ4k4dklcPe
BoGbfEJqaTqkJdWPRxxL5mdfvmZdHn3/IcexrZerLxIhJnhJjOMZRjqcjqdmYOUh/i34V8h3HvQh
gcShvh/PdavQl0HktzghhMHCq1YbIarMQWEmThSb0wr+CsRtUGaA7B7rp1pIqdlMoM4XI2VAB39u
2gNaipPd9eNT+yqeJ2hvBdeclZeGbRabj26EMkaGQWVYq74bLbcfCfFnA9PkR2Vu2QMPkF7k+jCB
4Z8+teEx3P/SNlSBwrrLDwgeP7XcHwUF4rxIFXhOpz1wHcmcy9SKgPp3QgUeoXep646oQY157tbx
DkqJccv+HvemdqtZv1zjRgIumUrLxiGbqYRRutAdqxN4HE+qHaubjD3e8c6UWV8XBzCNAXJ73cYZ
2lCUNqXnJrt5G6JF5tUP1kIAiFKNuL5MuX89o63tMILpjwPdLbTXaV16sooJfhj8VRrH7xoEz1iE
gwsxfop2Uy0tcXLefAfLoSaWVl7ANVln5Lr9A/s4FdWEqhtGLDLvn6nFSM1MQkUE8SGSjU6OpvS7
oVOxcwptmBn5gazm6EC8y3HkfqLQSASvczfWqfZw8U3pGa/xWbHb3maswbzaDUgpGwdssZwcmSdD
5c4XL5q0GLYr/MfIXhkG5isAQ7SXVr85k2Yu5EaHXAZwWSULwWBD1YHDvuMn3vFucZ1CntiDPs2k
6pS3sv438n28Qig68gTcSSsi/rmPbqvzohtk8pYnVR4zQ+NLhVTrIVjUj6EudnsTHp2MwE3nIa35
dq96vdUzXO1RVAZ2H4z/B3WNOKeYsghYZCKHZdffijPEgkaLuCpzGqB7lbV7zbowMp3Y+1ZO/CTA
DOJw7wqw7TkQiJusfSiCcYKBb3xLcrpIJaY0US78eAndCbPQoSPzDUY78CC0KrxLH2tERy457IX0
IGGmH7iNgFrTKSIaAKDvFBOl0xb+S49+SGLBDGzy/swahELC8ziSakfNtCodyHjqtDAgupElWF6R
ZBqhzKsj08OJKZW8wOUSkKymxI/K8M6J2fZXQtYOUT6RZE9Vb6YKBg9eCqdTLdnDCr0wq3iyxJQh
43u/ffUEFUd8UXjBACtUr3GCylXbsh1OXG+KKl7jqXqLZIzv/skTHDEh9D3zmCpJjOTPzf59wnAX
Mpos1TXzmK3KkfGHlJHd/iT7s0A+WwyafN3fuJabiuvF9xLcvzROpFDSCD//QGAFt+yel3+6LiGV
7veJEt8wPBk5MudV9nZq21w1aL5lC/urh/XmRUwiXqgC+5b7CTSVwsh/RcXBc0WaMvLMPv8yaRoW
/bIshHpWrhp8zA3ftBjh/kHUUS1SOjQ2pYYJy7tRoya5g9HTXOUO/W8FashCMxTC7bq5T6B6QEVe
s4VSeQfLdncstlgn89tjdARCu+4FCtv6ew6DkmsvCR8mfdunXNDFwMKW7HyJmcFE8oCCnBDFj3o2
yU2EwWXElvi9oiSDZIqwMFfPoknoQnXE1hbzfhW/WzfEf+z0SSIGswXxrbTnlL4jz5aOb6aqCz1d
OcadLyMooPlDj12kFJP6bkppE9xfeNWR+iCsQi7MYmZI2tm4iw3CsaBfGQLD5dO9mvokR7foKJUs
/bS05j7dlAlBZoBavVLTKArDFpE+Q2Nx6ZzIDTI1A4rlE75pgYoyCk5YQ/s3oaey2AM1+qqNLyDI
d4GDBEZVbeXqhvQvGL1m0yOmRjcQa6ZkGV3QJq58Vc0y6hK99kwbsKl5Fy9o+RauYnwlErmo1hxu
HzDqHGw4frjc0y5xTcAVGoySzrbBDbFBcYEYYmUS91XIzcsScYLDna/4QvlzrDa6ZJiW4O7/xev6
OxrMdt7LhZFz+Bvd9Raffe3+7IMYu1ZTimvFlISsUOyuWGNHYDy9Y9CLFkeeM2tMlIIbTBaZ869H
6+SVQJCdNXmcV5zJ4AuZ/htRlRoAdCQgChlrjAb0IhCdBf46aySmudStrkxrSNEWVzvNX3RhFfjT
ZE1ZLIrrGwbiBnf0erCkiCm/U2gGctgX/e5ZiDN9Y8v2J3RKuThF5cYnIpxC21yk0i84iCz2MWg3
TQ5gyhAh7lDOtefHaiGDr60mbX93Hh6nmeCKZVFPNog73TFw+xgduXdFUq1f+ba6OKsonSq+ko00
ldMt+LGIm1jy0jIQ2X/T+nmxmVuJcwpP5zd9cFmOR1/bVOIxlBrNk1umIEgd6KGxqE9itmQ+7CHX
03x4Fz5MfJQObQgQCVjuxP3gOoCuhNkRe7OgY7FdEJXzMjqXdmlkHGUxf5Qy233BhhatfwF5XoQb
UfF/crKi2h0bbppmPbUYIUqkhaDw+r3EcCr3Cyw3tIk5n19yBW0js5iYHp2XKzeL/SXrN/Q3hEia
XXUYg3IsuGKmt0x5e1jkcPqJ3zZykz0OniJ6oWag2LgnesWQEPff8i6wc4L5ph1iMvH4idbWuY2e
HyhQZ6DR33Xlsd+Z8iXUGMQSTfcK5I9r/EF4TUCjrUmLbZzksEot93fVsXzgfXYpdfnF7zf5HX59
O/yf5cjhSnD+Mu+NQtAIjZXcMOJI53RPCdAObdq65rTzhNRMGNyUZ3iCVZeSAd4qHjO/eamoD2Ee
Bc1RJDAGohiTSF7WLxy6a9WfDL8k9+OkoJk++WAkEiNaKF/jNSyong7qVCEpMTeustoVfVrYl8zW
g85033y6Ar0C9WlHM6a2SwjOIENaBCpNPNdGWS8PBwfzfayxTq9iaxoFiLdctwQscwobFYqUzLfU
w13WnnhaYKgj0iv1cqVVGITJKgIiNoiMvJZpD9/YMk0jq6u7xcui1qlkufMdX1xlkL0YC8yrCkME
/qJ/GMLONLoTftnlJsdPvGOShnOPJiCPgyDjb6dHe6ovkgXmHWu4l2kkuvyYSBLqOReJ2J8/Dbf/
ynPXelSqGl0qC19vxb5dgvO5Q4or/VYrD5YSeG3CPJhZ6Qhf1IvveugYI69Pp4Lhj9R+7KNxeP+y
VUHZbggboH9BThlV+2MHai9m+pGocT1bh0dtdLQynf8eQzy8phqKjrZ6+YzkJc763+eoziKtm1JC
hPp8xiNpz4MtaQ6ct+eXpC2nEF8T2Gjvj3eVWtr0W7vzSM2GddJWHoMz3pXY6SP7JyFQqLD88mTY
cafXnAGJidrBZat8zXDDhzMRDMlFHpwn0WuLxF65P3N5WRiHi7R29aX7vVE0j2RpVi8Abbr0YUqf
a5j/Ib+tbInSG6M2J6Rdt7wabH7JYdfI+5qx5dMj+o72OA7hoWMNVw52c3cjj1zFtuho84CXQOsy
R10yTU1o+KPCswFpGV6scWcdb+lNZp9pmGeqG0nW2BrQL+1ZeoQS9tvAb0iqXcE57v8b7jXJlXbp
7Tdh9PubeA0IgHdLEYm0wT1i1X8YrVaiWY8g89QbPjpCgfsLtSwFmNrw6Twqej+kcXPdnYl9SdQQ
psiO+eMO+B2Hy3g4GHGOXGWGPTUi/Fpc+7wrafVVQdZgTkZy9k+qTy9ISLGPULTlwNzsr+/kIIHE
1JiIYwcndWx1TaP/BPvJCrqT3QgW1VpzGh2NwktIYvEn7eT+iKPqz4NzbFMPiT5JrdcZU8j/RfS4
lKCot9yipqXs/439e/jOGcHCoaupYYYQbTEVlACruvOc0wmF8L0Kbm3q9rfQPzL7WnBgJJUmEDxY
dbDTrKINSviUzgF6h/jwC0YQbBJuZLdqoHKcTbwoYsdgbLoKel0g6tMeUByQstPv8r1tZ2Exrurv
ebj8ZQW+Lo9CkutPJi5IdNq/xWXvQC//1no5uUha+KM2gjBpbx3zGv4pQeMzdRRinio9rER530es
cVi4jnFDVCKGsgrwh2wH00akGxa0hKfIGLhq9a+hzcBlNpMxnVJbE9kpSJNez9pnpCrcAWgdxQqG
hEeN5ksLBFvFUUKD1sPFGZ5yIrwaKQGNSB4ifKFlLJUB4Dj17uKatCfYu1rwz9cIf6A1ZGwqvq52
hBmVaMEKkdyFankHNKr7voCitr/7/0u9dnjQ952UjZIF9i21fjsF3QfBihsIcisPDDMtUyw0iRsE
rxTgsmViRQeIYcZUU+JJyqiT71g2oGuicpQnnH6ZBaKNAvmddMzms59J2H2G4MAtd6LaE+rgimNg
SwE42twVcqO7t5/aLGyfTyPg7LZrCfItckahF9orPOtG6N+cse6+11xLzyVgq1445slNKlYJoUy7
u2UsohsLFDq/OCKgIvtfmeCtUHLuqkG92XzXWA4rfFW6i7e5+nIGwDB7/CRvTbaAKRLpvZY0lQlw
F1FsnoXC/JFTD47JQ62u5nfrpLHFC7nM+3BR63Icta/UYSrUDZt1i9yiplLfkS2NrE2zC39d7GTN
aXcBjro4c0G6ibyEQyzAClKiJ/3PM6iRNRzcmT4rsGf6tV2t/owuuByoeXJITOMNPiih7IrJw1eQ
MKBAUL2r54szy0aWFtE8jONFERk3ApGHhb41UeQb9V2esALPdUVGP/bpw1DcurgppQBKaokdCfLW
oH7NIMhnpZ/1X3MVjmMIDbvYKN8CKrJjp+SsSZ5X4+kUHTsPTIDU7tfwgZM7VbKMmw0Y9UG+HDmn
HoOowN31l8pI572OrdJPp6STZAqwLw+QWcRmywDdSR1KTdyA6sFIA0Y7T2IN6d08MLw+omJQ54T2
b1tqRlenhV42AH7j3ErQGC9hdxx7hEExaF26xsGNGhrIVqWqTPZFzt0+Js97HnMOq63jYegLIxut
Y/77ZLyjiZw9/W8uzly8f/zxv1a2tlJYNlmu2P5DXmcPCMTGjdabt9WfVF6XzT6X4i8n/LHF7FzZ
LsexEWukT7EQV3bbHArirzO6pxvdafigGTkGf4K1vcbfZpbY/MgjtQyRyyB5IHpUW4z78CrdP9zJ
ToSz7Ldier7MR1QKqW5vpnAnOYOh+NCh1/3t3MVw+1hq2fUJnkg2stm+ddX9Byq0UUb15FVLFCFK
oVYntOFAZiJc914FBOxeuju8WDWVVMXwP55YMCvDkVqrHNw2f564dyP0ElPMuHuEJAh//5r5fPVh
vQz5NO2BoJtragKmrSAHV+SzmvOQzhqltzyC7HCrFuEjW7RZiJ1Zf3SDO6+5Y7EC+Av7yxdzI61L
3WiGM+DS/QsYUHTban93m5zh1Cz3yCFVyKHoLY8OBUvzCAC3M3GwvF7LnSK9c2EHoaZKD+F6alZ9
y++hy7BRR6GFfRS3h1CWcGsf1Mnl/Cfncq4VA6I/oPhm87T/kLeiRoK7Bwe+ltZyhFeElW0b+xSn
gUqvW168gzx3UcVLFJf1TTW5JjYMgkkQx04VmkzMNr6EtILyS7aDoUgluHqrJnzbAei1nzG6B+fF
40b1/gWiWEs1i8pd3noiu0P7m72lG18ASVxaRm2GDra0lLQ2ZHdEVQowWMKwXmgg1ffx20L8s7dP
7RmR9t3appteKU4S4AYbE8avORmvO53y91uxliPKcVh5PIIaLhXkmpwbwxLxjJ2j2c1O7qtDgc//
q0BcOvDjgq/P9zsWn2DIDMplCjqFAiKogQ/YclY740IhyYtOo7zUFMBVTHZ208qEWQjMTZQ8O8bi
lZxKCm2aScRStLZTnwKF6rzioEgoyQNq51YhfL/OuBADUCpU9NF9/ploPcXfCIlhlHTjd0C3Q00f
YMPq57m4LMCIfYhRtwRe2IybKfrkCglWRUduD8yuDsUYDg6HALuYgzl05j07AYq7u8QfVBFNsZJ5
FtQFyND7/8FBTRAFXb/pvbnUSepctKnSNjpC/LkXq7C4baFzbbE623uDhGjJsp8hzoakOedN35pO
N8rdMmkGKNdGNu2vx1jzRUKJtuUKUri4aZwPAL9p6sabhExhYHf0pIBqEJoAICnIV2AknZOVmjwE
j5VmV9fxeG8gXKGnFOsoE+L6oHUUJdR2paoZR18zitVXCCbo5hJ1THYP0xeqBtm2n+630Cmmvjb0
+N0KJHfiebXQSifpLBbW+qH7ygpTJ4cgFZDzS0kynHqi0N6y7QD9xyO5+cVNRC1b00HAWu9EXMeo
KSZtxWUJj3yRyQz103LAUhjcIcbL5fU6Ws7wPTD6m3Zp3e++60kb+hyJ2viTHG2ZwQ2kx1Z9aPko
iSq2p9vTV+Jj0g8Hf5LI4hHxaDwaM7pY+b96C8gth28wvsymPqplYWTNteUpzLEmLlWhlf2tomRS
3kVYpGiwsHGGXuGGmzI7BNUld/5kxNAJ6mtCacLmemRHO7jasWJhw/6f2CVNjr1p3mOFSv7JIXvP
H18fApOmVIKH5u/0e56G28ve8NwL0w1903dfSVUFOXCqSEz9ZNuJjlztPhv0EwkgKxXyk+KCj+Kn
+J8/uvKFqyhuNjjWf6FPTz9T1PX2byxnD0wMMRqWTMiOlSZBWnBUVjrySfKTwjUgmZHUnGh1vHsb
X8VA0Xc2Xmqzmo1jHpon/mDvJX3gFUsJyZq4/YCszJvzmCR+iCFIil+RvYczStW73SjukVod8o62
HkjBLLeCXRaNEk/oC45ULGr03WJKrG+XMKHDYOJKaVZy7LBf2xo8nKq+svhkUrt/xNktjqME/dAJ
13v3s8LLdjhKdaJ+Ryaos3NgDHFowdiVRC5drp5UygIYtddmQljgXpRFHVll711NGHH+9JGQBitb
anNlzuhKa/rU+A78t7DRH//Sv9dW7leOTvd61P8Z+wcZUtkiIsQthFuUffHFeI2XaJaxp3Ca5qKP
DxIdMTRTIvhyK0fcoWEPRDy1IFqZfk5PSNBafn54XBXCggLX1mte/YYnuuo7xpsSzLCGTBzMmso4
8gyrBB7AbxtUIpsQuJzkZGZNNEL4b9Wz2Bxw5iz6CAC/HryRDha8BtQF72sF4PbGc+wCuRJLSlJW
suoK03Jc8fplv+63CmXBe0cKNKwuhjpBZYq2JVXtVIX3kxSstHNaP0ieO2YegxjOQLzGabNZiSOJ
O3Mlvi5SCL7dJD0QaY2VClCIcLKrNV31peEdtniyI+r8vvP9KmqOUTwVSCZtAiS4FkgeWPj7ouou
iok1Uvpep0lh1aR8F7LteBf7iWm7slp4JiroAiRnLi+Gh9nAsYzy+arfihLdPJMjJji6Lpx5M/bD
h1m6+avJhYg5o+I6+57zpMjvQ+7mCaTsN66Qk9reVYEaYJd8gZnJF7mXQ+8IpgMo23iKgS315zPP
gbhUHagXHGaESOiS8pSVjSQ6jTjHHgnSRhc6Zw28rPzPc+x/19y07wfLBP+Am0RcEKj8YZAt4pOK
5zPmiGlMTlwxN1AQQkZBxuHtuHf19N9HywXoLr0m8uHBLWaUZnc2akyom87HXORp0EsQmGCyF9ml
eJoajDWUqRE604H7fsx1DyfQPCBSMi0pRWBi6sNlAyovu1ICYnKJeTLSjoRVv1rlC+UB51xZiNbE
g0PQHJ1LwlxGl+5/qqTOAP5WP12u3oOAiudO55+2BgOWiKtMd6G5POgbrCpCVLKWTjtDqR28PpvX
wHsnT1NpHJ3Qoe09WGoHM7RIhAmboaIT4H2deZfcO4JSOnkAb6T9sJqUW6XO1cPT2YH5moM40jAo
3m5WAE3qskMg5RSG+7EC0xyPQh97v0Ie5wZ+riP/QdLddShF7advOwwQQRgYsqamh3PeiA+3M0dn
pPCzTphfLjqe8dUFwA5DCLE6BkokDpAYzu3RGYCOb68G9Ve4l+/YiH4gJ6y29D5Xtfb2pgffr/xS
WUBLaYwqfo+B5EFOGUXxxFhdCKaSbTchBiAsGuBuh40ND6v6yBtvAO3ztSST0JSBpoEmBsjDCSem
SnOtH0xN7+Vi7Te7sRAhg7vrxsvjrxwYgtDe+rL8EvRMdoHxZB+kFW6G6YPZX8B0BiKmJbpW9o3B
pr4GmiEWQWgpq5AXOsaROJATuySxrKIF5NSJ5ZOOe7phG2mUbM0AHjiX/04xzAqmTXk5f7U3A6NC
8A6bOUBdwiHmTVn+Kt3P+AndJMea5ZtNirlDaptgGiZFP1tMajwj0M1AsE0LOtGJ3PavhjThOrOq
9yMreq3Gq3iXPfZ9SbPuGlDxoXl4P/7GKwBQxOLxNb0404pckrE1iSBIRoy0wig3f9cejmzLBLGl
yD0C96SXQO9CBu8l+61883v0ndo3mwK8G+4QrRxzSdhyeGHGVOT8v4Xg5ZPP3AFyhZS7eQC+21m8
n2T6fxI2bjlwmpaVVrxqokZC7HIS8CbaooJd0g56209A+LYjvZRkKj7V5SbusgHL85mQp56JbSbO
Pcqfp9wIsDF8wAI4H2+ZuRIYhF/9H6Lz+NGmFlpygPrrCwkit42Goco/6TuldF5NIUYOg3HUwymm
a6M0BbHSjGgViJCOybrHFGdA6U3/bSZgOGtRfeC/OxRhYe8b0AlHa6HK5G5T1zqgXMstCk4D1TuX
S7woACWbEHTwph+nLJkHMbVv0+s5PyDEZrnRuebVQ/4VvnnvgvzgULOdSnHoTVfhQG9v4m9NK4IT
EZ/Okz4xXrpjtwWb4vp/able4sWFXztUmtMgFuDSVrTMETwqDZC6Qf40v3vnMD6PKp0MzsN6VBOs
gpOKntXbzN+IF+9QQltgGKFDSpX8hrdp1GpQQia5j0T5Sa762A/hu51LhA7BQZ0wFZ3KRhoUMCkB
tnssBUb2kbYI8K6as0kCX/CPmFLgeimSVy2dH8w3tyuPxotk682IXrS/kZN2qwUd46lQHTsJBN0Z
4qo3to9Zbwd6mVnVsLF1lhmLqjPha/cAqVYcyOA5kSXKOdEASDWOs6RQZY3SGB2Wd0yg8XbWvUzb
q2pv0gPxS/WpdiR9TLbYaxBU8rjWJ3pQAybR6XhqhFXTNGfjnm7B0m2lMWx7+dnZN82jgJX5BLLQ
Ww6SaxFUfcAJkbYAk9p1GJQVNc+dMptAYaEmCIUR24MZiV5GYqCdYzeOCx5+wYS9JQDoNNUtJxTG
c9J1WksP+L3f+GfwgQNlGlPHCDKPmUDu71ljm60YjgPj/wuvLxaV53TF+W6Ja/NZhqXHSEc7JPly
j0yfP0g6XW3igAmdCW98bnqWm+LOk1vpHqhed+Cd/5Ex48lGwNRpPcvOYyU1tngaCI6s4VR8PPLc
eSwpBmv6s6GK/AX3yij0xaGcynQJLtAEeOa6MyaJvcbXdTHpT/cYvPCvye8XExnOMlwe2bAzH+vw
y9sCgKlsXguQ4e6L/fQk0ObW8CeHHvM7ksCCPIu3SY8w+J+CABI/eUHLp4BJXjDzrESU4YFbh3S6
UZv+uvj3+HaBrbipUCJD47etX5jEItzlkxBrQqkxh3DT7obK4/zhM/4du5F0TgHoVzTCESrK/Pf4
5ou2ak8jJrxAJZsrvgw2p7zKFjstb1BgVSxYHzrSLBW9i1iYBNfSEeLvFtRnZg/afnwujtlWYxQ3
Xk2XMTEAXRm+b6rUOQduitgo8T1nP6X5yu4iOB75CGZh40AI32fS617I5Z1xSqHoCWrtzlj+FZE0
T1VyEIZglbCHGfqGzbKa990no1ikhRJQsDphG+VE/5VF9fKRF8b0aLL0pMuGhmz37Hb3aiaP5ukf
aGczpuDYcymORGIWbFnCDdMhzdEkyB15Qiyb968wPatUBE1CJPY61ItyW0GFTBXTTUOfuSTbWCbs
OVFgJoI6IFrKPxGh/xW2dEz69O3Jn9lDHCQb7ue8ooz7d6YX6Bp4KY31YpEz8udqmaBqXaut4J38
6bUVMDGKTkf5QhaiXh4hS9pP558WAPTk1Ag7xar8mgiy80dYtilTTC5gj1pYAFK0dyXDOG0DDrLn
0eB4+x9PKnxtLAZUp+u54l3GAZKekLY7ZmeQzEQ18AOv0EEq7aYroXCmIy4cM7EZEKAnCGug0gTh
NSbZxCsWOLsLyWWEEKxDG9mV3p7e83mQgOwZtJUJJYL3wBlL+38rCYxxxiL1o0GPIFRJRj9q9Fnl
4FnMbK4FUfP4Jc9Myr97Qt9V4Ng6KfdxqnqOKHKpldvvajq/cCdayMvTIISJ81nNu1SexIXPhrIU
uwG4MUz45NKukJ9oSdkqoQgY7Ej/xaXFsLDiLTAU8qeJ5xQKSIxBwHLqb45U44aru9eGbevu2p/6
A01YMicCGFdJqAZHBBq7satrZkaIPAiLGzS0IXNrMdE/ltFQgXzM2IE0pOKmFpREeu3cRFznBaJM
SfBLIqRP7aSKEOqHM212pdpgAXtL5nZ3eODIk5Thd/W4lgcUhQW74x81CuTigVBoeY/sok0DM5zw
/tx5EQUoUFEdp5M5UflQdYGBj/8+mUaUizZ94i4lZ32ZnDyPted8Cu0nqXLu0/UYC4niCe8pyZYI
HqmWX9Zn6Zo+Nc6IU9KGFB0jlnoMotgweKbxIJbPjYI5BIfTWqajd1s91Iop5XXctJnZeGPmTNU/
m8nHR4rehcR56Y6UlJxSi8p8WEKeLrJnUw2wMGOC/JTnNvWopscTuOMJ066Ef8z2C2bJjLac4f7P
Drfi4XeswCGI79pZ01jaNjPPmQpkUb6q3U0UB9IhiMF68LYyzKNTeRtI2Gdegvz2JNaY9+7dLhjg
3I1l4PpUZa1bBvNsC8Q7D5rYdq6C4eSvRG//td9pBITFd8s2LV2wy7lF2kiCgocn8FPpfTbWV2Tg
sN3uswId7Lg8DGmcmhhPf8rkmz2H2OBzpoYEJkMCP5yQS/Xr3cqB+UZ7MmySxPj3SjYmuulOBsRJ
TRUEiaRKK57dsOf81TS5qJ5+2Xd6nrtxQzE2kZxv2InaiKf74CSZfxlrLEPRR6lRSMSotpDMv3dY
HnV3HUTiibwmE0bviQHqvFr8rv2gcFedwsdCZ0PMlIFN+il9/LYwCMB1yvgiqhg59uVe2M55iV2h
dEJxIAMzOdz9fn0qUUz4yhmTLxjeHP0aWZ148N+1ssTMzCGLfX0+i414Ujc5IP50V//0RVLbztTW
oJeJcDBgbL3y/0hQ5j4Et/Nnt+df8Mj242VtUmcqQI/nvWUIJXWA8yxyTBxzM+rp2qpt7UTSBYtr
p2lK9OaachoBrjCntoB63Lev/Ck32kw7wqLSoiuY8i1jvM0TB78oxAG8tHkvBAv5eHw3VCPyLMpJ
1ge3hHOT7QymV/i0/fGloqPK3sfUlTUcN+Da2/KB1flGXm+NUXTOkYLOByiB9E7fy4WmVyCAPu8i
U7hlDqVu4ISVvQNZ9iXl9SCCa9HqtxkwtM8FJ01tQ8cx0U8+EXjcPb0bzzKdtDZL/Xx6hCMzxTc/
RwAN41f6fa0l6/oQPFkgAc6jHr5bz8xJlPJKXmgu6Mj96/sCXKGOr6BMF+8IThrpqyMZz3aRM6gQ
7V9ncy3CqAV0uyUJLT1jsHOmg+9U7NgGZFIv83gKkcpMq1CppZUy7+bMQN0V7le1Vw0/Bj5zLU+G
xMBfYyeDktJZQr3o/N9NFnL6sYNelo6nJjgsG+6DR71hLAXyPwn4FXtkIvtWXYGvl9StFvcBTNis
symeo/EjXK8Ea/Dq04baEz7Mb3m2ZiodvwzhR2jydJBDwfjhsN3/35AHIR7658SJ5pHcJCpf7YQf
Bg/ejHcbtEDxVFAplcek2IeqB+8hJHXJXZj71xVmcbuTOqgQ/vSpFIUjNjA/+T5p8dJZgGGjXmV0
R1a/AFtQAoOTTwJIaqavCH/n/OMVZcXlMtoGXYdSr0T8zCCe3M02Z9rbcFbsQ5Qva9A82GtCtvPc
6UV619uxljrBZdqf9Q1lhYFag3WnIBilptik10YrsdRZotrAVGgaFA6wiWDZjZBzRFZ/x6A+T33C
sU4Bd7ZdIVAgHoazMP2ocbThY6KK51lVFXI01K+tj7lha9pmbCFU4gBRowSRSb80Npfdj2g1OiK8
pZDPLivNU9gUgYf0dkh5iMcMFOC0UtRzyVIF5+XmwxKaN8e+gA06W7sq3Vvmji7Rk3ciUrwgD5Wq
ZPiFeIQa25a1ZW7JaZn78OyyckGER5sDdUp9NK3xLy9lEpXQIhLB9fC1XZ+hqJ6gDymtmPZvXPyB
B/00TQjUqSrKVwpt0EnYivYFTKyVTfrU3l139hu8IPIPBum/F5hhvUm44xQoinaUQa3lfp8uoAxF
APNl/IXXhTrt2aL5vWMHPYfbhvgyKCkZcSLH1401hYHFkB5TL4xFmsHuLdv/EvjsKEsXj+8oqtU8
0UuEtMLVWPKpR0awe6B3NXg7W60Yyr+TxipA2gL458ctoQRrQHPApBgW52wQVJmFUXhwm5FkFMWd
FnNat9Rw1GB03Lbn3SGnRiGLnqmLrQ8XBYJ9YVtRoicQb9rRjIvW8VTjXFPu37hkyApIqHqO0buh
q4RQQtWAqyChohuFT16r/pfcZ5WE6HXn9YSp7KJ5ZmPOsM7tIT4glfCV4a2uV6JXgep7ITz2zLqh
9FcB85ZjOT+iNVQKD3mCHrfI5TbC4371DpxK7li+cZBO8OXKD6F9J0wvdbRm0zKrW+j5FgSxI42E
W3qRDmvCjnqsUjBxyVc26cWy9G6tyaUAk7bXDl6350x67TdgZx2hprP6b6+ovc0UnNU/cCN5noPt
wyGLxkGxtScErIz1hOC2M2wY6kdL/nMBinnzOh6PUHAanw8SHi87NigY4HOsMa7XVMGiZfUa3oW6
arpdyB3vW3Ce9zJUkp1Giwdd+wbkEJjUZFPPjnTeRtle1zsFnCV2zOAc+hbntU7+47KNQxmZ3gpP
OXDSF8ZtRlSst3UYRTkqbfjXNjfDaoKs9oxYkNVWJ23rp/SoSPgzufYkv42qu57uhhrtSl81zNez
j4ex4DO3CpxBgPqkj8FLq+0072DCEk/LsW271fLxefmxj6OFUCwrUMcKYTKnFkYldlMuP0pqsjfA
C3mS6nqRn6RE9dUDdaRRzAs1VlYXOGF+47e2or2YPyph74uvHHOehRPaS8gLp4+5grZyM2e66DDS
OXaE+P0f/CBesT9P+D6UZIOXbhDYzD1R1VfajgIqo5ZsqG1fOmikFuYjVhano1E+N1iZUhSKXPgB
P75rCXSznum4OrnlesHHOJ5H7ZQZtkYvCVdu+AqXGCTE92hbiW8P7LbncPDVBUmO6G9q9Za+wFgx
7cSW/qoQw6ttcM51pxfsbmLisuE7CyXWclnsnhE3keIQs+hiS0D43/34tSSBhcgqtgYhszpp0klE
sf17w+dXGP8QUd+eYSAJsi0TB/tX6va8//JWUPam5ntz8+nd5Shg2a8mueP4yOJUrB9V9spIB1em
Q146WiaJWWMlKmMZQKjTvN9YBdvoXlWEXH6LUuwF1APZlfGnaax16mhdNhwgi5DeHYejuxjMoet0
bN32mocIHIOMVv/Qn6Cu5Z3mehOqbH2Ohbhu24Yhp+lKSh1KcNglO4Xzzn6IV5LtxnRAEitkmhnz
+qYBCgvuLP4lSV+BzndyYtLyJqCz9y8TZN5ZfSGQ2iG7T7h/LRN/ukzGMfd4DYhcWwpTqDtIfqq6
CgwLFHnwEehvrt+5B5JEVw/LKu70xIYkz39vakz3Z4gcaxkmomWG3Xt2fu8lsIuu3J2xC5de7COm
x4EK+VIU4DWyCKGkyR7b97jboulgYlika9SFJ7q90lbcTalwc4nq6pDk5edDJlKZWaxxFrIDN+la
0RmdflkMNPh3spmgNiE/HLZGJO2GOjxkN6jYbGht4+8ouHGefBt4+WbXo7Po52TnONh+orLn/xqw
AUnV1QnP7WYy6YyNRUKKlUMBAu5bzJ4+2HToruhSV0wT6nT79+co/AC4PBl8bcQEFCmGDw031E9V
UrONG86jP186ZzuUlsYtd2iPmBfBXC3kevdLVRsJvYVSR6iWmNe4Fj6ikLTeS8oUhp9rI6AWazd4
vNDJTpV/4ceP44ie2nCTCYcjysuZS6zNOgm0Ra3w9cX3zF7fJ0WJ//sSSxp4fIDzteV/mSyBuRrR
rZWpEq23uOLb2CIEcsrFjpQVZvs3XR61VgqX1XUODAq0+TuOVEPiPBBi0oZVqTALWas0lo/+gLm0
by0EWj9FW4A+HlijUE6hqROS191FA7bGrXuOsqrMe91bqZt7yo9C5XoBAU5RghKYMRu61Eg/zVYB
j0QdDrTU0vVm9wrcL6kzfa7Nr83AR//0kbVxGGjOB9fNN+FrPZzO/rDOExRUoDvH5iGVgixn76vc
v+3awaiN8Fh9mjoDnhPe/Xq1URR3gA2drbYSEZ+ypJZWlYpHKj+GvV15RNTG22jStHrPYEVIFPth
H+ZDtbo9XF/fRNx9vG770ClxPCfjLBJ9Pa5IV1hYtIhFQYr2wPwBgXXURRO72hOxY2jCmd3H3OQT
xV3swasUYVp76ThgNqnCo8iejIluiyyTdVOKKbi2/ry88qpK4OaU5Qwql/i134z7YkKFq5c7DW/y
IlUgJVJ2/qTvBqB1dEQPyVZJNUqE/ffe09e5LCDRFFU5YGCWIXArURyaYA0eFAPGMZpTvqpJ/EmJ
EvVdAkgwliIOVPr5cNtT8H3fYTxK8oWb6O/PqQdxE1QEowiEJHxaqO7Bb4mTEo+9GGLCup6Zlpx5
zoBvPjgUdM7ON5srlm/5T9E3BxK5RD3s/NBvRvwCf6GVcMS4dv6FQJ0PXw5gx1wC+j9Q6f1RbK5L
mGY5jvDYIw2fpsY7BiS9LzKoiDdANBY6h4SvtBJPkI9lUsOoLTCUl1eLmyxcUwV+zbvt5ytyOsqf
h1OcDj68JNZjDriHg00UQx6ajJa0DZLpdJRwBJ8Dfg3Xdt2Qw/OCPuAkYBMd94StQrpxHrP8HLBL
BrJCdvRDCKRGS90lQixHy++3qLD2c6WoskdF3C2q9Rf6adS4K/++0M100qLL5wRjQH/HD73LuB8m
g8oAeBaCQeO7WG0amAKuH4T0s0UdvszFtrCzu+mXJZBL8V2WjnPQ8xazf8wP9JUP6oEOyGkw2cl/
yfw5vIkJRhN9uxLRZpALLtVIqIJo1z5BSKf70h5JWIl0xO5/cIugnargSGIcvheFvtVoBtY1CDAt
ACCEPlV3NiB/AzrWZcW/7A/hRkRAlAd698xePdM0qxoPCa3rglEeB/P9cqlIr1pEi7yCFT/vmD6b
0nEV/Rncwv3VKgPpkM2XROuqpsClvbt6DgMM3UoeatmT9//iCCh75aPwKWux6WIxRiqwdiXoBoCC
uJa61ItnD/Tl4N459aXynIcBTgjT6ZGI+dvRDBJ7klsWkppnpFLCUr5OCVMrc6dd6aUNwZS1iltA
rgxESR5hRJRuY+clYV5F52FscQUEF45zf1pV5dQ4cbobK3OhYG/AoUulpcGnFF/9iksFnX+m2Grf
wL94RwBh0vZlDFFxtgbMX20UtLqCI5mjfZKOQwQkgfCpfA1wNzaTmknEiVQK60VXjrHBDQjLIPtC
6U3jGySZpvBFySvPsDTxgj3xXzyPyJ8YPLGZjxz2J6xaAdHFJ9FoqnUao6P5ykjlzNl+zLscunzt
F2iffKV/m0LGGaevTp0NN4B6A4NCVC9Oq+QiZ7zhoZuLg9TwSAFkTQZF70xrtKPzl4Fhe60EKIhV
8kDuHTKw9InJ+zgAvp4i8gh3TVV12CYwxDLP1H/6QkjznOM8cgxurO8LD1YI4NSfAH6yn1MS2+0S
v/1tmhlD2farVCnPxKqtPJ+VhEnDzThtGsdlaDNzs0mlGPs1A52ki+tDIEJZqYMdQjWVGN+b6+2e
kqrUQyucQZXuzmw0h7JpPRdGwJGRD9q26YbF5+Nfg8RmDEI6H7Qn0YvUWcJ1BjCdxrtrZzqj+JFb
0OUgE2j29EoYD9mH3GceFmMuUuzGgo+tEMNmDeccD+cLPPqRxZ5hEAJz9a65G5DJCRJtP5ePtmpj
UvuWHwkEfRgwbMMD1lvN1w8OgxpSiYaiOSw56f/hMiuHEvgBz1eb+04SNre0NHSbt91JrXz2NraJ
mjh/U6DgQjMG0AqlHObrTGXCZqGF952d6mZL/QZjhw8V+ADSpm4oyvVlOwh+bQMabz3kGwcn0+xR
8oExjTkUDhYa0NtSmjB6i2ihvh+3mF9OQPwFe9Wk1xJG/CgBNA6emuEGMSjTtRizYxln4y8XHqDl
HodvC7Zngr13525dMkGKs3alx4sDJRPCQ5BHZVissKoGSZRFt409MNgQ/rEoRiILn5/+hB18sOUw
Omb8PqsPsbP7zjnx/ZUlDGiItw4V5/E6rHzsBAlSrjTrShFDQY7DDHdGuFj0I1RW/kQreZqafDXT
EP5+MMF57k5hjG9LM0pheg5glyF2e1geQ/JHjaZtyozzuq+RwA316WETrp5zYdAzMclTvEqeSM+7
splY/33z/wv9/PT97bRwO5q5++LwEK5BpmfS2zYL2v2o3jvNI4YV0QsbFUOmqgFNTzg7you7r6yy
Rr0lWRKuYzQs7EP9L8sCuwSv22yQZG3UDWDFcmKlKRg1yeYmpaNlxAZHXSsrcPqbNA0T8jtgeGX0
APMe0CE59JAWId78OVWcZbVYGhbuSR3Hrp+wN5T080z9zXXrQCt6Vlh25YoqhWsKnRVCZLEPoSx1
JhQYbgKDQJ4OG0Tkw1bgUyNt4hIZOdRUwsFTqODtrjAh6+Wdw8jorxx7IR6abwMSpyqzjAD96SIO
BDovzlRX/U5ovH1TqqhZP1uyA3KCT2BKyM3U10wbRDUiSZyC+OGSJlwQ2UZtroDyk8MCjUSDeEbd
LfTcRPfsLzU5mbuMowimHy9uxzcCa/6L+QgFV66+Ej/zaYB52DKajAoecIw2gnlOfDxt4s+mAsaJ
/AJwjcsGjwP9aZIKc9svcMwwQkbU50m02K0VWF7QH0UQNdt1eQ7Crv62+kAFTRbIiuDgUmgGlQJy
RT8fdj9yi3YJGw+5N7Dam7rRBVtZZvHoH6OMlagkByNRGCNP/He+V6xMiItBs5bl5ebFUAieBeGA
lEG4sqv5LXZnv/SZEIDVxzDX1VNXPtS9vYskF+fKVEcx3zfas9+bQO1+NpZAsgMKP42op6d8Dlc5
dUDRSwsbHdcckEh7hxbb1HJJskU9qmQRbAExgEa0fEqrr8gV3sUQmzGqmz/9T7HnVrUj4k0jiI8V
GCzr2AYW7bSZI0873f0FuguCAPoZEciCvGcJaKFUVHHpRA8dVCvdyQ+4y5wISnGrZam1dmBMWZc+
qTWKdAFH1Zkmqtxk2uYla9InPi7eePdEbYI78iUGo6fPSmAa8IWnD7Iuya3HYzZFkbc64vq31rY+
PO03wfA5xfZ0LkAxKKIRIOSSd6Y22yrYa6YJhn2ycfOZwFJFPHBcOLnZXCJfmJvhZB8ffGa5P+0Q
GjZaR+4LeXwjs+GIsBuT16IhbPOT15NR+l7EOaiHqiOovLct/L9zLTOyaB+7dWdJ+TQWszPozXyP
veEIj1tR7CgBBtCsu3p9+ihsvNyhkAcHKYGSxb9VjLsB+rQjoUMV3X7nn2rnfkWfCuptpz9pNyVd
qGRoIzpXpbCGf0s5/EfKshb1OKCmBqC0hgVs0HZ+6WoNSOKbAoYBpI+b0JgoP+Vtxe5LChzwNr+d
LuauNHjkKgy/vPCegXO+WGu15PCj8NspnY/y7boPshFMP43VmridSqTivjKvJP6HLxQrzLCMFojF
l+FzzeisiCJ4qpC8JwIJa9sKuWRpsnTasF2Lsc8V+nTe8ywSnxB9+pjtctidhhGj89TSyZRshuP0
4ym09TZl3yf0zwBgUSs4F6V78m3XPD0CzzCQtc8AXts7bFjCiT7y/RVEBFdWf/aw+U9ah1i11ktz
l0PutgfQyGxHPpY8a5a0Fdfuk7jUJFpS0+bvbWfi/qsKID2EMj3OIupiBe1oGvePzNJdZQPXsKuq
SWL4pUN4g+F2KIzSk12CbpxP9QPVl9wEjDyg9BGsIfp1W8dxTvngCvHsJ2HNyLvUNhgnAzW2LyWA
ERHZ0jSjb10/NliXXYPzZJn1WasuQ1ESPkGIeFpbOH0Fkeg5tXTeL0/QrAp/m/Gvg99o3ydLJm/y
DU1GcjLfpb0v9aCbDH2kNBZsKEpWZzD+mkm3MuQke0aINmdVbcv1ZRXybX04iD+oPm9pKaLkqm6g
LDRDBmc/dBb+cSqC/bSgo2+vmsr4OMKQ4QM=
`protect end_protected
| bsd-2-clause | 0b13f3147c2d74662786484f46211504 | 0.952073 | 1.817237 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_rst_processing_system7_0_50M_0/sim/dma_loopback_rst_processing_system7_0_50M_0.vhd | 1 | 5,956 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_9;
USE proc_sys_reset_v5_0_9.proc_sys_reset;
ENTITY dma_loopback_rst_processing_system7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dma_loopback_rst_processing_system7_0_50M_0;
ARCHITECTURE dma_loopback_rst_processing_system7_0_50M_0_arch OF dma_loopback_rst_processing_system7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END dma_loopback_rst_processing_system7_0_50M_0_arch;
| mit | 9d87277f47a981c925d3c3ff9bd47f56 | 0.709872 | 3.579327 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/obuf_tech.vhd | 1 | 1,073 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple output buffer.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity obuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of obuf_tech is
component obuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end component;
component obuf_micron180 is
port (
o : out std_logic;
i : in std_logic
);
end component;
begin
m180 : if generic_tech = mikron180 generate
bufm : obuf_micron180 port map
(
o => o,
i => i
);
end generate;
inf0 : if generic_tech /= mikron180 generate
bufinf : obuf_inferred port map
(
o => o,
i => i
);
end generate;
end;
| apache-2.0 | 8cf68f9b40b14bb43c04449ee57dcc02 | 0.513514 | 3.859712 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_status_flags_as.vhd | 19 | 15,251 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
iEtOB5S3Q/0nxxj3yhZWc1e9CYVNx9kxE38Uvw9Q5GTpbeWA/PaP7MHi1hZ25jWcWTCQq2m6lqXe
j4/ejpW9UA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Xuau91ineWkILAnXNctj7ghjv8v9lVNvmGeO8/qKPRA098IIoEEWbPkQsDw9y8PN0Kc6j93b9RA3
24AkaGw7vS3twv084InDNHpEnlN63djkx5ZcyOiUohe4xecSmu6QA9TFBRDs0Woq2jQD5/qd0oJL
/BaRHEN9wihMkCnRmi4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DukDx60lt5tRoBa9fYOjxQXcMx39PTzSzi3mfBKPNtGRH42SBSoh47iSUDQLozXc9RVtQC3PW07a
TdEl+U9LI0QpSHNQLVojqhahZCfYOg99dtV1mWPojzxtpV99k2zYX2J3PXN/YbIzV8ZxTpLcq1Jp
CAIcrPJ/34KYVzvzXFRsvxEfk+CxS8lIGg/nVz9ZI/SFfi31TG5Gc9nsiydQV6NxDLfMTIZ9geQt
WjMt/ZdcVbixfIDM01Blr6PmvrTG06LX8uxL31TQuw5SZfsZBAh/PoXSzsMleljAYXIhMhdSUOnh
qfkHi0I/YHOxbZGvwoECi6yzPk1O8e4p+mbfJg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
JfFouWl9C67kV59ngW+xbX0i0eu6h0roaptqFtm5oV4WYkqMJEDqBwmHay9e7sJ9CO+K40RDFIJe
/eeImbz2XS0Q6PwgmMgPAHRoOg4fHkGIAEugmb7hj+mXvk7iQo09CaB7HocKsvGcx4nu5U5a1pLQ
6UjYczksNjCCieDaJQc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RNy6OyrkxjF2nMK7NTVKf+mkYRQZVhnkvdhxFI69h+pJImlNAm3GMG9cNkr/rYPBFr0KpngtSqYa
zub6qdQpsLCoZ7qDFdEc1+wws1xQHHeB7VAyyByyPc8Chu9XZcfd6cEAYC55a9lNvtmKoAjppEfF
hj3OtTTwZQDicoWmteMIzi2n5YcjhwpDSzFHpmKq+NQje013CABovpP0/TVMHv74ZpkyX30HW4tb
0iH2SzLvUD7U/AR0ul2kht6wcMaLE9E6bQipSYn1DEnfUpMfQgGpPJCWjykHayljMFWfI9ucuNXK
1XTo7EI77uCstdWwv1uP3ZSQ8pFNDP7NXG8mpg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9552)
`protect data_block
M1D2l4NxaLnfXOdDYZ2QszdutNK9OUT1NJMn2puQlbjJDzMn1qJQNs9iF2LiWLluY8sZheoitPqr
cOhqBS2p7ZY3GerPC9D89CUiIP0GKTF3tSraXs5YDGUmYZiM/7G3t01P28yYppdJ7ylv2NaOpWsw
iQTeLvDDfSGUA2Rwqp3PXYQTnzzuFtcl7O1qjcjpo1QVugMgdmeaTaODmo+zdp0T9/10DxMilPvw
ij5+ey58622vEGmsnw5wncVKldBNRmK5fenecl2OPkFM1sBYsxCGbjSGlf3u+xsLO9BpMLLaiowU
J9e2OubNuo2ujy4CRM9lrrA2nm53SXpVVQMjSfHTlU5qlVSvozXnA61B3uC2A7EoSZPi12u2A9Ig
mDDieh4wP3pHT7GGsYteVye4UKQfrJO81nSxnUeUSJdcNAfpFEOOEXdCwDidNlWTkxiuyoprWes+
GSE/SXmaQpArcm3PCG5Fik9PgXMz7fN2fKhTCfxWVxh7giCv3f7iASjLqZ4KWd4SRrKScAl0JUtk
uc5DaKEcrs0Lzz3Swi4E1jRh4U6Gefpwou0jah8Bq6n4mkqpuwiP/O2BoQd+wamCuGiE5ZaAEDpj
J9RlPeUXFnL2k1EmDi0Fx0/faKNrHEiWtdx3hyCwS7cU1+FszYolPf/8JfPqQSaqWGlFB2n/R7BC
JFRfyZtVBOs5FlMp0g3oIW4k3sYztuBo3dp4KhXYki64j8y3Nlxs+hh1FkDmZaOm6UaHPybqHoTN
Oo+ZoJ43lx4jMBVcU1vUqw7CQtU/3joZHJ4CEMNZz5PP/BPxA4LB2NRn/sXrYWkYPAMNi2Ji2g4B
+1K/6KAaoiWDznfeTV0q6rlO6XOZEZTiuShVAQyLevLwnTsUyxzuQgwTH8jgOOcvjIwRFqhitf3D
1B67B5RCz++PmG1pxIm6GPTJTCjwkf+J1JauoHejWZlDVVROW7HZOaQGim1WWXbXdz6e9TigMOjp
J8+q5YmdsoyrbvHveXF5oW3lZ/e+g5z0Y4d0A0hWqEUyYEzG5xZiYgVKPKR0PyDSytBiZqynxJZm
DD9UAqXZzLF/mBdZ3pojYumfWMEzSKL00g6dXmQbj6hRANakbcRNNuUunA9kbDU4qgml3T7NLkvz
d+ig40fMcFne7YpeyMukyzRDdrd1CLSmOpiWMf6Dmb9Cbeu6vGu7PBd12zFofSClBnGuP/ysf9Lr
HHtG0qS6JCWMeomPEWOOLj5X348vAnt9+ZnwN1pwyQFYavNYFYemzqW03kgQoL4TzuIoF2Wlbwk9
ds5PFYdykZTpwwsgzCgWDOvMN+JfaS1MnlZO7dFrwIfXroMvvfKjCNYs99W4tGQeFfFODEvMen6O
1UCmx2arYCcBg6gdOq+8y8ChACkCaZrwYMVNTrtvy0A7mK2u3Ha8g8c7T0x53q0VgqhsRI/6uhNL
iUfKHBU+rTNawFo5V4dmj8aPNeWkzBWrXAPBa/OIUzSVrfLnLJdPkHmeyrbuw4mQI1XRKwuQsqf8
3lOSzg7z14lv7YkrcpQbochgzV9DDfZSJMRubL6/1jlO1tElcV4sohBJ+e/Vw7fef89cD512NaT+
r8lFtfQx0vCelT+3/YZilGXQTD0Tj9YrAtNFKdKj+Q8hN50VIaLAiKyxEGAIdpxLa17p4hjIDf6a
N1KTo9pyEFVjVaGfrZrhXTHHbH6biuIj9ot8IFKYX8W78mgvRIHAJM7kPmM2jCPW6hskFq88u2IQ
8VfnfaU16BkoOC55ahZI8hHNBzh7qRhV03sBAJ0PStA68ZcGLwoyia00/sHAbHj4mgjTLEFaaHcH
CYVGiPpFCX1qCYe029+lbfIViTqiXSn8NFPNHzgjljcPk3YA41o9qkvjcBOkP8xRtGaFSDKDeBKG
JxbMJs7q3iPgEtVgWlfinF0NDfbjBdB1bDHlrFFhZeQbbyJfPPk4BU2hYI77nRRx/2GkaWTxPj4x
If6xIiFo2sy9Xgca+E9bM6DV7T94dUBAzgW0Ujf1VP3ox+0vh2OAP5lTRIw5hZld/wynLL7NJfka
18K974j5BUap6wPEQj0ovqzD+F7mS67nIyZaPEDFOMEVwoY/9ogKwVefNYN5aV+7aGQDorpTWQQg
Kpl1BWwx1zb9EBZsu0L7i8HDIGURjxOwhraXJC/gZ/+Kg4aqEZQ9UYISUYdBBKwyHC8z45OPbKVt
QQO0VJ0AlHrJr1eP03xOa6shbZUyHqeP7kRN9ysUyO6f01/e9iORrO+cuMvUXj1RKjI/FASsNx/I
EF5ltu6nmcbspl5jyGqeLH0d0JGiNgiZQyPblK3wrlefXqWavFXDn4ctfm5pw7rKdc23vdz28LYb
N1P+20zslRj4iKdUkv11oalFz8NdJV9QX1J7pixVgeRQXRt1rLrnd1x5CrlTsZdEo3JgEt+pHgys
zIwG+K7AVYCsDMTNftmcu9gc7LX+WW8nruxA6Ldpr4fWkwZcfGFwrZvzO97bwxniBm5Ga3KNkpgW
nltMSr+Cn9+vHc0u2KDJ5IbdfWMdtWzJVAKHhMXiaC7O2bosOyCQ5o+glULyxrHhdzes8RBQQI3T
cPTU0NMZLa6JXmw45P9NHjXVea9h/svBctWcFgB8TwOWT39QUQl0E33T8dXvuqZR8ob69KenAukF
hGvMIjiHYM8zSoUmWo0K5JEn15qYu8bdztyDkImWO84QWGwbwmDCky93dvCnkYqxaNaoI3oB6T85
icsdd5tLANlp8whOv102UoyW03Rzmw91byHByZ+i90jz+VIvDlNt8vfGNy+z6fCK6MOUtfRGjKhs
wwe4SiciTnjM0OJ7NNqKm80fcATBtp327U9jF2w5aii2GW4B52EaOvJfCxNEes6jtLla/s8A5ONN
7zB7kAz92Yc+WLLVjiv66N2EqrMyPF9pF++OM8SReRWvIqvmSJjIgRuW8BFtJRaYVLcAmt5Tmia1
3bqpgWRNAcOuRRx/gDUbAq/2DfwUBCGfaBooWqQk+SsNs24ePWuJjACjv4T9hM22wSaYMPTAHVbl
QnFyDtO2XllY3vfjgLV7fPZA/arXM04ujUIrWsJueDi1UtT4gkhITPjgn2EG1fyrF+aIZOiZxGr8
JvS9MslEVfq/c0Hb+/k4CA9dSMU8QyEVtTCfwT4gWJWZ4z4JQjnzVb59ivFbmaVzxb583ikzgGpA
rPy3EXOgMZECDAB201e6BkdaSEzxCnFZ1qJJQdni3Xb0oI/wbUXxNDYs53gAzqNwsu2gbMAoaRnZ
OJEs1ni2U9//ywS/6FdHV2i09sJNDr9FsSB1cZDk20kFnLdx6GjMv8FpvU8mSFMAfd/y5FFBjlhR
ktKM0bAHBY6fhQKOfdRaKO49NoWaGrHqDEFN2ZUtYH1jzuCes0zVdgYfZhouoaGu8kRaPLi1sWxR
mZN39OVTMF6hK5VwzLST2kLZ4+lrLZGCHQa6mDyM04MQ3zFh/iOWaMHBPtx9Xk/s4IAqNBvqmSmc
mQOPisS11ah82VHnjN0FzWGm2FFLySruf0ouU194FRKRny8QHX0mQ4W596wl3aMyXMSjBp1wU2B+
XOLd2cNMrvn34VvQrM3S8ojB5R9ERq/Gw9rkOI5GscuLqC/o+lHGH5mkXDHA8S5Ci+Bmy/DdYl7w
GV0H9ZGYiCTqNmdRaUr+kpe0hjM9d30zRJE7vdxwPHMhZSEJYPewmuj0wHLVt17i0xJ5lCZkQEnE
orHOo0CKEZuBYOG2YDm4dajaLvVqnTtpIlNr1PRk+p4Kjwjt3sB5dVqf5CG3jpLEh6oRLUsumGx7
DDmz+q3YQa/kpGizSr+uwHI9A1mEq50+oVr0tUxC2rzMBUPxKRAgcvK8geKsWjeFNS5o1sIdEdAD
f7O1ucYVHARxD23MUOYiTkonZ+wCK++xc5yYikJrv6VkI4XINZGl7hexhwTS2L6fTCKlLdFCZeRe
nIDjAE4c/n85+4FWFM3bjadIrwLQbDiXOY9q1KQUTMheOYkWnc2mvRVR+lox1vEiM8wssVwwFnEx
MEKqtIcfxHxQlB4tEt0Hz5QdCOadmgFtbGwn1HiR7AUiqqBIZMfn1NToO03ykCCtG/X6rK6l3sml
ekNE4z/eSk/iaG9wdas/3Em0W4aOvl7ri1aUOQhbdAOmvFOv97jvrOxNytq+hfaJnTwSrpwKzuRo
68AwVdn+A/CKjwrRYSKwijDCmp7Ahl9M8INYxi3kbJWJ6WV1TlEKkkjSPz4dXdEZmoLXKmrOo6TE
SKmRGKczc+Vi7ywxbMN1SxyZMdrG444XPo7QmUoPZjpwwdR3f2yBl8yCPj+xE2h2DdfMvH/wUxIT
Yv5rxslWqDBpO/y/lEKOEw5obqHbhTEBb/EI4IzHZIZ8TitNAr8j0Ic9G77DewbgOfTmLjueEGEO
pPrOdK3tuXweLirN4cPmwzhxyYPgJ/HOxr5WV7NbLmAYKjJCcbdRpQZE4eYun6ADQBBHQjv5muOK
WDdPIbSGtI1XvMYPD37RkFLRu6JNbh5sD/QzbfsIlhiCqupajMOKts4hdBJITYSIFmoyxCRq8xSe
w2geFapTx0R8qOiCNARttWpW6J5joiBFuM6hnLjaplUGx3kBamASCoD7a1Ca1Wk5d5JdfPmK/R6w
l5xL3/BSc/hP7ymeOW17P5fShHakAlXK8w91m5FwQfL7+dmkasjyg8VDTNVah8g4ux2pD0OsTpX2
9jRFw1BqumJsWy9cojcr8X/Z29xTL9WTNcDDDLlfyp8Yc+OOx2IEdXqT0D/5PH6jXAlZCRJI3ZT8
fi0q+SPKJVY0aY20kH7EblhPZ3BOT4Vnr3CtibyEXAq5FahnsVT4e88QSJLcMaDerY5kiSKSKkiU
RD1zMBoc/icSPHCreePTY87ek2uQ3rTHvAQZB2j4TgCSz8+mzZq3zIiOnHLAhbHXeaea3qoh6vxJ
cRMBTsEkahHNS/mQASt9G+qowB1DGEypEdFPW5IZUf3XBSpTBQYBJnPGJ7fNjMlR2oFQ2f1QxYn+
SAG7YKlYhYR7usgn/LAEKodsK9kpK9r6nzx51Uk6A+aaOHv0N+TueULTfctFz6PmYglX6eeWoSFG
GO3OG5LQhYLBeKJbvLlmYth7oBEOF4vGn1pl/N9kRENhZMGtWVfoqN6BOrzv4uu2w1uyx8UFLTVy
qKtgVz5wJ/Bb3kv4rcSdkgOmBWkdsUyfLno/zROTvk1/UOGXuIASvL/WuArCVfGF2oj1b5VigDCd
BZIJM6P8TCLFvBah40Qcpv+uX9zzzjTpe0fQP6OiGycUEdLs6KuNvqzCFywyjYEk3T/qUvwH7dtH
dtYrYh0m3aKWO6GqsHYgaWvdOJgCXsPMsMdcUF4Y+S5Im6oCRL28iEIRHSdlQU7bjXu/49Stzb9N
7zXkBR0hoL3LTNcmTol0sCasYTYGPzpgd/A9TSd0fq07uWOgyIxefgc5CXBHtbp9P+5JHiBh6Ce0
zLLgjfg7zUgkXPOZ5qcE9LX65qPRcEm6E5Kp0mIbrXQll93qXTk52GxQ/c9ULO5NUZr9voj2mLt6
whKI3wTw3cfzpoSC9DbTwgV0x1g3khRREidwCyhh2blkPc7xMQL59TTVKtXEGbGTVCbcTCfdQXXh
v7sSw3sc/7jvG9XgqmAG8y9Zr+JD+bUMiBLtQmUPIOeFOvFHBb2gfUFF/uhE0qOJB+r3FOOuyad4
FM7T7cNX24AInwQ1/1sXlamEl9J+86gkSKqrnFAiFZ7oLnjdkqQq2hzUW8wNgvm/YYUxoeSeq4bd
E01I3FPG5PsYqb4oMj2vBTdMux8X3lfge91nGokzGGjwEH4a9sYHzlpI16IYMyonOaLFi7AoOjo/
9/CYHyaFOTlrn4/xBr7YwitJUK3xgfvI43k+tthjc39HMWPR4YKzxqBQPKKR57chsvNCJBKzo2OD
d9Su6kO2CteCnEPSDo/T25D4IuZ3vHKLA4aXpuKX5eAICHaKfNlY9auL6ShhMZRm6vgHBVEsu00v
90apy/OgANz7FbJLltfvlmzC6gqSv/jm3hQgb90nm/4x3QsptU7+DewQs10zDYCjCqD1XbgLlRAI
TWEuqCpBqKRknu1/bgbEZVIOcuaAHBnTDqQunSSfYj5DAZ3s4Zfqbo9GvWB3afJT+0F427p0Ivvq
jjtFVPVxzZD25Q1UEuwaKllNRND7MUyKeyRsfjFtJBDMSCMEOGs6l65U4ckrPxKgxMkuchSW/sQ0
E747h+dXS81vr5UWOMR9kA5lNcqAOqW+0AnkdA377aOmatL7fw2u88gkba1iwHMgtcrWvyPhmewK
l+v97g/Ocqv1LDDbgrAHGW9X1qyMqC02KpxV0yUEvKqWv4G0EMr4r429LRrFEd325JgPznQzUaTa
srha8p7noJlLfENl/piSL8G0BP8a6W02Qv/MvVWTUgZjlZ5z9sXP3lIDm4cWMKoLeVVcl1z4ip8D
TTnEB0lGMltzUxT5NDkmk8vdAfw6CIqdaqhkoKjWV3KPmAfrG9piPixhgqphb/toaWMhXeSR1ybv
B6LnluBcqPUCgrvsuj8dta3+Nk56BsbzaA5fGaD5QixaJz6wfyX9RIJV00mkl89Rb9ss8uG6wdyE
o3D7LbM54z0qTQ9J7f0rocGfsKUy/TYzg25OfwWN+xekJZDzGFgPBI4WUu79otS6uoyWIUpT97xL
YnLjPvEYpXs+bn0dbT8aitMO7myUpEBFlD31xmYak9Dg/wb2pKDUBeCRM6pCSr86f5/LEtng6gtA
DFQ657c+dcgKJAZPKl6C6dEdthz45A0+Fg/dWvAChOAZTlcK8aIbvBQ576q3VFJ1HY0+MQGuJIOP
D7UOYmgkYppDSvdLehY98dzWa7LeEiBajznAtZrPJQE/6rF7s3PB3HXyeYnPw31zkeJFBqY0r18S
sU/DgO6jg2lxxlqFLD4yw6lpVFwtrXZ30xKZbqvriWJNjZmnpZ7TtcZBw4jvqKsKSW+vAzd552pq
yls1gMzeAoOdgnQrvPhJCOxnSWP6ZB/z4RdXvnV/YnkpPqgm8K48IvF5UZHWe6lshqhcEz5uJ4Tf
njUFa1/YEgm3GrWjjmmXc8Ct8SHBT6G/jQiDdRfPhLTXS9APPgUarMip0VcVuZij2d4P7Rc5s7bl
+vOYKW8QF3YkH0oQx5IjRpML1Cn3q04LVSDcVZq5sjuogwS68bPXj2zGMXIjx+3E3roXQFUC3l9G
0DRepAVwakI115Z0Lu2IXTKHK70VuLqApoO+ANyoSxuXIL/p63ayyxfBQ5ZwBk7q3dmlxvm0gw6Z
K9BekqycuJOfVdPevbaEvspsyhoPljVQq1sc0LbfRMxcaVNyAsqBxPkTD7N2N8PJ9br8YW6eDRLH
z6S6k5iOhaaffXvjVZQ1Gt8WsMyayGwqewgPyowqXh0Om3xSAIwsOJAfzWtHS1vNyJksDhvG7FV6
mtA47hcA9x9jxwN8FTo4+MiwjTxMc4EqA3f7cKTF1y2Ypa1yf5MCCnA+8zwsbeR4YQgAqyLV0o/3
CpRdDJOdO4XzgOE9mV6q/EBjia1QR1P610pyP8qPgpBHiQiJwwlIvcDTCyZuSfZljGU9U0C+Y3c8
4XKiPC1slis99jM1bGOxKKd/DnC8i/LTXNnuHaIZxI2eJrLgivTTla8p3U2dIT4tvbDmopkatPN5
uoNbEajix0PErDERltzZMC1uNpAQkSPDeAH+F3KR/45lr7xwov6F98v0LdaewvfakqKnF4qQfsEA
NjhTdWe6dIDWIHMm+Yv1d01MDDAazmXBTFwWe0bfoCwYay6B9PS1iTkAZUj117dk2H6wC9mk0krL
CdNSKAELHEXwGG8274KkcJge+ETwrGwy7Mb9Dtg9Vda6c8ixkIuqgPTmUC1JZy2LgXBV0/Tww2Oo
BB9NGASYBMLQSHowX4C8PbW32vVnV9W6xUeVRJ5pVOHacBgHZ7Xt4HQg5KMWWobLG25vc7hf+yAF
sMHXp2kLYmlaHnA+1LRirHdCtAwTBbi3DfvBA/Dj5ysRLPxlCIO/aAZr/y86VVYmyJelOkqWe2ED
TYvHtUxL6lcYISKR9CjIRgoGmf/BV5QB4OafwUJYYkGPHicX+awOnlmBhmJH3DJ6E2Z6UCbIEYEY
rvF3M7MAs+ININsOEEgI5xFGZCWHB/vkUe21qL5rXA6KNWPC9KycZnRQJZnraVb8u7XtA3R1SaWc
fTyD9Hs+LkFSlOIUe5UyiQpdRu+qdKkhT9YvdJSlSjTrMj26HpBssWx2blXE7FLk+V6aypIsByoQ
Oml2/CAdV6yQ4TVxb1qNgBfXzt6n2QZgOV3WTSeQjDILQo3zKyyDGW44SVmULrxbeU8qaAtE5fDA
kL3ghagOjE37qFiJobMs6IgX9UcUfdRLKagKY0IrB9wMBuvqr4tyzn7v9zPxoO1yO5WxHGDEbabR
oazg0Vmiz/mT2B5QQ1yDXJUwCcvRAoSgAulg/OapPJVDKnmvycbbW818Yyk+yr0mJn15ldfW/cy+
1uw1ndGXDWrtvKpjR8zFR8E/qGOcH9dcsC1HU1U/MoCPDqxL/2SfnWU87Nvr6oTIS2hOKQKT0MFN
0KBeWy8tQ1hfS6UWI4xNOcHmonmXcEZuCfuypnQnTQq87L3XeV+RJcP6NmHPSohRABwhs2PmZMXJ
27v8meXV/P0vmRp8R9wIBbshNPjpajul3OusfHspYCJrpHOGKa7dBAgHoWytJcRgUMhj2AYUxVxG
gCEp5rvZS3OXwaayP8feNsB81UYpVKuIpQ/uXLuK7rwyn7ZrzNEWEwuv5aC0xDa7at3weJ5lf0ai
TjB02/s2u1jmI0OI8J2yZhcXeoASrwGp9hscnPGBlWo+bJLIlIhQTBSuJ/0UpfujSYpMA9hRwv71
1cB1I/uHKywa4uFu3mq98nNiigSVlOFmkP0lCTUCUi00J94OvlxqUkcwqw8JIpnn2C0KfDhx7Oi/
s022hojCUKQSPnqrQHf2yih7McjWs3z4NuDJALEvHEaBgPBY2EsCYWN50XAIYHjMPHzZMjVgODiq
eapDyd7w5WZyXQAE8xyU6WdITHpImhW+vFO/YjtYQzRRODISScp2ygLzhLy19bwJzBaTqs/mBWCO
BW0MivvYJk85r9cAsUjaGjiypxA41YVNFgfyRXoWs+FEQbdiMjuNSim/xpUlgVJvTBGltgZfaw3G
7bsmfDWzjSuQ7kmStS3AK2V2Zki3apGpYJ6PvQn2nETVsJLDXIcYiid/vCb8IxYDMsogUvYKFFni
LxWjFFIE09Q3teTFGeVxsn9AwGF8JGZZq/sdjHtKZSyeqmhUk2Snhrhw8Ll7Zk+OPWkTHDtvFAO3
AwsRpO0sCHDMLrgNT3Sguaf6Mk2Eqmuy4Tfov6zeWi/ZRKCCPLXVI/HGDrWFdvoq8i8/Q3epoTqi
Oab6asLdLCwZylhLL8qPm66PORrUMHHnl5KFZzugccNhCZfoPdYdSS+eaZyCdZGbrraH6tr0Nllc
PYrBTX4eY0ZdFEor02dIPl05c9O06phFNcXGvh/gYeFwIWtW6fnuIHXbioqEsm/VMLY/1cBElwW7
XlAGXGGm/Ghb6yuSgHfNgQ0txBTSj1N33Tel3fywxFUEzXNIRWxlPwU9tABcZEc5D1V/vjfl1krJ
X1XveAVrO8ARBM/eGmL6B4hxD3hUBLrS4zBUTN9IaiS3oQeugn8ZYEM2XmxWSeArnATsKC/eS02o
F+Q+SCFgNQLEqRKUfEgqiwspPX2XyyMFHUT6FZI/vGvfJvICSdeIYtgRKUtixYUl4Tp6Jz+2asVQ
QbmimLWSseon9JlnICQc48cV/tdLIUeTn5U6zdWBp7/wqSoxkmObFH/VlVw+eZ6JThoc43gBGVLd
gmzK89vPy8mDTSsXJ7JXT7XJXZeAbxiS/evLfFcXqmGAlqY2kVuNsKmpY3d7hJtJapOvz6aZBiUz
MiE+8I13oV3pSyOsBB9kK6XHdTomvSt5jayNFtCjOzTAzatyyt3JKEy1+Q06/1dA5fVqyxq7Xj06
FcNSbtE0eZodATXDxJkBIXadnqwQ54SfpCfwuqC1RidqblrLFaT81FtlecjAEEqnh0VaFeiM3r41
hV0dPgyEVkDLv7wHWq3RjNQqGk53N5g+z39IYvGE+KSZ0XN6BOucFjefAhl+aM2VgIX84N+QNo5z
86I1MZzUyHK9F2ti/NTTVVjYEhRVXDrtW1Al0MwCnVZSMctqs2sd4eupQLC68j2pc3T70MVUq4yD
4FabD7vAM70K6COGdYd4vUxsB515QQwKZDsDuiG/rOXRIXETSnkKj206fhpuj42gA3V5Xcb1OEsG
R3scdlf47R2gg1mkQsu07lJU3NiO6RE4RKdjH/9qo8Hkku9cMHkEU2vKO/WrubKAjbxo2HCBtzG4
5sAlIy6PEjD6pHRvxxFHGtP11KECv6cYaLtyF9ns4GVDWeuWl4ugpPYjDleE0mS4lIeJXULvJkxh
hd4fn370I6yTtMTJZnF5qNk4fJK8u5FbHKucy2edUAOunHb4tyygOeVMJK1U+baDG/QGNV4EYE7z
bX05XkCUlTgwYMyMCf3ERLzAFKMARE3Sf44DElTCRET5ouVbyPHneu1Xxjwk4TqwMMv+gpJJ5c1E
C8Ps2xA+yWVsbPX7i6KjPPjvw6JuJ8HPKq95qb3PVu4/FI4EaoLYJHixIUGV7SkPCqL3b9EncKqy
3lH3gY5tAqCdQisRjstlU9eLVsqq+ioUZ9m5Nk+JUgATqH7cfolO44qptRALyAZIvzemvSvGV5AP
PHDQByquj38xLwOlhj/zSQMTVeRJcOFK5+/EuAqzjc+g1TG6g1fpKodvUE9i8lZaCCSYkwFb+5E6
cZUHM1GGPdFxVGpeOIZPnPiPIseL3w8ZVhvqVKTt42sx5bw7swpbjnorvmjO0AYk3qA33kGX+kbK
XcuTsYPrrC6nxC4CW1cloCGngmwmPtQhVqj9RgZuKopssDy10NSPr6IKpGcLW1Si75ShDUBzkI9c
DBKPzRO9xVm4hUZQhRxS2V03DwQ+nQiY2Gr/R6gYo1nYWVqNFkQC/YfgkVndTtQtYG4Vnk+Zr3+4
avi544ulT7NDlFJ0dns8ZQ6YvHTQGMahN+LWyh7JPBTHXgeBxDJfudY7N7P1oTnFrwZYZZu4dTtn
fdEHIN9RDMGpF67ac8jVctKOmEtJfDNSMnNT4HpdlqYzU/yksf/OHB9TyIt6hsG6aZFH/u11ofFe
GfV0DwPW7qLe5uBZVcN7NpH7x4lBNitD5Rsxgqxmhn8d4e3bnyHibSK+B14+eR2YqC0rICbIsvVK
iICibzfUFlArFyyGigQnQLm3sIPu6mXHrYz6Wm8m3nptqBk8Xuze2FqB3CYgaOvDwg2OGCbYoCVH
VL8rjeIZjlp1ZQ12mZQHaIag+OGEu+s/B1BKqiPqyGjIYpv5vU9XqLdi1Z+Cvc76FejhWGlIfPVs
IBkRQOHhwxLM+1MXjtkYHy9oQMLcYv+nOCPT9uHRXs9AJs6hVcWrvUV04vlFmxU2QZLrs40M38HV
5+yDzW+MZaGSMXiQ2moXvnhAZ48QXmWB8AvHRs+7DFsr1lLZqVFMBW0ocpHLYFSe/YNteGvkeZfy
14ngO22UbkoJe8ZwvdhG5QdLp0a/LEuj3x/DZBfcb2LXKbPFUHzYIRkb48Q/mi0WC49LCXF2mpDM
3vn6TbLzL/NvhoZq5xylLKyfF5FmJwjwthGAduTUpp4bbzEghWZ/PhpvoDMgbh2itNK4AY/xm7x/
2mP7mtfF5Hh1q4d/5EYLskApla3TJwrGIMH9ovnaMIbIxzQUC1KlSaB1hFmCnX6WDIKN9li5r8AF
IvydEgJ9wxoeW88pV2TMD1IwF05VQGbhe8LmFwJovNPrL+bAabPjxHWH9MDi8COJvhXOxojBaY96
R4rOostEX7olMOUrzZLYopJ4nhnux/GokFRrd8voUCusYH9N2FTFRfhuPWS/rxyhl/B+zDd7cA3z
KqTCLK9WLd7WItM0VyQ934nYErXqM1oc9bnk7zG2CBDip4zBeV+TEh+vrNbO+Kwry1DscoMMSkNZ
UUw3PFOv931/DCPLQcBSiGkpReSq1i/Re6JQrEuPKx/5fV7vhQguR8GA5oAB8H1lgIsZbU+X5eil
Afv01eBy43XVBfjZL5WVyN0WJtmq8SuY9fa2cXlMukZ4hASl6ta+6Em6AfxoB7gNjjiT99NNAOc/
elEV8orltJEzB/ey382rVe+Fzi6usI2LHhX1h54vCIBjTC7YXoisixT+ySpHCJ0DDHE2lDyLUuiQ
4bUawcwxWl9u26ztl92M0CEHh71uQhMNTOYnmmIZX09ZmQp8haMZ7+nu7loHEbsRKUl0RBlDXz6h
M4zcQ//wKQ0qvcEagwXXHQM+NpTjXc1S2ZP1UEykCVyoFNBF5iGzvNe2QCYri6aj988pClCa7b3t
vZsxWeE4VIvjm7njJiAkwDktRD7AsvGAeaMdLPXTmYoxeqzbaCi62L1xl3BxsV0L30dkiU19PdHY
aSmAmpNKjfjGB4LtdhaFrzZdovv78SkhlglzbbMTFO1rJ0wKeGd9+AwooeZwDBzdTNo1D55f2u8M
sxocLXUVw105TcysyTt2MS70iOp3QSvcVrRCB+JVFBInLUucJmVpbm97N7gNEDnBcC2/x4cjRhMl
2DqXbzQ4cVGKJPX3/sxBqhpi6soIF1g9lcNuRk50mE2D
`protect end_protected
| bsd-2-clause | d5e9e634c483c97fbf0861c376f7ddc9 | 0.939545 | 1.879591 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/ram32_inferred.vhd | 1 | 1,275 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief 32-bits RAM implementation based on registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity Ram32_inferred is
generic (
generic_abits : integer := 10
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of Ram32_inferred is
type ram_type is array ((2**generic_abits)-1 downto 0) of std_logic_vector (31 downto 0);
signal RAM : ram_type;
signal adr : std_logic_vector(generic_abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if(i_wr_ena='1') then
RAM(conv_integer(i_address)) <= i_data;
end if;
adr <= i_address;
end if;
end process;
o_data <= RAM(conv_integer(adr));
end;
| apache-2.0 | 6d24cbff31579941bc67387e13e80a85 | 0.555294 | 3.663793 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/sram8_inferred_init.vhd | 1 | 2,512 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
--! @details This module absolutely similar to the 'inferred' implementation
--! but it support initialization of the SRAM.
--! This feature is very useful during RTL simulation so that
--! current FW supports skipping of the copying FwImage state.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity sram8_inferred_init is
generic (
abits : integer := 12;
byte_idx : integer := 0;
init_file : string
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred_init of sram8_inferred_init is
constant SRAM_LENGTH : integer := 2**abits;
-- romimage only 256 KB, but SRAM is 512 KB so we initialize one
-- half of sram = 32768 * 8 = 256 KB
constant FILE_IMAGE_LINES_TOTAL : integer := 32768;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
impure function init_ram(file_name : in string) return ram_type is
file ram_file : text open read_mode is file_name;
variable ram_line : line;
variable temp_bv : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable temp_mem : ram_type;
begin
for i in 0 to (FILE_IMAGE_LINES_TOTAL-1) loop
readline(ram_file, ram_line);
hread(ram_line, temp_bv);
temp_mem(i) := temp_bv((byte_idx+1)*8-1 downto 8*byte_idx);
end loop;
return temp_mem;
end function;
--! @warning SIMULATION INITIALIZATION
signal ram : ram_type := init_ram(init_file);
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
| apache-2.0 | f79b1ed19c8a54a869a0959d3690f152 | 0.624602 | 3.656477 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/memory.vhd | 19 | 112,775 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
XZtM4bLmkglBewlWavfkobXOIMkrnElgJo+k4jE78ykb7oIZp/SGV6Fmfr/ogrusY/kHxxmgAde8
wVKEHfi+cw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Qj5OXRmuDbyb7tXOe/IIP9hVzpHdYEdnGFMGPum5TPAz9WJzfNr2HnR7yYGe719tx6wYAvdRlfH7
1KYaZqML4WollrpclochLq72pgPwbtC9iEEWlamVuKdvYSw0+IzNRBHdKqTykxKbBvXaQ7+UOUjw
UnhOWIyi6vA2XCWBMhs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
wc/9BtL9LkvfKqZJg7KOk8nPkSL5jxvAGfC0RV814LDUHBZcOVMBTQdouKf45+uYbzuqQuzhrFia
FyTrOU0b+Dpp/D8a4O6aOPezhZlqDF7SuDaIsbNJNkVeEPTzKN3+pib+HJ+07zD5sgOQyBLQtobI
4fQy7ggQ0o0bOrWPzlXO7kD45yraaLu2CaLqYlQzcDjqnvaWtdvg8Q6aRiloz0plB7OdNZ9a1tRM
Nl6v3ocdKRatScwi+YnBgJn5ewXMvGYuuBOXAkUmcc+AFWML9u7RnCLEmrft5oAR19N3inWP9hTR
9sdW8LGJ406SdzZiv/gZpUV5t/AFjTB8Nihgew==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RuHNUBMTP+a4VfkYIP3nKug+Q6Ygohn4DcPwrCybnrM/u1NLZNct3nJM51Ftp2uYn4LtBCAEFd4j
J1ykZQnUjNHc8Om8TkpAk8Xoe4lNd9c07VFQ/PdNEPsRZobFbRhtaTn5kYtwFZszGT2+NVjW60i2
zzHWmeNAYn4vMcnLRnc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
M1UhZ+OMYDjkT/STr81dVx9PmVVG5A+2IqAmn0405vupx6bbRZIy5mB6w+gLHolhJXN5SjXXAhWo
hTPhhYqRE6WXBSt+aNme9SGwhhYQCQHfdP7l6de6Oriyjp0GyOVTMXW7th225i4gd1/MFzrJY7uC
eTxBA69zF+OCz0UpsBa0iiqA6SmkbUtST66y3rCQ2iRlo3MqgxqTXadwVQPjyKh+YrZv8hSoGQfZ
859BObwRsVOuARh2h2mJuicqAywYo8mWCsE9MJAhCYkJvjGEbdjUCSpq6KjZZuBtdg5UMkBgdSnW
7odTSYiZWcCz00u/B4xtOP+tFTZhOrGrUTKipA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 81744)
`protect data_block
MGwC+IIIj5H4QY4UvMtnSpQECoHOY5f9TWadWoWYEDVsHm8dVH/hTaA0YPRY0k7Uglybzdg2EuRz
T606SKEfFYHqLxrTXFcIH+MwTDqrEHAEUN5w7RSyMaTaTYR9bVmbGri/k5TIRfqEJsgMXBSHWQHf
bx5/ebbAKl72v8sRGedMI1Q3pOMayPgZyi37TdhTNCiaUMOJH5lSBfJjDu0xmI3CSTJhufh3k7lm
Hb17FnttqodJ9Ms4p8p9pQSlvNaVsDjGI9j62lh+mkWyzdGnjN+ZLJk/0vPP0hZKr5/UNkTldLBN
NgP1/QVOSt+hrxH3iQY6f2gLRkzsACEsP0RkLU1ndh+aZ3hyDmikTkNCPf1DC6c86o0ArvMVAB64
ulS6Aa/2olPKgKjhYA7chu5rgM1xLggaT6LCC3+QHKMdrUrv38AiBneWmIBKS/bqVSoJA4WGIJ/J
K8B79ncUc3LFHbJRMijl58jSt2YkC/s9Cl5E4/W53/vkD5UWJqXxsPronxbM/LQOxv01zd/QuHkr
3hMBwCej2T7Qknpi7KQVX3yJIDk9gBDaRPEncSj+ThAXSzye7ieOLi21XZTOzwub88AXznItCgD3
dWxlFkpdjWYL1ZcKKm5vP5Uc+Hg34knFl/qTfB6zpyknZwPC6JA8OO93OdslDCYBYS0yTuNo8smL
thCvSSznXsvoR0883ev2iQnY4pdZxVPs8r8z5Tozr4GIO0FkqasXvfO9KeK6om+4No1s8aXrgtVy
LJ+BJq2ZkLtc+UVQxWpgOXSeZUNpwUPbu86ZFX38MT0In47nBinsLyh8MROXqXUYmcr1a3hKGPEu
OIJjFFtCwGAUec0UIQyvrcspofRio1CVjlXwc8iZ1VGrrCYxwMhrDf7xKlcYA3/wrr2yG1GADbge
fGLMjx3B/juIQ/cRDAbXzmVqyEYgffat6Qiek6GVGb9fo8MVf28GCi7iZbndbQby+efs3XZAsh9T
NgK457zFR3hRuVaXrFxfG++mUAASY/AcnuxfKpgTyKj9AOWdwfFDqE4b7TLlUVaUYOSmZivSlQCL
rtoK0wn6BF4xNr7zulI6DHpnH7NkxcFuPQWDpexz2XsiV1RaVdlNOGYxKNsuLSqUzZvIZHx76LG6
zxRs+97eQOrvOfb2cP8fFdlWxb1oc6iDPxFbgKhfl4w0ioRasBzZx19lIW5OeoM8pd9XraA0Uz9v
4/o81CbeHRxx9LlWNUzH6cNMMYDfG1g1iLrmznLtsnBjG0fhkWI6BxNHpc+HuYIiuKli1j/p3wJ+
hATXBoQxrRys6qMX64F7q9+D94kVbHjYGjc1tTVpHoEscBZEPtOs0Gqj+1x0IRuwGQU03hGOaC44
QrECQ0KWZiYNZMJcqO6AmoVXZpMp90AukkRBxRGO+s62ZMkddD52VZ+yC9hepeubw3k0+iJpTG3X
cZnLg+yp9rvlBVgqifxgfEyMWjjMqedzd878DVmpg4NJ0pKrhcWKmYhbN5rMH7Ct7aHSFZyHTwy1
VUE4R6c2Ky3KYkhFvkneCNghRd62L9x9758xy61qicK7ozsC90XV19lucxPYTfPFDUZzXFwupXsT
b1XOpxqKNvyIjjaaHSvaBzH0T/FC+mwHbCpTF5yNxiHzjS4r4tHNNxAbrZU02NvLQUhXzvLqF6uN
+8Af+z8Wdb5F4H7OyXzRGucn4y+kfaNh7jzUmHwEjolni+JLdpuDB3xF9FKRH7RXzyLQMzdCcKde
o55rPN+VaetsYL6RbTrg4zOMmWxddqs6lFooApX/wW+mNCybRjTqUlNvnmxDgJd2BwDFhLq/HBVe
AVXsWUmZLN5+vS1lk/uW/42wP59++8DsU4f4AUSlVpxErqSMX6qhXAtDPNGvi++Dnn9TZ6kzEvYu
/hYQklhCesUgDOp0KbPCuNVtk1RkVnF3KuF7meRHJxUIi0cebHNAyBFsbm7cXuRmaRo1EbIW0rSc
IPe2R/Pw/ZFYye67oKdguTcK62NKO4IF9xUbRgZcSCOdPGopY+D4L6RkWp5Nj4ZlUlRLgzdGBQpE
NBEKcL+nkilsWLT9sBaQMr6one4XIfDa5E8iAx4pw/8qwZyy/s3qtgE0qDK1WiLKnjdaJ4AeQi45
tWhwYtTHCVFNvCnmkTex7yh393HRuMbYEidFbyHZwlWXX0Uvrvj6BzII2FKwe75KVkl3X12wmJiI
V+xmtbDUzWow9WM+cNYMZRIGuPjcvpEh3EjlMKM6kqtruzutJkoYzyUXY5qKBGGy+LjuGc9yBbbD
qQu8Qurn9aHXY5bWm4t5aTNZpGuIqiksKV1qv8KJK5/FmIFNTB4BVjIuXN+0n1hBe8lPHQpbURL1
DhpuqBJlXz11QSVOX+XK4sqTU47bZbawvUYLE87kY0Xuguwg3OTYiofcaZz2wJv7u147TwFTaLp7
uXY8iE392cf4VQIDuTHuaAPUeSn1cHYhuq6qgSdi+WPOe/GqZcUL6xo6zX3IP2SjYvpz4C/lJR6A
pylAJh1fK7QmUGk9bAKD6mu3TPzM22S2F/vEJQFn4zaCblJE29IMJDaOOMtJEocD4sFvyLGlDLqJ
F698sbRgdnb3/bs4yRkPd3rVLW4uVdM+OkxayqKA0eBcTpqf3UlbDKiSMHWwDcmvYDWwb3SbrmuZ
FRLVt/DlUUtn2NwuQhM0b0B4mlBuf5IXIjU3Vs3uGuWIpNO5z1IhwhY4pAzoRhCZx+TSaynJwEES
mKeNPxK+r1yHCO+A8LbB1dUpO7Sc5WPpX1i87Gb961lGx8pOG1qlDAbZjQNLlgaPDSwnAqOZ7RuW
cHtSBz5ikn9r9x6OYIy0Io4OFsNbEclv4YLivL9wJf4uUtKRbEOImgj+OXea3/dTZGWq3UQF6TQQ
gG5of9T8GdxpQFd5YvCwuv/2jHP6/f2txkUuE0e0aK7vrHJIDvVKBNsZeKshUHBSwc5t/NJOe8bi
YuSZUY1viHgtCSX9b5GFh9EfimF+OSM488v7svc6Zuv0NJdTEys5YNx2JSrjRqbNZOs5e8NAwq7y
puIcojuErbb8YDCnGC0AnKYLVd/+2hESZxEF8Hu8QlDv99hRHqjXzfxZBgRmhVKBedjJneCg6Dx4
CdEEBZJLMYzVWj/Jdn/l5zwVCWKLHUVG0KnzYGEn9d1DQ9TWAcY0bWFpHrz6Dq0HRyILubyLXyba
v6yRjMEfHYcXHBwlORDOdav5MnA7lJMsWCscyxJ4a4lGUl8J2qlv3TkrSPwpgxmYYY46m/+5N/8B
HEGMAPaqEv1+EmmhPkPaYkA5Bf9T4crngXPYEL6BixXApn8z9Rs1ssRsdYBhGTc4EhN7mHhJpk1f
n0/r3MGRge51nP/4/u0Tv1rOLWkUdyuaWRhZu6Vu8enL5WQ/TWV/K5nrrnXwDyWL51jqqoB/s0nw
j4di9bUMl6dAasksh0UcFx8rMxcYKfOM0f4UicPD51craGGUJdMW6OfdCu1G3b6V/6+YG7DmgIXa
mWJ2RT4khGFFR0mmZgfl6BlYsjoF59oGJtjMKk2KCFvP8co784c5HLXbAmEhq+D4Ye6Ka4RGeLYg
4Yhf3vCdSR7blfejfd7+CzWmJbmmIZ2zxkgH5QlaDgm9XdkvGvpMX7PuMU9zrQw1g5RUd3kw60HL
AGeRGsS4uGHy9jvtnTAnDpu7K/+Fp5qTODy3lDfiQ6va29GY6CaCKhnXC6YsySFNjBaNI4eSJrjc
6Za1Kj2YI0ClJzmjfIMBiMTKlFhklKQzmxIKbATbM9YydEpiHcWZ6FHNW/IlYDHgQHuYbwZNN7l+
p8lQWoZBpYIShbjWLQvoVSYmzPK9QF1UMzfn+okEfS/S6rStNu5F4ms6H13EHL2hr5Svm0MvPpc+
pOnybovDJPrcT3qmjsIw4X2rk9cfao6oorjT6BGclgujw5ebjVYHnA7gTW3U4ef7zAgbI8t/KpRJ
M6LaZABDkgrmbxe6RukMVNAtKgo7C0jDZvGC1JrGIqmGFndUvtrW/MuGe3xPqPnFf3j4yRxIDAP6
Qi/GP5MdyazuXdXZtNW8mGYBP+IKXSdwKx1P3disEQXnqYVvZSWk3o9HlyPSyfWk17sR+1xcQcjW
+O/ehQTigI65TDPqMocAfxnI2HIzlG+pQKbVAws1WOkvwDbaIcVLMHF/mK+E5fzOs/Ej0bEgc+0d
JkaTVFUk1WvgPNaADnoh2edXUjjfGTE9mZ85gEjZvlrx/xQhCg57VQdqsfNYmSLjCFYClZqjGie0
ZB6uyGWhFc+qVG3HMeLQK6PT9LIUbhgorNh56FZOgIBBxxmGrBXBWJlAOtc0a9EdznklYytGdImx
d+DeiM4CKUeUp0aP+10m+XHbCCY1NP6eUdaCF7/LyE3+Xd5ksuTUpPhhzeExFbxkCKgnGoqQCpFs
SKROwV2v8wkFp65w3IZRmG/fJvVAQeyltlvLVgCOABxnsb7tbyRayOxYUHJmZt+lffEFx/sm6FoV
O8QG4v3ZDK4KEuSk3zf3yZPnoNfqXyD9LyGBpaveFu7icKbvEBl5dLIxKhZG2zFv9fVQeMr2XY3I
8fqPQKKBLcquzpuVVifwGCW0Ld8qMp1m/ilCugh11P/I0vomO2H/02PXmYkoOD5/3tRelB5ySxtV
VxCLg1RvKKeXTDdMBbC6S958dcYLZv5fAl5RMf0ITN0r7YZpqI5zjkEqwgz5XsiSuZ6BuIbRHs5i
54xN459LoPEGarUCBFdzkmjBafkQcvTB43MvfoI+AYoN09El64zpyNrD6MCRM1cfzd3oJKeLdCJO
FBuwu0CgXvdQDnRY8Rrm2H7PL91FFEDIcnqcyOpEhdx1NjN1lwy+oPKasvwa9/zhKRroUZ71ck9S
A/nO1HdtAd9nk12qwJnaf8Th2R7/eAb5IeQ3tMLCxgA4adgbOfhwSi0HV3VV8z/98tyYeOR8karu
JtlH786mYaVuSCWNOHEz0gJcgADHLTyZthFHMryRm4LmY4MkfqQus+Ed5HEQOe23UfIIUL1slIXV
JyATi/JERTBxCa0yoaY97tMl08e8cdYJb2B3o6TuCWBMpzQvCG1EZfq+2yO/ZzzwRb6l0K263mlt
qCFh9MZz+MHeAKUr5DRItQYNpxBJopa/tWcLXhi7oWrdn/p38cTKoAyl/Qn1VWKTU19SITaDkHJp
w6WjW2nX1QZ41x1BQPtRrhx+u3Z10vauBEE1luNmpd1sIDn/CN+2HgG5VRJPpDXRfS6p38+Z+s24
ApgRbzuGK/acYL89W4C9RUdMFMND2/IkFsziCS7uGPcru79HYDo7uCxyigzGQ1c/VxZv1qTDBSa1
ZOKP1xWm9i1E/azwJ+d3IGPSsiRf2n+/gs9enSXdTQB5cfbAwYNb8npji9N5i/0w6bHlqOIsZ/hV
ASzuIVPk7vYmfox2xvqMhFk1EeGEAweOc3MFRMFZ7Y83jf519U3/VDhwg1zMnkksjmSkNqnF9j/6
Xai4gVFKXt1L3206WuN7VkyY8bwYDlUmAqNA4kgNtMFlB/xotumSuq/cCb8k01xR6RMWn53byqAb
dYS+hKE7xXBIDKEX3ytFTU/tcMnLTCORTp7PVhjgAau8AqAdOQCoDNj0gyT+WpN5/a5uMSdTkHlK
UthpH4pWcZjrpW2fN5d+XBUKS3SoY8gmn2AjDcaFfpTac5cublvu4hNJjJWZGV8iMxyFGmmq5b4K
UhYuI79t46LvjHM7upvBUjlBgMV7kE0iv+4PAcqAkWo6K4d4QIr0BuspbCTejJTRO9xaZ6bOZjSz
vtMKGrLDf4vP8GafQLTAeYsQmZa1W+U1CYA1dnlgtu2U6gHn3S+RwU+fs1Iz48ELKZZdAvjO1QQ0
7YuCJWuD7aT1/G/tWoL/YwbeVCO9mTrqOERsrjINPEjGN4f7fk4ftWmahFkLlxCQ+6ADcce2uUr+
gW9vPryzgdi3JX3SGZnydkwryCq8BNIbFm0M0ZJ3PgXxewZFy9UIYKP74GjO7K/RfPBoBopl9ky/
Awqekgr970ww3mf8ezlqSjGUSz4g2rmb5k2VSdCT7stL/oQ+8MVD0oySR++wCZ+RMyr+MbEfqBnk
gOTwQ9CSjyReA6bw9n+llmwdVXPfuCgSHP+aHx+i3UHk0LDYVqKhRVD/3G10rflfEqEkOm3NvjC7
2odQ3lmlBEFICETO7iqUaGp9gJ3hbKaiQu+vADe4aN4LP9sMguHwXbrT0ewM4C5bq7ioFkGrWfmf
w16TBEQIt0aIxrsDkOus/R1mctmuAvdvhugBcyAcrKsVpscj1ftl5AZoXDkc9KyDwJqPlGKdENDQ
uyWzFNqgLT302e8WHbv9cYAqy0irGupxsAlZdygWHvA4Rg82bmyvXfe0wUfpLzIKa77awIB8aTFs
N+abnP5qTMKMJlWetjhL9f4ZViV0ImK4ZrvY2Lp7VF8sIIVd6ogGIu26KD7F9pOVpD4YIt8gnjMo
JdTyxWK8efUBi/uLJGPYr7ALE1OTb0T3eL5pQDkBEyUR5kNaO5MGWw3k/LrBKXQ5/kMprMQM2ye+
5chTFPnTQRF88oIiFlrGZZ2ijNZKR3GbO52Raqwm2lpAY8TX8myCv7eqkIdpUPiGKoIsHX3PFdYU
zWs9LRPts6wU5+rvZiSMOY3+ISDHjLZ8LLJ+dFpULeumZG8+lVqhUxe3/Sg4Q2yUY4qqMK8gVcnj
pPACseYRZSu6UO7Bt/366zDrOP8ieD0Is9foUcTRe2iZ2ByYlFsd21QM+2YJhg5n+VdZusAq96qh
WSQs1gUmnRKoetSuO3+Q0035utBhhXyTnUXoaFepIFQn2sobeu5zSzepgNteJiuxSLQrUXa64bGg
CH24DAG/KrEO5LFSmYS0H8lm00MjDdIt5Z7+fqmry5+T3X+dcRNoNPvL1IzQKIRLRJsy2vR6uir5
+hFWRFs1FGZhaCrNdxEB4wlkz4oC2571CwZTC1ovWQgH3vqfGkEHiyVHvv6T5853sjWAY78RACAr
jAzRn+hqS1TxDCMDOJuRD1BCMAH7zsqDPcIntIJz33cRORayz6VwGQkDTcN8kBxcfyl62taNKRC/
W5QuMddgeO9n8+Z8/aFw3RmiCDLp9M9BhzbL/wE7eH7ZeAg+6pjaple9nTikDQIHVkip7SMPTgv4
eFqs2D7i3yvU8uYoXDLOhmp0kH4HhiZjyyvvn58u2Xn2uuzh9FPsYmPshl5FVoZvOuymlzMAv3Dg
2YdOqIabGxYQc0xiFW141bxwzCNm5nKlP1V6oqc34p3GCHhrVKRpkstbGvP8cfjs6CvRJz6LL9lb
gDT3XEQaycs5HVfHuJQxOgGuKk6w/Q3ebaagefGj93E9sLrRVeGRRmiyWZXL089Alo5ZMER4u5d5
2wvkbpYVfqf8p35HhfQdno4qCdyA8vpe92lh641z4l6nXWKZmAl4B0nnu4hNsqczG8u8arONddCG
x09X8H1qZiqE0b/gngZFsvhGFotcJtbErEfIRRemB+yLajB2gU06STFtoS3XF1YwvMJdTCF2a7qO
oqG/3hNa/YIw0dcCMotbcuY7jMIjeXi9+6alMFseSjmeftlgV7nBJ+HCYfcLvzACMjjR7isO6J2o
WOW+6aN+azEyqnZSFUBoBVYxpvUR+b7lmifXEQNUJUpqPfGZsMsgrA4G6jWPVl6+3xF7NbZ3nCgw
teRzXHvE5t1cbQRKcWlbQSGjaLRXGmKWC9S1dHYGXbUo+qZJpEd4efZE2dbAea6GitkkrSKGqKIJ
FX8UzcnSYvdmC83w3/qRHaE/DpTY8flCQ+su60aRMs0P6dVSL52VWWB3rvPC5GiyIfK3fFmdTbP6
5DNKtGyN0ZW6q56ZXkiCY90L6vA6Ze5WIuC9Ii+bMbl1ZMPJ/4ApHRCT1gFa0E/Gi+IbB6LbVP5m
wDIIiIQEfAVOpx3cB9HvvccWCBghLm0KrnOxgriSAtVdctvUL+IXP9Q5lDVHrXQ/Z4+ejp19pbko
ioW0up0qN1C+Sx989+Rnf3XaRFUQfyWgUmpnZejRVut2MWZ/cca5Zvi2vOsQp06RW0jG+5UNFg/q
389G4UORgDnAJRGQeB64g6h00cy9Byr5x+kE4PehEeQFtnT8a1DsVLPCYfavBOyGM5AXCbmL4EGI
CMHhp+yKVuGqPvfbDFL215/fYVp+mBMYiJ9h4h632Okg2lYLChkUeXBMSAE6/QQrGpqf2aPXix2Q
IiOreHtj6Pq4mJxkgl22eS75fNzx5ATZ6WX1dmOLJFa5iYcGlxzpQ0nm2Rsz8QUbq1qFwBgeiX1c
QenDjqpKqmnjhOdI5WdPK78YtNS0OfO1/RbZDSV7LHAZUoBqPFHyjv2QT9w/EA0CSQrD0xc9huPb
+4cqqwLxw7ftBZePF87h8yl3PtA4P14ahg+NdCi6yL/vTB0eiELDy3/hUew5jOvWFTnl08tdvGGb
4tzlUJ02eaeM1BVWmaFxA/Tu1NvURejYr+GUwjL0bRX+YlnDS72U2zwE0RUDZHwhLtc1hwpA9beZ
c0k2G8sHV03WxPh9QbKMKr6Sgb3x04Ia+HG84TQToLL3yWUWlBYDEfVQXs7kchMSIDA4cXOcGoGP
SnSFV+9URkmMxAllC5sakk/y07H7IHsQsDOfiIhjdGBRcIAy8rGw/rSS6auphePAljibG3fyorhh
MhSnpvtfyfRORpgGzdiwUtbs0aPegJWpeieuDnMCMTNC8S4jHWoAXdXY7Z0NfmaQZ6Av4otYVrQ8
w7ewdBsLqPgADFSZB5nJv6YzCdf2p+wvdRYvMoW4zlojcCDJETIKKEEUyt34iGUM6TR0mU0v9fSW
lyYCsA7/DPZk2MN2NhZYtpqOCzboSUDCVxMAuqyDvndGfyA0SNs4efyRJF61VAlJ2t+0mghY4ln0
CM55Vjd2XxSK0di75IZ4zSmcps571oN73Xsdt+BbkXrvef7BOMriWlf+QB+YbnNc0BjFvOaGYXUa
il6f47dCDaFeTNLjAqNQqDUt6KFf/x4JC7DM/VW/D+tyxyXaUOYaC5yZaNvrPqxhbCQVzHN6zLKP
IsGyFivuSgU/mW4ijzCgH2cwyyUYXhHM+em5VvwS+P+8H6NWjCQ4sUk77DBm3Euqv4lRdYcHKn2T
0nJW/P6vi9CtRAC/0oROTWzyiZ79vaYAEmUpkxrK5vVZ27XgAVgvfVqjElT6rA5QdyVGZbT1+YQS
4IIW7tlbW3S73g+U8yJ9d/C9GGmrNdGXUoJSwyrkLLFUtNQSpd08ydSHOAYS7rlyVKyQTiylok34
qppFsGnGfNJbkP3bVAuNHhx/Aac6137RfObgoeGn04s5s5oVw/yrYMUt/8iir7sTdqA3R0XtCx9M
AW0B7g458QUeD5Q9B0EtvlLPfKhMq9LOoxnya02ASCvcFwUJjEfRWvijDGn/tWYQpmtfhEm+5dBf
sjgSZ+FjE4xFXTMF1o31BhgfItLa+Txvi/8Ir6KHH6OrqK5zGedSH29phL+mkP98z3oXexbOew4w
mTBCcXjaR7pqwqtbfuXZIcgpGXGES1K6eT9yq1ZePUeJPEoCJF36RJGAAj7DRVac229awMlT67SU
gNKCOYr1XovQxk9TkSesNe5VjFGytFp7zUZLaVhnhIrDi5Seii6go89m8l3C77Vi98iMlxs0RPrn
rYNV7cwi6JoKNJVAPFHPx2486h2IgFpHESax1eXCZp+ksN3Dqad3PBzboJzCAN4bXK6WKKfSY3Xp
lsX39E3hqi1u+zykpbs1dtL/bGEEzt2zcmLzISbsotVuih2D+3EV3eCoKyDExpt7vPnEc6uPcK7i
ljLWoKKQm2M9qSNG2C4aU2w1Uqq8HEhLwyXwZdiq03OTZejfpMIGpupqyWehq30C/XhCSLXSFYeE
10tJSaCDSaqAoALcX4D0GYVMz+YhGgcV5UuKbruX/f2pXT7H/h6Im/rKZytVfvI0Bd7Y5CxBdxIj
jVygcY1ePoeshR7yrEO8e5wB2NlbJneVklrjWDyN2FfMTn+MHaOvffCiIbZN6CY7oRkIPEHkvUeD
ofhXhdnskjG7XSuvLO5an51UEwrEbsBbbP7858+v9exqe6JPDtCIY22MhoiqapKSla2aLDRzCbrp
Uy+QfyewOQf8PkPl8GPXE25QsnEQ/KmOgI11WrMfhC9GdfzNaDor6P+++08UtE0v8k8AKXvkTY42
p+SZuzGtTLD4ZN/pGcHnEUkFpmnJTinVLdFoSZz+yjdk/Mqpv4ztdmfuZdhhIFRnHqqfCR7/b2qT
XJVmt4Yv/BVT2d5ycNMyqcauWAZFsVxpbsPVwV4BmZL/f4bcgkg92Ec0sgzMyg43Fn9kP32W20OE
atFUVvEDVpao9YzV5E2vSIMAD5cwgM7tOGwC3fTNHB41gWT2ahSxTqsChq5KL7iFyLpoghUfVYGN
N34EHaNTcfDYFkdJst7vXeUaPa3CgbDMBNUDs1C2kKvz2OxKxv7luxRgzPs9dipQ2HVczylQ04Fd
8DrBpmWA1DayzpX5WyL6afTvYnWCRUSdIEWhXWX/qpYalGl0oRv6/O2ZjT5vGYXpVwRfVJSoHEGo
Go5PIllY1Xe9A4x2zdqfTnHEzfCukaMYpQPTz2LY7+PoeGLIwNH4MKWovCkAh1v5IKJhUec5ifao
ESSYECa1qWtnv7ezT+Ab7TMOvBagci94Y6XPnohFf8ecntgYWlW4nD7EKyk/uioKQUG8i530QYyO
bVHi2CKIF2m8QaIPkuBtGOrNWqnfBMoQj2IwWdffof7PW3u8+IfxKPucxAfSkK1iqlTXnlppLdWK
mhdRzLIevNDUYHj8VYiNLKtJoedCz4eYyk6Lu9LUkFqjQsoyWXJFpWmlTfQnxdQR9bbHgJmQIvlC
5ta4DYSY954EAsmLjmOFT6Wr4TeutJ56qeHXBdNdxfldzzMWKenkTGuyB7iwJ1i3aioJba/ak49e
cCIC47qkmR9ok49uL8OYIwntj/DuMWRImbpfn5DC5ItFz+kNd0rbp0LG/BEkGdCwZgJYd7rPJbsn
2uTrx8uK0WJh7pIgwivA/hi9262e3fjzpcf4T/rj+kvl7UcCKyonLEk12YDiB4ABtWnc5quUEATY
6zn2uXCOsjBPDtDSDiqbJQTCrhcSE2EQ5+4TtbJZr4+9PQdxuLpqpdHUw6RCbdjbzShyOulJjusz
LsPH/OELS9/gMO5bNJODfhmKCDxzS90z0/Wa98CKf8j489O3WVJ+Yl82VCVlUqu1OTWMFDaRRY1Z
vV09wFyjzyLhl1k/uxmpZLVu17svXqp55L7Hma0eSr/7ILJvbHNrwzCPwmW6QXcVa3OfZ3Po6q/D
z5Li/raKNROYKn95sHJipI7FN1hsV9yf9Jt7IrFxWJ+/tBTa2XdyMyaNsrZBhJ0btz5ruYixrqB9
PjXiOAZzdu+bNlcTqF1sElc57DPqXMpGXMJW47FD41wvAn/iUxxpAMjsk5KAMfoVemuEmwZM1gct
1mkVz0TmSebfD4hNFgiTOWk2avK64iVor/hvEy+4quuMm2KSK2IwWBoXGuz9bbS992+c1Uwqol4W
4olqkOVcxxC9Q0EcAe4CWwjrnoeJQBaZvDWwYfLbVqDEmRGjx/l1DtQ1EFVEvl+AK3DL9XRiBsnN
OxTo6UnetBoQNX5IoGiIThvIZWI6U3BH9iy3rfFz3Wq1AX080tNgzPhdkN2CZAG6CkRX0cbmeoFg
syZR7whRLXYbOUkLQRwh4/g98a+I6tGy0GnlWep1rv2sVYMUCJ+szfSg7iBr1janJjYI0XDKW5l7
Qgb+1yZUMZdkg8ANZICKSgEYkXSlUWssZMypNp/bSt1GIs6mZ+Mzorn78ll7PI0CB4Z77jPw6VB3
iHTmqMHh63NgeuxiM2ZW10tHV48RojisIzDgfKLyGWakhaYj9yDCpIj/TRrqPSwmm8PrYtORMb67
FMed/CcX/ZRJlUMvOm24C0hUx4qpwqp+1IJJgzq8p2ZsUd9nrxsnE6pgSPGtHRzDK+p1goEXwhje
51ayMBMY4EuHGNS9+NbtKVwjTPAUGe1rw6YwxGrBwT9AkW7eG/5fZXDtiezdHOPVvgtQ3YiODGsx
ESRlc7y3kZazW//sRPv4yy2dRWzN9pCj95A7MutIXhjBN04i8dizLYpoA5+GB57iXnfvxF8ev3EO
iDb/X1ODnFj8kgZBkg3jt9EOAu1vO8WVvGwTZRrc+sXXTVpdaVh4Hse6lvRefxDpEHkN0qY3tMmt
pXX+Rqkr03AJf/RQ4PhoGOWdXxLTUoiz//8FQWkZOvxzoGKt8ptpT8fPTYGI+4AITm2bgCJhC2oa
0HinZMEaewTc5mCCo1MMjDIgHImvV/G021UD9Ma6c7Cdh13kypRSeZTUxa3w1RrRLkMzlr6eqE35
jpbC+6CVPTXiDTWpbOYOiuXNwMM+p7yRV3P/AbAZciAmfURrvembc/0EQYUqG+PAgtn6h3twzWgL
0TZszoExehigzPapECdi/TtnBeOl+UHon8zs60XJJsZxpOup1dPqfROnnJsMrjR7MZuNiPiOQBoc
M3MAk3C+EtrtrAFPvBrFpImJ8+vbfIukOgPYYcm24onVBPR1WMJ9V5YJs0IBIvUc+NsZUWCDYWl6
3Y2zmEn6au6vybe9Ia31MnsjM39pKZxMnZvlsBlQAnzg7L8jL9TQIzFE92r757ijplzyaav6ev9c
4AzEyi4Krnlk5daRfJmzE5vIBLC5P5j3QTLitnqmBgHGqwUjyqkEcHu87xE/1DiKk0HMG9oOa8Q8
1VMqOCGR2er7b1baQJrNPq2RJ8oBI8b+0WB8uOa/wcRWOHKMpZkYXEQ6Vdxs+uUloMzDCtGxJblO
gLqGiYiO16Qm1qZrkO1etALJI2hg1pDw9nPNPyt0y4IhTksZiJX7ZudU1n98NxKZVpaqCOKVUsbt
3T3Pa4QzyZbWrEfUJF/S/nYe9t5I62paXUzVBSW6/DVM97zJHtaZSy7wZc0aiUZL9BZBcKLI/Vo/
PKbtsEkIi2AEjSLP3AJE+BZVoSVU3rCWIsioOP+TH9z5CzdWsHXH/kR8dBMofyXfzgDWlnIcVHyl
1mZLTjSDGUCub+mhW109KridaCzNdJBSS0oKN0TJrQgWCUa6igv6w22T2DEQOJzJ9WrlPbUvKcim
45m8Z79YRhmTNjGCSWAkl6vVqATS/a6o34+/5gv47neYxkpDOV06AoHR6Q/CHLasoaJX/PuqKSkR
Pm1XcrIrDY4JYtwgBUroExYtXeryI1pfQPQKtKgbxzdqd9PH58O0drmuDTWuJZauZSSkV1ixJwgg
Vg6Uivuv/HzDpHFFThZeqENKC9Z6LeKosrpLaeZ/Gq28TNmExGezWEQ9vqJ+CMA9520kIWdyAQue
jO0S239z76mU3y62QywNiYZkxdvDdFnci8FQwHZpjsPVW+/XHDTVvHCeFMzuRyiaPL4kNigU8aCp
pVTQyuSCDkr4dculFLEFhxAdDSzJMKhUXiiqNPP20/zf9wVRENGw0jS9IYSWoWHKK9S1czW1Jaln
9evBhnkn1c84wSETRy1kP3MEh8RRH1r9GI9XnHFNBFDH2kFOPgEX+Riz/vr/Ieo9UEu3AdzyL4rG
tg84C5Uq+fIbrMfH6yXyP9gQrKOHjjJYk05SCGHKpVZihi1c+yYfyBzWCQwx6V9K4q18OL1PQQAm
vofvo9obgREX03NN1zoKpivyj77k6AG7BLY1FmD7MZb8NN+olDmKpRBeji+u2PfiVvxX/GISpMWi
2pKvGmqVjpGhIC2B6QLISi1mtnpsGoTKzjy6An7MELGPusi1SIXmcoG0DKy3ZHmAXNkqXrWEFqTI
EuUGd4wm+6rBFYSelIjXiys7oCcwTuBLG4n8yxnYmqQ5/RIfSYVZ5NgqOpUZ8IpWQMPorJTlDyNy
PNbi3Z9z1AeCVbGOQeMsidYKM8sDF39MKpGQ14VPWffMwzCT18qL4+JVIIl16fEmutDxj3qt+vT5
ondxmI4uKGdaFyn+JDRGVsFV7dLUakv+952Dw0QqpYeh8ECMpJcemFMw9mn4y7TyGLtP66SDEtxX
oTCzuXmskRY7WEaFKns7ChH27fvCx2v1CJUMFGarIZvcOOuNWf92y/pqx5WKx+irTbbukDBm8Szy
z6c+EQmp8bBS4Tu+K+WTUsfbho55rW09PSEwBnk6ks+RuK/MJ8BL/FflrNeD1ngJTs9Z81mNj2GR
kJq+/eqKu3XZ7e9V+pHGfofgeKbCqBUexzubIDm2j+nZ4HDEEPDJo80Bci5ERaVjUw/wZC0j7Kc0
d8V4JgHBw4lQMnjJ71JxqRjhUes2E4/6NmKqoHvZAQ7JjPVTgqHGaEuO5c4jZtSBxhneBPBgXyaV
5kG7sr/LGXf3Vk0U9kJRzMGai7svjiB+ZRreXQFkiMMnFjyhddkfgIGt41cPTggtV0ul7qXtdfWc
g5pn1+7GnHq8DQLtr+/cat0Kq9JKlMaa5mv6nESdzpr6gNsd+eCl1tTDzvq1TuxVUz5cDdDsr5EG
ejc/N6Mx9xlDap3RE53wwT6rpttbByaRqij+yPzLi+aRXMMH00+CSswNzYyr7j0z5hNQx3l0bpvt
Yxg5CB3mmiQcLi82BIIC9P16AislwTMydXpjBV28t0GjG5rhop0nH5Byymp+Fgcj7dlCHMdwX1gF
zFp/liwmDDu8zDP7PLSDLFQL2Yjd6YM/stnr91ss/dWF58N6/WyyJA32zo5jzxtb3bOSN6yPExj5
jb7nhkkQX4EilUMAZQhvfmer7dHdXW8W375iIP9Gxo/8RZVxZNXXpU9E4/BgNZNafOgbvJg9Q67W
nOausKvqBddQJBVzDx3SWc4Mw4MlXTZjlAM6Woj8IeCU0SdZnmjRZ3aN6B3CqZ73UbbCCeKVPWVJ
MRx735DTktRN5IxewBTCc/DEqjjXnrqcvsLsZgJMxtGOjhfhfuuh0YG/4mGlh0wDFwhwpNDf67RY
kvnANLmtaLicvVvGZHUp2Rawe01IV5WxsDAsiHOzSpgYYQG2iS8cyGnz6P1+OQAyMVSlVeco6DVd
MqF5XX958ttYHJgDSdp54zyOHQf/1FUxtvzq9cwFJyUQ8HCmfFeKs2MiOMqjPyHku9ihXtRGgFm3
h5a+3iRlmYivR5ucjtubwxq+UWNsnpFqduLzl48ln12EE8ywkKAUp4n1WhPghAA0fHy5E21CRv1j
vYdWtdpuNRD5aLcBDKhFjSOZGcQkzc/lBeIsDXtGVvUm/TS73WI87MqjnTkuVmp9opNFATamnhZC
J5Y9v+sht9P/goJzPyMb6s/OjHGS5aXNHe3MjsjaZvzWuMkMpdGrlkv1xkr5KAci848OaKTwF72L
2s/9fSL5BLEOxe5QlYw7etE79JxzHcm2bIsAcIleZBPjEQJKLoCgeXqNrP/sYC4L1ydk57MUHUpn
Xw6O3GA2RAA4rsoAXWaxaqXRcauyoc8E8i9oCibWidSySundfuAooGaKc/obQjwhSvzJOXgPXEKg
8J44tPqkLgvaa0kszjPpnxvmPMtTz+AETw4KW0ayahgodhqhdW0xjAUJCU5OUTk7IQtoaYghsU+f
W3AqTULo5E06PIxvJaWTZF6h6PMjW9JFN2Nd7Ikvs8u5TpFuvA3OAoemDktxhciofVpL2LRR6JMy
aPiAj3jDW1dNNdxMAFMWGPlZJXK0PMJ+v7+7Bvsk6xYO7BI2Eoz6xk4jYpW9ajh6LhvxHQzBW1hh
BR2rAdKm87ceOaIBs5V77uQe5StwLHGPdpY/tgJR4bTe5R1SyEdUR5QpVIb1CXqGrlPCfCHWqokj
uh6LRbZqcRG2u4+uPoq/nbc+lWV6zks3+BFTZKQMwaRSFBVpE8o3YfYcnTWIgce1+E9lMvmBi6h2
+0WJsA3WSFzlkPZqKHCrQB/U1A6flHHyLkuGWMEXB/eS7OOpHcwEHekxyLRzj/VZcrVdLuNOD7D5
BrCTEHeVtZ5wU1smTN7T4cSxCL3CRB13y7YRuHq+ZdwbY2WSqQHiO9G4w/W1lRGkeR8zxlC7gZSE
T/9pJXpggovxdxW81gfnGRZ9bePtUt3gx6lbVsvARWhHbkO16grP7uZXHuFctv3AWDwrZc3nBsUp
8aYJ9sxLjeYVLtIslr79bAU44TiL9lOojvwCmaooXHVvADobUI1XEdkAS+ThaE9jJScKRvJtH/nb
gPBhcXEoiC8CWseWeoBIO2LRZQvOD2f3Xk3C09TyvKhtcqLkGPtporLaP6X/7PniUwzGAkhUsq0z
DECoPKsj4NjJwwtEeFVa24zXWY/R/bhp7QLbLmaPJOPplyQr0loiF+z2dUbhOsFE64JL7bV/tb9w
loUA4qCOxaXEf1rjUdnevE4ZlukKNe09UE6O9lU9RoBLKEFU8ABZt9qBKpJh1cRvwZ1TIMmVniCI
J8Eun0q/ynwyoGDhwWTtIybegbVSbP8pu5FUvwhXjvEy6mdDeXiyhyzzWRtLL7wqYNlC2yrjCYHK
uM/DL1coRmBcUM+O9fW/WalUUXZb+eqZQOutEc3JBBYEJOOHjm2HxPxBZajGkvgwT5Ul4RucA9Ee
66kVdx97Zsz1Blu+XK/NUWR/goXnGy1hdxoepfxuFS7/KveHrHTFy4T5lImrMgtTU5WjND7drBMs
96TilEhihiZyvI00ZMXsLnexiCYgyQ2KpGWuCUTi253qcHSAVuf2qbjFpVjUKPzwAeaW1n+wgPtY
N/akpIBDhslh5HcSgFxE9zbmsugCecfmmJq8WmDNMOAudBJsvSCPk2WF5aPxNnUwda9+EG6Iccjl
LUgAsVVG0zMNtQNHUiHgW0dJFh5swDGTuT4p+BtkVQAQoP8zm1qjdv3zxALB2kTYloAyEyE1Tdfd
DtNQWCWyVATE98A/kbBblV4AcpZM8VLhmY6pBE3r9ztiKvQIJGynxTg4EDhD2ld6J35EAt4NXHu7
olsaU+7SSG2eju1jkvaITtKI05qWvbaKKnI4F5S/L1Pevdz2qK7jNEHRXbLh9UIjqNwBCfrIkljW
d4sDsvDBEhWSGtShzaGRX55yLHk4NWUaJMtUaIxN92nJ+94nc7nEyn7nA2eUCjtpyKuQTRxhpz48
5xPRz+Qq2CIcXRHQZ4MY1rbARicuvMnxFXkHeyP2bwX/mrcO8GMtJXL0xKLZnpVS0c5JF+4rZFFJ
nq/dFR/+IY4EYhJPFKB87fO1HxcNDpNDOvcB/algJyfoBdc/wKVyONK6lE2tugn8EYQq5Ig9diQp
wodjX6IsBM8dLFmFZCBBSkMKdgDkZNg0l7suXpheB1iarrptd7tjKI57nePpc/g+xyp/DOjoSPbW
PUa66fguy7aBEFabc7eazoBL88Eunje13pmrBR2oR7jzNnjzm8JwmwRgheEDpC1rCe+kEM+vQxBR
eBcNAwreOVk5ENMbWMFGYIn+/ls8Nup32f2sWMdp6uXdnTGkwC8sWodK87Z1gnadlYZNuC1vTaLp
7hZKGRWL08p5bLXwZZqri9QVfANgG5MU/YUa+mS4rF2DY2bH0u+3DD/yTeyOowBzU058bwTWvoWH
snvxGwe217QijPHzVPNLn/UqVOV8CC8BnyS//05uO1OENql1QnckOJWHIAHYxBh5NQe+vgPGZn6h
sBYzeylP1hWqKhzbLj3i0U3vq1fho0p5iEsUqPnsr0PkP7hKNcPVojAS3yuf969tNwZDlalEylR+
6tD7xotnfSFkTYbW0+X6sRrK5ju02/C0UBzxBMhvr75fakdJzK00GLavsKSru0pElXY2/zu03qP1
OyX6aALqun4X86ieFjBUmunQc+3yu7J3mzlgL8GQ9taW1RmtCf698aw/ShQNyf+lSTCZqj2A6wn1
yNPDhQGZVAHtwY0rpyERE6bY+xCzHsz03AJCXqAoogWnjZ6QWgjc0WlOiJ0A8wYYzxe1Ji/Y6Mpq
uEQ6tLs9GvvtkgL4FJfK99+KmOlu479H+GYIVazpk+zBpL2siyLC39cXlUJq03X3q0uA5vJbiTsc
Ir0gvmjj+QgnsXWDkeL/9eYBsmzFBUnALoma7vx5AT2FflzNg51Xc4Y6/cyS9n4+RgjYhzPj2z9/
Ew6XchiR5zY8pau4HoGz9Us1Y4C6DxCl637YzrKd4fTlXlfd1H+AKh74KHsq5CjAAX9SpYkDvGWl
rg5KCplS0gGEq0Y+hqEX20SHDFj7PUY5COzlI0evcNf86e4RiP2cstEz7lJ4z6eG5jG1E5CtvuT3
IDNsnUkOekd5WJUsjKYe9dWfSL13zvSINqAiqrLlfq9VpT5MAPNOYDaEfan2kBnaaVKyVe4k621B
c/W04MeeLfyQz2c3ZlQA1wvEolbH2oxuX+eCpUgb0JYF8sU/gIubwjNEt05XxBWw8bh5a6/H2WhZ
T3Niw1H78+dnyWRrxsWAonCNPvI6M5wwCw0T92n8yx33enU1nl5t13xQME7HtH0f2KTBKsu1nUxj
Ebhf89oJ8zXysd6F5HqMxPtJXWjqItjVocyNpOqhECNg9w4q7Qrnq9ILma8i7Z7QbMlrhHmUOURq
a+GHozOsnKrtDBmL/5njfSsUqfzJk/O3umSFoh2KVWOOJNgjKhUtBDm7hS9fPOOM9HIqNh/Cz6UK
IMcmwtISrMropei43z8ENsy84TnqQzM/xZnmHFq1RUbZcrhqyyVxGOhbikLltV/WCEe411nrx6XS
OkLMjOxrltr7mKEeatZhFcopffJwlML05QhxDnvMjacGtxKl995aMFM5EVkIXOyqEcRIiBlGTFRa
pSb6wY5sWMEqntVr7GwkegPWtSd+3uRfPVNodq+aeJK/0oGOmlmHuWo0wtMvBXY+pXn6WhkEWLyB
cPRe4TErvZ8u73ZlHMlO5iDx7R4Hjd2vd/Ie5Ol2uEEM29LthiRjV+zOgfjqMSxM5M27vgasHBFY
hVujZIIcwWLmdDHh+kvltkddkXJALOLDoHWFphMSBkJxJUH8w2yuS17e8Wxnt6aw/g7YwhrlUu0e
IJWN/fA3K8hiyP3C5bzKBrY5fuYE1R88bleH7U1FJexnV/wgckRe3MePhvAzO6nMLS6x7MZttK1e
waQQcp8IPPcEzyKlxIVOA9Kto8S1Yz7WRXnTQ68v3ohQpnPGcxXLUAFa8c1fxw1MsAzwkxsqnAAC
uZgGlJhk6anF/V5MqQ210Hp2Pa81F60Ls+n18BdxcO+U8qztwX98NqjptJGZeCHVkiaiOsGXD8S5
YzxRhCy/sfKT3udQLMn/oSeXPeMHbNgsU1F7btL5iqWJi1CyWx+ydH6RiG2dPdNqG3+V+e5fT41Y
njSV0wFVOy7kRzpar+0YM2Qlhl/gEuZcPZrIG8sPbYtRLT6e0KpqphChGEsNg60LY+hEuASGnA5i
Oq+0R974zeAxlrRAMd3k3Ij+YXB+hfI5opXlYYRtFkaeT2JkvgINrWlucfh7WJ9RpR4NqlMeo+MN
spdjtmGCF9aI1OfkcLOPj/xdS5ysS05kHHJ7TbrdTeS6aZFTP2h9hI7nLOJ7y+XyXPScwl3UQ7rR
Yv3if5wC5hopKojk32FnpSfBYZQ6OY5CMmQQVfIb9lI24F9lPfu1jt+tLRX88pEnha+KGZTKJONm
xseJUZrZwg3TE8b7AFg/T/S4TMiN47NgO+QLW4l5JZ3PtMF0j9olr6XC2p/R089PHcooL1h7lBjG
WcB0AzUdNDatmloArfWQZVoqQtPXynUfErvsMr3lHsstm4dDT09L61WJo5QLMVo6WRcK03i/nxoz
54RPwWK/ceEACr9gEcd+yiKfv7XlH9KYEgk0zDdYGn6iHTq1ZSv75iyAysKXUmKHNISbm0aP/NaY
yx/kdgxOZ8gy75gYgK/zIBaZo3oIfSufX+sz3qgOIATyV7YWK+BNmlc8j/B35vp7dWKPnynGCCMp
sl4pLrYUW9L1+qzHAEOo1/SEg5pUWFi+dM9aIY/fZeqfxGclnN74f8URM4A4qyTaegjBlLBtZJtq
SKe6deYZEncgi1izPdQB8kU7vsoGc+Ebinugl6GKqoxs43Ti0/8m0jCTVS+J88kPxEkskGNxOeSG
i0pfuM97MO4DZmmEu525t/Fu/3Lp1Ql9y71Bhfb+BVNHkCUhMH0/kc3+YAuNo7sPpI1+B41gfY+x
cVV0cl2X7/v1n2ddtSPnxUoMc8ELLb/wOlegVXqJUY6nFhRu0bbrmaP7MIafBDfI8A9QR2j3wfTW
xWEHS5zscdDI4dJq15OA+seWzd3bsw9cWu66vkxxHTi/WhFOVG+LxJJvYeCrGZASzoOQjGSaosLa
7fx+cAOcCwp1ls3yco5OCFJhHDcgwOIGb2DKpk0mPkXpl654nc5dJF7QyingjnQ78brHDr009b24
f2bCK5tDPUoR3PnF7NaNaY2xwiclGQfsPH5YCHgMBl9mQKcEDdsHVb5AkuyfinkVqG9qypeHWhQf
28lyiXwb8ooCp7IAIx0EZygEmQ6bdV3eQII5sq5MyWSPpbWNo1/KxuEBAgOuDxN8lzUfVgUbdHOn
Fu5WrDaALtUZFvK7/2HSXCHep7FMcDMkLr7VI2MfhsxnYJfFZSuIwElfMxUWDFyJAsZzv7jR9jc7
HbrlgPQ9jfcRjrzv2KRjYBNpoLkbRwq//g2dow6tbKp7ZkmsVpOSVcFbm/ccfKuSGFirVJKiztq2
vu2p+UcismWtlaVtipmnt3HrrOBlrbQHV19rmTQDMjslOOvSsKLGhhY3MYJ7PMZzM/IsQyeFqO5+
pYI3rS0wre312ZAcnJYrXv9JiG1CF5TDjiII0VRoVI8mgznwYbr8LwrUvUylvUqYGpiOW+ubLAvb
UdCI1TlwyTPW0NPTglhjui9H8NKb89YF38p0Zgd2B9NsyPRa4LviKh+dCS7pOjq7u5hXE+7+XMva
VY7nXx6mB8lRZOVenxHej+TRRns9OrJf0bzPUyDAp+8w2769+WpFeGqzfwXNwW7WtEKMXcnvqyjP
HSXkLA6uDfBPHhofXodATddpKiKv5bQ/9qsHFLfMC6xbWyGs6GEeZgGUrAJL37gLoB+jW1F7aI0C
+Pf8fO5jDwA/irmQI/RrmUYm3PZKnUqVHx9cRtLIYF80A2bbA/YXwIn4490iaAdA8rhBauYreUkg
/mhCw96eBn6eH2x7H7wQeK1G1vKu3hKQ2OZedsEs4usC1FkzK4cL3WSoR0cmUfbib6+Krjwj18Qx
Xz73AfIJ7Vz7PFGq/KKHZoHWkbXSboGtNEZJJ4NU1Sg7qjndM+SAfFMhp3+Z/iHreuH+VRHvMoa5
45yFSGxtRSuA6UrNw1x9DgFr87O/qisKaHn6tKpMCJmw1y0CcXRME/nWnVnBK1nrYUMOZyvh/Lcb
fjMLkV2ip6IduvkKB+Zg/h6WktCsNWdTxTIm+rz9KHlCerxDrLkcPqyGz1E3G4QFgQtPrliLAelY
GehR6pJrwYFZTlrA3Zu3zya0euoDbuvUSPpUElN3pwLX0V+NHFJLvlD9xvB3PBJlnrxpSBE1pLfy
RmsZRv37ADcoZZdLHKE89MlePUyQqYHyTgLxm4LCeZBlNhYMgYL+99Xf8esFcDRCn5bBSmEX4+0z
JcqThA5k8/nTLEzmPnn0BUhqVXrXvfjBTZwgzc4jmtDqSFy0H1vXtuqGI7Po3XkrmTwcswwGGUyN
JfU0ZBMv1EXTsHBdFJZjp9sE673mdGOKS/8keDASr5U3JcLRfY9nJiXle1oxDFYiNVYNcdWVFJd6
qLpvoMMIBd6mnLfTQMi4tM1HmJPDPSaSTYHPil6ZT7MwuE9JZtGditMHa9o80516WLhcP9dJpIRb
gEGNOnMVsSBVVQ1O0ngR0UoToo5BV2DA+M+V+ajHsVsFoNWBHZAzpdPsAXb6zDBsXI3itvyQ8/bz
l7CYpRJs80x1ZEfW5SFUrwO84nYErFf9/5u7+vaaXhg00yB6LmuvRMEDNlPJgGVJu1TLqRlQDgHl
iYU0rA5S9uOyP3kyedD6GxiutOl5Rgb+wAmtYrU2xMOAT0aP2GKrfqnoXQu7uOIOYFCYqngqLVwA
+JSeVao0CA7XQwxI+c6kkQbSrT+KYvxk2TqvK5/9lrKYvrrgaVY3fEy7cEUcj4RWaq519n2s2el7
pskyVMhdTdghba6lpGVbCKDksnYDdku5E6RyPYbenFDQZMSZ/JaJIJBS4C9Wh3nZXFuSA55bMWBC
V+C8QUSqOuQI4c++5nE4MUUqZg3kZkNZqsDqvWTLbM/esVu1wyZLtDApkSEAcNMvfWk2QKWz6t7f
CqtM0LcpvOJjJv/k/+uzo4RuKSSXmeHLyeQpTDKMgd0RgZn4l7HgqXTniZwuwqd+946LUnZ2yP7S
a2WAzHHs7PjWjiyLHure57CpUy0XXvOmbnl2hVFgBJr6AXMvabTrhxapv39CWoZpy9jeQhDmkDox
WJrVY9mNG/OFm78PHbPIW612XRDApyBClPTLW5/trMgReQCMl9Igfv5kfHyTPb0taK+REDCH/pG3
tIHs3lKbgHbWaSXSMgumKKbQdTcKbUTXMSBtfOLMwGRAki8uUO7raz8pvigkJcgeqZlePllXcqs/
RPzRazLY4phgv5GgfIx3jjP/+KndLAf22BnyrIKbg1WkfP6KVNe3UjbeyJ257dmHSjpu/iJXwZnu
6slwZTesC/n+U0Zb9UZi0R1Ucx1MMZBJw/rC/6cxXzV3mXNMpUXG29BPXlZnm4sCsyKGQfRm4jIz
H7jCTk41AXyv/3Pi3izJzV9OW6/F2zwZlzwSjl2zOL/lYCJtMH9ODtBw3r6Xx/LoNA4EmcQjZ53W
qWBRkIMdFOzP9TqvcO4l2lyiZpMyP83hjKYz308GKwwFREwC9jifDYo3um9WJKhHrs3OGACQ9Ibt
lslxmbv4ffEjoAhuNMsjEmK0CE6hR4UtHiqL0Fc/yGGFXlfSycGfWt4RIPq7RJu4avxJb6pvBima
UKtan6knJYZaNMheYxrnUovXIFuN8LOxtkRMe4oiKJl8EmFbxmb88dWg7bjbY1663qrQlY2DH5wu
ECRW+CZVFaTaTZUvKGWmZnKAaICvwJ9AWtkiK0cIL9z/GoHuZqsj+voUAaM11pHKH3Wuq15wKFrl
vOKnyofpJ5PqIeJUYF/pO5dlkaPuu513CKNNsWHJVrlvJI19GZfKValdpCgb/8j8K05dY9pjQzR4
ZRlt6JuLReSFWLXrs7DXIPyO8Hl9q/C0/rlMDYaAe5G2xq8fqy6yXErb4dKk5CX60+M5jqEFfYRc
3cTboYDX2nQJSJuKewGEqZjmKpmJePT1yYBvs5JGpRW+j6ko1o7BShrdcQIvFi9UAKQHOCcLYT0U
ZlLLFCbRa6DW3KNq1j5DUJJMcjqf/N2UilotxU6GOeNIY5eN3y6vFOTvFZpT3iwmqsI765iyxVJ/
8Uu28hqCuwpBCU2ZMx8mNbTFbK0j4pYocXXArSPYp1U8jSvnVes0a9j7cWwC0dFKU8psVAiVSTaL
rRj0t+S5B+pCyjFl/DjGnsZt1t2rfA5axzc1zunOrS41XgvcCKrgxD9Vx8faAck5HjaiGDF6zJzj
lhUmKhwjdxNfw6azngBpmezGz4fGcXSJ25zU3JyBUH2SWroj0tcVX0MyoEGYmxaJXBtX6M7/tuxQ
tAEHFpHBuVVvoaYWMwVPuyl6MK/zSQ6xo4mDll3B9mSub0JbIrMo7JHxUGCvfi7H9A6Pe4kY+bb+
OT8cJZbiRodzB39Ld9BRrS8y3SQoUb8097N148387PihB13XKMr3H9dgHUhuFqnac4eu12QwLZ0r
CUyra3ofM545DBu6Xl1yPUc0UypijccRlZHyppcxPLCp1VFsZLT0B8Sz+J3/ghosgj9LgXS/O4Hy
4rvIy/r8unyaQtiFo+2eVwKUBLXhP2lOsJSV6MWyQ3bMut5SMKwAziHrfGBdzqwfqnYOdU5GaN90
6B+0UI8RZ7W6gl4ctLQCNBFVWdNUmTxpIC1HfNtoMicfAgPqV4KYaFN3Ub1ECSYZ+lag2iFMw07k
ltlmbEUEcEJZUc5+vTZfU24atAhSS9wNU/5eAuy7TqOCHpYs+0gVRC789JmeWJRhKi1EMVTO2/ER
ovCL47bHTQFOk9IZeAlizm1t052i9U1m0ahMLnItWdAJ2uMtkRDWYeOz+K2fxB+Gy3DHRW5P3UNt
5hIYWQ2khLrw58CU5SOFf50hi9a5AzL8WxRvuaiLYiXrPvxf14Qti2Xo3NA0NQaezkhWmkS+coi8
s5nTd+wYIWVHRpch+hSfW6jiwXX1BU+kEcoXFXXZ/fI6b3H3PkytJiXMqsY41azz12yNuavNR3d8
fc8TMW5LuO94yxicsp4i5CAZG0Y6gqcHAiVuu60Hlsa+wdRL5RZcPT7TR2ea/PE4jYsgqEpPa+RO
P8lzxK9Vkt9NZEU7OTT/I0sKx8f66Vfb3PL8+r+iMUjp+newnKt/sqHNMQReRLDnFyOCBn2Jrcf5
BfKDBZ01dYkD2CajG0NRysmRyrMB9CtRs9N4I29Aq4B04RXYZAZ96mZdqIeZlMXpYB2/z/MZKJoC
evazDZI/x6xxoAlp8p5tsHgbpq7/DYPzS/WdhLD3+I+KOOAXb9VlqWLq7pJw/JWHb61TnoxSmted
RMa1sDuWorTdUJvJif78Iu1b6DXTgGSFAy5yrDc+EAf3qCGMnKq6kjxADtqgCJe5bPHF9upNgn21
eNz2hquPJOkcqe2lJONE30H2cy0Hx3SyOy09HcFtsI0HU0gVSmLulwQsqVF+eFZPyQGaNk5ltIDt
Q0UbUbM1bKVrqsEYAfFKnhC4WozbofFEekPnrtp7xLCDze15sjE3DIhVxAK2VlF37093FZLqfuni
WP0kTQth8AU+ehO1ykG/8DvdCRzUi70vWoQXwR+X11UrTK7eABIJ8yXa7qcDwm2yjo5iWR8dUXHw
81FyqeMAmqXiGM0r57eR+cYmcXJZN7mrzZirOHzdvNvN/phaDzIdMLjqzUwQxM2tZ7L6S5jMaghu
UXWjnVv6V0/tX8Bvrwos+1HmlmHSWqjOCssKLPBS/+KFNwaKN9/+WX9hHxQJqG98EwVPqizi7pUw
MrImiIo2gEh7ncc3N2/7AasnSjhDOlEwr6jgc6zljQho5B2noX8DVV1unLsunE5QARHw9er83E3C
39/yuUmN4NmRInPanenE2TN3Ml/0xKC3za81c75MqqMtzfYu5KSoOg+OBp9cfQcW+NWzg1N1tgX9
zGKBvcWvWH39jvgheAfZupZvwqZ9tQu/WXRuIrkp1eClvguAomMIPd9HMWyQ2se/ZiCwMaG/KUye
71PAiClyvmxXfOlL9kY5FtA8yds4BKOqtskXNaSxZhXGu2JqyudM5BAF/U191+MaLtRESSxQoXXC
QuKqMZ/1iRnoZAuU64p4HUQmPBmvctee33WtuUl1LT/djxd60qcAHrT60p69aZy8/WWoNB6Wrvso
OQvZCJ3nmCKTfSyglBQcZY1DSJrHKowwyvvetCL0D7K/Z/yd91aLf3Fhg/4vIHIMrqhygHwC4PPq
emZvIPR63RaIr23FlzcjGr2scZVWqebPJMBE/tUWNDpjphZxToXo4LiKdGGDtaivZWIUEHghArvE
oO4hsXODA8cwHgsTeYkLcjzB1D0L+owShQHs5r/OiUKDKgOLWSTkQ2L1tZr2T32b8/MPpcDFy1QM
zaaZKIVFCTpKnoCqpTbgf3cA+8IE4/oKT/1M4jRpes2BeWKOMz0tLVzE6KkvTOykpjK6ZlaxbOYG
Nyvff2rawlFXtotjoITKbo+san2OB0e6/mh6RaQaA+WNZnmBiS/BpAj1cwsHU3wZPR3pgrpUucSq
HDd5Yvh6fBB4380D43U9O9/bxQfNR09C3ajglYPXNpq/T1asOsHfByIKby9b2c8PLfM+WKsQ7Bd3
soLngTip+pEJkzZ+L4p5RQp6bjj4bZ4m/BMP+V25TTs2KMSAd4NNhDKuV4DF7Ogn2mgRJsSCifpp
LftJBCWIOf9ZWXg7Cdo/6f4hNi5aF26lw7TJqFq1MUqoYKcC5mLSjOTA407fWeK3XJMM7eE/4Ond
/ig7YsV76KmB3r8kYU7g7xNId8ADMkNBkKbwXuNrCFC/d0uoyNhro0ocGrDimupXLhzvyMZIr+fx
xCLBxGS8PcsyIdt2Q45TETzZppyP9l5OZNCRw8cWOGCdkL8Z9PlAOUoAdAaqRY/tjQWAyRVFTmFr
7UfHFTo6C7W3+cz94djYyEx54l/lkgvC2yk4FKWUUqtkESB3buWHeXLCCFs3Xw4vqrRxJYBdUCM2
M9vjRgEvrY50hBYt4G6okkMKvbBaT8sQwv/m3sTQxlVkCYmsm3Ka0JoHVBMcPjtk6Yphp1WgE1yH
1qmlbAxs2Dn4eehNr0V2eW90gY2ww8OPGyzaOwW9VtVw+pcr0ozkHrma6hygZVz7aPad0LIWr+qJ
frNTJljPpzSnahANQNifRa3GcJ/wuEByV0VjEPbwLrlBWo/166/7qTcEgOU2LJk8a2bpor+aLcC9
AuuGZVW+8eSVA6afLUxuTEVhv1s8nhqSszoG5fSwtR0VHmVjbRekXsoMcTJ3qdQvEjLEsWOfGdn/
aj2VaHqBnUMJ7+0W8rYkE4JvckiYtES/0lANY5uRcsNN/MVsTTIu39AdZa142tN4fxoDnrkMRj0u
8tYmt7d1IjFh7L4FcMmAoQ4HBKuZlqN9mP/Cy+z2tuK+XYhOHaSTiMuamIZ4saFwdDK/ZogW5HAL
eortZeZNQ6zpYPFy4BN6HmNcv7+VfU1R/drGUYPOW9hVpNftAAA5dpoWlbZ5SkhaENMqspHBkaEd
Dev9BVCHsWFokN0q3Av3MINXl40r9WV1SUpdpDZAZVA+vnv+3g7fHB0dMNBQB/jKDvpn4905MovR
GfAHEXjVTFgQSZCL7C3wV/VMCOZ06MN5tAQssx39cI8Aq20VlUo8qLnY82uv9psm+Dg61NBsl2aY
QOVyaYKDs1I1FnnyrSqySEV37nBtTxMNOnk7lU2sDAfYiybv0R5Q7b/cFfAcFfgZ73ZaN4yOwysc
UUQ00Ib6oda6WHfjpGxIDWz6XDyGKK4nFp6F3rTRV2QkJG6uaoedEanjPQB3FaCx1HYUA/JvQ8Zf
Syk/Axap79BsjkIYaZFYSYXnf5xsHBEG52nnOq06zmRa+iFsQVbphaVSsOsqDfJtdMqfFlBvsS9T
CTyWD0dkgSqmVU87lO7VHhjSf0LDCUKFPnrPPV/Zwh31DpusjNBb7FOxtanEFGFuw5RAzpzWB55m
6UhUdjNVhbYbFB+XH+g7d6jUIJnKZ0jg2zufrWpGo44SkUbMM8ALoXQPEDS9WK30brUqZs7CrCom
i/eyRfglALclkgyhrBRjNcOLXuHeim/KH65ShqYBcjl9St426DhFqIOfVAfhq9Ozn5TzYVyvqFpk
GM37zaKanDUbS4w41FgN8XkSXmquK3QyFOyTgVf+yuY66BR08RRoJlXYFMzYFIK+ZfEWcAbdsmat
h6xROGmVgqnUXNjh5E0MXE2WrPn85DvzeFiYMFNpLzQ4HWzgGYw1ZTdg6Oe/JfWKC+wD0zrH3/XQ
BKtzsJtdQ8YLnituHF4IkD5e3M1Q8X/vqpiwOkFi0f30DQVVubOY0Gxwy/7Z39v41781ZNwn4Zlj
9IySh77DwOa+C+opTErvEq4ZV1N2ysednqxjF72NvFvDnev6IET/w0U4BvLgg+BapBd4PMtA9tyj
5iI8GuSnHI/yKQG/595fU3ijKO6sumU+UUifMrOdt2Y+NsI1+dnYjU7IwEfuZQS1vzJ5NPujI2/t
SFmd1eNiAz3RR/dM6fbT/0ztuRmAcDhfu3EZcb6Jq19vT5siUnC6zEUenXlRJsHnHJUiH5md/mns
w0apfosEG4NmNdajXQM5qJRGdImCZHNeHNBsHRS5ZPtExZ05q1Pw8Y7zRPExFXo0FYm5RpH0a6O9
GQ0ZdLcdyWj0YuclkBSNdpDeq8A1dZmwPfdlv8WrUSSgpLC65zIgGU0yjQnjVfq2lf9FQlXf06T4
9wDhHSUUSAlZpAjoQHt9Ct7qpXsSwoh+E+8+DwjPexbDlNDtsDOo+y36dll4GzT4T2K/cPgqCLck
yODNM0t5xQSnmyw14vYbflO4UHYDYZhQOwNXmID8Uo5X25D+L1nVQliIS7ADK3gpI9dHvGm9wP2W
HnHsPex+ylSNpfwc0QXc7uE8stUl+NXH+0+QyHP0OiLUE2EB2KfkKuOftbuQ2etIiJ169/C5rbub
zUHH/p7s7GguKQuk2vnELVEyjt6idDTRga4c6yeCXSxDC9/BjPUyoUKcwFgiLmxi8RcvaTSPdiOu
ag8zCs/pA4Wvtc1LwUvrQHoywRqyzUYgYsEff0aHdWmVXUXWNQJrc8/CEEe/lSSyj2HMwtx/pe1d
q5x2OfFJUZnmAJ8VuFLH56rOndAUhlNn/PBJmi1M3O8dcgMOXZRYHCGBunXkh8WernysQ8tFPQuY
auYDNN5jkeszFabgHx2AL9ZaASPG1kWifSGo6pcqjvrucN15hGGPvZdoMeUjUMfRVmZne81f0zDt
I/v/z4a4v9rlUjdjssFEjuXbWrBZ5BsF+O6uePWeFmr+o0Lo2XQ4eKWmCMX56en0GgFfu3sKJKLV
XKsjCpxLQylJWSamOPpyjZXqkFV0KBa7+Z29nlZdtt/ge38qsoBZ+dBiq9HwEORYN2XLpHg8Tyx8
XVgFKeojWdnhXSS0zjc2XRop8qz91MOX2+VA4dSdAMl9L4ODE4ePjtVH7DqtbTuR9VRgnOoohFk4
IW/ScLqOuFGKZhxBPFXUU0yhlWgUJyBec7WnECZX4W4SKUQOZPD9y5QdYFBZSHEeaSv/pWlpZ9rK
R9GN3HwzyZDdgu1rPOGhvuWfCxWvx0Z5M/n85wb8MrcjBeIZ/tfYEcCzfGrwI+PWbfEqJJQVFn6S
X2eH9Ifud7gFcsxIjVInbFOYfjroDrKlhjbRbNfyxgRenqILejyHM0rXG0GjaDxBaTvGM6ifCB/8
nZ7wGbXIF+I/+IlYdI4Y1/JxyN3LPtq0Tb0sDQi2x3y0ZT2Aq3N9MaM8kbsN62tCVZa4z3Bd1u+H
QFyKLa2DYtdZ+3Yp3JamnMT8FEVK+yYqPg6BGG8XFCBxEQDiKxMx9V89EAkcBEvvhNU0Vdx31Nfb
+gxlEPpqRWLmla4QqJFCHVpduJLsD5RY+sWOb4pMz9tvwG0q2tdPc0/lwh6O16CaZ3GciNLcL431
lFIIYKppV0vwCQFgws/UQud3qFH8YIyw3rMTzu3omyBM9byp7U97itwEM4hYSu4Ad0fpDtJ4DyH8
N8VAQqTRcYk69mcC27qA6pQ9OXs2HBgYFSe8YRWY4uVJsXNrmfHuZpVfi48QA+w0JV1zaCliE839
asX6M7elIqGolyXZrGUaX3ItKXzogMZVNTW4bSEs+FiS01/nMx0XMUX0bxEDo3G9fkuOY0mg7ZTT
wv5j7zy8LJgHrHsd9tmDDMLlG0fK2RmIzpYbU3ispHNXgLe96QNsZItAHI55ioM+Vh1iXNTgfmbd
Nk9eEAmU5/kYijyaPpHgc1J9cSjRGrhMKz/Nk++gDQAbW8MbFBXxpYcwTLUPKPjqWbc3SvaRVFe3
Dk3/+USHi6sns9ViGtDHz6so2ToUqHr92UbOfclRRAUVB2ihROtBcz6wtr2MkarA0o0T56904PjW
HJBX+KtvQOOJoeGiBZJm4eFgQdufrBzoG5H2zt/Cruc6lKTDCcVCIkR83kLI0+9R+nj1i2KYHnDh
NZklu3Xq50RXEnyQKspSYjNT7An09uWdotc4IAzY56psDaVfjBdMTntm0pg1vqQmGsTbxGm7jdzL
tgrQE/leKqgMO4MlJf2kYKp9fOUlpWXGkcqa2TCRs8VePZplMtiCKGg+BRkn0MgXIDw6pFWRlBnS
BWiXOWFYWFuPhDHx3YPxeY9rL1MtAc8X0643bxOXMgMZSfORXHMiCtiVeRHpr66d0aHBEsRQELPK
s6rh5TbGNuP8nkrxuEpyI+XlCw135yKsTkOwxZhA/PKJhz1nzrQSbOvAcV7PIJmAmv5krvEc56ie
P7kbPDKFbntV04LUCnI/zfwUUTT2g6x4ODLXGNbxQFji6sxmWgDfz+sEZDjpR4BdqaXYApILENxl
QH3M503nal6DjHRlPnxyBHnh1AgM7bcUS0HxSf87q21qt59uio3kjslt/M/eornPgUzUFGsOfJL/
G2AOj2PtfSZ8xMOwKFHmtNpQ1J9kU3IIwAGLQbKoOy1uttN+qlZD03hipQdkk/NKbK0/ZigzheBa
/Joh8trDF3hCBHhudzHJ+YhwR7nrkvDt/4JQCl3N/YTFB7G4NYPZX6eELG2QJf2CYhncLB2NvNsr
q6CmmtfMbJHNbqrmbhYEDASoRp/CTnNihgpwJkjlA2Nr3lTvpQ9fmOOfJe/LhvLkpX9cX3gXoywe
1UMw703X1TqTVBPZfirnZ7sJUmEgS86RvhB2BQSZP1sHiqroMAj9NpxmewEDGZkQVSbmNW1XSJkA
Y21hvkHwYc++ByC6xdWqEZFpoGhxKIei0RUfmJOOYS4cYX2GXY/SSbFfroKtYb5ZazRc/G3MpI9D
lTcx8R1rYNcPFYTedZWjIy5apVkuL4ld5kGu0Sd9zOFvIyPlibYgxz2LBR+YoY3MIF5jFhdZg1Pc
n8P7viMIYpRR0AvZuEpJPgJbhTl9aFJNmskwAJ61U1T76xOgoLe0eJ1JHXXdBZpifZtP8diD6s3f
x9I0q6DYMLdt0QElMBID3SHiiGPQfDub+Gu8lxa37vs7ARoJb/2i7gEXGzVX0D0WATOJOaKt9v3/
DDhprN/njRb9SwD6vq2Cjp7hXhuflznMVwVEHhW8S45MArTw5Tf6svYtpgG9WinpKpYtv3QtctCK
F70go1crVEYZbR2K/dthAjGTQYE1xfIIvBwoSBr1RvxSnaAreVRtAvE4D8oaOia5P9IeWdCx+OpQ
L9QlnxnVPW1FZFwZvs3/UEAP7bmuljqbQfLybwwEwUmAmzF8VoLhhWvIwY5jnuGpTqsQi0r7Bm6h
qnVG+WEsRNu5IYnwGT2j5DtekD66GiTaorIVnkX8S4zByKcTAbI3XlSSHhXtCmy5rghPMfCPh5wL
ypX2OdTK+cMQIbMkYIJWGvYaNgBmtkubUjQCz+W7yXYCvTb+PtxgoiLLiC/DF/aCzjHtV1krizOJ
Sjo++i7qpNqx3LEvmrvRqfmoPKSz1AQV03LDaNUUs5wsjQGo/0XVG0hRt3tG4X7TGkTLWoMB4fYV
IxB/qzNHfn5AziTMV9ZeICdqBxNmaf5pUbgY616+val7oWeDIqBXRPWdsDfuHkCOtJ5TJyI1izm5
mNRsGnSONLERQBDvV5864dN8NhjdQKbN+2A/fpCLn7rNB3lwoDZvq6xm2qL6/HUg9YWPGSjsNxKR
+sZdqcagCWuKSAT5/PfbEpppzTYtBH+c0RM05PeTL1r0Zl8Z7aTS6ZCJfl5qW/LjM+B/R6hYuZhq
wYog4hj4/4ibSOH0TzaAAwn9wzIRJGqUujPryBG1BA327j5Ej488qJ7v3vNopl7iSRTZRFVjTD6S
xsiequn0J5T556q4Ly+n3/XJmhKaYGO4M1Q6aHKutqJr1Bw4cVe5PGNW5+h0Ifm7pxbxSQzvVctU
+4/fRl/s6nOUeANB15BGCpjcuNZKsBhCMe3QtpCgP9UD+5FOZx2vJEPQkM/TlnACKPNEyoGoyTIv
Iyr3t7oyVmOnGZv16kEXJPagJW73IiVOrg12mev6kllYFEAmb3pDmi1TfmGsNn1pshmkOH65j9XD
/GLRc+jBtHYPcMDAMKSAJDr25J67xLlcW1CFdhf6bYm0PUEPUU8z7+WTmq/dzXXSOFjxVk5zWnDW
wEdbPKoNSvPP9beRAQE3f2XYHGyYTQ7Y15iyhw0JQjc4IrljGdKNIqc0j00bYav42Vv9fNkZ6LT8
gl13opF9PypNdO3gn54gD0zb+PZOX2IXa9k6FfHx8hShqmlA/mgGCiGa3zTmXiJlyL6DOrksbKK8
SLXRNw3OJe58w6OkxPV+QGRQUAP1qxyDQbRbPNeOUHTZoTtZihkeYDdJPqcRV3F7W2uH5iHHNwl8
pxI1p67f+A/vjeTI3NRe62C9jgmg4pPIPQuUnL/iKuAdq4YydJFhaRLhXYri8visi6TUbcx05Cbx
aD8XQ99Q107osc/8ogeish6Reluv5CWMDyPBQzqquj8aHhTvSejaib0tHcYu2CAcALObOv/yzzQL
1uUMe15fePrR/7dGSCnJ0Z6dbcHOqKe7r5pqPbZ6onV8Jf/G7VJ+Zn8UercwhVI9MSRDR0uESmyT
AiN1iRW7a22inHCRCux91cIbgnwMfVdBvu4JQk7wnW008jeAA6U8BmIMcpiZJsO4/aWE1GDm7OZM
03/ML3c1nOYFJOqdRbhdY7uDE3eHhGVGBmyT/DDBwJszC+/9R4vqkHZxoT2hlCsFNyxDnLyqbbyK
5P0Gu2bz6WMkjuY0clRWYV0TxLT34HCn+nubaqoOHjO0myw++9h7QtuDCe92Jl6lsbDSUQZVKRka
Tu43ZL0WWU/4p+OcwC75bOF0ZpN1aiayY3SgSSJZTVNlGOTmwIJgkvBOyrXqbOYI8HFn1x43+ZGI
E5p7TgtxrbLyLl1QwzXlhd0AJy7qxXvvdU+6nFuTPLMEwSlD4WXTvYmWMYPHhzxaUkEJW1vPNqqW
QsXEkIDTWEpLMqxOnOH7hMkGmrhNvO5iW4hL/dFRPeXpoKBUu+vCGxAjB207eYDCSYFcHIEQdAfD
A1wXwAZgw6rjXpFNykCxK2KySZqs01niYx+DvignN+goMbQun9pjcU2bUQnYZ9TR/i2YsNGpFIxY
nQgVgfUe+x2LecQKX6TfshvbxPXREJP8jVP9L7gJDA3Z5cBIsxiu0bRofKFryEM0BdYw4JF0p3P7
E4APIiTdTUcDeor8cY+44mZeMmbBqwyHw1Cluat2fJpiaioA34XcA3otNifI8hkjpK4nXDLlXzYV
XeQesthilcdvGH0KEduAsgNNQz8zX+aZpDoqwftC5ktuNXFNkiCTFoYGHqvTAJ8xTniqwI3z4Ok5
EhldcBl9xn111QrwLAaaf2KhQ2z20zGQ9Ol6/OHXAxoug2tqwJyrGe612fWE6WdQsFmbuqLdYcN4
BYysk+GWH35gA5E5m4pFbeioFvHhQz8prX9rHLB0Z90yEmfDRf0pUAZ7ksfrFV+4BDS0lKcBbnY+
XJrtElFrCB3uUyaq8uyPdHXroc27304RV+KxKkuqMdHwvP9fbDXa4XJQ09G+M7h+0k7Xke4QeFuT
69P/vsUlLT+kPnMFl38H9b4yywyoGl8loV8oyl3FRtVwuOgksaYzXCz0rqZkQYD77O0kJUm0oeWj
zp1+meBLLSYtk5Ve71/8nA7DW+h7HhxDheNVsWuup14EvYgvlhWhRqQbFQogOOEUaMPV6l3JNYzp
haoeiwhmMSUqLww6xegkFVprQXzzsuQ2ytpLYmZkedk7A8Sg5CNSAQl963mHWiTerKdKyOWyzt7T
Klv2QYZnZn4ayU+TqT+M0hiGkBitParv5ZouAnQvjCrk2tXygRq8B0tDG3vyXdCdy9MZnMWTL2bz
l0RMggz5s9SoW1OnynOT1RyvhfGCMdxBL3nawQ7sKVJvZY9RdzkLmRrMUQZw71VpogKDq6r3AC8n
aCZ5PK4i5bjjQo2IkaBAX4JlQ9AzWOkQ5Y4OXkhUrYF1Zd40PbRWojorJkjsCKmvUtnmlJ5z8I5D
AFw3tuFoX49PdgPBvQQlaOmpS0EyQZGx5NtQs+DZtAz31tgNGyMwQDBjZHUulBsitpqHUu86us5r
J5b51bfyg/y05xYVT2+9n9MvKgGab9VAUcJ0CJgH4ob0AIKfUpcGodQ6FV3MKlS37Y0bOO+0GIAd
AlnxQB7DLbm6UwE2xi5uDAeN31DGJy8WQhskRgoUm62FVaVgX5+6lGNZSCy82h5Z5I1WgGoWUImv
N/F0nuZAMXloSz23OaZbv/WiQ9DLosLjYwvPKlPsdG6MQlKR7P7R0dxzCNpv1rZDW23yXilSs9Lz
huSkhLZXG/fWLi13Qgal5xVoVd47X4LD/lxa7M1zWb2L7xj1OfgZotwF4pRT3WPbkJj3Ss/QFGQ/
hdYyDPHRVgi/3l1+U3bWINcYT8oB/qpu0Rf8b6JP7KnyAVrzrv8r2gSHuqiFwCb8NgDSR81DikuA
gRwpg5OKJzx8Xqf2hHwEMkueC6NGPvgcCz2f4ifnXxSiGPfDvGxxsB7EZBbttrWwQeLsSWi9NVa5
3AEKAFfS+d04XWspMXfk8tK9kFRxihhPQ+c2efx4aboISPvU9mVr9Vxm5tHQ91JXjWKIRkQucxlr
jO68/UY4/ESB2hEG8ISE5AO7vYLjaU/1OfGB/YBS+u4AiPWbDH+NJ8sgfF/yLCEBXTQVCIfSUPjc
o1GEucisGskyvckcmK6TkbHIlZuUccvGdBKlKbG1T1bokH4Gq9LEcNyo3Q/FsUVaXcU6zrULaHKD
T9jmzWifoL/j0YU05ylgZyR/Cxi/OI0Av7lUeKjjVo6zrj5GvQITqgYuFy/3bdIk1+67UiTG9GVJ
8GpJqguIlU/Aszi827arb3fMwOClkyXHOZcYZaidRNLJMbXXws2NI9txe9xXSsyCUuINvQoycDqg
vunomulGtpjxAxJ2dJEVxHVXl0avf5cteJ7T+r4qBCduYqP6BPgnGU49RIK7H7dd5Z5mu70wtr3C
AFtua+9WCEHeWAvEGR70KblP7oAp8MZX/5QEixLcT4ZadcB8o7Lc4TUWTwTZXAy8fdg2JsffpRat
xd/O0Dl/rH/maY1OwXLLwQ5+RvBPThY3aSzf0esjclt4ChdZz0n240C7gr1vC4c4huO+drE88xmE
DfpZQRGx3lSuFHVqUc2RLE77jt/DSOphH2bRZG8PISdNulYt/YQ9uJSSjHTzSp8/XyuAcYhnTxue
/s15wM30wbpxglVXLV6QE/qZ76tn2TkD7UT5Jl2Pv1OEG5b9OmStf2akejwJfPjFO5uH8ez1qDmc
rJJvN9f7Y1+3yiupjFSCAZxcEORX2fJJNd5MlAEmKlyR+s0Hwf93TQos7YljF2TUMlUgwrJ+aBHA
KBslZF3vNaS2q7X+/BoiVUGle9ySik0beJt0uvAe3F/Dqxge08dEFtPwOPPTBQDTG0kvTopwX0Tc
t3iLN9Q+9e8z2ia/8V7LPK3RG/6K63Hz0ToPTVi8x6j72CQ6sBqp756GkNNw4NIrGfZ3D44rgESw
86yXcnywPJDWNjQ5lYcDLMPOaLVmes0Bj/ahN7zqZ8hmUYdep8D6eW1LGErq0CCUibHO41PxkdNn
T5XeDj970UeTM/m88ZRnWJC5+oQlNLcbcHQhHYnGb2VFDKUitsaGrHoy+WJUWPUeI7QifZt7/DIB
/LU8kPqP/FMXWTM6lUUu3bWLs27PIOzDvhj8Br47loj+nWPdDcEqT0Th14pwNi/VbZ20v2wCMYRu
S1WzrPU/ZUJrO3QUY12qCCRscBCnD5peTllaN3xjx/Qvsk/WX/ZULYfLvLGiOyht6OH3J21VftJC
gB8KIL9b/mu8SSPXPJfEy13V/+wyS9SksrRt6hCWH8q78ymmDg3Sw0HFaZG8bocwYtGsB9jxmlbL
IGACgtdbhCCCMRnfS7R7wC2VunfxY7NAJIxX5qjk7teaNgpCA3rSqUUFq0TukU3ZCiQUfpaFYp/S
2gTPuTvZExFfOIz/AvI7GE6TA+roAqzatsf7rExhRGdzZEKXJXXPL6CNqPdy0kCL0Sl9ggnVXPQy
AcYr1Ehho61Ugm805+C/WhT7agKun57sZdsWclwWaWN/Obq9N1WfjdM1WRf2BFkO+JVga/Vo9HyX
9f3IdCddA8uAAbrQzoS4L4JWHD7j/CcIWSICw0uSji8f6jqOVevMaCRfoUdPePYI4yRSbcEBte7Z
8s424/gqGFsNEx1JKEgj450VvR3LxwcCzowELe3h5JyQz5/vZwrObSeVRK6f5QBCdStBfNKpLDG3
zcbVfGyoWDVK8rWZJCdrBCakAuM2QBqXDOKMmM+HHaBJxlxPH6JiWu5JoWmlwOQVqd5403OitMKm
+26ORHdCpJpDznS8om4/H/rw0drVgxfuH/ZiCDns+WsA2eqeDDBP2xo60lL6TqMoxUTjyMYP85GR
KRjnCDxQxsv66uaDJ+yR1e4d6sIgQ5MrRS8l5jUfGSo6v9ijHWPj887nANRW5Tuh0sRH7QbobhtC
5vi3s6j7KFseJH0WAvyZuClFcInX3RiXDRATjoEOpL010y659jK5pXFDaYjMb3M0L4ifjLniK/e+
utYCqwfpkZR9QRZ0S9RoAuHvt/VeHMc2Zpi5zTTLvbPuvssqL02DaM/eraMo+K6GBcnedw6A0cXW
ju+8ZgMezF1YSviTli9OdJQZJWyGggs2/R8ozSW0ZJeZ85QiQu4ijgOVCVacMOEMj7LdwJnnV9ex
QtERlUBtjzraDXOBN3OleNqoof4OJ1eGBgqbg4GIcvssbY/XXDw17oRQc0Pc+EkKE2ToB4/XSyrH
moEQuWJbYLiuA501L3oQB6wMQavYUPiTEWpVwQ5z64l64NVdSyWCZyGPG6hHX/N8IaLRfRuK1Pem
NZT1IHQBXQhu7Gcy2UjzcvjjUAJsJUbbhAl1JIRMnxO3m4kzS94e7gO+ilahFs2NcLG/pFuBM1yH
ai8dUeMcAB9OvuEOu1LJB8/zEDP4WCC3fnfbDVmjnI5cnezmIfmcB/dVFwkZLnGz1VUJO3JHiKGC
ziobs2YIJK90I8OgpMpxXGpYzz4K4tUGU+2LZ4SU/WhulmvJPDjY7bv2TeUb9bIMg5aCpYlWWdRV
R0FQADqQpTWH9pcAErU7BTNksFkDkMroVnvDeF2pt0n1AJDorVB1OFuMBwmEFE7VUf5+RbU9u4sK
WCrUbj6RO11e0X3YwBl80DfHa2cpYEZEEv3X1jpueBtMd+D5tGJKwOnU5/sT0rgjpIiRV0rGkn28
Uy1e1+8vfcOzwHx1TgG8aAh1hvh38FJDptATRUWiGv3yYoqJ7koNDA1JpsKau3QKmqLAVEZAK92V
2fsxxWjul8gigRmN8l45KfEfGLM/kPnKeskVgG1yX6S+vmZsM/ms4WVB5e1qTKq9js6jWysqXj1/
QH0jXP53J3XuIBaDITJutjhChLG4QF5OYd2XL0xCzJXqmJktBhOf1sXmgQ3ceixaUTl7ULkgrJEy
PRJuE1rjm2th1t3vSryry4+NUzJoLTqQotlOfDIIW2cJwvUs1rupsL02SeLDm4KG1ENNEQxCNzFC
xWOu7qDy3wliLeiAJa7lMLH/HY6s8NGpJjw6XUlieSfjG9Fsyxcu7n4PZdXDXlceQcLaR6uuU89T
WyHt1nQ17ZECA5lXFt0d0CBb/UNVq8dr8vYFPHAsklgYN08fJTJ9iFMZjWBQgrkiS4bkOAPpAbf5
aQhKnjvRs2TWlkca60b5lMgfTHdYHZvKg/DKildO+bNrcZVtgGAkIckT6zSyNh+7P//Igtz9gol5
9yRspmmt15xWSDrun7205+nPCbLY6PfZ7DAExVA+k1Ie5XeBBeXd+l7dw/ZK3VvyYj6jXgx9Fef8
vJ865XRrUUMTA6lnMTnacoP01HZzDA72k4Qn3sr+J9WqylxQ2bS4EDvQ5AbzveJtyYU2IL+kknGn
7t4wQInGESsUItFNhxqEF5inzAQBlMCYFZVoR5IRgywTOXpCqv1/qpDUdfK3HbZjAanV6miD4lbo
ZfeyEGplXc5BE7Ni5NUthNyD/mL2L8XHqKVSaOvd+UDhBnjcDPjiAvEOlobQ+7EjQJSZVTiY8d3e
UgwwBnaGCSHrDD+Bn6cUNTvHjJhvELVEP92qm/clLT7QLiksnQ6Q39VarEunF0dMUTt6T17Iu1Q+
N6PW4E6X7M+jtYbOQc0M/FUE6gF/X4T78lU7jafOkv/fUTITg5T0Ta67DjXpU2X0ZP/3c8dPX0ka
3nfQnfTg1FdjazfLgEZyn7Mawt9smJwIsN1pjcbGmawbyUqHoeZaQySs9hv5lZKvasNQkxlAaxjL
dv6svIXA/yxZq0havn5KsfPsdVlmYWrXXluDrhADoT9EkW47vz0oGQhFVbrSO3f2DmiRpKK1ZnYg
9OZYIha0bx6v/OxZ3ICs94A2SKmnoTEOcOSp6iSUKbUCPQlodIyk+OnEFKHNEXGA4E6+FBoAkWWW
/YPbELhEgtglaeRysDNoBeB7Dm8GJck6pZEZs+9vEys4Mbv4DJL2gfH19TwzMtqblQQJiRNK+x8t
C6DKMQaA+02lWjjwcCV0PfS6BpK/wLGgpqNELpQq6bMhAF2/L2C1cxkr5XHIS41t+NwFNkQYWxSF
ji5yAuEgQSFS8C0aLe+SN3Auu8DdaMIY17i6PiQnxe6s+dmooeWx5myhA75c5S3r3PUzihntSkJP
oz07byudLkTdka2/lLgCMF2JVB1MxXw4M2ZLZivtlqBuO21acjA1XAER466+yXZYISGSKewUP/QD
p5GLeiikQnBVDuf7ExkFeEsBK9lhRgYfRI2B+GaafxC7ZDRXCr5OjDeBPY1uUM2/XJOqZaMb190B
ALO9KedftHTchtrFXtfpYzeGLO93XlIMxmFXarnfqc/twb4vtb56IqjNBswdw8hXwpwW9Y6AfSye
42nESqTY3r9slnPp3Ai9fmvc/t7PmMEu7YJWN18f/RV1tnHzOkVHPmGuOVKU1KDtSRb6mCOZOzrR
nbDonWpG/eTUNz5ZDJlFRnku8yG4Kpyrsgk6+eUZpf1wKFeWvP35ydjqowUehKvZ+7hTs3nGBKec
S0WQGSuPfbdya+HEm0RB9h9+N3chHycZIdxsZ2Kp+acuHcNe5aF9+yyYlkdkriN2v0YrMeonU/hg
UyUxTQLTzptubIYqzdR4mGQ9C4uNwR/59jX2KW9TJd1Ghm9ifCfuE64ypJAkfEF62327B2xSIz/K
ml07V1mzMh2s8bkMO3VnGxuTQ3h5GuQ6JRum2WFuF+Sl5m6I2MeFGmOnJkE+Lqy1O852yz41vleY
m3tZX5ppXRThDnxeUGKQJkzUEuvQTM3+LMokeL/X+5jOHPgS5AKaP/KsWfVH7ThCPZgFXsy08pwu
gBkC3vslBsIgwqdPo4AfyLLi8+qSPPrHxfFS9hsgEWB6g3sA+zRstjih4sxGnds7D8FOInyNUPrG
KhOA9BFgcYUtVvTUYhxJTz2/XHbdq8kyU8ZHKCeaoCsg9k8btGFCuGPc2fkuxR/cjDOh7kf97091
Juw0VKJCp3eUoNs/VxuUvFo1MiDKoMz2upoO+pWw6j23x4FTwdC1NXPRxcydVJYOjlPhW/LuecMO
LmAYTSOW3KeR3ohuR6Y2aZYpXv5YrI1TVKmaTobG9mUA96tR3EdBkst71EB8On1j7n33jQcL6Nnp
ED+EH67NDi038VmtzHQ9ptCjrLNrw+wHae/Z9QBwa1IBbgpnohsm/eijnhTpZiXc/u1Am+OIFVBv
UY35BzzUWwGo7JRlKq6tMo9dTslEIHW5AbPbRHw5F/7R2em6LDlZ/BboUkH4UsDSuWeurats08Rx
3bpzgqmN0r7rIcPeg21HfZtYoTRO+8LbVprNn0u09Znu4wni5I3z74b5XUXcfSgsbQiLAhw4fV90
PXdS1kwzLhGHrK7KBiSHPhzbunWeP59AcaxK/eplBXy8Sk22nzyQI+JzIfJnUyw8mFk6cO7VDjsg
MZFnLL1Xc1A0hMSIv1AJtpTXceYCQ1wo/+xG44xaIZ7TJMKXjsGyzfWQz2WVbJP2HfNpZr0mJqHO
VS9L3hCnC8Sa6qNyVOOckUT2UPvgVAs+H5XSWrgcs1jr4gsevHfGcuIH9O9AHE39L8WVegLTt67D
oShiVlrhHSsiRHcBAdWC+EBnbu0MfQH0y++CtnUlzmQvLoZEvYOZcy2og2xNseybL/7SkR8e3ZJB
8qJC0dJvl56gkzgYdYp5sE3v5VMREybzjFea+ZFBSFj1kjHamhAUU1sNV0L1t+4fscNIHMaGRNqV
+GpmxtAe6T8zxXyIR8E0ZyGTLHg2EykidofFU3D85zRT309VhqhhcQaAf9Jf5DWPM+HS/V62Jm+o
UtnhMWnXL6wCRJqIeZlN8uOvaQMzQ8C31RTvK0KmKUq2ANOAfe8sLWhUs0gQ8UYp5fVZx6UWrzR8
94FJDNfMKS2o8N6PMy8Hz6WXhBc3vcBloO+w1isU/hnantm8tx2ATPCCnr6TYAsLi3zCMLEhJ5RW
s7GAsGKcHrcSFP0zbu3Z/ygzUUr4YE/rIvZjrrAXwmkwDsD8wqmWapCUqwG62+meZ9ZmLlN5tad/
AyVro+M6ZnKfER/cZi6UZ0KZFyQHexmrWzbvGOo71QVFBLbj8ib1jpmjIUxiOJZDfSQxtjOgdOiO
LrZ3dqxMJO+3dk/RIo9ySPaMcXQMOLP1nV6KPW8379N7LJxubg2Ywd5KuGIqACR6I9C7PwQ7o1Np
mJ8j83cZKBPwyd4sBn/NHJbtFkt8UMLZ12R7HMP67ExJ7Gg/nR8TysIIkkA+kdu/i0Z9jZdLzX9Y
Cg1Av+8gYGz9T3p/WTIkR7SrUGVObGgI5ch44c1MlwqrYDPXZPy1RydndBYWJ4r4+K7Ft77gomd2
khPy6/576Z987+o662fJOuyqncLpFfB1WH/LKILcKJh1HV9DFM/lQIg2+IgFyIY5dBdIWv1jqZFO
/L0Zmx9hgL1I9u3f0BsnDdreS46CMA+P7Q7YotSyXwFNHRBuZYnjo1LCIBcvG1hGSdUwvlzWHoh7
JmcdnoeHefee71UoZQGKe3BqaEviupkB5/chV6ZjdsldYOeVp/OXv17TZPS6PtutrXPEHGXDUTbc
SY6A5rvmc3X22zCmRmYSR9oAwh4UtxxW7AE3OdDEwjsP9tbDzpeyaIYY1wo/pcNWLR229Kn4fi+O
+waQDQsK9zZUmP3YsSikLWkxZja22QmengjhCiaZd3r13bxcVwafg6Qvs5mV/4euAnS4CQSQMgJ6
8uX4RlawwC7M0PfWsLCihq9BlimUR3sRoPBkn46D5se7eHXasp+1a/RG9ALgap/eRiFpT6djTUgj
xiZ7kIbUEo99ue55/rmKfdPvbDTZYEnTbrPX9pwiZ0/VuHLiaMw5rL/P/PWCrTQM2oVHFpC02FkV
Z8hosVqULjYEXfdRiiFr5gILVTvMAhFK23/f/ZklrKvOwFd90lUcn14FS8bOpIfkqYCeo6kFCRG+
3ynbKObgEvTG2Thrka2waHsvBsTr3s2iNIglx7Y0RQHLymiidaCLGLJHh5wYWdqTUjEpS3FfZL0a
UZtTtAPp+/7QrDwS6hcVwEK/vARnl5XfWnFlSUvHfrSaTIdW6v3OGbqCiFc9S/vVUFu6uyQD4HqS
c3RuEpq2ufUOnlDQuTNQui8UN82Snm7rFXyvev2D8hwfNwhRA6YcTA224FL9VnXMoTZ7EEVT+Hab
00/xhP1yuYlHmEXg/H3OVADHzYt5rmb2OdpnPdBdcfp60J5tn3ZaK1XGdNvyhJQpsZzkhSEHWsqr
W5gR8Qwq2HKSQQI0nRO2DKCcorguB04tuGwNnIwS8UlB8pxNzdMULXNHIOTYMlRxa7zCemzAjAjM
YHFCetaKVv9IRTPi0Gq7lha/L+kaNGX9gMVaYEB41MB/R9zLCJxpto2VXdPBc/IYu57/rFwUw+45
F84FkSqOIkdJSvBIg32Lho2G7SHJmWS+ahyvNUvoxizbOk0/8ffCw/yTm85eMStmsbMm4+knjrlt
IiAgVhiJKUsVepJKUQKzGlXa9lsDvFtEgeqhZC2Rrkmtgs9zwlkL0Gkgc702tt/RZJO+yS4tKp75
XMrNUCZzkwONs0/a1iQ7GvQOP3KHBg8WNcQAa8T96ac+F8FPiZAltIHUiHpz839URqKEK53Bzaue
cwVcM+oZGk2cdJ7KpRzA/h/mVCW1Pzvocfkbipi/BzLXydbfB9GHjk50g//POKOq0m08/U5nkr1t
1f3LTFHDid3bt3CLuyZxqt+29+oakXxXF3PlxgYnmLh6ruqgLzj59d5M75E8tLlOlm0CzRw8pxYR
dw2OoprOt49vLe2MMxDU+aZ0F2SCOSxpMqG7j5L7LPT7zF5Qo/eEHQr+JjlVlzf1+/QsPzTKX+kP
3Wv/vcuuxklnd4TggCDsQf7eG9QwhNSY5oPwyrWeVxpbAcHrmX5ZQvHXYjb66e6GrBF4ciy7iTx2
SGNyY39C2Qa2KkezVQC04FMYELgSuwcEmzfyCjCa5QrhZK89D4RiC/gisblEbIrVNStFOzvxDv6t
NHApH36rS+BQGA1heXKyO/TQN5VvOuLA21HXkEYlwFE3Mx3eMLrnxMOuHVaBV5Q9fIjMZ2cKCuay
NhSpxQrPgnLUn6PfQfgsTLvp0GitiKvPbt7PTTnzDgIesm+IT6lei0Pww8pdgtyCTOBZQGhbVC9v
GYXLuT22YwFgA9Jf+dLSKnDeBEbrrVt0CBdL19twVxbiucBHRWXYTxYkGIiW02XP58sepjwZC0SO
W2785+jNxaA63mFGQmP0drl2/EpaqQ8o/yjKkkkap4rX4X97cbi8Zt1I3NI69gDGNRlYuVmNIAEG
+IcSAi8vV8XV/oZwyaFS+cUx1dW1kUep0g0NtmFYFYDE28il1Co/pR/Xju97V/4zkm5ClUgYAcVt
PuuYrZWmS8ItWyHpofhlCnUQz8xlcJ41ECXe1Qk7xpMAKmHfKHXDWywAHUYowSUWvfjxxe9cBa2Q
SmPgCrZSTPYRNBNgaaERoXi/e7MJ4R/gW4dOA/nHJcT939uUXnJBmcs4rqk6SPxhi/CFItN516JY
wBZqD/k23STlHJRMa+tFKiL4F536YI08FXc/hSVPgNtyF0SZmeBgL+nUlXdwhwZlUB+ocMpgHOko
FOeK1zPdJ1NDrwZ/kF9PjNFLyuL3PykC8Jz8kTxkGrsRJwee4M3g5XojQiAyAv/NbrI4MHoJ2GQk
4BLCFWGQa7hbSxAUm21CxfCXVD3h+SdmfSiO3sG/Fhz4Rf2dvmQDJvv4pDui6fUfCWz+wfDAfDEj
SMD3Kq5ErJU2/KkLV1O2OF8gAcWyqpujul+IhKEE7Sq/twfglQGeyqpxuuxfV2RclbucUFjvxDr7
e7fUXM1BTF4wNvyg5TscTzL/Te/FkV/JCojVj7VxcJq35jh+VPtwi5iOBzU8EjheGhpWZwCrqt7f
/W7QvIvQukYEgGslE8MITCthzrUAOBv8L3uL7QhQqIAzuvBB/GLc2YD9661Njghgmii3mTWz/ihf
LLwPJQwTQqPRy3TloteiQCFn85Aq18VsHvmAIuHoDn8MhFO3lhVIZ6a+mzy0oCWoE0Deyn3Qu30j
Xl7XCT2NAdoyy4hgEzHwWGHY1FHjxqynokQ/zFSbbBBeF/3cgqy2CKWvq/b0TNChXKdhhDFXGW9+
v/vIPjvMv9/q5uYxMKMprOvJwxN0dUWTxb9F7PYgkZApzsEp5zahycGTJA1aYFjsmcfaa34y4uzt
0hi4kjX4vY8CLA/UqozlUg3+x4JU6yWh0PrgI8rrIdvMpq20JxGp5hOd4fp1DsBQqwOlntKPa4Ao
avXHSnPbl3khRxvdCooCv8Z1ix7ZIXbQ4hU9U/rWI0j0sW3+yk3G1oGH3G0YwcfqxHNG9Y4/nAnC
3y6ngwJIRzRIiObazsQJgvSRMFq6bXb/06Nvlw8C8wnJU27z5w51i/GRLRd3AyFTWfflsDqfCaxv
JDX4ciFzfIVLzJN3CAxBpCjHuy4sBPKfcWo4AvsQDmqxEWaBtEkSNLmt1CYwCiP1dwC1jMN+9ckl
hVNAj1nub1mZLy2cvTFq4OXGBXM0mzPxHYvHXTzYhcxCvFwItOJ4HoAiv6vK/Y4P8JSySDmG7Nb1
Yw5v6lGK+TMJXzKhUjEni6t0IQ2eIEua6s/rNqrBd9E9hBZMCHNgNLHjL2ClSEv2a/dznY6Jgo2u
1Jhh6lvrTWamfGTSetEWZYwgtZjARgm+O+g6a9b/TVsQXVhOptDVoDsiMXjKvqPa8Fj3JtXMJlz2
yOR99F3ma+wOHZsJz6g1/HDM9ShvWW8AECZkN2ZcQyLXNJHmO/3ktENmJ0gEOCVzrTcZXQnZchmO
Xul/+f7yWdyzWh1cUBH8toRTfICC5i1qfZpw9AHHiETKH8EpnriP0yVvEV03J9zAkdC+D+YNA8jO
Jl2fKsYHbD2WK0uQNNCL+qYTjYjqUVRkjkwDPO256T8w4QGV7JZC0FjaE5E39Xdb7oT+bJIdHgMy
ffbab+nQsgaAGYHkDBw7zuc0UwsPNDEALQISij715SWeEZBAfuc2HDVZg3XkyatbUuZjjYHpKxsb
9FMVkegByLsk+kM7GogvTXLjgkw0DKrmndXfjH3oB9+boo6ZbqlJ56G09uQCnI6iDWqinwK9+oWi
Ww/TqrjpDQCb9+ZYe1EobQKgrT0A9Nx38IuXu8+K8127P9mi6nLuTecsc/YUZ2kzMXbJV+YI6im0
eJ1QRpzOWfiidnikrJy1AV8UX8nhy+uc15xQozb4ddkwXpbQeOqtwQsAi0OckqKrKroRP73Bc2tz
gAdXWyC6DPEkv8bc9X0l0WcMz6yR3nlxytgPBvFIn/0MY1CqMDOb+QL66IRzohN4wLpHtZ5odm8A
4Gukd/mr2DDekZKRURLYxsTQ/lj3G/PJzGWyy8d/d6oDdQ2MK1/zmg8CZnlXELZM3pCRBDF/VTU1
gjS1791YZ2EesYU+OgCWl0oKEH04YLLWCQsRabKfbjMHDpp8PseQZ8O6zR9cKqcpgLEVj2ejZTQw
uFr/BxrPfLA3LyKTM1PaUVMMwo3c2ox+DEvlY5D3jxauEzwSpDrODeL/8oEVd+Ef8Fg24lEOqEc6
QGEMdYBI/XekXwbEpO1jxXQMsqPXoCXId0pdRsj9A9lgjVE27I8XHOT+Q3Oqra28vO/Old+o+F0l
3U2mInyylHn5G8Olw/FdvTD5xzT+kKoLW2o3XH4mi8+PICi2fV2mcDrxAWGvd/2BKZdBNY4bJl9W
j8a8fHMMEjMOWpok+1uvzNCjcdOb7R88HjLiV1JXT0j2hj+HeWzDNya+AMRF4jXuSe9lLtuJaPJT
xMrdeJioxsZxbZRn4ie50ye3qvSI6NBm94xpZLqxZijFkxwhGFZ/eww5FEp1pVLfuY08yJTX8cLe
PA1eghmjwyunSBtisIXPt5EVYy7ZvHAr7Ij9GC0ZYfIEpqOrh4Wl9O6VN9xL0Nf5hxtMLMos2NAK
BF6TTloLGYdHxPn2c2NaCly8e0kbCLiw5bD4KPTTq0jW1d8coMlC5gtJgI8I5TBRBeXJ6/8XGxR6
N9xhjcLXoQqBq6ppF8nY+2n1wTrXjwFjHAW8xGgH+HNylseffVqeEkwwa++H5R+faq27ZmYusydY
oEYdCMtBcYSSMJKrqFWIPLDwai3KQeKyJbqZqOQZHW+DhHFM7rHihfBgTImPyX6tNoq8vebXDJS2
dxkkURIHTu11jdK1poNq3mMymnLu9Wiwyk+sP3mdRstv+TSGSX6GJB9seZIsHme4+Ldd8P4EQvKz
Eo/pnnmxcMlV+kkAjU8SmN7h/gY+zjbaHqvHOPaW/me7n37BMXjTCnTnoYP53cazz/9iMLadr7B5
o1dfd6puCHjlFPKDsOnn6Cy6HV+sJxpnVBRrrcBdBOHvLVcuU+RceGE2/eIsOCrCf//K0n+neZgq
tHT3p5WlqA/th8DZw162cjBmHo4qBmSVtA/elAbP8PPxg9UTeXcy8KbnKegK0kf8aKI1Iao6Axfo
hmY1HLWZmIX4IUJf40SrFRArArUw4E9heqz3WPorbMboUKDlgK06NIu1euScjm3q1lpLOrvuf7xl
fvZ9J2uvfd7Wc01PgfH/BC/Z8C1kpBfaL0LI3UhIe0E+6jhlgav9QakBPMoFhR/abD6q/10SuzQn
CJ4R3suP3S0DfdFZtlZZ5loCdwAkDNeJB491Ehl44jvWxHIxAzNLkVQS15kmMoRXQNwvncm2+Xic
HvDix4oZ7Zm2rutR5Zwb25OfmSRSKdVwHKftPILPFRBMI6C0yNG/nymOVE2pSN/7/xAUhoqlJNP2
pirSp7aIEIj84i7o9YlUf9dgcbYiBMfMsZXd6rB3Iv3xI/1tajKmVf3MuxvO64TRL2tEkKTEBqkG
5eCLH+UUqX3gQg+Edsc0vrxX9i4RGMzCBpXONSoC7O/mloVa823KNONOwVAcP1F+FZqgea/RGXXM
UEvmqMTFexZe7V1MdHoQYv7AnCJtFBW3TXN7ubYGAe5vFijidfAgI0vwm3qDmKCxpFL794MbKmBn
s++r+pPk3exgVphXVyqV8kYdxSgqFo+FRk7iJtxl3mGpaj0991sKhc2lxd59e9iTXz9O6MF0BBtN
LN0aFoeCIUprO4Vv0p86Dgz73VW5JXTT9bZoRgNBI/7IRHBE4WlgGYVIXKmxkRt35A+Q8TGcir8k
xXAdSiR/AFQPWpN619ex5YvZBobO/Su/p1Urv+0dX6ZaiO67DY0VrUJSGMn4aCHBIu6LRyVCuM8V
MwRRWtSecfWxtoUtW2tSd9QZDOLAUygLQs13dVORdPbUy3tC5Ap7QDf49p5J56/EhP3ePGOW+4Uk
qOqy0LLjaXgwuzNID7400Vd8u999EVANKkBkmoxll5G+v/etpNymXDPVP5YbQpZjCQ8P8jxuMZt1
Ihx6DCCo9iibv/sXdqL3o+nc7LfZWghexcpEH02uJ4CsDwK4E87vfHHvOtLfx/IZ/Nc95jTft3A7
igoo8/BT/Eh2qXFCPoHWpNQEq8KW+0XCsNxrE4oFbEASasXNwOoaEcqPihRLu5h/t/3LzeVL0cA7
hDhF5tuXRowT3D1MMAxWrbLIK3Zrf/TqbOGDbXmoIFw60opIExg6VTglrVN4o6/VR+JoVd+pPCok
ESBtHXrFAeVMBV6u9+dZpBA8xUb9KnYBDybABxp1TB5sAstSkYegR/Y3rOccrKjx0h+77qAFtbO1
sW9BPUta6sLjqWsG3RMoG9ASuu1cm9nBouXN6XjhOiI5BiCDUaG3fxtyH4YUzZsgNa8+edyIpRL6
GIBeSFDIzFhZuR2uHdgcr1/bSxgEG08484DGErJ2CEuuwAtGB/lZgVA31tPR+fv4g2RY0IpsH5bv
WhUacCWiQKRD5NgmFHM1tNqcMjJkbkiooErF5ITEFtgk9z97SbhD9i8nQ330QmWLYv9IAsiOOnTF
9VqJYjvbsvvmyVvF1fSEUqjpVgqRA8ciguAsovxy8C5D/STMrDWC6R9IjhMnFP0qz+l2Mh3sGZv+
w9NxKdeKyV4oit/m3qDQ+4j55+8Kc2aawfwdV1iBjpiOO3GfGj5aL5GZlmj+EuF1/ZwE3y4LGIZK
ran1SEyMzVemqkKyNdaGGRCBjY+3WZleFnWTWzzjw2gPFQNUd7I1qJyhIyladMTHziT+cmBM8sa+
ds8JPFIZrU65AHkt5o6ysi9BHS97K1fBAD83Ma7FJwhT0IrRcD7qBBOC8BrEIxcLvVV2ysACYOSb
l7E0V312wJ17jzIQWtUiCkVNbBdr/iFOdvv8dPRVuX1/Yej0MRATLz1WN1JwM9lKNZr0lBnZi2+c
JZpr6WghJr4j7Vn1fcco6h8eGQAw3idCT15Z4PmRQd9OThRcgPLAxcUj/F4W08nMIfoQBsE0MniW
W5kcbGOM22OMtiTJc0HA3hSCt8kEQ/z0jghYIxa0xSq8Yrun6jGG4p5WMX8/fkUfNCQVu0Yx8ck3
yjdwrUcZ1AwV4bbs6GXHqkPhPt+a3AuDVLurGKspMNpuadlmK3fPsv7Sxp3LRuLSBFziiYKqxnZS
SQkJWIUQRWDqSH3/kXl3qTMPr+LtjdJwZj65Qo5FvI5vXQ78+zu7IBqa2bBuhmbjjLGQUKeiqALw
BQiAhx2DdKdqZQtBVBH/WI5yj8Q6qhW/b5x2dihnBCUD60LqORDwGYlKwXxxClarbrS+oZf+jQyn
p6xejSPEq4KzhT5Su4XPs3xEvLb5oCMrFYHYjdo9BcA8rcRDr5t9DErdL5OHSsLepooZWUdSANnj
4/uVGeJ5LngfxwHxUtFOK3mBODuBZ6bFmz+MXhOXvW6jOgPQCLf1m4Zs6aRcfyJ+mToXwHEb8J6/
Jvc7oEHkp042EXCd2AlnnsEo+txC1IdY0xFMIXlxY5LzBekJ/UVwnYiDOLm4UCCRZIedrMIGTa7n
YOQmVLoFkMCaCCF9ooDWX4P+PGhLe8doTKZXX8wmwOjORzTysD6eacvBCUqo8ytwYAt+p5oHVcFi
uqx19smd/E15qcx4sqvakidegrYixne5O5Pb9Etrd8dLy0Wxg7dshxz4J9I+jSTmGrAo7jFFda70
8QQCjMQnjfY7tXu1ksp/AjyiIR5WkvDOb82YJBJo59z/bRAd8TP5NXYSxZUq8WyGUCbYfZyh2/5Y
G3dquHw3qX+ybj1Pl+zfL6BKSHBpnsoy1hUEpy2Kla4IvIqMYd6SEYLd027tV0JG5qAE27UZOrpO
tNnLf700jqkTRrIjzxvvcf6CL/Yd6TbGtVHBeo20J+ZsRaSESUEFeWj+f9jiZZcAnYc5EoQR0OBA
nQVYTC1gg8DWxV0sfS0BZASyUWMDny4ORrX5m56pso5i3eyCMyyGqNYVbb/vutlE+xTpNCOqHdrM
YleDAU6Q22D50/brn0qfN8n0+0Z8YxI3bsY/w/1vHtvJ3j9cwm2tTw0/dx3AGWcA5pngBrem7NuP
Ey/rVAlIjmJTvUpt4LHDrAq9OsRAM8Fjwh4YQtr3K+gWU/XNX8HnTpW/iu/rGtrffq2C55ReKI6I
62weyWrxBNfqK3vdKyTsHaci4JcgLfKoxToBp5ZNTIUtJnhb01hdRpJjt6DK5zmXIgKY+0+I8spR
+/3K9CCm1IND2hB/CHSvVV4WCz7FZRREqLqZo62Spwkc/TaVFrPoZXo7kBcHntSt8WFCDZm59K7X
nc5oHcnvtPiz1vIaS/J7QaexDG3FsBlRc5m4YILoAJdMdGRepe5Tifbzii0VJEm8KcglmXKw+vmt
moL9jN4jgc2MxQWlDps2oBaBNN6WCYCtBlpdhzzIhmjdIofukaLu/fzOEBKUycPFDNth4sux2GAC
3T8hEc7/qEhE4/mIAj9bPTHCJHake3Lo8dLXk81NNO/G3xVM9LPDdmX289Z0HCNJe6iAwq3O7iHp
GiDEMHjgx7PzbFdznzlo2fpdJYu6nLyMlNuvV3IxLlDh1UOMPXs1qZGplHI+O4nVfU3I7Mzqtt9O
J+t2IpTW40/PhIOzL0XiTnvHCzKfJT9JiAKE8MiZ6f1w9XYgSW7nkvOZyaJM82vJ9J/jltjWQxwf
gCQP1qpRRA0bCVVmvAH7C1pIhgD5j1oC4Juk0jGzg7SHzqWTJYITU5cFIRnd5s1waWAhHzmu6Nu8
7M6olHSFoI7wkFlOnsw1sqcBrJBo2DBrMSdtMKjT3OkJt5VLlG9wmBaoGPFZa5NceL5hVh6vuWKU
FWKeAvTLJc4VyZ7s9LFUo8EiljimEVPLFYecRVQRfyrZ95+mRrURe6jUliCtgsvWob5WkI32SlPs
eEe45Po2OKnfVhzgdQrYoY3GNXOk3r5SrYvqr3u9x6DPPYV4gtyre5te9jja8tKswvHekgkProrb
dkvXzWE9c7a6b59rW+7axuoO80iWPm+tR791f37yUWRqOQi3yGnWXMSouMGmmStK2+iUft6HQsWt
D+m22NjoOER4GHYxpG015qiuRkCl1J6PDNq5e9Zk/yaQZ7dRv5TYn1kcpPY4ZEJTfF6HRK2hX2VK
N7smBxpIF5c0Kf57C9zBtaqIf8jaBM0q9b8wnad2bTnt6Y/BPj37/G6G4Fpk85RjIBoeoddp24J8
4rZqpB5IIsz4yTX9rzac97DCOjaaPBgOp1J8qWeUK6hIK7WfK70hGs7pB3/K/vB1CFTub4WweBq1
KtwYjaRyIrq0LcFO/WY1jF9FmfqoXrwDL5y3udcBqzgnwZgXP3GsBopr6knEObDuNuwaSvUWY8tN
kOQAIaTBy0u4+syt0iIiqjB0GqGNUqKGqyiPFEwWxot7x0HJZ32yvpyz2XIMQ10rCejFUYvwGuik
7Pj5LKBfght2xcKZeMQO2oKpqqlx6w+0QH8m+L2BjSqYsKi2gxg6W/xzDbgmIjuSQRjHTSxxZhcT
L2xsf3GYe5BVdAdNhAcuCGYRAjBLy0XpX3TN6twgGWZGlFxnqnzPvRMBmCX/MWt00MXZajZijYge
SSW+imQKRuRtBbGaq7K1HdCinPBWD8pDSOcr7c3hb1kFFhYQ72RTelTobsfYWcO6xnExJx2P2muA
znhijT4WdWyrcc55sKHCR5aWCIE0djux6A7ADgpKZFD5+U/zYBl+jlt+fgcYJT7sln92VuBwzNC3
3+D6erPFtSBvo518uuuAe5YfVCujWqgbSAQFj4tD+36IBFbbyHjIUCoUiE0V37jHW1nyCF2Bje2/
ON4I2cAnDr+53y2ocz8A+ERmOLu2DD+FGiMRzq1cwoJBkRvljUhCIjpQv/ZmL0eXEw3KGgme4gPO
Eo4ar7CUNbCA/090dgRF41ZqpLhVVPdaY+/1VbivWBOPYpnlP1FP1dzpbTVC5MwBtii1Rt8t3Sal
K8D277zyIMfvvzJS2ThaDBgOPd/FNvE9smT0B+EiXyle1qfVNv5AnghV8SVXjb95OdVZ+d/PDoSh
RTm63aDp5v4lpzTbo6W2B/evQHrDbgT0XKCsvBh5t5WAn2m+9dunAlgU04s6XahTqdM7sg8kL4iy
hpZ5r5KxHCPW2kMcr/ZqEJjcYwnaKU2+PTsupKHd5IqIXIR7Nkby/6Xco50pskyF68uhJ8CR7mOO
S6q05Oz1do5kI/LzXKlRgCEVuadHqRmxOCLEWqtZHye01t9XpTTPBbRqzYh/hlnq1WlNHIqh59Ot
GkxXcK4tAoPnyjqvtSDqD1DrIsuUSJxkWduD0D0V4ahztYlBPGEmHyNHJUCVBaHZxnKA0ytcS8lk
sR6eK3qQJNwQCClbG1BHdEy2lwsR+dBGxt8kcc2DzEHj5hRKK33PyvgD+wZnIjOGftGUBRQ6yQc4
VCLaMdrfuaVOBC7ZShClYW4iNw8upInhMzBP7ENk5SfE3T+/fxJ976QSII7TbRmvvbWsCpdahvXF
oi4qG5IAJ1VK7i16IjJ+HTyrJrrStcAics8IHGzl3KVVw9WSYIz22BCgDugJsZ4K7ZXOXYnS3q2P
C920XdDWCaZlGRT9p0J43vlEhm50eAlqwvtp9jcBaNuiQC93vsnJQDYEjFyB/ZYgh9HbuIlOkv2d
D7dYeHlIgHECTtjNtgp1oBxTvRntBqTENv/SXvg5xtRFjqYj0yiHMIL0O2Jw6h98HrRnqj4fEx+l
tNo41sMgJY5D1ELJZJey2H/bz3IifhaT546qAAvrsP5+H6+Ql9j/7cRH5Y/P89w3k/7Fk7thOu2A
GU/oj9M1TwhTWd5jjs21pHdnTSmTweEJKXCt+ZyC6PfHkdKlUg+Cey7UgJ16VyNsC6JL3tCJYQ81
6mqN+OzdsB77+4J9jgMNJHlAEji2uDChX5sgId/5GfG0mcQ9xQPRNCYbY+BkNDuSSodPtWU170PD
UF9X4AwleMbqOu3OHpUym+6LImXSB4gvaVNh7+OgF7d4DBw7DMvENBtzeeOT3DoTnZkHI+iZUvz+
u/fAkSB4djwrlqXTOIUAs2rubaHlX7oyAe7e9WpLBP2gqr9DKffcIOBc3I/rOz0FcCuShNxugCRd
hggayDu2cDmjBZqjnuUbcFAJqHHbMRe7quseQP4T3AVxQvQvzPhGV5OgFeh6JOmCxRQeSyGYi8LX
we3umj7T3hBHjhCn5Tg8/Momcw1RIBTVH0++6H/Al1gDYKTKx4M0evZHPRvw11mhmVx0CUd/vkXv
lGSIT9jcvH0ReTIfvneEJusk8bOC3G3P6Av+JfBlvLHy89KvmvxlfaRphS742y3CEOSzy8mTXobO
MRSxPHeXS6tm0y9COVVzdmshYYWsLddFnJaDwYfI8v7xM06vvBCq2sPumaPeMHVO5FhtiFRM32Jr
1hckg1MNdVH4gWI4dEGQ+bZffs3mgbmnIdPL1hEb2AUVNEf0qT14HE+/rVQA3wDQnSc5WUq6PYkC
1vrxO8gvB7RFfXNwxSOV5hJYZBQzN82KPFhYtX6ZWdcdXA62F6I/bGY/PfdHaYDixykfMPBaJbB8
KR3vPPEPc3s+A+G2WChKacIZ0GwluM0dUOD1ny3ZtTpvey7q3H/7JHA8hDWU8MFKlWu4AHdxy8zE
s2stJ+rILbZjbpZmMBNG7f9C/yQM85JNY5umLrQ+q5s6DqyUgluls+3NUNJJEaInBie+I7z9Hkv3
f20H6t3s0k1bU0P5xRPFb3ArGZlk7FcIeZpRXZgxCHzIQiCuhH4z58/6khRGuxSnJTVQfLiUxTUm
yA4vGaTgrATPgv94w5aOpPRhpseo8SPK4hzs/46RCG/QZobVAArnPUucwL4lZURLnV0UtpYCCtwu
jdtzBzWQAiX6U4PucIQsvkYSD0npqoWPpjkqBdWSJ72XyKweFvT6UELa4af9Mms/EEOnh70NkuDt
f5zHZwt6VRh6eocFkvuNkBN3NHAgS0xN2E9AoiE3coR/QNHHlNO7fuxIHVLkSqwGdwTvp6xfqkBz
vVfVX9I7N0QEYr5IXFmK2kEuv3vulcismsAYj2UQtbXWSlOr5lI4QLIzcA1HoDfbwVvvK/PQ02UP
fuJUg47d3SVbZF9eK4go+UyPvpUBZ8M2mStE6xtlHC8Pqk1SNSnOT/P9BMkdHraFnhOXK+2sDzDI
hxBDV2Hr2FjanKCEvbxUWsF+0BWdsXzqr9XtYqDFhwbNjU2Fc6Z3vI8Fe+1dDWbEpzvaZjF/00uA
sFsvGZ5b2NvjM4FIheVNl50PhXIqg018jqCBcWMm8GQGO5LZ4/sYWy14SacrDxklV1J7LCIV4KkR
kxU0zjoolQnb3kQv90IyPkYUrc+7b+y0WYcjUfMvXdhaXDq0QldM+hzM6N090eCiD+1c5SIISh4Z
ovcZtYcWcLy6U89ASSoJ/COi0ttdIWlu3dXCD5cKC0uJHUeaxTsmGIHSwFjG+zkjHF2gRYVedAnl
bI9dKi14inYtZEoKTE7BuU6fzs0/xgVFlAU+5FuxUmcNHqt+tQvwoG0rGuFCbY9lVx3wl5aRiK9h
sXZx6PAwUdzHqgH6kmy9f4CyyFF5axbaYq4Ojua/8xHioRdjIqg3cRlfC34W7HWL+Aop0hyR8inu
6W3WC04K1l3oSkA500/K0UrjLB2C78rtC1zjpqdWDhKKp8xtKOCW5Z0LnKqBLz3/hALhqIJRW6pS
QQYIAWA3VKpbkbeVVirjVKgZR1iqeqkrdw1K8v0KUkmOqcK3BmdVJYJ3/nN8uOnoPwFqF5gkwA7G
SjI3gIAanDj9cebi+ysqDrAHcTtalI97xI+beyQkPwZfzxGvYf+pF+3Z4H9shpCRBs9wjOTbsO37
h1yxAd9MtjPNSO/t5z6OCm9T5TIIWnSvT2lzY2UUkh1+s89tyX84S7q2DNHx6A5uW/1TL+6NLzTz
h/tF6MPnk53i9Qis7Fpc9SfdfbObkEKS+Q///hcK0tA2xQinfhzEmH3dvcfxddLz/pGvV1SzrqqK
Wd6WWTA3F1e/qhg4lKHO6cIlSikbxr0dZjnYFWfdTyRayj7MPAjow/bDgpI0shLXa8dBFWPnD+cD
UWdx89i+bHX01LqkcEgmyzNDrO3ALMpHBwgOrdHnedZ5a2BlaCt4F+iBbEoWcN0Oea9bjiRGuHG3
oMhJx3NU0Dyw83o/gi8pQ3DzY1IumXBULtOE2pm5yn1IMIzt0WPb+hTGXtH7Gl/dqKzKvyVzqRHS
uBbPCJLDDNtRd3DuzWLsxwSSoXHiAHXqWuozodqQwO+jEDxdSrgPx6v+7TTHc0yFOIF31cuW9BDY
og0o5RIGIFxk+lUAxG0/PNrsZEM3q1icpsnt+JcCQibweHpvS1ubvzbjqzwrK4qJO7WPJofzO3RY
9wKmS3j5r4xQjnFDOsW1kte5NhAeyD4CX6lDn8DYswBWnD7hR79ui/P5+g0cLs53bSRTugVz63Me
YiQ3/90qzAj8q2bPrXsII9t6s8vVSRZkvdsPjtxsDsNA0VMOjPZ5TLz958tVaLSLlGHW8U3FEOJA
UHP7udPvsbX/GdHsur75inx8y5qfPR6Jn78LYD2F9ABhtrcKKZiAUBDeL0dWGUa1+9FZiRhUjDns
sP79qCBVOx1de6MdTu8JLUxYSnS09VOqH7/7blR9/aUiXajNS3lrrGgDFZV/ry5RLVN7dkU9y0vU
RqF1+9tbDyDLzHDBr1ST8FVPN5jmzBYGz55MVrpJcL0oSYWd5ded6VUIai6qhm247vQXcIF3BAxS
7UJIOfeEXlXVB1gNYj4PfEhth+cl3UFlny0AT+gMfL/EDGn/3m1DIzp7XvTkEXzR4mZtRt2FG08l
JgEIsHcKbD72cF4Uo7aFq8aAOPcNqoMdzFtUtpuHQ/oSlUZapSnGhCMXVXRPxPssK7SCRLIxj5l+
pvyZZe/ZlMB6sLqjn4Ue2AIwnwU+51QOg7eSuNefOz0ax48/XKpJN2ONMOunSWiV8AuMUpUe3zt9
fSXvjEVGQ/ScityRBxszi6L5WUrCBfDr1AEUyzvahYkTLQ+Yf9V+bl2qCIcRWCW3pNfU4ZiM4MUU
WDJ7sooLalDPJRPAx0SXnq2xQDsjykVpdehxeFUtaWfgOONvDnRTN/X/YUJZyLGDyCFHDCbXnVTN
cv3+tRkzFMtFwoQgNWvO0/ZLb4m7gRXvOER1VJSUsRZau9qJAlP+zGN7VFfQy08DpmZqZWCMjwoV
sAgCdsaEEh4D5Nwbvi+Mkkssutjd3VR1IYUeZScT5jYwYJ+Q78qjSa+BBxpyJMr6utbgogfgVDC0
ydQYiRxdh0t9DE5sGqLctCW21DQxLWWYWVzNQk9engRk14eANRywJBXIHNxOv8frzy47Pv6MMhNP
EiS6ezVkBhSZqPGEkRyqsRSa1Y++AbL9ivKLuYMPY+PZwtrOzzdgouh/9LiggQ7KaqBT9tQjIZSa
tQrjqe4smDZEk9Hbx8Cso6ay2Xup1PsNxjMNLk2jkbT58v/25zY2hWNFaBD6MpmCQr3s24iNtGOe
kj45L/VBmFf8LuXynzcyh5ZMMjZuSU8QcO/vHb5pLTLpN3FDqY2tZgohycuVGvV84D0z++4a0Z9m
enZrL8tM2eMHH/wYhMYf6Y8H76t1PZveIl6eClhEEB2x4mREnjOtvCrnOQ1IOCOXV1fMfzqfgc5H
c4SOzNwKS8byc7VH8FvTxVentJCZn/npqN35tcg6H1N5avzY++jHIih7xwZMm7sR4zeC5aJ7NrPU
OYCyurVPPSafP7LGTPjb+bvWEoLtdocdemdmgTnaqDTH5q2+vldl3uDaqwN+P4ZNWgda/Ih0rOgA
TdDnPMdtTwVjjwMKrO+90eivKfyFzVWnExffG5f6WJ+JzX1G2ER3x9nSx5LRQ3rFI8Pqowosz3pd
GFmtzczJWYYibtp/bWyzNJkdicVLTWhUrySbiITQFZmjOs+Pyoi3G/FjU1koGg1ZRYFaQVtW6Zt6
9lRc/THVo+thkT6XzRzexWN3UGI1zFyKZoHW7v1NvPyMy1lfyEmOPI/sMkV3EtmZfrD5BhBhJjWN
aViGY6p7yw0IRN5V4aECjccWnVuEAxs3CrpfPiHl7rcwepvfjMqF/e9sdAuBv9hRRHN3A5GyPxcq
ABxsCP8duzMczKxptztTV375CjNacj5iqCKi7HUnDcZDxBxBBjNQYEQbbYkiSmPrXXcBwH/Dy8by
7kA6yrNUL3SXdgnr0yzj/XHcoeShjRysNcXRRTg5szDFeTXAjMEAASEA6HZ+d4+V31wimCyzzxv2
2jW0hlI0WEBXv87xl0kq94SqdU6/rTY/oyLbCifag5a2ECYYyl8go4cWGNTJhvs1vktbiQPbsC/o
ibNuO98WP3OqZMudU2qgN/UK8iCkcCUK4wP4uTxRB6klbN9om1iQR/Vqyn/KJG9dZzVsOtXBGdda
4wkD2r4eWBD0upA2ZW1ov5B+lpb3olBl6OVCgBKFu9sVcZLzhaNot1rm/lK8x2Ys2UKJgYFYzI4B
zJ2dyQa9EaVo9cu1zwYthyOM4/pkBIonw634k2Wj7Ea6nfVXD1DhXrkkJ9Owl/qT5f7jZi2qoxCN
zAAkOcMIlCdLj2KPE6ECtTKEtA0FqKXQihMHTTWzC99Gzica3oph7jb7JE6V0giuhB07DOc6kUqE
y1YgClGpikepNA5QsGhv20ZgvZKbD45el4tjYmFDE9Ke9k8OBKpCIiRjAW9wL98FAmgp407AVouE
0xUcm2Qzli/f3H+m8cWVt1UbobsFb0lt1zWOuMb/DXxdYjFW++KhDEb8opmsc33CClGFsTCXGYTf
SRYUlpViigz8l3tyZzt9h1U8s1YoU1KV9/uKDtrz30nkAwKOEkYhYYCYFdGkXX6q46XbKs5vikd7
WgGlH0Dpz51GYVb1OSRHrw+K6JSfzpa+sPACr/ED8QRMgbf1SqxdqKJltM7S0KMK0I59oE0lVDGu
5BgS2Huec0a3UHssbX+3xr6gCAes0+AD9J8vNRrBVcHloEi/7HF0PfLEaY3GP280iWoSYElUyb32
/2IR7p/+ykHpi2flwX7HBAaFKE5y2kqog5Hh7TmFsfjxZlRrRR3gbnedL5BTXFPYEuCL6wxuRyib
K4MRmvqTuMmE/xIMmzZtOHGvIXRQ+C0u+UfK4OQ0Lj38R1fe/92b6ygXhdRRtgCitvVWnoDpK1H6
uqvbY4D/7hgCdzaTk4FdJ+RAazKqN3FS9PFwYo0tIlvHmGw0r1JWeK1pAld5Is+OG9jXPZ6ik3xC
mFMUu+rkVAmBTpik0QWCCA5Noi5997D8PLK4cV99u6y+BNskqDswwQWxQodrRNlCFiAjMpzRKmjS
GF05Ga6rLDkjF82BViBr8uAiWZSts/tfnrk0pyDEM9wLqzY8GD/xqr4nFoJUAD89U9tT4w55ssPm
chsyPXn7ipmhtekfT0n3dh/seR64ZRhoAqqep0nGoRnNPJmJOXqECHSsnEa29FOhbBvxAuL0kE4i
uACy8N1gd+r0LcJQ4bjuBUm3gTkKD9aw2D6kbaxDawhC+y4h1IolXI9NEdRqO9t8udTiS8WxEmtL
BuMfiF5nKtglrVtOEv54/xzgu7XKr0ScBf4ldRN0D2XYjWVspwjI+l6Xugut8SGzq+qjroXXms83
NCYKXHqvtEFP5MIxVa7bGpvIGibRdvsOlBSE70oM7iXxjB4DvTpMmYxrQ9dArTWVuFVEw+WMvprm
mMG7ZqEFlqN9Y6WSYNtIsl9rX437JPIIpQHh0jB96v6waEWue32/4tpWDDDomCizbcnfQwJInFfm
feIHjQqn0IhLF35viwxQofQ8EXhsp8WLATK++htVsoXuTPZsd+F3npK3eEUIHKSO8EigekjjApB7
0rmK/l+MjjBUdOWjep5QZ5hHUEvfXd9dGFBmaq4Ht+/4kpkgVVZ0z2TElwphVueINokClHXcnjcM
pyr5lJM1KC8Ryws64odgAo3cuLwjvr3MNnyRJBE8FN39rM7jzA1ewpMmr65MO4jKPc3BYYFL+waG
Cq8tCVaDnKcZeluvN6cR92RrcOcvlQpktLyDKFu8L0r/3yw4rx+B25zuRiFr9IdGcD7QGVBqqp2c
a8Rhe+0MTdOsJIYUHLK+2U+TbZFBaIehCWSUFKvaHXJsDcRYJe+rnqUVlFGi+N/j72OFHsUKZDIc
9kUyFuva4/j3llgtpLTxpE8JPgnsZjEaQI4K3yOjeJQLpAOwhHblwIHKDL5ujOl0+6PB+Y7/Ap7+
Fb6wH+6bYmKjX9d9QBGjL5Lx5mUh6m5ioLB8foMlPH21LjOo4Ph3ax5XbHrE1ia14ssgpThIcFYG
s84H3smC9SoAw/2LQZvNxUDesajhzHNjQ5dGVsZ456tNNNfvO6CdDUHed+HKnaLIkiEqL2STPPAB
f5o0NpMNfhbBwb3QL5GArSKG14B3kznlf4u/kE8N4gS6BicJjoqCgeAxb8ECxvfDClko8iUeVCOB
tdGj6H77iOoRWMYVEzADeu/2lb16+SrkhuXH360Kuj2kTMhC6MTkMEy00mFnvu3/G6NLfh+TOTXu
RPGedQMDwPDhsIeafRp0XyR9XMg5dxMtQbIPi2Bh/stbuVh2TiDT0yWwERVi19hhzY75WA6RxPPC
jcf+xFGUGHo8Mm3ICk81miKsE/kbhT3ZcRf66a1V+fSkiyh8gwRWzOHJ5FVv7DW/QGOCdzUZVY+R
D8q/rT0/0DDwzsswr9jShBj64z/uBR1Obe76FIHjFnaY6wuUfzynuPBILbAc39AmUsQLffWqGMUh
Ep/6x++iULqA0u2wRfjxLRb7AyQHTI1zPf7hl0WgwvZwxJ7T4rENJA/RG6iqS7n5ZGUEbDfCgGHy
dSOIQbmlus7nFlzXHQ05yJx81FwTMs+eP/NaDfg8bjzR0FCWHyqi+Ye+b3xzTC1ySI+lZ0PxyxoF
k5nBdlalrs+0hxYbXyzgre7hLjqqtRTax7n/KwPnUl53O/7VXnucraz86GJ0uR4ecGRnTEl6CpmU
6qG345Ao5G/1Dl9a5f1x2EINRH5SzgWrunoYXj98vKQvaG5PnAC5XcTMLr/nyFEhwHooMM/RQ1Q/
uVUFfEQyDXaL+t76DiQE4dnCxiT/0t3ZOn/N2q+SmMKPYRu0mhHoZHG/r3VRJ/I9IvLFglhRajvJ
EnUuo34ZapvrGowEZlfWb9VuTn/NXunX5fKEX4RMSsR1k2PppGW90UkwveM/P154Y5bpvkf4kE+0
mRJw7eilvXtgjXHeyMONfq9bP0PlxswqmzPWioPr4Rfc5qNHR/DTAXga2SrsKZnb9onqJvSNeyRb
FF8sM2O4b6qMKk4AYcctpw+zB2IZ+gWTwKR1lvQGam7lpz61RHsWr+XY0RqIPlcPqXBVIlvAaTig
cVRvqi2FkHAtyOnUx2puWYchsUUwMkT8+h4Dl6jX/sk4r0heaAxPknfgtG+aKx0p/THt94skK0hf
ovVQPCmxUsomBBxkTrm2xDKyOATYMvB+noPbaiUjxl/Hr9SIlbp2OtYK4KF+VTVbHnCODPMLumbC
QQ8XhulbiAXDkWboxEJX1MpzE4B1+t7XSymfOvuAMrj5fraMZH2jtZMg7lEWNMOrrTV0rvs+1r9P
MRMVdq0VhBkJSBFykzcJhRJec+sCgJPMly5uV/ahYVR3+1ZgCACTnzuX/6QQ4WE6UAftiDrLD7jA
7MtI0VyDRfRxKzNd336wg7debEjJa54NBJ3x7T9rtJbf2e2JSW4lFTVtUyWQNp/9Vp6yn+X0v8ac
z5MHWVAL4ZQKt9BauX3QlO5Z6SxhKakEZPqWtDPXI0Y4JoThMiclffwFzzL59XF6x3J2Rnd69UZr
M+WwKgR6IFoNONexUZ+9aczR2pCYGpF7YjZwDSsYY98f/Nkdgot6HRDzxNZ/1IGW1kzaCUb8kHIh
4jC8evBn+qJlobKy7TyP9YnhvYcjNaXcX376zLg3ZWFrGPTo9oYQdwvoMmJgOy1OMbdQKLl8woFf
n6/xpfPhTvKOuGVAQrio7jX62dGOg0K//LuY3Xf9I+/wY9ay2HogCVKtxlb7BoZBtgJjJFH3y+Gx
xUP35Xh9ZMC1btFp64mD1c9VIiaWyWO+nfzeBjBOJIpgGournaAOTVa3l3I1J4D0LM1rhVcpRpG2
BJtCvyh7jk770j1JhUW31T2PVHp/TEspdL3QNYjJEISM4hcMZMiPwMQMg30BwRjv9JbHXAIjFCMJ
o7qqwyYo6z1H2GVAwvcgc6c3xGzY7qphWu9fdBdra0/ni2wV/Nq3inupI+diWEvREBQID2eF3mvb
qBOz7M8RfwBmPYy0gknBSvrwZdedGUw6QsqsFZdhrvyzFBqgskS52rbaOTkkEzV78JWNOB4aUNnb
zn0Sl9grduJFAekmTFtObtGkpZhpafNdVAZYl2xjnU0lIlqZufoFcVuGheg54KQGFTXEEDf9/AcN
itsmUr7M0WkO0jY6Qzpr/3MLz3fv8LM+MsPCmqS021EtTSAbKIjEh/4AqW+z8q+U4GV0h4n1VOVE
w2qk2IYLQ//ymkq8WjvXyt44Jg2u+3b/52cCm5ZDiMaMEdb2WldoZ7RFMsf+mV/m2DgZfdzAxHed
T2dsdbZyECvShTcJzg6+sUPwQJg/PDXNSlAtXdetnWoxCjHfFyofiQsg60S4xJJ/BjbvBU6+0qNc
LgkfbEEDQIETVglUxGU1E2WqRss0WPfuCf4uAvlyFF4aLsyHF5E4Ov7zStQVoHz8il5DWQIH9o7s
/cphyKaGI5e4ef8ACi/hunU8ReHu8sDE1qOLJDGVLW5eHCJAQ2KL9B1gZKHAL+X7PizivcMCdCYf
W6WxdhZ8N5addWwtwKqzqK1iCioz8oLeuU5V0HJt/vSDRJhZ8oS9AYzj6cWUaEYVfJZBe1carh8k
QM5kwpZNARAUjzM84REjaqWoF9vf/R2MAhCkce4f/l6Y9hbv7ootLQBD5TZ1noRdLrFd4tBgsCQZ
Y8V8aA332zFxqJ8cKT+4TU+dzjC/bcZVKuG1yAHYY2d2GJPW4+SPBgGMlIk7xiOgGX3F9XSOdNg0
Xhz1l2qcT/q1I+5TwtStKuIA8+Lz/d6AQfaI9MJ+71ZgMaXd7xTK+fyKC6eWzjvk2iAUPS8QioMR
RAV18Lml7Urw2WAhytqJ+bwOu5g57/y9HlhW1kXIRj+0p6+rdUXL+yZP4LyI/AP+jfv23aPKUuaQ
GM3NqtewMz9NOUyuyu9FvulPCx1nil72700Yl33oxp/HWiwmz9QsoNZrMyfNgcyLduqkUUEcK7vj
0QSQ+mIU5KAwJ9HvXgs3TDgH3tSXrAJszJO9Kb8mmFvfQ/64tAI6EdLeoDccDrVItF2lH0B3Lqsj
cDrSQPX/SeaYR8OGohFglxx9UoeR2T1G01I59g0f1ZtkDucbxucThNiGEJg+fCYBPfIfVwkXvYwi
o9YNKsNIR0/hyA39x7MJpNgi8bSe5SuWkFky8EXLPVTUz8WDxyF3bwspWC+pq25k94kqCqhOqWzQ
8BAtrcX27XY6pE+Y93TzHNMUgOn5Oj+M5sI/SxgFZpvWOfEKpPdLatLLGLJpINkBS4v6l0iV5eP8
qg8h4V6Kp2otlc8qdU1a0qIWYW10yRWoMEy1A6y6xr60pw4vHykqG1JNaYAlTKTu8ZM+OpkxILwD
sGY9Cnq8naczlxL4sr2QAnympJhS25dehiQBwdPaYyPs15CcJyU6jChyy4g72muIsapz1nhWxbtS
J6hSEHyCqd2nvthfOKQE/PvsbMST8TbskUi/V0cbbTN8964+SHhKD6tfaG2n3VzaV0uCxU+GjLsP
n49Zmsaqh2fSNgRcvMto5CdKjBxB/EpPC534gVX+x7BF4brt2jgcM/a7GmV5d8c60LcIDqEoSomb
wv0+OiKyOVHORQfHvW6VPCZD+t328v3ytK0gzYFXPdsChHWMs3XEIAXJTlGQscei1Ck5fYR8xPeB
z3Rm5O4NIOq7eAjQ/htEl7KU8Pj9OiOSfOddRSI2CVXiEmziYkWq1Gx1Qw0542aiJ04Naam8VbfC
8BhqaVFPc614blrdynP7v8RkN/T2aHFzK+ejoqFwzCV17w4iRxLMn7/ycNxVpLGq3zzpYxgaqhjq
uBgp4nRtDm3up2PgEQNnsKvPyx4ptqi6X+cvD2j4uBbJMzxmj2uGxo06I/TfZ8Y0tCTSHmbytntV
AwsASD6JqLx0soPUXTdWmi2PINA9CrnePI+UTfBq9YcLEASL7scQWrLDDQgHYLQN28Ceddup/Gu2
pfDePJs0a7+DSpQWe2f3BHu6+c4ZhvDcbwNT2LCvZO0htVVGU0MPu5S9I52s+nRxtQzw3CH5cBY6
MoOZdvaUsSK9wtTpMCoVs0P/Pepd9InTDLsJaETTJmRH6AIn/39q3AaqGcL+drNzOAItgnsJ9CQn
drCtDHJazcrPz6NCm81U6ghbee0vy7rlCTJHZ9GgrSomlqEFJIlYQNOD25H7ehWp+lXhVGUUOfLB
bP+S/sjpgdC20VdcHrcl+Wvp5+j1Nwu87TahhIbVQ65iB8sJ7ahpY8zRuxKwvDDjHcHsnONu//eP
litlZZu9og2U7opmvCv7dGKZo9rxTeBYEOIVtsNZF0+CF5kxOhoHYeuAaRnCSmFnz+RT5AoL19c9
YZKdB5aHNUiAOAIiXOpe8GypTISbNlKFRupESLcsEL4bH1s/lQQJrt1sywlPQbjjeuCob2qNAX0B
Y9+roHnQJQeXRNA6vjbNSj/AYSctmJOu0aEZM0SHHjN6pDIYZlTxoIUTsXZWGR9weDgRBEMJefw9
kP+c0/j1cL3Bk6BpYNs0nK9psyilcezvjJ7Fc5K669frTJaWWqRMcgUyHlpdPEJqpT+IiwkeC3f6
0fSLaAuXPkMbjw7oLshWEAEwfA6Gr4GJb8cMFKwIiS7Vnt0hAsvDm5uiwkNAhC219mo6Sjkvn3/h
ElmSL5JOBsqdpv5q34o76SgMVQ7+6iMAxQim0H4RExv2Pfm5z3V654F2CrElVV4BoNrSr6YIqOOP
+VBiayvLONUADZ+GiJOuHMwYg5eTn0vkVqghTuuNC/fWpRmAOhQSTtoVaUTrlyv5ddcGNZeV7on4
HYafxiuqF2a/tnUkBLAuQ9t1fbPE48l6Drf1sP/Z+SdJXM6zQkIXzZI4Oo+9vdNVspfikWnaAjTe
Rt7DUk+tjugSBaJFc+MWpZKciuOHcdNCuLWoNxydywR/5++8yCZeYrM1JAIzauhy9KbGxv7OVIrp
TCnklMJclo7DD9nwvYfl+7Rp6wvD0zbvWdIl1NMAUjk0Gq8KZuecMfp0HNs8K7HKS6yyw7NZsd5q
qwNUOyk3tfauhYPLJpL38Q6c9E3/cQUg6DKwmnNvqOl1WAOd6plxqRTc/I7Ooetgcbg2UY9PHflO
WsyiFtFxQxJhfVwCN/wGdVWIO/o06IHKi+gL3G6iOD8q5w7V7oL1xMBqwyN6WVj5DC2jkWLdIVDT
Rn2G6fOe4hrlOJOKyqLKMGqCqUXSSeX29qhgUCWmTj4gxA25pZdCjCReDpBnPZniD5QqKupoSnT8
cf3N71WqBFP+cdA4dGjiD5p4bPdPSyy7zRrMNuzyImTDEgN1FL5T1D3tjXGOU3cZh0eeQY4xK6+U
zrY7QPI38Ml91Lvoh0SddNRurKFAZDngghbYcP1u0qLJRxTGcbdQZVjcd9j+eNNx830mrlgDBrFP
hjYXVV4WzXUUs8j9soNNlGu0IXVCjVCfYztruE1dHhKP+A3DEHIvOYjzEhCQ/lMU0CT7XJ7+4+qS
UGOnEVjLHDfkIbgeawxS9H/VHRtVBfiu/SXPcPphTaLAEIbv39RcvLkXbYgEXgbRmJH/5Fx1rlQ8
ERm9V99m6gSojm2odnO/mP5OZI27FFi7dPmE5LM0gAl0Bm1ZayAgp+wkxCHaY2mvpY952pQFUO/a
rhz5aDPHnjS7U24TNxiDGZ6HkSOEjNxSd+Du9i8fkaTqKOwhdgrA8tGnS/vb95xK6XDt4TgIPIdP
kv+Xjt0XyLQeKLFT6+RPdrVb7ZfW8ra3lUvqHfENf7Zm/41IZeLCcmXzyogncv/6Itpibcq1NJ7R
XpL0lhLhJ4QNAZbW3kBVQykJ5pR9OFaFRMUdj1rngp5xnGvbF7HQC3LWhCmx9b17Zs+dA33mXDB8
MiatcbrECUrFp64m2l9Ku1jQHNLBOYHU4YSPBkf4oIdKM5+mIqt+BBpVG0Y6t7SI/88996I3DbUh
lJOe5sYj6mBd9afHHxPehQAKHuNRW8sm0AgOhgp2yOA/3pf1magNgQ1Cp9aEi/bsXDKk6FiMet61
aiA3wObe68V/2EoB8QLHDORZnVtQSqrVl+71Y2zyVI/5g+EyFH7ccV0fBiwPetu5TWZXPgc+9fIS
x/g1XCljxRJpOXHci2YkI1jDavngMfS5nMXizQBeJdbyKyLj5tJcwsNwPV4UUgzTb8JF9CiA2TGN
ZlnXib20+jsJqdejGugawotiK4GEEPJ78p/B3+bybNam0Jxr2owdrA4P6xPUozY4dm2idd6iFtTn
5YK3O8a00qwTivFaOXRLFZGipmDB0Ww5M6iTA+w42GuM9y5/yKBthOlDwyicwPq0wzaGTHukFGcP
cHKbXyHWsUiba2YaC+uzrCHMBIOHlAQJDCeKfelT7OiAXh0rWSyNJtHevUrvXbmKizw8pXG1IYbs
pwhcH9UsxE6CXfEydkc7l0BmTWyJkXAaPYE9WHFJEkfNkJIeXhAgbl5nphgr0xWX0bHo7bOEJZkF
9wBM6U1OinZpXktkF/IWKIfj7UgHiIP9TCKS7GlhE7lGUe0Cjifoizbk01wS9Q2Y8sWEiYJOGJdA
W/5HEGFSvYmHg991fKvHEUgM4XcsnzKSQYABbwIceWyxecFctRn9Feo7PM4eoltbVGCxk9UxGvid
a3wTvTF+8IqR7xgLQwC+TlmDf2BSjvG1SSk2bIO5JOhzzqWkTNWdhS9xwaz9rvpl9Kr9sgxf4K9E
kcdg9oLPb5fXFL/JRoSjpFoIE+Zu/Z/zEYOqEytJaP/s7nC4pgblpUvfWhEAcr9scKA+BpTtAbz8
GjvQhYpzhQhiFK3Qme4vf5NK1hyNzwTezHrzo9gUMicgfXm/jONgtrfA+LUaiF6eKGvBrSE4yQoC
f0ZTESvmeRdfq83kchQ3MpfAejn+kE+645Yg96nL6XuAFGLA16b62E5+QIxY+rEYNO65ScC2o7lM
x17CgcIFrMnSYAFbqb0bqHBL0wwjVtUPbGqq8Y7cXWEYutXZgeOfdzPYVCdDhWOBmTnm2xbByL3A
MJJ1O6mmZefNvVsJgPuq1Hvp0bUuQ5WO2GTvGrnDpQxomuJ5YVQ814+9JsLohMDJgxPZ1hb1iFxN
XdXBq0AnhBynr0d25Df6SYK0ZKSdippNZ22coSg+KY7nURdKgzN3rIIekLNNVQkMUvSzMI3GLqAT
MNnnixQ7PkoF9vvk92bLxEU81zBZmNKKGTAcx3QDC3MDMeqtbbjFf4qN3lQhUayh3RmtkotyYZw8
WRrvB20AoEGVO+c48u+Y3sDZOqN+U0kIESlXQ3HA/ZyjN3IiiXzzbYJsqflKvSNTB2ozdjBgzDc6
7QuBKfxsdoIJK09n8DbXKyeMYKzG5Ay8mmFvfZPrhBzko/TGnN0UvwlQaIFWI7nOEmkJD4PoDGaD
ijweAbjj/oA3hq8YZsplQNNx8S9hb0fI1QnL2EO8skePGw+en5EqRaUyrBF/uN5dtToBx96cgT4f
QyNpYB1e7z5MsyA4nSieQuhPrrCi2WG2JQIxeRjWengaxmC1jAYz9uK7Hne5nyz5CW3rqu+k5SAp
OrQPbnn/XKwFe9jXob6gnr6cLuBsh3bmpaVRVNnzgfVCd6n8a+sywzCGBSA8GKXA10VQXMF/lNJR
O2Xl7dGAdFfU1sDnvhRxnIbZ9SmpAQrduotUV1hel+To7NZQ6StY6L9gwkFdRGm+hIY/BjblgGj8
TbKcdJ/Nba6v40yeqI5Z78vGEcchLEKx/Kad/hOo5rxOKnrmDqVAxUaAcnyVDObwwt2+f6zMqXbL
El+8AT3wE5GaIsQfOndGv4GVLvqi3kOmNL02ALaTYEzAhKguEmjyh/KsJcz8o4slErJGDhXhBI8O
6/y/fsS51MwcGCL+x2oe6k2wEXDhkcF2FZywhdyTiApFN9usXBUFdli3/LpSgrhgUI9l8B21iPQI
WOSCw6aIVUKoCcBIcxiJZk3LFrk2+YtoE8fRezO6+kxJH0M7+MWHDW2/L+ZJPeqv0ftfviLHMn5A
ex6dnldrbJKVwbvEIoFs20fj3LLgWAXaU139ra0kIbU0XFkcXK9Zv+8nkGatorWlhP+4qB1gORV3
5jRkmXzxPunca8Fbc2np51I5LDQDV9iuB6Yt+2vyjNeg2hRlgzXTBoYQYK5iIfPUHN918YVGllQk
EmfaVIxqpzqTa7aD/RvFHAjMHUIqrWDyVqllMKPZOi0AZjY/zxyCXNjoSdDy0+TmZlyGMqKnUu01
/l2JNizX8Z9Xk5WrCpPq0GHXMf6HEdwDUSS5DCddpRoOm+M9mB6TdksXBmxkQqya9QwC0G3cM4ih
3z6D32fLHR2lKEcxHSXdEjpvwMJXhobrRolfj8TMxvYXclY7+gOWt7tW+COot7BTXcyLKxwpsOJp
3skxlPaW/Y0lVQam14EK7484Aq5MBdwgyE+CsijYHbTDxGSbycuzrt0sUrbGvdFZp7o9U1CSbKy6
KMBOfyydjwQBcjaSOCM+60J283i99IKp8x49UAFrbFybplp67N1WUJc/7/g4CFbWFQLPlQ5pJ3In
FTkGc8XXidq4MfT+S3kHheaU6aAgzKNh7c7U7R3h8P8zNIFWWAQzfREqE6Jln9qdwkSe7s5iQ3nw
gyxNjYARWC+H5iq1fjur4tTlJYfHwDZEkdvugUjIoyKqVwUTaXQOrHr3NqZpi1zHluZFXIt2Tq7P
hFdxYmAPypKS6sA5Y4FhBJkrvSTH7dZngjqGGUf961DsVVKiNmRoVkiCs9FoJ2P+mxySizxhYqtY
HHPQMGBHwqZfRffCKJxEXpVK8hhBeNawMFqJu8cdaS0vuoaMKIC/Cdt5dJvg3SiG9SuPPs92TyaE
Lkuv4Bh+5iA1p6YVhoPhShlChDBnSx0SBeRGyLAsimFuCCKSA5z1K7zb5EAYlvIJy01TV1OSu8IM
eI+Poxkp9Eohvx/TL5sL6SF7EFaZYFpbAKarw6yJ1zDBegAAygXAIvQUQ39soJ/M+2lWPSCkffR3
y1efXQMYtmapxV08Y238pXH+OOPu3ICD1Coir15FPRsob527bwsoueKXPd5aqCVMe//48W9RzVk/
7JeVm635FsKRqPwcdkwz/BIircCz7AD3HRRxYE4Wp3yCHrnrmwCeqqJwvh1CrBHyuFEfbmRUkMhc
XcVgx7dPXh6E83DWTk4H8rulpg0CJc4dEb0JgOFzow/nvAxqPFHhkDs2lbLVd1MdAeZdpTaoVih7
YRN4CD13FV51XL9bQHhq+UjKbsny0fb3lZ9xNaIOyn9VMxQXJU2ZoFTA/WFvUcCZom2W1Dt/sN1u
nOZ5/UfahGgo7eJchCv14GMuC6TI7eITkyMezv1ehGDNvpAZZTAT4T9p0wQT2vcOnF5GbEs+lA4X
QYDEEzjMgOYMQz8ul9qEj0TkVYS62QSg5MCxjguDQWKINEkkjCHwi9s1p03p80/sK5f71bmseZYF
HJ4KHKa1DFYLBJxAdONzBwT9IWwftTMeGZvWdyK2cjqOhOkcG0svY6hGNaVc3UuP0fWkfJbXFiEA
eQgKRlSCVMpXKjJUI7VPLOotEhIgKY8aZvrfF6/YRig76x+KzO3z886F2VO6WCcy22+z6SpSSR8s
3DenEbTayByTCmZaq7kE3zm/3B7QGjRsBJE2jvc35D28vGjRuI8RYROivCU2I9H7sRMpCX2XcwLz
vj1HfNeJbf94IBr7NBAapAtDmlQJesDHRxpXtCxSrWZcZhAcPTZzNu+r32ly3DTT6EKRf9NnwhXK
0ZIkxYG8cJJUL2Hos/FjLNskD2VVcTBLMOULHIXQURDLZF8Y01fEhPzs5J+rHsG4J3xqgSqyJ6kp
6P9vaMaEY8aob6LeAqEZwpJW3YlvvX7Shz0Oyn8Izm2trXEmuZD8VBLudN5FAmevz/VIbQezXGWu
lY73AtR72vxRVgGnnPVdn9I+94idSgRmOfC06expQQ44RueRzJbl0J8Hfbt0BHhOiqe4xca7qt9T
7nd5tGD8/cQSjJW5pKmjaqEyWJZ3b2VtK5ffMy8Kvjj7fzuVZu3jcmHxMA30v85hDnX1TnVQySGl
FJeZLHbyxCYvqaRwm7aeUPhXXN+kL5Ku/l7zYHLGZJFjtoniPxM8/tWTttbCBoiomuQEqjzMW2Sz
1LUt6HcYhVHEG06nvXA6Xdu1uMk7rJX7fy64aVVzMVfVJyZHI3bazvUwivWm8nw05Ir+jiKIrPMp
+p8i7I36SsKQH7dM/97wEbhkc2QwpDZs8zbHmt5jtBwyIRuMu3Sgx8C3uyemehKu6SXEnJNL641b
zWkGkZ5CP9UlmqLcYjd5hTVDCuHsRu/si6lxgERlkr87VJw9ua9VcFTHto88lFsxoEUK+ULNg9zr
zlXZMOEx7Lx2ELZ0OL5hBm8I7u07AVpkLjXmfQgMetF4VZVW4o/poZ7lhV4RFU9RLdw4wLsHJuCa
B70LFmIykyX+3BvCG7txDr0jh7KJpxlTiDFg8SAz8MKT+I8K+TmqocdcLZVBT6/oZkP+tZIDjTta
HHhR3KFtvGwJ6kt3vF8/u0xgTlG2WT5Q3mHfFDs8iJQfo63UfyhL1m0oMJ/ZbQzFeCIzCzW6avwW
6DlL6PUddNyfnGv8SztM5IHgwW1nkSxrmRA3blzNMvVtAoWuxXeOpFegMuX5vBraxWlBZ06mzveO
xXaYPnwiYqJ3hnq5G8XLkXOwduKm0Lw+8XgtTfuTMqXrEFf6pXfshj3gTAVRrXK+oljmWegr105Q
U3qAk+PLcOdX0Sowa7RnCpofLdX93fkA+uaueUnL29k/gIQ7oYBjqMFhDSgeIcnxXn5EP0cx5nCp
Rn1w1p0Lfh2VfmOtadrZEFmm4zOkVFjx7gV7rQvlhhKIyUAbz3adhc28c0eEuIDGHvux3d21K6au
idkXRBWiE/7kIiQ+5/MEZM0FYLB+l3Rs3tWZh+NfSm1hARdVla4FMCbU66z2BpicXmXL8+miNUAs
rSTONC2ZcgSNptgdPFcIk2k5bfAp030xqZ9i5WboneyER17a+8m1ko6Jenpy7CrlzA/xNDPdtCWM
+IIMymHANghHK7+7DYDjFBd1YkHkpEB5xuzA2fmSHIw9020BMg9UesOnmoEwtTqHDe5Ip6Mmz/oZ
YilmWyDsr9mklicsmj52TP32QJQkJzR9vkAh75BeNn+Nn0qZ3N7nut0t0PbmDMKZZTN7GNiL/V5W
SDag9ITd8pD5vBm2tXOF2iwmt+k4CwJyDRKhgilmoVwigvcstSqOtBCS58UUIjx0RQD6IKo31MmH
iTogEZi3PIJh2Ny2KlCyypz4axb3I9RWxD6DwpEoYZ64uvj3+wK3jA5hsqecPzBlRZuTjYbXD/F2
1ifTziP92+lgYSub048MVJqN1AUsXOUmqZRk6piWY7I0NYNjZ//QLgaMwAOtg3erjfJ84d3Tbfis
Va+6HoQnGmMkv0enO09x49HzuVxrZjBJ5KumMOAkngxG8948KXyKe1G99XCBLlVnezUMggA4eQsD
VQY1njiW/w7dlJLsbRiq6d9Y0GIyMYOekJZGFd9+pmBFYi033VZGZRXUMDeAja/iQBCiSd5gJDwB
ip+y2vz1QHOr28XsrHcD8ZoulR+IOgYY460wBqR+6SFL1DUxrqEJwb2uw00zig4wXEXoNo2fGObK
CgI3hk3vcoSbntrciLnVSX7gyffxgNBcMD0/ZL1JTuJKHg4Rvo9PDncWR4po7FsLuTf8vmVobip4
thadmJvfxrwI1bopeT/zsriCl3ECYXkpQ9NC+8D24o7Ee6tQlptVDcLG45Jt1jBCnSyldzhvepl/
K91U5BBS5OQcFGhiT6TaRiacamAdYOCoLaQODBmfNg4q4upZFn/yzeTf0gQhd490RJiP78Rlbpa5
pkaDsMATZu9d4DIgpSET5umsSHrSy8RURgtgbLI1nsnBctz44qOCqehMYfvnLOfHL1V3x1b4GVWU
avPNJ3RMuoL+WyyQGchfXBDNxzppC9vUfuaYMV83OEH6kUTsm6JYgHq8sF9IgaiHA1i7uIOvBxRn
33ei5tTKqnQl0mnv9FwKuz9I7t/gauZmihz7rlGZ2+60G1eoVQrew5qhx+9j7k4WObVDVXoGLDn4
MAzgjpIm+cdpHfrZv7h0j1Xcuawr9h81PJcph6xx/Z0ilvDqulVsU02ea9x5yR5fsQTWFv2b+Zcz
E1UOBbY7gS394r+3Y5FN8tjjpZYSEYdUlRhmRt5qCS5LWDhb39C2Wo1szqG8IVmhzUJV5+T9M5P0
XCC3+wio/LIwsQ/B7l5AArM+cd8adsIXnoynYenRja7kVQEfRq9JQKD2vLFU0aASzVnZn8YGq3/n
YzS1It1afSF85EOAhjD8QsGmdx+vyrZygFk+NSbZxc6hCKoI8kYc1o9nMMpng77uLwXfIEWdexqP
4lW7ThLULgLVDoYNFky0YfabjuyGs5FVBT6RTt2tY2BGMzs1Vu/X1Bn0/XSL6Sj28gVfYrmXIJk3
UMKyajmEpOdsWNW3pijogb9de1zw6NjxVWc100aSI4qB+j1GnlEsK9DOc4Vt/tsAX5P47etwrxw4
UtSTAAUe67ErQGKCNvrx7JpHBMRM4IexVRnxhbC0rtJ6KKgarzIIQDFV/08u0WIMe9hfdFOybg5P
e3DgnAdo+urov4t4pGHGgc3NAqLjMK2093ZVkbouAHf9kQdOLWVcry7zCEw4dXZStb2V8iH+V36i
RUxtmU8tLlH76bcNj7Qn4lcr3p/pyRYR+yoc6er2nRwuiV1/EfBW/+i3u+jaf0lktgIfo0FQkzwP
WCpH1ynKKloqwqPytttEWg0FClaLgh9hD+Z5Yq5lfCDVwgsQrS6xdwFXkJ12PDMpg7g1baABhRQH
QIRfKa0XH5hLZRQizjAqxVIpxTHXEDtqPNhxmXXvk06M3pu7AyzFmdZDVoXtXyM3VFuQ/YvGboVF
TeGhZBNjv3cjlQxiH/U1r/sG6pYulEGcpjtkyekflJ/ruJ2TVcP+iiGncWVaIKRK9x3Y6fDsbVzA
uf3+mBtsEe556COZTmx4sJr8Y9Z6Q4GINiyZbbdPN2LoQv0f0u9lOYUPIKLTM2sqH2gP0/45+KVG
Kj5fwirKSlE7sU8B6wcrdmohk+y6BhJiaNBgKbr2xznGFnjDbwWvtHChsw1H5Gq3N5Tl0PWZgZz1
l90HsFYl/+oldbEpVT8SYBatEnJWVPeIu5Uy72rgc1612AJFVuaeZYrgGMPJ9SWVC4j9+6+ytTMS
8B7qVg5zirHXdieaBEV4urhwkKWlYczUD0W2JyBE5TSMa8lvYrwOhQjGnS1hEwyfbaTf3uupQh97
rsq/dVKSR132E7Nl5R6nfKds6GP9hgBGhx9QbBBDiGD/EZj3DVs23X1+PFZXHL4gyQ3iZMjTD9hg
cuzyt50jk0WDRw0OkoSw8CIb51OB8SqtE7EXn7Lt0z0f36Yv8MN4jv7Sitd3tpUNHgzhwQvuzX4T
fjVIt90m4+eV52Tjg0iKaU3KLdsnYLbDzTwN7BKITX3afivkV7SuEUdKhEtKBWFVhG07wwvZ7Jl4
rEKHcepLvkbRTZ3vAGK37qFLBUxouHaene8Hu7S9Rg9SYHfevX7e1dn71aKjDl99D6QbMaf8HVga
F/csxJYBXblLkORzVvWbZ8Hp9qxu1N2zis547zURQ3iH3RK1HlRH51uoEgOeVizYiM7mgw/ITyMU
e6rnhMUbChxbaLo3IMLWglnMHqohMiASau2ilwY8G+PDLngY4IlZh6JH1+DZ9dipnQ7JI876gtSI
vC1EKj3Q25JspzFsXJyTA5+elpAQNfgTe9ix3xTLJTNoLltbcvHBcHgaC7fpBMGK9P+uIaDCmDkN
MONRD77TC988UXx7c2FibKikGQ5C2lStoKG0L7ETkJZQ7x0x5lYMdMZ8hHv5k0NDQ5/wCfsC2lI4
2RxidUx8WE4bihQbU9IvB82DuSXLut5tFYar4YdloJlzZyTnExWiMzy/Q+gRWAwW6kkdI2/qk5uX
euOjo7Tu5eGsqJPT4o5TBjl7YzCMdfbcAt0496SjPCJIhSsINhR9zNA0qaDah+R3fS+7VBuqhSjk
1OkTnKDuwxDFwwwzoMx1QIjdqkLDEdbVL+aHtjNuGzsjkcLt+E9d82C5qpHwQ5s/ZUYJmqMMNK3g
RjyDh/DqkDKQY36EfqsgeUEFI40QMx32b9hNGjlYEf3sSCc+Z6RFMklxIB923VK0x9FsiAGCTA3Z
UCRSvrBsT1dppfyOfjGanVaDAwMs8OFhZJCzmv/+2W9Ayxxioj2edpO9IXnaW+KAr14MYK9sApXh
WHBgyXSS4wrxMG4gmvIulW1JuV3bm7PM5kW7OwPkJ3sxy+l32MqwB/ZJraTg/GoLkx6G3k1BihTJ
CZI6ugU2bcZZGxxv3jmCOG51Xi8HTTcC+UlDYjv4dVhpEqNqhLuOeEGXuNm7YQtaIkElfDm5dItl
2/jtCth3g3mi9kb+jqGsqX+2CoyU6C7O5DIGiEyPfZTJj7eftgrzyQWYJIj2o4pckEAsJyUBuEtD
G3k0K98WuSzh/62HO9bfu4SevnnjYQJuesy7hlkcLQyGVJdynMQ4sXt21gIvyGWJaWCSu1qoHTTc
bGCJgbC6ynUEgn3Jvaz2fTQJysarn6dAEvGrVXxxjBMkvKgIACM2L3def8X1A/u+cYRFj99ZRBgt
O6bnfYL5MObYViF0222N3MTZIupNAGmBbaWi7m1ocEREsgGxpq59+xgzPmtRjKz708vDiUI9J+M+
hyVelUt3cWJS0hCig/Kp+GgqIioFKsnJPm5JcF97tbawlJCCNe60g9sdsHLGVs8qzdjXKSAyR6qD
EJxNPY0CliO2YL2YSAYOzmVLM6TEozeyOC7cNeRe02nsLXOviuoOXtmXNVZHciGY/3Nt5mbTOkFl
Rbm0DswhUIUo/pQvfDc5vYm9qwgBqizRfJbPwU1dBIRvUIOogYq7zO53ibM25tIrN8iSso4dGw18
9rtAxe+2iAG3d1EGUDdQuStOpXAZYJkkut4PoZXAAsoCEVmCpPnM5LUscEq45/rwxb2U4OsYbL8P
v6vev7hiMZPqS/oGUvwZ3LF3F1M22dA8IYfivq+0/IHSkhYJGU970rNroz4vKZWqUL2kpjqFteWb
KkZP6/ufb8OIKW+tUcOK7st6U34QTYsTvIaWYYDbTYPq/thfoXC4yPHF2Pv6sv8EzMeA8m7fNItP
dUTlTO9c5YTjdyjKveMB3QzzPG5xykZozUA8dqJ+pRyHkWPmXQ71DybFApC7vds/cGWzVL3pkiiP
fGzjLkDC+cDuArs7I3KmJNVaDTa4P0rqnk5w+ucvWOBboOorp571cGJ2YfjyI+nnX80lQYmG8o1/
qBeyWOvh+r/4NjbzhKroJ8l+O8JtdYLOTgxpl2owEQmZeb9E6Y3YCbQO28WVa3R1UqO9kJl73IFm
3P4KmV95QAiHVuOHWML/+SqCtySX69Mc8zYV7BpOJaGMj2y8hMJasd01yPFDrRLohpy/j3y0IRIZ
sINR+W7n7lK6znsVfwNFApTa/PicnwmruPzEor8akIxOat1VlLOXpm01kH9hNqBrkVlUP0PtbZkr
UGUPWHdNJelfpY216matN1P3Gc7Xbd9qk7tQNvTOzzYjBjTzQs1SRvPZr+Rn/4XtnK/2hD2/CjEp
VUsyl1nF4yUDUxxUe8adQ20CYlTT3t6qlb4QqMRUTAivOoC5J5Z/zHNt8ViDZzi1koJlLBT2sG1j
maXXwhC0CSx3wM9ILC5VYFss99/LEYvz541xnoHfW0VZ6W05KoZ57HI1QGfw2xbp+a/Z1ADUf3Ui
D34KiNJ6C2qCwVhkPRiG40wVJFsmzXkKbj8WPOVEvVB2J173R2Z0YEzinkkCgzx25D6Zu2Cg5KV+
+N46gpOe8kDww+SR/f9+fcmmgwxL06DEoP678hhQzQ556UsRsVm2dWi4vFg9aiPZKHSukIkI3Qhq
XDm+ohaXhTJe8BlumNLGetrtvpHGDtPfnkwPgqzFcmEEnJm0DOCl7ienyqheFbGyzWJxFEpKe9oJ
+W7IcVe9CBBjazFXdoHL1biyoYqJLqIBLs44fPEsLOTwlBxx4U0N0i9ygpOaldk2rV5YXuJh4u4G
ZUul64FEJhORu5X+dUc9zfyXnZ3Eqs8wS+qIU2pMANceSokB8NzwQFTMhriEryj7aM5LUx80sMp2
ytkI+iqOndROoxiTFTp8a/S6ZOD6TBm/03KDRKZGyc4TVztq/bf2jDY2n7Q7IwcLekdhgNIqgW4k
OnsBhsa1E52r8h6a3Ua4ZMPKl+87PS89E0iABz5BP6qMNB5dU8zqwzs9TBpdCwm1+K4PfcZMzM71
keegAUXt4aBGI+kAd649umdBP3ecLpQr98Vzh/bszgXma6Rdk7h1FPwjPhINgGCDMDfd0lAGMWO+
aXbVND9V+znb70HPXR4r667LBAsMgfSm7WfnfzaMrx9KOgGzPf0sOo3HCedIF/cEPXKGS67o7H1R
lYDL6o3/U3YCpRc/AlNo6OHnIqxRiVuyNo7t2fjRIBTUEEQaWGiW2zKaXOWhOy0nyWwDfYududpr
2GR9w9p35O3LfvoBKmUx24dNA6Chq3F0hC0FRu7Y+zgXxXUmzoOPuH+R1suIvcPCuxNwcelENYfz
qeyF0Jvf+3K9LNKV8W9W57MYYaHyYpkS/JF6Q/2MDxzFr27fPU+0tDoIyvjVzBqof5blKX+2hzDc
NbMCQrYgiPDTdom2lOPiCiJ0XkA31XBkwugfQE+w25tvKky7HI/c0wMQeiGcDL1/iGRqGnfrrwgP
3mdMia3Vc45nvTrCLkZpzCjwdNPiELMOgq8fHVy+e4evyH7aGjsNV+V9npFeDdMyC3SadUgxJS35
Y6WpVnJWejgaNfZQNQQ6dpFJAeDAIgIgdJ0r/sEWB//o7eB6J8pMnJDG0JJpFsyXPRNH6w9bj7LN
Y9ElBoRQ2+1OJvJEtPsCwNhl7ZLHBj8JWnHMSgwDdGcJA1W1vYAWCs//Nb8bj1gQg3TK5oMZM48r
SnPlL2ofzbftE10bwDE/AXyQtzs5oePlh7J7J+QTItocQX4DDj8xcvMe6I2IzuJqd80QMpiLml9S
7niV8Rdd/gmU+JxG7ZuDcAp3j4ks1JO/ZxfIT7KPC7I6h2vhfEbjBKcIivd/ubkT0rrqml4vK9SM
VcSQE3Oos2zoxZZKPE/OrCJ45yOHSSx6k0Phr7O2l7aSl1srzwYmI7pNdpcKAzo+J03Sl5h0ydml
8N2Qz61jb0X/tsWGcUJ2Xo5dsQWk/SFXF+GKdnYZIpqWwNNVrzTdHXW6WwNYP/2qxvnPQG7hgFa+
zoCXa9RQdj8bnXXhyWbfU4T2ucu/SkWxBQIKF3+mS8ZmQOcWj8mtbieUUJWatU72kY0UysTuKBgE
4D/WsHiyJeatDTiSoukxBwPmviM+bc1oEcpD/CY0cXD1ZC2EfIcUDZqG6gKilSm7ItRZPY0JTTNg
Q3CZZKRV6axXzsWK+9i161Lx2Y0LXGkHOMTYMBp4KRpdw3VwdfWuhcCnscBJD94Okt6xhpFBneF+
UECp/QCoXoz+hyxZ9ozztpT/3N63bE5EBDVAs6ckn7dhn+PgYpNA0tgqoorpd2c+1qCGmFM4pvyI
7I5wkP/PAlcEpHD/DDpiaZR8HVWU8Qjw7jLXSdy07VwE9Lx7e9Yn0P1+XysUquP7EkiOQqI7HZ/V
TvNn0fUY0En1t+JfKVtj5nKrq2OkwTXmqABx+Zra+NCe/Bnk7aMb3nqGpVDxGt36OnjUqcR7hvt6
8fhWaBqREpkiI55oTvEd0CFdlnjTOwmmISxCNYoJAOf1XIpmePRUL/ZZJZzHk3e7A1qTMky8t0nU
r0e/rssZLwKNamncLPmm9+p54MEuZo65MQLBh4guHPWooiUisJRk646M70XiqBneEZNN5in8RrMj
QQD3htayQL8retk5ZsHfBy7ohenen1R10tOthGh4Z1XxnU/lxnLfpzKdlpwm6ivR8lgEXkGek2CN
jHCuOnwPkEBz7mirlpfpQafkdbG8K834u9SfzQafLCpaym1HHAvld7sDuuXG88dvcjzpNELOoVEm
rjKK5zRwv/uxX8EszDh+SDNv0+K7Kw8P4A17UYxBZ0rZtdWX+azIQHcSpMmZyFwZiDDuQHNuQ3hw
0ExtEiur75mSUD7BXIfDSyW5zN66HVrNjlOCDup1qOac3Vm+WW4PDGnetACz6OWRL5sn+0Uo90Zo
mqrTMUpZ3AZ8KOUEBEgZo4endHzdjMfwphQK5u7KEb/r6ayZcNy4a9F4LIGXlUBnyzEXLm0rTzPG
oeMRez8/y2ELftzrZw9XrZiNnRCo1d4RjiMq8xfPWRIH02vsc9e9xs6wR9KA+1XSeRCiKwH2tiT6
9gUZCPU9kZ6wc6GJdofBye35Mz3dmdRLhkiJZmH1pCQnrxm9X5iHtYgwnEnvAdNzsToXRV3XNsh9
bntEhSWB3/7ANq/LVB0LjP+nCru8HiNqKSjxja1maAFrzV/Je4tq78eJDnA//W5aLVVZzY1OeD7/
wqpU00Pu70OMZEymCa77vAdw9158fXgatk2omkxNOHCP6xkOarUlB1t3M93fEcocTkk6lklwOVfQ
32piJ3KgSkCW/T7tQebqAq+PJoGlnPvdk3G1QRv78iyJRRs4mMMLwUuyx8jHkQKkZ/Dym/qL0FDK
2RLKmt8Y4pyIIamzdjM5sJPkVXpAXz0IOr9FBx4tdgB+1cPNtbdbiGCkqHXsT8F9lMgxMhAh2mRH
qjYFG3wa1BKfjqK9AQx9psoOQzKIt/t5AW3j5tJA0CwRHbGdiG5V+5+1aIp46Qzeo/iUwtRq0jp6
QnW1X9dpf+RynXkjcHEvw1Rqmw2EKn71M60amMY91CxAZKsGjBEzOWXHI6WGA2p6gbKtVh963U3C
Y153ea1Vj7M13SowjLN8vA+VBw37dOlYQ+ndv3cwKnF65qXV+hcQf2jWW+Bii3FObuqq9olSHGN7
RlQV0BlYOonN9RLkSdJhVeIPcRaXxIG5khXmQ3Pm/ksI4nUkOnOhX5AXoF/9Fwd7f93G/30/E7co
4FopICoU/+wz/WsBZxchQPeNarixv159RNBJgd5h4w6PWT0qfWsSsXPylZFKBr27fu0sQTdVfnAs
0JKBPGX/jboq9LJABxOF/7drU4sqZDE0Vj+6jAFO5p01d7AertWaZRjaO7boZEM1fFmLjjzBicSd
3fsnc0ZyOVAlXLcS429HxqOBtDgy5HiiIW1tNnYRLMQdpE8Z8g4cRYAkMKctwMTxyq8EYAjYpTSG
KEnh5/9t2cO/xeOOJGT4mGtLfHimhoaXowMNGyIXlwQSlf7FIUKNqdlDi5SjVyN3mFFLYzhX1M3e
KJwM69oz+XFCWr9hq27dgrfzYzd9IgOijIz6gRnTLPPNzKTOVf7/Um+iXYjcJ+wYXBwQs4XIJHmc
Vx7OuwbcODWPJrD/QeD+C0oh4ZTmeAOC8UGImdgbMkaIYFb3XHyvNzu0qAlOz1KkJV9NSVs/wxR4
0miuF6hEhk2aOuWdZqKNzh/3uPXX2Ywno3aFh5cIEZHA1tiNYpauMcVscZNYXdo1/6M4xmdJgDYG
vnVRuVAGRPmSeR8OEzAT6/6fOy0aFpStHQ+YqVhtbWyGEsGIgatqsYUuNji77dONfgXeppLBFPH+
uv4PjQmPh4IrtYd7kiWe+IzcvfRbWriGEu2IEitN/tx0yEh2G//IxC3PIP5HeHKycOfncyu43SZz
WltXuRdqZEjWcGHOm1bRd9WpXdd+FI1OefLxxSLXAvScSwWfSKWBZANhI3NE7OFcs53oTCrdiQ6O
DPGOzmOppQuk3QiVouXc7zZ18bVK0ve0E78OIyNQQC8mkcCeTp+7mTX4M431xUm5NqOOFSsRbtpM
+hghklQJHExK6Qchtqow9pHMeErgxRrRYurAeEvTkfBG6k055sGie9zdbSMj6b6g0TUzIyUd2J2q
giD6HeEJ9X5rhnG8JVKjUmvrXN38x5/KFL43MQ9zM98jOt8MKbidqfnrch7wke17blPhQ3NHIP19
UBYotKFJdx+jvZTG0LQr6nv0+37VHF4jNh1IgRidL8kN7IWCG9etSdJ8STHeQAy5fG2Jz2u9cY5K
EnGEnXbts4gNE03pWCBOLWoBT1n669FOZhuQow16jvnIbfopwAr/DGOmH8gzRlqIX2KM1TbJduMp
c5BLFBiyAHiFqp0ROhjJgQN6kxpno22KaZZQ6edRxoLIHn5EZdEG3E+SQIc9CYwMqt2AHCd8H08Y
5vRLSI7ASfPb/OzJuOCAg/YCX7TKcc7+TRnBVGWe5u/qU4BzsNg8i17jveOSBZKlgMiL0x8/jaI/
oiD+BcI+sxujFN90kfwE/N+vIEc8k6aYhntHJFdYJSR8YQDUSELgRezn/w9S8sQqwfeoh4P9JiFh
H2tizxkgEDmpu5UxhSlsbpD0dYh4hehdFLL7YJyS9dBWWJO1SkoxNjo8uThPWCF6mBAJ3duDW3QC
2CrW4nSlV+pw4JTf2Nv2W0G7vH29bi+3LhVrt3b1vr+tYAcRfuWWb+sjYtNFLSNz7pyHWhZ6/6DR
nTR7ZpgYQOGH6NXE87yMm7oPiZawFB8Pcn/88Tug/8R2QP3EhpDTD0ri6zGsl4av7f3v0TzfqBpu
F9whqinTghtH4n4axswCfC5q/Mzfu3uH72S117nYEInGj8kzqBbUWxHe07h1S7Yp14R7cj2whGVT
EF7jjcY4ekXQeTr7O4DTisZrA7hstx14PMLMupoQKfoVd7MKUqrJ8M8RmOodpV23K14+IKLihnxD
Z34PWPfvCZAtcxdRczXY9MI75zOUcCLf9n4j5mnGacVq7fcaroaXpfVQGF9lfdBiAPRGndeybq0c
5CI0XdAyc/5VGoZ7Bk3qHUzj/mqyzqOATvy47TVfA/OYjL5WGtsV76hIF65YrCqRpOqPXUATmFXF
LPlseLPN4b6IEQBszAYUke6TXeTe8FEFvWbicfCl8r2TeKjg7mPUDEcOoaCxmRGGPDyhTGl6oFCc
gEpsMfhAypxDnV1EJa0fwLmykR4da8IZ99RIWXa1CSwZX2pxhRUDfBCL1m2QX61nRt9w6NMUJG5N
CC+jlDNjKuRb87HbFaQZagwF8xsHv/dTQtpZzePAyzGZf9NN7mG3Xj83bRxPMJdWZTuonzGwZ5MH
oRkwbWaDGl+OlXmGUkuH+NI2CT95lesFR914X3BvmeNIeVrmhNMS4DnR7+Ahq4kiVz9LXYYRz4Z6
K5sSwE9EJ6yYuUWf6SxTSnwaASHXO2N18fbTsPryA5Sv3zcQHXbXv6bQC7t37JxG8jxpMXr63hR0
XDHZIz9jGMSW6Ziv8VIGON64qx0k731krvfiTjVyJFS/YW6FkEOpwxwvN54BWxH/IK4NlJx05rh5
H6wQICCfpZj8b7IUCrLhPd1lJxV4Mwn5yxmOsI0XHKtzoKobzY3dDAvofzgdSEeYBHRN+dzIiyxO
GlVDJswhx8009csSHj2L1JWc+1E1MXmloIP3hsD8Zg16TVFNwXMhKPl+ezTdyul+evm2lX5c2TvM
Q5n9/rXqfiA7CJ+unhcdbX8ISg5Le4b8+JSpfThCbFpp21KZykqaqi5esZ03IaP2m+Nz5nQg/Ger
VWWLuLHdIpbHBn6Yykfa9Cja0ppfYVRYUylhqzqYb4MByLn57Wg9pATR2xLDTjp5pQPPPlnEXeXQ
vuJdsOo0UL9e+l2XS5RWEO+F3dL+k8XhJQpG46f3o/jvyU7NKZVPalo2aTlkiR5n0w4sTLhdZEDe
DtFqYLJ9RhJK8AYd1Z/xbPZfYw5yw8qdU7RlXEKij8ZqixQq9y6iR0JiWGCKOB6hjcMOqOXQ9hc2
aqFBk+eat23IBW2VoCPUWzRM0aaT+8BYZAKrMDqmnP+DvmwhQ7uBGHJVLuOHWl2vcXD83fZu0219
3VhjL1y8dhMNPCC/HHVi/Cfvey6eYbFId8uKL60/XFTSYoHf0tKYmfIrVhvEvq6a3IKudxwNI8E7
56ntgzpaq8b+PXHrOmloPJh3PgFVqEwJvLNasdsfX5+bayinosKNzqYLs6LSMAA8ya4PA0Yl8TC/
2JSEN/IwP6hFfBnxpntRWwitiuRhkpuomiHbqJlco+PjtyvyiQLECTRfJQ43jul2JWvpBXve8enw
r4jApRyoB35tP5sUm+VvUKCjtO68F4XTKqugGAETaRPIv2U1Lv/vryKhHujR5kHWFQNZHo+XJw6+
GV1bEM1LoB459hYs9NC9XSziZl4K6Tr77XOXPzNzlKf1OUr8S9flAGzvmlHdyHHzk6Fx2NR4+4QK
Wg+ndqdK3/ASxe2krO7i5s+PG9Gb9+7/5HPJTN8U7t4xoCVAKTfbI8mo6vhvlUt+Ee/Gj2Ofl0JB
Gt6WYC8M01hQyQorYM+WjoYmhWQnwiOdq8Aojeg/5mQSR6d3qV+q3aY/p6lLCCS9yj/ND7bj08gl
YM9G+D7ZUOFXjdpXG2l5oLI/YDId2mH4AknQzRnKcxWC8uVoB33WCwwl8IPJTTvb8c1F7uSbnkmb
7lFcAZEYsjbFzZnW4ke3uXns1k2ifYGzRd727o0e57MjDrYIXM8SDU4a+a0nzqndn6t9xu9YWy1a
Up+i2AS+Z2A44V7LI3h0srRmOHv5YucsKVLTBBXVbrjx5/DEKYRmB9pcFYP2EL6z5SbkHSAVptlp
vdp0cu9U7vsplbpVLiKeafemiRquRiVdpFlO4YHl2xUcvfjpnoDDodbiFyduZb/Nyoh/Y2LEBcSE
U4dI5JZ1UEj6DD+XkM5cW3Ke0u412T/okadRvPbIX09E6iR3gXiUPbZj4eGGfsaBnyeY1NInc2Nx
djtZNXgjSUeuTSLrdp+Fa8hBb97MEcXNvkBiB04EEF8GOL8oL2vqNAzlNw1Et8Itp+zF8UeGilS8
HL5dFCWRp9mi4hl+3WvA3iHGMIg91/B2Wy//AtsfM8tLhAFT0/odLFWkqB3S5kDICgtER/oeRacT
qxVtkZ2fBKCVvcDSfEeyIA6BzRmvl+640PTfEGF3abCAbbZD3/JlllfPyWxURexOw1k8wHl0HfwS
AM7W2lweIPWNu2E8vMAxdEw79rHadFFhbRAoo3COI9RccZh2cV9gF5t+eVplq+wifSMUaiIy0gKo
mpq8nK63ng380TmWodZcoug4T2IUJCMoKH/AlCC56wCmz92zJxjMOTlmoumL6vBAEM1LO98kjDuN
CGeLknR4KpovO2MXil8r4BzEbWaq52cwjXILWbTz9X/Ip21jDTkM1J3mIWmxm/DniORrXh94IWlF
BPi+pohcW8IgDoJFjVvfKmhK/tejwh3XOcwgjUxJmIlRyYBnWMNKzxLps8to7c2TiXMRwXG8Cugz
9AVyurnlEwi2TEo2sahPSP0O3n0ZBtdazgVc086DLDKxPiOO8/uYkqK6OD5ERL33z0PNWtMtLTIh
TY0NH8XBmH4MdxSrVRnG2SF+N033NYoP2bJxxtqi4gJSi4iy3+Bg5wnXDgA3JMnQdVuQWFXSU5aV
EGiT5DEmmapdjZGyNrG6Ko8vc1emlff+v7fqAtJaSEvguQwmqaYOwBt/hPXJsx6hzA9a4tmDzpKP
Gbaiy053szthts+ZNVf7ySt7rYHiShpayB4GBMhSl3ytZjgK1PkVx7kzNixCoR8TBdxHnBF+N6nM
wLiIj82FrQFs4IxAY6WPTKvVUBKbiMnxWPWh3b2lvxcPUYNOUb0FZlX++U657prqx0mDQKLvYj6L
GPGxRbWZImbl2Xw/uierJniUjFcClCBnHm+CvNfzGBg0U6Jre4nuaLKnOypKo5C8YW5VpfC2qa80
OaZRLTZLGYwuRoHtF/X1i2Lme/oo6OtugY+eU2Lz8vgEdVyEDDPuj4+DgcXNZyNN1DBueeBlTlpP
EfJVLMbC0oEZN29q7bVDzuEUBWzGhSSUVBKmEFKs/i6/1BeIoFY86iavbKzELPlh9R/SLGn0eSfV
3gJzoVHR3HRXvnT6ERWm+Wfs9xiYcvG/jrbNsBiOF6QIqHN/v7Bv4xDdr+LLHJeoSALtiKecCcsb
W8lvvCuASSqhsXXHU+T4XOSC90xXCsED+GUiAzIKsxTSgg7C9HF2WMCrsUkhYRAOAgARwwxnTRMj
bmzFIkvQvOxWpGHUStDfbhi+XqJalxEXg5wcHrRoxoy4q09uLTR1fiKm6hNArFnkjzm+XXJ8Bl2A
tUcsVFSFmK/3oRBMfRm3aI4jyAuH6ZXKHaX2DG1uTvyvZvlCcg8L+z4/HZvRT/7klKjdseyr8I43
LTLDYKX48/5AWLwhr5jHtlwdsTAuNHtnxcrN+Tmt46QesP5zpNJgfLqU/q+nxlHUGcFE4+cER9UY
aZuPJIIaIQtFpkvWJGGC0/t3e9SnVPWnrZ1nw+Ka+LvzPuBSN/+56ZBAbAtmmUlTE3qfOtjNuwaK
Hj+J1zuFP8iZp6nJPgO4VKu/yrPF6La9ebtF+ECExPB7LJly762CnCKIavnkd0lL1CDIoUFkIFv1
kLhnb7k0QMGnxBpvsXOnwFc3wgzjWZe+KXzOJGBAzLj45aLqhnLTallk5dBB3WxWShlHrmyhRuqG
A33n47sw3kuA1rE/t4i4H6ysITRP1W4CqORRpcG2HXVDXIBbL7G6k3xyn2q+tHFVAD5dvFSPWDUt
XQjTAYz/sBjYLS/eN48HTBishSN1cyLzZM/JgJkbMzJfTl09+GtBmXIbpyx1+AKvboFDYLosC6W2
cVsexQjiSyaBoQasFMcp5gn4m46HnwHccN/1ioc9H9IHpja2SdEqWLbJwblb5V7Xh6iwZZ0xQUlo
PeaaW1xYeWSLS+x7ePywfF8oW9bHU7NsuJ8vNW2UFzPWVhCLFRv0VksRoDBhIvRV3S0DhWHBkZp3
QdqEns23Q96C1XQ5iQLyCGa8m3WyjFTzQ0OeEkvGLr/FVhsXa/Nxm7YFuwUAv2Jk0VdlfrMh5Yqh
2ypSZLk/ynmp+b3lIMvTIY4oZ7X9xcn4tEeHYBorEOQkeunU9duMuROMi9xedLI3E8bRzWaFt+j5
0Ug53JEWiXj755luK5trR0fpXX8+mHsLsOj3zTk6twus+kUsRw41UjWhUNZsjacIBNscAWnPja1Z
pXh389sxPpi6iyHJDL+10nQ9BWNamANKaJmxsq8UHU89gDC7J90MkF7QjIxOMOIXwMB8E+MFt7vB
zLquQM2zwgkr0pZLmm7ZsGFPwPS4gNFxGk+rA79zNEIIZ18v/KNc/Mj6pCi5MiAvpp6TlZuc3fTe
2+BMBMm4JQOqoiJSJ+HaLkTSGcdBrF9UcGX0aNuF/axZrEkfo9GZO2yRobHCqPEe8MW+L0IU3uND
JH0dgLB1MDH2TdNp4AmSJlz61JwKbNSZVkCpg1wY8C0CLEGR63frDAUJSpGrMR/b11PjDCOTxj7+
N7bxIqp4munirm4SspjuEnF9fJdRykWCtVGMxlgbYpdED3IYvOkYUgORVawdJLZtnN8qWmo5XW8V
1gpdfi7lCakVscyYUtiCrgV1LQqUuyhghBMtHkcsWzMXCUcabf2sYVJxmg2xZ01e2/IOn6KvDIU1
xcWN112qmV+SQaQV1DgN1XiB6qCTm75u/KWzADM62UtvV6Fw1WqeZs5Zbtllu1VTmAb3U7t4FGCP
bnM+kW4DEjuJcB028KbYpfWixDxzRABXRKON0SX23ga9Cl29KRj55m/9Owp77VK2jMXqrFpUvcpC
H8NtPKRX264+jxsvQGNSTlClhAdr+SzlkCoIDmp1laivUtyyKXxaXfj57BZKvKyp9W6W3oHh/6Lw
YOXTHJWb9Uu/KqesBZ1CkQMmepykaRY+jMT7mj1BrDzsdux0lhKOsVqc1tB61db5QgJC36whrKG/
z0MWC6p/1ldp3pBt4JxSV/F95OpFnH2JV6upxQs5buFFR5cCCYSjEYJvKm3FFhDZOTjlI+kHh/Ku
ZS/gDrFZjWg8iVN+FrIDdYG7pfTSAVX93xEzhBwJp6ndmnsfqrRZCUqmTQGJVtSj542q5Fxwi+h/
qQGmfZkLm9hprOOw9pustnEWAHtn6pFwGUE8HRJWgd185poZKgYUz7ZYy6T0tkWWSVW9PfTJ33wk
W2HiiFXcC0HhT/yt9dOs7VSSDZiUYPRFy6GKgxPFmjRLE+XjEX4O98s1Y/iJmHRcdM9IbnPTVH5b
bTNUQ4pY/QdvoUtWjTr/g/p0PCFkBacwdLFDIsPB+baqukwfw9iF2Dxm8EsFDxTItkmdkebE1YjM
6Ue8E47rJ2MrMlkX8kvglBI/Q/8NM8wG/fY28LFeItq9CY1cyviix3DOpxKW/W0k0rndlV0QymSS
eDEzZ/JHpemKPyBaCGCPKjPpD/v3NHMLmSmdHzin5L8uO4HPzRlMtJSDevG8ZEhQCjAAYIBzcaGS
NLahZ0IYN5pIO3A1BIKv5TlnfPJYdv66l5NtIh6DWWkHJECKOFoPFmMHVy1pH3E9K8mnR9suopPe
l+xumN+XA7NNd9lWoPNskEJEnLndSebpV1NDqZVRgEQVeRMhYeaKknh3zELU6o+yzlrU4pRZUFNH
XaF5JOCS+aoZ1lvPfUUPYYo6awFOSAY3dwfx0v3wzj6XyeDpaJouMFxoHfiL/KaBs8EH9vuoiW1y
i1sUx4Mv/uqmM3ezNjsoquPTJtvAusxvCDF8c51RcQ9/M4R2Q90d4XdsFq9H10c+ZNfUw9pRvJLf
KRY3JhyQzDdoOV2hIk/IQKrO4TIoPYHK6nIDXhKBrzRTGS7a28JcqWJPlWxGIDV+msjf5DA/RvFI
PftG+QsFs7GIS/a2oM/ImokP7x/TOXY+6Nyn5CiKludhzgzHapT4NraHn0GM1VmB1iw0YCjerGid
soTeEnxBieJu1sMROb0YIIOVZ2nv3noPYyig/Rwo2ePJuzFfM8Kz5vQZYOn7zz1+LSI5IVP+0kb/
vprkWWoIKkaBoCKAhyxHqqhpjFy+Dhl8MWwIryvTbMzcGVGhEW5PxyPbH9J9bQqjl7fhyELt7Og/
Bqfle7LvBMXf7w+aX+/1BRC9vR7PFC6T8SDx8x28w407a8C8RVHK89iZH6KNA6bwEedIzRoZ/DHw
z+J/7I/23LQ04PnWKU8EHjlpIB8FdQ0TO8qpYGy5QFhFV8gDCEfX50qbS/e2zWvvi5W1VH0l+Fg/
s+PlfhE/1/JERqsZ7Q3S5hMM60+u82PspWdXjZnMszoLy92Lx5tk/hTc68zqbsDzsTj9D5zUoQH5
Fzqdk7U3q7EynXQZwDIrVjxh/DGIyjazIzA7YeWv+3vTa746HcIBE6Tsw4ddiEChBhISdsIX4y0+
uPdUCZuAnaBTz8fXuzmpJe/U8FtgJcZQlpi59Aw8T6VpHQe53uCZdD3KX8z6InvndhX32GSntyZi
nxpwQ4JaoxjwOG+5viz9LLEWqTWSTRFgyn0qC2Vtw4Bx+J1XJWEG9XGHQZgPQrON6lSS7lY8fHSY
WGrLxKP1wKhkLumMUaAj/oOOLOd2749tFf7GLzeqlPf5vb0dVGFKqfFyX4XsV9aNuzuDQGiBPs3U
f3X/kCvpfLGdOv6auE3WHk3euYw0ZWsJbvmw0j4skmjV6rsvzOeMr4R73NrANgn5ji1IDGD6AOfy
kmXc6Q2dxWywSNXXsVbCw2ANYA4QkBS7s4PIEIJ9GECcdLsO0DgPrM9oHEIY2ghg4nx0aSfhpPJ9
YBXLTHnixlABmaui4ptfYHs5R2IGALW7e0bprPVKhW8saHL8N45ih+IBP+W5zW1YIK1Gh+2zkoRr
MFfeNQw5Ogc5mtcE0OG0rpwUz2fGWY4rCFY2YsDisZ+mQMh7do0hVmwm5FYFQvcYS+HLe9aMiloe
dNCUghHuvtF6X0Z3KMS4pN64qgwNQfux2Nu4HCpOoGXvUtoXQ8RBg4uhOVAbB0Bz5H7cDRe92z11
8EkwZrLuPsvNzU3mn/8X9ErpClsfVyxe0nAtiYX4Ygzyx2mcm7ur2McRt7rJRffLdyJVI+LudnaR
lx3/HJwXE0piPgayMkl2WNIVnVS/HZQCnv1q68Wsw0rkQfKNXpowsKAzn6N9Toq6DDECNshUdeLJ
JpnsdlffNCPSsHXfcGB00deGxF09FoRPkgHGjXZEW1VqEJ02tj4h+TimIVOcPXmDqm5k/xoKTi1/
C7yetvqC45v5F8kxDZdak+8NRXKnGdOSQ4EFrs5EUMkf260yg2xlYBgNBPFIZz+DoFjcKDlh6jss
1knIFdURbYTKz8SZtyd2+jN4f3bh+F1AMu3RAsFAyTanbeB4qKJRn5ffbOeKBTmVmgKGjJVNXAuc
lAq1UluG9VZrBY/7UDFqiII3ZxDt+4Iv+SDjc2W9sH25Vfv+pebufb3RTMf/7SfmfJGb6LDNvjo9
a6zA7sgLgBZRmDu7hNvq8VLuvWPlR8X4Qqs3wf+1Crv1lZhoMkCn36zJSQXqcoz6qn5+sek+InWs
NHvLEKT9B0uc2u5vvvaD6PbjkrVFJWDwyqZdxs8frXvd9hqKT9FlXwkdJA3GCX9PlhU9oqtHj2RU
toNXx/HB/gNIsyM8AeeFP1zJ3OshsWAKNngCOGGhmZCqZg5Q2MO3qVF20RgkAUAqwAVgJxJon0wl
yaOGXNdR/IHHvP5NpkBPHOdtHKf9CJVjSMHJjIqozAJjNK69a7LUurwAZNFCW4PVq5rDSkQFPAOc
FHX8WQJT3t7S8NBSVBE9Ho7DM7hpxftV+53BHK5RvaBGMCvaQNGoSBHs9cZ8zQ63HLMG6OzUKvBM
cb29q0yK8ULbyqx/lyW6nwMiYPXRQ9XEsd91duzLuYk//ozDkX/dizWfdqhn3pu2P4WVytZfP2Fx
2V4FtjeV6Pg352B4hqUye2SHQKmKcLvkNPr+R7wRWbSAJFTEsj7ipxZqYYX+Lb4yLQ6wTMoDPlKK
JCOeqcvCEcyPA8bZd3pWxj/Vs2Vl3/DeahRKNzRXZxFFlY3Ulw4t19i4u4NZ/VLS0vf3envsKs3t
xO31p4PXwLEmFVHaIODzuOKpuyqSTrIchoZ6I+GG3LrjXVHu4VOZ3myR6+UYPSX/bvwYXtNvz7Wu
igUhDBHZ1dmb8lIoAfj+A3e2NW9RancUoZWjW9GjjsmPLcvi3EHmRAzZFbIseR9Cd/Pd9Qem9Jx7
X0pdZ12s8ZPpCeYBctLw3OxmqcbPMaxRFuyu/uv9n6PbfrAwodwsNWkPKf8WcCiICqlmXsQxvpaz
HpXLTHUlbD/XGMT6FiuMfbEwl/ExgonsrHaw7xAxJBkjXZ6onsGk8OSNBbKuy1s6psTNXU5Liudo
iAIzqKRq+TOEI+H1wztxRbIw7Hju9xjvnODZ2StNrRCIMqwBcsxLEGwQN3F7Z5H8aVD6XxJi0Hm9
l4C/mbA5bAD/XkUta+EBaDiefXBFw9zj5ThuP9ClPwzatiTgTPIY82ODQ8lf5suijnw27yjfPGVO
2oDx5dmZ4FkiiYUKCWpbuxUYQxGQZ/eM0TWromS2+JECqQkQphhAtx6N3/OIRS88cUq0xQEeeH1l
NRDM6CEsvWYGNX/H3LMViviMIFD9DLgfqCiRR+nV64psjBpBi5aDn3WlBx9gehEqzRNWC2IYLo2w
PjwqP3MyGUtMZPEl99cGDb8uhHVLdZp2hKcBBsdqu68RqtxvlbniGMIhT38UBgfaLTh9vWPSmEdA
dkNIWTXu2jDBQlchZM9nlXqG9b23Y9HGioajfRl4qOMENwCxg5/3fC84mSir05FlvznpAUdAZ413
DI+by7HLhuanNAqhdm6yHsY0jrm8HAXcKKEJNqZJjY99YRrIFObwU+7LRkZjsvXCHeFY32QG35iC
hUN+hagcSW6LNNQVVtjkT4bpLdOtXdyUiTNLvqNzawJv+3XH7wJuLWF+Y0wtAqJ6z54j4QaWKTq+
JvEDgt8gpU+YCk6M8+y9HPCR+HN/XoGNIg+cW2el5zgdawxAz1BMbR3NhiZDaf5DTLyPELGrWh1T
pqE8tdAVHI4NLtrNSoMBxiYnUsM8b7reKo/4m3myv+shwx+tVX7gR4Xn/bliZrX2AzpQR0tM9f1X
PjrgTIILGlT1JACdmXu18JTEh5usDhVFN0bxTJFpxGob0VullH6tFy6HLVOByfcd4djB/m9DSrw6
qfE9pjBq676CHqjzYrXf3Kwzax2YvQW20/DT1buAKQjQ10eXfYR/O2jd5t9m67Rc4awTN5ThoU8c
g44AhVpplvSooHT3GPQFuwfB5LraVBiUcEck8/GjOC3tvvBN6nXhEHSubY/wDv/nUjnwyJvhGZ6a
j8ScieJPZyqqnLD76i50NNxn//tnJq2Tv2FCaDOShGlSKnwpmXUrzih5CgaC15IJWShnRT+3YQyu
L2YGYw+XN7kDxoBUkP39G6bpD0L5fog07Mr1Ju9GQ8CRed2Uf6Jbv2pEK6b+/4dgPO5aBXG2Xkt4
/U1TztodcqQeJ5FNpJOf3b10UESesNMAYHnlfEkS4azLDaKNj7vwmCyUNOs9dvfwmx2l5GBdsKkE
O+myIcasdL3+rMQWLJdef1Lb/OwuVOXZWfdFqxButfsxiu3pN7mT+1lICNrzV4Fjklui0JwRLGnh
lmXwyC8giEBalmW7E9aHUYT8baHm+ZaGa01U8IsT+zTVVof+7M/oEChoAkjdIwmRxRGXBZenBsLk
FCeyaFyQjSNcUtAnbs3QO+z0cvpS4hQFny9dYHhCQB0JihRSGaBta9pZ98OJUyg0AUc0B62A8ig4
kRC0uEFDZn20SObrWo/9sOttY4vc8+6YH0SsdSsrODgd5RKgmbscmyAfuV9uTD12JDEyuSbbl3iR
imC5OUAlf36KFId1dp8tibc2qaP2Nuvdq2cmWQC7G8biz7QZ33M4vujeHDYkFoH1fYEBaNkDJXMs
A+9S06sJGMKyUXCcK5QGjcXgfU5A/bZ0kbTmjW++R103ubDeH5QyuHgLy2ST7KkucXs88IMAyFNT
RFnUJdmOWDjlZlCrWRqzETOKwSW/7pTZd/JlPmdh8cUFG9hZnRi1UAaIVozBZFNtnDumqUeagvtj
xAiZJt0DH64ch8kG1vN3FGMABfVKodrVvYAr7EMVez3limXdgwuTKWof/a28zSQ9OOB2EBWUb9RO
BFteRFDvGHadvkNGJfDXN2BJEgI/V34n0I0J5XQsCXEYFdBkHp0RbDMBEi6+ycfrVRHU6sv8zA03
VBfAEt0Nnx4FmrptHZ4phPfHgIy25YbOARrlH6BeLbTIEbHPLQl8uGi6uNyI4pe22EgmuJR3Hz0R
LkvE9kN1d+OPHSCJ/qpf++R1KgQc+q8SLEY2IAqPebahDx8QEXzXi4T88OQLgmKcsDjKffZA9nw+
yKFGC5sxSrSmZWax7+9U6T3pDYxmAS2QS9k6WXpToC6R5A43g2zhNtV/KwOvGQHZMia1kNe5Fviv
24lgdQBANK5sCini9VIPan9MdQbtSp2NRjS+rL5AlBXpP+6VnLJ6wXX44hTDXSDnJUubVSy5H3dV
p3dgmMZL1feDwzn/AK9Tiu57ytknNjjv6/ij3sziAZ1R+VpBR2BkU5dvWWZlWaEwbjuaKVX0dY8J
JH9kXzNhLO97piu8yHdSxT9Mm082AUjFimgObmDuB2YPfcrDufWWAOv/c/T/xEEmqYzC8tMiqL19
udQeCz7zX+cRZWWQk/C37YVIEXmO34mzIr6UHiHcFPUYjand98qWIa/rSWT/PVIMxWuArUMdeA//
nbkpkp488tdvpN2Dl5OE55Y9HLrzldfSjUF917EKpU8qnkUT1w8UPTjVgvi8d1lgfWuiXA2LgkRr
FZTca1GAvWvDHSgO6DbNE80w6F51XL2Kg5BwRUQRnRCzFqi8yaZtqz7R01rfZ6d3IrVQtNTcp83K
eqBbgonnT5zFfdpHuOcuBGXMNdTM6ulGqJSHcwDUtrRUzdiXBAfGofeHSUVHPlHf8ywTicbnROCb
iosyHfAqClf+v0FXjZYLASVgnTzSzkUu8WHUW2jcn5kxPF0b2z2jEDnmHGq3dbGvbnzq94yFiS9b
mEvSmVKBjxdA3S3wAHIJjYVD11Ul/w7/wSj58GYlT3irLef3mxDHnSb5b7LXLLS9fTrv1Sh7TOyy
eFxXfgEHHzTrDPW5/iukBSLw7FNnkJlRKoYRXb5rxI5pLIb86CAdeziN0h58gxLQd/FM/Uu/krZW
NUks/sSJv26TCjZOkKysAywhdRHbnRPE006E7aNdgSm0Cn0qPDhrMEV0IB3yWWEPNAmGzISsYDD8
wJNSAj+zm7apucDpgtbdN4gObJPUE7VrTep/uavyov3iJU/xGFDh61+ubKldPrnZQbUWKpd8NQEC
yMdFxMZJqai73VT9FfStS+hjvTvYhRnUsaP/IFOb45EDdjdDGsqDPwBfaOZwllsSpn0UnVHEvfNN
H74I0hoWMf+fgp92uMCk855AIr4pfq7Q375r0+ds7/hpabhG3x2klCsihKl62URRMrEoDHig3N1J
k0acKucAMzmI9w7QziiLSnXJaqVOb80U5c9QYrsL+OSuLqQu8T7B91gVrDpO6kuoZuUHkfQzXCOC
CSiQJEp5IIsp3xBZaMONRotYAVJCJKT0dZoW0UR+lA2ciCoWpIfXC+CmoTJl06hARwb35/rKfouB
6nrAkilg8tIUOi4za3eSjU2K/xMIB4i/A5FZTMo8LhrDtisZxD2MqJignN5PjTCDn5IaVCmYLaTS
wX1DtYIaFjUxYZMttOHiQNvvY97l5ILwqlxdqxE2nZAgHElAEBSfg3WobNlOsF+jRgwkTbl7W4KQ
jTvUBiO8//NeFSSjx59fQ2dQd3j3CD/aKp/iJIHesT/MsyI21IqmyTulBXdGQmCp3vLXhwezDGGA
OeQdz+Wp1U/oyGd5VaihwTGtv3BwXyrlSjMrQ7F/thGE5S76BmHBbuJC6lm7UPUYuNEeb7PKYKQV
wrYC4IkaibAZG9wg98+p5jDs4AzIBVof9RvNxWWDitbVCLtPPE4RkdrDmeZoo9iJJ0CXULwO9aYa
8clHL32E4cRSMGJmVYDtihdj8fr5uYOQ0ipvrlIMXdXpe1c511PFX2hjQz0H2cC9k2xDCYoZdDhK
yVK6n5HwJsl3ZiR98IAQVTYYm8ETqRPXAmHUnFeaHTwZdioG4j976hbz3QXSHn4XoqtPpQgUSjYc
MxjO9BmLyEVEhA7tEW5X8odbiVLCpBxJDI4ODu0BHxsoWebV1hDDRZ/L8XCoAcSVdzlrlBLInMAT
7jzhaSwnFyZEg8MbknqPjuZkmm5pNc6Nu6Ecg8d0ax1p3Xgay/gbT5MYYKNzzQEzF0LgwJla2qpM
s1nhnt+wWt8u383wMkcMI4tVDqIdXWMq3Y6pMfH48eFOavS/tvpTm5yx3EWZ26DZXE2cBMjGw2uv
wS/1gksgdZYQSG1KQu0+YuQcPFte9epjmzbN1wfgn7j2W7FLaDhj5Dk8qtNb8xlrDlC7eZUNbGXK
pNwVyvNsxLaUJE2y8Ff5oq/GGn92gjhw5qYTXYLwqC5SX9qbvANcLIgqYbRtwSFC0dPLS5+VfZjZ
hgTmI1k167uaW4qfnp0Skrz2fLDK7GxJuIG1q5ClJMQ41oip+RBjnTDtvYdIP5IJp/wi15BG5KFq
B0rh1RBDL2mgaJuemTw4LAGha2ibnsQEcB4/w9H3hr+/FAdR0OCfCpK8pCofNEa7tH1Knu0bOxUq
CA+9EMHOLCEG7hfUpVzRZQRP+bZ8WcdGN8WxPZyZPs5QZcKrCnuUlMwQlwLsTi1VkuY4OgUzjkGJ
31LSOhEMXIOnYWqkY23swCFdUjLbpQ+11lDFvv+DkS4YcgJ880d64CXsVRIQ8mA3Lt+ko7Ht8k1d
BwL7xOb0czuZBS8HqcGMn+pbU0GCD4W7RuAigLJ5N2YplcZomvvJBa0SFA+TeNuTzQXZ39ABzC22
5pTlAG3SXfZbtcf4r4+MQJlyQFDgpHkZ7K2wBC4mznWU6Zajk0CdFeWiIsLdBgHsqFkr2TAbsHqc
KZ2DhCTXL60WMD2/cr1eDl41IMgoLCqNsrCwLZesLOZhFJ4L+yD4Xh50AuMN9wYUaKy6hCb1W4wx
SoypCo9Nbs+P5/YI0r3dJe1T0g4/iYMUHSYYkC9BwtmbkwmaDWdozChVVe7sZqSQj83hATedZACj
mw7v93V5uaxekBDji1UxDMDiRteN7bgS3kCNBzH0BwNb4rftVgBWKGiKxgL5FjuU8GqcHpIz/4LE
sI7N9NX9RETGcqPpzPEiR5hJn9NCOQr/ih8MJcLYRG2q2pNuBcfu5nakUPd1yVVBDut1lED74xRB
yspoWTbxww94JG3yrYednRaPguQrG4d6fjfkCoea4l6MmmShSjdlYC4W/gVh/G2/aPmYWRBOflVy
7LpEhE2OnzTLwp7cgcmdbHCJff78wfAeLOSTw9SBxmr1T/0HZKMZ2AAe/tKM1iqiJ2umXTOPTXe7
82Llqq15gJWlcu/U1K1rOGYZuE7AXXcuMh3PwP3gXQw9fnuvqKX+fSuy6N4YlyAlzt8fmyppWhZb
6gnpx3AqZREtGSxvSygOz90ey3SWskRA5jONtrU5UUTs0YQ/89FCePI0mk5MLNanSorGssTsBc9Q
a/vQd1eHFd6LUjrypwtLrHQIBFzidJlbE84c+IQt+aLIMzWyXUnfEn4Tnt9r52Suu4t0WTKgxM01
su1uH4VMJPddiJNY28sQqLfYY0//QLjlJymhZZI75EZmSIzOt7jilTjMfp9kTjn7fGAOAfldtzCw
mwVsejl4tA5qkieA4n2CgWlZZEzCjV38BVrhpx1VMMkIep63e7uqFo7q7gfRytvobFIpBNA3paCX
uFMZDQRS3LfdXxITJPL2/bTfs2hPF7s7fduKLLKP+l7s1YA0D52WdOUDX1oOtaySK9EQb34t3Hyq
AmQppz4owjHgHtD8f1RydVwnOd8psOv0wiHSh+M5TDKKvnVJfY+Kq93FXRL8IGJoQ8GyMrIVW1yF
0QZDR+/aE7Ob6ucApTaAhER6Q9agUWlVIg3zWXxUzJ0BneHqoc0Tdf43xwMlu9T9/y6bupfDWnVI
0ppFt/Hgy+lZ7tmR76ydSFdHcPjYnUdkFHEn6PalJcYvEIOZPGvfTGW3vSpa07No8OHy1RMMazwy
ga7ZYTVfgNRuMdVEo72ViRbinxmGQucXqzHmFyvrAZkmmZWKcCjw1kEi8hlye/8YXVnfUq4UFmYC
rTNk1hMirz1LtwFFJJ2czZUSTa3+n46VUfHBEVIVWyA+fY+XzDdfur68+pO1rFeRbY3OlTX+OMd/
y3YdeC1D1Pys8c9Hv/B3syA0ZOMdVCQhOyuxKKzyEhnQ++Q33N1zegj1BxSoVMbA9aiIY4ezcehQ
BhEyysir4WxtNiCJ8eQHakLcQaoi37Jr7cdm0kdACwimE7rfQAHG/T9gS4xEFpNCNRIMfWzmPWTf
JD74I8zvYki50Pu2ov2BBK+IOwyvafMjQ6SC7JkRp7bGMKnBcGYXs7aXCDa2/NJrFKmWQTTMj8jo
xr2TngQ7RuLIUQYQhVke2C5JPOUImbN3abPZICegHBGZAkqvTvG5rW/98b0NZrcx8crBsvDye74C
GdyR9etQ7QX67QpJtrsMCPCZQIRj6RkZXw4lwD0SvY82MroJYPULhJF4r71izK9K1Az8/hLt9AkN
jO+HDTy4EidxoLf5CTnT6nOq3H8+s+M10ZyJZamFjyMfJ3Xmix1G26EL7buBdI+FOTFPFG686ZUs
WVN34h2Ec985LpxDsZhC2dxwX/7a84iLEKiq3FQCBszh6r1g1g/QwsyMTf2HhEv4PDLMone28xRe
UwANuv17P7HbPhaNkvkwCaV9+PgAT5mV/ZqJtmmy3x/RXqJDkgxYcNI4Qi3+rJis/b7KEPjF6Exs
pyWZX1pf76q6lx9wTr/Tq0eZGdAq0NYjPf7WoZt4EAYmeMVciRAJttwlCOMx99S+iebb0xwTVwPr
TfSoFD8Mu2xq/nzwA2mpulZfvMD9F8CzyP1zaqEfoPdcgGMAvSXn9jf3bJGywbfjfeZ9VcMnv4wV
h3R/AyW4TIRcMCOAEXntCMDAlhpOS2vAZNGDcM+/9Iovoo5coAQtDu4tw7qwjPjOCgB/h4l/VzHK
m5G7u3ReB/Z+1RFTDmicN2ESNdhBocNL2DP012zsw4UjnyY6oylcqbP3Rb5R1Jg/bYPVtJO1ifOu
WpT5iv5zxbE/h6uiYqZdheVOucNYA50dOQK/q4f5VBauTsgdhdh1lKWLFMSiIaf7uSL8y1z6HnEm
15ct5bMJUUHgRugG99l3BntumMJCd9Z/OIws/5LP9inTyeIrXE2Rrr8au3H/I+P63PU7n9Brh334
MR05zV23O6tGD/bHxX2DtiU+o6cqax7lJxigVduEjq4ECUdJ+HLm81pTo2HSxR1Uzafx0r8uJVKU
h0wnbZwYOU7oI8mbnALb9UTQppDTXpVoy2AdevSbMmz+WRpNH6SBMmlBGZG8RDeNX1e9yKAJyCSB
ymGkNHgSgCzD/lQKXtYxs3Y/0O1mwGLt9pj3G78n1YqyLSYfAzs5QbsiEKyixwpSslRFJ2T7NScC
bpv0V9ElC/1bGXBO/uj7VlQ4XASHf7Slkz/VVMaZzq9Qe55/PWe68AODS2b4vW/NH8NK4Ci3c3Iq
785KsQCwKRRKXn7sIX/AYzQfny3NwESzURHdc60Tu8zXtzeJ/aIUXNTRF849L7pm3q7ZxEwKvUiY
u3pmy2z5U9bP49YZVIQHmI5dwwk//GotwR8uLZutMu7clijPnnWkB/LZygyWssOuwDMxeMSRLnoz
AWEFzvaMhSu3NhXaluJxaWJaqoFAY49GKTMY7QqCUX5qs/BVwvkmKfH9JiJDLHwPzTfi+pptGCmu
v89f4gfWJlO8Phdn1Pw1A9QKA3RpVhLfs8JvZXf9o+rIuQDu1e8jULxIz38VkYMpyhqUAO+S4yKX
Vn5qYYMsiPKuDu5njZ63VilCq7CEMmtHaCytAbjAldcxH1sC4RYtwqwT1Wsg41T5aJqtC/Jrkr1e
zxewgnICulHIOg5/vtSSKYSSerq87fDgs8JX5ktlFu+L43aH030Z6mrIsbD6kArf93AY5gijGQMe
UtDwcmf3uJBKI3HlW6HSNdF9ypKTmfEHowtVP0CziScFyDdTVsh4eiET7haVGu0Nu3QTtVRQTCA4
7hc9xb6LunfGf68Ek9atQPwNCCV6DqySDk3y0YPslnB+/3pw+zvwBSOKfLfs2HM6pJxNpkWYiqa7
2lRDqU90Qy4hg9CNP1VqMk0g+SwID633WfK+EbgrJ/cqUpK1XjSP2SLatbjy9nFBUzWEVCavaHfV
bu6/jtJx1UaUrhJCo+0vx4unWRSebB3+UBdPNE5s7E8IS+RFRUewXgZDF3tDBGGYQiqCTfNoxo+s
xEefmyhRHcoP+apkG4ewRALPlf6M1HxzPT70edkQeWl9LvNoAFOl9M3xNku1eFHVtl7UmUJEPfj2
OcfCBwbhFzgM4feh6E+abCZz+cxLmwylgUic8Po2tYo+gM7PPToXV6t99ZOQ83qPVofswcLNch6q
nGepO1Q9NisUAxB23RTh+e7Gydm0OUi/M6F9AR2NPzCnKHSBI53VQPEqk9gjBQWZ9XGst0qsqym/
otpvGUp3UPIbtnnaIXtp6/9/ar3W6YFXTooR7NrMPnz+RkT56xTbu7zoOyFT/zv4m/i82/yzAe1k
W0EI/QdwzhMm/i3PfqfsA1wN81dJ2L/cPS3znOH5bWnaeUqznrMXqk6paF6GhRakM4nmFL8Hm7aV
51hES13+ExEa++elZlfG5JY+Skdw59CI+dyiRG6EJACJME7HU2YVdHJL0AuLuxuC/FDhcQnZy+5a
P0tfCcVI0s4Og6vDaDGvI9hvgRqMDyMaoGSCuDIVghl9ua8JAX9QlVOYwg9W/Ur1ibZ3HLex45mK
gMbuJWrioXhMz6R1QJgPJEsAbdPc6juZfrL5/4ge25u1tJoZmo0xSqUntdBOzaoUxqHn++7kb1s/
U/BKguTWrehKPcjqfnRrkmAm8U/Bl05dm5GX7F0aefLCN7cLGOML/p6EYPgFP4H5TTfVnq+AU+X1
gMc0ejFOc4DBktYcRoy53cXDhqn6VlX79V2A0kPCPuuvQ7Prgw2ATpEXbEv0fO9Y64EHlyQkG4kQ
DrtPDAgPQrxAFDc77SYe6J5gyMvM8Imt0vRgwgOn25VgqWWQf3n9q+O1dTQC2kYD2QpGFIvvaVeh
7M3RvLMdUOkBw2Xy9yphVnbmkgHouFR5lU3RwAG12D9pvPM9DXzuVtIVOsh951Z4A0NQvTylBDfc
nq6Mjzwuhf3L6L6zuy2M8eSBfrB3H9E3Qmsk7RxT0Pmb/jX70o60wYvMIjelZttwmJb8d47JjzhY
+VfLBzwa+Kfw/vp9K/6swFs/1w+FUXKvGdqNTsJr8h4I3tDIUwSeX3cRmqDApQHipgJkP4ugkXPi
qSlmYpnIh2acBtqvz39B0/Z6Gwc78uTX/VJk1oXieabN6hI/mTy80tIY/AxrzPj6IUlppMLIjZLU
ZuiCQsKwGlBaDEYBRkdpLR3Pmxyg0HYSiJV4J1Xpd7LSah8iWemrt8VnZMxLVgVWFVvliG8gjeuW
BsMPFzHd7XOkcO8wer3tFaC5mZWxwgOBuoGmQ5ddtzGnViupm1lOcDLUvR5S0IW2du0IwgwqLjWJ
o6XtB3uM8fzAKCZ1dIJFWOax2+Ju/seuXdU9ka6UurXQVknnl+bQ6jdSp4p8xbS3Md5RxFWcJPr0
OvG85ySDJNVSsfQsQwEn6CZDjPfQAG5PjS9pRN9X12Ti5xbZb5RFC8vZrG/K3d5taBfQqChkTGNN
Xe/r0b4lSfHEXc/VTfygwGB5wlYkpFu9vz6rfHPkUfrWhEsg5ypEwftAiuhQlTAHGFeY+4BNSYG7
tpJjAWbd6enxDOsbq6IOaFKIicbxXES+/UsqiTI8V0583XCTxgvpw+vbnQ5UAq75gQ5wiLkyfZDN
Z6APCQ/W85Q5s9cpyrq07cTi/fkZYjscykjYKSzXQvvh0Nyxu5iTOPQomnd/LYghnV6DXIFvxYK3
67yTummlApheUaLULEK7knVSpSseTncWaSLRwfRg4a6d8Cu1tFwh3DmF75XEV9meQDvs1Fqsqots
JlUlNlCn8z8XXgc+Qj4qHGFcp1ziBQANNWB5Y4YshVf4N6IxYryhw1HhjEvGCq8Ha30G+M0aZ0yd
u/9QjKp9sdI0FagyZv2l7YZG3bt6S403PiWfHs4Ds/dGtCI7JCEK30xVFNbAl5gzCJ0Lsefrxebd
z9IDLAZLflxm3KqCaC7Hxm+HeQjv5DLPE79JVFyk93rM621nwIROkqdkN/N7xRPhpEbVycyY+oyd
zMpGU1hg4eoDngorEFtnn2h3vl3P7OrpMglwheUsGVOrBSPaDajznf6lGEh3+MhKAL3M4LRTbWkf
u5P7NvAhprzVuRYCzNYQoxXzN5LMp4AIm+PG3PPT84JBaJ4m26fTUFGxtsBPvzNcFgkA658c9+eh
suwYkPnKYHN4l+IXu0q1AmwECgEt8x82adde2Sl1zEoM6TevfXVS8qes03gCAsJlYDBMefg34Z+T
oZc9ClPF01ZPg60V+MCnNArEfLElEy8J08n1oJdGUrGz8eVsq58VwVYRWnQD+R4TF/za0mxKBWW3
JQin9USyit8C2fJ+tbv2LkjWTiZDREQbEp9dqgiraAC1OuLQnb26omKwnYl37ESkO+8Z8v+0CNNk
BBYAKTjUnfOiv5w85zspvH35gYtMH8cEvZT+ordRXj3qwDMzyNCe5qo3P3WVPPpRSoxNyWyanoF0
0lhmnl5c+ohRUXMkMhx9XJWQ95bNMS4rZQuhWHIgrkE5scQzMtCP/cogF+uQTdno5onOQ0+xwpRx
wehAUIh5FgwXHNz47R8QfhLi32QHSlwv+RkWARflUds3GWFYbYpEI+p09SE7Mm3EiBQdW5zPkaxy
Ri/djPSUz1Kgw7GWs15yVLNAyWogOdojE3UiLHsD3GXRFyHQuDfwbgnPyFgMGDB20P0ejVHPL7ts
JGfZV18rxNGUfLZZNW8mkPcazS9R4sKAZYnS4v18V+5ZK7lOovXUkVK3qsESJ+0FdDtFSf4QP3FM
ERqRdg/qUB+e8tyb0KjZtcfb649O103CjE1ahoU1DV7iM/FMQxwdLdBPeYLyTzbWGNIVdfJxE77M
w8XVCYZwk/lYqBYtpGAYl/5/d7wSUrKB6ns2dvqu+1TRryEjXVs8+bbIeNcQ9mRv2gLc4SdggqVB
oAOO2z0juGBsf2jGrKtErayykCNA3XAv/vv0fLfpPniKAquV9iWWX8tcyNDOzs5hNdYzOrFVAy20
1cq7WgYiP6ma/LKVHOLRLgw+qY9aMgedOUf4FlQ+sSTLwEMNrci1NPUgwS8WqNNoho3ZfpZv9W4D
LCL0gRjwHL15InCbtPViyllns5bZr1RkhblxcTEtAGw9SdGMk25ZjVMLqpLABo50JBNruTD2KgT8
qdB+z0lVByN6wkKC96J0t0K3WSedH+loQ/vSB2eTR8FOHBIIwE5ARTqEa31JRGlKRswfKXfKhAtF
AVq1HKaoSrsmrdNkhfeEp8+DnyYVGuqH5lklsXQN0rmHDUcqSwNAcwwLhbYAeb9j9oAFX8XMsVFC
iGKFHaaelYDinpZZcrNpc7/T1BblB4lLPZLv0JTGXflmf2mLJxp93qxENIqM83ZqcjWCuY6eLdCd
OPdEyCaGk3Z1Jb4PiQeCmfy9M9zR0MYlW2MKYfmCPxryIGNGybpdhT1w+0sbx/kxJ5wMA+v/Mvq+
EJDnsqXeltAksmgvC6gAbxrKKqAXjFhzId6RgbD6yD149uEJsmCO95HIoN6JRz1z5QiVikREAjMT
t7/XJRIzUmFZj+6vhSujpJ/wjC1BBciQ/e6zq36dPZATIcUFhIcbLdllLlPk/wXqqWhOtJiHHJCG
UilSc1YHmUC4qjWZx6cWVRKTVnrYzZsiyo1mxE4iJf1Y93PBwMLckEhTXRRIhiNNfV79NSGk6PdW
iV1lwpbFKHOIVWKGsPMLkiljkdg0M8QqNI8/h1Dj0V0YM+tMV12acOR+vFkCx1tVfWZWfyrz0gvF
IkwhZ3ag19fnoIW6o8O4thnMODuw9BNnkwPM2wnJRI3KIlucKH15e+O7VnkMOsGyf1/MY3nV5cSY
YTbemQ7Yxfr6owR7m97tdZnb2BsTbI43Nw/Rm0DN328PtQ/v2e/m9VRnfM40CHCA9TfeqabzNHXU
fzeXG1BkP76va/EhvfSakE8nWEvrapwXw/zXErIZwh0AR/zq4x0JaKfmIIVq7uU9Bdq73f1kAbXY
Y0/AWsMna1hvzk2iJFCfNEN8XqgBe9ZG7F2QtFS/GwFwVt8WT5KpH0JJd92Xn6TydBQy/1l1TIds
nsUuGvqEz3oqzW5O4Y34DDTAK20o/2j3TSiIN2x47c9iY75dnAhj5fkIRbG88tVFeqJc8Tz9Prid
D1O+hR2YaAWHJPhrRtiG4WmAJ0M8y3x5EZOTY8quaV7NcDMgU5q37smmtQlsviOqz/vA7F5Ml0Ue
8NindH3tu+qSAF9GmyRJDI0AXw2mJywbe79BBSFY2xGIOWDhgIFGkKVvrT/F2aEDmaPDORPpkjtL
FdvxcTqL8ZmkcGt8NxRpXwIRspEajyirKTs4XA9hiJb2wfvbLJ9rEN5QlymSiRX2+NO8ADzXytAZ
Wnu+6HblYB6R36ZtIVWCoAdBNFYk8JpkoYViHbLx1RNNebx1jLTcUJ6L0C3F+sX2p14tCDDjEUmh
AhHqZt1uQjnmI+apLqeO4pKlGMxxhVkUecZwz3vRsjMKDobCzkQAScGpgKJBHp69trUJrUpRaPHN
6cH8UaS8zdLkqy3SGA3l11WlgWLtw8U7te/Zq5250PK0viO92V/DdJeycLCDTyOLM8cV6JdTZoRh
/iHH87V0OdsMFRi5qZQxSMhNmSBbUDKGM386+aLCEk3YpnE1tGK4sZ4+JK43TCOqQgbuym90wIvj
TLbIr+C7OOYStfje6H3qgBFgR9yNLZwImBjYLCeYogXlNSfZQDMqrlPrWwiaqhQwlEfEhyOWngAa
zXYSLDpbYrnWnGRejL/XoIyqYG5Iu8l+hyq+cSD46IKkTAvORU9htiHyH1PLn9G1aFdy/9mBZleU
iqk3NEkRJYlebSlDIBiNsA2aOlLZ0et5vXOrigYWELE5rUpQtYdQffp7brgYmN44QgFR6GHs2KMY
obX6sUrPOG0aITN1dOEhHq/jw7AgYY8HmyZnWac6wBBfJ5F3GW0q3iMzYuLI0dePeMHsZ8mSH6yr
1za9m4TA0+d1UmDDYVhuV2hA+yQtQF8+NhOsIkLjZ0/1txOtOHPzc1aMRwlngZaAn0GhOvWD5Fvx
ZzdTI2hFFN9ULagNWRsbBREJ0NtWEhTWe1muwb4pQNN+cyqgmxmIRwMBes6Dl3hmUDMSS8y7ya0I
+2e1dJ7BVUjTGjf4Lc+pYnS1p2cRpWnuTU97/mFqk/iSXY8haYWZnxp3t7KHfmGmMpDGGYnBxLuy
y8FrSXVGjBj12hcb6Hx7xs4mpsYMGXY6ygaWD4puEEQQM0ppOAMGJM2vmzrlBjybuFfZUwfE0TEu
eFteL9tNKVl0MP6Q46sjwKuxGgy/3kalFKs//Edem+QbMrfhW2d6dLxhLK0L8rNL/jXpn37oUSdW
pFEPBr3jiErseMmXfgecNxko+VMZ2p7l1cLvXg5bXh0gMEKRy6lSncM8aSIjHH97h4E4BCXOKVkq
BtX87jmi8F0tAHZzmFPNK5l1lw5ghKsaZLFkZX2Kul+WHzZ/0Fo6mgyXKfJqQj5cl3FUh4UHiHUG
Q9GRsYdd7B7Nv5V4zoq2fbnBHb04t73seqimy7b70grbiqN6Wy7OyoGByOJtjF2+7iVy8AxlysEP
uRKo5P4R1JhdWT8R2tqhW+W/FRvxvtLfpASRkMc6QMtNOprrYglvInckH9/GYHsYeOXpJMD5wwlY
6p0da59ikHVWWkgBftQBTa0Wbk1aFk+q8dVFjoiJNrNxrLvKZ/ctAO5gmdRc7uNPtrhRN56FhD2h
STX6KYwDsBc5I0ZeMwPussAGxcKWpyRAGfOAf0MXTQhfFPh/ySKsYD3+fnKHVyNzPYvGd5SHJFxO
Hh4Zci+IZZc6IzhseZw0n3/gpXV4o2kzPq78y1rhW/IulV8GqRmaDaUtbym48snaBz0gV/84elBZ
LsVrk7y36o8WX2v1fnUa9fj6h/YjbWkhNw46pbEBvnzrFqN6dS0lZv2oLUhUacGGg3mQzQgvXqjU
SP16Y/XVsE1/MzeMTUHCONOPJVNMhUDWsXEkKeJVWPpaRhC0cpjMCAnrk8/hjvgNJ2rVmVbE6huv
vnL3Q2tzcxlL2Ps/YhLi7d67LEwIphkFU81atXWf0jVWjJK8s3N839wUFpn0yDu03jrlAq22bO06
hRD/YrN0OO6+naASQeVxqYIwoPAJqcZlff4O+/hjd+Cj7tkDu0hoZfs6bMw1E8kLufVlioAmTlVe
7pJ03BlewCUH72Xt99O5JV0CRe6+Ws+hEtLzcwL27F2Sxu/nHJRTZ/PGvqnSmecq/V6uCdyGs3WN
JyE4d3G3zPyqksQkSSQJqX/UgvFfH3FcQUwkzPuTxQrd5cvIXYhtur3qvuGShSlhH9+5uRIp4Ogb
4lUVlMyL0xtCY3J92S0ehpaeQ+0gUYWVsTYMiqhsm8S2UHC0RUpuu9g4GiXbEB4wND/UJSnUxKar
g80eXvhpkuQfopRFzPlMfQ8KRtsSowezgS1gsoRqbm+gAdPYFvC1ba/z+Huy1XdxIV7IbSy98Zgk
ykBsSw7x9wLJFyjJbN+8KW6uoQuggwkjaA5Lvh3HWPSXb/wqJezhQUWVurdUlTl5p9tmLPSW/f2d
pP8x/6h367NOvAQY0RnR9EHvaVZeo7X/BnfnmAa1NKsQgact7OGg5bKiSgrEh42MH+Rwwuiooq3W
CtrAqJ4usgJoZFW8OG9hzFcq1s4hDKvIe3JZZhBzjlz+WQNv6niyakAQYXTjQBBoOOzN8HOuYar7
6H9rnh7DSq2EVkIi6V5pSEjiWTrALGLth9Igxn/GHN6smrY9Y8m1Z3Qw55ngxvxpK0BNRHpOn/gC
4E7hNU/cUv1d+6vbtRyhZHR0xlCmyJBREBX0iTO4vrR33OrJcDVViXJfkzwGWSDLbjgHQUWtmwuY
vKlLrO8tp08+/UoKCnDOzlCwObgwZie5KRof+AQ0QiILssFhB0q+wj4hTBwbsR7zWnqThst68nMD
KJPSzo/WgEomJbXyrzhBnwOO2MeuMIwc3LE2lvf4qkmIxO/7G2nv9Sq/ex7FpUc+zPfyPt+KAptm
xOY0mTiFhfKxGYzMjD6tvWF3mpuhmnp5FxY/nGETmfYFWr0EHHJQFGFOpTITEuH6dhCN1W2SWBu8
JPemT3Su/tK6blPi3JPWtpLESXrKJpY1Ifmbr37kd9UrMgSfKdUsn7rTaXF09D4pSRyK2ugmmOc/
DVqmk4cLxuLOayDyChY6+x3QSgsCorE0+4q0h+IOfLSyp8UzU9QW3qDUUKS/bPLaETiVBpUC1J/n
wRL8L7fJaVhjLIOyQSuaW6xJPmepvIDSO7vBU153TDwNCqx1aKiiK4VhHPMW/hSdAZLIrDajdjCq
J6tbOVgnz/DpW/a7OICFx6N6SL1v3bEEaPuOCfbCD4bX6F+EVNmBnUYjOea6RPBhfmkqQmFlrDZZ
3w3vhc88hAIb9xBl27IEyTURHGj9jPa0zTdYOyEsAsugN2FMgJMhm44km+LLco+GcGM3edYanGHl
x9ctxqKnP8uQsiyFF2Py8SQiYmyDkvITe3ucZ775/HL5fOd9sQBHJvBlml+ylvDVz00Qm6qpJsaI
xEcvx6YmSC0SQ6zx0bTSnsOQGCYgod671VH/rJvUCotmVcb0rTFkGnlp6Gd20XV6lDOgqXNltNh8
ZYvOzxYIZWvDERjETdw5aGmVc9ztiXGTJB9m7Fta27PMH/x5vTNTTd5f6eLbklOEJTD6NZ8GODD1
dLqqaYOEAYd9GXEGF0MMxAwiSccONGm4c02TRCQJZZ92L5XyqaQvzxnNgg0l/+uyibbS/jJR+N9p
qMQKP73EI2+MOGu++JKlH9Yk5NorDcfqntKFkhzEN9tM2i5hZuWIeOJFLr+b0mFIqbpg33bHNxcX
l+m6zAQwUofrMhwoPMl0Hgk+wnrZS+uUbuDu2HWDa3Rm15H0TFz3cUfNw3OXrX0jwp8A66bZlPv6
qeHN4SNpJeOgdgc2Ktn7VZ91EUxiFJjMwf0dkOkk00cHc6bsz+y4noF3RXIQPRNCdVdpAHoT8iDd
7eIIjh4CYNBEXoxAQcC552rznEEiYuIR8szLcEnEYyc97VmTuchxWGV6j2RprBe6e0D2iJqATYEa
o3H4TAIprdSrWHwrqK1YSm5G64qXanzvJimeYWw8Bkw3N8W4vXtRLPet48zeKReBfj3uLo36MT1C
5C4lGdX9DxuPQqNjDsk/hAyIXka+XpZIZWC2zlJ/Uf1CjTnYcSx8iqLpY2huuw0y7hE2mA+n8GvO
3POUglWnDY40+gyLFaHuJQVjRhBg1ZkhaeRVpZZrp95vR0rjb6uFNG7Kk+xvt+Efy4+qkTSbcJgD
51dsWtwZKFXI26N/zp8gq/wlM0ZLvjUIf4Blc/ebiiEXL0gddF51RXpYT1UE0N9+t8P80KuzvVGb
fRU2ZFWr8OW8AqSE9bUVmml8M7nsc/EmCGRycGCPfvYBQIBzfHzWnVWClF39Zq0fUa4CZqZSyRvT
OqzoW9N2llv8o6fDycJXRQJDcn0n2k0YzvbjZRjjgn+kSEFmAecLeNN4KprDNspUiVFzjhzACsD/
BPqX/rGHFYi1+dKZyIxFHpSO8j9rgEzg57pb7XLtF0jSY0tzyu561h13x+g/3pg/C02LqLiV7enc
1GYBevZn3Y4MUaBpZUHBAXzHp0srSusNdenjQ76/6nt7iwwrw9ysGlEFaqoLjbtKOscOGCt2IIZB
qhMu0Wk6+Re0kmwiK1HbFIGPWxKDv84SfG05mlzDaksghseupmNR5p5Xe4VCFd8BPYqgLMM6DJqf
brXuVk4W7rW3THhnrS+TmkFa69oTs/GnJ3OxNmbXpgnsjgNm+GqZ0uD3Qi59QsWs5heVLuWqRw0A
NNeEcMuKa0m3ONSFJn21+1pueyuCwhYjN1GF2NGQGzpP8svML+UZDpxUH4znJGiUgsl1vDv9fxlf
pjy9xOhHzHrfBCznsS0UjEsnJD9pXjJ2xECuYOMZvGVk3zWyesY3gkN8+0fqEYlojXfumvv6Kb/t
mpR1JfyHS8vx3D8gNeAROkiG79Y1WN0mp26tTGHz0807gOz/ZuY8yiWDhyE+D1A1BMNeBdtEhAPg
GK5PcjZsYP99kZLuajHYkgqe7uHf/+Xly161xnPPuQYeVvHcre+Y5vQPTwL3/TdooaZsfoHWaUHW
LJFUafHikS0OHNTSIZCrMOqNUuwF0X1aD93Wy7W6PWK63fi1Si7h3oOzEPk9hr+5ZNZIsIEJmIZd
HZbIzzKkBGJMrTmYgXKuqpfSQPX7d501XNn1k0w5gswc39aSoSG0V0Ey7MWT+FWrT06+/nPv0zmN
yD3iRRDAxXJlMucPRsE4EmyW9/E5H4pWI5ZELy5H6a5m57MUAsR37KWRTH7Vt/gBXejtr6I0pChi
GGULIXIeN3UtFQU4z6AzyREz6+1QjrI+f/dxE1TePEMyxprsfEMO2eclnh/n8jpdIY3EFogg/6y0
L663skcKqm0kGjte/Jtu1FXrsIL21YSWPeETkFFwIXnu2uPSFFEmAvgJPeP2Y9xxkp/aaWzp2EFN
BybYbO7XPoxM+dBae/6FEanlgi+KvKU5hdSBMkt/G/BYFCN0fqZ5DMd9zd3WaUX/+js8vBtSpdhy
jcUkKYNNmDxyeVd8lb1BW/yKKfrYecHAyjpQ4zyAtODzxJl2nwhlG3xYMlJz1JcCYrXzyDZRml/m
sQg6jAph12O9rDhPBqSad7L0FR+1jkoGoqxDsPIFSiBliyARJnHHnuN7LyaiiqSSmZwAGRFfdswE
qWNKHi6QYG3Zuh+SWG8EJPvcCAzL02pMnfK9oau7vMmXUfBur21ftBkJ6T89d1FVacj7CfZCnn0D
OlTeRfojPZMw+sqlQ5cuhDT9OrjgJa+/A98Xx3WG5jXUGkNrkBycaT1JHCcjG77gcc+ZRU/MTzeT
vZoWyqcl1D31MQHxNOVBV7gJK79Gx2U5DMYvxIAiZFWUKY5E1TD6rYtQVCnnstfl5eTXzhofJgtp
1nbU+cAqfilG34KqapNkxia5MDN5Ub0BNYH270+fEdNR7Izr7Z1ymzYu0vOm6/OXuhZx98xiQ1gb
7nSkBlSwD3eT+k8MCdRqzGY/fQWHCKVi6fYo37gK1hiTAkfzlo08qcxcl48SEID3FPdN/EWF5N7b
yiIXvcGqbHg00QkkQrcF57clRCSGJYFYTYWnSQIJM3+lorWVb2F3PPSPVkAqIErIX1/218YEkZEk
21bAkb5ZiccCfAxbcPAH3gYJKUuGuQen3wKRg8w20bXAQKdRJX4+2HqyujgSNpnV7N71GIhyi5BT
XVa4JErC7KjNPgXL+vlqn7+DdOSLyJeyW/5xgI40HeeDdvgHOiGBbyRZOZkmdEdroXKbBTQ7AEkS
wyZ281zl/jrE/XEd+pGRebLliSDlPykq+WivdZeopfGSnjgCLdEgXJvEOf0o28wuLyruibAqFAz5
tR03+l1Jmn/U5+DevkkJLUjQfrWMlhCQ83yZNIH4Vunle2Heaku6s6Q2GcPvAgZpNkyjrC8R/VW+
hyU4lkqdujgSjDM0mPJmMWtmedSE1Ld5CsemoP2kKMmY7chJG6ZEbLXIMqfDPFKlhTDwPAHtqdya
Mp5yCz2MFIn8DzMXmY+rUbFLUf7BC3hX5V0njFse20s3e9JGbIAYlsgQ3whv4Nmp3ISP5XqxqBmr
hGmo7YkOSTNyUApT/a61z5hNAwQUSx2s4Lr6hPrHAJFoGaRLHVRlyyh+UEN50w7GQf0Vp6/CQAWo
vv9WNvvxfrGS5HoY92xDNytwTof4LDKJxDpMoOwyy5oFihg/FrB6O9s7f5kn0lPrYC6/dZj/cFPL
/HU1PMH52cB7G7KtLB+xXi9nUycsEPUxQ/nFbJyyY6rdMmS0GA29tK+KgOuTPTLwwkZ9emYvqkKD
yUKaWIfDX09IG7EUQNa3DGW8HRlXqR5cRCNUZZBMmPqJZrdfuIAxm/5c1EcvoPfXky7TjWLkmMPg
e5HXlMtdlYHv9ke9diBqw0Nb6whyQvISEqdAXKdXLMnY1XE+oYeOE80d11ds8ZwIST75ItaZ4E18
TzOBCNoXuI0yf5S09dR4n92qBKkKyR9NtVr84N8QXXDLzs3gJ/pdeCQlRQAzep1Gu2QqYIa2HJaB
yA2f6mWCYQRJTkWaRHpnNVaAE0SZp+88XLLC5S8vXba4yOJL9o46OJSqVj0090jP2Ryg5juAC2UW
ChGy/7wJv4pZ+FWxmsZj1r92lPOhT2JOimgL2/NCvoCz/52IJ+SAT2mBteQtTccIgUZB+Ew8MPz5
b5x8orrDHFpA5LkF/bomZjqptSHIK2Jt93LgPUvPiBATOCUR6dgkEHHU5HYw/7P8Z3Jauii9168r
XvaeT0JVdd7IWK2Hk3U8KQ2x2gGI5irVHdQQVb6hvNj+QbsJmPl0gJXjP8rKVhNpaKbJ7LPeBOP3
MMaFJXbUG0qDG29EOLiOyXFu0Pqtmi9IS7+59Xt6+mrlWU0+AGB7LxlJCb2XcsqK2OC3yKEzXPPu
XkZ6bS1YzJJkYZZ0DO2DPfsz4x54bZb49zfJAMiLui9GXtDOlGoTnL1Ty/GVFMTMLLH9vmZFQNnR
xfliia5aDG3dWRFgfkJlG1QMcnfnDNSewy7MMwcNQY76mvTlXr4oVPPYquV4GWs8fDc7GmHV17UB
QlUWi+bkeV6SyoE595eyvDjmubS6cHdrXZopO3FCQXfk8i+zpcUxqVzGjfV7ohThQG5TZsiZAOBp
A7gSiUzJgs/1r9Ulhlhi9uJR5BtIkFLWhJgXWQ9sd2AUpDsM/6miVPGEsXzFfAbpoW9F6sTdR+ft
QqMzYJxDrCzDIxJzpZu8q5k7/9ygXrFE2vw1QFbmk7uW1U1aHK+TbKLAzMIybaRy4KRvRdRmXZev
k+MDdWctnAnhTpsAEHSkspTx7pj8bZ58UVjQWH5opFPxY1RYPqyh3tZS0qKEjIxVAIF2CS9KvgZW
93jl55zroFNaadptzQTIPHx4Cgxb+HPA6CF2B2T9mqiBYleO2WEJPng3ff2VFLEpk2HjcOkvWnbY
Vu+VDOi0hKK2A225WnAS+sTVmv7xS5SQev+Y0N42Q0xOnZWyCot38RzHzgdQbgiMwwomedVPy9oX
kn4ptdoVU4wViWyO3cQQ6dLIsdTJaE9Qr+W4ecY15h7MT9X3m9sNORVeue5w7Y/CaCo10hXQGIJv
XE3mdmcj6izpvVVEMmf5GfDqTA3XTNQP6aBNrga6BMDIc+PzbHkdx7MJumWLhIWkLN+8PoeR9Ed/
yUVRJadniEXg09+uVi2oXV3CXRRI4oxbGrcl2IQH2hSVwB+s6JlYpNXzlysmU0DyktnAxLZ1AS8P
IsZB3IcjU65vSkiWu2Vjp9ajDOINcbpa5nenvJmjPkxTHv8S9JoVIEl8TaIuCLK3r7cbinteZUWB
CPiioySICCaK1JeJ5ofVJWitQZ0F2nfzKGvXKkxd3c8+Mes6KWkqIkI+oPbGIPSCI0WCp5noTwjz
skZtHFHHM+KsYaYardE7QNSViW9U7UHwTpi7bfJP3Sx2N8QSwcEDKwj9o0TxBfxf6ltFlXZ/mY/E
R0YsOVR4LUXD2X+rct1wrc04VN0FkjgzhOB1BdQnKGh+A3ff59OJNJgQFjUpBEkhQ3fvdHUgnu+0
B0M2EBO4C0uh7ik/iF4veaa5n5bAEBXwwHk1Z+sAURZeaKD71B7tZWQBhUkBbFB5VCI3iClffvNo
d26zviKC166H6ve7Wx8JSZQuQm3cvFT/SoXXvko8IIrFzsG6FqtxG+LgIpEFvfJD3yERs0HVblUU
MxGPKSdmEd9yMoYNB0jdonFMLJpxHVMR8p74wBo68rKrWG+h2auBmIN7gsQu18yifOHyZ5hjjb4n
g5gAUO1W2VP3ID4MI9vn12nt/6nZZzUwI6nlmD29DaE8VQZsjJxp5U9PhM13w9NHwhQUsP+ySWfJ
mSPA1lihOcvK67iRIpc7FLRy1nMozqk+Zhmw1xRedLW9JF6RP5cSROsK9h7zKqS+9x8nZ3Sw/iMR
xVO9je4zRHu0P0Y91Ir1dbR84YZ20ev53RG/aYCE2Tmoc6zkAQox1wwk6W/zsH2adlJnIBFazR3B
XHQ8P9P6e8AMd+YieTz3bmfyQisimrE+pdMj7dm48GADyPG3JZQ1JFr495jxwVpx41k1e643LlC7
NJQDrv4q+L19ZNisvAO2p544uuNyzFlr7kW/k/HcPolO7kstazZcZer18b1RoGFxxDYtIqHozAo7
JnGe7jM3fVsTevyF/Ro+5041fDD5tGe1dc/9X1l1jSbJmalrJ6mEPTqUr8UCd1cZhIdWoedR0wBC
EDnFxHVrBerwRZvpV8VGeezUbXufEMfCseCf9bjVZrbyL39VnKymsV8F6oAMV2AjvU64tUaguaS5
VmcAjnIG
`protect end_protected
| bsd-2-clause | 866092adb5d7ebd7c0aabe2038fa822f | 0.953518 | 1.814883 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/compare.vhd | 19 | 11,879 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JtfK/+1JKYw3I976gLBlwV2xqGRbyVsJ3RDvlPNJRewqWZOfwn5MuTyc+U7c7Y8NUZJKZ6RY1Q/g
uXt328ut4g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SKJFICLwrmXfYqYNdiUThnnX5tJzUEdqxXF+PdKpwSGA61whpH8w+itTbLnn6xyBye2kcWPZGi5e
86BY4EjHm7kmXxm6GHfc5MWAMFduB72GxoAF5LRKlUMCOdVsZag78zFjXdMU64ClBQ4zjB8EgXvA
zXBqthWa876wjTEo86w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ho0WiFevcJjvoEEaYGtHkcW737RD7c5clzugQBBm9an3ZkyNmpivYZbh5x9redNVt0HOAIz4unf2
BSVy7qVCwKIsJQlB2q0JzVYTIfuco8FlNbrUR7/BeLSPV7XOk/MTxR/0Dg6meFJjnWuC3OrBGp8S
Ul4C2x7zg4t68SLTuFe/LzPmogzBzDfD3+nozb8sS3jX7ZaQAm/T/7eoy3grLVkFjUg9uj1IhVTP
59FDPnvyx1zZ/V9kzMjvM4XKEW4i0DGLbDEkqT5cZNTgcxi+sBHO7OnQuIvFzoIoNFONwh8iJ8xI
jfha3bFVgIjIJWFL/KzL8e9Uwq67H4YDz6GAsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
tPUgwDCRFsMzMdJqCXSx12cw+CNwvndABCoiKOSYIqrjgxTgSZ1CAyY61ekJUz6cu1q3fnTmoaAx
Nh8wOKV+UbnkqjbXLltbzNbjSEawEnAI8RSn8gStXvDoHe7R6pRqYg2wbvEPk6N6UhaMjVC8JxUE
Nl+LL/ApnNDqgvTWrcs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EyCeFS/0OQO1er1RAmOJ0VIpIQN1auXP1dzcGUAOeSe9eyc/jA1mhBpZ1JPfDCNxALRFgLLGYZec
wCmtwGwTJ9NXiyrouRmXyaKsTpp21jNq9KLTxpWtw00JZFdcekT3NPcfNHa7nkycvsM6yWSUR/cD
frws/8FBuaG+siAqTh5qClTqkxCmbJ08Qh/l3c/D5bCXbr8wXY+SVe6EK7TiYFpV2oOMuwWw5VVW
3m3/ZK4knJ1G5Nn68ZhcGx6rqQE9ZbHMigIgQyt/y7vXemBfmAZ3xkMsYj2X3k1fFfReGPYzTOCE
6J8z+FWVfzx6XMFACHDbKayB8gE3RAvjSqIISg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7056)
`protect data_block
RVdqxvN2SQpwPtgpKRC46v+8mT78eTwW338qWd91xC7Uw+asat3yVeozjmhmB6r80gHAYtaSaEae
KCwh+g5iL9CaznwaBx1B1OGIVt5KKjnVTl05qeFEOSmBU2TdF9i7Ny9JZpRK+bscZLWRKNQPXN08
jBuyGWqvZE1HU9r4KaApq8Vub2/G3UR1NKa11BmkANNusVOLcHjFMpXXO670ABDVW374LAkLbJ5g
78TWIvHyUdE0nrp9uwuNGaY6V+Ooyh68caJw5my4AarJK2p8gTZPCh3t/MjKFfH06mkTCz48xdJu
bH62yMRLYiB2BUa16fx0V8onoVNj0lIAbXRbaEb7MdGWLpAFZZh6GsRsTXLrto2+LKLryMrEcUye
o3574t10s3PxSvkOoq4W2hT76aUbShEANjgmCNvpJgqVdsklSlomXmjRHr4KIz4pJpVM0ftgpTNO
BrCiltAJ0lh6VPdvk39TqN3ZdFNrszRyI7dGzHukbuGEH8URQHkNE1Q6lOKcGvurSSFBFAnr2lNv
Lx3z28GlWfg6uV2ui9kK3bEDNpCtZzR4P/vNHborbwn7uKEyKLoPFgXMpi2Lcz+08ctLPVcg47Kb
T4H1+Op11DiT1pFrA5SpdXOg/IR34UJu9VAN6FdOax1pdPd0OqPeQusc8mjf+NObMKO8XPPF6BWS
W/FbTDl0M4yEnI5NdO3WANxq7bnRW+6UILwp4t/vDTZbAY9Ll0Bi857lmJsqEC8ZJAdSBWdYxUGU
VXk4Lz5rir98gxKGm0bbMSk5/8Jm+ElZRUYUKo0mlgI6pbyYf8d+62MxGKT9Lpd2gEcKnfoAhIV9
xInbN+l5AaLecCPtDMQFTG3kKNuWk6oe0VXHKg+tzHKunQ6/dtduI3VXxhZNXwrYSpheFbjA/alN
vE7Fz3YvZpLz4z4vhU7Wb0irBDO++NkOXqVVAkOB41M/xV3CeoSjmxXFkux5Ow4zy7DxPyfvr7qA
9wtiiaPXBsrZ9OYDSBnHzrCk5x0iwDwJV3WcYDnS0EmMIaHaAT3Ei+h5DiC7fbxfPDoDxAMfnzMx
9SDJef7kALOvfg/B+TaPMcdFvO0lk67G65WfSVdwFZ5K9V6QfjCvdZF0/X1OKolvfFskIfy+ADRJ
v6/4Zehbs5US82hWVEy1bLgIwIN6DRKW2Zgmo0pnz8z6hlnDv8QyzXAEAzeJ3zGiGwgDVUEah5ky
aIWPVA+DQSNBN0sNNoOizPzv+WMwdEa8Ng5y2sLu3qspLwNbaL4Q9585qIWr8Z9qYvGGoht3tKR7
GDsT1VRZcxVq8hHctE4ph1J48+u5LvQdTwE5CNGrNqG5ouZTv0iNuYMAVofYO0xNCJJRX5nheP3j
K7QAKdQu8H8gDU7exgkHFm3HdvKDRLOsb78bkyk5cpd8/84618KD1NoCcQsxwA/Ux3Nj25uLUazf
f5lTvKp1sF86qYgmcu+AQcvfZinyvtrmauW1nyQ9KeKq9z9zUxpQrzxSVyfYpg+iBTxpyRYtVnwX
nnp/Y6fLPeqfz2zK/nd958kvFtE2zZoVQMGmmYE54cPUfs1aj+stNMEVLpVla4VdEMKbrcvacvyV
UupB63CzPBYjGAouauIZQQ/xv920B4DNKgyDloDIhttZBxZVD8OOyF8xu0hgS79a/q/LPNRL3Iaj
mLp+8kjuXQmF0fLj6ac8x0ayTE7v3P+v03ReJVBAmT2IjKQ5fgCFlp3wSqO6BrzEH3s2mz1TC04B
chlOX/+XFXuo6vSSgaIdG6WtylDuNv5S8s15gM/egrR6oFll2lW4UVWcMumxlG8UmHmoNljd5Or4
cGLxOTj1P6XKCwhoEum1qdAffXoVnTwO5SvPdmpCBTxx3PIDRKwTZPhutXbA3AqWQSxjZqZC436W
Uae+eswTEdlGxr5M8J8NkKHG6XtyLC7pdx2aUQF1NKpX4w70j5Y5yi2CeTyZM+m5ZwJ9s1ODt2uv
pW7/Zak+cNx1TIPgZi/fUG+2NRBi2NXkMZe5AJbiLLT58IK1xK5iF5YpWTLYWbE5LouPMJi+RPse
b2V9dhLCTm2DewtZIdsYQW53vdTLBntxGHNVA35CGfnQxjWwRN/uj6kSE25LlSTzifuH8m9lC4sj
aOgaPZGJQp5L7NlS1i/w+UBZLPcym4tCHuTNpCA5E3CNcKhRRRC4DiBswK+0Bpxtn/cQC9EDRVnC
kQRa9ov5NNDQjHoEQg6wLa4w6ziM3+cavcXxPDyVZD8dsmjVjeN6lCzwF2nE1vZ7WZb9RS9QE2Xi
xF3lpJeqm2RrHDO2i6MarU8nJcU9I72dkldo6sUv4797SmWFI+3hC1s1be9dA4dlelj8k67/gcy4
jidhNxceO06yzWEcv5SBJwwwF/NL8m5lJAqc+6pEV+AfvboxSpa94QC1HTA4Ddzbmqcckm2Uq6wc
wUDhtS648z8/hPmiNA9r4tdW02MGyckkiRTEyKbkk8zXfqd2nP316nobK3sv1z9vBY4AXqoUNF/p
1LSBS4UOU9BUaZr4WsVYHxK5lHnVyti9Hc4y/TvvDgVg4Nkfiia3UNyIGpZie84fqwLsrUgkiR0b
5IRI2sBaM/DQaSzMr0rFoASlslBycsGCixgRYH6BOUuZkOOaOWerxD4V9um5v0oKqF0Mhx7nyPoa
eIj6eVfTV1TxMIXzg+7Jz2X3npmI0FyVwyazmU2awpvMbmzD40RDJOqq8T8zsJJ1Zw9OvsnD8mHV
5Vpw2lr6M/rhLBP5Q1m7LHayqewo7e0JVTAxKlOeMZgXNBCGE17ewkerZBiG4HEAV6o64Yjuhx+i
+wXVc/qeJwRQGlhfxCl9Mil+n8lWybi5o/CGJBxoGjXn1ofW/qGDsZcA+YCp75NQzNaBIF2WdIuj
0thW1hCWLPvP+04wyg2E8h5ZHggBcQoz2c/uEifYHJttKUQdt0hOUylKFSHUXRCU7Vcxw18Y9Vaq
ulKyyf9Kza50mZLcfWpLfWq2QfJejSOGA5j4FuC0u5vhN5d0wYcLoSFEXsFzW0r9z0V2oGYDrUom
txc3ojoLRehJD0+O7KD/jft/nqrTEV+PzB82DqIWvCCibnId4e3UtSDnz9nhJia6AVrCn7YZo+6Z
5/skpa9dzmvXbGhXkN1BVTrrFDJ22ZQ2qpEr6Tn9xRwO4Y3TIqvrq3g+UEG+syMMnP3kIYpVvEzT
yu/Qj4UuEmsZir6EU/FRcCLz+TfMl3TfRMEZ4I+5wBqEKm3TGcewEFPhv17NRDBE8VjyPDkPlhDO
mxNRCWd00MxhZ0iSX1IGePvJMjOFErVrOiWwj982npycSbbzqWJub1U9QRislvtpdEJaqx9gnFE/
tY0ASog/kkXLFSJkNI8yPCglFHbGH+L/P9XBmMFnX9uhUbv3J2oof3QG21Kc5A8X25a5od11NNQE
zHR5WIxkXU5uQjerID5WzqMrgVR0YYOpI6VFZHL3B+E770Wu+pW9iDThYn7xb7VcQwVvUt0Z44qs
ftT0+BCGymyxPvI5cDCkCqjRO/m93WGBLcO6Y/dXpWZSjz+rTFqBJU9excNtBEKM6RQOSTFaoMSq
6znG2/4sTu0lQLi0CWTVVzxkFkN1UowwW0Fj/IPfC5VKHstOqOSDskLjbGaUy1mhFPoGuDhCAY4Q
+8q67vkK5klh7nGLJtE7v8JNvcKp2R4VrEqf+30ABoakxcsS+2EGHZTlrbLcQxavlk/WoaNPv8xa
yNuueeC9UdD54ZwboRhUjkIsS8zIJmXGXtH2HN3FRzdqQtkRw4nBOmHHHoSvtTaA3XlmfXFTxW0z
QndoZYykC8/jX/eWskL43fHj26rYk8cM5wpoJ0M4OCvQl4SgrNo0zkrX/fh/9N/A6cNz47CS548B
fIRHTZMVISwIiN4Cd6gmxvz/LTCp8EwYaXa1atIeuKA5NBGqqwFJGPycWSzdeAm/YifgXOyCiIuE
19G9SOs8WPLg9jvsoscLGH6iJbroFGV7Gh/2rawi0iQgg64tZWiQCMIQfh1YVxizddqe0s/tkFIk
j4DyUQmQQHI0uihqCkKpe5ju6m1xy2YHM/hWWY1MZyJ94Ik+wZUGKu1jmB63jroUIodtQGK0yNt2
6H2iKeOiedGZ57LtgwPrB1JcQMZmgXACCH2qWNQYh4FciaG7W/w28TsXy3htbB54T9gC7su5JLQ4
BlaZSaJawLc+W3EijpfgMBAcDrna3xWWZq0wzPF3PgDMXubaNcx836RkL4WjBwKmlsnnBR2JGjde
FAr/EEZbrlP7/ab4emI7PjV9oAPuGgD/9ohxSjxr5OeCFDYGzmW5v3hIOgcvvB6v6Mu1iJtfQc8z
uVh3o/14OEgHF07lOIk3MBmFC4v2+QXmvKsbfuQ6LZ9pd9WwAfS272OyFn9hoR82AaBWCsAl26Nx
8iHOgWIfSOt1VKmqdXR5Oosga/otfTehOjKIpvP9w8qvdSMbQQQZSheCxpUSycA15q6DOt76Z4aH
b0NdzUaBBEyIYOrNewwjK2o3L5iUzFO6WMkCYvPaVHDq3hDDmhskwGwtDZWhPX8wNuzXhFJWRXWS
mZeacPwsf4HUdjjcQdXH/FRVjmkoKt1YuYdePgzThxcZEgEIxD4Ge6XVfqV23cs439m4DhlD1b3S
ysI5KN3UoY4BL+tRisEezWRMlg7+bLq2qK9E//Ol01EbjYHSdqqqHxAvCiNCdzG9JS3cC8pYqPbT
l5t+bzqSd+3D5Fqy2eLxqMVQElkcfX98NgbK1dderGqeKM3eBxGr+0P2yac/zmc3d5GlOMvZiuh5
kkTExQnxZDsmRVVzJol8Zf3DMFwABu3iQwToTkilci9YcAKE4KglLfssQWI+hW9KkXH27rO+1AFj
/WZcVc0ABJOaIxlIR6K8PqAaYBbRUEdsohB61sSRRL4WAD1sBv758zRYMdGVu3dSIAOX8GAea2g1
FeyMkmhPdQ27e4DvyCsnyFPjLvzh2Fs0wX7rWkRzMLvSQ48twQafX+v604V4NAmfdVUL4jJb0RuL
Ow9OGJqQQUgo1ugZ6uomnes2FGw4/Erubzc1HLogBv1mWTRdFgRIol11dT3xJzQbfHq43SpnVaP9
WZV7EjLz2nQviFrG0XEDV4nyIlN2Z2zUXqsTMEDKx1zGG4ibxXMxtc3ajv59/g2jZdLLyxIFNsTM
AlUeWnImtq8mzFO4OqqzqWg7kmhWtlVBv30YORrd9wxtnhhM1YaB+UYpObQIOy15jjHrfOp9z64e
W4tkkmNQ6SSyqWbKRLAeF6Y7PAz7a9T7kH9I69dRDoAcAGuvPNZsPlzhhV3xoKCwd/nHHklYbKcI
X6Z+8YMKPYYcJt1OAeRRicBZ2ZL4uVMarKelzSI4I110UX+6KvdINqSw4/1MjGFAYAumwM0goORP
eHAyx9NN8D5Vc9Mfa4OENk8h15x116emGUxmsbEfGMM5iAMp/KZ1xr6Z3DUfLZs0GVTykePshOVg
u2vIHxygWwW+nAOmc3O6KmByKDgxeKwieYwKPd/Vkbidgq7H5lq4g1B4aIpdA+qngWMyAtxB0/jx
OjTranf9kSVeShhY+b1AvLYzNKi2SfEnXR7aoKpOb4UeQKpBHVuzXT/CCzDCcXRXNl0tkDfXnxi+
111chhxDGkCyQmgeivrwf9wSW9/b3f+bhjK6XDMN5EYpyQSlhSVfMGBjp6SglRJP38wh7b19V6ZI
83NqwzLhZ9/5YmS4FtQNT0C/dficb/VhsndKkO7wy+BG+iqX1BSL0qPFQROBseuKbxle22+qDDCh
3LUFdnxGrx3QE1pQZTgheepPqHlrdu4cvBBAEqNVyhKjYua+qerjn/pbZIfif55MCVY+nTTy81hs
hYAp69JJHwbMMhpd6Wz4EkcJ+28lPVLW+Aarao94uFzZIw5tMUjh1ups7880CY6KCj+K97UW1GEw
a4oCjY7uLLqYQxwmimPdy/PXC/EbiBF0TuRLR9rdvqNjcHIXwnvNcxS407BBot1m+P9VnJ/Ka96N
STgb7yWaa4XmX/X8NrkcnM0Lylg8E2FsVyG6AQra04o7tNSaIJ7wGFlqUhf6gwaNI1lySgEWJ5tu
cBUoBGNNMgIfMUV431L7zh4wUZAKqIDDkBpLMwe/yJa7X1p88qj35toXrJ5I9P0wn3Kej07UXUQ9
iOEENHkYm+dYBmpks/8yDqYQlgFWcoQ2M/eWEVXZw3ZBShYo7gElOBTcrSMIQWyyz4lrmtLjCJNT
E4IyldDNvacUlpNzYb5MnH62gVkezaBF7vxRoYVA38DBHPNdGnzVMtOpoY0wPwts3A2Ynoagfgip
ma6CYuuTa/mAuEFrU5Uts6bU1rH2G0W7R4evWzhCh1WZ4NHDFSWuiyEUPA9cmtpLuBpQOce+zXBb
jBDxmQJ74eEDgi7gGy0uPaJRz2px5vtnIzGf1FqByFn4QZKgmFyv5X9f+M62SQXCXKOThHUyWMUB
IzReHNcWGXdxXFiS476xnd5WadH+P8X9rKTOEv8Svd9n0uuSoyBEALvabAqoS2gR2lrUqEQKY4H+
sZKUkZnWZzlXv5sEiGJ4l2BhMJbE5+KM6WGAvbh0VlPctmQKR4qBUd2emlIjqS62BRsneX1RsjbO
Hb8Q+/SYMCNwSJJLC0nlxNddqJo7Qx2zNfJ6BWMX8hNknhQhoaP+/yAv6nGacoiS2MHvk7JXRwt+
61viNwOEGQHviZZhS5PbAjFcZao057el99TOFVKMIdx53ibPcb9InMvLlZg2yR09WzoS5Ska8rL2
XBLowUz96YC84jU0C0odOXPgUxroxOTEKQi6rxAEEORkBd4PiLThJXYXRWex7MsSR10+mrDBxPi7
o4Wc4IU33OOvJet1ZZaMYiCetprt8rUimZn8mNk2IyWG1IiQkrfDlnzRPYziF3o9Z1E902wnwafl
yQ5o4nKwe0jj1GAuqifHQeDgu/kt8pkI2djHGXklaXud2AVIONu46ar4poJ2lAIPYtE3Uk/LK+2c
Z16CXH05Rdnb/lEdPRnwuaCAEDR+SMw3sLytVvBXlxJNwSSZz2QC1T4kxm9dgKJznLnEGBKEJplJ
8fmcmFamD15iBD16mAY/TRD7Y7bkty5nEK6T3OjEw+m7b+D5zuiECgzNkHOSGmBMXLgTE4rLfnx5
2JaOoQeuu398jMgQzuNql4K6gvBagg/IeLoLlVsCeCmHfX48lpiswFNGkwBpHFAA4qKdO90CYder
WZ7BEf/kqIF3QJaQFJ2zyYktKnvms6ouE4WFjwsc2ReiJN4OXHqFP/uACylvzCy6XUgO+gZ8sBbr
GFlqwTJkCsLYoxf/KSQdmJrwYSBJ2GYbGAl58lJc4ZjqOfL9bisg9I1v16/wVgOLksQm3lBnnwHN
mbg860Y1LmqcLiYlJ7iNSb12GAAXUiZ+Cdmuv7cJQ3eQyAO/2VHcl+Wns1zITVog/irCpqZ5e8Hf
11tYyMStZJUSJVHfk5sPIyyeVmJDG1TkwCUu/NY6t5Z6nBjrZm8xBozfdGQN12qkj2cAwHBMwPOI
Z1wRF3ZE9E4ocC0Hz672ralbiTu7HxOMZhzyj53nJHi8mxKYWq2b1tM42mjUfwPEsCXdNZUz6w4x
nMvrKJ21oCAzgM5KJGNzep4+uAvpCN67B5i9SY0qyPW7ued39or8wr1sLAHnTvR44GNX5OUJdiYH
WcCrXzmllReOPdyFBuVhiZmbQcOUqDN3aYvhzV04ULBlLDkunIzXzTdOjMfPwULWwZQTYgm/xJ9z
Botkk7b71p8b1cqLhPqXGukMLL7s7fCcTxHuhTGHWX79f/w6Oxo15OkYJpsA7f6De6pgDJAN17VC
4nv7vwhnPItLLgF+LHhAZiOH/4+zVGezU/npykCatrdNhIy9O6aMaIRMDbI452zL+qXXtXTN0EL9
ykg2X4+av+m/jzMbvaTenRmP63Rpb4INkYtoP/tmotriSVk6mFHG5aSRILUU7ks8/AFmWWDhfyV/
M87IuiuSff7BtXknc7/axWTxyZB0ec1wq4RCCnd6wlp+kZCQMRyMBhCLzrBjOWPPUxlImWoy4f8f
2zxlZJvsTiSA0qq4cNTPmdaj232BbrBsw2cO9qFgRmKyMvkf8yhG6QTwelMm0hxri4TAmEDePu6w
3iMa7i9tShsy0kEYAMx+M9FHhbk5K+TPEV2zd2i4TJ9i0Aqv8m9VBFFl2GhAu21j4PhlCYAMHh27
jRxM0rbhxUguHyZ5t5/IJ6zxB+z4rf5sVh7HEheGOhzKi8DuD3954ZwZ+UFNg2kb3EKJX/Q83N3t
vo19LSf//b6GAiMxohOmuDCNgj1iu8jKSxYUYEU+i67Ul88oXa6S3TtYhL92g9AMqIzo3PnssHqn
efC2gk6A8J5TwmWEm/m12OzDF5xMK2z9wlaUdh8bi9Ik4tvgfhiJ/hSaT4MPo3w18U/pfyOsXZ5O
2jYGUF/1a/SsmW5lOEzARxXFMFhJdNYCGsyaBTa9sv3hABDOkr0N659i1mdZJNIy5oWEJESSD9IO
wUjSgcUkXE/lzQrrUgnw+98uU7qBNPxWm9aXAuq1WLKWTEM9T5L/qt2yqsipV/yN1iF9fAfF2dgq
fqE59yUC8jSNFpDCRelLPH1M1ZeEzaEUfO2LU9QlaM2RddLGokOlRlo2OmmztEyzv6Q9LuZuW86Z
J/XaoRWwxSKTjRmgxNay+oUblRjxKceGWQC0QlGA6yS02leiQjqu+Ditf4xAhvxHTmbdxc8sVzbA
KUagAYN/5pOdzy/Aaw17SEd1QBMZTN2tdkxqf6lXnFFcJtOnZLXU7SxDsjxFjjwNblf8NRhT76i+
AYPkWNpMGKRyb5AQwkcXTZHfCd/bB8RMFF4oberS8Sxs9+Ak+p4y/JCxlmoIgDTxvrvaZC1VRnah
0Bql46GsD7PMlOo0FhBWz6FcG2p5UlaJAXxfioVbobtzmtUk4TF7DARIoKPZ/jgUmLv9fxQqv3ey
VflKDIMuL9AZT3KZKcYbRTVbex8aEUyqYycmgtJgXt8T35MrIgdOWaM5j+cfPr50MKpiWi90PHM1
qtxlTcnFvXm3pxzw/45inLOYvgMZ3ywyI6MA9uknNyAWq13H9/wwybhGHTu9g2/sBBdqwLq9O5XX
Zj2JPqOeqId+rvRgPjfaaZGdZvYITNaylATWfzgrWg16tsfueTysxWdDQ6u5OCaslwug+cnRAX6E
9wdjspT9+U8JtiwiGAepb8iHVamQBW6j78UQmr7StuCuSs5WCA+HFmcn/IULDxyDLSZDvkGj7qx0
PIgKDXZ+CjvEXba6V1AAlKCwlNeR+um9VIRk38QCrHITz0NX3sKRwBcOQHAe0RbpmDCtWs/YFHv8
gzziW7WDVyAHCi480noipQyNOCgwiN/FdIgBrYlPhO1mOt2Aye9VHYV/WgO/
`protect end_protected
| bsd-2-clause | b45f7d9d4b7260213325c63546069e40 | 0.931897 | 1.890657 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ethlib/greth_tx.vhd | 1 | 17,419 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ethlib;
use ethlib.types_eth.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if (txi.datavalid = '1' or txrst = '0') then r <= rin; end if;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
| apache-2.0 | 41e8560a8c74bd0e2ffa3e303bd6037c | 0.516046 | 3.200845 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_CRLF/CTRL_CRLF_VHDL.vhd | 2 | 5,360 | -- CTRL_CRLF
-- Carriage Return Line Fed bei Telegrammende in den zu sendenen Datenstrom einfügen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 10.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_CRLF_VHDL is
Port(BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
BYTE_OK : in std_logic; --Eingangsvariable, Byte OK
T_CMPLT : in std_logic; --Eingangsvariabel, Telegramm vollständig
BYTE_SEND : out std_logic_vector (7 downto 0); --Ausgangsvariable, zu sendene Daten, 8 bit
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_CRLF_VHDL;
architecture Behavioral of CTRL_CRLF_VHDL is
type TYPE_STATE is
(ST_CRLF_00, --Zustaende CTRL_CRLF
ST_CRLF_01,
ST_CRLF_02,
ST_CRLF_03);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal BYTE_IN_S : std_logic_vector (7 downto 0); --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal BYTE_OK_S : std_logic; --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal T_CMPLT_S : std_logic; --Eingangsvariabel, Zwischengespeichern im Eingangsregister
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then BYTE_IN_S <= BYTE_IN;
BYTE_OK_S <= BYTE_OK;
T_CMPLT_S <= T_CMPLT;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CRLF_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CRLF_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
CTRL_CRLF_PROC:process (BYTE_IN_S, BYTE_OK_S, T_CMPLT_S, SV) --Wenn Byte ok dann Output=Input, wenn Byte ok und Telegramm komplett dann OUTPUT=CRLF
begin
case SV is
when ST_CRLF_00 =>
if (BYTE_OK_S = '1')
then
--CR01
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
else
--CR00
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_00; --bleibt im Zustand
end if;
when ST_CRLF_01 =>
if (T_CMPLT_S = '1')
then
--CR02
BYTE_SEND <= x"0D"; --Carriage Return
n_SV <= ST_CRLF_02; --Zustandsübergang
else
--CR01
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
end if;
when ST_CRLF_02 =>
--CR03
BYTE_SEND <= x"0A"; --Line Feed
n_SV <= ST_CRLF_00; --Zustandsübergang
when others =>
-- CR00
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_SV <= ST_CRLF_00; --Zustandsübergang
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--aktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
end Behavioral;
| gpl-2.0 | ae0a88879859e344088f829465237c91 | 0.61306 | 3.048919 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_logic.vhd | 19 | 48,192 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
DZrqnYwqMkKoBvgXgaWSB1Gvc9B94Zr8xHWYvXS3Yo2in98iiVsrSf1RUePWKa7hVSyhM66u+GP8
6zam55ovJA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
paoR3khjnzY7oR+WJ9YkW1A7ZzfFLvvVEXiP81AieLlGnfQuqZTzy9TqIBQ7d7KWJF2u8/GBJ9gB
S/XHVoSTyo6Jte9XVVsqnnFiHxvEAnWbM2e9+Vyqd/Q/lFB3TCGyLNKIFNdGxyml1xea2Gq/DUf6
P6PVaPylNEwivSbuc64=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IuseMdZSknnKUME+O/YmMG9MKbslcWjYg4y9t234jonRTsM/8uUOZLlJPdAz0Ojsb7gi8Afg71RU
Er0Jr7fpQJ8YMMDdLQ9qwRqf4zAR9ZhntG7zWMIroK9jxtC2bvBKKArJREVpkzOWU1g2+f7dJ4FH
ubSzqp/ur3VRiEL9rSTe80jSph04B3Z7vLg49YvLUGmYKlwP09xV4/46qike4zQtuofkQ8/u3jTv
rlLcM6RtgeLWfD/CY/EWIIuhTxeQiucCqPyYilV1cA55FNKfdMv57PsY4PVV/CwLFMYY9INUTcQ5
vlvEZIaCBXiBH5TWThAkm9erewSr/bL5DW9PTw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cyY5ZPlO3Eo0cmsRtMR6yuz2Eu2e6S2W/D+8CcC8VsHPfbx1fHUAOMrMRz8rOeXuKPOa7h1hSFcJ
XZ1TcAU5VIvCkM11jW1o53hK8qachmkkZZnfj8JtjstmyVTyWri5LmUnPYRufwJmQUQ0xqMJytkR
VTqDp0ZVnyDWp2/qKN0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WAcKeockg4TPNpKWNqCVvf1P8zBdM0HIqALOQnRkxsC2RA2Dy+P+XMiOG7cG04xrgm5iFejfnqcO
5lDRzw1y2vm9IxrTgVR8u92CBfbBU5si2daX0ciu3+tUaMvbyjjRBHmWEJd/+ZgwpEBd4jKx2KQp
YmRUDFYL5WDDgF6aGgbY7bniF7p7fSFQgxz06UbHJt/aNGcXnfge+DPA60LgmbiAZYAbqv+bSmqg
gA91XQkI7oyEKtZ35D6ZzgJ25i0EzUAy/u4ctGTC1xnExC071TQUx8Fakynqcki4h3cwrvs6RbsQ
1XULS0sNZpYYdAavNOXALBW23U6uD7bNRcfAog==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33936)
`protect data_block
VOLhYhIKkXWjetLUjE5rW5DQXkpxt+F3F7mQn6k5W7YbdJ7D0Azpu3IcXaUiginkg1B5Th4HqWU7
osBSHKIuNQ9LD4/HNdyzIs2o3fqQ1P+qXRvablpy2UjG9YhuDEnW9OgVmv9f5La6dVTzEZojW2oE
Jw9vS5wgzsBmg2AZjsVx3HbrZyjWXSjhihmuDmrZTJMaKDStk/4XJc+tznIH+sK8G8yeA8jtlQ7U
HmT67xWdPf03iaiItCELiOLHHqlolMWUU2Ubq1E2XbrTQjP69rfk9bFHAqohuchDXshcW1rpTVcd
MoM/EB9OGgGNWyHGQXg4uI5PDl5U1zW04EZvtKGgMMqDo2d3B4XIZbubk7UOE1twoeqX+iIEzhQb
d42uk2oTeemZqxC+THqnNLCA14SDW2x6Kix1J7DqT59W1+KO0M42BfAEWO/4QAXclvgJHR7WiWy2
cgptGj7rDcxjbKbRvSiJ/UljMcbRcULenLv3Gtxylj+0RIMghWJK48W+RIqOZRZbE7rFLcFlb4KZ
T/qWXpDzxYdGc5H3CivxzRbMZuYXgxBVEdgEwVzGVZgDlvGfTN++GnoI0AK6ukBztxJhIllLYeAd
zutmH/rjrM72X4xngomKftDSWQ7MrBuIf3gIMfXXG31trMiXyNjt7JLVc36vf8GCGMu/F5Q3zUQs
2OlRMpgTg4heUkK3UZGWY117sVeLFfr6wk6losKqPD/QMOLup7xwaC8uk5jBlQaw9QkLTGhJoEdG
NiAYraxoDirUYQaOE50v5vUqOXwdaSVfEp7WrsES3fVPZ3d/42yAidFBfK+B5gOg41GNOWcQU0rc
Lu9WmkFuGibg+298643vbMjc4juikAunkj7krOUVg+KdcjfSrI8AZevM37uTWy30I3nQcfPCg0tw
6vFU1RDfa3DzblYRXmKlqDcau/LKTwkr9bPIN2krQnel/5wNa72oTWe9ciUL2c8DmjLs3zgjiOvI
Ad7po2TP8ebwAplXkib57pWIY+pxqjEsDjSWyu33y5nQGR8pHeOn8iwivdRF29d4CUVqZBWpb8zC
4fXj5SwvtKnvT6v9OT8M0YSH5s55f2//a7BNio9PePo5CebHteSUVjXDSOuC1HSuT41elJ6M8YW0
B3gzDe9/X/8Ay3YYyQ1g1HYgU4kQKwuWSCxb35FGSpRCuMht1INf50pqE0+hazgN1s9Y2KL1iU5K
C31mz8uoe9c3C3hjFkvhOw4t+pHAgULRfsmG0DeI3DOhsxnsP0fu33+7Pakv0w1jakB62mjEv51b
c5XjoRbM6hx+EPfF0Y34iz4g0Cymdi9mBIOJIXGpLeOvHDpm0UXLS2I0Sbvvgoc6gpkwhSS4WKRr
cvW/gSFR9SjY9WbQdSG7/S31Ajy/+3arxU0YG0R8QHIf3TRcMyDYci1LqYw2NtGOylEwpqVP9DI0
9SW/132zv7ciMCt+0kNhFQPuOzIEQdJ6iQmyESYs0PJ7hhdfYLN5KRqILQicbFh3AK2YGET+koHI
mThTPugQ2GiyoziMq1/dHLtDHvlnCqYw7TQQPdtPFfRtqMofqKdPWbMZWH0arVJWvjiyUL2215oV
c2+W2Yj8RmjiEi3LH8ToszBBxL52Rtk0pCj7C1qsKnCm8nDBHdmBuqiskjo/MSswALP9k/VlTpJ2
c8UvqfYq0mLUi4vua63BoWIOXkROxAS9bUI4LZ+U3Z0+2ohV5xeqQtDqsjUocDq7G1lEMv03gfHO
YydiyvJjk+lcVtpTUs2QS1B1tco6tnV6xzmimjuRBAymv8F6hV3Wwdd1qxYxmYmyptXvKv9vR+fk
isKaCMXjI2AkZcsmbYrf6LM90DqpkDD+hqyswhPxSm8MeTVq9KGLlUnvzduriJLNtxPS4DiXRmZ6
o/44ZJauPW6B38LMhzeZa37Bpot20wY/OfUgL7EA/KiX3ce8Fs42IgzUiTa5xDc9XQEkLsV0rc/+
hwBqUR327bKXnTug8yVhICQU3CbdsOlbCvxFxDu3rFQ0pRM0PJdDgp5hH2oOBbQ71fe/r1Nhmuoy
FPjxkq0buqLHVRypTSLBIcwWZzKzPT7+8Jodm1gNFPoZB0wlLCdGU9dXyR1zKCDYg/RMGQdFWLmd
04tOMIlSPpOaxt9h92yfBvGFNC9BJPLvZPPzIuA1D0GS4a0LLPVMy+qp+44Zas/wj+CgBWCZAdMZ
lnCJHPr1PkSVNw7o/YixDIKjh3r7hkKbeiEo0qGLemNMMdcj0Fqk2lSh5nEk6cfzApwbkMtqmxCO
kPsDa3xX2LKfTeIHKoKOny5rECp8wJcUDegetyzvLSuGD24QIdaYzXjrtPumMDPNUhQgZjzf9YbT
Q8qFjcU6nJ/c/rhSfFSgA9UHQjcMBeIDkk7x4GjUob6Po5zII/4m/Kx+QmeBz/D8TYFuO7UfqyXK
ob28G53il0xBFoLXMr2DMrEA5ZhVS6O4NT2QhXupLII5KxUtTNqMgkBWgVf3k9s+o3RsOyR+n7Cq
HHbU4HJGDun2nxN6xzQlbqpBq+SZLb4bgD4hHNx3DTrYZGFrw64qiS0iuOU6GCytn6Sq5Pl78KMf
icV4V7ZdyDK77zIoQI0Q5IXz5TfB6BtyYHz3rB55suWbt+iXXSxyUauwB3RNbt8XG3SoBSndVE27
zAIcLjdiLuvbLcUJrLsURqOFhoDd77DFjqujA6xkZVwRm8/7VLllvSwZaNksm+tTixoJLHSOhm94
NVPveZfrn9GZIf+cpC1S+sC6MNiI9lX2zvv42eT8gvw8sO5tlLPaqmr5Zdpb7l+OR2pvGOotyFJ3
kdjnyYRqTNQt/VASAPNe1XjfS1CwhRj3Cee/9ESe0XCMI+nRwME3Sw1l7Qz4L/4FRTdYWwQGLyEC
ZMTSaEfo2g4OvBqpMW8PpjVkO7zYlI8fGTWrQt98yyN33AjyFBYhR2p+zjFogFOjJ9Hb3YOC+iAB
/38qvbM2+2j6syeYqOyKRlAvfWP6YxEtWPAoN1mDi9Z80sxoJ841iLwRkpKWP0t3rvnF318/gZ0F
3FzdI/RjAmxPztODhwRfw2B7E5YJ4V6IpnoiLYPaChldww9oQvCiDyUOcySm/uKkp3gmqqMch8GS
uUIzsWT4pKWg9Zk0jpJMkKKKm6F8XPdZVCFZZWPr7K1zn96u9nrElbsgFxEjg2LNE0tR/dcIv/wU
eb/aSsNNKmnTlp2Vg0Z0SsdUFdZUsWdVW8foqvjAqqiZ1S1/zem9wilF2B60JXR9wztX0VIhFesD
/NK4x7icvBgsyeUcigsD9IVcbJAx/4bXeE3JcUZVT77WoBRTc2jmlnHW/G7cN2VqJdb77lME1dDs
CXWcNR7OxOaVCbM0PIEdqlJxaZ9PRhJu+uxWmanywEmTK7rx9v0H9R4vYXRo1sWWecPISjeba3+C
GZh0C5+TFvmphiePEJrRzDB78o6V67+Q5TNgJ0AIPlaNuZTqoj8cEg/LubUYz1Sei5LlYiFRMHIh
H1FERJHL6dcx/w1isoHNJK1CZNwFH1edFD0alv1lq5n3wr0fYmhlssQn7HkjGxzdXF41aWMtzonw
8jyCqO9j59Co9TpJVhKXf4wKucweAdTk9w38Vy49Q4DPv3j0ETDWflZ8J1NbNspOBhR7AS6vHRcD
28jzM6I2sRkxwi6Hf7+wjiF0LBZcUZeQVgd5pDpD8px+Me3VFCGnoVIn9l8YS82vIL25UJxQqQAp
vZXQ86zFFXbSohGme5MxIt+iQ1NjQrizfoToh7+cj2eCyXJuP17ST8cZa2pO1Em/ayBm9ltV5yrT
SVFUsAAs6FVJtmg94tk6CaLmutv53EoTYsk8mPZFrdFV8oA8hVllucEtUj4JXcLr2zTdGkxhZJPO
SpuaPlDfIHThkyfIttjkwT2xeeToXCpf5gIxzIS7dcE4ndat7EYq3PPGohXO5ZZKe0eiSXSyeAxX
vBtAWh6uFpF2m60geL8vUuXMGvm2bAHZm8SZTCxq1KPi/uGoksEWmgUJc5f8/rRT++yr6iQo0Q/A
fN2b3SoD0Q9Cv8sMAfM5HbfiPw1g5Vhpew08fNvrEk/KDHmAAo/X3EAFnXzfYHV4XA6i9Kz7rH8o
W3n2eQMwBso3VkxTNtS9im1XZ+EitOkbQ9jO//STKyk/RPXfoall2EAcVe3+P4+9bmsPj6YEai16
QYYYOC8It6Ps8z75nnI9HpBSGQvso4jo7f/DOMvZ6TJggcIa8BdZLQIrtlHXEqJUGUfim44kcNUa
hrlxM9XFtmKibRtYp17KYZXyuClrYjoBlL3MspaczijP8L20oiW5GamktvH0LilEY8/Alkoctfo4
dZ0w5cj+uFnsS3NlBAjjWsgHQLGpZtXF09dQL4la/rIaMiONTTOuSahWhumfUZSbwYuxfttU+5Lx
hrbQDQq2MZ9LD8bq3ZHF4UWFUiDtjchp9ndrjMM3PT97IJ2cgzVPGEHtLtWPn8+jPv2//OYGYXW7
5TO9+vy+jccCoR6wl/sKlsJTdfah+Byec3cqeF8cAAwOKzwz9XlsqW4Wlidd96qyfvWhvfoI26nc
ODj68T70+/A5rWUGj94hkKkj0tZGs+3vRPxbFnvA50Fu/JLKn8IwZ+z0RUgnx+3mLZCr+DIFlyEY
FasG4nKnPH/1225xxD23s6/wMuQx3YZUg71+lXd+baDjz40BYZ+zQpQ7nf7Jcr3T23qg9yN9Xo57
9bH5n5d+R2PflSdGgR1+ExTZ9yFa5nEIHYdL5FzITW1uq4de/kv6LAv+20Afha4m7tS0LeqvaDHM
nwid3v2ca8eN+qOW4FzidqoiUTMVeOGTCt0lPhjzSOuZ5XNshdFP5njBfvshFRiZDZN6oZKexcF0
SQd/mGfMoNnSJSths9F0arZCSd+0Vu4umo7p8kN1o11dF9MP9CgJ/ISciJzp5d3ZMilnxwWpj9Wq
63MEUx/9MmoHI9XXkGffCzohdUlj5lPFciXL7hERZCYqZefpEwrKjIYh4Bk6ZReDfcvuOhOfvKN9
VgBaLIK7m2MbQRL0qz1pFq1APVYo6tsvfisx+2JoewzcnQ4irMibLJEEKxBJGNZ+A7CorgE0WE3M
l6XYcivRqUanGR4+dvL48PByHIwaD0rDSaRsjL6ewP4Z2wsVyf2OEAWAqYjHJ3z4uj8R/DZnzblk
7/zaZI9FRa596vyW2FFt9ijgtlJ7DimcfOyrFpDQ4uwQHT4viIcu0w98dJa8ny3etHNuVfnHkKXp
R1Ndcoe3plI5WsHvas/co6VB2qzth6bdIZw0oLK+GoyWcSKd4UkzQ2H7AIJrLbFaKtwF9ix29v1M
1S0byI/VjUJsRomkOiPEMsL/BVAXzHUF6mkFhbn/y+JtCykEpdGGwvog+qwFBWd2c0SocE0HMYMW
ZciXWDmnlCzBLlUmZnFXKC2yY/YQHpQVEQWnlH4lWvun+wKx9Hsm0pmTtKaCmCGmUPJQ/HiLUiHF
/tXr4ZnmGDxmRsD/fA3cZsw1xyIXZV4EgfmSwbgyMWtIt4ruHAKEpLU7oc2JhSEUhDyQUA1E1qxW
FwGyyWI3itYO1pViiWCqKa5j4qjXlw9ylCXjF/d19hNbb1WYWATNusqIFSX19LxNIdi0V/mOxJYC
jdrkqrqck/7kJG45BNMsoSyJRxbDWdleMc6hs/VYTpVj2+6CPX223Axyu3LFo5KvboZntZnALlnP
xHJLAMVGTy6s7ANDlpIAiDHsuiu/1qab8qoeUniPqvDXvrXvU2Fv8hcGbcyIhrcFDGE8Z1mUcQ2M
DGTxKhxyUNWh5cS6gYVLYShacQXaPZ79b4iyrv+rps0LM3uheKqw07W6eaWe06GiAii/ow4rAoFX
PzW13XzH1m8rxas6eZLamgod36M6X4M8Dnt/azOuB5F8A7tyu9gKM9GBWyDK3bu1cgsxBZ+6hcWj
gnlZ6pTnY/j2ENDIXmfeBNSSuZmy2spE+yCI2JV5HvmPZBjCIhBznsiQ9OQrV7LjEuJC+TqgS5ZS
olclMUCFxDXjyEJRLp6of5NGl+Sd8sJTfhrEMVU2KgbIRRoZAcHGcF3GAF+hAfSx/u0QH410LL+Q
uMJSIazP1Eed3PgYRRNyWNaEfjs8O09BflT5XZGaER9uY/aF0VHv4QY1u4JLJcO2Xf1lGasx89S/
RIhXU93v9QYYGx0GOxU6uw4rdZ/cIbuFkyODV0e2UbR1cNjt7P3tzKjAcoGkQN9uLGnBV8+XA3hk
pxochmb0JpoW1UjL52YQrswnqRftE8mEHLtHtxBvcp//zfgfHF5uj4QOUP5N1341/bLYWwOlORVV
iXuj6xunkPdAj92yI6/RnDFVhTEKfWtcmWqy6jdmyUy9AFXNES6LTWMN44lNVmaMwEKXB+cEvow0
qFKRpZT2rTcxspfMISTnH+2yxvntl0M3KY9D/T5vKfLR7W03px1Ql/PB3EjiVPaNC4DHtnN98Z2B
z3k9uBlVPmz5JZJRGDXlyWr0ArlnsI/y/pAr0/SfnpE8/TB5ByTkYNfooYRb3mNYPX4q7lZ6gBk5
T/f6BwFl6wb2OClwFu9q4uLq26V3B0LsS7mvSosrnlSs5h66FMw46pkvdXhTXm0aSDfsjjDZUgjZ
39+EUR3mzeSohzp1qHQ7r07LFbmgf0pVrjTjZ/CgZWTyd3oMcwdK7C70ohRjYxvWfL8+liwFDWoi
ye3Jxc5shzR7/IN7tPB5cGhrjMgeaUwzQO6eIdOwUkfnYdt7oEuCXcieVeEphFFV3TZEDqTRTSZY
0vJBU7oisUQEzQK4gD0tuM0PXRojcNHUucA5yV4tV4sDrunZLkjXuQSXWS/Se5ro0WTW4yWZX6OE
oVZAaiBFNFrQX8D4PCWpY+SR11vC45WpRyZUa10wpU6eeZoLMpnFR/ItjZvBtGEDrc5nT/PjXOqY
eFA708TvAZn07hxAHLPBUenrshgbulBTIzesNwSidA24Hgxg005bHF5mXLZA9dLpEPosmH3n/xgK
4sJm7AxGovfvLfKffkv+0oYu2bTpWaYrnV/dpAnMtNqCRXvf0Yr1twbensdXuvzjeTZFQ7pXJfpA
I1PEhNQmNWyIhEVrwSlpA9qFIQ2PGKmXcq161aGS8lj0H87Dv1ju+3MHa6MbQV8Ing9gYqrjltQo
OueAUxf7H84YFWtqXftOktxxx4SQ612Mqf+qb/gDh7jbvF+ItDTB5OeW/WQToumx4vsdVTgbnvfk
kD4El45FKFvZIT6PfsfiRj76aCkTy8UESHrnkGtwS06Q4OJ4P89UozIhoQdM8ePE71COVsZnCamN
yH93vEJ7zJ2uqFzZs1+84aY7MhNJfwlvkMgIANxpAPYzTZDAAP7dgwVuXCAJOfEs0QnZQNNpupuE
gRpge+xQ0tsaO7kEdriIbRlp7TWM1RTx/UYZmJYA6jNNMQ95Gnyt73vA2AP6hdvwGB5i6EHRgoBi
rUKeVyNNG1cYFlXOop/TgplqWIhc0fMzfHg9Mm3Xc/z3ThNVTK3yCcAGdbochbG8cq0q+l8XiocB
44D317xqpvJFOXCbXp7dx8arZ2o5R5z+vo4Sp+dIvHJBtsSCzbiDqsFFdbTFlgV8nuK64eOFZkIv
5fGayX3p0oTJKuoD+c+kWuWwkqFkkAC+9Lm0pIRoEeXVeLw+9AqvHHOq4uIu34W5+mMdpkkmrOir
nXMKUO824HcxYoN5ZN22t290IDO3JItaPEc92Azy7xL/VwCbs8LOtzRr17URJXCK+lq6Tqoxsoe3
VC+RHF7LWRPv3OkT2R2OUQImqVa9wWDvRWnBkj1etlD7mTyTqB9HnUD6CRoqiYolP5ZOP8UOzXBU
woCiFX/5NzzmAt1lXBnbDDZSJDhk/IuBa1iswshzuY6C885mY66aNU9G02Bg5b9aishmWj+qDyW0
m/XduvAKZOYCPjVx/Twx0vkDlBc7OXoUFl7eXYZXBHvCk8FiceLr3JC6neeIivl8G3w6qxNFdh1/
5pXesLq1QeyC4Zv1j12G/rtukaziTxcnZQti06u7Bgu1yfrMZ3TiTORg4mQYMruQDsaYFUCYHbWm
gavrfg1QhMt9omdN3L7woz5DhDsEkTLrXMoEyGkNwV0Gu2N8ftarBAQMGUpyLA+vjdsdOF2Hoo2I
NLxYByDaoJ7MOEti8IqhLnzE9uIiNNS/q4bFuLBblLg/pXhgKJA+Do9IzObKojsnRzMSJHDQqHxj
rvA/hkUgach660iiBj3CjkW1YbHhyxz2lq9JZHLQxdKoNDOgc3mWDXWPp+7bO3NSsCNZwt9dqr54
QIX7b9PAXOnuhfozsEgQxykY+ioVFyzRMkYdxxl6jM/frLiP33KRlQu70yFblqwD4KO6EX9DUYec
3K2wgtY7tDyMYRiIoUbUYsbmi9gSopMRpya9yrwEO+n7jI6phzovqk2wbqTGEGTtrvVBo7CtOOBQ
yZLvdSYu0cn0ki8Re6vLH+9Oz2Y1PLoMZ0dHyhYzXjK3qKjf4iqefpnIatMs9wIeFLQb6+8oQmVC
KIiUTNWj3dcVGGaoitRd4QWWd+av8XJ72RQS10vexhV1/q3qtAiI7JWwXeHV1gsBOtUAV84eiCSp
Gy3A9b1YqsbzK8UTPjE0cqQ7Zs2EKTymM/AYoGr9dsPFmRexfsIKeTerrCDcjCQZapHS6CEbEQgd
GOiZOzGSOBpbRY9P1EuP9l2Nc1kyJqBB8cgLFxiCyl7cxmn3gy9ZwRCH2RfnSTiMCPxXk+gxhpHO
MiZygT4mkAAIqaZD80x9A7EgQFLgE5m3xiq6pm7oFZ1+POmIEbM5L1hcUB/H2Z6OVY+7/4Rklay+
PmMpmDXh5wn6m6xhJyPfM7u+HiVqWhlJSIg1XlrYjjWgpL/DKd9Q2LHMPxIlzBDL3JRFG8NOoKrt
XnoBouu9MMfGhF+NjdntTk5aKmtDDoT3Hn9rZipfC6fsE9D3nfM8XJiHzp7amNO/u+M3tbIgx6Uc
ARssUPnx8CR10puERWpymZAOLEvFMr6gs4TVsEoCSbz4JwogFKTWdvCD8Ocq/7uss4lHb5DF3RyN
5IC3ZnkXPvlRvaqXCP7H8KwQPvik4REVBoQpt5yxwRS3S96C+/NRPxjvxDEm1VuHHMvE6N+eZKS2
Tt8sD5rUjjCb6bQ/vWCyk/gLNbvECm138Ap59gsbD8wV66hcH4SBSdJHQjI/fXo/9LTvaLZgLhtD
L2ED1oJJXNuYblyN/a+n+ff+LKWWYd9ZGom3EZXpu8J5BlgGECpmmZyZXJ9pmMDD1fspw1/zDmxj
ewEr09yDLZD5fMti0gsirSIqHwn0XE1lw8X3xXbund9Fg3hRa5TlNQPu+OfEsJDCVn234+EdsfTn
Jl+aWD7MYBcMEoGGcL9Y/vlnw1geQq89GsSM1DRKlG1ddUafBZ1SfXgEKmd9Bx0qutxMQh+6TM9Q
HOGPrSv01HpTIacLDdhQGzjAjLR6ikEhm6WzTuEaG8GmF7wYnofJyF9Nsq+sBFAUs6R65synioz2
3g6ZKkfGExoSsipqvG19necdHPKZOVQQJGzPHdTphRNgU+1kYfxHbX2R23L2YKIn+SN38rKZhd2a
Z21ELlRAD8GqeDfrKGPg67qVZAMHkSox8u91THHAr1PCOsg/S3EJG0swW3sbK6tPNZ7QjUqr5bAk
vOGCw8YL0o8E+VKbMa1pPfuqjfcRNaVCgyj2BjUQuYKjcB1fvargXZTGfHQYuaOIQTD9yeLzjJdg
DZOthIGzeI7719OFrUNrdT84ukipCHrIIlyC6kU0LnhwIOj9vpcBS5VJqXozrOEGhbUIMiWrjjza
22onpZZCtYhEJNEBdNL49WnZDKToHFLl8H+P8Zp0gFZbYFIRrVM29yEzm+yEcJdbGxZc6q8hi0zC
iemTBEnhZ+uduQyqNCDSx9zl67boxy59h/YHHkMzkgH/8Gx+/+Urpj8EJIrlmVq6Z4UgNgfx5JrT
GJusCuwkTZWrB0dRxVx9m2GtGXTNpesK5OitVrb+N50ygGCp9pMcIaIDBPoRQeVdSRz0pa+BmU0J
p5Iu53aq7h1493B/1j9NgRTpaQSyyBRGBFFhZ8AZnMmqUwHGfd97rYB2skk6b9iu32v60IIbQQC3
gWgmJE5iXMOR2XK08VvQxBPfhlsKYiVjsrbeBMsKM9TchBMEfa7QuHmk/MIKHBzicwmlpPU4MW3f
o0rasNdqS1zwIFjZt/AjCDlbxU/Rc8WT8GlzcHGZhDGcHvHOpKzKfXUybKGGjJB4M6XiTk2RP+UJ
djzVqqWp5R9STR4bEROYU6Cbe/72z+hjocSMAUinNJHqgVAMUBYq3nW0dlG3uypczXGPCjJ8ChbC
zRYs+bQVRPNuQjjljlV+zDYfBac028JpbYMnOAnwYK6qUnofzePQhQg/4hw5ISXDe6VX1aG2D57D
hsTby+Bo9o5nh3x6qZUpc+4QXWD90EsSKsSt8DSKO6+7di5F7o5lIgIB3HvypU9v4/Fh8zKwRFTI
P0d34KiEwBooLQJXoWlC6ffvADw5tZt982TCO6BfKeU7QzNtXG/FHf4zb1kXiqcEt1pFI4RbSOV1
1HKUPTvx2u3T/PDODUFQchG/1fnVNZh4vsz3Vl+A3GtiMpf6xtdrwSjy3NjmksqXgJECk2NDLb5g
BB6j3KicUeBzRjj7igl1fGYKAgPNYs9vRQZ64uWpU5Vq+VWJBCKo0tEsUAsgXCY6U7yPmlVEQcnZ
oD+4Uv8Qk6qBx0ZDyMoZ5rEtrY7ljLSGLM+pw7/D5Hm4O0Bk2PnNZxKWei7TOejCrUD6oSW8mkk0
q+HL1C7r9n6XNDI5LyVX4/0WfPCFDR13LUxa8JUbGT6Y3bRzG/A8XFfuhNFCyRdaS2SRF2ITic9c
hrPIxA/+4WJhEw4qE29CdSj1BCFmVso39oFs1z62xZQ4d3jd8YPwkoKj9q7f6CDMri/ud3zOFdWN
nb8BR8JvOvDDSAq1c8mDsBfIySH3FsTZ3rTnRpO5aZ2ZJ3kmZcYxRw+isaKuY15LoZQlBW7bvJDF
vvfXSDjToRiE/d+RKdWiEgsZtr2dUHFSG9N6DWxJMqpchHErqOBj6Y6BtzvARWXCaMICkxDo/ozH
StWnIzO9ZTkaF34ucHj3ovvBI70ssJX6Ojza3HNaCUyTdcAE8+e/0FmI9nfWjT6C7RmqS23Csafv
bgl1cEpLLJRG+PCR5t+g78QU2nikiMLJ6o/oIDbIqr0Elkv6reEmo0hZ5KZlJn/AGriaFrraXjOy
fns2EDTade5fdKai2iG8cX9Nq1nEoU7O9xN6zTR8cXKMAc0dSqt2VIhyuQd83oZZLlf0VIyvs1Ku
wtyJgBSbH7NODDXPI5+Pkb1HEybg9HCwsEPQaUAmyisN7Cqgyp/0+tZC76m+X6eTY0D9FtlHoSUJ
GmGMwR/JXBdpwJtM7qmp3wqaTTV5jYXnpwE8DPehYdcGZ8cLzs5jKGNtcVmq77CVhsMqIjkKNVEK
6q3wQki1Ex/ch3aygOjXPZiGfRTnSRrqbeyoNY7iw95P7SvMMk1TzXdMe2gH0rjPGxukuNyPjitD
5sdKQR78vUlheTykMN0W2SlbetZfuohDwHpo6EfMqpNVanCsvbIFoaD9ybUKATfcxxzMvIAqYdHz
BdEx4R8nuJZ6/ZGDRbQ8Scjlp5xAPO+AGNCLajRAlrlE4IlbiiksqlpHEfk+S4yjoOnWyMR9h/dt
vahZJxbALZgoP80HnyDGgWSwzzOJDGjUrXVBLubHNFfdIxvmb+V/AsfGa53lFF6iqjEcZfm+W1oi
aT0uBfsat/lNp08jKJG1DIEe+FAFQtS60Mx6RcqxVua7Cqs8/lQ1WYyAkMgonyMNWcdoelCY7s3P
G9YiOsKMyNVqvJgio7SYsEGRFvtKqfU2mZXM3N7H4+uND4+jvpECzPDvIn13FKI3F1mot/rlpy6B
P4GU6tyjJcq6zCTn/ojjBO3h/Mt71ZgWjVGs6m7eYsFstteaXAx6EdjQsrr8QqzBwnIXnY6J1X+q
hLU8xWEBmmpo2UDVorYnINLNAraxhVPtb20Lvf4Oidotq2cdFmU/ykNgwuvjcgPqo2bjobT2BCu3
rSDfulNSapSv090ou57LXTz0Lic/WU5xPmb+XNxNYSRKAKuPNGqhfbKsK+Xts8LvoXonRV1t/qLq
Lo8WzqK4P/2j3azz8Zvc4DOG6RZYo2RWcgJiLFfOF3aa+yddeAIGYxHKGRyodmSK6QWEltZxNWN9
yKJV56mJgvl/1UuwCwmP1ta8sm8pxsu43KP+ufHYVYztJOjlC1Cag/K41Y/EYUvioEu+GbnVa6ZF
WzROKME7xdZEOlAeXT+7ttrVVNgtaa3J/42w0dyr6N+TB2OjFRwm8uXSIah4dXc/Xiow+E10XKux
r6is0/npYamZpR1np3/ZgKOj6Ob9Rxvo/rUhyH8at0WRAE+Rn3jQrxGn/UOmLprc9x/GvJgXTtxZ
7P97PuXRpS4/AD03sQbIqOgsJDIgSarov4UvdBJ0oy9a+sFNyLoEm8uwIvGDSV84/1ziGCJ6Sbhw
EC/y8cDH7tJ9w6C7FZDaSmO71vYvClPo4u/L0Q6s1FjLPqyhk9zW3Zl0SusYy2HoTXGxEromOjhU
1AaMQS94N5g0RK9kZYMMsmcdXpN2wKzKdym+fFXp0EKhKjMBb4hP/zjhEaxe4WmhzJT0qzwZw6km
imxlcj1S04xu2gD1zNDr2fYarJW4GFYMfUngULyVbGk9zp0e3OLmt63asEn1kjgl1iREQFp/6l/u
PQzZoD63SRK4QF8j2fLG/HQilfcUQkNE2VRQvScN9Vbo72wQdzTaPg0XD6jmpuSBjpZ6jCoUxHdi
+yxFX67B1q4gnECCjQtQJxV6edEAXU3RUu4gf2YCbZ/g/8TLqeDPKL3ipsJNrzGQrMT86ViM5DPW
Q8Iec550gGJyIKlw8EuA7Ly4TyuAP6UOKWDDspHqM7QJv/Pip6JMrhji0Vt8Vw8UuI95pIQ7jFDC
N6Y/OUBzSWz3Sl+Ht3+M/uU6gIZnhSK7DQ/RqsWtoMJKoaoeA0sq4IKXtnWLGgxEcCNxKcsTgfeg
0pZEgqaqTDox/tD9IYiwUEJeUiaT6TNESB1GjKvuhiAPABG/mRitu0CVnkRMT6b2m6bg5kpfuYKB
+lqpbzRHlq2Z2tbu5Euw2vo+lHubdOw8Pg8xRevLntyq4veRSBAB7QlT6GBYyZ7QF51xdiLSc8rz
Enk31WczBhWkJZEHahUrUmc3hgqSkQGbjjHxD9moQpoSc8kMHUFtYAwfqmnKhesdZi5nFrHTthyk
n5uBJjsehOrCwAmG0PTAoHptO4ntteAp5znGeT01B4ecHlFRxs8v3M+eEIfMsPivTvfdyrXcVeR4
R6EsEl1M9SYjP5UFWjPXuI85H+CF89MiPAu6NNxnFLAaIBoU19K/NgtZHCOZV4zQWVJCAHowvD1Y
YAHDAESJhmULERWrMYM41kinr3o6jusBjQpQEccBJOIW7Q7RQWsFZQUvaKVV8o+vY9IqRE8wS8Fx
TZrDUL8SNh7gsGqVNvlUx17mnCdOGa2ZvGHeCIcsqlNrUpsVjC8eaOYzyf9N0r8ixb4KxxXLtjWd
f/rBOdCtVmnVyebvNhpu9BiILwHlxmZDRVZa2PLR9qVqhwJyRhBY+ve8hlQqscLM73L3SMQre4d9
bwWOKbG8OP9L/Y224kGaMAVqmIBLi5GJbHm/MIsToNOzJdBTM1jSrcV2arBi5tx1DdOz/NPBXc+e
cXWn83/u7Y/eIuEO+3gHRrGJQfa0Kb/XduRX1a8qcFaZmffXe3wbK2lq6JEOuBZGwdnmFq5xWtmQ
Xq+LPrqPXdyVarDgFQ+tWX82/88VWdsK6gausMn5FHF14Had2J1Dlge+JytAN7UZBVW08vRTw3f2
nqmuz05OEXdzJKH10xPIBfPTgcH2A4UsDi9zebkvjn79N1wfJ4ZpZCyVYG6AIGFc1hdfYdYSaO4K
sbTLWC13/AXSAH9BBjeHMBIzyF7OpIm2cVMcrQD7GJjkDVXR1ei6UIVTmD+1EVtYc5CEAsffoda+
EXe6it1S3FEdh2PvPPrRQhro0k7ErdhBu09hKjoDbl/I2OMgnA+fjquRzJLGEB7ZIfQ2kYJVBVQT
lB35agbmEXW0NUJf18hXr52Y+Jqs8VfCRwzx2HfDwjejEpdbsS0h30fUg5u6VQ+BykJ7ozSghZT3
h9RTUmFffGXL3rEVzwby8ZocNbHNlHI2mbwOzPz9UP/Hcp4sOb9iaPhtvtK+3YSwXGGHn+ZnlBpk
R9Ki8kRbt/iTMmjhtoBOpVWKgScMXc1CH+SYLmfhOsVSXhiUDXU+GVGpM5+IMxNoeOpo4rXYp6xZ
ArEPuGWIuZ/JEuaEp9BjNIihF3ux3aF0z38NrUSC5ZUIPIGhAfrI6HIHu9wviMdvmGI7Dq6GK9F8
K0Lxn+8c0jBqRVOFxlMczx2VSyKMQLRuWY4PmZilKNhDZ6VgUzGebnKn2rvTYbM2G3MtIGFrK5zI
MdYDUMVT9/NfT0ISyQ5i+aDp9aT9/GamyfGtitkYezmiZuikRVeYCx29DnkHUiFXBxN6ksOGhggC
7gqYd7jNxMYGmBbOG42pei9w43pPoWX2M1BEJqqoS9x30qD7HaT1bzJaqQ8dqhO1sOQT+DtKz2gl
1/HSl2Cc0rrga9w5Wz8QOqUXh8B8/UZEhIj4b8RdlaeJHXJ+yDuo/twqt0zXi3QTGQmcsQTf5XzA
CYGOoIffavg+ecR1463nJan1O3FdOJeP4Kg/OQRxz7xqTteuAQ4u2l0Kv4j3qqSvsZKiCz4hvrCH
REPuBLBftvVmmb+eMx3jQqoXs9vSC+lTvXj4iSM8ZP51qaXHrzXmmTaOTOrk7amMxrNR05Y1rUap
SgnhNt7U8Sw9sp/tTozToalxkO3La9Uq6RZfZlWOncfbuPttDUZLCULq0sRjlx85AWm0uo6AkbAX
W0dxcQ0DuyBTWrxkM900hTcKIVIipETljP9PEgPJCsPJEvp/3xfo1IZED7Nsizb+dlfJ5pcBVsgL
Bm56adCZzBnu7lmVpnptrRJUe9/+zL+Fe29jxKlou6y3/gigaRunV43MpjTvlUa9zXhGqDJmYpas
mAGzp7kJIInowQgHt5wZGKUTyHfofPLyhOE6aS2ZtC4zE9o1mk0rm4WicRsZqV/oY9+phoL7H1HG
BWcy8C7OWDB9PfdvUysTAVLzLW+3YMOASm+Fwo9GzMmK4X7Mdu12TbHvgdXWku4AR6trOGEUYb+m
WRVCt3sNX8dVYApn2GsYVNTyOQ64BoIgVo8JG54ViNEEYPJNDGRQXKf8tYsYHp8FytLdp1y/gPlM
2TQLHCg2eeMnN0KJVHHuD+CvxYHJLbHDnQHP7E6+vSajU+ENs4CWBD0Wq9VQ5SrK0d/barBYxnNT
6yTfWtJYsSbB+mLdhAwyCyRdXKPsKoCtXEl5n2s/gzEL9yizd9IdwV18tEt0C+OdQhjEAOof5jpc
Yr/bgkdxKP9+5uiPAzKooZS8iIOQZR6X3kDFT793XOcT4o32IMOVsVIXOPykVvZ072FELzj2PoCa
qzKmE0vHk1A/VPBsAub6BHDiNmezXbUeaXd5Na3R/fDrpdloHkBIANF5dm4CQCvv2wZfzunCXjYJ
MtWV6ma/0dyyStEJwHoCnMmZGyByjCBQPMWmR9iI5oQd8nGuBOzltpH8KnYcxupiGGgNhxaGzpFu
XPH1fzuKsKIc3zxhJH0RRFMrjG+eZI8q7SUjqN7ReE0nNS3v3vGbKca+TrTOSMs3a2Hsem2rM7jm
C8/eXHXdM5UT2L/d5oG2Wk4dlTc84TrfwRbk3COqf6oDPCTeC2DPUjHZtXvj4qqKqfLFxJn5jKXy
f7OQpBn0Y6H9rzqSqqWk+DyxK/1eqx4rGbQ/mQXuXU96zsft15KgR7JP9omft3AbSAmvCZgs8i+d
KugqRn0mHnnJeeghvrqMeuBofFHDDq003bDpkIHrbfckyl4oqwvl+T1/RgE/p4d5/nhLKVJH/0H/
rtztQj+R+zp0JjSiydb8SDxbEma9sdEx2FtkpvUXcbs+XunmIXI9dWzxdg8IS4jNcCj6Tztv162W
rppePVfwWFjujIQuqNbAnQ0WWoKy1MkIhbTUZHnO8CPBJRHpihVO3GEjwjFqfVNOztaMPqzrs0bf
fbzWrV8i3gbvdjmB+n2+LrfEg03+qE+56LxHEG2z/zyMEOwpXzYRp4XFAjzS/Ft58/XZtIJrLyWT
/7aRwVmzkgiNwDu5kOICGnprxlQw9vnMvkjzwO5JF/BJujv7pmZQn6vnfnnqvh3uYhCdTtqa9aXB
0o0/VF+9s9L/HdIMEB2lSU5ELrNHTkGX+xOdu4M78wNFwWUjKINAaOTlCqkjld7SXAC9xhO0htBO
OBXqkSHCAPKysMDT0giFk+45THjtILUceXXlQNXFLXBlFYirhwYD++qyerenxgaNLp4sJTDQWPWG
Wkhp20eFZ+ukA1KfzwrX+vcqcCHqSRnpKOOO+AMF3vwHvd0J+7cD01U11Jm9KzaWxh1ooXCswH8L
AJ89TV2MYadVR50JLByuxDom4I26GrxCcGfuO25KJCDFlIjtQ8bJIIJMVme7Ga90jLKyTSZVWGWW
fP5sCVoVc8buEosC0sdddhcXRIEJFu0wVMX8bD3cE8Dvuz6914yBmllGxVCDsX3NwXUMl1NdigQh
USDQ7vkv6WUC/CP55mVx2HM08LwoDNWvGY3pOs32wceiFvJSXnnrOhN56MvWXHmLNy5DzhEkc4L5
GXkwjkbhT/rzji8JZLkb7z/KKljdEJPzAsTZHlWqdHULTeFnZuCNMWfu2OCGsX1fLVOWQzWaDJ1c
sLrnhv7TaEV639R9OvZBLnal4aQSa8008v/R+2FVMMP/6NNwQ0bHgB+apY6ZsnYKlOrLMfvE5eGC
bB8mlrkwOVnegmeeArTG9VUBDSiQ9Pf5HM4KpzJcomOdd7fw4vPm7kp6/YCqTcXVlKmNtvTzbzvu
AMP87C1yHs+RPfOeurZKviammzOAUMv4/hYkq04O5aksB+SVwQ0m4fsVWcjI//V0pLX37Ibh3QDA
JXYWgReJ2CcHNHIlGtSGUKlZv4scTtTDXmDH5oP4GPwrpR+UyvzkfXX70HFqaDanLS8FJJd6x7XU
OxrVNYKKPYnmOk5HsETm8Rt2nK3eh/99RKO4TA5l0Ln5lQBLcRbE1Zvwq6Ifj5d2JQVqhjk+zaAX
BoBfsDKbGL7se281Stym4Af87XOkpfU/7TZfOAkKePyx4intS3X374wCTpUJt6pVyF5YNyhYzSXX
1CuM8Hzb8Xa4N6ib2QKQb4vhE9Towg+GiJJ646M57t/Yz4fgBGMHGI22V1coE/SOEUMGIPcVqomC
Y/FAjBBkVdTCNt8/byYrUVV8t0ZwPcBakE8m+8/IO/6uymp4nAndPkWl4/VjGO1cbsBBm3m4Zh6o
+NxOVz8I69Aw0XJDAAeurQNEiqjUOHrurqzU4DJ30gw+Tg4I+WMLNMqF5jGjTYalNEMtVyxCnyKt
aRoO8UQ7EDJzrTsLz06tWN4HHJfgLkCP2NL41AdvuH/nvnQUGjM8ZWiu9173vkzzEaWpBhEwToQd
gq6OA7zbyi3q7t643sAdsm0o2QEDXeWMan5zKcmonApVoHFAtCJW1nUsw2P39Ooykq4IPkfU1AN8
kI/dZZHOdc056wvEihh5gKV0Yf8HLFC8oaTEtxSr+Z6hF6ao7dmaLZVLJGYUH9zAb/J4iMY2FA5l
j3m/wByyJDED+fqQlvnAl0+M1JZyUoC+5qfLmc7T38srKQW3oGOFlqGf7ROaq3L37Rslq1S7DR0j
MotOVTpjTw3dLuyrUzKpNyxI++XLbf7XohWiVbThEF+I52v6LZUXqh4neSyIyYoaRXCqjY7bqWaP
hKd6B10mqL5PjeNi46KHiNOBb4+5QlmHFI9AiImZYjAHMMo9ahXyi2IfHF07MiPM5UrfSw6130DL
B8KPpEUspxODrazsH8XzP/HgZHJh0E6PY6fbedz432xx7/ASXB+v/G87fkDFekfvdJBVPsAVpKGU
NOQ8ukqsAd2S0oRmi/4kIg8TUNaihzy9Vx1DEv6aEK6Lebc3VCTU4/MhB5EOTcn8vKW3W+z57CKO
G1vaIMU3WrP9TI25HKhWlAri4OhjT+dM2SY23JMbAmpORfJyIOZTFsTBEs5nEZEGaXOfFAsHlNlr
pBtPvqKmb/KIVo1WwqLNiBS3tEkskc2h7RXAf+7Uz91Zt1CvhaulLpMdR3FDq9qZuIZvxTi1349X
BgvRJQb87iW8qbnSlA6SYifQ2wJewqsH+6xDydmdCayUIjCPNEWcE+kxemRtR1DXuL5zlJ0gGkDc
L5G3J7W15zur376Bjcod2cZsOh82A30n2E4kUWCHtm8P0C1il5J8s/uJXSJlPvK/P6O6YZOTcUn1
jK7vYqPpvDnys5Z11VWITDVE8yU6SlHIXSOfV4MegSG8SP0922kLAyfp6kfjRtvwC8oGHiRcQdFz
oyQEs3N0eZuqBTcxbYwp8vjdrf+efyQofKqxOq+hB01gOZiuureY4uwtOJo0zLVjaLsr/Vr8qV1d
9Cq7AL6NGFQ6vnMMTuBbb2ouQiL+eWs3M9PQGA99Y8NIe5S4OYHLxaKQjBSEoIJK7NIsduWtK3PZ
ennsydxEfCpHQSUZprlMBNroklmR7j1+D8TiuwHY74rrr1vfZvxOvFs8UhiSjCKdT/P6C1Ak/rh/
lD3Qy+1rFHOwzcepif00s7+9TqwtNihAW5+DzI+MeXiENrJ/Nt5G4z8W7Bk/MvB/13mg5LZL3pTj
vghofzFevv+BmRSAcdOYGDjzjZzjZebwzwYCkfFRhYhjFT4Cd34FyOpSADgEXKo23E63y0Y6Yr+G
MvM+S5hEPmC7oWK4RtH+Nqv67919sBKlQNWYLjmAbVmefYNavmz4nEwxG8o3YdQ6UKT7KmA7XqEz
kjLYMdNlBF1HdQpCmZ/4vMJQifiDAhoQ5mXWoxrvf5QlPeLflKu+oyzoBE/VxkpiUaSN/fl3lYdp
q0R6y24kIACJ67jnJhjBfeLA6k3e8XPkGm3JL8IL8FN/eaYvt54CeOvquAViH8Sph3Zq58FKKL2d
FY7gHFvqy4y9pAoOEfbi+yvYxfl6wFv3HtEfzWWtj3P0I6hIM64QlmGjsKZTDirJ6aQhDDIOR3pb
sfrVkBeXUVasuuKmTx10CRktuXBlp/iiDEz2lCkKvGTYHeXcuA0rDt4IPeEAljJmMA9g9LP1mV4r
yvbse8KaNM5aijKhMH6JB9ngAx/xCcBjhfu6BVRCqlM5ZNYnEJCSP29ueU8rXfJNDPdfdWXdNx4t
mW1WJk9LPw6NYqaFhU9vjIQ4efO+uJe/V+PaHYLBvBN0yPvWAgpuNoOJJRF2/HxlTgd9rKNDbBy/
wEMTnIQoVjuPgmbXFUnxK4862wp2STIhw+byb584TPkZEd9m9v8+TAergKkexGuySCMsUAJuqtoK
TsAngN4XFR02BmmaLnzySseR0uUmz7HP/FueFV3DKdPESf6dkbUmzVRHoNWiTEQ5R8XMlt3xwT9p
H5q/Dh8fe0HewO79UZa2ckqJYOWS8ZLtwVhcxMoquWTY3ua5x1oSn2668UO4nASEI89am2FobGpq
Aw4oqbTcpah+iycMtJf+IxgF4f7MFCjqmFkEcKBNnKTgG3tKr6FFBeswli/qTFhoFQklX9sPlbEs
hQI/BzNpCuQSQYVUD2Qz/tbNjk6vvcSUDt7EDjlCvxbRQ1n/LgdAodXEUvDbOeaNhSNqvOmVqmI1
2c4WuysYH7LXpb+MVieD98rSSXpoqex9zjdvTfoJnZxv+MBaQfwXMYBY5HSuiRKgflaW7TPN+SGt
VbX2z4ki4dLajUXjKs5C5qTfrGGcOEq3NnZfCdunw8ft1haNP2Bjv3c/w8Nh0oAdmkWxUvWuMbgE
47a20+64Yee1YRvTwi3C+/xuwGzoQmxTGUEkhrIGv0wCMrD7q5hmPy/S1cBwvK/pMTT7x6Ix3gCK
FXuHINwea0GMMvNLeBU0MSQ7LQquOdG+hLs0si93LRdw3BKpV2V/k9RTuVs6wLi8vboo6jo1meHM
xliIGbqoOYrCshFwrK6vjkwlNR7YKj7fV4j/4viQUgcZQPlPFOh07mkFMwxtiW6fKDjD1Prt9bp+
WSX11M69ionRP2+zCrTA0fdOYHmf5kq/qhwIL4y0ag8o0dsUlgYy6LM3cfphz+0utu1uDG5UjxPX
bP/XBd7v+yiSIOEbKupkTkiRpuk0lS/bySu6Oba9+Dp0sp/ZRXbto2/f6ZPjKjdZSzwn/UPdYCue
/MtCAoO06m/Oks5DDFlRdrO8arxpfG58QbRdlvO+ax6uFHlQhKxPr6c5RJMwpZ0gLBU0ZdPtklIs
xXln7vmJ897F78gpresW2bNx+le2JVW2NkqYdHFBa8lRmyrSfUL/GVhu/tnDa+9ruVoTOFSHv+UE
iCI9OP2S9YKpMxDA8y9ZtfVe2we90drar3RjWuO96fYLYWym+TFWogLD5Ub0TY3VPHnuKcw6FLjm
09sCLREkVWLCH5+UQjGWO1LioT0T2EK5BXz88537nvdy55aEdTk5T19RhveXbFCm9p8w+jYKKb+l
FznwCl2IN/qpUHpRsNkj9TreqVQvmX3dIIeZRlBhc/BXeV4o++Ewbe0kRUkzV3yC5ugqV+a6SIa4
GLRTwhBnzJJKE/PzywADxgyDbFL6LwjE/lGGLryzEefVYNE5tShcOzYyxWuYx3UY3Napm9LtU5iL
4mQ4lcxxbIobqbwFjeDDao9yfofqMsVYaUnjSf0AwzsiNpYPu9EVcw3TC404Frd/qMl5lQvxyKGi
H+UWgMxKgNhpXUuZiBJopmCsm/H8vtE64l4yVAxjgFCZ5u94pf8GVCFdU0qRnTyLd6lmkV0fHXhr
gDXvKv02BjQwQdgdEASXRapYWFwNWS6NJzzO6Dpd0fJDS/PZuvjp8arv816twVSxArxe2c50MpcE
gGHgBvDHmyGRLgPT6mPqC3pnztcA43/90ndbMqof29lRqTTOGNIXA2GzaRqc4HoyAS66qvvQoU0S
GxoKacz+w6v2dxjXAg4i75ZP63ilTDclvJ03ACXY320Hb07QD+bECfDfmKxvXH8zhf4hCuoNVAUv
95XKtfpQ4h97DcSo5JFLsWPYTyOhT+2y9mohDcMjg+LhSpwuoyTys7ZxGKC+MX27uNSeb6n2xn6k
8AGBSitm3L1d7JQvT/4YFiuiElgNt/4AbT4LihUyhSLG18HjlUFajHv4dKB2tzxJbGF6htBKag4l
zRpKG1mVNpicIygI/IJk12G3sLP9LMwSNg38kdfbZataoIPKydbVYJ3QmYc7JI2Fv8tZ0IThVoaK
5IZx0h9/L8C8CFjxfOi4/kL3O/oTg9SdwBa2I+ztMVdBErwxlDmWYURhGFz9iZXkHbvJHOkt32hg
sIPYg0CArgFiR0vv9XKxH/uWhPbDMJFwisi+oIATn+4go3g5iZSNPO0t/A/CMPcSmwfyMHDa+NkQ
cxyQuRaTRohTdKqXPVgkYKjv9e1iXK6+JP/tSWul4STPWaH+J6HX3lbxJunFheNqNqM9lIRva/Ja
TYCyVGZxSbKmDyFsxZipfHUaaRviFOJeF+VRGg1tuYBmQFjt213HatM6QPsaw8mlI4Oc3zLLrPVv
SDHc+uzPsnnR6uCI6F9X6zZ5/gGrixPBJEkDKKFoqDN/YVY4Bas/OsdB12UDxQHNKrrP335wQ8G4
rWO2w1fjGL4FbJIxQDTQLajp4pLace3AeZWW92ho5RDBiJFjn26l8hKLnGXSBvWFWOUyFUGw+FVp
zzuO01NipuuyyHi1/J5OJvGBWzRmvuFkLG6tj4mqWehnIo6S/S+JHYIlP6oFnbC/F2b+ccIZ4585
yxXHTViVT+YDtGGG2zBzUdFHlo0+egeLTqrk/3OdgcyIYcucJxGwbGj94U6JxIx7ZaP/5kL4PKuC
5GmMAawJHpk3Jmq566N25PPL5MPL4IvSW514bW1eWOZluMgco5Y3jLp6IB3inYT/hbFPpZ33qEYQ
AuMEIWX1L02r+1xMCit6tx0LxIilnRuZMwfI2jAbBnBZGv+yfR/5v1BMXBu8+cZ9IAeWLgWcGLuU
/FkWvzEWhANumV5T/doHjUIPl6lfjzeV1as8d2NfA/ppjLTbOlTshBvcH5BIfQlpzFJNB9MCXc4f
y2shyF+y/9tqlYRjPkw0YiCNBEEE39ySZYSkCFmKlOtAxAqI9QtABDK8XL1V8k/HdKSLzi/DV2UV
ZmjIJRfsrz7UBiPLOjVVYDn4+fQXWtsPf1FiymcnoE/sYxkQCJL4MVtmFaZapMfY8H/3txUMuUnV
6IVwVOTum6Ngu2ll64mBBDYfjhy82UMiV2OyAz+o7PIAK0lx1/LdlqscOab8K+tEl3HQwbr1+bed
MpGDjgEVdWmrcngm8fsmSj8dcXZpxhthpVLKrHpn2YsVbUOCzYmjutarc5vQuoGzL8MYF2e6oJwB
S1n7qGdpVCh5xgXQplqWi6F/2epehK192qG4TIrfv6YkNwnOeNcXTlVeeElPQjD3CU+C+QAHvwhz
S+WHmY9FO+Y8HaBzRHrMf/hJl4WHYifK4p2zhm6jFGIiu76c2PjNb2JuAxr8uKThJHyMqT0JHAU3
sfEC2ftl6zYsOvntYy6Uqjv5HamV0MeS+ENzvtB2mFfYN2oIN/msor0Lhz+EUqvoWZpAWLbTV1Ke
zHoj+cAjYU3ifRrkmA44dxxFjCVS33Jdv7dY8kk+KK21+5vA12XZ8WW4oFDuBAa9KbBt9Ex8wusd
o0cIXLMGXFG5uhUUNCrj4NlklCEII083pX+X3hsRlYjG+gfuPupSeMKj2y18fcacB3Pd+HA/0flz
7ro0JnLxcbJpWHcbd8z4Vl/e8AtVqbAwyQ0nix6NVgdU+Mfp7sxjUJ3mC7D6jlKTslINekqVHXtQ
7KvG0jIW9uTGkgQ+TTLQCNrJ6Mj9rVRL3BUF7qNLftnu4c+OCU23nIzlretX91BwNKBwyk2eaQTT
yqHN1lNvdmR6wTQiU+HtDRw2ZgAsrTx3ziiS+Tjhg8zqQQ9yO2rFEzIvS8xwrV0TceJvXUtURC42
XjQRu0ygbebvL4gudhOr4XOwI6uhqsPG/TUrCSFOqz83II/7FIG5fLWCtDID/JK/mneEXbL0A3sY
w3yMVfjcktNA9oUHVkofMPLjDlT9e+JIVWI34++Ebv/vQ5IyH3ldvLZr/yR2viFmPC2gx7zMwSWB
FIIE2YG5AEEcj3BpdO2GpKt7VYBUy3ZkMCBVvqEecmnEkO1UCmvfl1kaKmTtv+RxNQJGfX6xN7LP
dIzPlN0e7Fu2J/CNy10zpj+U6x2LxK6hslNzehnBYWKkKzF4MLm+FFajoccglHHQOm7YAdfsqmwv
13SVXIN+LKbHfh1hd6sBNwbxSPJmxza++QsFPww/msCNRAhE9QZvLsYFWC82fBQECxODWKUmDMDk
4+IzR+7wD/YNJ0i4a/212+VZ6IjcmfS23rs0PbkxD2ZRDYec2nfSknMEQHL5eOatalC2CiYdmLwS
JMIvM8l/lJRU/oeW15DekpO8SkU6sT6H0Oeyu382YTdSZfvn9SsArLFe4wZRiYYLB052NmKDeRgm
fpYvysZEC6nQ3YfqhYW+ul1bm/M3TnoKy00VWcn1WVfAMKs5vVv3lB4gBQIGa8M3jMA9TkffhJ4Z
e78MuSHXlUwcaF0C3S/bYlpvj89q5CIBFz+ZeLfSsHq757YqASiehzSJQrXgWHcvORsH/pchlS80
RfHREStnOA8tchmXDhW3Soal8BZedX948tD3WnhwtPsgGiNODtcmS2VQEwmiHMMh+twxXZNVfBCR
HWYs75GUYEAwhHqxo4tuifhb+PHkHoH8GPJ2yDEDqfPfOBJfi1JjEXNpEBpwzp806iYi9cG+LhHu
hUqhwsgav0b4TipS2ObZDK0/Jxkmp3WFzK/uq3hzxW1Ywd4GXYsYLNoQ5PQn2m99ftXNq/KJnNLN
WZ9A9nipbziZ6+R7Zy5HydjL/dnAqKMBFYazca10OHG1IZMpPsHUG25+S6oBGfx3J91n8yf6pg4U
XsHv7/R6Ld3cWg5grwPrvIbZaACuEAwqXI5dGBuFi9JkhvM1YYoqxrPyhMh3J9Ra13zTN0P3LGiG
3iKjbon0/eFCjSN31pTMYGi4gFyN4vz8JfaUriivqYaNStQJl0RrNuuM8auBNzaTRiIlIdT9HajA
bSpub5TFdqGROBFcYi4q1Fi54JWC5PWuFGfqhtBeuLXiFXhrSgsNXgTqa2WLA9/3oPjW2ZijRaEB
bIZ6D+crIrng0DV2bJiN9i+PHhGadI80Z56gwQt+61b5trP+bkpNHbwl6xvrret1ZhEC7pC1HaER
h3mzy4e1P08VGVjPqeTbZauitx1gnr2+WEFG9O3YeqC+2EdQEJdYSS9+We2xjFBzgylQDdKptCQ2
PAgtnB/LT9vUSbqw4kbDokp5RlQE15qOIs/DxnMe398tbvAFbNFlUtU8ii8otwJyI/tus9CtrXf4
uDvHbgugI+rRMnzjrXwi9wHb8UxLnfX+knnJwUCFpXOEbUmJfLsvaG/2U08Q2StRjqZr2FoQ0ZFB
gSKIhtPXKlEgVtO5jvgztAYwr5M/XTKWJoDZRfTKLOntCOc15rGiVy+964gm6Fgwmf/LRb1Mn3cT
lmx+gcsVlliUUeg7CjEWeYA8mejWlB6B5k6C9J5p19B+Vao2QkZSvZAuDKdmr2KK28K7lcabLTFE
URwYofBoOG6MFxg0FIaDUbI5JQPr0DvxHe7nTdQcJr8Q9I4Yxg+xccfhC/MOroPV9kka13ALNqQs
Lt2Qcv9qSXGNfBrPl/2rL6DVU2q5Bly5rY+7Qzj8ZC8yAlkP3W1K/CKtFoQCfnib+4MaQgIXHsve
x4OahxNblEpX//V7xn/0bzPbnQjY5Nw2H2WFojZT/ZIiBnly/PAEaurJA4wps7L6BBEgjz5TiiPa
LXzvti84ooMNxNDZlB2LOKCcicZDLfd0p12Bkmsy4AUTnch5O+wN8W9cZsvvF2ltHDmDakQmqjLL
Ga0FY87TvbEi05sMzdvqMSyZtSAQRLI1cQWap1SGszvmCp+P78t+jcYVZ5uPVyW4mcKrRAdMuBWI
/FNu/eXzBSFq6q2pTaAIGioegcT/hNvLUev+IVp/7gnHRCwJaEAFJgcHBbzsXPm1htQXo+UDCWK6
NeOy+JYuYoXzblfkVHO/q23vKz2AOLTrMr3u0yqMxOeurdCG9n9XFoRossXhVF60dU4pEyeU8U99
eqn4O87F1k3M0QOCjfY3/1YYCzAcziCO3DGFdi42ufkPgYH3V+0X8oUkEk1tV7t7aiLapq949b3J
ynuZHZR9Cy1oQ0lJhIoBsy088A9P28oJSTGsM17DRjiL4TE6TQ4Woh7C4bkcogfdFsqCqpGCIYZO
tTia/iMsDcDGucYqkgpfttLv8TzmusCKeJT/5ZTe6VZuST9fUlB1IUT8X72jJ518Bk48Sj0yiF8C
a4rS3hk4oVMaUT3Xr8DEkz8rcI0Yqi1LkXy9aKiGFByoqBpJjadOEJsF0YL1r95X/oxcN02FmTM5
57P+Xmq1XO8k9RsjH4Cw/NvOkzur7qP5NoYZW46hv9xDh1ExW3lvM0K6+DaOKOy1NdvbzkN1kPD6
932dNFpYAPtUf6b/PbLGM7BO5fjtVm1txA9n/GG4LuMuzPep8EQY9O17QG2PcJmv09Q9hUOm73ik
E2rhSM/HOT2MFI2MUSJObCJOA9UIEGoYugEkeB3FeORc91QLapRoAqMVsEilQiKWmT0MFZvZHkyF
Uc4diGfJT07NKwuwzNaLk72mpndIEe52qKAF012yQ17KkKooreSEo3JVgPequrtOG+QXjv6Vq/2r
hL4KYN4s5Uslgqp0ptM68Rc9FlF6so6hQyuVbcmSMKHSN90XD6rZkqWCTvsJR+qsXyzCewF3j3Fc
R2ahFLsXVKnKFZExjJhSUH+b0UJyHSx2Myvj6LdSAIQzlYuXl+eMVvLVGpF2IP1CNONc23tOvfLk
deM5wa5O3ga5I+VW4zT3sCL6qYWLXNOORtZa+bZITOoUgSY10x2p6rS68EoBSOwksYcx0F/yWq7x
s9cYNhDb3+RvJqB3jFGJleHQF1XU1zYJGJktktBQd8Uh+qmMM3XzcCSzQJjks7a0cGgWU0Dg4zxu
f2tnT1TEnogGEGpo/h57L1yGdR60GXUVK/rrUkblBeis3D6IZckTaWIl6w19FZdD6C75T+3YYgp7
7r4GERNU5iNIbHi1cf9Cki1Csna1w5/2ic1wpRzwvW0AVxtpDyGqg4qUu/Pq8bS1/zxoDQ25rhNN
rp0CF5UIKwvSUyQhvMcKS4XWyDEMhnoV0csknsUdmvGvp9G1/iz4wmy5GbMJbGfhyMm/fBevFw+y
2QumnDLkpqJ/PN1SDMmdEjFOkd52S0KqV/Gv9nadHo589a2zpFheqf5lApQELdyzpsDrj1Vfdb0a
kKMbuSWmhOM3Q0qTTYSQ/02SaYCMiQdfscp5lcjyunBCQeXdAm07MmneqTdWvKTRjtmGNhtfPuei
c65RZho/EDc/9Gk3C5MPBVnPyE5pTdwuHOm69v7qZ7ZjPN0Y598eh9srQlZ6a1VmE3J9P8j6mBCp
pOc7riZTkecSl1fvmPi7UCek5qjyeCom9Q37BSLsarsAOdD8XAYLRd/BfBVmaTp8B8a2/T5HugPo
y5M45DZHvILLOhQ8NkCDtc/G5YU7advoPcro66K60gnbl/ysmLRan8sJJMqGNz06yuemFe0hOPEc
oMoqPTR/FABokt00i/rmcY3RidJiSlr/Z4orTs65cjP/17yU0p3W6kG+Gy7ctJNxr8iHBK+JTXod
BzQ9ewBmkTP3fBKqlmjYMEb320WwEDN+5yUL90M3ReZ/+VfDhU5GRH6YogyNQM8V7ElVE8zyqjvn
eW4i8IDMkYuE59tBs85xIJ8wArGz38lJGPik5p4WuwKowkTsiC0JZR0tbFWlAjXTZN6dE2q6QtwW
Zefv3VPnokw5Ix6//Q492PPqtwF3eI/FPTULiXc17dym/lkh3Wyuf932fX75JX3VmPEeZTIilo99
6yMWuNEjYB9S0pt0GraUFgB6FrxFJoKBNJVoYIge4E0Qr9DPSxlxa2Sov7NvB0T4o1ohqeN+aMai
Dsbfb5mr+mDO7LCR20wwF/I8F2K0bMuPAgSSZ5otcDyMximPayyw7vefX0qpFIJwcov36HTOdoXu
uSTPKQ3HhfFTi73Nc8KuOr22OJQN7Sk9RUNgKVupGQ/ZDdz7ePGCrKqALZMX4fQAaxQ2xNS6G9B7
IbPCV4mXmJ7tRVO9FPZm0dtb7eYav9t3bMcAuL05GS0/f/ZTYv+L57GZZXewiehPFwN+138vVeGn
evL3XytYdjW/ZhzAwu2EJNdlDoDmKFVyl6V90cZ/IFloXSTo9rbsMGdRX3mFUUCZBp6m48ShI0Ck
Tvs1JJ7WXrTaYsltzmJ1IooGQQDq8ctxBY6saGZ8VE0I9pVLO2hcaHwPJqBvoH4Ry/rx4cXua5dn
xgWIA7gx+aeQR466d7+GzAy6ULQlwdD0kiK1VYcuZhR3iVGggW0nbfKywX8iBInfg0ALmwsVfIRZ
qI5swIMlCPbPSExmS8adkLggoXb/0+9MizGivBWkz4rLT5W+ZkRLIxWvNdBL8W4IkBvlPQ6E2Ia5
9yPpMTdzGS44/L76WflVRB/w9aJqs5cOa/l6ey0SzsNOi24lut4DJZP/LOjL4ZjliNOPqF4WjVk9
PTURF3Y+oBbz4+LaT0HqwvYBrMPPmj7yz6nN2lq+PGsmIxtIcDsUUV3PrJ5jgv5NUWIdJ4S5fNPv
/oYoJv26Y3ogT+T84BleyIraQQVNvS3/BjtuWV2L8RmUGgTWx9idPREoLuvjGwPh63MEi7XaO8EY
fvAUQSdy+zeVG7f9E1TYqHBURqL6549InSgclxOJ4zRnY6IguSbo+P6z7njLGRdsaCXONzhGGkJV
ow/78r60RLJnf7WvrUoEDtkxXJu8CnNHbb+vZVYU3FXcY3LYM1I4NaA0uDweze2NQYlebYxfTDJc
6lwgNC5EqX9GVtWcdsvR1/PCswK20HVaYdHwJP6R6gNVkRBlkE8uv7yPWKqDseP0a6IfIRX85tM8
wy2Jmtm7Rz4wg/MZ7KNwc2gjxFIMJSggPiJwiuX1ov9fHpzqLePw+7DwDRPkTWeUsd9JD7BvNNBr
QXlOWG9ercwekslSqRGZqfhpiUNjkoKTUarDu6j8geh6dUXOGp6UL2KxX2WId2r4PGKRjdlbfoZf
5IT3P46lUNaN5/+j4UIPnIeBXhN04vdZ1YjqMs/88gsK7vh1kpFTlN9tT6Fbdxx3AvZWVY0LaCwg
aS3WBwhHYOZx7wFUgrnwCito2wKHjDdxoOaUdSjvLf5Xl+hUSlHrzNxHLP+cq3dCHMbXfP0uXeUl
BGGz1ep7mhXG2IVjIavSsVgdX0zPRCOkhJV98CUYtaEMj+eNi7rN+QF3Yoi7wn7zwnh4kUrjqQe0
b9GXCIk+GrpfsOjFnOcHwJ58G0zEogZ1xjUCZcW+qE92In2VeStTTv2Xfnk6ZPGo1fTZWy/SjAC9
IAUFI03Dyc40LPa0NF7OnBc/9u6eE/38Aynkwf+D0jzJ0BFqdB1/9cOZMAygXKzdYEY9TJIs6RC9
usP3CjqaPDG8NQ+xpj0W4LVenlsnLHX2yc3PaIC4iF7GcSwzey5lD/go3s+z9V/Dkf470s9YVIG4
7BU8WyA6qnkMiImFp2H54hNz2s5S3zDCcU4eNjJ9v8BNOu+1uKfM5XUY4v+Wuqp3P0L0VF3jvTcW
KlhxFsFR5SLBspRGS/utmhaoq2Fh0lbGmUzo5PCRkPrp8zCrvt1oTM+k0ZHgYCgCq2+5UKymxFin
M1O4SqSx24QA998yU2psNBK1HFFPPdfrMdUQJiVFWIBgR+1BM0purBInCYuzEirCx9FkKk/Q2S+1
P+l76MFY3LSsXvPd6nB+amm3J2ju3SjVtfvsW+Dt94z04DTvSXFqyDk8kQhmFhU5T7R64hhn0iPj
T7u00VFjtBX9hcfyZRK7OgzxpScuINQitb0yNThPVwgAyqsYoMlpXchcRqE9aukTKY344JTqzfmo
DzYbJD7GAPZ18+wZjEU2gLr/hUNog7Zgtk1fJ921hLUK3e6qe6zMssDwUNU0kdyJ3T8ZIeT6pNam
LWDYfi+NsikY3fuhQkgJ++Dd7JQyGDJ5Jg5oLsDX6RDgyPpouZDBteukiYxxtrtylrm8aEapcPlu
6LeDf1dVP2Afib0M6RA7uLkHTcfhR6xLkDlGdAvn4vb8NY5dNjbTayYFI/FEgCebvBI68t4UrpmM
MYTwqkr/h+4fDZjYg6tcVdmt/J1RbmvfolWf6n2AabHaIcjqlIIu0gs5l45EPN5s5aWT3qciFt3M
U2JFFpmrSI3zjxdjA571lLWXRm1gM1Wz/K6aY9uCvSmRTgp9RWflcB33CCq3548luJUS8pxmD3BH
N2XtOmovMIHUcudPvulbhm9kmkYzEu00qSp+OEkjs3gNvjCTZ5m75Unfw2atwaWo+0kABz3JXbZv
L70KYL0B+hf2MSMVRx+Lc6XudMOZsVQ77Kb3q7SrFi3rzvdSUhE2SDcun/AH+cgb+qBA6qeWnZnN
ayjc0LBLwUmi7xjHt6Bm+0UoqhvgpecCV2nNBXHcYvFZNReQPZ4UWwYE7+4TsRmlyer179jUH4Kl
Ii/pDiCBaoJWULis1XxNODtcUed0lXiPxrlzxPbmzntqvpNob8kgpkiE8ekMLYL8uYy7YaBcpqqI
BFkN7DJUrTJ7pBqUH5vleq0zQVkPjHj3+kVdVoQDGFv7fp0D1SEJmlrszZzyncK/5+rlH4CpvSgE
ja+e4xPLklBRYRNaC+jO2tA4Xf2kRnjgrs5Aqp8XVFCC5mBRm/Viaj6qQA+bd0fQtAiqGyg+IChU
bR39uv1Mh83dJAoMB/zfCkRMiQthYomooXHQGOPQL+01S4aguqSNSgOoGkfol4Zo+924YVUpoTLc
Tf1Lw4SOhD/6h089dlSFGrU52MZ77qUJNUYi+Y3ehXh87btIqoiQpgtpZqqd8CdMIK3zLkvfhlaH
1qKlZkYR/pHXiaWwqeupBmXZjbYtq6yPCQKAnButFUNHFjrdUe9koUBJS5IyA6iSNXJn8G+tlHk9
7Rn1ELq73cCS/CeIK97GRlOIjLNA+gL3UN0FhKsn3rx7S9w+f7p8zXvDNyW+ZzV6wSLdrcsou+sX
7ByfJBUFEAhEA7Wx6b0qHdfd6pzdXXZmtSde4OH9Lb2n1TA79y3eAqQgn+q714mb/mQLqCO7xUwY
v1jvejt0i89sPZ+5WAM2IalzicnSPVb2f7xnjj0YtBYn7XnU9lQdIInS1VIBuTvRGCpX8bO2pXss
Fb3ucWBWMRPiz8h4IeqMTj0kbAAEb7lO8Nq2yuZCL7zptcVS+k9xdaTb3V0pc9GHf9Sdm+PuE4cT
ax1aIKCOpce38VtIqoNnjx5MxN9kkqsNaN0c/USRgtJIK6eG250lsqEY634vKw2g7BEjGzd+nV21
/UCvAb91G83vAf2KkOvd/VwkpWnlGLaeu2muV2iu/PXiLuai3UkiY8SphOK6jlaOvTzUAhTn+h6f
HS/AZSA+C6YoVVyQbTa3UyhP9zEiEUGTwntHvvOrDR6n6y9pIbu1qrENKuznmYlmqeWoWuHdJYPM
CzyCLOcgHDmFD2QbnQSctLYWnN0t7DCpl/kvP4UsS7/OIynPwCKpuqpfln/tpLz3NixEWCdbO8qu
zj+6uBM7SOSKesg4ykb52Y+OA8TVR6MLfUkCM9xIJb/RY1TSjAt1Ab4XFaUMKGNs5c+b87E3Sw9v
X0qA3XEYzxmI0n95PxdR39geXF9EaUF9SE9JVc5TVSU8rUXae3p2ITuHP3mB5e1GTuKDcjQmq5Zp
KF5kLbQAETNxUkUOuum+IkFaCjgh40HxswCtI0ddaS/INQ0NSqhHjc2AXT+cTMqbDVR6ptH6xp+F
0Ui4NqkVaXiEL2MxdBdWSYc/lfpXeusjWNS0j8FM8EgHWE+xCIZmJBWMJ9NUiT+c9BRs9jz/G2V1
6w6kbSdBCWbP6cvb/F2lRCOUaWARoajgdkxxN3HUBwJxW6kPZAqnSElt14aZN2Q5tCJaDvLmgGhm
o65aPvIWwtiqxWyCnrx7IXXsaq9tc4huE7Fs4ZW0BRapVRsCfP4lvMi2HqfPYOGWai0UIJ1+a6hG
wXDYHj3Kr7zBGNpcGX32gMYE17/6tANZoqnFPzeT1uRQuusB3jdRAsV8Gz8XvpEDfrcaD/0yL4QL
F6nb7arIcS6XelqNm5zOqmcscpuzDn1Il6dH7au9i/P9lhi/EmErW+s7Cka4B+UUi90a5qR5G0Q3
NI+8bRpqo7AjGpMw4L9R/RKKACNXEMYWdlb6TVoLpCjioVLIm4C+9c81aqg20XyzC59+kBc32Z2Z
0F4kJecDghmRtzOxkG5xpCRvCnnvttR7ErWKaF//fs64qqZhHPOqaOF5Ha3WodfiwtJIKAN69Pd8
XVNjmWia/EFXXTcHfTO+lXgLkW0tJiy/6tx5Uk1t/M/SBfX2MLd6mHZxg3MqgSTjh2opv2B9wQ0H
QyXPP9wPk3Jx93qqXiV79EEKmDE8bYTdKpN5EYVdu0iexMRc/WpvciMKprqFdyb4iO99Pzopv691
cjGYF2l0pfTr3QofgMIewSoJlq7RnXurYNX0O98y2fS1DvDErhp4jM7s4B+Ru8Vorpwbd0pJQBZb
Hc1+F62M0Jeeya1Gfb4dJZD/ZVTF8p3OTLn8EBBXx1MSrNBofVKlVJ45y1DCrR+AiuRzVWhOfpau
1L/KGKAzr5oRl8JgXn4SxxDgekekZOO40gqWGFaJp0Qt9w89DJ3FSSxYwfBG/ILK0PaDC8RzGU3j
hOeMGmW+Zs2XC5LhTiJaZBYCAPrMMPx17qBg7QOpEQtBryMEUu91SInPRjcSEdHoL41NQrVOg25f
k76hhn2kYW8vFNh3ePafoPjKVxJ1M690g0/pFhsJX8BnW7ToEpGbM2/Geu4exdkPvxwcJnQ29E/H
c0xB/HB1v+JUA/ZyGqrHkvYv2YfCg6g517FoYlTXRILo3Lx8QeDa2OCxi/4ZUwYhj7pTtk/NNVW5
/NzBiRoapsn62IDGYWHuCE0AZGwTCp4BQztECTxMMTH8ltwegD7JHpFTwAd3sFh3Y1yF3WuzZpFh
x+SgS6GhWWactdqHSxCTFLNqthdXvwgW0TRcPWDaGUF0Q0iWT7WPHB76ZaKo6Urbx7QqXG3VhQJH
k2iN667G48bEv6Qhr0PfnUgcmUT1eDDCfvOxgr63tNK1IelKvv7yKomAcxLc0C0kAespgYH9cX2N
xUDxk/2xKLK2zCxKM6S35o9RHyfaPVjclFf79J7puTtX1SLJcVcqkg90HwzG+ceclcGo9ZBtbxUb
4zEYQHzlSSM4wcSOnJprSTxGzIvcBQ5+eW51PIFc9BRzTYQQV6YmrlmLpzKv8xKaTpHzTz8qU/5p
RaDpYhb+2aqXNZmxYuk5P/wm+cZp/fRdjY+q+8YwCD+6Z5VgJygvpnCHdxJMXoHjsAi4pZDnDEN3
TYDtMq9e5zhk4wp0mhtViItaZ0q1Cxc3g0YzsKo8xFhC/16Bkz0VkWVsaDWXIKruOtVsLPZ/Y+kQ
0cTd7NajmiPGaIKIIiLD4EIjgCXH+zotiWmfVu8HfXgSB+vK5iafVECKQy7abdWCFWG+GPGIPwlG
Tmg9WZQiBErn7544Dvf3QISp/GtllhsR3WTeVLOO0qx2K3pDgH8l63u5aZVt4YsJb1DeUz7Tv6px
mxcdxPF5whQnbhr9ux3ImpekOhgAvGgeFNxKB8r3WQAx5ALujelJLJh5NGxH1Vir6OvelLHLYfn1
39ugEYy4t8/dE6IvugjYRumh3PpOxl98SJR4hW8E+FZjCeKZRwxPCmCqpZPbrDIfKfhtLe0TwGrJ
f6hF+llKgJqawvGQlfYTj7z2w1LacVa2SM5EFUXotvlIjpy6oNpy8jxE+Wy3Sujfm+a8EhqM1m8v
/vt7pvsmT/A5wKcN78oYJONtN5xgwqOJciVECzUoqPEAh+uiyo4+2ROeFISkNzxgvw3EMWPfyZ4W
sC8h5VMBSkYelXW0x2xurxLvDNeDxAtWBOd2T6WbeNOikVeZOzcVVi31sBj3zJZeimQH88oq5DiG
2U1AEdu/P+NiBRcHqiPDFs53ODm1Uz0o8pnKpZ1zOIAb5YRu4wBCBAY6vePRilBGOPxpZbsUReiK
ESyUFiwiudgZj7DU27KUAigH+3JBlNJELlum/KoGSxYAoSV3uv/SjjKG4Fqld20+ZTscudY+KGBZ
Vd2HXfk6QCbZ3wkp3CT2ymJs+a5D2xWEn39YHEa+woNSUt4XUfZXvVigSSn1IzuwEdWOaZ7BK4F+
dCgC84pB0x+1EWDYLWdyuZfepEX+armijXOHYOECjTTZmpSQE/7epXYJu1P0folR7XmwpZLN3KZd
dh6j/7n7bbj8OKcCq8dDSqtQoe37Zs8N/i2VukxkWAX9c0t+apAhaQVdS1q3XktOn0unF5uOFJr6
+rGY3131V+ZfqfSsJnqdT5aRPRmb8FwWVv4zHlAyk5GcskH2lIAIMrB8WuoXdbCig1JqmYNDhPbV
N3oh+U5YJY4a9Ar1SVUdc7fDibHYRdAHeUryo9ERq1BBJF7/REQoPioT4bjwNNfLzNOA2iqgVKm6
Z1Y8rv8QeRYIWZKKUEaqn3L7SEuqjeLRDjPJe5ktCsZzsAp6blQWODTj+IM1KmBhkzUbbCI/ouNl
RImtpf0FdwJxX6k54V9yNh9w7b6zd1dPpsTXS47daHbZtn9bslZmqxlqBOhPwowAzu0cNTHlcTrd
gVDx6vBqh6R++uDdAqLhXRcuwPtaiMRo3/Hq5goYVQltSnP9Q1IXJpPLDJl8XkMdoInsV5KpWpDL
taFj+euc/sFBaoteMN+qSV6pM2MbibZEKgY3W2ZS35NWHLLgJZALLmjU+8N8XEBGIKWWvQNVRD5o
lDA7CCh1KqhIIvySlURidUhLHaL7blpBcQmOhFy5Ahtd6+sAUyjX/JeAfISMY+G319AVTVJICMkb
64j4iJrFul0a3t4TRwKM7yiJPkxb6uWOIJnLNY0tW0rzXU5aK3qp/kOfRZ+HskIFT1p1Is7sQxRo
1h29yT0HaIqOuB40gGOtzcR4A5yk7FgR4TigsT7rkXWnJJ+Tk6ufMsYHTeVqf4R3Jl3Nec0eODCD
vEjE4Bnr0Xq5IVXo5eyAc4GsnT08XgrPEDC89aLDBiASQ9/RR5WjmcDL+8V3PIDJcQ/Pbie5GYlB
8H95BYBKVbPUziYS7CK/TgUTdRsXVbbgVw0Uw937Qkxt934uyHgVT3L3gqrzqQLEjva7MjIyZSkw
iyj16wJ5G0eA0uRXAYxHRJSpnxC4khsj6DPNXQ/kIoWDWCI6jatj3Jd+3z4CigwnNZF3xUAA+i/Z
4hBRJEfh3LK3sFR+sRWSr0byfpfOGu+zpF3KPrgDbGTMniiQp8otym4OcCW/gCmGEgKD9urUH4gZ
0f7ACHpRfDYNgh3jpkkV/PCl6zdVKIkVm/3DJlsOQntSuwaP/1bh7auVB5hPYMIESYdNf5B+vcpO
eOeAtzYbKmEqr02R31hpezZnGbcIgfj4rxNLUvLm7RAWMxlwPHRK1nH0t+xZRofOm/DantwREH0z
1Pm9izlFHsgYrQ1jNy4Ym/1FajaRJkKwYh73TVEoSzAR5mjRVH4lqBKCL6/Winmisu01YmQGAeJ5
T6fRaJiKVZkWjIvDm2zlbXG5PsnuzGLXP13vkf1SmVCRcwKHXn+LDqIauIuksQ/H5ykKo6VO26v9
s/LvnhBN469FvQAkMNoSS8AOD6K+RynB/h24dWzZKmqjib6tid6KnIOpOSgctySBgzDe5nKNz5cs
TMs8vrrR8O2n5fg4PaNWTiGLPQxdLkgWYzkaGl8F5BPnkuUefATI09KZwUg9Fj6TBVOTu7loGuwv
IF/hTqVDuNzFBCO0TKwpJvCLp6/BP3qw7fmWLAzPteDYh4wWzIr13Vbi1Z36Uh3OhsZqXsjqj1np
QgveeYvcsPDqk5FNWxtjdDR77AtOEmc4KECMxrtQcB+3ZfQg4cza47fBzEFJdsgTN1U5QF7D1SfA
YjDc5Vp5ZXUIrIgQs6O8voYn+Ps+erVUrwZUDL8IgCj16SrkAillQR9cy1tWU/+A4bc9L50KJPBP
JPrX0kb99pvULelY62HEIYoUt/Cn23tziN7BMx0BOoMROI2OlskrzuYlQ9BQbylGhsu73e+0L413
Ob3Cgq0EK+B3KecjU2JO3b5sQEGzW4GDIGvktSzjasR9xNOaaHEGgmXrwN3muLhMBoIO1JHs+9Q4
zNRYRKWeKAdNlBHS55jjCstliW32ExKc6HshKdHkfPoDCzLuWuW6ZmMFE6z+bh0l6JmMdaI/WaeH
KQi6HLgPDhIoSvIyOPBaq5ldwUgkoGHJJACseJIbDYS5/1GRDnlXD6qzPlO608usGApMzzh+189Q
oGgn/Zrd9Jdg5rYsra1XBIn9AfD16+d/7aMbx8kVPmrjV1Rg3rz2itITndIZraO5XqqxW0IEn0u1
zx2hrFPVz86tu4VDP96IsK+iLxKLu6kJDMX/teJIhVJfsWm0NVSja4Rfj4TaGFp/MEuFWMlNfwT2
Q91CuOg76QprJRxrKpQShy37iB4XQxSpsLRwdcVB+bZ/LywQ4/hOZN/t0jGDIgfqHWx+gzaEd2y7
rkP08X9YRlh/+Duzpsdgj1trRNIY63E0sLFnW6JzU+Yt4Tip4b9Az2fReZBVFLM1bTshvYuP2cGm
i4FjL3TSa5YoSikUpr+EgJKcg8aBUHBz302SGHPOvcw2fm/TL1DCFKyh/R9epsxDJNwdPwTbP0Kq
JRjO+o3q+vBhuP+k16lGmWp+GrlCxoFyJSlulEw34GIQ4bYXM3c5AHknmQpnMWSuWnV0Uj5KBfYy
EkKSgsjc/Ti9c9mtWyKgTTNIUdUjIavhwj3ApMp2U7bh1Iz8oKNsc9vS9zxI+42tAWT6nk5ABcAU
TuIuTyW9oCsLXduMkJwQLcl97pQJ2vyNq9g8bYTDyukFLMiYet1fp3MRz6dYZ/mZm+T1Z58FOSdo
26gqhPbGV3qFSkI74AFKl5NOZr3mA6XrThP1VYU/ShNQRNoWiuoTwYYmJYedFDTE65RLOPVT5O9I
PPBH6VvEsjF3veBHZihnl4Z73KOFqpxOWY2DDkE+5hBAojJTiokvKCEQxXJmKmBK4ciM3RDNG54m
ITUtZA4JJyCPGXaLvskKEBiDg/1gXN0xLh9EI1hs4BldbVTHbn3yZeSWvP/tsFNxS36q88MUXLZh
JVg33mMx8Rlp7F/jElM7ldmhd4UaDcBubsiB2WmqA0EHcXhGDR1oaxqWgLiKIxPD1eib6E0k/AXo
kt4HvdwYV/xqucX51CpTgzrgI+gu7hoqvKn5ANdCIEI4SQzsljrqkfKvDYvWp/XpFn8AYQ90kTel
OQZj14cVTlJnkFYJOTEi0sf9hQYMjtXnpMcTSehPBVhVCQrqO4b8AwOzIH2v3AqVmAQszGyXmRX7
KM+4iIH/PWmOe72E+5tmEypTP19GI3XU0ZDiyta0aSuNKRZa+YILvSlQmcIvjJzrtBTuoB8DK+IO
JbJQxj+iLzny3mpN1EnjJMKAuAJylu2X6r6c56drSUTNbtHFfKMkohdjoTAqzniAv31dtrHfJEEF
4YQl63i+drotBLCyrs3GTmCvgdAusAyhKOdwEZYsY0vNDxJZ6nVuW+tYtZ2gV4UEvPO0lvbp9qMg
iGIQG47P5peZy7I507V7G7AiKfIHW1vwP8JmDAq6cbCfX6vCN9B/7LwFhdEMOvPRqgzR1W/k6iFT
LcqTorvcBPD7insT4IJWlSPXrT513/UtF7KT7JtBlrfCR9g0+ZDo+uaPzBc+IR5q0gfceyobRwmk
c9b7WY4OEmkRcKl5EQCLY36ikTRhQiC291UxVtVLk5GOCxCOWd1FMT+1ZUKnHJ7XSNfe+YcAbm7t
zSlebVOUktdpsF8Vgx16LhVpXXtFxLw/+Ul92bGG25nEoahaOOIie5sm721Ul93OUdJeoc3FfEwu
4CLFZJ45v11Tg6QrAZPT7wDxi/hwjsSbrW3Vwyy0ZOerbvLhJEVThTnoZ6wLqD/aO8AQOlPnXnpd
D1Zuo4m/BzGDDcQx3bs2b1R/KT73BhUK2/BSLNbqLKnmwKP4lR+zoqGhSXonPK+8Ya86MkhJ1t40
PiEpEIgwa3eRlnlmNa/+X2bxub5265e7meGCTHZbhO40B2c/9oNeJfJozW+6KfWCvzg+cYHp8N4Q
wppcNB0LZdh38dXuXXTtBv16EZ/ZXfG/8LbWpSaiI9/cedpn6dMKAzJvpB+MWnXqkhTHFN+gI4ev
UynU2uqSU9sdUtpAk1w9433kR88SCWw5nimYYWlSlGGSXSD3fUX0Jkjel0LpV+2EWxc+Q+aY+ppA
yJQErKD00hHY8LYVKOa4DHB9Ugsb2ti/ZLGHbJ15+Dx0YKpf3eHsEhRjlKKEZT3WhN3ZqvB0R+Iy
k+6Ev8Hl8jNBx3Un9XDBU96EShI4kM5/2YSljkx0UWKN/JGA2MbHdGnfelaY2tvyhaocw55VZf3A
TsR++h00zxqsXrXyC0vV5SNPJkhNBHFkTyWhJZs/HMMIoPVxlPQcV+cCTy9ak0Ez7GXFZecJu3Uz
tmbwOPQcExOF20OmJl5+tDfbM2DThbkkYUUyUfzjLW5WuR5wI3jU5dMLjlOckqwjnPD9TQRG9Evq
iboNJySxHaXXmFfOrGGDeOW1dFNnqQtfjRYIfewAW+NS/hoWhJMHd7ssL6JggY9dn8+uPMyE4WyY
UFX8n4jn65oRmNBpMkoFPdpXY4mn0wyL8S8hGlJS6GvJTKU8hzygVHp2PUPn5EpzEz0EfDTpdNhm
d1J1X8+JThDe+kLZlTEv64UE9+JlQUNmj6yq0ScpW+YPUwcs6MM5PbfpfpbqA4hLoHDrT0ENlLiP
1E9936k9sfKgcUci+vH+OWf/XAkNjFcbbl/371sC5VitcW9TCeq7SapY7bWNb5ATY1Y3iFkQiLZY
GYIdr4ufCjqgDBQ0YSgY4rHF+/CLr70/HYGOYHMdea45+nwQoG+Lm+VQaMFk8fWg2pGC4kdN233f
8C5NnzbgCkvK1WAVivflUTU3Y6tQFeMQnXo3C7r9CNW5jtvXubI2QjG95xzRtQzvORnk3YC9t5Gp
EgR0FmBZ96gMDJCGuVt3EZIWaHfFUiBR7sgZfY6AGNsKxnn7U/79FcfB4CXJ6m4nPExgH7HjGQVp
eZoY8oSX5U8F77tEvixoglwqSUAy8YpqoN8Bh0Gm/uQ1tJJjy//wMMHuEjifG+e/EJyS6EZgRj1z
yjvXZrv8Tl79V+lt/o8morI0gqtQUJ1ftAddlJ35bUgj7EP0iZ98Aup36GtDcx9Ie68QQ1egFDk0
Y5FZ65mRvLdRJ1pKk6G1fXzBpaA9k48ZuNW+LzZV3h763JuJ+RJ7Tcawsar7Wc1wCUeFx7I6DkS/
xCVMlZ5K+Kv722IL2qwCvxNLaU5aTy263GukPybEvbuWedy6cF0YPqXRiBs733818Tuox8EGSQT7
1W9vx+IB0AQDmiQ2B89HJB67KOPa7rxtYZ6Rg5eBapAiCTqsf50hMQyPrnCJVMwsLEm+ItBTW4dw
j9B+iVMTW4Cobs8QHs5KLgWvFddFxw+WDdCDbjKV8bv5DZaEyGC7uEHlR2mWS0cEVLyZbkV8jOK4
BQe0xCpSn8alSkW7EKNscX7hdLNn/oUUleN8DOg9Ib/VoEHdk/OvGo++J/mNmD6YYzrhSwQvCLRV
LqdbWkeIQDgcHe0Ivur9kky1h2RqJci1Fqikv+3/xCAdrSgHXgx3q7mAKtHbXxzGH9a7WV8u/QYI
hfwxS7wwp5cSxJrUc+UONL11922Z1pdxKDz7ezh8Jhy63RR2If1EFLOO1YrizK7/0el8OQDMZMhe
GqBOUTgwmutawgdSoKXmLzM4/3GluMztUz50b/ukJDbs9lZPf44HufwYeZSu2QolYlhpStKD9Xsp
iZKKaglJmwqLr52jYDERCXtpH694T6KRNdZ5NPLWMJZUdJMZlnuzA9ENqZp4uW3GS/XFVfB3cG3U
CD6H3pmtLeUJMiGUOwbKti/pOytvXnvMTTyppue/3mOh4x8b3z0+/UpfoiXH0MCVdgShYxyKqT6f
CqGraS4JwlhkmjTt4WPPe1mNdQzsXFANPQPdUKTOBwN3TNTmjVMccC3F7MTQCd5I4w+teHwOOx3N
+5+GZuyVurU7RtJKimblWyGV+AlZwHybKy2gVvADvkv5S3jzkqvT6/cHL387rSM2mob4b4z7KX39
jsb8rBhGR1pUeUh1HZ8b/eLDyVWIHeg2z1dbQKgre+DIZTJ3NRD+HWU8KREWIXJdMNsHd8saECVQ
/HjxuRFVpo71eEg6qOZKaLp1ePo4crXrYM1AaNlyROdptOpvA2uSP6qqrEMawvonJD6gRhNLDlWU
TF57tScGuo2LdIHgKC0A8THwoJs5y4ElwN/fsVtbJOSXzZ+z3uuLeexPNYyR+6m1SbyQgYyFqfP3
NlbYwlM9HRG9WoIeLIC9UuHccZi+960bnhuImz1Y3SwtWPhOykePRt9iHSRcZuTYxn7wVSeBVmtU
EOrLY97xX7o29+1YSO4jeyk8eBqwhDZJcehdImIHlhMsMGBCRqzJkRgrCgv9YxjiY2sTySnQWzJf
PEWGyCJvqqJ4JYvF9hoYYbB5A0Acs1PZocqNBDG6r3xaoTbNWIk12D4qgL8hCEPVWXa7AB1Gz5zD
ocg3wj4yDblBLDFwH4edHZjydb7zWGzc8nPpVqpOZYZ5dwEswCtL1s9R/8AVudH6IJq/Cs0jaiEg
XPl5TiFM6EBvtxNlvk/RErIijba781vEhpsvLFEaQIZscOkTxlZpEtPOfblYL7qrk/XfJ+BAXZ4u
EA4wnoq2rc6ANoPXZyxa3bYpWEojVnEwDy6wWHcEZEmxyIW7ZPTumMoDun1aWUAvtTllTA3P7sFv
VvNi0QbY8wv9PXLZqjS3BTNENzfza78zPTGlNdwAMxIrzTCYnhTUVjAUKjSWz6yDn2oXzEqfr+nQ
mHZ5GC7xv1scBkD6alBMc0aW1N3A331DRHIEeR8VT7Cfoeugiq5c3Ianq9wUVNcE+tWvwdTvx4oe
gbeylq5WBx9yFsDiGD2zexk1viqq8BWa3vbbVzorB6WYy5vbgt61z1UM9wa1gCKW0WKXp/MoEIBe
VtNmp1aZcyIUWy1ZUy3frt3emy1OnN2Mj3+q9AXC/0HryS79qyxNe+lXJA1zu66DnHDfvFh1ckRC
e34e30m83Z8Y1eW2ql4Z/StkdKdwYEkjyreOVr7gLuufh8yH/8kYmts2SplSkL0gLau7HT8xSqub
FIXX4UrsdHAeSBbd2ZyuUA1fRX+cqV8TVFY7aO9b3/l3pjc9TqprD0Gp6lJhACntrQlDEpQ88Sdi
20peUI8TViv3suLd3MTwqQbOZIKEJXFWtwtjISaQ7nq5W5ERmqxvxgcqCprZkVYU3zv+itwB4ulQ
3SsLXLyTFqe5tboe2A7zJFGv49RP5qVMJrihLBzkEDLSAMi2cGE/aV/EM6yT8D8ORolWQUT/SdVg
Xyg9jRy/jWhL8AuTztEQ2/kAnfW2noIfcciAtq+QEMIynOtKFtGmKiaPO7PB4XMxfa7SOVWp6eny
czRqxiYT2xrswYWmFXWSchxNCOXpWwZSmNJ40PGFr/YS/PufcucMy4w+UkGhqX1/l9B8XpB4Obia
/m0IYymBt4qrfKy7G3DZS/YMgh4MUdt0t6uE21VBQjtvqZ1kVTPgspFtd2o6XliZ3mlM3U/yDpjc
gxaJ9BE7i0yLaGBd0uCpm5z8Sotw/uc9B5CLC8h1e75XBHmPUKsQ4SpXtXPQnJ7CsT1Q4ycCU3dO
ajt3D3TX3Juf4uccXGMs1oDvOyyL+5lVbvZ7gED3TqTeSEdil047S2w14Pnkar2NEfDdxxrobna4
SlIiRRmQqixWpicj48S2St/TLaDyvUTK6IH+MUbP5NqIJZ86cJcZiOP5SRO1ZOXirwz2UlJS1Hmz
Hq+wtLfNkU104rYLbmc4t6bRqVLRNtEtH/UYLPtVG8TovlU8pqsDm+YVdtGUnLean3XkHkLTbT5A
XM3yKJLW/kj3lEHVaCqyEUiIffnu0R7Mju/V9v5CQge/pom41G3NcfxxU0BlM9nfeTPwG762kwTi
nx8rL5cFWLmbX5N8Edx+oq5xMVHVKx3r4re4xObdkAt5y1ONo143PdtHuO7h+1CN4fdpMiFGeFro
9pvP23ft/rL/vZL4/PfQnXNIeUIcnfKR+5s9pidvrPBQaV8QyMa0dSm6aKySQDbQ9+K1tJrijDSm
bDLFYgg7kltO/rxaF4fEt5TbCiVgSQWtdDWHo98oJMKNOmBQvcCZUvxl05UXOb6AupwIeQ2werlN
2XzdWNwLhDVdN3rcmAUa4NPX5yuKVgJM/igcfU310oiTFIyhYT8ONknCmqCFIYUjrOC4pfbCtI1b
moFhv674SM920DZUh9xg5Al2mr6KrPVvxVwtAU+ovRYM9XOTzziL4bWTR+suTQZnvWY/66jUtSQK
Tc+RlSZ5E+Bf2F69fYwoIaq07OPTWwP6RYAjFKs4/2Ap4o/B/qzzTKwdaWhgQxr2b1NN13BiP0AB
u7qp0ZEae9Neh8VPkk9v882oHCB/lU+KThfQQLy2gQJMy4yZ2viQYdx1UjDnjbVUB+30Km//nQhr
azePWU3eeoTqbjqdKFD8fLBMefNN3mY4G2iqyW2CIo1ZZa31pMGvJSvQ0Z1szye5ZM2NJ6ASGbBP
PSZO19Yn3QHsgbde+u41wEro2TcY7n4pXFvXzrhph8EF1K8S6Kv0YTPDIIXAI8Z/E98AO7uypgRa
zPe03pXwZQXhUToD967ZaX/mys1ai4rqAPWn9PPOHqrPh6LoDrlVdBTF6wGaW4NTPzYQQPvyY9wY
0qV1jptlezirUkjmNcTQG90Kkl9zpvd7QcIdPluOC46zlY1IFho+a+uoSwQbPfArNMOpQR72endn
2IHS5Hwi+qDfUjCgHNZX0pexvz24Cwrm2B7IKk3YDXUwzQK1+1BxdOVJz7z2RtmHEjCaHd4g+l04
MxCgeUb0aQU65PwbS/sonq9Ne0U0QAGf/oyb/mM6vgDnDpxZVIWRvs2fbv3CjnQcdtu186GAFXTa
E1yWmfUN76hhkzabTf34gkoYBFIBZGiuY3ZdmGf9Ho6bi7xI/hJtleTAQtx18lRzv8g2rbu2nk7z
3LvKox1WNmoGMa4XyilkeWsrsHTItT+uYqzGPWYuSFv11My+hQE319R7c8bvESIJDWDZe4CE3jr2
GFmdBBcdxJ3Ue/y8wDXgf60U7UymedvfjjlysH0U8f77ueIsfhu5mh9hMj464mqAILvCnTUDrIxE
Uvo9nm4C7MA3EnZsTU3ASnlrcei+GfTDYFSAyG2QZQb1IbWqXSgSPHF5BnFS0NXHWexYOfhkEqVg
snZN+N9IOTw6HeJZHpWklpqPflnGyJ4tCCvJybOVZIBWnWUK+TwfyUZKfKUGB6m3wbDRYSGZNLXn
lGdxxF4Ct0YN+mOc+HoE92VyMJZ064BcHLRsH6eyn5DclCIE9mPblIKX7uC/82POlA7C9+k7okv8
eE7xyPm7AynMKuQKSgz5rrXdPOR2Od36gF1hFqC/wIz25nsO1fSwkyHYZOaBHaWffv9/d2H4SeAO
O6zDkUellKmr/VPT0Sx0oIsgn9qJA/sxkgy7t3nSJaImHva0AjNNLqk/o9MFtT7x42LGLdwM3gmP
YxsyzkCXjCDzFJtm3tJnIVKplbVzvpOqJX3SU0Y5CciKXhW3jyTZHcjCFKas3Ohp50JTwBOmgUNK
g9zuJ8p9cbF6knjA+zZcdcHJVt1GzFQ7YUZTjH+WZX9b2kINBLTOrq4et7odFauSWLeKDn34GkW1
Mby2756do35CFal/laUDZLHGTBTOo4EsS8ruRUb3sE+80lJ9eJnxTJ2j8aUDOQXcn7HPJMIen/Ct
BOgrIZ2UCioGTeBLXljPJro9XxtYu+zNHo5poSiA8Q/7DxzOB4voV4skEUClB7f/K0Lgl7XIo/V1
nX4gRuO0omrO7jac5CyfDYftVT8mscjNx1o/4q3NJsz7R7Bn6J++9Y2cdgJPFC45XgB4uwDMq+TC
zjOMg6/UcE5Jrg1YrXhAmGcLXiPyf5U6tkspWq23s8pCMAbhPmJKvyRuehGM7HI9Kx4A+c5r8Sli
GD4o/9R0yK9XOm/hjOmxAIxIIfDQTuo+LnHBUInmKqW+5jvr6XDt2rSeSX4Ctiug/WhD3FvV9wx+
ywqDaj3/emJzx6lqroPinjZxJYs0ueKrGKzeL0EdrVngjqdZwE1k4ISc+ViIdwkMs9N1OlJstScl
FfUkkpt4AZxs7sI2in9Aj5nc5L9IG6NxiLSGEH+/Ng5P6DxiDHaLYhIAsu12mLg3Xz0VaIMx5rKT
FrVbLFeEKOKuORDS2Wi78ozOsVC6ZMcoVzwvBQtAyWknxd3Rc0+f6HR4Km16SIphs1jhEHoDAa3Z
9lGVr77O36xlrEmnHDZPsNU/nhTY6xSDUuQqZ0eP5vGMnB8Z/YKAsU4n6+r/ki7f4OBqrYtIyCS/
tZlpfSbGBEyMItDiG7ZPUT2MnnGm2GGvkGj4qak6fmRysffM9qn6su+UBq9q9Erpd9XF0msj2oXh
g9sTJc73fAb0VOrzLw3qau2sONEYwZJSOK0Ua+peAIsY0W3qvMDtJS1GuJURJgTztEjCtSMn3day
qeRPr03NQY3S/pfedGnAOoLIDmSC+mGnxOO7Yz+X8TkXRt7k1XcsGa2uQ4wRZEvN/MTijWMIEhpi
yElkmhgOdMexPlCdBDZuCI8UQ4zodVVkhZhnw0VwotGpwpZsX5CaQF4Oxe0KI/HYTEDO9xd1yYUP
QclfmR2S1J/0EU+C/Y2X2KpsR2//EknHkJ4jtGbV2KvaFd15VhmjrcsXoCS/GXYv01SWjdM/aBx3
R+ds3pVsNlziX0XlYu6R8Q+sAhseZjSHHN5wE5EzbC4+YvS4VDYb9GQSH/aJZg74FpQbHWZ/Mf9v
Ny0C85nfxizkrCUh3uBNHx9MwaDfVXPIJdrTYxg75ogtNNYSfXqB9gXjz1E1yAJxqMM9Bn4SoML1
FpGv5pb0lNUZyak5fpbyRvfZ3DwIwIycep/+Mdt9FcShLcETE0TuT5VxGaro8hkL5i/Y7zguNeRG
o5aaw1mYFHSIQiGhXOOBeWy7HzfwsH/AxUlC6WejGWMNehEyVK3ac9sYac0PO63AsZf7XWK3WoVE
0Dpvc9f0GUZTMg3cedKecEoeTnWr7kBy9w/agRDg8fwSwf2ebqb8wHJM6HWyhYYbCGfjjQBzcAoy
FvAy4QiQt0I5QUzOhEBgWhKJnVZx4dKa8KKyVtFzxggDIVJPPsXMpF1gMnDnaVmxz0fdAq0xPFpJ
Z4HLZfuYmeQfyt+ei5HL0Er4+ZnNCjYEXoS5T3gMtVV+kiMR74z4PNE3AQe8D4eIQt3BtAyiTJdq
i92bhMkGnZKPHdsxrKqv4Wlyekgtbii7UbA5aDZXeXpuoz5aUG4h0dG/lCXbLc36je9cfGktXXF0
5qi+SFehOXQWrWxlSuM+vSGVpWEyzk85mUndMLG+NOhPYW9d6lo9x0/JM9GOKNETtCiGRf9YJ0jk
X4zbmHU/jIjZYFoXj304ypDc2ErNPj9JezkFO745IJxVHTYDEEEgZ0cbFT78qpK3SaZZEVPrb2vg
DHKe/5D5eD4A4VE9fGIz/35jXQZ0mFow1HHItqY5hHgwjBnfo29BYeykcgbZBeAUWqAhNX+E8t+r
QA9Fxb7WuedWGc0ARagdSzAozDZ6HNxFejjbaYXwOWuS4H30qqY42Zccyc9nmqrCOTLucYBPyAXN
E2ENCP3Wdv3aGFleNodkVaKOqW3b
`protect end_protected
| bsd-2-clause | ae7eef5da9f51a8a675e6fa79c4c0ffe | 0.949099 | 1.82104 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_afifo_autord.vhd | 1 | 15,525 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_5.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| mit | 9affb9e5d704a38333f20c280e05c61a | 0.475556 | 4.203899 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/l2cache/river_l2dummy.vhd | 1 | 7,632 | --!
--! Copyright 2020 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! See "Wasserfall" implementation with the real L2-cache
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_river.all;
entity RiverL2Dummy is
generic (
async_reset : boolean := false
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
-- CPUs Workgroup
i_l1o : in axi4_l1_out_vector;
o_l1i : out axi4_l1_in_vector;
-- System bus
i_l2i : in axi4_l2_in_type;
o_l2o : out axi4_l2_out_type;
i_flush_valid : std_logic
);
end;
architecture arch_RiverL2Dummy of RiverL2Dummy is
type state_type is (
Idle,
state_ar,
state_r,
l1_r_resp,
state_aw,
state_w,
state_b,
l1_w_resp
);
type registers_type is record
state : state_type;
srcid : integer range 0 to CFG_SLOT_L1_TOTAL-1;
req_addr : std_logic_vector(CFG_SYSBUS_ADDR_BITS-1 downto 0);
req_size : std_logic_vector(2 downto 0);
req_prot : std_logic_vector(2 downto 0);
req_lock : std_logic;
req_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
req_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
req_wdata : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
req_wstrb : std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);
rdata : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
resp : std_logic_vector(1 downto 0);
end record;
constant R_RESET : registers_type := (
Idle,
0,
(others => '0'), -- req_addr
"000", -- req_size
"000", -- req_prot
'0', -- req_lock
(others => '0'), -- req_id
(others => '0'), -- req_user
(others => '0'), -- req_wdata
(others => '0'), -- req_wstrb
(others => '0'), -- req_rdata
AXI_RESP_OKAY -- resp
);
signal rin, r : registers_type;
begin
comb : process(i_nrst, i_l1o, i_l2i, i_flush_valid, r)
variable v : registers_type;
variable vlxi : axi4_l1_in_vector;
variable vl2o : axi4_l2_out_type;
variable vb_src_aw : std_logic_vector(CFG_SLOT_L1_TOTAL-1 downto 0);
variable vb_src_ar : std_logic_vector(CFG_SLOT_L1_TOTAL-1 downto 0);
variable srcid : integer range 0 to CFG_SLOT_L1_TOTAL-1;
variable selected : std_logic;
begin
v := r;
for i in 0 to CFG_SLOT_L1_TOTAL-1 loop
vlxi(i) := axi4_l1_in_none;
vb_src_aw(i) := i_l1o(i).aw_valid;
vb_src_ar(i) := i_l1o(i).ar_valid;
end loop;
vl2o := axi4_l2_out_none;
-- select source (aw has higher priority):
srcid := 0;
selected := '0';
if or_reduce(vb_src_aw) = '0' then
for i in 0 to CFG_SLOT_L1_TOTAL-1 loop
if (selected = '0') and (vb_src_ar(i) = '1') then
srcid := i;
selected := '1';
end if;
end loop;
else
for i in 0 to CFG_SLOT_L1_TOTAL-1 loop
if (selected = '0') and (vb_src_aw(i) = '1') then
srcid := i;
selected := '1';
end if;
end loop;
end if;
case (r.state) is
when Idle =>
if or_reduce(vb_src_aw) = '1' then
v.state := state_aw;
vlxi(srcid).aw_ready := '1';
vlxi(srcid).w_ready := '1'; -- AXI-Lite-interface
v.srcid := srcid;
v.req_addr := i_l1o(srcid).aw_bits.addr;
v.req_size := i_l1o(srcid).aw_bits.size;
v.req_lock := i_l1o(srcid).aw_bits.lock;
v.req_prot := i_l1o(srcid).aw_bits.prot;
v.req_id := i_l1o(srcid).aw_id;
v.req_user := i_l1o(srcid).aw_user;
-- AXI-Lite-interface
v.req_wdata := i_l1o(srcid).w_data;
v.req_wstrb := i_l1o(srcid).w_strb;
elsif or_reduce(vb_src_ar) = '1' then
v.state := state_ar;
vlxi(srcid).ar_ready := '1';
v.srcid := srcid;
v.req_addr := i_l1o(srcid).ar_bits.addr;
v.req_size := i_l1o(srcid).ar_bits.size;
v.req_lock := i_l1o(srcid).ar_bits.lock;
v.req_prot := i_l1o(srcid).ar_bits.prot;
v.req_id := i_l1o(srcid).ar_id;
v.req_user := i_l1o(srcid).ar_user;
end if;
when state_ar =>
vl2o.ar_valid := '1';
vl2o.ar_bits.addr := r.req_addr;
vl2o.ar_bits.size := r.req_size;
vl2o.ar_bits.lock := r.req_lock;
vl2o.ar_bits.prot := r.req_prot;
vl2o.ar_id := r.req_id;
vl2o.ar_user := r.req_user;
if i_l2i.ar_ready = '1' then
v.state := state_r;
end if;
when state_r =>
vl2o.r_ready := '1';
if i_l2i.r_valid = '1' then
v.rdata := i_l2i.r_data;
v.resp := i_l2i.r_resp;
v.state := l1_r_resp;
end if;
when l1_r_resp =>
vlxi(r.srcid).r_valid := '1';
vlxi(r.srcid).r_last := '1';
vlxi(r.srcid).r_data := r.rdata;
vlxi(r.srcid).r_resp := "00" & r.resp;
vlxi(r.srcid).r_id := r.req_id;
vlxi(r.srcid).r_user := r.req_user;
if i_l1o(r.srcid).r_ready = '1' then
v.state := Idle;
end if;
when state_aw =>
vl2o.aw_valid := '1';
vl2o.aw_bits.addr := r.req_addr;
vl2o.aw_bits.size := r.req_size;
vl2o.aw_bits.lock := r.req_lock;
vl2o.aw_bits.prot := r.req_prot;
vl2o.aw_id := r.req_id;
vl2o.aw_user := r.req_user;
vl2o.w_valid := '1'; -- AXI-Lite request
vl2o.w_last := '1';
vl2o.w_data := r.req_wdata;
vl2o.w_strb := r.req_wstrb;
vl2o.w_user := r.req_user;
if i_l2i.aw_ready = '1' then
if i_l2i.w_ready = '1' then
v.state := state_b;
else
v.state := state_w;
end if;
end if;
when state_w =>
vl2o.w_valid := '1';
vl2o.w_last := '1';
vl2o.w_data := r.req_wdata;
vl2o.w_strb := r.req_wstrb;
vl2o.w_user := r.req_user;
if i_l2i.w_ready = '1' then
v.state := state_b;
end if;
when state_b =>
vl2o.b_ready := '1';
if i_l2i.b_valid = '1' then
v.resp := i_l2i.b_resp;
v.state := l1_w_resp;
end if;
when l1_w_resp =>
vlxi(r.srcid).b_valid := '1';
vlxi(r.srcid).b_resp := r.resp;
vlxi(r.srcid).b_id := r.req_id;
vlxi(r.srcid).b_user := r.req_user;
if i_l1o(r.srcid).b_ready = '1' then
v.state := Idle;
end if;
when others =>
end case;
rin <= v;
o_l1i <= vlxi;
o_l2o <= vl2o;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | c89b7783704f879357a9a3738351ce76 | 0.530529 | 2.818316 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/kc705/config_k7.vhd | 1 | 2,748 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := kintex7;
constant CFG_MEMTECH : integer := kintex7;
constant CFG_PADTECH : integer := kintex7;
constant CFG_JTAGTECH : integer := kintex7;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
-- CFG_TOPDIR & "examples/bootrom_tests/linuxbuild/bin/bootrom_tests.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
-- CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
CFG_TOPDIR & "examples/dhrystone21/makefiles/bin/dhrystone21.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20200207";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := true;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := false;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := false;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := false;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
| apache-2.0 | 6cb0a2b77f9878d13f20314c497f3c65 | 0.687773 | 3.881356 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/updn_cntr.vhd | 19 | 10,193 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
MpZqUX7RHqqBov6r9sp19cCgAmwWMQKz/kilwg6KfQHVNd7thNhiMjNr9jWB5lhCnXS2Dmq96KWe
V2+V1FG8hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
eHZEt9aF2k9bUkzJgCuA+q4yfEhMdqCEDNKyWFDaQseZ/ofqbFQAQc2uVVXTRkEXQs+GrviVm+j7
2wxr0JrS1Xw60RqMKKhLpfqRVe2BmFAKgU2BRL0PnA5WtTOSGCOmSJGfPa08juK1otVgwc2Gzis9
06D0/bVknfjjRpJI8Po=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
s0TU3tsqHiK9WgquIx4poaAXQ17I+2l5Vqn12DnbEwMyPpn0YeINJkDaKFxRf41aPK1Wkun6v9Z/
YYZDqYBgVO9Z0NMkbD4LC5C9cZSBdk4ezqdUWACnMS4IR+6qI0nvPM6pNZernzgmYtMGFsG0h7AO
2CLMNIzANr+bYhHkAqpdx/KPtV7Deh8xOAkQeNSD+8rjhU0z6Gg+2FjdPjkTgWwsP8xrTSENuxiw
xPh+QM3dvd2tDQbC1sSMu3CzeLQh9mMzJ/R1uFQDv4VC1TFFFPI7VMPMlrl3y0ondyZNERO3SeHy
Mn6aVbKjlR68QJuFwdsz80LSh3ZTJ+foTk16ug==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
uIfIqnJL93Nk48nDUNvQ46MGSw+0jZe8QEp6D5vC3ytHCm6yvGspxOPTR0O/6R1kGtbYGX5AVD6b
KvoAJRDP7Wr2E6PTOWfFxWtEHCKiApDz7UksHM1gqF0d7SCMfsYR0KKn9LnLJiQxmEJD5y64ve5y
9s0qEeMi9k4HxMVPc9k=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XH+fS8ngHwfDFxF50DT7MdOHeXbY/uKmg7Eva1j7eQ+2X+a34Rn17d34wKLf1Z56AIT4ksXzo17E
WT5KT9rKAQNao71yUm+YQAunOwqKEPRyxOz3bb+3Zvx3y9p+F7xTeZFLan3KtqwByX5rGkNJtGjN
oI8H+T5FEpTIirQ9oxghooMSVVhKX8RsayssyrgajR3SSX0Q0ggoCOy3XtjsFKfrcDNlt7iEsMAt
+8vV+volJUxGGSYbt9ATDx7fk+pYKVnFR1jV5fEpxyqiZQoGjkjsnbN29jqgiZBfhyEe2uAb7sF2
RnfrEGY96pFoR0k3gse3XEc9radVftI75N7ROg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5808)
`protect data_block
wSnbWrCNlW89Hl8c5qLI8x5XsG8/CghupqMtsGERdMSXa3EK5J/Qit0WHm+njR821JFwXT565GTk
PfQmbPHqNCS0UKLtcdc3PZz0/PLyHx2I+i3o31d/LEWCSvVej8q9Im/IsuTfRijqwwpHV38mRUJu
zFppdNstRebIZC07b2wx4/Zw/EX4cSUu0lNqeHBvLS2bm6IdBe4MgzTchruIq08TrolYM2Pec74I
8AurMryqYhC6o/Ybr8S5oyAQKm3bDPQMozGLd2GswnXOpVxdQR7+Hcyfq/5aTzsLwGcNe2JCa9i8
0p/PpVMLrZWBL9KT3BXC7LiYyvbQaSj7GlTH5LlBKPsT/zboxVe8l8P0bRe4dyxRXzeeXPmsxiOF
0/97i6LbZCS1yzEDwEIGqWsQfBYSuYjMhqx8QLIPe7l4MS6pMtVm1wAwbZnR8MvKCKwrridhlL0a
sYEM4o5StHOo/sLWgJlTvYzV4wBL1kYSyuAWv5J2XUHvmseGIdNHnQk/EHV2Q8USm6z0OKXDAyPU
Sh9aHmD9LCdkDiyrAJGrai5dRFUJ3Ddo8PUjEdkVX5acXglzprK5M9di71HwWMt5aZ0Wi/SF68sY
UXFKCBlotPMyX1Rn9f+qiGldR2tYWjyGjaeTqzgFYeTDOxuNZ9gO/D+s8NmGVG7VaSGpNswKgdiP
NbcOO8Nq2ovne7Rfr6W5Gcc6ZaQI3aXrPm5aRP+LkyT5kSCO1bNOJ4X/klsW3zGGL8Vj3wS0zdci
2dUa6AaFKd12zun70jAFPzUE5cTTAbFsMtClV9Pq9x/yrZt1elEvkGg9M4qPjj/U3+L0VPjb3Mh4
jcxEwGjb4ogTCeX0kg2z+xYoihuXrU3c07HF8yg2tM4y6HagSoYplt/3TuLuBovINEnhdIW7+Wo7
wwEIEDtWtG468YEvpPnMVZL8DQPbEFRaN7ggyg3ajrUmGdEtPcRMeD9jTiRqin2dbsO0Awpz2Rw2
fX2w6bcZuUP3r1GAVYOP/fx8tPq58+IOCQkm0F65Rto25RJaO57YXZxa+tdHA9BBpp6EA37TfFhe
GGQoH92qkzX94C97QPn9a0uRzBIZzUXMXXZUhEbG1W309NbQetXemgpFw0Te23Dj2PSYua5lmUIm
3lYjodOPINOD7P8upsOuPgxvF0mVRPbv1EtF7G1dl7MYCqLDh+ES1/GE4C+Q3Glrcgn2xP4XJJjJ
VSXnkskBosP/n19w6EzI7LlEFn6VupIkTa2s91ujn8dFvwNjW3eu7SqSR7kPuoQT/uUctwSnLu0B
1r6df9edkDQmkEkI8rbERFx6Xy410GK4t6e1wnHkXzpSwqPwbb/h2F8z9sZH90KSbm2x4hPW4uaS
Cpfk2AdWjIYpUyB9uWvujYFhEYu2FhnpepEbo0UqnGmi7nY8Bcipe/uJWMfUd0tkMxmrDDMY/PgD
8/nodOpNOcJA1euM2HklIOvK74fGp5ZEip2nXGGNBVL/YnpS4W8+dyRYe/Ai0+0mVOHcBt+vqKBw
A6xOkZcouLNPHR/tA5z+ThOnUd0NvslK1FY7BB1Vgfu4AhPX79e6f9H7HRW/WWBDso6MpASN7NQn
ZqJcZkPN7WmHcKT+Be9B4glpqx5Bb+BqHR1RsFwCRRTzrj+8JppUwrLiiEyAhcksWOXkQSpd5DRL
Igyh4e8icsYXhfVEW+rPAcgvsiFGBrIrJ0vupk7WkN7kFwNH9kgNup7/Dvv+UgDQI9Bp3wNE8/vJ
Qw3rYD7p/QbTvtEPzrqm5oLEXRObv9Iars8jrsnwJQi9JCHfEvy/Zpq7fmkvAPq+ze9/1ajaSej+
j8xVFpMSiiYQ8C0nvWWcFqVe+3yzBm1j6R57EkF7SZlh7OLrqBEv9bygNvk7l025TgL9LIVDPtkX
AlMWZfEJ2bXrWqUkDD1+wTYjPXQUvoTrKab8t5wyWg8SVVQbRiCT5+MP8ShfKgaDvuV/40VELz+p
LihJQfbg2IdRC29XBGeVnlhwhSPpE3KXVCPl5ZjwgXc6cS7OVwBn50JIy0lErtdqdAopRtXyoANC
+nsV0+rFq3JCsEAXrsfTW2yoXrMnoABqY+V6Rv4C/wd4i1aoAMp+sgKgVMVpRA7QlBRLoCAjzrF/
jiPqfrpE9WM2yNPW/P1v73UQCOitYKQmeKE5D0VnfbB8yrlhKYElulMkI+0tfSdxJB5+tVTI8RTI
J46CsXxjPoYHQkhtZuYUWmWXcgH3D9kf8iFub7ZKZHgDz9BFBh7gyRXXyX5Zdo1uhhMjH8nBUDoQ
mEMbPjVIvmmCf33HGlROPfG+avNhyVz570/9XjJMOvOJPU3HlBtSQoE6zs33xFyJCOObvzcQCJG2
aZVtSEfPBbUVI3IWTMBpkMKU4gQEbBiNQdqnmfjLvOcIJ4pag2zIOoGa23QbGC5fk3DNCZlljHhu
l1EayU8CQCoFW5R49Dba7Ic5Wb5vxEwLpssaqCPKMKDyBL9dh4GZKsLpTYlHcaRYCRocL0LrTLjY
cxFBmOuv+2gCj6z8lXG5NY/0kNQcd/+LOsYvvMAP7tGvQYm3SNRPReBZIfbx1NseTxLuLb/da/KJ
N1ZyzGrugnyChiV2/k0XRoozzu3i9tZ8L+soqLnZv0dPV+b9HBCugg/yQ1m6f4910Twi1nEzBs/B
QbF3VWpcOGoUm5p9fcILVRe9gk2fVh7JyM8dBsVi1HwJMcnxoUuWCzLqXgRVU5pF4z5QxQOim6M/
/gPWCuhV+pvogyEUrpH14U+mycKeMMXGogT0hRppCovDZgDavSlp1nlPe2kl47Q3NB6fH9/+ekOJ
rNWIEJtw/77kqXnQYQGr2guqvZqnyUZ14+ONEmBPeZHm8jhW+UQHsRk61zLNaxrJSf0XPNuV58nK
fAiB2yUy0TpzQ+qcuwjBUEoIxDqhO+K9nnPJUhSOfxzk1OPTkZxMhr9KId88i8v9DzWJyNHvIaLN
KOzhFFRDn1LO49iqeZfabx0Fqu9jj+R1xG9jLMReOz/+EVcEopTnSen2SgOBR+yFMDHc4bcJl1bu
8StrXNQOHG9CcVaWTTyfM6VUdC+YhI+gq2IUykfnqv8BNOq9FcwGKI1rBrnZKIarvOt7Ox+4O4W7
6fLp4OC11RL4jemMTFekYNM3+bwko4NZOcE9Hgh/IgzS3D/vg9wOO5qoPm0WMTTyBU4tEbEK9TMR
0C6b76r4WraPe/w6cDZKU8et8pdhftc393/xONVo6yQp22BrW7W7shIFBU/ye+iXTiK3omLftWv2
UUaY4uZJ19Pj1KKi7m+C5BFEKaDafpbVmdgdtN/OG3BMY015mHf9DawcUE/4P4vh9mJTMsXl0a7G
owb/SKrLWo1SO6tiXczT6dlzLaberrflmdPWOzxRVT4g+kth93PhesenGDq4O7uf8e+tIRQ7opSb
TiwR9kCP9BekwiYg2fT72UFGozMOL8/HNhjWMBSl/jMQxP4edpH9rQz/vUA8GF/ixNDDrPrNoLes
yXC1prvqJIYsrfrdzaoCYild0p1R4CemRPopfqqwJRXxwwLDWFksfqKxLvvZz8JA0uz70LSSQmEi
YOtBnoHakvM9/yFjprI9oEAEKtOoK/0N0Hv6zNHyp/UbMX9O0JF6iDemf7RvyqWu0Y+pza5M4CGw
x01VtrxVlxmGc941ZsBmH0tD3AaSydL6wVhzhd2Ujo/KYpSRUgTfNMdxZLLwFZBidyKc5CHmlnmi
PIwqw7VvRfsGsqQwHSDNSciJ9/nApAViPFTxDTiPzfFRjX8VmB0gHdil5x/4jSpQ+l24n5C4l7S4
K0LWz7DeDZLjDBMXlU3O3ZR4KhkYMjdlw37mjVjOK6W+339Dgz2Ft4qzXqKUA/ZGY6wJeJMHJwcv
aIwSG3SzixxwbKT7ueRbtrLPsvdHmZIF9b8ZOxypm1BXKxuZ8ZO5z5zCb5RnhkWoouZMRYexuBCN
K8bVb0DXbBLVx42pjwg2d9Rstqv3KMLxkIVyaH1+pBMH9o0tXtEqEaZhlDd69RoFbrxeEJAB2Z3S
qSb9yO1/UCIOes0WnZjgdxBb8a+NyHIzrylK70oua43cGVTGmHToqQavumxBhXl6QAP+jGP0HyqJ
ZKLTg+eeGsNb4jVzG0ND/UVOQZVtIqGq+/BJqQbY7fnLi6vb4OZkTYkIpYmLDrN9i3T3Zv5wkIhb
bFesC6DtCFJEb8EYYun7JZ2+mblPfsNLQmcC/Ra8eOvjNxPoGJshRr+v6dS2UOgHaILWxRlA+7E/
pdsfzU/J6zLpCHyoZ5EbtqKkyOgI0H8ImG4VAfR+YHdkaGhz5pPzdInbIldNl8n9kTwjCvoytVhZ
auX5mrq5AYrRXY9aqIvHg0NPGYt5fG57KPBLGhu4QLzil54zV07mUQ6PaZ+TtU6vBJeUnyzfRw5p
gSPrnGub3hbkGy7oaFINsdoIM4vYhdp80TFNLKatx4RpkJ2p3JnA1+rAZbpMnbDkcdvZTvBfXuWV
EAUeFdop6EElXsHK2sBAY0I+jHxjhL8v+uydJ0Mtu/24RnYebsamFVu54ODcmWfaqS73dBFUyHCG
f7cccuQHZrQPzd5l6tZFcwImkB7EkS9DKsMfjAAm8Ly6IDDLdvRGP8MTyKz9ZYllt4RCtD7d51KE
LMZ8aBk2rTCWdIM3DGxYViDzx+MQO/beexzZni6QLoXaOcxO0ZtAm6jelK/Z+qJWy2ZHwXcjPXSq
UIfzCjDYNuvLLzdzZfOja+8xp9qqlSEgwZxJT5/oy8A3/DhqdmXDWJE37T4eZjwb4j8ZA/Z8/DZX
ruVB/k8qzPfFtH876p4hhQlqjaFqmWxQ/zBevroLloNqPXX8g5EoAI9FC0LiWrx/3bDu+Q53rUw3
p3HpQ3KgpZGDvkm1ilulVN54SEHyPH5pUsZ7kdfw0EiTKryaggETK8yvZD5564bQ3mYs1TzAt3FT
oF5JnnN/WUgqBSKnUAjM986kAdUn2ssD3wCfAWgRjog+wY1+wzirK14hFUKZ4YQSpMc8kQOvV6L/
xMSmpnUpImOke4fnILUTJ/q1smzXIaoUDvZATHHIqfODxvu9jjxxd0yS/e6N8kq+t9Aqs4QhvGNe
K3hO9U9r2pd+GmqMA22Ne023T+xq/5031gKYMbWkKSsIcU21m44ATTMES0/5o5AsnF0QC4EGIxcU
06pAUhhrbe2sCw1fetB/x6GoS6egWvLAoWcfnqdHFyIHkvtvxBX7LlkeILavAFQWkjksihKG1DOz
JX2fvTBRFPOThKHMgOMxC7XpMInLlcKv8queRGcTkuRRI84kOL14ho6OScq/8JsdFLSvxASR+aJ3
Rgmh8CrClSueKZJqXMvOeXAySGovmAPQuVRaEEvNrrWTsw3Y/YQX6HxhMYwuKLPtYd255vg6KUom
ztcIVOK5YFLO5qEZhys5Y/tXoXCkmMRV3A/5VKRbyWdf4OzVCzV5h6KCJs4dyBXcNC3AzXl3t2lQ
vAaoYx7ti0w5NyNphC4AXnZj2YUT0ZLOIq/xE9ex5ABHj2fnbSsnJ66jIhozsKbxLA7KimDYysLi
HaVCqoP8IdrV2WX15TabZPyZ93dXqp1EFgqDqvkYyyyTx1qyYHNWBZHBST7Epayt+nn8hecgtsu3
GpolOkp0Uyfn/dR/1D0piqKzuM55CNlQPg6YU1sqDpyLVoH+07EGLcd9DT6wYaQe3nIf1sWEiV8f
eB2GdF1SG8nsHtclUfWE3SDikn99uuQUpKx3Dmi434KtWCRBhhkixNpGY1mL8v3PkGq+aV61TYn9
eXzOyO6wB73aylUtgdxeQ9sA3o0oCCEdN897mfJtJJ7O+AuS4RUTVTm1Lr6CFsIBecq3Ygi6bqJS
eaXlsFpOO57BydJDP6HiY9gxAIJ48+iFPvpW3gq9FzMFHwvz7UWXwAFsLAtox4lkiWcHdXn9ocnX
0UsArnpTwehW6tQr4SU553YuML77wavoaN8iPIgRXu/tGnSFqEW3Hu1MXfd5Ml/AkJwslvD8qa2C
LaCXQe1fQ4mw5cnmKwRn3WLyfh1n2dV2zbKjVXEUlW0VIiaUvSmHNbST9FKA+HXoj8YquE35oGLj
GpybA7Vm4/GUxixUmH0M/6B+GL/kRnyeRVCyuXEcVMZFrdsOp9a/l5fjrSFLJ/9PhyHHhqXbzMGi
xw8bYZ+TI6VxADEEDfzv0sD+70+nYuTUpkssKWrYzNzVTNQdD6loVM0IhRgnNOta6bTVYGPRl6qc
nT4KQFc5BXT24DmdX8a0YDsRA8UFvE7kZdrQTUnunQZlzABfqrKbkRL7S2WxfwdBAEOpfGyfjELB
4prIzok8MJRwQlcJnnVvG74n9NumqAopPR/rhH0DaApJnJM0CEZJcL/afIedD73tqwvMM9R+jR8t
UDLHDo/zv0K2eZRMOdZmtEuxdtsOMFhPRFVrPF8evJ2PNxx84ki1iTW/SVREQuUzDSR5CAbHUUc6
jKVu49yXxRYutVPNdYu244j453GC+/Z+9LFOkpLscm/TfmdBlcuzkJDy3rx2LA8Wjr/xC/D39Wl/
KKWzzXR9xDI5/HCIsnmQt0/71u5JJWgeur5wDsXzjdLiG6J3br4buqwbPYalv2lkunPXFr6qMVh3
QKHq1ay9j6oOEFZ0JXlxX3jKSOT7mM3BGytgLixoWlEAW1kjf6KdWd0uLjgmIEEZRRRfThq6HO99
6u7Wl/Y3S4NY0kjt0ka8q7aKKYQkLHZ80WBuXcZx9P4wC+ky5I5+8dtI0ZfQcUAKKjF3r5knSpUd
RVEUukcQTxcM8xREbGueAEn3N3fSa7BYS4CQOCFVKBVvCM3FiM0CcrSW4ePSmLFKSXnwH6esZyze
rJkmSgZU4DnnGCNK9vqTKN91XHm6BaIxl9Z1vncL/DgQ+axeEr7ZomuScGoc7SHi3IIiY13F3t+G
C98cdDSj+iS5EijyKvQ/WbNOIewerOyp+X9/Ct5wEzoSUObAAhIORugc6eYEPiek/DBFI8y+o12z
SHBcmzOvEPPiiYw+X4HYPsVJcy9GRqhBD7/biDvp5pU1lzVElYcbjn75Ol09L7WitOiUfmPBoels
WEzGv3bGQz3mhPjVareZdlysMkTVDi6sZ5GyA1VL+JVHPjuPibO5Zws9YawrFEcfc0nW6Dxa49hu
UGTHNaGvPZJXKmVaqsPkeSua3jubEzs9EkyjfhubJIUnBO6MQP7d8TeSAP9kYrpLH9kghFm6HmXq
XRU92W/nvSJIQPxJOkeS1NUXuqRUtz0/CR6otZNIR84QA92zcn5ua50BX1ool2GfAaIzwyhTA3jz
dvAqMhZQh9FwPY/Q3LGz5kNtRLtJXAUzXRSxGtZKosqd/JzT2uxoFQTTmya/y4ykuztzTHBmpEZC
i6VRxUgZAhvKI6C9cO3BWtg9g8XE/6/V4ry1Xn6BXvWLJVO5pjtVxSEjVXkLvo4cWRqnmU4li2eM
EZPlt/fra9+Xp1dBkMlJIrOraGOtvVbH1tB4tzJX/f9kVamPStmvhxH65OZDIcaD2PSyWN5Js11F
2T3wr46PtaHnUOJkbLeqrsfmYsbEbArM0XxRSaMiX3B0//X9i5v/Q+dIfhuvY8k6xDegsHcVZz6x
GP5+c2vIMAZR9eGMA4wbxSValgbOJk1Fvn9XV+zVdlhZwA8LDODZAcY7UdUpg8YQQ9wjLQ7gjsW2
uUPcU9jQShaLx0qxwcpbbKS5w+NFWp3fJJQb2UbDm0s+9irVpX8ShsgfRExB72lT1H3G
`protect end_protected
| bsd-2-clause | 5ef806c5f663d3f1b54e767f8c73641b | 0.925047 | 1.893202 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/axi_reg_slice.vhd | 19 | 17,522 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jPOKnt2dHOagW4dFov86UptHPGMdrE6d2ZgqMnfJehhzqeTiVLl89did3kf45SSrRMnQy9YGjxY6
jqpfslmzag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
TbXlwhQ0d0UG8+CBDSNOnRgRBfh1oNNVi5QwoMGV3zJAlkTsnTywwNiy3IArHTxG6Niq+d59upyT
QOuldsHqtyc6KQBpxueCYJG7Fv1OIOGGq8mGjrkLmbJVhJEwBvPv4mlhsXKQ+/UhmQDpF2ZyKhkK
EbgpRIm7ap2EmEdPduA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iaTK7nKuH82rPJSrGYALVeHLyxEbb+9Rh0wJiyQuCqzY3/f+ne/dT7ytF39Hm0BXD9csWKwQp3QC
vOqzo1FyLi+w9Ik3lkb4njvMdZauHueYbVoku659dslyFGV84Aivwjcg0Y5de7FqsEonjWrVPTE4
0oo4m4QHuK8VN0pa+LmuzTIHDEzIPM6IMp8H0IstAk4VaGHg6wlCrG0u2kbbhcyaOKk2xzxiDfSu
gcUy11TT1zHFME/fHUU4VO3aHMSGacP3N+kgMah6x7bBUjBd2rfEXkVcl+/1g+qp0xW2BzItYrMY
Q1wtoE+N2GipiyxU+AmrXQ4zQNqO11zaj/N6Ig==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
QkbQ08NIPb90+bNjwXDlVNk6WbvhfydYhJZqryulAczmjZMBvdwitIPmanwzKj9BPStsPNHXyOKf
9PFA9l/uvQOwVNRTz3G2U0+6+YFy3j+qj97mRopffETTpncxm/BoroKpRNN1DrgSjygcTkfrt06N
1lOXW+551KWRUPA+fGE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LXGnS/C7HF/SjGcWlSWMUKmilNZr5UhJNWaaWr/ybus0u0ctzmNkXcydCyfmEQe8OngFPF/IKSaG
XMrlZODcxs6BdW6TBJGvkBlKfbvIYg7iCmAit8JvgZpuYsROJrZ/IapJ9XCUZT5PW0Y/S/PoGs0O
fXalNP4hoIYlP5OYjMaSowkFFmCMq49fHUdBBmi6thqlMFhrdpbAhfGoJVYkjStWry+O4YcFvpKw
Q8WXsOAh5J64eppUG0x86EZ8HpsK6EGAeT39tAy+jNSSIcnklat3mhXxMF+BE67OS/DRt5H346yK
YrLlKC5qbVgH7HjzWMBFYeVVtUec0iic45xLPw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
`protect data_block
5GACN4z2tO/gYo6MO1yovLXtkkEwYwPKOapvu689pkt1QtCUAKG04IRO2Eb7RImDWtK4KojPI/Ta
oAWrMZr5qA2YQJB7xT3BIfqrN3VqZGCWCl/OR4zCkvn1BVqVSEegr+WTt1/R3Jx1TbBi3abiznsD
Szx+o6Z2v2Rv4xg50T4lrlUXCNccTEXQ5BKfX8mLMjZ2JhQ14x7leJrObEBicrToPKHTXXFO1pGV
c02xmXVdpE3ExpnnZ8/pMhcUnP+nvo+VrbtOjVsrZzeftmlSqipjqScDCV6yNrGBwD55Ma1QTNK+
y58huzOWfuXae4m++Oz86nbEUVhHmcPUlKsrRxLz/ScJseKA8ARe+mYuCeJioYT2/oQNKgV4ZiVG
spa46nZSYbqrjPNDAcThx/crrPygIGf3NY7FRNkd+Gzkry7R7CcX12IJqVaiEQN3MyjDz1epVSUz
8q8O9iRugYEQfYKhYBq7wbTSH7zJrujQU3JVAXs0YezhPszCG64YQVd6qeTX2R5h6LntuZr8YS+g
qamWj6rQf8JanCWWsjEPzoPhCn3YE5lk0Z7fBZJM/v7z0GPMJCAqKTUfD0NT7QsLgZlJZp7bhpOQ
1k7nvaIYPWYHlu6TT8o2msW5MnxSm8AeSngct+ZGWKSz35wvbRmVZLKnan1AoAx6lylfDHuP97Rs
HykkT59jilSkDaX+xAtrfS6fSifDHk8pHaGXYDkJrzXhuGOGmkkSIsF5JU1KpsgBT7zuPPW9NXlP
4BiOy6QZ8cQdS5OZ1uE62dZnWeSHvXun5GTHF63g8UuuTBHkAZj4r46fEdLiRmAvnP2jsomjdTEc
FnbTrWXfZpsta096et58a1V8cDd3VQ4brGKBUuxg/AAxUUIEdbGdpoI5pjIx/xfL3Y4fBB4VI7St
hJdxzLN+UI+H6Ia8w66W1lEAIgpxe+ak6vBirKD7GjFxpoBFSH0qNi9F3tDyzpgqLRqPKC0Qid2m
dE0Jnp9PWVTORQqZgYZzCBaEfIfOX4s3rWvma+dDUnomuCh0kixCSmyUz75MIqSXAPt7cBO49jOU
4BOrsZuAq0O1DwP8LXdeeXSbo78qyJw3jgKKHZN7rzn8IEkLb/Xn6Ehh3paftkiaYmO96JRGJobk
1XPfhP8HP0ZDC6pfPYE2oDhufnt3EG1bHuuycjq3ZebzZOUZ3VLDFd2B029jDuKLSfYvIqlPTExe
JrekrEB4iogBt4A33fCw+W4Tmom8i++rsux71xTTpNUVOpmm/z31rVTSEhMMGXt2EHThwMviFppm
nh92jmJbeQ0B4ahrNlvXgQwN9QEp0RqUGL+vqKdZN/4SiWc3eNgMydqYyQ06LXhdmUSr8Wjpnekz
2lPZYH9YzW3+46EP98kKIM67HbS1IWiYuMnmCIzRE5VTUWEDe/iaZp6M107mpjudJv98i5D87ONW
w7MZfFm76/OKNs7ygj9ozfjTYNPrwbZwLffEAeJCAl8qWTK/yhWp9V1IWWI3dg8IyDesLE1EARjt
4PXZY6r55vKwyXnWihZkXGAemUAOdOu1uOR2LOayX5JpW+WUbNrqyOqKxrkxVfFMOMvD9O79Kwc6
2vZ2QIGBooJodE0+6WofwgWmeR13mTtguaNExKPJoNR8YwdD+Fu3LmplnsZvRHlnpJTYmfCOWw/W
OVy467eOBlEcmu4Agx7lH/Obp+qccTos2hxj4AIURsYjJ1P0kd3SzH2GFasqFadhPSwYIsYw0naK
vglWwQkt3cxz1qlnjjEMGL63OdIega34sVnkF76Pi1KDm6GuPIBTTUl67nCyyb/Q0zc0U8EatLhQ
vNKCLaMZAZcI1k8y1qPo0SS6B2yO4CnMBRCVUQwuWKzVwcEfrEq7iR+YPDptyKtnmNySkxSijipb
KcmvjUvvf8zu/YGQhlLniFKNhwOzty59ndjiEETX9ATxXF5LwCEBgMBmsAamuOsAsFDmflr53mPn
MgQdXALIXLeBFI9ZlJO9DWhDbuNjkilwWw6pPhS/JnxyUkljbWMpR4knptQ8xQq78f/S/PnH6PFH
Ew0T/huAzrvlkqLMZEBI59ClAEUrztZFMy/0V2/qgcPecF9EFy1hgvS2c2x/MnOOwTsad/mb6UFQ
+89M11SI1Il+7J/T0RoKhPim057Y+RdnnTAJhJEN6IOd8J8WdbFO0yRoFiEcYk01b7NSYYOAdWzY
YJVVbz62nw3v1vHAOG18w6AY8Jx5qK4+GuA7IUvXWyIbWrIDGj4K67ILLIV0brym7JERmvwUUMfW
X8axdVE2BBvx+4Zuo6q6kV92DEv46T1s8Q4HmZfSrafTw/fVvfX6H7htEBGjSEimEYAmKOy9c0Ng
M5axkw5FVRNqJIongXKfFvE9jOHgmwhS9QH0iBk8nqRVcPMNl5js0s5QAlRNlpFrmUhilDQvLHSg
Y1FnR+WekkLXJabZOTxqAIIFTlhqVpxdmScOP9qkjH3fr0whwf7mz2+Nz0bAYbrVz+NqVfdVnDrf
Zq189OFE4EjKy+/4oHUrNyEAzPwX1nkgJvrzNI+BGftcr4RZkqSPEwYFlp6fetqH3eXUNfvl5twO
fN8uX1M547A6f954ExZjdjgjEL1W4kWyq6H3mi1Ot+HI915Fu/0Dk2YhKUgM9ipOn/hvOJmeNe3X
BPrf/4+PH+lcH0Afk+RnCnqlbncBox4C5CIfRWEEjBHWGUw6u3puJWt7VdfkojlEyMQc3hXQWQrp
O43Y2z407O+UXhWa2hj4Z2CYxaQmJCJDUjTuXYCaFbBHYQCaLj4oDqlhsHzHzcz0a018QVCF0Tow
OnLur6xTIe0+f5jY8R4KbdKWcAW9StMgePsBpcbw3fTNpzN54pKjmfK7rKblGtQHYHSZa6TZo2Ci
RqiwqvjGgNG9wr40jClUV/JL0gF5fsHtIbi4ml9Euh/bKUCTHbtREZPEhjxP4x1McoIUm1lvzhx+
PZtZSuFbQNVtgUyaxzn6taxVTqOh1RHcFSkQNOnCoPqP3zP35PYa4LjBO8r/xaUqMGsJYJwyFaDc
VF+NeNkePftOKQ3aZ4AAQ1PM2HlmcWCfcuAeXNBNVomJb4Ts1CszR12w0QyJCESxDcmayC6hi/C4
ynWxtYkKH+6MB0Sg16RdLfeICKIIirUt1EvHItIimMVlfqPvj3qk/ELuvlFINjiTTP1y65F6pG78
wO1NR5/CI5+SsPYvUgEoovTX2mrF4LRgY08jTxUpzUBhlHgMds5KAB8XweVoTT5N//rvk+v5PnKT
+v0t7gMa/rjH3BYgfa1uinv1Vjt7UjfcJP597igizkpldD9mpdWMmVyRXk/qbHJwaZDru+lVhXiG
xC857xrxNHzwsyOLQcpcQN65nbHnTB+cRV5LHCMQLzvLp0kEhZelhl8qZUA9+ZDWxwHh7bRO1wd6
Cx5Kr3rBEQjNGvPVy49izNliiyMThU0OXOEttqowsjrxghe+DkZGThAP46yOM5vBcaVOACjRqQWl
qrjB7Hz8IfhynPzpjH0a6416AwcyVKaXVr37eEeJaHvIqnCZypiTjjru2I8iZd8HMSIwExjEM/Qw
LQsN6xCwCZTt20ERDyJ7UIcm4rqFAGdJwqUxo2W+sgjVwUytuDh5CR5QUbDbNiyXBaVTHvqaCkJz
TmWUUUG5vZG/cJVQm0n1nM5ypJH9kI48x6ucrFKWzx/dx/JbsIGZLc62HzYDXQN1yAjgT/cdzyJ2
GUSts1riluCWkgnAS1nAJd4nlAzeBvd+O6MBT4rV4NLV7r7pnptVj/Tds7y8EM8KZbM5kuk3kfgc
vUycUjjyXbtrCR0V8gRVCmGF7u1NQrMux04VAYjeFIorQvFvbl6V/+w+lle8nj5qi0IVIYNl3sSK
eVZ5+ZODlF/ebBnk3XAuIzPPGras3rdgYUFlvdeip7oLsl8SRZ2I++e6hUlp8Z5XR7DBns11WuO+
OztyHzhRW3TykMlSbkti5irUaPU4pV6lBB1yEEkJx/MWuGVPh8TTh8L9oVxHtzm28ytBFyF83ZUf
X5Mk7j9sUKM39lgcb3Q49/Z+3jhsudJ3BR9WQqHC6lsQm/RBthhY/hOy1hYyZx1Vj9aFnX2eeahW
wEyyVYhfKGVn+vOW2FpKwgzDsq6Mk1xzy7yqen5jCUGxcIyIHFug8+jFHYUjijsMsOxWlf1ToL5G
bFuflj9xtuolbSn2k1qUBjnssGvF6/k5gifyxVwQWhkclBedLTcYjKn9Qg8wplRzuwwu1/aNSoWR
NVLpEmHRENGIn7wv1drR65/Yj+d+lfG2BEkmeVTA5ibz5y6ac7Ks4X/opggKXfnAOuATMCpMPYHq
8Zbq0lKhFFAQW96QSbD4DAnwhbcUir75HZ01Im+/SV65bNYyUiahlg/1dPEYEXelreGAGE34SHwd
rSc7kuMi2cDXlYlOBPxCfdkrJtWCBsoCz7BoMi8JcaIxq3m3N2mguhlXPxJ0mg5z4wBm0W6AGmCI
uIm4qXDquALE3R0juG0jqNxzOpqa2F37xXphcz5NSU+8ot26E+kdS91z+D9lmWvVrD+BjBTVSILK
mFKr3kXfIIFaBM36dOEwokN5jSQnby+aZOSBcQ0+o7JnWCEoZZl6RrRkPWhiCbm6w9LkUKhcCpF+
kxnuh1BWkdxWlgeW4/jJGBtBR2yoWv9CAzRV1lntbqoo1tZIwjkIQ/dvEsrlXvTwwE7dmszqP0g2
xgW9R+deZMU1kDGNr4Ls/L8R+wU6UFPKwLN70KY9g3oePNbJbTwtzk+znX192hQl6w4KLA1x39bx
W+ibGOHuy6Kc/UuU1HWcULomLiL3JMrNW/L7SJItaXMyX7BJx5tZHNGrv/3DZzbD0Zib2yyLtUsy
9K3tcfaIJFvsUlqkfEhwrwUSX2YE9/NEdFEEd4Ug0ZeBtWTGBnxYmgFTLbum2E1AnL2HYBkLJCIY
pxaQYHU/Cr4bs2140Jy/R+kkcZoutAu+OfSuSTGS4eaiCbENY24mWg5JAV7pL/QtGS6d/80e0Pny
hbUlQ1B0fEGyn2vkOW8hk04/1SvreLl/UXu4cAWnrJBSpOXZwBV3iuYSjF1o0nEvyo9TcthPvnvH
Nr1a5od8V61qh8pY5I73uHbV0j27rhpW8IBGJTpcN+H3HfH5jPXCsSGeOp4y+/8webYE0oKBFu5V
J2u7A95kpl0GLHyVPgLR+mcTlDUv/7pvd6U3hkRSRsI2tGrzrU2MoJ7Y4ZouTAY7lhbqbaS9IL7J
6YddXMPZksmB7TaeXdvR+4n12KiIEd0TGWz5eLLRQWU1av3SSEbZsSaqwZ7H7zqEe5m+0eGpxeDT
P2gODMpc9LhjJR2acxaorT0FB7JPjDh9RKIZVg2tSU2LANuBuMP6Wf6+ZP+FIt5/oCpwDPQsFHkP
rux/6o60ED5c2rVfGyDua9pg8x02IZ7kzFIGNd0inTuTn1XNuPVWQI6phQkj1/daRX8BqBz0Pdhx
mou3c5jdkqRmo93ye31+OWyqCorIAwNMxyqw3BXizBXTAfK1MrtEIIrzLhFLW8obU5u3thv49A1+
8WfDW6wBFypaLfKn+U2puwBqzUtyR6n0mHxoYhfpHcwSWZhGOCsABhD/ViNU5ZW8qlxl0w1+OVZ4
fpw4NhqpqELxQi4o/PlkmXBfkTQER355Rq5sMvVElRds+ULY/CxXsR/frlkEl4Itvxh/ggi/U0wN
voPPW5BZUYG3FJ9oP0MPDND8rnAF/XdSJt5WRhQCSo7UVoIxQX2NlaQpJ1aflw8FkBsTYBEuk8IK
wFp1tLKOwTlt0Xd8fNx3iD3HLHK2+I7kxQzFEMD7rzS5aT57CaWCoVpaixkhEF+Xmu2ih26pysWN
ZjN85EEpFhtNWewSQZ4lU1ceLCzg5TX/jb7hOYl+SiqZqoqwtKxtDjxFYbohR+73VlkeU9lXZSO8
hsoYr1pEWlafEFfGnl+E6XZbDUDFyMiTkWJ9MqG1mnavAOTD0fzit5ft6VEMkzCxEku4QnHD00x2
NiRZxiwP2+DIakhIcJyoGLg0ol3v6Xrb3wVwPbAXLBQJrcif+em+A226F9edTF8QrnG8C4zodGP4
2xaxxJC1J3FQ0gFISlPqqmnndFGQuvelT1G059bKeKVtV9fYCmCbCHebiQ6BdbAxMpLHKFOfpJgn
k1eAeIF6J+pZ2QT67t2TVJiyMNKWPRdMOxGADYcj25QSLz1TIzmcaUpnrCJpWCA4zZKAs5Df/G3K
OzZeg0X+6Z0lViJjoDfE0mK6TVRluSWyRwXs3sxHKL3aEAVohe1YE3DwyyaPklL721RXl7YejbWW
hXDQn1wzzqAncVb6QdQRlzUi0UAmV/rFBYxwYVf0jzSrG501YO0toAi89SRmrfBWd2siSschRvZ6
olnfXRRO+DTPmJr30Ljy3YBz/F5LL+qi/ufxHaQzThkCypQqlKRajLKFvJUoxN1lg0tAS9xptqcs
9DTPnuK/g2AmdDS0izgvktzFWi06HKarjuCzcqQNkEgmJq4tUSoVrxpQPFo2z1Q+OrdgJiAwNdrh
NUOG08s1AZJr1qRTUGFPme5OulHi24OAPMPhBuAmVPd1PVAGCowsy368RkfbTuLspw7pLSnkYkAU
ElTcTynz/3cHu9lIIEE+esSdEayhEZy7ydUcSwv4Ac+GqqTVlHMarbhi9C5cK7ZL2DJLhCXIaIoS
4RP1Wa/bOKQqQMkpxEj+rVGTvQL2DaDM6F0VhsBLT9Nv5z1FeoquGu3VoimXud3cMdc92EuDS2lN
GGiUzF7wW3xkSq/q552S7qLHOJ1yxzZgtziKrmoHBSB5o79vIjLP5Qr2QoBZx1bE2PClN7FMVRDI
V2vrfBjOrwk9SOHJIVwAbAJAS85Gku2JZ/adusWP9NwatjiBHyuH1qlQt6Z+Lc2/NpCfRU6oKjZG
Rc3SBfC+TniGXTbzQAfpOl3W6bmKyVwr6SdJbDZGxiKMX/Gqgz3n27GxIyQQGfsWdHhpIJsktTX6
ys2SVSgV+f5iZkUkI02okiO76sLJY84UHGJWsNdEMI57g38oRvRJTmRpxynHTEQZ0zoBtB0cHeal
Ag6xLhAiWICvVV6/69bXGe07XzEAWgO+2hNI8kXhg6Q/0UN3S2waznzksEXhdZ4FU7MDX+Cgatpd
eslcHuXhotDK7ZSXAcM+KCvqWZ0znzcMCxBy9/iH5NG89INTeLJGIcuiCs/vO+ixQs8VgSKZ7DA7
+O5VhZWIuCd7HX3RscYZ1M+2zCgGR0omXyISfj/BvTKFFDAw8P0zaOy7icdT0WXl0DeEhGSKPCIO
bUuz8H4uFGtnwbo6yYWq14X7Cp9FNI0CQOsCSyO/88dJbWsEMXp+ZMCd96x9UpzvX0nrLilBemUq
JIdD9cwYgBRCFUM1U9CV64ZOPmTqdDKGRDLf4ct6arjnAvgrMXfyajWKE5PiZ+iB4Aq4O0Br3rNQ
0WtzFHgV+84dcNPljmA9iHAseNs4Du7R1/j9j2LZdSU0YWGwzFnF/12jMx4uSwrK7zoRYH56eNXl
1H62npzpG4IAIj2QO196i3qtE8RRbO+w6u236yHrblyxi3BI6ByMgSvskn9kr4sgqdQRL9h+2syv
Uab0QnKuCIVowXK6kGDebppE0KDFol4m24rKvmC4j7t6wmEvzvrIggyEfwTfKdtELuMOUx5J0nOh
QiHHlV4Pv46MeNa5fI+MNhFCkrxzSaCq/sxobE0A24QftY5qabo+ihRDN7DVsQfhOMRsaI/XsAac
ix8lD6XnGUxY/Iko7QzuL0X1gUn71kKjp1y+c/rHLD4HtMY+OCY6iT0jX7eYKbKCnvjSmf8aLnUg
iHR0YaUssQjh9YgwE0/s5eM7jaKU0hHp4XDXze0e7yBBqdvvCYGBamzpN+0DCWx+PIkcCLY1dGFQ
3C1rJBzF2GFABW1/GuLx00pxWi9u/uuwCNHsCmWwtCfVIkvOgrFG0e5Hh42AChSmugSEohRurMl+
m/AXAo8nAewfLXVCRF7MLGkYb9KYTDExhkXrwzGqcJxRahNPKo5D+cCamuWMwO1gfsSmaL+PZ6rN
neBRRNk35Scf9pg0XG4r0tjImF1pm0X4Ua0W2SVzlKV+fsMWhFH4P2HKD7NN+oidRjj/IAaLs802
GElAHcxa7nVmeZAWSu3MPI4FKBLuzpaggVd8BDCiMoTX87X1RAn1jObN6rrytf8HxiPsamAIfc+8
P/E4T+qH10biGlTvZBIL+apjgKA6sSLGVguBHvoSXTHwqDN9XN1Gde/RJRk3ezD+qKcB9HafTNvb
cN8F+HJvUBMZTvo6Z1ixR8xSikdzB0pD7ZO2uh14g6Z2Qi00QYplx0TL1ezwre+VlYtTQV8xofT+
VYzxwmdzKLrYlCzk4ORyKRVFzQfp1H6tev92Xc+MfKDh+lDFpeNyHI885A5vwsd5EPbvMwzECLOL
PjhplcFSO6XhJuumQmRLhRof9ktbxmAlT4Js2UqcZ6LVntoPqd2mFsqO9hhlQ6T9MSG0plgJJYqS
YkfJyJccgewulInT8B1+pnihyxaTIECUSV9uPbKzSe6A5P0duwAy1SyOFIq09tduDhtagctMO41K
HcANUFbB2wvCXWQ7vRKn3+Z7y84cK3/uWG+hgjtNUMIaLYYglxVKJ/A9qKRW4ArTmdXsfdETh789
VF28Fn4K5prmN5E+ZcJJIQLhRLhxBHeuc09auYwmwbq8Wu4yGi2okaiPs1anQA7MwK6oNcHCTl9k
pG9VMPkQ2vCkN1Ehndku3zNGkQAv4Ja2XQvHNEdO6Hk1ZLxS0PRgqh0ktk45Cip04H4gL243qsf5
f7FartbJK2IqQp1NEF0FSKfEYcHIdDdx2NLj+ppewxCK76mLttAoDJbLbFweq7/xmlHJLZbwokGa
snSvC+h09kMNSWmiS0o6ss6Pmkb3t/S4If7ceIbx/iNijo/CTJZXvosHrR4HWA7kbj1Q3FBDmpds
wADM1T296yQBKNpJE5ekkmlG4SFuDjHsmPtQ2pONvn3vijl9RcUPMo+nmBucPuQERcnoDo/udJw7
+xaRWAm1aIsozeqMAy9lfnjJtFpjL3TFEp0DeOh7n4ioL9pt0UlI4+wKfgB5ldHKv7wSPSY3MHCi
BJjlYJvdNdgxdTPsiJo9HFDNlpjLHL+FXtKstWYiCO2cYbpfxEkfrwvUa6ZFJUZhm4iz2nzl8IoM
vdUkOA8Ard3D6bAwpv7EKWpoF3uHkjuv36DaYzeTjFaUaMAVM8RL0Rh7Vu87kFzQMvey2e6v1p1a
eTlBjVNTf7hsI7zH8SFjYjo5J6Wl1bQQ5oj5KnDjHyLY1ueE/5kigq8+vmmG1Fu4T186y7fwiKIc
MP9utTTvp55uhQonj/OGQ6g+NUCpxFq2aFqMk1vJUBQpSrOvPBcBQSDHAAANxYdd19pmrG9KTSoE
ClHdDftqe3MYoT6I5wDarW3KbQ3DA0qREcrvfxKxnDd8iwf0pi7uADO09OTJ0vGnGdpuvNzsBI9s
e1NWb3+AMHg0NKzW5jasBMs9YfPsh4iEhxLnen3xpvnWtJfJAicZ6r0ors0k6ZbUT9AsHRDahjM0
eg40bf086NGDCUcyjfUxmExlso6YDJBa1MIrqeJH9A37l/0g/K4JY9XRvVzFizuCZaSGljuN1Gn6
xAKulk0mcsxYQLWXc3OxMtnGv7FScsemPNqGwqAQSbbaxGFh+ubnf2iAwUznWk/NYsGPmEqLuzGv
4HHY7e3yz03Sk7KB6qemp9FO4B34+5C2Z/8Lk1YhI+H1F6ar5WKo1TO3JfHsjuiJ1aJaWfOMGs6k
d+V1F7GVpddKtzWVydNQUCQDzxz4RJW44WoUtlqObV3lvyw0MNadyE3NHk5AlNW5CCdW4UyKR6Ol
3L+eGi4JXhux5CQp2B6MY8+ky3FSKmPVbNgDc/2WI0Pqv9ObTYpsOz+t2LOKTw9wGae67XzNq2qp
u6eLxeXmhjTECWKpl5uAGld/ggtTP4zBjGljeHCNkDoT25AQLaOo6kqXgjjd5X8zvlH+lUNhSKW4
aIqLP6uxm1UvjayTfUOT8LMzonA/fi/iW7BtX/tVCmOmHjO2soGoCXlfFeZG4nMHIuUqVRkLz0tL
gC9U0JfkIbCzjerOXQcdws1ZxbKNckkGY0Kp1MppCe68J3u0JFbu6uKMLZMjlwIePyqq4oHmuBuP
oiLQKUstoYCzpgZCJPfo3rcZVWFUWc7RPQvxxokJ1NSJ5pO9F1qeNN0lj9S6x+3y/sWkMmZzEMA0
RcCmzvqoJRWkUABPWY0k1QBHC+yXfqYaIcpmTkE2dzftqT1dU5D3MzuyUSwCFPYH1nJ+98X30XfK
NJZq8K3psq7lz1kBChF4w9K6ok0LyEnN4aaAvjP1FGIbYGOzLM4tYzkO0gqNdHmTcwgHvDuVi2DE
DOfF5c6Y+HCihbqEmhZhsnhEPIUyoIFvmpZJQvKA+vPdHmuze/787120WTQnYS/C1UVwjHOlfwwF
dek3C7DZAZyPUUr2vLre/YKR1ufwi4lDPuKPnsnSv8tWycGVe4JpzHSLMBEVcfk6wtf6mNm/N5Ag
NW8bGZKC3uOkAJqlvvjALoUP36IRgu+0srfPH5QtGOALQutUJlzfpLXWzswYes0s/yHQkMSO8iZV
VLhB7V0bzU83b0FM/ir7yPRGgPIe2W8oRHHvoWRomeXAqb8XN4hz22Y7OCCvM41FrXG0qn2R2gGH
fZ3hnOGK2Y49Pi123mEE8AxfR9rcTGi4Tjo+f4Qeg/tzMHrPQV4raTU+orU2lTJXX+KKBIIcZ1fl
hG3wE0FE2gCope+8cxr3asyEz/DGXPpqyIqRXtaPOKknkw6kK5/zbI1pSOPTRh5pNBLZeI+fp8PP
QZRyaFVXLeCmfcT1kMxr0sD6oUZnH+575X6OVWtoHmkcndIexVnG+BAeKhdoqnOVso1r2zPIL1DH
54H8vv5laWi4CzyKXBqevgWlryoRvEMRDL2Uhj2easS4GZYrE7hlvBQ7or+FiCBml/HinCjGf3yx
0A5XIBAtzH+L5WiHoiSUgAe7RQXR5qcuQZxHUN2YbQtxcPgd/YgGwiNeunzTrAs11ha9HNaEWGWm
eIbpDvvsvuT5Yq//kUyib1cv9L2WOgu1KL49ohP9AvEu7u3U4hl3EEsyZVAxlM/7AuUyF2nIfVG4
y8+Nd7YWqjsTelFsP7yPgvYWm52OKsnfYVca4gROYFGqIWDkJthPqtYuyXClCUpTLcNrLYWwh0rp
frzEOCDiygQtvEGK70Zr9XiqbMclaGRl6PWw8UsZqRQwjM8mjAkhkDMoRDYfGT/WyNXxWceg7qt/
A4lTDRNEq1S5/SpSmousxwGwu5il1oLNWiuYDKn2qBI88zYOqlGC5vmG94a4FWSuJkUC5XIC58KF
fQFptuf3ri1/rx6VIadt6fsd5y+BsK0NiRsZSbdLM3Uydyo0gAVNenfytdZDx+fkG6xImmnJMlFh
2c9Ddh87NyZj+/x6woPhA1KOwgZTgLmLNPOKLvaUinMIOS4QqEBb46FDH62ZKh54L6jpbPS/tMsE
bz2YznMNhEAMvE9zd8sHV5rX2Au/v7KttCUWNpf78xjTe1dbJPJAf3WT2TCtepaBNMtSSwnYV6Cz
ZofgDs1kNpP5Vacjofnqdrxs2ypPFnAVHOYvQDnZnwwFuduPS2CZzWky7vAXT7cb1uExuebWh/uj
ItyNyrCRox+7fugz7ciQ/2WxVtjJUusFyMOS4RGR9kQO1zRPT9FtvSFHpuH0zUGiJBXQhbhAdRi/
w/3Cd7OVCwOxIT4MvBoCplPAoGgLgUvAJftUccZfJYWRV8sVptGu65W75uC4YPnUYulQB+ZVwwKS
Jr+gtkSAT1zIYpFiSRDttzjV3OU4UBXbS2hBTUiAX8eNuYrYAK0fpP/RnXXKnoOSET6LImLu+gyg
8H0/wKN8bOUBm9m6zvHLvzI8ThB+jZvxIe5BGxeYvxPaJYUeRnRbcpbQf1kiV/hgcAlK1+HgQney
ApGxThrzB+X1RIWPAq9VRz+uzzbGeTUY1xY1KHt2UqPQQQyhaF0eKUlGRbo/AahRMHlvbYNCqFtR
PY5MEocvmNJ+ohA0JzJY6qjpyF/2SHBiB63pnCcKCtyAkzALnQeMx0WxN0dWHSV+mOAoMOcK9Hmf
tGfrv9JUVm+NobHzy8drg21RgKJb1Kd/COarKFu8p5gpwvA75eSi+wxQTu/GdImdqC+0Swab0/JD
uOQEs2MSWgZWRatVC0ehvi8hO/WqxU64zVBVgEjrozU/CC4U/SoI/wdvp3XEDXssDdUQ7PtrJ42I
5/41eTO8JSXaV34JaKqMPosiUUQmwkZWBuGkid2xw6KkBmkFyTmYSuy93g22/BWzjNCoC0fbmPhO
WxNls/ikA3P8H1qa8j/jWgIkd+7wQB5zVeM0Ho3pugTC1/LPUQ7bNU/AUgSq7TwOZvBmMnUgVpVY
eEilGwkR42shTKtaaIMxxBF+ORq/zjGXTZdgpzxUN6LwIKxth3j2ihDnRFtk7ZRgTGDOXvAFzFkY
wFMQ0YlxK6qtmrXKNUFQyTkS/IQXeiORtXJqpAoOExFoH4XcENoG3NoplBuwqjGfSnDOoFi/dRpS
MOOqC7Ambdi8t/MYS+8F3d2gl0+nIpQG4trFqSoWuQ26TMf4aQ/oIxMuYdMxjdkkP5pmW2Sos8zu
1K3VoHJzNodNYrE617YjMbq+ESCKPCLLnFnZ1JtTulYhXxwaK4E1jz7vJ81IPYp/QuojArbVESTY
TNJqLKp30jZZmAedr4x4P/6r8G5FSQoHrEey6G/DRnCdAzHOBVlFo+ta3eaJPXLi8JuwLqNuPWWL
ZVe5hDcTYQ/asI5djGljwpujYL/Xn8wMjewrOpCjJnkzVD8wrJxgE7/i/Ya/z6rrY67CAsKqZQB2
4Xo0ZnNPFZeavxpDrorUBwo6V4jjFUrSUYS1bUHLdWr8dj2/twqRUVPrFb5rqSaRAmR5/H3RtMRY
q2QrTJWYlgRIK/HW2O4jTwz3gYi9IxJJvwkx5Y6CFdEy81dM352lV21DYuZc+LRoJJfBFOs47YhQ
9cNSbFLVdfGGL5/IaioYfb+yZLPHFzqcyr440g/M1FlH7cVU+p/3Qqv+kdRmXfQ/wQOkSstaCZ+e
E/dW6PrVVEWHTkzA4kgqzsqBYDx7qj0dGpRf1qXIdf2bd3p2h+sEJyisEpWXvcF6KyX/IXCR1N7/
ZPh5gHpWwv+7ZsviBwPW4q/KJ1cOx9znKornQjQnDF87t0MR74dKPhFg0lstCewBkqCqebbk3vU9
m67iFOnQWW++12wu3nAKYEFoYIzYFYX/TfEXMjDiFDGyVWFvSqymJD8mJiqHYUSmS5TFq219NMn5
XKUN90xg3qhUYQxQtIQG9sL2oLugeoLOCq4Z4njuebOHIS45SmzsxEIhWqdQiM+umg/avPyFHkEx
xy/VFi8URa+aEnZXzZf7ot3vpp1HFsNgztO6iRnVm2UQ7dUdue9aXP/F9OAbjJkYdjgoToU9ZPMj
NE/05pbyieXHVa2YzY6B3e/LvOdyRY6Kp09Qed8kaKhiUuaHaUiFV4Zlu1pKfpLL+h94UMduRd2K
3dCFcmu369uAXFIWdwWm+W2fF4cLaieLF9Hl/sz/QHWYbiBPDqtxjkjnv10sp7FFPWMSlBy6ovHG
rC775q1+Oa8YA7keQ8KSykyHBejZLzoZK1guT5mnTNFcuQ350ZgVrKwIwjCCnnFVI4iTJW4pdpgw
LOiUOX3N4K9IIZIZsXWvGjHRIb0ExeZvs1s8Tzn06Se1dPXX3MtgS1pWLn3C/VLWiBXNEqc/MuNd
vb/nFkEmDslxJzcgpeeYo5xsCk4S24uCjwlR9VJPZQr84Q8xbUQz8caAIlY9vg+I1QVoxTmppHQe
1qqlz0+BxwWFNNlOu1nzssraD1ENe0MRcXXyNRMrnmBcMs65WoCHGWsc0jH65csL+gEn0m256zEe
9YVn4S99PUpcm+swqPZDS1ANraPqGMx7+eB8/Fj11aRgkWggIMLGssDqFqTf30YYE1668/n8hGbM
cDh8fWfry6ekjnr/qgki0mAUuNMUO2nRoxdN+30fYL+WUvHunnGEBcjcSv+VCtJUbuqSIm7W2+/z
aM09+Pr1RBduPHKBRWabxAhG8awmASBHLCfm31hNkvW80UOcF8mP1UT1esWnDt/+TqKQX1b5dNU7
ruMgGNCnShFW23jP4lZeBs8WoNmA4AIoZ3oqURkIuD+m508qnse8ZhoMxuQ4xLlJyTQxD6mDaojR
FMmaXo0sCISWJGNZQLVF2lIKqpvj5ZQNS9bDasg2iz+/TjdCMvVXwyED9QQryU2SRfhllRKKxCeQ
vzGjzl0xacTFbmo/4wWeZql2AS7SDw0sgi1YntYGiBKJqRZCqOlGWTD6kN1eOzojuxFExBMxPWxY
TmQ7F4QVwmjOlgx0FOWYZX4CBYnaLe5ifBdbBbipwCuLD3KE7j3EHJB4fV3A5pGGhCMxaGbbZqGa
ZCvjYHXxnogjNywkiRdYXGChwAxAbK0qISycAFtzd0eUwCO49GaRRyl9qLrihpP1CGcGbODvw6RP
db8+Th3BiX7NeTqjaCGO7WOb1neMVqtsInLXovfZAIKstqqaNSSg8yMrsVgtw2+iTUEwQ8ykb2UE
lBjV2RCBq0cpgkiqH3Fd9NnBIzAit5Y1ZvnwASV+ybwCr0PHlsT3/zo72k0lCdxi9yMGdk5Ip5PL
I/lHLEPzKcWxTfq+/WPn3j8/7pJ+zq2TQ7vx8vcOq2kT5M1EruN9eMpUKhxR0IkuEfyc/6Nca7ad
CzLOqkNQSjIaPl0OBaBGfTL+yuJJvUBITheBLj93F2UsguQESR53SEYhPLQxB9hNBNjoq3j5FKFY
4zplmKFaiSteBKHUP9Suybl6GQltRL1N3xSG/1oRem0IHDsKgCNHVQ74En0NXty/TeapanpAp57a
u8hl
`protect end_protected
| bsd-2-clause | 1e4aaaa01caea4695988c9f820ca81fe | 0.938363 | 1.881254 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/CTRL_BYTE_CHECK_fehlerhaft/CTRL_BYTE_CHECK.vhd | 6 | 3,794 | -- CTRL_BYTE_CHECK
-- Bytes zählen und prüfen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 19.12.2012
-- Bearbeiter: mharndt
-- Geaendert: 18.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BYTE_CHECK is
Port (BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
PARITY_OK : in std_logic; --Eingangsvariable, Parität in Ordnung
BYTE_CMPLT : in std_logic; --Eingangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BYTE_CHECK;
architecture Behavioral of CTRL_BYTE_CHECK is
type TYPE_STATE is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_BC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_BC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
end Behavioral;
| gpl-2.0 | 8e57e950da2d097063740043506dbb5b | 0.585398 | 3.130363 | false | false | false | false |
AlessandroSpallina/CalcolatoriElettronici | VHDL/10-12-15/10-12-15_compito_turno3.vhd | 2 | 2,970 | -- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity difficile is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end difficile;
architecture beh of difficile is
type stati is (idle, getOP, getA, exe1, exe2, exe4);
type memory is array (0 to 1) of std_logic_vector(15 downto 0);
signal st : stati;
signal REGS : memory;
signal OP : std_logic_vector(2 downto 0);
signal A : std_logic_vector(15 downto 0);
signal counter : integer range 3 downto 0;
signal enOP, enA, enEXE1, enEXE2, enEXE4 : std_logic;
function next_state (st : stati; start : std_logic; op : std_logic_vector(2 downto 0); din : std_logic_vector(15 downto 0); counter : integer range 3 downto 0)
return stati is
variable nxt : stati;
begin
case st is
when idle =>
if start = '1' then
nxt := getOP;
else
nxt := idle;
end if;
when getOP =>
if din(1 downto 0) = "00" then
nxt := exe1;
else
nxt := getA;
end if;
when getA =>
case op(1 downto 0) is
when "01" =>
nxt := exe1;
when "10" =>
nxt := exe2;
when others => -- "11"
nxt := exe4;
end case;
when exe1 =>
nxt := idle;
when exe2 =>
if counter < 1 then
nxt := exe2;
else
nxt := idle;
end if;
when exe4 =>
if counter < 3 then
nxt := exe4;
else
nxt := idle;
end if;
end case;
return nxt;
end next_state;
begin
process (clk)
begin
if clk'event and clk = '0' then
st <= next_state(st,start,op,din,counter);
end if;
end process;
enOP <= '1' when st = getOP else '0';
enA <= '1' when st = getA else '0';
enEXE1 <= '1' when st = exe1 else '0';
enEXE2 <= '1' when st = exe2 else '0';
enEXE4 <= '1' when st = exe4 else '0';
process (clk)
begin
if enOP = '1' then
op <= din (2 downto 0);
counter <= 0;
end if;
if enA = '1' then
A <= din;
end if;
if enEXE1 = '1' then
if op(1 downto 0) = "00" then
REGS(conv_integer(op(2))) <= din;
else -- "01"
REGS(conv_integer(op(2))) <= A or REGS(0);
res <= REGS(conv_integer(op(2)));
end if;
end if;
if enEXE2 = '1' then
if counter = 1 then
REGS(conv_integer(op(2))) <= A + REGS(1);
res <= REGS(conv_integer(op(2)));
else
counter <= counter + 1;
end if;
end if;
if enEXE4 = '1' then
if counter = 3 then
REGS(conv_integer(op(2))) <= A+REGS(0)+REGS(1);
res <= REGS(conv_integer(op(2)));
else
counter <= counter + 1;
end if;
end if;
if enEXE1 = '1' or (enEXE2 = '1' and counter = 1) or (enEXE4 = '1' and counter = 3) then
fine <= '1';
else
fine <= '0';
end if;
end process;
end beh;
| mit | 7d80f297bd6ae080111a222f8f7b2b47 | 0.550842 | 2.739852 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/divstage53.vhd | 1 | 6,574 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity divstage53 is
port (
i_mux_ena : in std_logic; -- find first non-zero bit
i_muxind : in std_logic_vector(55 downto 0); -- bits indexes 8x7 bits bus
i_divident : in std_logic_vector(60 downto 0); -- integer value
i_divisor : in std_logic_vector(52 downto 0); -- integer value
o_dif : out std_logic_vector(52 downto 0); -- residual value
o_bits : out std_logic_vector(7 downto 0); -- resulting bits
o_muxind : out std_logic_vector(6 downto 0); -- first found non-zero bit
o_muxind_rdy : out std_logic -- seeking was successfull
);
end;
architecture arch_divstage53 of divstage53 is
type thresh_type is array (15 downto 0) of std_logic_vector(61 downto 0);
type dif_type is array (3 downto 0) of std_logic_vector(60 downto 0);
begin
-- registers:
comb : process(i_mux_ena, i_muxind, i_divident, i_divisor)
variable wb_thresh : thresh_type;
variable wb_dif : dif_type;
variable wb_bits : std_logic_vector(7 downto 0);
variable wb_divx3 : std_logic_vector(54 downto 0);
variable wb_divx2 : std_logic_vector(54 downto 0);
variable wb_muxind : std_logic_vector(6 downto 0);
variable w_muxind_rdy : std_logic;
begin
wb_divx2 := '0' & i_divisor & '0';
wb_divx3 := wb_divx2 + ("00" & i_divisor);
-- stage 1 of 4
wb_thresh(15) := ('0' & i_divident) - ('0' & wb_divx3 & "000000");
wb_thresh(14) := ('0' & i_divident) - ('0' & wb_divx2 & "000000");
wb_thresh(13) := ('0' & i_divident) - ("000" & i_divisor & "000000");
wb_thresh(12) := ('0' & i_divident);
if wb_thresh(15)(61) = '0' then
wb_bits(7 downto 6) := "11";
wb_dif(0) := wb_thresh(15)(60 downto 0);
elsif wb_thresh(14)(61) = '0' then
wb_bits(7 downto 6) := "10";
wb_dif(0) := wb_thresh(14)(60 downto 0);
elsif wb_thresh(13)(61) = '0' then
wb_bits(7 downto 6) := "01";
wb_dif(0) := wb_thresh(13)(60 downto 0);
else
wb_bits(7 downto 6) := "00";
wb_dif(0) := wb_thresh(12)(60 downto 0);
end if;
-- stage 2 of 4
wb_thresh(11) := ('0' & wb_dif(0)) - ("000" & wb_divx3 & "0000");
wb_thresh(10) := ('0' & wb_dif(0)) - ("000" & wb_divx2 & "0000");
wb_thresh(9) := ('0' & wb_dif(0)) - ("00000" & i_divisor & "0000");
wb_thresh(8) := ('0' & wb_dif(0));
if wb_thresh(11)(61) = '0' then
wb_bits(5 downto 4) := "11";
wb_dif(1) := wb_thresh(11)(60 downto 0);
elsif wb_thresh(10)(61) = '0' then
wb_bits(5 downto 4) := "10";
wb_dif(1) := wb_thresh(10)(60 downto 0);
elsif wb_thresh(9)(61) = '0' then
wb_bits(5 downto 4) := "01";
wb_dif(1) := wb_thresh(9)(60 downto 0);
else
wb_bits(5 downto 4) := "00";
wb_dif(1) := wb_thresh(8)(60 downto 0);
end if;
-- stage 3 of 4
wb_thresh(7) := ('0' & wb_dif(1)) - ("00000" & wb_divx3 & "00");
wb_thresh(6) := ('0' & wb_dif(1)) - ("00000" & wb_divx2 & "00");
wb_thresh(5) := ('0' & wb_dif(1)) - ("0000000" & i_divisor & "00");
wb_thresh(4) := ('0' & wb_dif(1));
if wb_thresh(7)(61) = '0' then
wb_bits(3 downto 2) := "11";
wb_dif(2) := wb_thresh(7)(60 downto 0);
elsif wb_thresh(6)(61) = '0' then
wb_bits(3 downto 2) := "10";
wb_dif(2) := wb_thresh(6)(60 downto 0);
elsif wb_thresh(5)(61) = '0' then
wb_bits(3 downto 2) := "01";
wb_dif(2) := wb_thresh(5)(60 downto 0);
else
wb_bits(3 downto 2) := "00";
wb_dif(2) := wb_thresh(4)(60 downto 0);
end if;
-- stage 4 of 4
wb_thresh(3) := ('0' & wb_dif(2)) - ("0000000" & wb_divx3);
wb_thresh(2) := ('0' & wb_dif(2)) - ("0000000" & wb_divx2);
wb_thresh(1) := ('0' & wb_dif(2)) - ("000000000" & i_divisor);
wb_thresh(0) := ('0' & wb_dif(2));
if wb_thresh(3)(61) = '0' then
wb_bits(1 downto 0) := "11";
wb_dif(3) := wb_thresh(3)(60 downto 0);
elsif wb_thresh(2)(61) = '0' then
wb_bits(1 downto 0) := "10";
wb_dif(3) := wb_thresh(2)(60 downto 0);
elsif wb_thresh(1)(61) = '0' then
wb_bits(1 downto 0) := "01";
wb_dif(3) := wb_thresh(1)(60 downto 0);
else
wb_bits(1 downto 0) := "00";
wb_dif(3) := wb_thresh(0)(60 downto 0);
end if;
-- Number multiplexor
wb_muxind := (others => '0');
if i_mux_ena = '1' then
if wb_thresh(15)(61) = '0' then
wb_muxind := i_muxind(55 downto 49);
elsif wb_thresh(14)(61) = '0' then
wb_muxind := i_muxind(55 downto 49);
elsif wb_thresh(13)(61) = '0' then
wb_muxind := i_muxind(48 downto 42);
elsif wb_thresh(11)(61) = '0' then
wb_muxind := i_muxind(41 downto 35);
elsif wb_thresh(10)(61) = '0' then
wb_muxind := i_muxind(41 downto 35);
elsif wb_thresh(9)(61) = '0' then
wb_muxind := i_muxind(34 downto 28);
elsif wb_thresh(7)(61) = '0' then
wb_muxind := i_muxind(27 downto 21);
elsif wb_thresh(6)(61) = '0' then
wb_muxind := i_muxind(27 downto 21);
elsif wb_thresh(5)(61) = '0' then
wb_muxind := i_muxind(20 downto 14);
elsif wb_thresh(3)(61) = '0' then
wb_muxind := i_muxind(13 downto 7);
elsif wb_thresh(2)(61) = '0' then
wb_muxind := i_muxind(13 downto 7);
elsif wb_thresh(1)(61) = '0' then
wb_muxind := i_muxind(6 downto 0);
else
wb_muxind := i_muxind(6 downto 0);
end if;
end if;
w_muxind_rdy := '0';
if i_mux_ena = '1' and wb_bits /= X"00" then
w_muxind_rdy := '1';
end if;
o_bits <= wb_bits;
o_dif <= wb_dif(3)(52 downto 0);
o_muxind <= wb_muxind;
o_muxind_rdy <= w_muxind_rdy;
end process;
end;
| apache-2.0 | 07669bdf68ed839fa50aa883e0c8179b | 0.543353 | 2.882069 | false | false | false | false |
BBN-Q/VHDL-FIR-filters | test/ParallelPolyphase_tb.vhd | 1 | 1,175 | ----------------------------------------------------------------------------------
-- Testbench for ParallelPolyphase
-- Initial version: Colm Ryan ([email protected])
-- Create Date: 05/05/2015
-- Dependencies:
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ParallelPolyphase_tb is
-- Port ( );
end ParallelPolyphase_tb;
architecture Behavioral of ParallelPolyphase_tb is
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal finished : boolean := false;
signal data_out : std_logic_vector(15 downto 0);
begin
dut : entity work.ParallelPolyphase
port map (
rst => rst,
clk => clk,
data_in => (others => '0'),
data_in_vld => '0',
data_in_last => '0',
data_out => data_out);
stim : process
begin
wait for 1us;
finished <= true;
end process;
--clock generation
clk <= not clk after 10ns when not finished;
end Behavioral;
| apache-2.0 | 8a195b4fee6d25ba64a096340fa42204 | 0.570213 | 3.956229 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/igdsbuf_k7.vhd | 3 | 814 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Gigabits buffer with the differential signals.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity igdsbuf_kintex7 is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end;
architecture rtl of igdsbuf_kintex7 is
begin
x1 : IBUFDS_GTE2 port map (
I => gclk_p,
IB => gclk_n,
CEB => '0',
O => o_clk,
ODIV2 => open
);
end;
| apache-2.0 | deb1792b2108dee18ef1c2e0fa6c7c4f | 0.46683 | 4.13198 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/bram_fifo_rstlogic.vhd | 19 | 21,262 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dKfOe1Fgzj6faSFeL/IK/IGbXRIzt9OQ8DZnq2KAQwbAq1xs/txiDbhMB5jT5GTGOpfv1lX7K9mJ
mDVaIsrDmA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cmnaZ+nYMcuVxuKDdMnuchBB9inZOxPR3/E/irYVdWCPhl0UM4JuWPFoKMQnAcsoQ3vgnwO/qltn
0x8JvlvddPokOTwabXK7+R741NBmTaawP5Y3zobRhI33jusePpwNTanCHaHjalZxzALXRseOguzG
AwGiKgpBkrzwT+frUqs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
sUxQSwzYYe52m4+VJThnA3rSxL81p7y01A34NmBjYzEeDRUnhBCVE2EYcZxUZHf3SzWeAqe17qZn
+OUEYPsHFdXLy5QnKWkfeT6eelEedeGrqLjWta/XE+CwvggarDRC3yCpKHD1RObvSaidPkoLOQaz
Mr6i41kRIdL7xQbC4uLsdgEZKWh/fWAVQ0EsVnkKqE8EuxaCZ+UTjEptEyr1FyibFlRQuCcRV1zc
KGcqqHxwzSvE0/TqNDvaxlN4HZAny51ra9dxL1achi8jzJgZlO8wt9Agqbh7GQueaCXon2S1zoWz
ehgKeTmxlL7ytzeVDSpaRq2XKBPlYb/82fe70w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
nlRZm6Q4mAeDfFS8oXcdcSIf6QMcM0qJWL/GpoNfKsPw7GwRrG7w5Fv9DZ3ev8dGDXi3ZhhDXcQa
Irin1hT7IkRZSupkXr6uysVtJeCdG/feYDkdTZzOR87EjbK5yer40aqraNg1lVIuObcgZ8AniYE5
0hMf7gQTkG+H4+tX0yk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HiHN8/USAozrVtx8xCHzL7SU/8fs0dpiHUe+Pxq1X1HHq6PWwlbojxR2di+cVlcr3m6I0F2zjyVW
WLu1kh2il765GldD+RCzgw8JhGbJOXcaDKXvV9p6bqICOBy5WCTf6gQ/vOVRu1kKDvf68tu0aJcM
5GW26Rwq/4L2jSNVHzuzVdgC87Mdq7eVgLL1qlhKwYslU6Eg0eOYTUfGfgCo2Z6Lcfi0atBesKpT
DSbchvClt7fyjz3I+qeNhclJOyfOLBdaqFIyBSFk+zxyw4U3h7toqFVwQu8Fc+NwLgyBezl0ZUBN
S4Kep7fupBYYGAqkU2vi+UvgcgkZQxj4+5jXGg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14000)
`protect data_block
0iHMIpFOrX98h7sdG8ilVHYbTeEnJdFbnTUVidR1vNbZAGh2cr4HmE6keLgSfMCD5h0NPMJszn95
lefuw46FHgmdiq1KHmbCqItVy9Bb5EntBdVL98scm+pu6FWXRRXll0IwtL4DpJWcBV+kK2crlsm4
DbStY30V0UJHYPmRbtN7R+eKz1y7qrxQEJBLHntXAyEJAemLkMyhmSG2lui5SLnF5vCLy9VBDhgu
0cM3TC/3C+fmgqIUw1Lldfeth887ToXNdGBy5IWMOti/xwOnavm9yQQ1UwJbBkYiLQb9LaG56Ej/
6b3s70/XdKd1gISGQST5d3eCI9qFMafOlAhy9mBKK66XeRgNzy+0g0r068yGEyHb9ijAPwNS3hrU
Ba6w8x0UPDig8kW0gNzuw1xMnzrz6t1GxGnaENQ0mQ5m6YWeBPabdEav28e4EDezzj/HpYgvtZg0
12X04rYK337RyACk3j5D2Ho4fKfvgcuNAjXJrce58FX92+bpsHTSgl7nU0qhBeUUj7nsLotrgyvi
VfqUfk3XcleA/X4bxY7Z0+ABMZk9P8DArBqbAYiaAWXNw5Tq6D8VurqAJWH7lvn/YGDqAKNvA5pa
B27McVsttY3zNbmyQf5ZWCZ1il10jLS/WghDIpsOrZK5Et/7osNwi0ofldsB+I6o27Tmt5LRJZ8L
nERGcNUzzjKVopFMokJGr2OBWa0z3SRS5XIKKNcf0js8B6wwEVqujww7VaqPMbQKUueP0svfZDa/
NmNlP1tDSwoRxhsiLmiiD/g6rBkqkisR0Q7VqDUyd4mk2BZefv5U4GfJV93zvjxFd8c/7Ts2wZXY
u2SkYAP+2gF1dK9JfyX3lq6fEPtOPffq1e+fOgoy2ArmFsDR0SP6QjXnb0sW2l+vngzwPxJeG+dR
u3ujmcTCMVjYfrQ0hBWfk7OZFh5zWuDmCUul8OgDXLh6r9uuLoxwwwyjpXgTcE7msNWqZQNU9L7K
qxgGPgiDLKq5SBuhxWrigGr3a5XzIG6Ff3VPAqxjetGns/x2B2m5VmZRthtAo0phtgFNrpl/WNL4
rJ9fzG3/1OtKYs2RCXPM0xhx/SxJNK4wDtxzdAzPxwGktD2EsckwYe0fuWeZIpD0N/P3nHV0a60L
ep+OL0n68X8bf/6LLoa/UWDRHHE8Sf4qGAEpXmBIesYd3B0KCXEfAsVypFaLVS59I46ay6qSWzlf
YH5RbR/MtwNwEzJ2rB0kGob9cFMkDARuVWmq1ocVMM1NYekLuTqRQapB3T1xBNUldrj2DQKCzAyT
1Bi8/bK7Q5/uO2NoXvg4oZiWbS0m2iqo1NvhkPjEfkbuPJAcjC9G0m1zSHLDodmuOXbRmokvkn3k
UwSOgDDSY9F0GAKzR/L1wq1KQrMnZFNWKieSBwzVxy62YXsNa+/i27+DWimG1LczVOqSlWG/gtM0
s9xDlunU8/YgDjdVTgvBLCy0lJ/9fcL4jX50AX5qNjrzikVICzi0Ob3plQQFXZpGaCjgf/vqona4
mXrQoOI2hIRv3ol7MfwNNfwhN881ZZFRVNMgaIhn/7UelXuRnzGI/tcmput7Q9DjmcfIiw6z3fxZ
J0ftEWcOpRMlWhUjAL52/ymkVx6a/fs3zNV3SbKN9A+GLYrSzTewpvMs8er/nIIl8zA+YR8fVVPn
PrmmXZQ9LhYp3C0u3bKRyJrLwlEVJS90LMzAMbT2oVxA86MoDeNlTebNXpvZ0FkUVb2nuQJD7Dti
6PDoR+oaZuR0hDYwsiNiaEIR/7UzU7H4yis9XQwP8d2gd1cJfepCKqeV3K0/W1knlpH82PqISmhc
LMXw3dVQvFaacm5eyyjzi8FhdWu3gQYwOLZT5PLqUMHZ88EviQcthy8p+HVWr37KFfYUCGbOpQ86
ZOdDcrWhykSw3M7WrUhXYcd9sDemYfaM+qBUdCA+5jUndAtU7BkrU8CW6ZtXwXPDm4VV//R3lhAd
+Vd2y19v2zQO2+KWr27Hxm2qCi93u1QGijhQmMiV/Kvg+wC01VXNxAg6cWTZAf5H1r8RcxDLsUUT
soopwMpjm4ZtOB7tZUcs9M4Ndk0kfkIe820CHojxQ3kng6v2LtAUir0CxyOPLtXx8yd7VFfE3Gng
bxd7CTk1xGJvfgIl/AKvH3bd9k3HsCLIeQdi2jn76zTw3LBGxGnRcdRpGRLkTNPRYWAdEwTN3nqp
QOGoaptvvtlrBrrB0UYe1EhYEvkK0u/b/PgUdK1Pb3ckggRmILG7GeyCup3CwbXZJrxgKUEJoKLt
WdpbW7bWxexhKVTTb5PzLfZlZxMbEpv4CVgsE7VWCIDQeAAGCqMnOinEftBcWkS89acu84W620Mt
9iBgyK3+R2AGSWDpTwCI+QjfdNI/RYq03DACTlbjZjdAt+viquJfY9BQoUYMqzNRGnUwn/sdpbVo
oT+mbajETJSvdmJ+9YOIooPtyC5vEemOEzYiellrxKtF3Zdzv1G+tYRr3dtfgD6hE2OETb7UXAaV
BfBl5r8iFC+TVN8mR47gIOZJayD6ghtpi6xL8WQ5StP8e2uE0eQOtG+MXB56N+yUrNWeu/wkaTit
JHlQVhySOC/+UaszxaoC0RQomLG3xQTxDNm2gci8XMpnGQk6cJuqDFemHM5id1AFr20EPUMnJIgy
nnh2kz50MyNfKDUUhYMX1DmrxczU8iUJSfPDbmqumS6Ih+iWPjHtLoOhUmEusnBxz1dozgi8mCWU
IaUbJORnq+HIXBznjUoDupksRlIhL46I0FKSTHiTTgzV/Taq4Tlhnrpm2MCkj8Y+SDzpfAsBhO96
1Yd1o9i9vns7ZXjwuZAxwoNrLOkenIf7xrqRsfFIlNw0NHOxr27dzqLtq0K089n0WhgSj39hblbN
6stPob8LBDwUDJCwlWA5ak0BTOCCl7SAzmggVpKLz+xE/g9hE/6p4LDmlhQudtcVGxW2MKko3+2i
cbyg/6h9+SNUqmCU6TZqY/dNSbVq0m8RqoVBZKuQ6qmQ8OMpiIo98utX4d6fC41eQg4AiTQzqhZF
In6dc5C/IQj4xB66rkLzfTs2XoEAwsyw2AaIh+0C2Cq2fUAeWRUQMmZT45IuESFT1JwRjEDwsJPx
Cojxg5uw+GxWGCfBfuT0rWmPNUxc7FRPep7LbTie9B1u5jKLY56AjDwbVLyVCzD7XqOde0GtFXrg
VJpWsC5Vw3eXtYZ3v3yCDX4gOyXu05KhOcs5Gn9wvqqDzfOyCr9k77xtiDflpSPLgK6XQArZhr1s
5N0I8F+fc1Qxj9OcwNIXicGJ0OcjLaymo9pNbboHJ7V5/JW3qIXqW6Tghym5OHBA4CBnzgJVw8zI
yAcAS9EiXhwc2bQ1zw4Od1ll2JM+SAN87loCfCbEMCarAlZnmI5DqmJ07XG39Pi2nX48MkoCrkKX
ICIql/KssKNJbTp1qnlfHstj/Xyz40fQbuOhX0OWVhDSHUVyLt7vGGQGdow8EmUKtY4qxtPBds4C
FM3vjG13NPaAqGtz2iMamEky8mKWWdOSyH7j9OdjhEKe/JFsEWFSI6AHipK8+vM0fG0gvEx9asmW
mnpoBFkQNSWyhLTIM3I0ik4rBhiCxZcFz59KEfXDEXaJjLsK4n3YlxTbLpIhMsx2kfES/PcMgfcp
vMuxptIqXJhf/INN+lLoK5T1vM2spdXGEbgZ8qfJWRp5B1aaAHonX4HWcyS3XsL7mSLmXycvxnjq
uOa/wYSZqLivZPCrZlhO2r9pk1DFViy6e8g1oSQDsaweWt45bVnvakThKuXOb4J0d9IaDHltRPsu
8yiVrsvHn+IFwo8ws464qHTNKgPR9RIUdGe6IqrCLHsUeWxaQGqJe10J/TiQc+MNub0anz+JtnSl
5plfPH0Bxa94Js17TpIQYK22aU688QUsMcLNn+N0X/um/gs8HAaLRh3LoiNWUleaaxPONdPA0Sip
fvE1j2pni7Qig030RRaq+nSAvCxObqn7t88QIKGmJ2gTXTDNMarC7skBloE64BULt+knLG3CTovm
Y3mTaxrI+3bMuVRs8oujkJWrIFKhM95RObmrx7VCGw/ZW6hT7H0LiqW8pN9SJvhle4RBEJYMXL+i
5M5m7+nK886bCpLuv+Z8rqlfUaGcHV/LOB0dNYnjkSL3BsW/3MLjLcGASbcS+LP3oY0gWaNWgvpN
sZhkU9wqjb1doNSUsahPSnOklCEt9IX3N6pX53N2Qd+3mouhWcA/GxE6dcu90T4Nv1TSShZH3VX9
pYr0jcT2q5V7Glu6Ke67dH0ISbqxRQO8oqgsY2jFwRhcChwYVieCUbys20jaW1lxWm30m7t2VmRt
sEoe/sb7J9dm1PiIizRP+Jjwnogn+HbvUjgJj1OFlX9pY3oFQDdiQExW4/T+oRIW6vwLPIgH4lzJ
0XEKHgVXEoZ0p/ReE+MMPdV380nR5iZ0ff73LC5YP/wXtA4o90J+/clpXj+8g3FysWwRs1HPvG2a
rSzOVw2k8U88gXs5wMCpuNLEa8S2UcsfS/mowqbFH0RBYFT5RKS8kpWtL18B91V43PG7MDggH313
sBsAKRR1w4oG0XR4kJ2GbC49Ujoh7Pv7EU86Yaw/p1QNx7I9WJdxvkz6eK1Hy44s5kdykGCL2yXt
gTDREn4nge5vicp1/prR5s84iHGmCLSiFcJQHoAq2CxBLRx1kh1pSzYabNnlRjTtr3vYP3tOrDzs
nsNpRpNzL10D1L25SQR8dvGK8k+HlZQy3sbnZ2zL5aHmHDT527XzO2lGP8oKxXztRS2ORuEWKPhD
5hFKnx2WOolWeGPlV/8XS4KRuUNhUwLEKHh4hvAGjIwhfKXQkpJXkYJaMd/6lPfQXwR6FSYUk5Gr
CfzvVw+IbgTRzlcMvavDBOzW3alODNNl2p6yeES0vcGWdAdFQS9s/rlHtIxCYdjziI//G4HET/kt
4FC8PYWrq+p5vvTy7cwsZEmY8LLMJ0FST/KGJvZrCUtruI7ePgMo1sS/yjrrnoRyjEBnFelQ/HS6
cUBsVz44pgpFcb9dsFrQfL1S3vWoNdG0XDmhmsyD05EVZKtjs407bn+70Wy/pmyxwz5+/mJMZ28v
2RuZGqedXnvSfVepiU0HcahmeVwBcRx/VxF/BhptS1XNXKXz+eGX8zN0k8x1aSTAyzcEw/uGshvk
X0itjtklzZZssBD5Xwnt7IZXt0kH+POKKdzYu6lGRDDFhXhkS0X/qSH5/dRbjCCRJ/YMTuzht0W+
YIYNNb9JkYeJUayLlBLLVGQpwoXeTv93ZIbIwNtv3fpGXOo/6p1IZMerpieTaBq8/fV0EVaGCD8t
99KslrXpJQyHWkPBmeDd/inaWeJjEhzVoF1Ew6ivm/36MoER3umL0bBlCSAMSXfxtT+QsbCp+2k1
X7R3yokzRm6vHktMNpp0sz3XbKb2MPQeuEIcVhbsTSyVTkmSY9jbKnbNnxEzBEzcN49WUVGJO3yh
MYF3aNdGuLmaOwLlIrXH6evfo6jjfpPtrBaJC4Ma6J3PaF2kFa6Wva5J/iEqi+t16OG34T1f2T7z
AK5XcUWUU9+ialtY4YedmMBYKc7049ncqKmaSLrieBUCG5B41IaU9o/QBxiPwWm8y/QbYKTEWRCL
sIRtbNRezEGuCBnivmLTHYeXLSl/8Axpc2J5UDP73P9cBaHNHALxXrsrEvMQb0RpebwxHBcrikyD
EpwktrMcbDt5BnCiRgDFXmlw8+HzRDWXwvn7vMQI1i1VjvU3CMMFo7kQ6GpHAH0m3ykQQ/mWy+G2
WEDor6tLaSF0W3Gdj3VH+lcVeKxIBUVLRBfzo+G8WdG+O4nUYyqO7uCPMjWLkxTipBAg9QWQHnGn
Qriw3cKtuVxSqo1cT5D3MUJKxxxOBz0+9kBU7Aq0QkuLHJCLkZPH70P0XTaW8p55nv8GNTncmLah
UM18uh+yFEoGvSj1mD9ZaD76jVPH30vh/M6nMYgw+94ZxKbfTPrfb555stEBawG4zV/eCPLr5Vwn
2+1HSB4zT/w5hBlhzmlcUdv1iBDEbfjXTvHriZGxmulRi/HGWQV7wruDRMhSxQLQPCYaSlN+Beu7
lrLVfqB39Q3/yUVgZUZpgETrAcn9KgGYEugAuQaxq2j69Xm47y6tvdm66IcuOS8C6AolgxgQRwIc
CeQ9zS0jS0zfmZpidsmS3beF3/8O9+Q+sMYYKhmZHmcLNpF+/Un7+Smn7ruIG67cW7zlNqeuxX40
JXUG2PEeVfRAKxtSsxUJI/WTimZVYkXhouATSlxdVH5NiPBrboYOAwhZM2pGQRfodhqIJBI8VGqf
WOXj8J1zSRAq4X7HU/WfHl6NnBYn1sq729RTKFk5cmCHRqa/1QePQelJxHMr6SPATOoLWFUKzyTJ
zoLZNLxvSLV9p0WkMKW0GMUpCEjZgkebX7k5jwyt1fbKGp/wDI0NVfcb7argESrcHj5b+JowhWoD
duOyJYe/+Yo8ju9aa/2cHrtkM0hJpHFF67CSCWVkKJXe1ymWyQLpkEM480LQ0rL//jOU2LFvGQOt
r/t7pB2QoC7AeNwAm58/sVjRk1hW3SDQv2lpox5NoAIzQpykAdaz6gQzhn56hSs8T4luX8YO7FR+
ldDvsnKAKLIJ4ECLkdNp5oJoN9hfUDISx20wKSIqQdjDqfXeNJkw7zpo9mx98YJ5EpS5vPZXWf8x
u4zVtMrPCCuVZlenUk5WmYsr4rzgUwRl4S7tEyCCHZ1ZnOWfuvEbXNQJrXE0EfeGBSJZF3/JlCoX
ShvI4+xj9gg9RIY44Ypk8Eq6GfJO8pIdHMpMjRw2e6FUm69SoSfaJTencU8gTNnlHyunvTyAvd7e
SF6ThVkxI+VdPzNSOlw1W6dCIyyEJslPEMkNRI1/11LIRtQFLkxR4epgK72MFITh/66LT34PUaLD
dH8GmaWJIp+wOMDdzldTNEaGo83Dj/9LJvQ6YIidlI8vu1C6QaqGAIsecMuMD4/GrYgGJlRLUemP
h8KvGA46fHHstTRfb7IvgX7QoLhO3fVr1ncLNwiXsFKvqZejPloQfASXdSy11rZTyBrpDBNiSDLL
Vag4E9K8c1rQ7yjF9kn/OrZh3JGMcbOam659XYS4QBF/kndR3goUoEBs1XAzdfWZQHTGNJtuq+3d
EfbattlsSysOVwjXESd8/7Jb9cRguFCowx4e8bMyKLT3MG9AnAa4Mp7E0PsGYBxwje75qvF0nGxT
RNGZ3zEAxJ9pVZDI35/vaGXPumH6SJVCdF9I+pSvwyaE2uYcq/AfFSt8ZNA6a9xCQcciGlQ/G3ob
t2QHTpOODY/BKvQ7VFTWiZnGXVSkLKZGhF5nNoq8IMnflaqDPYcjjRahs8qa2am7+iYanlTUAocy
fwoodlUpoj2goF0LJQhnI8pKYT2KGHl6ksgJyu9mOhxQHiXk8SxsFJUmI7xoW3LGhnqdOp4ZThjB
vpA6xEtN0tcW/5eUFqUzReB7pwYXS79C8TJDaHiuU2BfrbzUQRONjDa2cpH3TNKes9rNUVMk/UQi
Flc/ZQYyZ9iWdU25Xr9ckvg2qCXlVfIf9oBF0N6IlXdWaV+wnPh2jsKfJVV+LmXG0G6PA2ZKvSA4
S1frjlb9zzuyWvo6l2tx1jy0MhTJlUnq2OKfS5jOskV/BfQ8soswxpumRvEKD2iZIJPlehPPtf9+
xGZG2NHaZhiWicZ7YDVd5N2TamV5fdxa6orGgqAynXD9lC6wMWLVbvfi91C+mOu02xaDJ0z+lsCn
m4pHHOseFrslqEp8UE9UXc+nchI5zWFVm8ajWLAIRnDZdQ4HJrRT1Ge9RGt5xxA8zSThYduSx6wO
X/A7yTASn13ookgc0rsPnh3ufZD1wIox1YXVvwkU7DWZFr8W0FBsUtyrRT8W8tw/88KdL20LGSnd
5su+ouzSPQOuNiIQVc9SKgEHlCJmQQE04+hRyi1UVjWEN9GldQJ7Zt5MpfesG6WdG/QD8oTjbUMK
x76+biyTj3XC47f/0DT13359DSP6vH+H/zpntSKimrsALrNhpNkuM37V8JhQG7scPErp+Wk2GFK6
ROamqGJZCp62DzWGGKt+MTu0ahT9/HBBUFalUAyl7Y6znaDPyAVcLuz7L7yhbUoODOscmJI9igCK
S5c3cyPkffwqiM6WY4vdg1LXUKW8AADEa7Ilb6YOX7snTJGRikgqnnIOL+Wm1ttVRMKHLeG/kScj
mYjNi7Xmukq3BA0CdVcTWdZvaVN+Z344TWO/Hs3422o9Aiqyth+htPXsSYUdXlTUFEEwKOqWxIQ8
ah/iRmkks7anvCOl2uc/1oaJnJuP+AD868scjbo1q8xnOreVw1HMQJaYeKkjMqWt+Up4ua2MMaAm
B4PyX8xeZQee5y4kSTBh6D6EayQeGyEP7o6+FZcOxl7if8VNlqmwREXYIGBNrxOVR/zJis7zNFBc
RXfP5YjdYePuGA26a/RYk11qkLPup4pP/3i5GgWp6HeE7Yrp82zGraRz2H53KNfva1pLtqBJM3hP
lyTnLlEy7BsHu0o63jlk4xVzo7E71+pTebzS6dmbEYmNPVoaot6ATYq6qc7GKqrO/Yz8uxyoE1Lo
qVQjEHoBbyVG9QTIoSdU6c24sln16DhNqLmr9oxF+XxF6Ekv9LabQrB+lhgXpab1dLg0OoxZEetC
A6+DmEms9yKIBt86XBmymqEMp8jB1ViRqMsIVX5Utb9lIllLIYfvZvLS+kllYhc2DLMuIZRxtvJx
YNHr2ztJVOIz8HOB2cAJqpJilG/7eSmKlwesaM9ow7i1PSogGy3mdkWPvSLg7WL8HWQvXh+S558a
vsgua0xFdLyp2reUMGQFYdiWs1pSSjS+HEB/V1Ok8PX2mmL0pUXMNjmJ8f8+MbWrzYtpf//bTEr3
h4HdOeZ54LGZ7xXroi8J8y0kp2l9PGbK7UkEiwqbjufry2WzjBfxG2QW8L9WKngcqGy5gOpvs/r7
s+7Jo5G6eX7OTphUNstZiN531lr+jr3T5yduhdj86+zu/SwZSMRZBRDLlklsJ2pJtLbJJ2iVb/iv
deszkgtBqGmYX9RFYo/EwWjNMtjpp9GC/4+UMaScpAOkE9h6rlzeGymzVl/z+t4wc3z8NQMnvr/4
MZsTwC0OVoYWl65GGkJSk31whsrTVgqoGkcyv+M1zNS2srxjprbBiFRuM/BdHc6JRJTFTf8qpj4J
piVKRBwj4L12G83+QV/SD40y2MY3DSX+a+6Io2ENoG7BvkmDsDHEh5Nls16rCtR5uxfanr99eZ0I
JB6ewXUdnTapbqxa9Om0pASG7ErPuz8GsVAlI9sf5nuGivycMr4sGCymcI8ZkGX1UCPTkzVp2YJ1
uuf/77qQ8rGh+QDYM/Bls8hImaaPN6ljPz/+kNkTluBu9ozRzq9OKA+j7SL31iwrbFukmFLzcXrG
ETB4RgzzMr/qpEoG2eh9L0Vui9zMJNxwsms3v/JOSmWgsvcpuBuaNBrkqfEobPoI3vBNsW6atkoQ
Djt72IfleuYGy3RWHreyIZRe/KoZrJsh6F4Mo7t8oKfkV74Z2cM2zvoV1N6aedSBZA6e3LYE4OS0
k/nDWnplc3k9bvQC47z7MUZS0KZ+l61uo6JJhYS4/Ix0GODbFLElwz5bOQxD6a+b+4z8NvtZkeSu
aVCF4wNVQQ1OyZkGV3HZBkJI2pcEgBD7/kn2vsy7DYbR0huaLI6CsQqyCaJMefSPT/unTvwMEz5/
rlgsrlQlPtCjxwg54wQKG/8u3/X4yrEUfWOAy6sgQ552uhGTHdGjrBwWYvs8CpXrel2oe/TAvHay
1K+VSlL4mOotnw636Irb6+YRpH3V3madbeClEbzGXSUi+4BSeCzxLpJwfTtvwGo3A8Qu6fm4Tsn1
rqz1vyQqOrJEndzwRQ36VqNj5Sm3Sbu1G+eAGX1Y/H1wxq91tpx99uWWVHRlRAlvMy3z/BlUSnVk
WO1Ec6hbuwofvZ343w7sOvyeMcageBlNK/5UuMA5RYwVdK/APDhoHyGniHvhKaRJnUNfZ0P5hnmD
0dtgWmG13UfwwV253Ke+Fd7oYmLFw/WUrdoqqHEwiL0niI7qrFFISdzm3O2FgMctTGIn0PyD2UEk
LDagdz0GFOQE8mLXfFwUEf4E2zE6ndES4ajM+4l08rTidGVWkCNOzWGhr76Zzg0/GrF3+Nt0CqK7
dpzR1jzgB72zBp9oP2eHu+gnQTNibWxyQWCv4T+AwAIGrnfpU4KkTDr1CVTCtnQCaP9GJUut3t3a
a3VxT7A3hfHXkeb2njuSEKVyrhymUq9ZQz7ZqISpBops1GHUqlEXufCDvNggIrCbDJ6XWFQ3dmpe
A+Ln6+3ZYzYvSjIWwIsxsPygbAroLwpCNP9nqWM9Yr3mEafkRdRf6cCdKVNZ34v7oKv82c4SGP6G
JCmdEybRClXvyhTFdCaBvw/0wCKfInT9jBmlhNTiaq1H3cogp6CEzZPqvUeHhcoGOeCeBxNYM0FG
UILxS2rVRl3CbaGsCKd+UOlAo/R4BddDcdAPw/mFx1Iqv1O4iLMh6WJFkhZn/1sRBm3NDqqX3bNu
nVBBYQcNWNvDdOJPfs/7cj6shi+y4mH7weLarPeoDh4OFyBCO+4NLXHV+Cl9e+DzZbR0iFS3DXoF
7Elimm54D4mpQHZrg2kJ52C9oVC+fFjfOgm8w/U/DQzp+350gAzN2Ma5Ptw46CgFnRpjfkPhqqUs
YCVQs8hwOSiIKUO4FoZ6Ljg+Ctsw1kgy8jNq6vz5gtYpUzuvdcMG7mRifIO25BI27woU3I6gCwbS
7EmkNUbcRTqHutYbX4egKeoh0C9xrrLvc7h1puWqnarddwJe1GKQ5AtY1z3i2CgIp3MU6M8XaBKl
jf1VxYrDuiDZ5la6lldI7q2YZQijo837IBHuFkUbq+y8ZuBrMyBtW47pCUe0cnK1VPY/3TYXNWL4
f67Tgaq9flr7URz9gQFUBDXQ5VBumJ/5UCD1rv9oZYsnGqWNcxPJAmehTq+rdESaqGnYHBUtRQFb
+ZapPW8I5FHOQOs8/U3OvmYk3jmQ4iqVaknwxOWOnCMH+JBjrcrVN5Mem3B2n2/g/4kHhQ0CP0Fn
RotkVIuR7i5t7qMRdCVepwCP+z7HqlgE4/HDFJRhKd2NHYgv+ynB9Fx1zq+sfYKgrbV5JkSCbJfT
HxFVO49ku5T9OnSyFjb/3ZooCy9XIBba/Vqei0bjoHoo65aA/FJ52bgO/Igf0Nkc5G+X3e29wUDA
Nhd0e6OVOZYQDqW9feZ/VZEhO+0RKA5Offz/Va3VjqWkwj0BUKl9qfQL/jVrCZgL0vRd8RhOrPRI
m+uM1kvCYeIW7+ao6Rzo2SNEc42uvK88mpB4zrnV02Dp3Iho4mdDHTDPh3tFTozURWqL01mWBkL/
Szyn2bOkH0qJBpEmk3b5FEVpKeTIMz4L1BQ8Ow+aDS/mHAawsSsoI9zArtxRuQAWZPEFxyc1T14W
4MXyMG/9m5BxSh4DFEDDGb27tckDbj/eCb9yB8+DD9l+FoVVmgNZ5EqCGduVMhiIs/jkEx6uvri+
oWx2HNpSseF6NPxWPApZsdP35hNxW+2TxPypNa7a9GQROJRxoIck5h9ifSZ4psj2YfV2bQpFmIer
TpFvkVI1btflORzuUseC6pB0RxXVh+A101Pkr4D+BOEBXzk26bRkicqhP17Q+hAXt9k7oG6/G1Dg
gLxU5FRDsUu6EP2Po48cm/CVpwraNvf1rgmvBzm73/7g+uwSMlP9whD+DtZLt8DhxlN6z1izpqde
ouNcthOUoNbQmkf2eD5ryXmAOjoqszWzcO3TYqw89xCSu5s8UfA6cqHRJKbP3v2pz/WctSe0Q+t0
IZq09I6/3JsP/wSm1ZWBUk3DsvQvpRzkfBRd/U3M0JzpLHCo72qiCNZHxuqKoIdpVE9hBzTh/vCh
fjT8/tdw9F9dtV3w5s35t0dCXS2T1s5eYVkAxedIcuxvMKW992VyGRRbcxJVLoRK7R2e0Pl7Ky2I
Q4Qt6ICs5yp6jUNYxQ4ydhzS82pqf6R01Cu2FZMAoMD36BiVBJ5oLqKulJICOns9BaaWUfPqav48
AEqzPsJyDGrnLRkDkpeqwN7YrTL3uYA5uPGnMLoujKKVVy0zJJ1g9eEQ0ycmNvTJNfvaUki1hWlC
SRM6zVcDIGORIrbi3S9Aypk5qtgwBV1T5MQAjhgvVzyM8OURivCEzP7l6jM3UEpZkG5/BLV+BwWA
hNXFifM7ywf+7yR7KDSYXx93DKsJ5ow0w3HeG3HCSM+SW30fGDRztvYfyncLAL2WlwWASaZGtODb
q6yaJ8SSMfAdT/XBbDSDZp3VgT6ATgBp0JuGsYJPgIjNNE3OdPGKVGulXVFCWXbFYg86PGuGXC/D
w2EYUX12eiAInoBS7pwMd6qA3Zd/O3CSqaRCvLs2QAh19Z28mva/7DMMDEyE8k9oTjgeAGfxjFNV
tl/FP+orcqf7bxfSkc4TY++Qocdv85tsVWQgEdLqtliXHNABUHU3QZMWe/U88JKwZAXxTOGhveZe
r2YKz50SSvNQmwzRxSz1q7Fx8y5X49CYYcwrWLKMvg1YOzWRUtJGQW1DLmWfCmhTY7Jhhb+ZKDnj
9b+R0B8ZOD9ov9J8/OlptTqgUFtNyKhauZ5EtAk5xjbZO3BEh5d4z6u/0PJngKDU9bxUlg2c2yBs
vQkJx/Bfh0fZ81WOjvWluae7TCK4evLtsod9y36C+JWgEPXMoGuonz5kjjYKhG8bAmoaEy0vcSRF
sfYNFR6DAI4M8ba0GXpfnvVqR+HmiEcu5Dg89QU5WjnsMG6sc1Ht/W//KWDTrCKoG/kZoaW2x0jG
6SHXf/9+Wk2CRHRu8OHuXos/h51lvSoxy7Roi/EopCdcSY7Ar6drMh+p28QdXV1ikWAx7+yMGEZW
F/r0/NeoUZoidedKCL5OKOEmm+UJH7P8XPBu42xOxk3XjYytih7pfLKk8P4F5PGbkyoV/rtSTkn8
unBEaVxNED1ZXbQRka1DPY42iZnRz3Vo+pdyVyxuVhqc011hPf4z1VePA5wdEcSpzVcPqS8aD4vy
MFKAKTkIxdwpJiQVRD5MZN97DZ/GAZdfJxRxK0AhxjanXyE6cHXo3MbLvi+RzrLx9oUcmVIZt4Kx
qN2fzXnNA69jV6DWP0j98du/2/NkaysaqPJ7Mo1sS/y+fQVzV/7q6vMtV1ycvtZXoIm5p6Vcl+3H
jFqiS7aqsmvpu9mbWBz28jf0oL/l5wIO0+3/LOxf8BpCdZ/CcZ97GV/k0xYxSY2qExQ9EKzyDtOa
JlKK9O5W8r7Oi1fQ4vshRhCBFvyxhktjA584wiIAafocDzm6V4wQviDxWEOrSXk+whYQXuH5CcOO
adlxuMGM2WHqCv7ky9yRWXWPzzCaxdlw+VZqcH8LiHlSFTe+HZjW2V/61c3T88NCY3F2N7XWsy41
bag27skyfeowbX0AhZsgPkSpTgcfkbsJyYhSJfhxEtwRcKQVN+GFD44+3MEZza8/e4d2Q9l2Wlf9
TEx5Sl/cKH4NTOsV41dXePHMuLz1D0zh94Ms/YKohKIef02V0N9kY3GuwPCczhUG3Ebpte1OFo/r
44TC+d7ijtZ7YOo/2bFeg57l+SFYjqAIDJIQom3PiHw+A3P2ztOgbB62VxB4iyVY44M9VQhAQO98
mZg789XYq6SpIfYDiRnbhCqeksMUItV4F3snJQ2w0S51QiCVejYOiFxNMyPaDaTXV+h/ATxKBikO
vr6DOKWm0xEq9cLBjpwnPPC3Tzy7CpL1qW4+sJyVhGm3XjUUSszGayJgjddtNRPIYdNB+RkjIPUk
d59ldMK8NS9l2TIav63opmyoSPJa51IW/5ALCC5otlRvdnDZD4bzJF7i6yJycuYVigjhQsIjEBFv
eqebsMfMZW6Y5+HAriWZ3uL6dMklK11TUBh1dAX34O4wwh6pPwaXv+mkfpiP7p9UMG/onn5JDKjp
/+wgJl24ZupnTmb2RRNwZlZh8AXVRNrhJFh2+uLCu2fCBCA9+IJ6fSjVEuu7q58RZqlLSpvp251V
JIkit5jd3cFC7i/LMDcbCIQHMRj9PS279Vs/XZFTc9Cw3sqXMzbipXJHwkhGq+0hkzmfbNlwZ+hX
2VK7xnTlk20EFZpBq3Cuys/WsShQUFQ1z9R0wgsajmk+56YrNPgqvQNTrk6d/EgnY6pYeNaWK420
Vta5mMHfFh6baibRWYLH1DmMfFLAftEqShYd99ioaf2ta+8IcfnqbhY+em6OiKGLCo1J2AQZ4Q18
vwTWJACjUK76A5IgEeD+XicgWbXgejZ19yQU+MfGyAvzNXWDj4vPP+fV/L4W4K8oMYxa2guONaC8
8BxXDSfF0xCt5UnvpsTxrqVT+X8Zr64gRDVYgqhfwOOz+aY5XEVs2eFOojPSOh2eIDFo9slnbnE+
ZLyE6dKlTfUKVOpBlcvaYPddQw9b6WQZRZcTsQfQEfoZB7alaMERzkHNIa2cV0XPdaMGK6udRQDu
r160IlskZkWylUUIOncok365oKPRXdkgHtw5ADPpSx+A1z4lxKvuYIftI/pJ3I+6uGWmhytAj0hy
Y3mfdAeASJetbdcmfigAukn0opy/cyycg68LaIjY2lqdoro8pHhaa0EC8pFDTF0zBVZBjA6qg35B
/VZ9URMyklu5Ca7er7r4EaHKyLYmnr9q24kNYYVlL7n0JXm5R1qyw1pVfVnFf4azUQF9r9BEuBT5
nfvLfDoPV1m4glBfM5HZFsb9+qSoua1uwMs/DpArungO3qrlBEo4Afp+hjpkwUzeAGQvE7ypLLV5
dzfQxcwZTTIMXc4z1FNaoyerJi/4SGusMSLwwbVKEMyHGoVVP8lUsImmrps07NVIzn2Gi4RUm9Ee
23ibT9VhPjJKIlvuMlZN0yYTj6HNqL8UkPngG5Mvh0wiq8w1odMRvQ70OMX7wGQnNVnZF/4VPdFb
Hu8QONUP9gryei4x+30+CJV4teHc942ag/NGkll+hEFUTH8iE/ZstcE4uBm/kWlJuH3Gl+wIcZc8
sN6Bbm9YsC1Y8yYWL/Jci8nw0uZHPF9L7srrYpyL6AtJG9iucMfrYL5unyNUZj8voVDhz05pHrPS
LVJ3slW63OUOT3kyNfwCPwuuSnJPDoWbl+bNZ5PggUkdn18YKVxtklCU8he/YZq7T5y+kJmmcPUk
SGzbrhfQtBAUZgxMDqOvAMfXVKtmhlJuvPcnLWCD0kWG4f76b8rj/pVpsXnAKT0xvOcZLJIPyfgf
NFZ0nJP9Pr/CYrQGhavLVqblNk6u8TTwoLg4hNaxjUgBCQGxU5XHv1bYgBvbhqiFg1Kmf0adEM2e
cVi20RXxkybCvT7QYYuGxWL/9IvaJSFOBsYv08qO5sXJ+vDZROwyPb/W5TzH0mw2cZI4Rz+Ko4M8
wqF/1JitRJil2pX5XUFADzBmM6vUdfj1WfMl0GWkve6gKFHXIQe27KB+wcx/RSDGeXtWEC1bSbcf
ME4gLdELjrr9608yOCdqLynRxJATmZJb3iTYR5fdDAiW/0jsNXmAO3ZxK+rBpltTB2Y7nobHgELQ
g0WHMZyM7LK2fTsj0MTZS4aoVN1oVJP8rtDDVIrdQ4w2WVu9wDBFTNdh0qwP0asDyUidUXYI2kOL
FRbENNdsKttHshmarYbqfZuoQ4+b0+VtqGbbCwiKU10moirBeZ7Aowh5CYB7TBIVgM/4RvZptZS5
z0BeHMmhUbLw10QQ/KHtj7wQUzZsY6YsJ/2wrFUaTEPCAw0XALbSc60PpnBOoZnQX2ZTpOdydB4m
TMBoSQlRvfv0g646QvOdnJVC1RXd4daRyH3kr0jzJ2wnw94I0z1Tjc+x4bKNzRmmfBc4AV8fNC8g
Jlj4inq4wVH+Y5O3MdCpb1h5r2gq+CI3BnOxixiltkN+QD2xTET42M59myj2+zbzhm4i6P+47ymW
Kr1Akq1k2hueUhSe5Lo1RZKcDhle9F+MJ83iX2MFZUVmKvTj6Ig84Qq55TOy1QfFzNfyfxtjuyO0
wG3wN/aMZ+w3e1ixG1BpSILkvYh9CTg+4jOFhr01s4V69GVNN4N7eRPeTBtkg3lNo8xNRx/x+Wko
AYdxMiiAjGjcywp//1NC53Kf0jqSpti7dWI72IP3PFp3TEGPf8toX5WTuL0Ft+zApg7E5ZgM00b4
LAqwbDaWC5YVRxfLD/VOk0Pd+00LedBxPha/YkgvuFTQ+FjMqeMFWR5RzuZFd207NiP6glwBO4LA
+dMs1Om4MUdyue2uuotss+8t2ur38pIPdH2mwBZLail6QrDOWUGLHGqGaOXbMJggawcxtK/Q31Bz
+OQKs9O/dnk6J38kzJB7V1tLfPUsAqgwzSd+YLAWt9CBW3CKG/gZn5t/YYEgpsR6BzDaFQdNZOg/
GwZxP0AWwX4rFedaOeBpxMMioQSk3tJNY2Yo4jQl+gGXXUW+315nJbSsR45Z2oNA5V47Oz3gqFEj
gaVZefr6jsWU1fCK166nZCH5z7BY8yQZ0Y7SU+qF08i543I40BlrKwOOa0LdZxtaQelhOglba1o3
xBqwssR5jPuWOYHGxFKCQIeQ4PzaJutHKxgQFFGyfxvMAVB/wNX6t9mB3aujKB1u4HTBz5nBvdE8
77T+dDynMXtEiEVbQgM0oaulF2qkiB9GSLvh7gIMm0KYFXN8trSRD8j2xn/tG5j8X+u9OGGVaNUN
3tb8ghEJflj9nnu6aiSS1k3BaWfKb1/1dF9rKzZUdvKsSjOsL0UhHbLJ+Kgumv/o31BzUlG5gjQf
dHIuJ3RTJFTns6a28CYnZsj3M51ZL7BfXcg7aH7YvDKTfKdhtzVHL9t3KppebQA0zip9l9x9nDBZ
JDQ0dWg9MsOZa2WXT9yagrSrHr0jjmdjUXcXJdCx6jV7tduKcEPwTpOB69yWprGctxVDPfwzARVh
YWCu1FI1mqCAJYx5mnN+xYegVYtaHbf1NkQik/arg4XBvL2yU+AVXMrnro06cqMrEgNiZEmtZH10
MmyGNcb9qho7T5d+fId+9FDmShfRK/ZY8XvTMxH8+WnDOmOsoqBhWn0YJYbbD8DO5SghL7sZssXy
1f5b8waWOSzJhAgx3wC51LiD98n2kZuKeKeNrqzS8D17A4tzcJXoqMViLAH3Ap0y2zHwWQO3xUXu
FTTIiCgDUkA16zJDfp2+2ZAtxjtsf9c/CjrjYJip9xlPRY/NfcxFuyDCBQ29QyXKtri5MGo/B8F9
hqdWyjp+3VvR8koemAiGN2ea7uEbpJi0dKMEFUvQ3YWDxOR6bv0qHJhgPySaC1wcuIkcn37j7ANx
OuwUHn5OJds1e2oo6sOBvEEaL1dGFLVhQLnaFvA16TOxfUZwPANJBYFTYEPLFIKaFlEyiCpiyKB0
0wTItyq6sMbE6YpoYqRrOxYMZ9b4PBtKryRekQXtpdfxZyQKsegyVeuJ1f+TsR2l37Q66YPELh8X
moYPpxPMY6Jmal5Uz7FyvEvBq22U9kYl10Pu5sBfV3mdq1mtDxHWyFT8cF+plYFl/9sAuTQhvIQP
p/CwQW+UF3jC8doUd283uWdp7PEaC8nH1WS7LCRz07CRCDoaXMmQP524sO9bxPLqP+qjsoGdeAt8
5hptViX3gxb9zDBcv+s5ng4b3K0/xAeyTgSaES9d1Y4KXwg6i0ZgjpPEWom8gNvzxw+7Uz/ERzo6
RsODZtMtPbI8TWgtcOlD6usFkOLmAbvKhby4my8NZrJOSkNrClJLqM1KptY6Hq2q4y2kGL8MWuN6
27fujbyLPb7lb1tHe+Lm7zBWSq5taxwVAi2JAaFlxWOP/d+eT8qxVT1YXVsxYNrXM9xWtMm2gbGV
UsGmTSzeMsTi+LV3MwxU4pL/W3YhHbf1B8/VW8QtZrmD58QsxQjs+6Ard3e0Cf9pAvmyhGcP5pXL
Yia/2YkNB6CsrA5YKbY3mHun+PF90fY+6CFMEuAv2CqHnGDkJdDE50Ap/XwUneOKCExbqRP6tblQ
LV7dZIGVvO3srIY+LYsoM3tBpIXNN+dA5lKb16rdbbFjVyRgKCFdaHFSBdA6mhzFk/KwV8o6Qf2D
/HzC0Qj5n0p12dojRm1118Ai9huRQTi4UfY98gq0EVQ8nhQUUNwLR2F6vFvbYiCPBX/jCKQ2ezrn
Ur7mTbK0LIkPZpR42JztPpiNcw8upt0M6ULn+L+GrP3qfa94YI2UXYBiqJXiIsubicjp9B9rJ1//
eSnB6KT3a2qrahnVgIeNpAG0KelctaQfa8EEJcbsih86TG2LaYLLefOqPyFQSq1oOwtSWFJQmyU+
C8z7ji0olCn0gImaStLDZJhFP/BuT3WbODFQ8/896zbtfNvjuMh3H80TwhtLCrPSsuB12Ryii5Fz
f7yh+QQu8BFseuGUruVBpG/Lm3zdcPCD6c1pW/iwk1kOC3NH3nDMkdCUoA/QlkPwRQf79nnrkygK
g+P+5QuoNdcIhoFN36MTyfPA2ttHWL0S56nOb0s7hFvTpxoGnWSBn7m/zEdz2BTPjB0dvhMQ/kTa
698W8c4SSmu/ki3RrCbxR4snjTKq6vr/7zqUydrW+7uFJfFPHUrDmrMWhQqDQ4Bdci00QijqFK4m
+lxJ3RqEtDmo9LmIcoif7+2N+HuZkSkfOD7Gnq55EftqXsI=
`protect end_protected
| bsd-2-clause | cabef40ee9e60ac307018bba4c1daef8 | 0.939799 | 1.837366 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/iobuf_tech.vhd | 1 | 1,644 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual IO buffer.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity iobuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end;
architecture rtl of iobuf_tech is
component iobuf_inferred is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
component iobuf_virtex6 is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
component iobuf_micron180 is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
begin
inf0 : if generic_tech = inferred generate
bufinf : iobuf_inferred port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
xv6 : if generic_tech = virtex6 or generic_tech = kintex7 or generic_tech = zynq7000 generate
bufv6 : iobuf_virtex6 port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
m180 : if generic_tech = mikron180 generate
bufm : iobuf_micron180 port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
end;
| apache-2.0 | aa009d06c20147dd03acd6d7b867be2d | 0.511557 | 3.566161 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_9P6_50MHZ_SCH/NIB2_7SEG.vhd | 6 | 4,367 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
Port ( NIB0 : in std_logic_vector(7 downto 0); -- Nibble Ziffer 0
NIB1 : in std_logic_vector(7 downto 0); -- Nibble Ziffer 1
CLK_DISPL : in std_logic; -- Umschaltfrequenz empfohlen: 1 kHz
ZI0 : out std_logic; -- 1: Ziffer 0 soll leuchten
ZI1 : out std_logic; -- 1: Ziffer 1 soll leuchten
ZI2 : out std_logic; -- 1: Ziffer 2 soll leuchten
ZI3 : out std_logic; -- 1: Ziffer 3 soll leuchten
BA : out std_logic; -- 0: Segment A soll leuchten
BB : out std_logic; -- 0: Segment B soll leuchten
BC : out std_logic; -- 0: Segment C soll leuchten
BD : out std_logic; -- 0: Segment D soll leuchten
BE : out std_logic; -- 0: Segment E soll leuchten
BF : out std_logic; -- 0: Segment F soll leuchten
BG : out std_logic); -- 0: Segment G soll leuchten
end NIB2_7SEG_SRC;
architecture Behavioral of NIB2_7SEG_SRC is
signal COUNTER : std_logic;
signal NIB_ANZ : std_logic_vector(7 downto 0);
begin
process(CLK_DISPL, NIB1, NIB0, NIB_ANZ, COUNTER)
begin
If (CLK_DISPL'event and CLK_DISPL = '1')
then
IF COUNTER = '0'
then COUNTER <= '1';
else COUNTER <= '0';
end if;
end if;
case COUNTER is
when '0' => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '1';
ZI3 <= '0';
NIB_ANZ <= NIB0;
when '1' => ZI0 <= '0';
ZI1 <= '1';
ZI2 <= '0';
ZI3 <= '1';
NIB_ANZ <= NIB1;
when others => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '1';
ZI3 <= '0';
NIB_ANZ <= NIB0;
end case;
case NIB_ANZ is
when "00000000" => BG <= '1'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --00
when "00000001" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --01
when "00000010" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '0'; BA <= '0'; --02
when "00000011" => BG <= '0'; BF <= '1'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --03
when "00000100" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --04
when "00000101" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --05
when "00000110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --06
when "00000111" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --07
when "00001000" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --08
when "00001001" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --09
when "00001010" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --0A
when "00001011" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '1'; --0B
when "00001100" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '1'; --0C
when "00001101" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '1'; --0D
when "00001110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '0'; --0E
when "00001111" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '0'; --0F
when "00010000" => BG <= '1'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --10
when "00010001" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --11
when "00010010" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '0'; BA <= '0'; --12
when "00010011" => BG <= '0'; BF <= '1'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --13
when others => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 | 7f8fabc0ba8aecb0c5a99b5c89287220 | 0.426838 | 2.751733 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_ecc_encoder.vhd | 27 | 20,893 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Cqo+FjfIOIw/0Kghh877RN5JtWmUPj/KfIaTRt94dXWp8zshF20HfBCWrK0/KjFcQ6xaC5bYfJZ4
kTgDE7VoLA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
P76DAxdsqqBm7Dhm+Xv4UBWtxeM3n7VV0uwUkGrQnJyruFJEvMXWtTIk68wS1svCurmxJblglPTM
AUuHl8lZTHelg/xsbfqIjFFpkYurRbfQPaEBBncWEUkGXitk2MsCEJd1XKoy7X9zf5gkivM+Dtc/
HmQtcrnx7yMmBEFf0wU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
TS87/wLvg3wp8BEZbJFwjKct5crsKQKmGgle2kFCdS51Fi9lA3booRtYf7PKimLYtiDNKzFnNmDB
yS/M5Wwp3OXdwvzTqi7m8nPDGJzv9CPlgJYl97xwwfb/xlITgLx+mE3FLNjQYh1k2fW/YeWIYcJ6
dHaLGRiPpSzATplaiEnfWr4z9y5Zgw529sAAgbJqopXb1oauD9xMSn+2U51TKQlk6QzJOyaBGs0Z
cYN8i3mMrSJtz9+1CorRnx9v0S2lY1WHtTTmGGV3GXP4WDMI7lTnhoLYTdqSlyv31x9qhFidZzgn
WXAPS6oNxDavoZXEycPxfYnQwSx2gi0tzG/NZw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NpAOviX6Xvaq+L0foSrleTOrW/NGnS56aJ5rqqn2Dmt6YUNEPYGn9LoXqfbnr2nu7OxEo+FueCzR
GTO3m2J9405e67h9qARcSi/hF0VUlC6bqx3PVbV+Lg35W+tGaz80NE2OUHws+A7UXDQk1Cp7m/EC
XxMS909JUlXKjJHNQPk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
P7klUwNMTreRZK7TaA1WE7CMMEOTtEjomJfZ7pHl1XNp0UR69ZqgBrqFP7D39H55daou+YH1hnHn
RPI1HarNWCxtLMV4hOqf8NjoCFBgrnnB0U1fZ2Lr4Pjyi28WQhnjcgxXDHuFaQlXuyVOq9XUsvMJ
ssrZQdiUjtMyy3njm+Pnbmk63891Ob2bUkQGGCsGTzQYYho8qCUxVS8K3X2BjFQusmuscPspGR3O
NvboEcmhCLzlJh3n01BooLiI/MFAc4YbNKfLIovvQV4EihZ5noxjjP5wWP91DT3v8RKOECGo+vl0
XfgG1PKzgtiiXSw82pyP+WwelLF2xj1qh8+H/w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
EiX2NukX2J5+TgyRDb6FpolzAYOQ4QOKtxqTXAq5PT0QYib3mBeRnC0343Lv6mt+UF9OZEGgk+ro
aUIkVSW+1KH0UpbMBBy9Qw3S6Z1g/U7xlk4BWvlLwi9VKw9J/90WXNUROGm+ObPM/p/OxY6Lst+g
gsTV3EOAlyvLcOttsVk1HIyWd7kyGFt2iMDPrpX/InfKT4DMwmxjaT7ho8fX5wV5ETG4AlI5o3E0
tTM9tgC6UeDz5tzorurtddr1FmZMyvtbeWJMVSVbIw9eH7bpX3QLk9Eaf13Xro2SnxpOMPjM1Jhu
PzP1GJdnVjjHfrvEhFrDQ5Cgdaf4ZBF+MpO7lv+nEO0F4jrjuMJVW1VmSQ5U7ajMvrytR/ylHSzE
fC27li09v1vMjplqERNJ+l7b4vuvyzvtJWIWRS2TmySGnjN6MUhfWCSDHdZw83MS/CbRsg/Rzi2z
bwW2cY5h2t6YRwQPFGXwQEwI866VZMC9/ZksYC8p3Bf+CJJw6HVAXVjFyAqaY3lmMW/4WUfDRjuf
FTeorM4Ca+xVNlS0WUsu6cgO81EEEl4g0xk2KtTKJf6HhhUi2VbNanV9F4G+Sb3CggGfghi7yOjq
equKMUyTCx5U6mAqGkp2pg59+OQO5DA5UTwT2T/h4xB+t+3XolGenaVmgYqjB51j2O32ldcpaZIu
svKhfgUZ5gHF3ETtb3fq3C65BnieX0n+3BVZFBwSwXaH39Su8WFh/FlBSv7oAvCjEd17ov3LshYs
eV+ewy6ePobOitV6D+tNQE8zzFrNWMaLe04jFsqyE9tCpU2CdB0fDi6OQkT/r8Hkq10gZdpPA6pg
6Zs0SpeIm+IA0M2wkLZstuCg46OMTJ8MkGBxXaWKRiv20pRgMBpX9pt8x7sZv3CBTdlJIonmFo8U
+lR4fhmcgLj40rAa7Ma6bY5+gMl5T2VdUOlSAg4DA4bhg9hCj4VJAm7ECxnz2KZKUzUp94soPCnX
/sACtazlpy2rFn1jIg8oVrGbPLhuIlLhWZkslpytsbJ/fEGxXys3wYAfKDAGuNCPGSAD/knuKmfF
SwrrhDX2ln5tyeccQjVJ7vpsrEazs//z+mclW4CYdgtRUcF6aD0uLdxc4OnyR2dKaabBTpGFE+W9
kj8ZIXJin3HzWjyZfFzgYuvlvezHHQ96Ls7WXUWGXMiWhCLY9T16GwWKgH0CZP9UZj9Y6YLJ12Wi
dSdJ2Z6lx9e7vASeXySfBcphaON/PEeWFyRpqFoGTomGwWCPVcVI5aHfcZc5r+mZtE3bnnVFQ7Ch
4OP2TLaPVADu438id4xlcDst5IGz1h9B0mGScuEfLEBSWPwDhTAyLpymbZ+R4FAv+Xrgao345BF1
VJb8nOTHJ6XxX6K+a7yG7YmoZZBlobjFqINeBf5rUznufD4dvcwBcRAwqVm80DfoCSIt57FhC4Fa
vQKB0+DpXwMEss7gaJgfJMIoDRADAqCq61XEoSpIXO6B0dqiCvECTqARJ+FJKbEz1/MTuFqrBHCA
ydWTDW36HNq5Az+ekAa8tjcG49f9sd2uAjieZvzMJxqaARQGEdDiEBQioZwB3La9PbB6q+u28GZh
n9knCcgBjV0fYs0+riHOkd+t27FDn2VMgysFCbRpxQ712LH8zTmTNacoBkD05dFCKPmphx4iOyIW
wfVEppQdQRGsFKp9cK2keRDOSlozfSdP4TCk4bl49QXvShLx22CqU4n1OmlmY5CjbT78VrQ/j3jq
Dn/5pUp5FP7FthhSJNjmuLmaTZSU0lKh9xBcUblHY1MBFLj0gPABRiPC95pb674R3liUp7YqmTfd
3pIHIZijNQtofXBTyW3Bdh1+09zAV1rmtQRhmmn2LsR4LXGuHY+3ap+5G36IDmcwCCVtRpOA7t/G
NLYuiaUvAwUWmGW24jvSszCU90iqbwgAOHcZSrE9+kvkofVZa80k1SWI6phA96lh8z3LxfN3r/gH
yQFlXW7FggGdi6SevpeD6L4cc0lV8qZPkfm+EOKn68saSrfpipcyv408sMwe15T7mmByzeHq+G9b
MD8Pe596rl8CPle5b0jzuVqtAdaiZ6EB+m5VSp2akxfePgcIxg+2IwQcSQcVFQuLas+DCMzVN0dl
5bCBlCUWwPFWN6onVEwIorpJbBLhcEm9rxgIJ4LxXQUGZ8fLY9JUSip/i3g/ZOksvh8+JNRbhrJX
fc9cvgt85rQLxnGsy48Fn5Ge8q3EEetVXUI8hBuFiqKeswwoEdXtrseOOZU7CxgmkrmKDWWrujZ5
R09A9tFrWvT+uuAfUHeBfmGrx/6pmAAGA0X6SzVWQYoXcs5EoDQxalGxwz9G/y98B0M8UFGa59PD
cuTBIuvIuFI2/zNpYBaNsOuxBbnm9OJLRhAYFJeIJFdv2SghjXumYdq013JBDgg6HCzJmv3EhPgo
HqgfaMLCQqGxXWJQUp6ftwcGlqaIDnmKCLkqsrwOKdAGTanNGtUVDsg6tnbZjvmX6Okb7f+Pr6TB
UDRAV1lJe7ytokAdgoM2Qp0FCccILYBEAZ2AfJEBvK1HPv3lAgYeU7PlzWrS//GsJVuTnKlUx6Ut
h4zKQCeCsJ2xgtQMi2PA+T9Hlh6GD/TpKhI7k0gEhhkrQWGTyn4msXkWsJVU7vEBO8MtBqByL3cv
FW7tiQEPGdcJ7fZVldn50YgZQYZhxqhdJQ/dhRgcSdyD+A1W2DiHlQbr4+JjHo3IatIpJ9Gnlt38
TK4lFtqDHPRZ5vXw2hf9K5XNtcpMzpOxcCmnWZlZD/agQ23uDtpE81aUvIYLkJT5Bn4xnveWRxu3
4Sa1FgsXEin0n78gen63Pv0I5G3uZDAmrbOIgiQYi2EicMXCL3uVDLafEghhEngHlPMhIX7NPJ0M
f1TS6WHQgfckDkWCbwqcj9HwwnKg8I5ejFINSnSJJ+WLnpZpa5U9qFKyuul1JZqpvNMutu4MiG+F
+IS18j+1nKH6kjhBN3PSWSImEpe5Cs+hlghx6JHzgOIY1CBWTDdZozrPnuV3zgGV2ab649rbPpDu
D1K5dDORJrtrliYscBMTHKconE7vMKuXEwC880+fBfAy2nBn9+ZCZeHqOPkkBthen9V0MyGoxqwd
fotGe+aUUGDqGzNVg+Ix5+N+s7oEA8tJ7sgPoIiyuFqXerk1/uTSImRTEHH5M5LNEsN38veEphIp
vF8wAOXu3sbYFAVoPN+tGj8nvnIa0sORcoswYhEegVMqkQwaxJv5iopeluCq9Znfr4ZOKdgRWbvR
MLEpJGldJLYNSZxCRiGWNQmL7AlPXsOacTL3Ei9OCLmjVL4xB2tz1o66aJEej5hlvG8q3JfbIOtZ
NSSSW907oqcRqkZUK/23uQsBzDcFyD13OWQkG4YNce2dc7CGHkNcyLDjVcgk9jz7vVw5NQe9kZE3
y0XaZmtd3YtUPUV7Ry2T+RhnVAxm5a2sV2EqiF8BPMUuiv+NvFe67FrF34cZjYleAQiNS/GF52rN
w08KoaVP7xDHeLxV5+d8P4s66lDVYKsBxM1tNXlQA7pgzsTVZRDLyyl2FaGeJg2RxRmo5Wb/bKDU
D4VXxjTaNW8ZUvypDo61EMureRbTeJVabz4GrrzRnzwJoiIb+UiE8x211CjuIQv37AU1ej1ulkPO
vW+Y2vIfbeXzZXVIlHA2r/z7WPVl/Mdsn0WbX/+iPuwJ2lsKsdXCEfXteGbMBuoo5d2lk3JV+I39
J/g5hQu+R+aFmDJgPs5rNgNSWpKYUJ7fizqg25gn/QAF0q6Fu05ZTv0dVzz6UDmPJPaGi+8lRTJ2
/L7/iy61wvlSUAD++e8qFs2yxl/kXZDKGv09svb7I8QP4uPcgKYsfD7RjGk/yNvYh/oZzrc4vbQp
ggh2jYC1Q2iSXqyBGhmLzt1Z/d4HVLONYE5CGFxxbF+WXpyl5jTK6kqvwlLF3O5Puu1m2yOrB+VJ
vLGrfaj7cmBJuBLHO/OrFpw0HayacX1NIyFNSszD6tJvLBrRhN3Jo/6hzgIXuvpWtyp/iVl7THgr
d2jv3Ot06aUb2mfyf29K8Yj8ZV2esikjNaTSoULT5LbUv/XSFO/jlWXrzLj4X+rVTbl3vgI4JTJR
5Hu8CjVbAI4M+h59TF5jsNdIPwlNVxllHiaEub0NQMMfpnTt1W1C8g7Qnq765ZzL/JyhndruB7X7
RW4TJWbUYeyZhd4hydITrH2tWf0S2ru8Vz5h2O/raw/gbA0FCt1bKCxKBM5WxoWNv1Gap61YRTIb
g6CnoZ186ZIqcKAKMkAuEfSO43Mm41uZlNmWntdQtG/Q88hKyyezAMMNG4YVrXZiQ+FvmLUp/53m
sqVFUyY9ROo1YVFMhfHAs4ImMSPoDe8jnBqEXnMK1CkSqFQ6lojYhK1xsXDcbMV4p+yPANZLWVkk
jk/z7LhC8Qc40txM36Xa8BfP553uN9vDYbkqdQevVu2b2AH+YgGjDDUJGo/FfOv3U7LLg0vOVIx9
n9XTTIb8a2UbKvpoEMR/DOPDICJpUQu2DMIRCa0U+cO8eg9mr/5SBlouG3INjKyDg6BD4QbieDsY
XdaULVJwSRV0nDgCmucr3gVKCViRUmfVGYwzNBpMK57T77tZkOPM8QCCVHM+4kgW9mYR+sdR4xaN
WfYnZHIQS7iFdGRqo9J6Lq2b8C2pu8wLjnTcTF7aX8dQjaWbjnET73DCEpT5/419FUIuEp4hhaob
HRnC3QEYn6s/MklVaK9qLT+yuO2u7Aqa4F3tojlXQiVyNrip2Cnbp2SHNiPOjtF1DcWPOk39vN/k
si6qLk30iuIxqfP8SjcSnljlYxJcOBh/cYzEYA2io4UW2+sBJ1oxfuTrrKW8r2vJnKwbf671N7/6
m60gvhRlW6hBUmZmYjzCTKbh7/nYvO+hNX+E2vCap/JQsqjqKFt+WcQMdiVFTV0Qw1NPWlqAk4uM
9Jo0v7Fs4kqgs2DJQtmp8NjaXmAbZwzYkY1MYST9mguUeto0E8NggfvQ81DgTo6keeCMQmg3xF/M
HNAf1kbwQ3vqWNKDVKo8BeqaAg45zBgDsWNE0N9uMAmMH6q9/0CaU8K7Jd7JZbg5MWRQOM8QifTK
tEdqLRSFUUtTCoJ88Nvyy2oX/S7/o1mvid8ddGjoRH7QNBPehYCL6hPXXB488wMJgzrCCBHP8fSy
UQlz/uQUNrff1GFlfSA7bZyYufv6Ds+ftUYa89xeY9CYrKuLDWVhV58BTo9xxS3qGqsjtjKfLK1h
bUD1NH/tpKSFnNWp2fu7uMHzh4lRArXeQoxkqOZndEWPnMp/aHXFNAQhPscOOwFXcLlwfRv3C6Zb
mnBMVfsbJRJ+1Itg/pDLtveucpm3eZlLYXerxtrY4Cs8CLVGdPztQ2OwhLaW7MkKR2dTyyCsh0Td
2VAw6RFRsq13ii7k2aiLB5qreHeA4p1AWPda0ymNggk8dDzVQZl3ENSvXDNpUEzkAEq1pT8UII53
LvrgykDqk0KfO/7K0FFuHSJpojv0ndQ8c/H7QAomN7ajnGh6wQ6v3fBBrRVaHLn/DBoRCUQn2gq5
TuPvpda27quCS5hsUj4eA8CwgqM/4WmtH5h/oMh78tL6vJvRsjK1WfYdGok4qFlt3X6fSJw7vHvw
EsRoDCnb1eL1h5jqDDZerScZb8SMpICDY321ZxedViwPI4Dx9KOd6GcQ2v3XQzQkBQ6DvP2TV4+z
0wb96e7gfsf5IhuP+VqlTRmBJ/QEgV649Gwl6NHiBi9Wf1OhkMI4gtsI6wRSsNt4DYv97ZptDBwF
Kby3zGsNBr4DyC0kF/q6rvh/9vF8k2Fo3HQgDRlgqG3ms2EEfACkIKn7xNzpGY4DBq1ghM68b7Vk
JQu4exBmsnt683u3Hi5H7TBGKMa9fZATNOlIsUjjasjU/cO1J4fSO6CcEk72OCknmqjb3CZH1gFV
cgrTS4N7lAgRySBFi7gj79CrV0ZilHokAyJnxdB40hbfX36fbxz6MddO+NF+DgvTUdxm0R/skhIl
epAWG6eoRk7MUO9rCe9EJo9E6PSEcnJoYsCCfRz9qyj/kRem1O0FFBPu416AyWEgpvKe+fc+lyI+
ZhOQpwIkLwfBI6T2MYOohqrwNgYVUPdaGSE10dkF1+MvvjejNWK8oTSOsljEb/Dla+7VTV4KKHpP
gegFmcVzU+cHhd3V3Z8xno4GhToznN6hKDzirpPZlImVn6q4N5PiSY3GfAvepdB5SONiZ3GPailD
E5x5G6wYDdTkAfizvZnKqUTmjB0OPVeGOMIVNNOW1kZVN9ClNL9OXhmkF4e7k346UYMRyZdkbvR9
uUNSbtsDqoCe/WVLT7eOdIrRNn02l/U2vCtQMtrx1Iq4e5sP1MJJ6sT1mk+zaddRc+eA9MJ4WKxY
6ij4NNe+mJYuzhWJLmpXhdxCEdRPAbaWIZKVsRzxJISc1tKXO0eYLBvO+MUe+CHJuS2iItFukw3w
lmhkuJCy6hDY8J/Iob0pDzIdaUN2EyVAdf8I5vGzW9w033q2afVaILW55ykVkSNJ93p6SW0Swwir
R/a4d9Nux3fhsqnmgZ6XeErznu+C6/KWklP3jhZmtWdponpCeyCfTTzsCY2hoNyyzSS0J/v01/Y3
kl9iOKZPxjNAEPwIpn3Oy1H2UC4J9FGBBWq7s0a/3dn5FWs6oYYI6Yvqf5y2rb8knJZ687CHTUEd
h0aSuyoyaBLP8nAILDXn8YsymzWUrR/H08d8G9EQ2KaJIjsdArm4rmop0O/KiWqCxPS0W2zkNQbT
XSgsepjdBFTJxZJuUtcamG+l1aJBcfagj4/rFdRtbsDAnzI44ubLIxKIUJ/ziIVxi1fwyT6rBjG/
hXSaBSg3JIvNLDjv0kFRuX1kcw5VjznXn8tBK75DMvVaBtyPvq2bxaT4smCgPQluLU5bLklJs2ly
Zxzly2VMmIjoV53mQEyyL+Z50I/XXFQsxwZW/sH/oOy5fzLsTO6oWjMYHKMKNQmf/ljvo5L5j8Fe
uXL2+M0pwOKmphx48vDxC1vEbgWPg++UJcEP9BuXI9mQzbAtmbFROMPwy14rwO7asHO35TLaDfV8
q0hCk1fzn84/+RLHbJXnRHAqCy73h8TOzSrI8GHjy0zqJ8FVFvF8K9Gsiru1Q950duKYR7KU6Elu
GJWAI53l35Pegdxau6UU5TQ2ZrS3fmh9nQ1ZKtMRjDYsZtPN+Bpr6WRy0oNZrs5cePwhxf7pzwEZ
JFLzVykgOLavs6nsUrCcEL1QvuiDzPEJfdBsIwK7Ux1xJtLGTcRSsp9Dgf2XUJeHxhW7PNvhF0vQ
ZmqHvCcT1bRHuvqa24NarAVh1WE8SLJXt7VVTcMz3YlBzzoq9IZCytELPks+FjKPO760yisDunGT
cdDmAQKIpqWhsMMrfnLLxgmZ88bBcjYr6xjdvO9Br/JEvP1xteLuGYsblwkLYuhHPzyUVkKnZ88t
d377JG2xMyLuaL2wfSxSZU01+ftbwLrtJpvkC2kPdM+gp4eB0brcPI4Cv/wLNtkUVuL8V+UcnmsP
PAnlKoYuOVWSjDy9QCvQHrDgd06BmVhFLvfA0qx8IeKhWPrkqGxU492nhHxRRB6LQI1NynPDkmv6
9KbRdhBm9nz+4tTxSlZPhGPDeS2AVRRdbW89f4oppYLbVKx6JgTaMfmHyd8BSEoWDddKp34MsQDj
ubYJ0/w+yolvDwYy2t2OP7WIigRhK9yYhgCKWqBoAfTWQ1IpJdwVu9PtBScYLRTpvfaRzibNQ+Pn
wLl0Dyf61Krbzqn0M/lmJdiX1tGkGSiSj1NcJVrLLS6UDndn9brSwMQFmj4NR91t0/FfWGdMefjv
qdfxu/E9cuS1fwjguvOvLSfGQ8QJBENrC1A6qyRN9cBPdyFcWXV2hvc9ZcCi2Uv4AY8YvxDNPbGZ
CuRXNF/ELd2rUK+8/lX1lm8Ostu3898Vnor8hUfD1EZKY9wBO0N3BWIsXuLN0l8vibshBd5SdWta
9+muydnaYf5Uczx9pceUddVLr6Db2st229IERPGZrJvEnkGUAHVqaAm+EiIVzGOvnD3hxqvlvqML
5+lMDy3BZxjzbJH9WOd82/pglYvDTnO5fDu/qdN2HLAegkGHVolEgzyoMvwYcNDyQ0ryk20H2Gbq
SaI/S3Ctkoe5mpNbs24N12FYboXYQ1KK7iDgBlBsuatp/x8blFDkJv4+GeSLJweL6CL0eV+WDURZ
onOX+jjKYTc7RCn96Hv+eZIflg4tuUfA+zZAAtCHCpvAKcINm6m/1Jl/xmVauXmrqwDhxi3RNmXT
ecLn3ASOAOvlrr9/Qe2ImsfQtSgbmoCoNtckTxuTWDycQQ6IRN8ZyTt96XdN6H6VHnS7HXDNujt2
vcoNZFfa6yi6LV1t6EmRpDCD5jNgSyfJZRlZLfkxkhtwxL7lP5kmUcPNqUmpJih0TRss6mZRZtPN
kXbzxz6+/iD3d7b/S9VYw7fTsqGHi3jXtJ/i/mdVglH2ZD/iCVExRz8ABjo4uJHRMBJLgeCdi/ZD
LP2afiNk8x+mJNFEbQGbzizjn2wccFlixaYIq0kKbbCyTRgKxx3G6piJIMZTBOoGvizGl+BEZyzW
Qo7B/rcu3mhifXgbzvcdWtUYZwW01/HjcdmeW2pL+wwvlG1zBHtEHGrTzpEmjGTo7L5C19e0O0FM
VJaw5PABm8d1DmMugzTW48UQuiOW35a+zrN7xelYJTvIlORajKutvyJTShsym7V+Mg73B/JbR/dZ
eDq92YEF3ExDN1wZ6IrW+NYXNFKopg4RpVqxdcJjMUQbhzCGol4XpN29XaDZxT2FrmDLyum+eGBb
FRg/gG2IlQXEh9iuXw8tmqHe/1aoTWhlsWTfsOJWhN3rjQp10K3lNGua/PqGH8Q+FF53Hrkr0BoQ
VsnIGLS/mfjnNIpuHLKo9XzVS9Is1MFnlVPXycERJnVsN4GY+c2MhVHl65/XKn2CschStVHxaCdo
p9FqadGD7EKL2mgdj945O2OH2YhHVYvDz0KzC3KIG7euuBUk5rIrGrNsi9eNBbpseWLYfgKMmr9e
kJb6JPalDX8sbFYpAJMsu2nHWfmcN3MWviEDB6EsjlBtMGrsjCsikw2JlVu7sX/Je9aMKjW+5IKn
SPwkeZSqDHiPIkv2p7AK52I1BRSziz5N5zHRa16EtJneTDe28YM/dF4QMYSqdIY0187fJ/sQq6S7
Q7V6cSwmyIUNHnZXrLmVs0Ud/BC93/wR0dj7Trd/ZimYW96Uo+Et73OK1d7gfgGZP4nnVgNALnDL
JMGn3ph4IquGUAZLovuTxjMjEyLUKaoyLNl2lda+z+/WFbN7ZrAEmlmtfmX2BFx3Gt2W0rgL004Q
M37sgYO/rNWqxQmecIIdJ/2KKf8Mcbec0Grjd/BNZA9ASUV17qYet5oRdoQeH09cj+srQUmOv7Et
YvQ8mEkfKPWfn3RS6dxVGCDGNoso1BTyc8fRSyRJHzeJPn1XRRoRYrQouJ0gJmOEjsxIFRNm+/kO
8f/atOq1tjj0XX74rRJbU3tYiHB5d829cWolm/qIg69qRv6OGqpwOv6kDqze/jLd+XVEo5uP8uyL
tcbnYZk3ZsX58OheO9RSInWebUJeDR532fVwUEQM3o+WfpYrlE4qIcfwplTFFa/gcggz+/IDjHwg
DbPQC0yn4PGpMa5h5TN8lkUB5D2P3VT183D/tO0+EHJstmhf+hmIqHneEoTe+rmveYHMhNmSR/Qe
sPIyW1EQanfwa50FIRTIVwZ3Qg28LCIgLBd8rq8TMUBeRayDevDsmpeKB2bNhxYRyq1w0QzR6krm
g7WDr2o34aGMmkZfOuCwik+ykLxZoCvIpAZArCtae3rYmawgPqn3JvUM3q8PDZIR0JMT/76CBhsm
pdINNRyQkClN2g5XHXui5txkJWc5zF1062euIJc6Sy5FDYrdbSRMZAiMSZyQo8KPCimve2siFb5l
lT6228AAr7ojWF1ACRk9jGvl3Vyj3OKc+SvTF+OYHYm7wjylPXRyPGOF7nF1V0ksHJNLFx6/OeXN
BB9LOK34wf4VVzezVF+etdfvye5K0WZsMIVtI4RqrFelaBNHOaJb8TNRmtcIOtDXNZ3FDmf5XdZl
f/w1DvD9VdejCe9O09KKkX2EPNMhVGEz6KqcSrBTi1rhe01qBEOJI9sktloegCxb632Lhv9ftLM4
+AP5QaA58tfdobpWGYQitubVM3e9RbfqZiH86kaR8SWiV6Dtcpu7N6ynIrM1gjIwL9u/3fPu9hcN
47HA8bFIaYa7ir1ZCj+1R8yP6fGdLQQaRIywFyt4zzGvJ84afj3NeMKPu8JUsBEPYEq3wS2OHUfB
g75UiN75z+wF00GGy1hlJ6GDWRkV/UAI5Ftrif3kTdQXUfymzSbjptmKPdD1o1mNaR5tkj+/ZOFL
QrM0wdjUHW3Xv9mphJ39eaT/EgX3gu6ajrcJ+jF/Zth4/BMW3QPGv8GisRbA+fry9xdR80AurInR
WF1T3JdmmvzOfXmijSJMQLfu5017twcCZTyLfGLtO5ST8UYmXUh0hmIEo91eZrw266sZNSdQ6ihv
UQFt9tt3YX+8Fl7phRk2zQsWOJwsBjD52YAHJXzrfxVXFjltnDdbn56fiDyU1YgDHxn+cZKHS4Vd
wqbQJL2URAuXZr2KzKwv49omikSnJAuCMv/l1vos8+vLvKisYgVlloyqctLywO1saAURVjeAr79S
JjFqCz4FM4OV7dywhQW4sbiX6AaItx5SxMqUnw+6F+N0KGskEvh/fRF9PtOUag/lwNbpEEw93V3j
SHhtqAuUsV8YNJoYqWcNjjwT+NL96CXH0pHeoxFItMUXUXWa4kkbLafARY8dX48hx5wo+M4xwWFg
mikUPjkEclPdA2g6/r+JxPSMnb9MQToPzQg7ZSCEqJm6Wm0EvyqE+yQe9J6F6lbl0OwH2aEj12qA
8iU42GT1NG+kqD6aMPu+KUfUskaAsmHKvhIoFI4d8eE/ElUu90sN3/Wbp6VNn7nPSvi4tgt0G7lL
muHA8QcKFOH3Yxk+RjYGdPJmgbsBxnPXkrU3ffwoIDqMowtU5o45iuzz+RVBLHjxc0HzQkOOBuFn
zaYM/PS//rvDtdPpoFcmIURhfuYx9o5ORp/tEy8KHjJKGYT5jmwOO/HeDnxr5nWvuEePhhq5vTFj
jHHYhaCTQCbIYeoF2+WDkBhfXDXvpUffvOgaQqg41cfbrIS9j9mJASY9jHR+CPFAgqcki+6RXAZR
eCIUyA8QFjX2rs3dG9yroLFY0673f0InM5WkyFFySDp3y1Imp4WNNmiiQKH4B3OrAmlnnh9pzGOu
7hA3IsAopAze5whXyMhdpJqq2QpaEjpfQcnxeurbCwrjoX8eEbOPH2Tmyl3ZgY22Z7uLT1FBCE0t
eG6VExKlT+rH5/FuW4zcvDEbl5KHJRxzl4S5sqQpxupoPKZ5mNYtYUygDujNJhUiMQKnixtKLs/i
utpROZDyXroLUWdTPYYQMdBd8crvwJFfmMYEnyg/c3NIOzbp27DdL966EkWIC7rhbH3PPYBGuiAm
OzobNP9YEqvNbguA5hZWP/NQDx7GrXxv+TTfhyNBu+uxAa6Etu7ygiIPUFnbHcTuuu61JUY6YjTe
doNExv3mY3Pm0SEN71duhd2mhLRaiZty9M5a39dMeSPX9KJ63E5UzsABTykFFE5GZjdMk+RoKbMP
Ni2pkvpskDMWTg3MUf98IWDNUpcrYJ8lDDUHMIGsSTDjwouV9OXUsmy+027NiZAaBfFkbOTKY3LB
BvOYm8uaBqqyyshqn2FX7VfvPCn9y1uYrdhfk05goG9wZs6QiaH/3AxCKqzRaTf/s43SISZC3ySW
BwmWyTDiKnBiF4AeZ5+3bQPJEmT1ou9WE2aNokRX4UBkM0+7WDj711EblNKjxj27uIs1iGe8LD2/
z6LXlFluJF8MSEvay7SaUXSbWT+F7nOFI6ZJ6uaiJE/j8IeZ00G8kdJILDftT8tPyEGXYZ1RcfxJ
PgLdP0XMIDAwUaTZ4rXBgr5Zgv7j9SsZjLP8ZH//xy3X+sVeI2WiSRRa1qngyiytp3IeEUKE912m
6ZW9BDGI8WhFTg9sU0n4ITAqmhgUjDQQK7cRCVzdp7GEVQSGYyzTH9R0/zzPMB1xuZg/5B2dfcg1
zGjSUxJIIUSqXioKfPapaq0M+lRkO4rHGujrrH+4Nipr9ttXN7/8frs1x/4BagiafxkeWJenEdAO
xJzzxaHuIoo2BX1CJzcLLKqyP7vYvwEsbr1E+wt0XVEBMIKKsvCqksQoWgpvKBm2f7Xs5OufWb7t
OVaErrav7jx7+MuhnK1gOGigf1wZU86LfOxGABSbUC4oLS6F6HBLwi41UbiE03uzRmoZMdu7EReC
ScVwEYeZgWwcqDOCtN5zSEBZ1QHK1tMc4dvtUQwLv2pejhkHps6EWVsWxakvaOJPQe1jQyAVa6Wy
2PnG5sjgFfviieiMc06V5IWX0tCD2CFntHnoTV1M2Zc6Q0ywrK5lJnfaXFYzWxHNBhicuyHAFpia
Sb0rbmJSCwPrXYo8fMn/4IrLyGHolhqf7+hbVzQUSU5oCptoXyFQ5Lzw+wL0v4+6XuTkcXSwO/8T
RYwN2TSWMnn/EmTaMhtTAlOnVqQq9roDnqj+aSQe7Zr5fQKKBlFAxWp/mN0vY4HCAqHw7EzjfAFP
KDRZObCGPqZB+6I7quWMbLKPrxnaaJk9LVPPKt9n4G6UIth8SQl6P2dpObi7q74X4ZHbieVdMC+/
s2npN/z2X499iQO86dDKymqoXaFx9tuEIF9+Hb8lYhlidKeDHVFTrJ+Icfh3tKiTpveeFJRIIlP3
4APjIj15bg2g28yA/pwEYs2muqPmiue5FmQKSLfPwJf5JCFr+DgToXiKf4JX62/p3Ftz1Yu5f1GX
ugSlx82FEe6JbZOk1NPrKDD651NrA3B04pdlMrc8Cwniq7MbMNpoFmPwpmzrlCGx6Y3Z5XsmH4Rc
KtNGIcMZsaPFPc9oBDIVdyfQaRUNLuTLjKCI/sOzkiQeKEnDRJYdVGbMaDyMkWBXZySKOK9SB8tl
GMBGJFa3dX3X1iTPd3Rr4EeZ4VN5obqHPGTXBvzM5wEr/dBnPEZZqhUWlJjy3mqeT5nL08DQKLOP
1gMB3FEJdOGmL3A4/yYS9IufhxJIdhcwbnLUGcGP+dd0FMnVtRHRzdc+KkG5Zk1PmrMqXbdoipa4
L/mH+OLWqhlQ2VQMb6N9zxikjld36Lu+JIcyescJ+gjWqfA6TVj3fZ9AYUFvfBf/m6KsfvxTP4Ie
P+MNckAy2EX1IFRPDvmwU5NXdx6PFBQc8WNCdlcxakFqBQzyKw7Qm+PxC43nRB7W8Rge2prbU4fB
mhb4MDGNcSCEk538hPSOy1w+mT5SD1v6jMgU/E+w6pQQvbCycEHydpa/1f8ScWduKgRY/UXSAcv9
6WUr33p1qql9Uz3XIg+mxkIRVKIJ+vynaYKwgGhc7LfMbcIMJdk3JRAcsJq/XNq4UD/wRc6U2XyQ
PXNoKvMFxBrG1oac5VtajJtabeCehjvESB/AHlOqpHpnb1+9eXgcesfnDPrTOZAXNfdSFFZc6mTi
psruCLcmgk5vhmvuykAyfWWTI4NZderSMF3j0/Vtr/h+Wm3OnS1Nd1/UCGx5S2NDwTFFOUY4Jj+x
O0i8b+a8N4JYnMMrw9sgVs5wlLiFeC0E/YKOAT73W3UDsdBP76zZbfGRcRU4klVLo+A1pJgnQhvx
wME1kUD91U1MEK9yw8IP+JAAEei+qYezcNfF4WUJnqQtv1tiwxvngzU8XquxCCFW/4sQzsUKJvXi
0QtwwDWDEKyDK0L4EQtfJVxi6D0xHAqM2ZPaHOcNsRoKmCbWnnrsEMXaS2zvkozjPRr/Cf2yEnsw
JQ8IthD2h/ayoNPk1OuYY6vDsTK76iaY/XvQ6yZ1X/ctdxx6GUExqhx7We+ePg801mK4dWK6w8cP
/Xnjc06VWVbDC6+Xh2OY4/vpTd597+M1yEmREJ9RpR//PI4bEiEbpXpzQsyvZyRhQbJnvhJ03427
S98vfIqW56VKisfqVlnkD6AYEOHjtUPaK1hlU8hUteSuffeUazqCGzKGAl0Okc9CIbxf2Vw6CRCq
lzRTbvQoPAEVfO4ps5tbiGKVsQDvcDJDVyZx9XvZI2vA86ckEJjWyUCOl5cqMzeBFdhyrJylZ4En
0fOmFzoUPj+P8k+BaqVZ5ulFgPrX9TKRgeqSTBlMSzjLg1Pt+mGqm8lgityh6d/zkzn/8HtD1I2G
/NhWYHepjMBRw53hveK8A74i42eiCRxK3XXD+hQKw6izI7G725ulH5werO5yyzCk2Cd54BqWIOx8
mY2tiSh3/fW47V4VQem12ddRrKsAOxPaHgRyC5k4hbwCgkQKrJSB3u2vmwPrHqiOANpU93mur6H8
WORzgzcXPibKmoDO6vt2f91vwMBLXBpRlFrbALnZNLUVIQoBHfZfShaF6LaW+jsVZPBJDpdvFAGz
j4j43CCzLoZ+kEXE3TSbHgtg6jiuwTo2aj1rvVxgI+n5jdDWd9SnOj9zxqmDv0xhdH9DG21HKnlZ
krE+c6xKF5VmTLK6oM56sAoiTEt24FcMNkEd/zD/UVhl68ayTLGSm33wxsDPvG5btAogKj/zx2HS
f08hSYdtPDhsSBx7gjhO+HHxRP8Dh15JVrI5OoqFRXlsXzN4fuPEmqq297YqNXiCkZ547B3IIU3O
JES8Cnj2SJ/72XaRddLrtg1m2ePS1jka/+3HvNXebQmBIDeAHhIkhAvU2uprmX00v3Uls59TX8ia
MIwT99GDtYIyvmdNccrKNGzkirfLIEkxi2eKr3SCIWaBXvLy57/oZkIl0c5PvOvppwIpl5nDTnI2
5lGQEZIoMABWSs+y3SI1mS8GjIy1jCrUz4LVV2IbgPEmDjrAqRG8FFDYSBCGINvjFBJG6VyJLB1O
zrzao1U9paiyvUzRlwyJfUDFQFB/r3cvj3ifDTU7QVh+KAiGREx5vgXMKQDBs7fmwd/JWIGXaVYy
uoKYogoKwcyjFfsNaFArws5+bJmJAZRIy0dFVOuQkIhY5sQ9vyicNpJDzesOfjF80SrDphZse7RM
UfISNWhA/NmTbJXshjZ45GiytNlImEg8oZLBQ9nfotDiK77qKWSMEWmcAkfevas03++UVZrc1QtT
Hz5Ge51TJ/as16xxXAynJFGNgRegcKB21Yia6OFXNXcnXabX4kfAJQXDYwIob9C1IfYcS2qXhtLd
tvwsMxrJf4ex3jYUO9Wss3YEVdK7uiPdnGPeiamyw1TZk3lSRHEZy6VjA48aTZX/7Nkh52UvgrOA
GIRfJ/xcfA2sGnj8HUtSPNROwc5se+4mzB/4qznZ56v3HIIVqU63ZcHu/TtkF4r4MkEUsBmaaVnd
WE5cUsxQ4YJWyQXmGEW+Tn8rNqzfEX1oNACTDbtdZ7FgMA+kiyzdoyEcDyJQT33LJUmeSrgv2r8/
qdViUOBRIx3YEXL5nzb8/mYCvPFGS668wxZrjRWVCgxMfstT4CpSOmTHR2zJuq0t95stcMcMEpYO
veJlRD/XeKfrF+Ne/XkU6eadhYSM4vrF/aawKIs062nstGt2R153OCFkskM6Pr9K/wMJBZBwTMZT
DQMTB3Yy4oX/0awdn/yNqQRVGPwSc8aMC+VuhyDpmul3FpHIp3jHpnmwATLqRbW52pQ/Ezcn4Wef
4HKuUXW8a6GU58tyVkvTexKoSrazl63f54a8h5MMEXgd7w4B7Nt2ZTvvhitkm2TbgYsNovs0K6oj
50FcKyTSR3YAwVjmaAc9GXiiWxcTpkXuAepDazDRq4yMjnECzpiVzVTCK6yUI9E/pyhFYfLugouY
2dmljD7baHAitY9k9vAbOHsBx97GQajnO8R3OqtipEiLllNnT2HZGVDN0wKrhoEnxyjHUtnsXnkM
i5C4dm3KZKOdyk71Vhrqg0Ibs8nG2tbkuyF6UCyWcrTkhdJEKB6Bq7aiIUEhulsG+UYzf49RuO32
kw/I7NAcu70RQiANt7TxKM7K6KGCXNbVR2m6aJxrZ5rJULEGHaiziN8kNaWBhnA6xNVtfzHt67g8
Kf6uyvhNiTGBlGS+e42Rn6zxdLwHmRdUW6U0rWRom0WclCePo06GZ4iOJh1v4YxifW62VnowELLW
CXt64U/9hIzFt1HcafcBtGBKoAhZIvEqfVdWX83YUPSujrqE5SND3pZcOc2+t7hQ5K5vA5PDNgMA
8I4rIjgS209mb7PHkfUpoQLZrvz4SX1KCx8IHiOgZuPkyQROBXjuhoWPgIkKpNcLKDP+XlwLPc2p
GYIhg0XX8jA60j8gyrgNQ8B/5rf/spcNAeEFdq/CZVaeE1BIn2yYv6ylzv8FfKrTzftJMytpI+ZY
9zxAg+1ksvbEwv7zp1tvKdxa/6UUQGFNiXHjBTUaNu4m4GFpK/zKCnjd4XilVpWM8i3/gvxwtJxM
PrmTi7PTXR5NeD0NgPBYmVNEHC+nloD3cp3xL5GDD5eeszvIBPSgYfGrx61Xs2kQpCW5+Mr7Z7ok
WyNjBUjMr6wFFbmtgTyzd5xEjAWU6SwNdwCLG2JVhDgGoCLn2TuAbr0+qyNHVSwBEbm52rwfDRan
yHnWWbky5jrr4uAIyC1rdeZ4jYuvedFCXogm+FFzCRyv0I2gZq1tjqPFo/UUWhAC9XZbLH5W/rhM
lFtICdRR1DStQxC9ZWS3Kg8adLEA4Fmqol6V5yETTWzNfkKHLxFvWFwFlwy7yQosHZv9gAXfcDsT
kDfKVwndnvojbEht82Xad6XDjTBODhdpGYZ1I1yKwv3Iy7UsRKvZDznLz5j3wPeTIt0e4yjHTJ3C
hGWatxcU+XNjfM6htAvX+yQYLT9JuuTYWjx8W8jneXZ3gW6YXAScwbeUIii2TiZnPyd8RvoWkshj
rvAVXHOpFdQ2Agi4OCnsdm7k2as/pcRpjMmuCZxOh9xupFU5c5X9QFE7iV1hIj9vFLp6L7HptDbe
iV1ubtS9hTnlRxYRcdL83oppjbrKAYYNHK4J2PvPwMDYNgocASkoydgYjhgqaxKtA5GN7ouZ0dVJ
OfdoRItoWZw2wFwhl8jjQygWIvCUF+yZbQeNnk2KA8Thw25u0qKTA8uJDTR+wMtLHD5FHyUkdTTA
Tia7I1bZ/sI0uAXp5dWT9CqZwMMv7dz4HMs9xESQ+FTdCFNC50XYlPv2EKHHdAwyyhPreoCNf7hV
h5RtepEPqVqNZYNyKxlLibrDLIAaWTYaW3kMFKe6QjNYjTsmTZa2YTYfsbmDaKlC+d6r4wkZApDw
bixqPs8COmYJu3pF9d3frec/md0FdxoZ9t8rdlZk2Y+hRul42D3HBsuIzIVpT8FoiwJfhGPBsBqw
+eJRolmxwiR+FSuCTtowD+tvC7cAU3BZI+L4ZIqxfKwWP0KolTwJFZLX+HOqxurYn+/bGAijJBuL
VjH7sXCjO458uxNqLA8RE8KsdQWVge0grU9SZJ5zgyWU8fepwe9mn4uA+1n6IfYNt48bTfQSQ5uu
7JKitGjN2WEg8bA4LIe0POGJk8Ox5om2J1iBfw5zttcBzzR0DV6F+MgRbFvHDO1Mp4JcKjM4Q6ZC
nJztKMiVuBWCAr6sWst+OwFCgTKDkHOnhPZDzOhWKO1QFnF0vuq5c5lASQy7Zj/zXTTXEIWr8T2A
HQsJ4gfwC2URoD5JD3L3+8kYcR2gCUiHV8oq4S4+12HGPT86UJXw+92epCFwvVnYJS1BLrBuOztG
fe4LzjgRHfIm+cnxcu3dZFuYg6zFy/tcQqMttMLvg7CNv6ER94xhGozvSP95Olq9zDQ5ooMjoxUJ
PWiYh7smtQ8Z9GJZc5ZT4lo+wVhWpuYaS+f+8gGDL7I9DBwaNaQHfUuJTLLOJyiBcljceZM+XAQz
X14aa9H09DtzfQ03Vus5ml6g15ZNKPXJa7+KfjkaE7uTknl0eDnlrBjRFG4jxQdHJhiOWBq34q9H
xqGP/KwCjKbtXrFFGuhtOpuF0aJMomZpLyIi7a0lMdnP1Amv3PGaWqaBAp7XOLl4oZ4uy8TGbvv5
SFIcALX9K6pb3HFZ+g+6ve0d7W5GLlr9EVUrooaCqkHx5gjurPNgHtbgR3+JjBv39aZWOM1iYLu3
he62v9H6yR+uUAPS35IswYvyqjr+5JtAXNor6wIVr3tGwn3o8AM862ToxyC36Mh5cKLWDZiyqldE
LCFHPBme/kK6kfYXHBARFwmEFgFhSOh8VYoOXSOpIwZt4Scc4OKB7yFPIIOpmP3R
`protect end_protected
| bsd-2-clause | e39eab7427a6fa84dad871790e521210 | 0.942517 | 1.861458 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register_s2mm.vhd | 1 | 174,359 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register_s2mm.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register_s2mm is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
tdest_in : in std_logic_vector (5 downto 0) ;
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register_s2mm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register_s2mm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant SGCTL_INDEX : integer := 0;
constant DMACR_INDEX : integer := 1; -- DMACR Register index
constant DMASR_INDEX : integer := 2; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index
constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index
constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index
constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index
constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index
constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index
constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index
constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index
constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index
constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index
constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index
constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index
constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index
constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index
constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index
constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index
constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index
constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index
constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index
constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index
constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index
constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index
constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index
constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index
constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index
constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index
constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index
constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index
constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index
constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index
constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index
constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index
constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index
constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index
constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index
constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index
constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index
constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index
constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index
constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index
constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index
constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index
constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index
constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index
constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index
constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index
constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index
constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index
constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index
constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index
constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index
constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index
constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index
constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index
constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index
constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index
constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index
constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index
constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index
constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index
constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 7;
constant BUFF_ADDRESS_MSB_INDEX : integer := 8;
constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_64_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal update_curdesc1 : std_logic := '0';
signal update_curdesc2 : std_logic := '0';
signal update_curdesc3 : std_logic := '0';
signal update_curdesc4 : std_logic := '0';
signal update_curdesc5 : std_logic := '0';
signal update_curdesc6 : std_logic := '0';
signal update_curdesc7 : std_logic := '0';
signal update_curdesc8 : std_logic := '0';
signal update_curdesc9 : std_logic := '0';
signal update_curdesc10 : std_logic := '0';
signal update_curdesc11 : std_logic := '0';
signal update_curdesc12 : std_logic := '0';
signal update_curdesc13 : std_logic := '0';
signal update_curdesc14 : std_logic := '0';
signal update_curdesc15 : std_logic := '0';
signal dest0 : std_logic := '0';
signal dest1 : std_logic := '0';
signal dest2 : std_logic := '0';
signal dest3 : std_logic := '0';
signal dest4 : std_logic := '0';
signal dest5 : std_logic := '0';
signal dest6 : std_logic := '0';
signal dest7 : std_logic := '0';
signal dest8 : std_logic := '0';
signal dest9 : std_logic := '0';
signal dest10 : std_logic := '0';
signal dest11 : std_logic := '0';
signal dest12 : std_logic := '0';
signal dest13 : std_logic := '0';
signal dest14 : std_logic := '0';
signal dest15 : std_logic := '0';
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
signal error_pointer_set1 : std_logic := '0';
signal error_pointer_set2 : std_logic := '0';
signal error_pointer_set3 : std_logic := '0';
signal error_pointer_set4 : std_logic := '0';
signal error_pointer_set5 : std_logic := '0';
signal error_pointer_set6 : std_logic := '0';
signal error_pointer_set7 : std_logic := '0';
signal error_pointer_set8 : std_logic := '0';
signal error_pointer_set9 : std_logic := '0';
signal error_pointer_set10 : std_logic := '0';
signal error_pointer_set11 : std_logic := '0';
signal error_pointer_set12 : std_logic := '0';
signal error_pointer_set13 : std_logic := '0';
signal error_pointer_set14 : std_logic := '0';
signal error_pointer_set15 : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal tail_update_lsb : std_logic := '0';
signal tail_update_msb : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal halt_free : std_logic := '0';
signal tmp11 : std_logic := '0';
signal sig_cur_updated : std_logic := '0';
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
halt_free <= '1';
end generate GEN_MULTI_CH;
GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
halt_free <= dmasr_i(DMASR_HALTED_BIT);
end generate GEN_NOMULTI_CH;
GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate
begin
update_curdesc1 <= '0';
update_curdesc2 <= '0';
update_curdesc3 <= '0';
update_curdesc4 <= '0';
update_curdesc5 <= '0';
update_curdesc6 <= '0';
update_curdesc7 <= '0';
update_curdesc8 <= '0';
update_curdesc9 <= '0';
update_curdesc10 <= '0';
update_curdesc11 <= '0';
update_curdesc12 <= '0';
update_curdesc13 <= '0';
update_curdesc14 <= '0';
update_curdesc15 <= '0';
end generate GEN_DESC_UPDATE_FOR_SG;
dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0';
dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0';
dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0';
dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0';
dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0';
dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0';
dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0';
dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0';
dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0';
dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0';
dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0';
dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0';
dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0';
dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0';
dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0';
dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0';
GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate
update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0';
update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0';
update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0';
update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0';
update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0';
update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0';
update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0';
update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0';
update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0';
update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0';
update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0';
update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0';
update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0';
update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0';
update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0';
end generate GEN_DESC_UPDATE_FOR_SG_CH;
GEN_DA_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_64_i & buffer_address_i ;
end generate GEN_DA_ADDR_EQL64;
GEN_DA_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate GEN_DA_ADDR_EQL32;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
buffer_length <= buffer_length_i ;
curdesc1_lsb <= curdesc1_lsb_i ;
curdesc1_msb <= curdesc1_msb_i ;
taildesc1_lsb <= taildesc1_lsb_i ;
taildesc1_msb <= taildesc1_msb_i ;
curdesc2_lsb <= curdesc2_lsb_i ;
curdesc2_msb <= curdesc2_msb_i ;
taildesc2_lsb <= taildesc2_lsb_i ;
taildesc2_msb <= taildesc2_msb_i ;
curdesc3_lsb <= curdesc3_lsb_i ;
curdesc3_msb <= curdesc3_msb_i ;
taildesc3_lsb <= taildesc3_lsb_i ;
taildesc3_msb <= taildesc3_msb_i ;
curdesc4_lsb <= curdesc4_lsb_i ;
curdesc4_msb <= curdesc4_msb_i ;
taildesc4_lsb <= taildesc4_lsb_i ;
taildesc4_msb <= taildesc4_msb_i ;
curdesc5_lsb <= curdesc5_lsb_i ;
curdesc5_msb <= curdesc5_msb_i ;
taildesc5_lsb <= taildesc5_lsb_i ;
taildesc5_msb <= taildesc5_msb_i ;
curdesc6_lsb <= curdesc6_lsb_i ;
curdesc6_msb <= curdesc6_msb_i ;
taildesc6_lsb <= taildesc6_lsb_i ;
taildesc6_msb <= taildesc6_msb_i ;
curdesc7_lsb <= curdesc7_lsb_i ;
curdesc7_msb <= curdesc7_msb_i ;
taildesc7_lsb <= taildesc7_lsb_i ;
taildesc7_msb <= taildesc7_msb_i ;
curdesc8_lsb <= curdesc8_lsb_i ;
curdesc8_msb <= curdesc8_msb_i ;
taildesc8_lsb <= taildesc8_lsb_i ;
taildesc8_msb <= taildesc8_msb_i ;
curdesc9_lsb <= curdesc9_lsb_i ;
curdesc9_msb <= curdesc9_msb_i ;
taildesc9_lsb <= taildesc9_lsb_i ;
taildesc9_msb <= taildesc9_msb_i ;
curdesc10_lsb <= curdesc10_lsb_i ;
curdesc10_msb <= curdesc10_msb_i ;
taildesc10_lsb <= taildesc10_lsb_i ;
taildesc10_msb <= taildesc10_msb_i ;
curdesc11_lsb <= curdesc11_lsb_i ;
curdesc11_msb <= curdesc11_msb_i ;
taildesc11_lsb <= taildesc11_lsb_i ;
taildesc11_msb <= taildesc11_msb_i ;
curdesc12_lsb <= curdesc12_lsb_i ;
curdesc12_msb <= curdesc12_msb_i ;
taildesc12_lsb <= taildesc12_lsb_i ;
taildesc12_msb <= taildesc12_msb_i ;
curdesc13_lsb <= curdesc13_lsb_i ;
curdesc13_msb <= curdesc13_msb_i ;
taildesc13_lsb <= taildesc13_lsb_i ;
taildesc13_msb <= taildesc13_msb_i ;
curdesc14_lsb <= curdesc14_lsb_i ;
curdesc14_msb <= curdesc14_msb_i ;
taildesc14_lsb <= taildesc14_lsb_i ;
taildesc14_msb <= taildesc14_msb_i ;
curdesc15_lsb <= curdesc15_lsb_i ;
curdesc15_msb <= curdesc15_msb_i ;
taildesc15_lsb <= taildesc15_lsb_i ;
taildesc15_msb <= taildesc15_msb_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Key Hole write bit (3)
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest0 = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_lsb_i <= (others => '0');
error_pointer_set1 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set1 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then
curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set1 <= '0';
end if;
end if;
end if;
end process CURDESC1_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then
taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC1_LSB_REGISTER;
end generate GEN_DESC1_REG_FOR_SG;
GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_lsb_i <= (others => '0');
error_pointer_set2 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set2 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then
curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set2 <= '0';
end if;
end if;
end if;
end process CURDESC2_LSB_REGISTER;
TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then
taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC2_LSB_REGISTER;
end generate GEN_DESC2_REG_FOR_SG;
GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_lsb_i <= (others => '0');
error_pointer_set3 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set3 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then
curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set3 <= '0';
end if;
end if;
end if;
end process CURDESC3_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then
taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC3_LSB_REGISTER;
end generate GEN_DESC3_REG_FOR_SG;
GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_lsb_i <= (others => '0');
error_pointer_set4 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set4 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then
curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set4 <= '0';
end if;
end if;
end if;
end process CURDESC4_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then
taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC4_LSB_REGISTER;
end generate GEN_DESC4_REG_FOR_SG;
GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_lsb_i <= (others => '0');
error_pointer_set5 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set5 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then
curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set5 <= '0';
end if;
end if;
end if;
end process CURDESC5_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then
taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC5_LSB_REGISTER;
end generate GEN_DESC5_REG_FOR_SG;
GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_lsb_i <= (others => '0');
error_pointer_set6 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set6 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then
curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set6 <= '0';
end if;
end if;
end if;
end process CURDESC6_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then
taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC6_LSB_REGISTER;
end generate GEN_DESC6_REG_FOR_SG;
GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_lsb_i <= (others => '0');
error_pointer_set7 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set7 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then
curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set7 <= '0';
end if;
end if;
end if;
end process CURDESC7_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then
taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC7_LSB_REGISTER;
end generate GEN_DESC7_REG_FOR_SG;
GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_lsb_i <= (others => '0');
error_pointer_set8 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set8 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then
curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set8 <= '0';
end if;
end if;
end if;
end process CURDESC8_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then
taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC8_LSB_REGISTER;
end generate GEN_DESC8_REG_FOR_SG;
GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_lsb_i <= (others => '0');
error_pointer_set9 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set9 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then
curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set9 <= '0';
end if;
end if;
end if;
end process CURDESC9_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then
taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC9_LSB_REGISTER;
end generate GEN_DESC9_REG_FOR_SG;
GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_lsb_i <= (others => '0');
error_pointer_set10 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set10 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then
curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set10 <= '0';
end if;
end if;
end if;
end process CURDESC10_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then
taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC10_LSB_REGISTER;
end generate GEN_DESC10_REG_FOR_SG;
GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_lsb_i <= (others => '0');
error_pointer_set11 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set11 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then
curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set11 <= '0';
end if;
end if;
end if;
end process CURDESC11_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then
taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC11_LSB_REGISTER;
end generate GEN_DESC11_REG_FOR_SG;
GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_lsb_i <= (others => '0');
error_pointer_set12 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set12 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then
curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set12 <= '0';
end if;
end if;
end if;
end process CURDESC12_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then
taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC12_LSB_REGISTER;
end generate GEN_DESC12_REG_FOR_SG;
GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_lsb_i <= (others => '0');
error_pointer_set13 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set13 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then
curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set13 <= '0';
end if;
end if;
end if;
end process CURDESC13_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then
taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC13_LSB_REGISTER;
end generate GEN_DESC13_REG_FOR_SG;
GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_lsb_i <= (others => '0');
error_pointer_set14 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set14 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then
curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set14 <= '0';
end if;
end if;
end if;
end process CURDESC14_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then
taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC14_LSB_REGISTER;
end generate GEN_DESC14_REG_FOR_SG;
GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_lsb_i <= (others => '0');
error_pointer_set15 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set15 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then
curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set15 <= '0';
end if;
end if;
end if;
end process CURDESC15_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then
taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC15_LSB_REGISTER;
end generate GEN_DESC15_REG_FOR_SG;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
elsif(sg_updt_error = '1' and dest0 = '1')then
curdesc_msb_i <= updt_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_msb_i <= (others => '0');
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then
curdesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC1_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then
taildesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC1_MSB_REGISTER;
end generate GEN_DESC1_MSB_FOR_SG;
GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_msb_i <= (others => '0');
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then
curdesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC2_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then
taildesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC2_MSB_REGISTER;
end generate GEN_DESC2_MSB_FOR_SG;
GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_msb_i <= (others => '0');
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then
curdesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC3_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then
taildesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC3_MSB_REGISTER;
end generate GEN_DESC3_MSB_FOR_SG;
GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_msb_i <= (others => '0');
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then
curdesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC4_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then
taildesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC4_MSB_REGISTER;
end generate GEN_DESC4_MSB_FOR_SG;
GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_msb_i <= (others => '0');
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then
curdesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC5_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then
taildesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC5_MSB_REGISTER;
end generate GEN_DESC5_MSB_FOR_SG;
GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_msb_i <= (others => '0');
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then
curdesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC6_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then
taildesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC6_MSB_REGISTER;
end generate GEN_DESC6_MSB_FOR_SG;
GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_msb_i <= (others => '0');
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then
curdesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC7_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then
taildesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC7_MSB_REGISTER;
end generate GEN_DESC7_MSB_FOR_SG;
GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_msb_i <= (others => '0');
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then
curdesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC8_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then
taildesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC8_MSB_REGISTER;
end generate GEN_DESC8_MSB_FOR_SG;
GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_msb_i <= (others => '0');
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then
curdesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC9_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then
taildesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC9_MSB_REGISTER;
end generate GEN_DESC9_MSB_FOR_SG;
GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_msb_i <= (others => '0');
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then
curdesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC10_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then
taildesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC10_MSB_REGISTER;
end generate GEN_DESC10_MSB_FOR_SG;
GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_msb_i <= (others => '0');
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then
curdesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC11_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then
taildesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC11_MSB_REGISTER;
end generate GEN_DESC11_MSB_FOR_SG;
GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_msb_i <= (others => '0');
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then
curdesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC12_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then
taildesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC12_MSB_REGISTER;
end generate GEN_DESC12_MSB_FOR_SG;
GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_msb_i <= (others => '0');
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then
curdesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC13_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then
taildesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC13_MSB_REGISTER;
end generate GEN_DESC13_MSB_FOR_SG;
GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_msb_i <= (others => '0');
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then
curdesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC14_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then
taildesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC14_MSB_REGISTER;
end generate GEN_DESC14_MSB_FOR_SG;
GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_msb_i <= (others => '0');
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then
curdesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC15_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then
taildesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC15_MSB_REGISTER;
end generate GEN_DESC15_MSB_FOR_SG;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to the extra registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15);
end generate GENERATE_MULTI_CH;
GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_NO_MULTI_CH1 : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15);
end generate GENERATE_NO_MULTI_CH1;
GENERATE_NO_MULTI_CH2 : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH2;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_msb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to new registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
curdesc1_lsb_i <= (others => '0');
taildesc1_lsb_i <= (others => '0');
curdesc2_lsb_i <= (others => '0');
taildesc2_lsb_i <= (others => '0');
curdesc3_lsb_i <= (others => '0');
taildesc3_lsb_i <= (others => '0');
curdesc4_lsb_i <= (others => '0');
taildesc4_lsb_i <= (others => '0');
curdesc5_lsb_i <= (others => '0');
taildesc5_lsb_i <= (others => '0');
curdesc6_lsb_i <= (others => '0');
taildesc6_lsb_i <= (others => '0');
curdesc7_lsb_i <= (others => '0');
taildesc7_lsb_i <= (others => '0');
curdesc8_lsb_i <= (others => '0');
taildesc8_lsb_i <= (others => '0');
curdesc9_lsb_i <= (others => '0');
taildesc9_lsb_i <= (others => '0');
curdesc10_lsb_i <= (others => '0');
taildesc10_lsb_i <= (others => '0');
curdesc11_lsb_i <= (others => '0');
taildesc11_lsb_i <= (others => '0');
curdesc12_lsb_i <= (others => '0');
taildesc12_lsb_i <= (others => '0');
curdesc13_lsb_i <= (others => '0');
taildesc13_lsb_i <= (others => '0');
curdesc14_lsb_i <= (others => '0');
taildesc14_lsb_i <= (others => '0');
curdesc15_lsb_i <= (others => '0');
taildesc15_lsb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_64_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_64_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then
buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| mit | 326c8dd4842f7006b42ce204baa42f6f | 0.445323 | 4.182675 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd | 19 | 13,156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RZm5UrZFV7JOtGxR4Pzih7NQYLp7LmPE59R/6o+hZN+ZT+nCA+l5YH+/j+E+cmHHWo6IUrn/ULaG
ZkaGINks7Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MRNQzUt4f7a/v9KMrin25EUCYvWi/twJzLlDdceTmDN2GCvOURSU7hHpsmsqqCb1xCeaV7xbvs0c
MXpZkAPeQc5Coi1irNf+9eKbc5uIh03B/PevhS9S+La97Aj9rjHplzcZDEBFN6fiyAdKvJgOrOyz
87nOO0u5LoaEOeyC6ao=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
L17wVQWzSUChaUkUbjAqDK1dFxRQ9orAmYas8htY5fjqeIDtBkS/PldQL1EGRGrFVbxZVbStDyiq
iWMlaMSfJiAW0codwFWqGkqnH6YMctbqpTZdQPbprA8qa73Xmy9S5tgWXo6y3vZys5HBTFHxXMXj
HSJZBGLfj5+GGMkAkDYYBZrgDs/jxx605zYzRg+wKonRxjx8C7c4r2cekqFXXjEfMC6t47HLGKZO
Wp8oqSV+SdxjNfsxTeAcFxqhiABG1hbduxwcNIQO/0mgU7awDWqjimqvnE1+KO7vQU/MVpl+J+Y9
bwvxkUUMkYnqQG/HGWvvQ7Zp0u8+rRyDh2dzOg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
yJG5RZbV6QsAW4khC+YjJnbI2jNRxPOtee58pTXfgJVvj12BYVsRuhi1xiVJgak8Vy8V0UJ43Wc3
ydXie//gOHZIACOddgGz8WdlyWauaZ9sd1K4GlV+vX4K5HkoOyunq5QSLYwU2X/ZYYkTAGg7My6m
h1UvByaO98o6pNd+n1w=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QjcZeibYm0SAHW7YliT2StC14hkmhpmI1+m8klXbQfAK/yXQ8NfNnDZicIHqHpAbgVQzoGSkcmXa
qhjmF7JhXI4I11rujpUqz61fAf/3PeUiYimqp9l0xnePLlrRBeItzqfetftMnQ8hBAuI+sARuLin
j4+kHDvo2V/A6kndknmKA6lyd7gI8Mgzy1xgvua2Bfq25TZ30r76kaSXXo5N6hFVjtfwPGqnYepq
02yTg3lN97x/f3REjUh0T05iK9mOISMgvqQkxFwl6hBnLhp8WW0zJBjFvAguLZDf4CMBuYBnnmGQ
axcOzl5DWDcYTgPm/DTciq3eoilijus/JUHuFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
Wy8avf52SKtFRWpdKbuuoKz/QISNFt5qyx1njgupdsY1yGpbX3zodNM63ljgbYDMC3fZW2KyZA85
bRsP6RIcYZOndRqOE7OfH1ur2jFen4OVLRXLO+1hOqazA6KQe2iZsxqSqjfPf2LX+tWfJO/eUBuu
NN/DDOvWclIkj5bWWjAOAtaj2ThrtTqPf/Wgm1e+aN1qhMvvZguqwpBvrrLcckW0KeLgbIZPyh1G
5qPHxWqKah52yTq7Ywnyt1sm4WIZ9hJU5H4a26cTUQzChHK2Zka2hkSrxwwmTmZ7I0ooQWEEHQG8
g6UQzKhhk9CGAy+kKdPs2/vSoI9RkxrUY4HloVEOl3p1A3FQMEsUHDbAMiQGAznYA7a6JSZCkgp4
lKQsS5bZQZ29rLBvJAu3DbPvK+fyUaOYB0iucF7/zIPubiPgf0+xTr7LiF8k6nTnh2QhOaw3gm8u
VqPnG/linjOiqwPlWr4/HVhCukQMM/yk+tHvBsdClSkzmOVr739g8WAxqh8oUvQuXWLmvcZ10PR4
4274FDLD2E7mjEq2oLGSjrS0MmLK1S++yWo7WqUMLrBMdBcef4aE5ZT9vp1/VmxOLlvne58oqvhh
/1744ufYxPMpdJvpMCyUynJm/v1Lyt9NI/TbG+74DQNz49lJCJK78lZcME8EM7UHuc6B+ubWNVA1
7PZPdrKbMLAwoI6eYJ9w96HfaZ2dMZBhZwM8mbQ7FThGdy1U9ECwxeQW0rxzTnlyRWnKlHdgBa79
D6e9hlTgXS1JoJwleRFdZccR/gtMATd5yiSpTsbf9d1cyUv2eewvsgxWaI8I+HPhOfd/uyzlZjbO
zDHdS7aILW0PSSw4O4LCbM7zQM3i/ui1KnxwXK9Nuw4tTnreS2LmjvDzcTrpkGGEI+JnAFIGll8+
mxMVRO4QndXwiNfHrJHat7vAfZ/XDXuUTrRPRc643RUhz86JZKC1aOYdP3Iiy28FkRoBkn87bkr6
tVdgCkjh7utXVwv5qlhc+nWnos9u8PggfRXAaZSi7Ajw8jX6s6FLAYXVl92IYdDyYJBZT7I6pUOi
4ql2ucfkF9ql5+8RiWm1SeDPDajH7w/ZNsbt7Sypir3H3M3KM+1q/ZxdZUyhBS2WZyw3ow0goIgL
9hEtchmsW1n+OtYDg5bISQvtjPouiXGoWqdyLc/fEVsBOeuFUe9DSYn0jF6zHSSSLLS+DH+N5s1y
MVcavlbR7r5mtqnhnbxsdICqX8CuCAh5hUleVbwlF2YcEVXXeCEPJtT5vsdDQXpoUXvWHjCFHMtn
Z80WkY0Qfz1Cs2o6IIrrUwdjKHMsXi5x4QdBFOQXy6sFXPWu14LqzGxfiVUW/bbl8v/VzpBslvpq
AvcVSGbnhuqqzgOkoqE12mfG89X8GRBWTIs4jn2TMpzVCOKEd76p0Gf8hwAA2t5xHVJELHM/CCNZ
25V1MVpsscSpUoY1AR6NgAoRP4DvAqJsN6C7UwzNHR/hNuMed5pS/kzhB+xMZ9Tj3J74nFKRn7Q3
JM5W7mHmdy9n0rkJUR6jgJRl4rU6SCkCOGDRnZW4D7LF8j6axIQYateOcd2mSJWUFht/xL0ZuZoW
4kOKSFiGNzhFNBqIAzRwhhe0eNSuFiixdsaVPHuPMAzBGiKUv/zkEjjSuIhev0pB/t8MmWdPmRzI
AlNbN6aVA32Bod7Rs6FSX8sdBNn+WmosAMd/mPmGM95pO/NNz7GvF/f4uShaRx6W66UwDkWcbhxX
7PGg6Q56g8ahaetujwOvhZQQdhIUgqD5hBzpSeCVG2tKWzKrSb843P57jICJRb0F6fsDuy5eNuhu
b4QtiRYcuog7Yh/puCz+rIfthFGg+7Ki+4UD7v3yO6SIbJkuwwx9YQ0oHHyir8MpSB+KJg9wQWsS
/MFNTlx6V+j2NfzBjyDRhLomU/xDnppWkQy6Z7mPf1LWILgouCIR3htQ0Bd6g/OqVJQGRmdePgok
3pSaO7rKefY6QmcdsYHr+9lsVGSIc6HZZafJcmGJvD1tDFl/nd8m7Pq37Gh9sn2AdppYDl7Y50Mc
1yG9De/Yg/kpBGCbCTQJ/X41+nTtCJZV77L/LDxZvMUfHqrdsb/sqjpHaF3AID2Z9EyG5kjFzvdk
P9MhlgUrdWNeI173BW/tx5ehaY1CmscCFrOFhSJmstGt44fmo4tH526BKNSs4FUK+ddSAXuZtEEo
qXoQOzRmAxsBpWeXRlxhwANqvwmFSVKB5lDW8EwM+6smFOkAlxKec8YFMwk7nqDBad413F2OdQe9
xHgl7d7GrdH4EgGSxRYfOwyBub5qDKRlQG2qdR+7RYx05hi27pL+R7yu2bZGcFDVlBFSPHt+oSWc
ryXBF2Ctyi1YdBYCnwXeI68GfdlVaDZXIvrokV5ytKkxicZv/+pPBeSucbqZuvMwsoxdzTEYXl7H
L1PcpVDt+KCV1q4Wb//2OnUatdXlCHzJ0b/Pv8XSY9RJdjTqKeNnTq7Y0O3Xwz/Ra8oVoTuNrmlg
SSq2RqxEBaBaQuMuxw7ryydzDtqKo3roXTYslewGVJ0nj3PB1WNEWMrA3x7DXm9xPcF5cuDNXeGQ
IN7Dgnui1QCenbnrc+vYKFeTg0AdNg77HJtYSGbdPl7ADpZpIG7ctckmTUrsm0sxK1kC/qewHJOb
uFG2ik5gET8Q9StUfddEMqNUuookgsb8IgD8uyb3duhstmtmx38BtaQbqJp/vqv1c4k2hg/s6G9v
zTDVfmPG7Mi+e0kWFymeDeTcPjYaLty49QShB+W63UzG0E5c33t1WHxeb/y6MW3TE1kN+59grgH+
C1EnM1q/SV3l9UKUeledCorm3ndJGEqaNIdnKXcrM4d/uuACPOl8hzo52dPYt3JEE/3MuP63PFCK
PBgzqhgsfStKaSrrAR8D5mTuO464ga+2d0ka1Q+u9e1uNs4uFUsRpqZkImpkFf35blE1txie39F/
DebDjawhICUb/F6iCA1BEMGt/ymt3kaxWoXmrcsNLfaKQptZhr4sq5TJ16GPdsr32IIuY5qatDeT
9F//kq1VRtuqkWaWYoWuSHCI02uOFFXaRZpppvkswsANVSfcB2+IatSk7GQb+dXWTDtqniI1t0NQ
InEU/RtjqtS/9x6LRHIo2e3gb0J6kyVTjfMoDXJv0EiOMizi7mn1c+kusLTDctMMeW7QZnvmZ68+
R4wRxxHusnPwHDstaClH2ZwISIE6OkH7MmXgxqG/wn7WN4qWAVI00ZLVAP2nUo2Rxbjpz4NIldZX
RUQG4HLiE3ifaZU1CsVfuRKvAn5RufBRJJsWWSs+R1batomtbpytu+1glZDv2qQaQiAtrAbM2eot
pVrEJXoeGJ9kyGDJgfbciIjhHwH+yVX5M9xu102ci6uOqGSFGn97ILP1QlP5E6fRe26LiF4jD6hP
DQa2uavFGESi7KblVupdYchk+cVeoVNIoexVvFgAWe5KXYpmXTQge+NAaVrGwqWrI5qLv3BOSVd6
u13CQjG1e+gJm0CHKsc44wiiGWTeuixnaLKWGoF0o/PQdfb6qwgOAWqkr7/RwjKmDsCVJBQJGs1a
AnRzOgoBUl9zg6awHDqX6uCyynFrywGj9ZCde9UqrYPy9w9oxqjHH9oFYfg+yWxxNzN9a0rt9Qy5
E9yEron2LBl0johs62Lbaemx23DrAOnBR0bmmNzwkB5//37/mNGTfbCTYCp9AhbfNair6LcHbtv7
1u4+QoDzdPz/uGQ+VDD+wVNkYS4It+dE3tdI+d5kGoLOU01y5Q229fmPQI8Qx/gvTjVDaIm4PvTD
hSQFsrHEe2Lbrl1HJzM9dHCBUfgca9lSsUt21PmojBDbkY5Vqf2uC4kU3oXcpsan4O6M3AMBQALL
p/H6CiUp8UbKFLC8tPQWls1Cz5zWFeu3H9zs5b4NbFj03IdGuuLzNYRQqT9Xgb9VIcpFsS7p8RDD
4WEVgqDaUHAujKK4vL3Rulh9dLEA99wkimdlcZLNo/WaM5QPhNiAfqVC0/1LZpKvAqoSL16GzWuT
B2ohp92tT7e3/l1E/pvu4zZuI4XezQoMzDgFUW3AoQxg2J43mAtbvufCl9u4NgkoMpsnDBdjxc66
VF6Ff7YADCb3iVgQqTh0Y3iA4O+nymCVfxHn4qoIa9sSnXGgpaavd4JgoXX+qVtu73OaCPzKu+Nm
wXq7JWHUgrUONz/I5yS+/BhuwMiG0dSydSeQ8JMLH24W1pOJXsoZoJZjtPpvV1JNlUQ6vKh4sj1p
VYcT4eLxYJINamRVEPox9iMFfxyvytbpaQ0ALxV1DEDg0u2SAFDpOGPsDvpLvJwEVdZMnB1X9TCH
ypAIbXEbTTBLSnI+KfMvaO574MHBHQGgQyVs0G/k+ytC/Hcjqa7MbT89IfwUP3Pcp1mHJNNbdWlF
i3LGgHNOnkqEhXnHynlE0B7vmkxxgpAGa4PyYkccrPI0Hw7CXcAIzfyc+necZADAPmlPSXds3NMq
Qgx2p4m0kPkNTeDGlbXAjhuRz3UOEVo19ojtfshlAPTgNDL4UJoq+jQS4Ro/VQeq9UU6ZST1Yu5L
nVQTN0pYifK+O/FRJhItgMBFbQBeD0i5RAV6OZOMC+j1ap459ror/H36czaHEDgp/LRlTzOA3XEJ
9DCodS874t+9SEi8sLFgToKyizki0HsM0d+1jMKrnIjuas3D2GcnRWZBhy5YB9Xvd8lPME9/F75u
ux5+GONncO2Swk9hhxX5SR+e+eJxgJvRGbXNROOQLqm+klu7rs8nG6a34b9jF+8XT8McnH5nixeR
a4LyDX48lh4iZ1YAEtdtPZ5T+yqjQ3OR+7Hon+xgw96hXdyCr8NiKPF5BRQtCJ3ZWe0U/g/aynwa
I1BvvzpKt/1G0zdDGDhBWMMGd4t0n1jMPWdEBZYX5WJ9mGRLQaK/YIzCSB32tsKCiiiU6AEKNkoB
1mPuqe5sYJCBhGOrHvlVewKUFZINfBkfFsd8ovWXVWdLuwOLKyJnLtt2uRQC+cswAd3xFtkGADgJ
NWh4+ZS/w4xgSzLbUFnTHtq596pZF5AHvK1UVdD9y+b3kob4Mfjay8E0UzHLMCs5jzkDNhifek5o
y8q8S/oSwdvv8UbdOv2M8OftwNgker8a2AUvfgFTRVdoQpGrSTvbIN3kXFNSRj7t263N8AGlJIvW
iYtqCI+ZudZMePrcfsxkuk7Bgd1hRFpntV6I7iX2SQIh8LdgojuPH7G4WnNutcE7Ah/WPwSDCuG1
mSKCVi5b7F/XQJg6Nxcbo1sIz/+AcV+VxDmf932S6amkNBWTeB8GX8NUS2BaEhUoHgQz34yzP41s
0SLtkfkFsTseKzk3ULdLZ+wuwFPRDYrnYoLnQTK/VLynB7JOifadeS7w/46RU6Zp3FbmEw1W1Vml
Ud9SypP0x0XGurN+Ak7k0wVq03D0kqXe3Ys5c7JYdxiQOHifKGvwCXOW+VxO2FAPRY4NRDbsLL55
mOi0yXjYRPRiqjx3GrsiiFxWGPq4lMhb8h57VGz1e4ExjcU1lT26LZVP4RiP5392DpL5+P5wjF/g
G/8sWdphmruQ7uKG7Qm5QirKr3tE4VBvrFpSqJOFSvML4/W21UpOf8RZA+xgScmauH2mRWF9fUXO
xr6lKJq+Wl66lAe+RXGA1ji9obfhAxerDaHH9NhCj6oBcTf+DzDvC8AAJKc33YXFX4eLwb4WgOVy
BKlsyCICd/6+4HwWqbgsc3G967uj7njxd5uWsHnl1hOjIj+B7zByVAb0DPQnu/0kyYM/mLKYkavn
4QI+0zYq/xENovVx42TUE9HWwXgk393/m2hCuFwAXWvM1uWztXP2OZcANEQfOLt/ZmPEmkKbwcTB
EkaUi/ME2SOUuw8ZbGLi1oH1qAk+kf1V2P0Ab3HrC8HyguzftxdFA0qcMMqHDcLeljHItlTzk59F
Chklymd+wFc7yk6unM6xC8q4hzF+0QrAIT+0s/G7rihsH9UuOy3Zp7js1PQUYXU9G5+RmAoiyX3f
N2pQ2nsP4VOKMLQlIjkgRhe/Io01lup4pqA0VWtYzuqdzi9oB8fEorZ5vUPzcl4j5k0ZIlxwsPtn
s0FWoGie4OC5i9J5job6Tb4sh9cAUQjhSmzr6Yt+dNJJ/F+4RWDfe8MdQUDLmy2qSvbHKJSla+0y
n/A/+9dANtZ0CmEipO1f5aqG2cMd7nEqzJh89vIOIlT/qQ+hZ+4vyhjud3ndpPTQEzbl4fthA7XY
eCBohxqj2lIMDKpkYRJGLN0L5JKH5ThTU5Vipct1I0YAFGn0CmMz+5yuLPtwLpQvWaxN7aX5A1WI
VLV7XVYuNcZpCLXcc2MRxFhjuHEXVXCru+fNPSA/J5hzhlo69cmR+9eYNpKA+2KJPh7/FEC6RO8i
AiLCriezmda155lyb5P/DWqRCNfoYAbWWV+DoVKeFvMc1OAN6KjyNHVPXCj98InKBRbZ24knjS+C
+M/EInkQI6czonIzW8l0RwXxG4FhUML7Ck0rXe+b1ELBhE5FnCT+T6r9F7muh3D83Jh0gAQuQokQ
Q97rLAmh96cjplgtfRXzmGvRYpe/gyDV6BFQo6PAb3mqI9644OiqWwVjtceZYkkZfs+zZFKKurCH
Qb6cpuy3+lB5JCk9NTP4IyuaN4bLgG2VT0y897yWX3caTh8IKUNM/f2ekcIGqP7nkE832yxpcgeY
UxpKV/hAMca8HLNw4zaasJwOrlraA6aIp8yUUX4WQjZdNfWfFYyCxQfylhsze6W7ZjqgtPCw5EMz
zD24m5wPoRRTc1YLTejkEPbdBwEUl9L3QbxOUZP38PG5u0t9JzyTm3tu+9/CRVn/3ftoHb/lN0aj
+ksTZtmYqIf5VauLa0zePBfgvXQ/P6/kduGDK6/wZ/Kcpk3uu5OBoc7C/bfA/QwJERmqeIyp7BLH
b5K3jh3qnztSFHUVsonmSoyOC3vZMcQmeOlS7D1Izubd4n20QCRW2TrdC9YZmT3k2PNPsYuZgM1+
r4JLBbcDtw4OsYm2qUokL9nhri5vRrlrp9p0pPiGg3LalBlvJrqA3O1PUj3MRcCObWAloKo931lE
6PrrrwyQAx7vlgrWiukxTjUk056MZvXRR8oCqbICtoxt+bK+Jy4Hl8k9KJLxKqLiH+XmQ2LcverF
QZ+3xxzJdnpVR8737Vd3qMBk3YkaOcK5TGYXqxAEiO/Nwqrm594E3wkOcygCUc+84o4kWRTiEUKQ
SH/qYUyW3IGTl+SfQGQWrsWj4dwpTc0jAtl8qyoOX51dSeKV70QLoi/SD8cLMK6CzevccMHUCDRr
7rqpSakvCAMkhYUyyp6taGB+kleFplZ2irPusvvuwwrHEguzDA24a/p8IM8YZ5kxBJkFW9HNX25O
p5gMYX9qFxqjsa0qalBuhJnwng5C0/VNNcN/xr8B71u8OPBpxDGwX8tkfDUWUVodFh4TgpQ/GiES
UWPvMRg33Qr4r5cLq8CpZEah5QxGtz7jDX8BuIhUI3cl6n0X9LUT3B7lfm+hgyT+DDzonl0KlpPq
en0wJ97YiOENJfOmWkVv57O7WCcXUwGqE+mLgVTHlS5dykoZRDyFV0CImmu7P7iuOjMpD7qTRgXN
i6Xnfn+N1lRA16ujst7QFSopVhhI/lKTk/6XZaZkGvXyIGzncyHiDZzZqGTdtPavJ1X9KS/tX4Mo
jDCv/qkBpaNex88hLq/88SuirtHuUsPIBIsYAC0lV08wASR2ULV1CG7zWPxpQy6sdFjbLBlHu1yX
GQW76lZLKfcy2WT6tEYeb4NCctVdsw5udA/G/ly5OKO0ZUpzhTpNF/6i1EL4BGAbySxTasxcXsMc
Tb8FQIPva8+Nl+JthCk7qsf8TXSxOddXtBYYWbNVKgc5S1yngoew+65sG1reGYTFYh4PlhUSxMIM
LbPiX/fEEiLSXySx26il7H8XnZN6zIDcP5WVeVLemtqXjXRvlRmibXCwFGYJgv2OBwtee27FId29
zdtuk16FJ7JWQIn0Xr2QRyw/8EMJf1J7NItHb0cdvZOTzfJlfq+OAD1aDvhdvIpclkq9bhb/do0X
FGHVGqSHDW+WG5YP41JiNHV6fSp2XskJYaorOuTm8GvPjRtT2l1m7lI2FXTzJPFRZ7IqCYbRY1iA
6WI9b5JjRa2hfEuakX+vv66nueoCN5bfo+2kgaAHYxvbz/CnfD+ez/vg76tpSpmlbE6gPro1YPFN
jpzCzZY/8j2aLf5KLWgdzd8fyf2KXmUdqAA/q8QXeDqtHKq99j2AFtue2yVHcoTGNIl6EIE2mkeP
kMecfC4fJ/kWeBUt5mk1Pe+2WFnUHY1XhRa2U+LI7NA4RjNMk3rBomWJPwqaIhnhrd746pRYzRx/
SW3l0nEV11PX5Tfo7EVdkgN/sZj36WD2ByPsfCR9ILHmIQaXSfenuIeqiwdlSLF4R/y37LESSs/0
rdFriXT+jdRUzpFwAoF5Imh4ASI/3lfWKest90Kmci+f4u5zrMqH6s7Cz+OrSvY4t3iWK/hNavTW
N9ARzm01uuMhTve45InkbyvySl1+PHvAie2jSob86hD9RF5Ka+fi1i66XoGFrB0sP6vdC3RS8Ubu
JpaXWv9GjEp7qR8b/GMFjoWtohqeQ56+pMLIGCI3g4uQr61211YN1w5hpMz4VsO9/0DoOcaZm/To
6HqRe0q7L7ur/aCkIt4Y33HrdMY7uu2Jh/5/qoneg+2trQCGBJ3KrujDStJR/cUuDeystob1ZYOb
eVR7kQZCSjldBJQo7Sjb7V3/t9bz6VpDB7P9lusb5ORI8iso/ci9il0TkVv7CUtkTs5OZ/yNH0wT
g82s3KivJJaiY2fZtVKwX6jeMF1GyubkFVeu9fpDDhb3sZptlQTpmFt8aPzf3n3xzCQhhOa32bja
+nKV/tAxcdUVKRP6JEWKscGRObH5HBxjSQvMQUTjXISoNwKyhZiuW8lgC5pJgUb89pqd+tGzwwxE
3Q2UQv1vYpqwDLwWPHnVY6mlVAMsp258/cPR22xYVuMy2usiw8DcqAkceLzuWKvw0udsumBF0bQH
+6Pm6xzFPw3Wj+OkmvVX1eqplimNf8zCyecJO+yslyR0pWln7NJRQua1LE8csRNO7dN0DyOfVo/W
+e7nIT6YI9pwRkF/hSkQgW3Aj2Ynq/KdtOn7hEUr16OPnV2HbdEXxngrbS3/1ImVWn10sPBT91sF
aocEu4uCMlpVpqZYIw0ItV2BQXXEdUwUUpjX24H6eLvc43D6S4Iohet9AexoI9oZyM0lYHMuz5vr
RIJtUnwzBu6xwSmRfQAZdZJRQz6WksA2/DGtFBaGyTVrS6e/t6c2Hdjj239GQslN8JfmqpoyhsTK
awkteIknfE+3DCQAMuWApiWehvLyKyFsGMqDpDiy6zNL9Pgrvm0dn/uSJ0tyST9t8TdHIFeNNwuc
Wm0uxQ4Wd8D3XB3riuwZPBJHp02rHbeSlWGswmVw0WXRjLbS3BGZzwuZhMmCGq/I60eeqEV9LU2k
rLsbFB5o5ywPB++lWMs+ulXMLmuJq1kBSbk0hJXIsGU0icC9T+7m8HsFKr2Sh+wUq17jB2xLrSeG
apPXFqnWZXS8HqHSEQ9Jzixtesv6QPfrpx3VR0hjNwapkEozhmwtmfMzcRB6QN65Sjl0g5g+PiMU
MboAXgTM81BFR+44m7caW5DDEc5YyGhz2nHpMgG2CN7/n0ey8JQpKrbggYvM0lTVOrJ+QPozL0Na
N/WWjS3B/MSQuBJHRNk7FLULgi4OV4oUYd+hKeXe/OnPnNXwHdP1rI7LDwYXCtl5TTmqE6opdQmg
ZW9n4xA0nVTxOXjehNc4AZFtNNN8dzzz+V3VBDpB1dZKpd8w/4He3R7+5VrUfTnhFR/FeJBrTEXk
eFGxrsfmowM0L3w+VY3G+wHCkCD2OQHxAjDq7naKHsQMENQWn+5ZAnRwIhRGCJHAAJjByYoBlFSD
xBaYfQ9+hOjAs5TA0yx14jslVZ9y9JrS4G33H9xFBNtHFqhdEOOaTB3oJQ7fUxLUqbONqb6nyV2r
4SdCX5i/LHZsrfxuaQAIJjRokscGk7MtiGomP7aHbnSv85xG9IRrtj2yNyVw51OoCbIjYcqCLsBo
YgJMxKcva3hWTMVRZv4Sibr2LUt21wdYbPIR647lyyv8aOzptM27empRWYaMwzkPXM6mOpXMo8LI
hWpfYxojbCtrxLmKvdLWxKcwDqdu6b1UoKJhnicWHG6qZyw/ao/JsCnPdmb8yBSf5CzUvMld48j/
EpTRYjsSX4O6Cw50i4hnqR1ADkWDnz9yluKXd1LJQSkKANLZm0AQ0sHbM9vKQABSYO+dEJ254Qmg
Yh1vYP8Nok5Mqu70XNOYqtmf3uSRx07El2OfZpEDy7QXomRmerZGcYYWRbkIbanmjxB32O634/QK
Tz+lW3CAhXv2W3OBPP+mwMFvyjK17xnw8OdfjQd6VXE0m5bqRMjaMBrNuSHSVDSn/W2wAcDo9HTP
LmkP8JWU+RTpPJvrWBu27folYM3OIthIpOkqgqnisxXfcbxJocR2dI7sx4D88onefwASCcibcdVb
EsbuI4vP8z3p4t0/zx5C6yzJpglCjU0laVdmR5mZkFA7iZqNzzFOVp0vMaH5dXKND6XkJ/OYoP2V
APdV9HICzjHWii2moaCn+hJw6OY=
`protect end_protected
| bsd-2-clause | 2a20b9dc4790df7a87d420e62cb82f14 | 0.929234 | 1.873807 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd | 1 | 24,940 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_CH1 : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
-- Channel Control --
desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
sof_ftch_desc : in std_logic ;
desc2_flush : in std_logic ; --
ftch2_active : in std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch2_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_tlast : in std_logic ; --
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic ; --
m_axis_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch_tvalid_new : out std_logic ; --
m_axis_ftch_desc_available : out std_logic ;
m_axis2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis2_ftch_tvalid : out std_logic ; --
m_axis2_ftch_tready : in std_logic ; --
m_axis2_ftch_tlast : out std_logic ; --
m_axis2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis2_ftch_tvalid_new : out std_logic ; --
m_axis2_ftch_desc_available : out std_logic ;
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal ftch_tdata_new_64 : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
signal ftch_active_int : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0);
signal queue_wren, queue_rden : std_logic := '0';
signal queue_din : std_logic_vector (32 downto 0);
signal queue_dout : std_logic_vector (32 downto 0);
signal queue_empty, queue_full : std_logic := '0';
signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0';
signal sof_ftch_desc_del1 : std_logic := '0';
signal queue_sinit : std_logic := '0';
signal data_concat_mcdma_nxt : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
queue_sinit <= not m_axi_sg_aresetn;
ftch_active_int <= ftch_active or ftch2_active;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (96 downto 65) <= current_bd (31 downto 0);
ADDR641 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 <= data_concat_64 & current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate ADDR641;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
NEXT_BD_S2MM : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
data_concat_mcdma_nxt <= (others => '0');
elsif (ftch2_active = '1') then
data_concat_mcdma_nxt <= next_bd;
end if;
end if;
end process NEXT_BD_S2MM;
end generate NXT_BD_MCDMA;
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
current_bd <= (others => '0');
--
-- -- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then
current_bd <= ftch_cmnd_data((C_M_AXI_SG_ADDR_WIDTH-32)+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process WRITE_CURDESC_PROCESS;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch_active;
queue_rden <= not queue_empty
and m_axis_mm2s_cntrl_tready;
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_3.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NO_CONTROL_STREAM;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
ftch_tready <= (m_axis_ftch_tready and ftch_active) or
(m_axis2_ftch_tready and ftch2_active);
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active;
m_axis_ftch_desc_available <= data_concat_tlast and ftch_active;
REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate
begin
LATCH_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tvalid_new <= '0';
m_axis2_ftch_desc_available <= '0';
else
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
end if;
end if;
end process LATCH_PROCESS;
LATCH2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tdata_new <= (others => '0');
elsif (data_concat_valid = '1' and ftch2_active = '1') then
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end if;
end if;
end process LATCH2_PROCESS;
end generate REG_FOR_STS_CNTRL;
NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate
begin
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt;
end generate NO_REG_FOR_STS_CNTRL;
m_axis_mm2s_tready <= ftch_tready;
m_axis2_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
Q2_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then
ftch2_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch2_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch2_queue_empty <= '0';
end if;
end if;
end if;
end process Q2_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
ftch2_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc and ftch_active;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| mit | dc5641c3127d9314e458952ad49a0218 | 0.44563 | 4.171266 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_14_12_2012/TEST2_SRAM_25MHZ_255_BYTE/SRAM_25MHZ_255_BYTE.vhd | 4 | 10,382 | -- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : out std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; --Chip Enable
UB1 : out std_logic; --Upper Byte Enable
LB1 : out std_logic; --Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
ADR_DAT_OUT_PROC: process (n_COUNT_ADR, n_COUNT_DAT) --Ausgabe Adresse und Daten
begin
--Adressen
COUNT_ADR_OUT(0) <= n_COUNT_ADR(0);
COUNT_ADR_OUT(1) <= n_COUNT_ADR(1);
COUNT_ADR_OUT(2) <= n_COUNT_ADR(2);
COUNT_ADR_OUT(3) <= n_COUNT_ADR(3);
COUNT_ADR_OUT(4) <= n_COUNT_ADR(4);
COUNT_ADR_OUT(5) <= n_COUNT_ADR(5);
COUNT_ADR_OUT(6) <= n_COUNT_ADR(6);
COUNT_ADR_OUT(7) <= n_COUNT_ADR(7);
COUNT_ADR_OUT(8) <= n_COUNT_ADR(8);
COUNT_ADR_OUT(9) <= n_COUNT_ADR(9);
COUNT_ADR_OUT(10) <= n_COUNT_ADR(10);
COUNT_ADR_OUT(11) <= n_COUNT_ADR(11);
COUNT_ADR_OUT(12) <= n_COUNT_ADR(12);
COUNT_ADR_OUT(13) <= n_COUNT_ADR(13);
COUNT_ADR_OUT(14) <= n_COUNT_ADR(14);
COUNT_ADR_OUT(15) <= n_COUNT_ADR(15);
COUNT_ADR_OUT(16) <= n_COUNT_ADR(16);
COUNT_ADR_OUT(17) <= n_COUNT_ADR(17);
COUNT_ADR_OUT(18) <= n_COUNT_ADR(18);
--Daten
COUNT_DAT_OUT(0) <= n_COUNT_DAT(0);
COUNT_DAT_OUT(1) <= n_COUNT_DAT(1);
COUNT_DAT_OUT(2) <= n_COUNT_DAT(2);
COUNT_DAT_OUT(3) <= n_COUNT_DAT(3);
COUNT_DAT_OUT(4) <= n_COUNT_DAT(4);
COUNT_DAT_OUT(5) <= n_COUNT_DAT(5);
COUNT_DAT_OUT(6) <= n_COUNT_DAT(6);
COUNT_DAT_OUT(7) <= n_COUNT_DAT(7);
COUNT_DAT_OUT(8) <= n_COUNT_DAT(8);
COUNT_DAT_OUT(9) <= n_COUNT_DAT(9);
COUNT_DAT_OUT(10) <= n_COUNT_DAT(10);
COUNT_DAT_OUT(11) <= n_COUNT_DAT(11);
COUNT_DAT_OUT(12) <= n_COUNT_DAT(12);
COUNT_DAT_OUT(13) <= n_COUNT_DAT(13);
COUNT_DAT_OUT(14) <= n_COUNT_DAT(14);
COUNT_DAT_OUT(15) <= n_COUNT_DAT(15);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
end process;
end Behavioral;
| gpl-2.0 | 89fbbf14e5938cbc65bcb6d9251118d9 | 0.568099 | 2.825803 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/wr_handshaking_flags.vhd | 19 | 12,657 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ZF7Gp+JQYN4x6Hvjz/p/glt8+Yhfw+y+NSJwSgFAT75FGfBEoCi9gxGC1aPKEYH1nKSH9HDVBmjN
jVYDQh69UA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bCrwACZO6VlyUjDp7F6NflPANkTfGVm4hgH/4AFvgK6LtR4U73r1HOWXfaKa3y3uaefm3opyWNhK
nV2TI2PpMLr9LswzFSOsgRzHCqR+XBS+8LwZ+lBVN3PhbED4ykAJBbHjWQapS4mEVXs8Bors5GDK
A5lW6VBcepABjdMHcOc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
sWMXC7ertaTFiCso7MQnbVyuVSvzDQRw1zbA8jCBUoJcGFv+Da5uM/ZInIx2vKnorpctjF+RfQ/I
vLvHJ4hFA7ai3KLDBa+osiqXeR3vvyAO0dNGGmO7GQ1dYRUzzSKKrGTJhKWqDfnAsYaLroy6U3UI
uNSRIQtxv1ciGPzcMfrykPy27NH2CEGiCobfxP5HXDyrOVBqWAZuLaPzQRv0D8Ie2O70SiCDKawR
vbedGBup6qqgOpbOuoCX/zcbW+qJ2FxQY5Zrju+0WyLSf0XnZd4src68n6rXZlziL4eo4Q6lUGQv
gUEyqpp9Wiyw0QLmYTxtAKnwwMsfY/jCo5ZFSQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
d4cZTzaonF13oHTIDZgb2oXxuKQXQmTrHOYXqYqbAU6BYAx+7y9fxq+NNlLqPYeukSU316ZJ2R63
uH6wrMfXFW1V94ov6Pl2EeLSPre3P4xtwdLCKbJrudZD4i07Cl6ICwNSN//h6MJD/kwUIU4k7zeP
ni9WJs+GmLVsVx0bOck=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
W5Ic6b6KWpsR2htHXte3+6CjlmHZcuEa6WOajuu7k286E/JIlKxSU0tNrXH7rL8k7QTBc55tiAC2
sT6Jtn2FOqn9b4N96SwTUIbdNrh5Ew/7EjwCsd26VOwpEgD86kAwm7rEEtRCtStJR4p0yrbCQjf+
9+YuvQ3Ab1Y5fgtY5ijqZPgs+knlZZFAxm+NI7o8f97lEMTpHDonVgfj/KtK8xhV46JSrDB2FPhp
PMezRFDPcrnrGio0JnUe1oPbSneaSJZPAFIoGiaaxfjjDJIOa0DMtbVjecaL42P3+sAmOk0R5Mfk
8MlmwedAmXWwr0D9NdqrNJ68Zt9aVa7CXXiS/Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7632)
`protect data_block
EDmu0UbGevNCld24ne/koL/GopkpLiE5pNSjnyCmXnaKUxgnHPK2f/bzqfBWe2mNT35zVJcI65Xi
rKaj6D415KSvq2+bTnQUnyhb2Y1f8T3figOBKJBCXZxSR5cNNur6mwsFJjYg/n9bkDxpDfZbQES3
IZWaa3ZxCEQpgFl3jN/Tl5jlllK94Xx0Hcazn/iNRXBiZX0t7ypqu93gDbrF3LZpUhDcn+ZMaECa
PBIuu9gmmmaRh0oUKs7PA2W2KInPr0uD3ri5s09ZgGT/CJIJU7xs8343eWqNWK/7bCAhsfCe9CoK
hqXdBVyxc7Ni7kQAu8LEWximU44pRY5lYy13wSC6i0TKht1cKJ0TmudqQfwr2qXIA7N/g0JWg+bG
i/QqDGYJZZMN8F3Rig/nQ7JA9sjn81Onoxsw8aQrJvGNKQiKC/FQfBV0pWbl+qwE9meNrZ2t8Mys
xPcwvkL1FMeq2Xb5lyV7T4t6XsUcgmtP0jErFTnk6aT6W54o4NVicKvCr2kR4a+sYftWdJw/PKr2
dR7pAkb9pSeXB0IlC3LkOvlgjk/HYQYWgaCYTzbVcMkSDoW1r5rjUX2Dd3xGb8/eOPgQnggagnTz
rbzGi+uMCYhLpVERBTw4xJS0uFkMkXABjyQDv246+aZiqmVWmJq87vR+Neo7tkRuGrdDz1MJq6qB
xEZqaEdPf91WcRn7N8AzSrfml1OhO9NUc/dDfQN3KytnP5TM6yMNhwvoTZAG6WVDNVLFHJ9UvCF7
j5Ekez5kajnKc+pJXhM39ycbWtImJdOzcnO1NgYT3v0gRILy7FPHXpUCHd+MWMFvSttD5CYzOKp6
5BG/h1mbTcmu5zvGWK31o2sXM0KfD7QhCIjKxY2TIx7YQqqrb1wvltpaX+NEXzudldcOwwQQcJFG
GZlpvIpZYcLntHCAIF5NEVKsP4IXmjotPT+iZcPY20MAXFIYUhqZnDrlWNVceiewLxgNq+onIj57
lBcuJIGGWBLpUt1pw7l6NQX03fl9RYbqLSKcnYRnhf3Y6eOi2QGVX1y/YcITejuiACeXY/BtAsHh
4rdrQOByx6vQtDINHdfYGoWHq+EG9ctXCPaQ4Y15KTVJU72JIThug7CeRIzhrtkuyFFJxWqz3Hy4
nCrFsPO99u5PO/RmzEuoafgRmP3c2EGvmyA4ONQRz/Xa81IXvQKUtB3PCQgI8AGL5MCjkr6PYInx
ohPfrBI/g+jSyvXue+pO3+ZS38s2XNNI/+R2r0mE6UoQClCkTfB3GCEX24rtHnJliFyzjm3Y2Wxt
GqPQ19/B0a7kmtcT+4Ona9Gev338vla2O9cDv+AUdH41Qa/HPDCmrB9XLmInVI1Ve8A8L/FBPTro
b1/i3nCCKr7WPZR0nxfsOjA3lT4RtUlBZzb/qMBTvtKLot+DJ47N8udcOQEtgDvKVvhlB0IlyJ7f
Lh61js0fTL8X9MAAeRiGoBq/YzSxwvEN65XjwnNSCq8sttg3VrUvV8Zlf3y5us3dgfbFfSqA/S7R
GtzmGuiwi9BcFJ4I1rKNo3kkswehU0V90JMkPr2DnkazRwQP3ejG5HT++Y49ZP3EU36IJM9CNa1g
RGZQrDwe+0/uepbzDTn8TVg8HkSTbCkB46WJuWd//p5beGs0rw3BeQeFdQvNgyqB5hLwC112BsGp
aksL2laXYuJdmgqmT+BtxGFjSIo9sXwBAkpbDdzhMuq/GdJFvmYcEiiyjCIo1p03/Tn/Ux6pWBbF
YTQO6oNqLF4FqAJNv7KQUy13itQG1/O2tkYS2h6CeRPtpzYRqAgKfL28iW2tynNMglKCOi0ovLBA
X7Z2P/kEU3A4ocGQUU/xVtpejyq2ysZcJ8FyebgFGMVzXmbz/E4F/urdanuiU4ZTy0jyD6EyobXR
uKnX06Gcjgc/Ea2iv/zuFamy2p9kBLMKjmYEBrfe1vZ8+P8to/PXIVoHbCivOsQgaCQY52n+NB0D
0gcV5PWVonwGhXfmSSeSbNxByJRXNc9lMPiEgchsjut0SOxDys2t46PW3yoNl0bnad+Eoh4lGgK1
DSjf0xTlkqlgFL/yinctpCWfWGqHOf1+kN8rThNCNs3kTvIaJj6RCkvK43cAUTKrX0I3G82H1Btc
XMKP4yJTq6RE9+Qr8GM59iag4mmVC/nPJwcAOr2NeVn+mfs4McSkbK+pZrekpmxUvkPetQXIqKyy
BCbYkz2WtoN4HlAk0B7L7cdWsTQn4sASM5bUFRFmtWy6I7saHYlSu93TGcm5N/twyVdJLRTiEbvM
VsfUsXvRLk63f3dBWnubQXGxw2jOudwXgLqtf7DqstfdjQFBEuGAoDxKhY8o+9G4YkKAZ5XU8uBv
hYkFxWBdhQOl/wQVpzbu5ThZSkWj+BWkih/wYaikeIxjw+7AGZKqi6Yf0Z+d+3T3rCifC9wyWFXK
pQ/XSkppnkCfS49adnHyFjOVjU5iE0vj5VzJkpDPhnUShR2WYF29+uwrgG7OoqgW+K1XtJr+msjX
ZsLesy2qipRLwkvwM2bxP5+ljldWVWvc7RMie322N2S+LFvWu4BhzPeiSsnldSQqoA6XijOxJFaG
qaUuMfBFXTLwldt3pDhpvIxEBs5OR8X8cTJ9INOcsjPTS4kYjvsl+aXc11UhacBXwNEFj4oa/E1R
DbLb4E0PPF6LLJ8aoBPAoYQTzbTyWngzc1+PjnJDOBY49BzM7iu2wURo7RP0aakl9NkXk2TNo7SU
LjYdbf6nQbH/BKMpbWt8bsv/SyaTzsFpWalXa+MdGimjX5noEqbQZItavXmT9ay+PN8mp+Cq6O6S
o+r+Itl3zLcxGChAKuyMvJSGbjkYT2o+KFRtGLs9WefbDD6WzYEtkjxGijYlAxV8uWsOYaNUKI2w
yaFdlYyQblywkmri5Lsx1cBpMJ73co3M632QsU4CkD3NfKolcgDv8mT5PRitLCSjkjCCU4y9xJKE
K5qmMcTLLHFNkwaPt/pnAKfJfqk16HE8sGimPln3GQJTDvCHpqvENYUq773JKtgeC7nQzPodeNu6
5Xk/5mlLnkjveX9L2mn4efjG8G5q4eTvKfAn//8heUPd0PmW9aiw2ioXECCrE7uBZeX85Vc+RJT+
W5iK7Eau0857QEYUydOdJ3y8a0bCpEG98kqqVO12AQULHoQ9egSZX2/dLOEXh2BKux4vhvvxnGSu
gXz4NHluTKz4jbujCNds1wdNtWvnl/ij773yAYD4MCBoRg6GG9L+JVgGJp1VAuLjXWIaLwXdLu2s
YFzWZMpqdICFzb31OtmMmxCXjl4lJ+PftCfXA4sI9/Z34sByJT1nXk4jELAvzKONy+C0yskijCMP
J/Tk786YdNKAIgT3+7yEbbSZszr+U1IQZtwQZsg2TvRX1e/PRRAFbkH3p2+kmVXqnKFXz6njLOGL
b6G4PRq+EQN12BzvNYPEYHIlR1FN6Kw4bzmrmACLSXgz/JPFci9kDxX8dORLhKU3l19RmBVxtfZf
oauzhjHfyNGC9lfGUrnycQRhoCR1vNm/Eo4EX6seak7jWMZxO6oYti8LiPsSEeVP6kzQbmcDP8mc
rKym/W2hhcQvWRRpsbU8Y4yLS37KGJFhX6UlI8JkUGUJq4ClJ1ifsocFYhCd/tDldeqk/+wCdLPd
Bnsm4u/aNcH1T990tRNwycPFOoT59dp6vnMR+b5mgXq07LTOKWAxWS6OagbJkPJX/+x/IfOUf2yS
PCKcUp5UNUPSPh2tLMe/Pu6tCWucUrOgq/tBj1+Dc2L27PkSvQxwq1Nh0emh6syWwGfHWYytSsbU
cN71KlJQ5Vp5xe9U9mzPFGSDNrgl/XtP0BazIrROjteTQ13IO3saPX2lri63s8JrhYUSyt2uAT1K
NYcmn7qwatw2Ux/6w6ouKmGvxWaEvuGyFChufQl9+L8gOUgODuEyXdkS1NTZMOTkWq89eLi7Qlu/
W4grz4EEGnz5bJiTzZv+HseP1Zs2s6x15UQ8poB6xMPRZCMmwg+iHZFmrzq/neszO4vgqcBz2hDB
39r3ouP0IB6ID8Zlf+h1XOcnpiDoPb7gciZwP9NMX6a9ywWqcAtJ0y2Jl20mrK2MsGTp8r0kLkMp
FV/wdPWD/B0aDgiDg/ZZcUmiKsZWOhj2qLmxJdJessIfBR+DD8Dxmj3ZiRorUzqK1K6dPQ9Fxz9Q
9f+T1zs/yRraT/kLIfzxET9h8N07CdoVNwFks2xq3sNX/whJGRrs7XzK8wYUuYis+P4yLtedjzN1
gGj3blIRSRCqWuFuU6VFvVlxRxsUwqwGPytqAIQbifrx/wNLI1zloNg2wvLpHaopO3ul4/ic2iAS
tp40IuwWcM1Mga6MHaRwK1zDX8IiZVPtMvheU9Fc/tHNkglYcIwb7xLvytqywOmTDJnIKTyA4Mks
N6cXZRLnd9z2nAsPb/CldjC90dzc0HkZma/RP1VgaJDYMq6yEWoMdSmTsu7Hpzx8fXzQdoKbelJE
C2hVT1wPTnbxsWs0l/XaZ5vVLAPqAgccteaQ1l+9i5tTh7uu1gQF20EbwsOCDcEOVvbNinC8oL5K
joeFumzDvwL/I74VkIViTOKEXxQXimT/plHOYWM8nsFqu0GSDxBtp4EJvbJvNThqa5/SiVb4mb0C
1Zh4T6f+sQq9TEbQyYQ4CYczl+Q6oCuaCd6f1SsbLbxZ43s8pvocVeeaTKSenwznWe2NC4PVhVh5
w15yypesqeMU4vneh1sUPGXv61pUpV3OgmLCJgtK+njTto39kdqR2X+xf6/UgungeYijMrIxwigQ
PWcgLscczkW9YbiTwk0II4yycFQGeakp9zAQQyTNTcxzMiW17ftBIhuxE4k4g/OdumgGiq2wFRuY
57vLX5TqTEsYFuvxkrYJlkwONNFW0cFsm3auRkmY/A0W6sL/Aw+3UqeYQ+JnsoK2O2EB4nG/nG2u
6uQFsYlYImCJSAp80asgZhFWVmyqU9lFXI25sXr39mXy00JWtKLGeA4z9guMYh9LT35E5si7+aSt
0hEfJTIJUx7BmlIxVulUnCNII7MPQ3fOPr99QJW9/EbKeCZKvoHL2W+vl7DUSW0bJjYkwJHlNHEQ
yW3mr0GZipZS0Bvx6XvOLIq4PJWC3bB7VUKwRoAFYfoF7AZn/Qlj7gpB+d50jbJ2KKNiIJEgG309
eFRKLWzSM/v0O20DzmXv6l1N/nQCkrHJKEWbdkm4s75UUA0/xxPxQmmBINrws+9FoTPaB5rHOzFr
DTnBkN/ejTIf/FuPaVLqHRfmEee8Jnwdy8vM6Nc720YNcxLYEg57tHKVQFvqsku6XoV6fgnnqLmX
dug0Rs3ahiWBGR2pCep5TjEhIQeAENh0RuHDPfBfWr9z9NYLJtjp0DrKHv2N49Iioa1h2P5ApA7z
PMyTYqCnS2ysK2HOEzAXeuyWewbELA9uMO5M0RUFXR8vKr07Y6wlEwXnPNdKQhxJIdkVNxlWyMvh
T3kLkfpLGusSpvbUaC5fvstxTmrAmC1lxh/F9xES7xRuQ/owcVVUNC2jvi5JqWQNg4dfRtSFtdVF
Lpr5xA01EjVSHHGhXWqxWsKt7Of8omIZ/30ctNVf9ImfXBtHZl4UDLqJqn3Va+STz3BMRvX/MBY4
WLI+KPukoPQkFiH6QcIII0JHwZ0zIXjektVIpAQ+j2JdxxrgClkmXJxiiwvWtF7adj1oMBX1jLfw
XN0RmSuSY8k8zyvGCsX0lMH7vta0PciAuaiigLwKx6AQth1kOA/oKusFd/OTEkHnG5GYnGjCfOEa
2b/zaGhO98WSkmKZeOVtbzFxZxZNcpNzPerzBaOqSpeYPZXpW+4n16Q8SpG1Tccim7TPnJ2vT9C+
Tm0p/J39uCNOvKxUiTNMwtAUD9KA05F7zuVNVIlT4kqLZkZlEz3lo7mnHGyEHEi7cBeHftk4H+jd
WEQtmeuXDPW173UPFt4/v5KLqjSIo8bMSu+24Ce91drx84kAwHu6kJQxu3AHgwuDSBMiRd1d4gvh
6BwubN/eWy/PzaFd/hK9wb2W7T6+dpHRzbGG1cf0VllyAzPRe2Ww/VeX9/iNm23KZeoTmt8k2CfJ
ttP719pHQPAvcC7TyWTl+0nk82LOx/SteFMtANZzKVAOHpqidWQNoBi07v3VZRgBDUselmvvp4MF
uUQ4CwWjIa+X7wkwcTy7S+TOsoHaXCPBCFRqglDzEw2BJYUctxXUuwp71p5ycwwO+m7IDCwsbKLn
8Cstu7QaSR5q9urDbfhJ3plceqJVmFSg81TrIGO3ogoGnO4q9oioZxGJsk9dkQID25YCwVGpyw6w
ytzALd3/zTJ3dFoPuy27lmsND1oQfwb+IJvmZ2e2kHV3VCn1LsE2vlzW4oARZUcBceYbOz2sDK0v
UYdGBIFsqevHkcVi4mi6In4AKqbDThQxqZM9JytEtZIGa66wLIe9b+lUNxeBV0udi//oRwhOSQ+v
mbaKvVDHLUiiG6QSAOmc+0IruhCBnIxFfYLnIknXiV0W6gZo7Aka0kjzWILACutf0IhHq0aQNjDr
CwoWaZnCK/iu+6UHe/FGGlSfMs5Dq1XTnZGdSLG7bV1Asrv3R/2Hn0CAZkgdZ/Q78NnLkMjC1SVt
UWYFJn4fbGXcVB3pseAN7HBxB6ITY6noY3d5iZcFetXOr4bRUJTUhPWqwvQD2YmH8LG28QUAI+7r
w22+1cGdWAErChK62czwXKsHlHaQZcdI1dQIFMslGGWKTY42/jXpk1RtD9GnIMMBmdbj6Jc+PSim
Ly4859exms3GXQVpniR7mWg953OEVrlOVvarX0iksKGXRLqjQ+2GFE5rDo4NBYX3tDhgdAC8Mq5M
sAnSRS0tmXXNnBfFgnJanR7EQnKIRD2obn6+WDGR90nsyy3n84bvXesBN/iLIQY5y3Wh/g/4aeAT
X4otHXGvSOB8vUZ+lLXRo5xjx3bqhMeAhnHUvPg0uan21WoPirzb/LJHi1plRLrdOrZhTFZ6wBAx
6Fk9VV+ZMJxfvQtluIH2WBT3mZphvtJAli7qu8Kj4Dr7kIecbNig7wHbCd4AisVgXfnfM/iLgx4r
/iqLPtLLByCavUs9+4LYOlPwHEWngGO+V7zC7d2h1/JNhJxxYQkBpeP34yAHdZP/G/XQI/xOaEnq
qWMp1pc83Y3YaOEK9N62Zg60lRdgBXiXnfaMP1awjxqr1ixVQPrif5UHRK/H0miEUwBiiGOHtsSw
ecPHHai6qv55NAVrycOJKBPyj8bpyEjwttnVBcmmNLeJKmGrJgH+KLXrPPkW+EWOLFPYTnod+Jvw
RMQdkn5H+9TL+0cc8oBQKtBxlfc+jIZWrdEwFYs2UxElN5GnM4ki3yHTeRHxA9eynxisa40SZ7bx
7jEeceQWyaRhuVYHuOt2WTfX0ibnTo/Nus2TyNlxo/nzafWr7cy3zthPzdhUHG8Wstk717x7LBmx
pyYU+15gTB5I0FN/dwyF83ib1MHyDoZg1Rt6dsmih1lCEfWUmbDgReMZPiBWfVA+p6jUgCTysxml
dCuMHIs4hKm0z46qpfEk9EZKogY332zGWDpWO4SDC4+40U22d+Ee2R5J+KZPPYKc+geUJga++Zkh
bnXiJcjDet/1wBpkgdZCJ8FeV2DWo9tRPr6Kw69Hbs6yIx6G0Z1ARMuMMVSD9kM5CqAVb33gNnqw
ivJ/4et08qGtaQMfPpevRYV6vSJMevt6lRhkfXgKYp8qHg9IVAx0x7zCSYaA8kAr1hZvlfkLGr0r
5CHX8TiyV1kRny+ra3+tfgueZcNMp7n7/5o5kgl/NSFhLzWoDRBcv1Oo6YbTZudKaqvef+vmJcTK
msRgndHCrrDUHUlsjMM77NHZh/I+Ei72VDbn7CzmHj10FSFIG7iz45zdAnKMzfh5korpxIo0i6G6
/JlTecteehQP6E6Gf+tidZKWKpKNW/+9t7S2XXm4AW0IUEaqZjpn21Z6gHVmDEN1iUsy+WQrH+F7
NVvsmRVvq34eNEh2LigrkHxG6ZS3Vtrhr6bnCasqXHcC7KlGeuNegjd9VGVsbpV6ZrCAKZIwXLvJ
IP5FoPYXgUozsl40HeNrJwA6f4VbZ8HGQ6+EkQAvFhXOb7k0gbHjHqbzDg5BprsaI9wC6ANZEUrg
v9t+VCt6frNrbAXVrnjKFraq1cL6KNHEwmQ7WDIyGpoXsV07HlsgFnBhovjrYI2SQMeFZfpaCf9n
05n1QXd4EwVItnq6oW9oNUqw4C4g+hvHwFMQl5hk6pJdka7SOTQdo12KEz1JyUMmIi1bIDc1TKxf
LE08vHsHQGYeKCBD8f0Loiqcq5kn6iHarzQrW/MS6HLYeYdGi3q9Ug1T4pPCZKH8GtIPlnMAHiZd
Ckpn39x1UtfdjehL5IARJw7RFLRmOhgEJG+T7c/Tj6VLJy8nCb1Ln3Ors5IQSmPS9rolc9ygBily
s0L9xWmiicbH5Y0QvjXjss5+uH4OIOg50IX5fvpGhl/7kCDlhFVUw10JYhASRWjmHMzBFG7gjMsw
I7hO2+0jwVno9MtNP6ibt3BBd1Q6PNPqRGYj8NdbpNIquwUBKOqywshCHR6SBy6g4njI4G5KYpxb
ZDiOxwoqbosuFKqXf22On/7GnMHfAIApekqfekIxkFXnYu2Hzz5BDTCOseZ84SWiskvdHyhV/ZVy
gY62JRKlVHme+F5/XVsEzDoy9H9kjtpImQ4+8zpdazsAvTHy/0QHV/RFBlu3ni3i7umy/k5lQQQD
HPb61Mt69nMZL+GM5v7KEZLWKD0ll0xk4YmnuFIpqScm5gtba8p9iOYxkB2FR0gW31dGJuMLoEmx
asJ7MIOiTKrfMLUpZFGUQ3TFjYQCMrhCdBRV2a9VC1uS8Wsg+bexE1kd1D4XSEeacFl/qBlR3MZT
xMCM5B39O/TWASfqfNus3yFwHrFQmvyJdnRCq3yvuQMRsVSKZirCREQks+MHdwcU4DHTHTtUMYtZ
XySDF/PgR906q5v94KVYRdlQaSepxw0VklzYhV999cx3xznsQhfC+6urC9uN7spoUUJRDa4nSYmZ
iwU2DOtP0GCgnMOUFwnaN8YR8RAGLSL7wAJjAHE4FI2PoOUemb4feGOmcZz4wMoXWGKVKh5lMQbX
slaZBy3S5Mhej6CHTiMLz/2pOIBqcX2XjZsmAFoyPQSnv89tNMrfq0VhEIdmXuM0YiYxKwyUdBnw
sEwg7NNw9ZRItnHOEhopXUvpJNKyfs4qREJubFtp8XmCt7VF87fPX7jJks99ggHjCiIEvdd3hZUw
7b3jFkODFkI8TWQ108Ka4NRnux4IxsF4wosMH0JqjD7OfXMwRrwlzyqYNbQx43YLEDqUAWxisq++
inDpAox9HEnGHJgRttKeTdS0hnrHpnH0EPUNud7nu2OevP252T7Gp51gdmsnZ0Llzp7Vpg2mPFqE
BtvH065zl0ajmpREJgVHoM4Tud1gRxWRHtz4nTPAR+1MiqVyd3Dmho9NR73Ap+dqi1kiOpMGtIxJ
zDPwVUfS0wOX991fr9TiqIfVRqZCmKhj1SLd/6z0SDFOjYmiOLhnqDI2VK70T939GcRZ/DLsnEAx
np7igBUUoDe/Vhzc9AU2ife8/8CjJKXTFlgGaQ32UBKMKC1qJbFtqVAcYKGZsxihboJktlI7qdNU
dtVlRG2zqsTg/UvJzvzKMJyj9wllCsEcDvtCQlK520HZf64innN19hZZzZZfJucR8on3C4Oa/F80
RXBYcX9amD/MCINRJxq1GTsi/cag+KF02Cf6g8R48dj1wMuuEPEKpB+w5GRLWJfIcXmqPrd+vLfU
RbOXbO4ITcJ5hCe3xeIKt59gzp0aK+HQT+CYJqW90o/R3OrHrbc6NQ3R1BZSsLTU1aDVG96KC/xS
hMVf9DC5hvX2itLcnkl3A1B1OjTEs9FIsCuvGJ8NhCBQ4PHvN3hktB7LLVHkf+0weec3PFE1ZXLc
mkTk9DvX8n9wl/sHdXvcyQNZOwii4N73IAhUj1F0f7U7iOohIaw5p1c9ISwk/JOsFx/V7rFIzolu
7aDzRnSJHqfWc2bLA+wNJ/w9YWpmLkHezvmcp0ZsyAPvN8EM/Y3+/QSfgX+e0N2amk2BGkY093V6
19xKjAnp2VDCSB3RZwN11/5Qc8+t3Y6+xq4+MKT+xinEj5Poc95b9zwWrKQ3Yl7YpGvG
`protect end_protected
| bsd-2-clause | 90f218239c0cbf0446bd03ea7566fffe | 0.929999 | 1.887696 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/csr.vhd | 1 | 31,959 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity CsrRegs is
generic (
hartid : integer;
async_reset : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
i_mret : in std_logic; -- mret instruction signals mode switching
i_uret : in std_logic; -- uret instruction signals mode switching
i_sp : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Stack Pointer for the borders control
i_addr : in std_logic_vector(11 downto 0); -- CSR address, if xret=1 switch mode accordingly
i_wena : in std_logic; -- Write enable
i_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- CSR writing value
o_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0); -- CSR read value
o_mepc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_uepc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_trap_ready : in std_logic; -- Trap branch request was accepted
i_e_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_e_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ex_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ex_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Data path: address must be equal to the latest request address
i_ex_data_load_fault : in std_logic; -- Data path: Bus response with SLVERR or DECERR on read
i_ex_data_store_fault : in std_logic; -- Data path: Bus response with SLVERR or DECERR on write
i_ex_data_store_fault_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ex_instr_load_fault : in std_logic;
i_ex_illegal_instr : in std_logic;
i_ex_unalign_store : in std_logic;
i_ex_unalign_load : in std_logic;
i_ex_mpu_store : in std_logic;
i_ex_mpu_load : in std_logic;
i_ex_breakpoint : in std_logic;
i_ex_ecall : in std_logic;
i_ex_fpu_invalidop : in std_logic; -- FPU Exception: invalid operation
i_ex_fpu_divbyzero : in std_logic; -- FPU Exception: divide by zero
i_ex_fpu_overflow : in std_logic; -- FPU Exception: overflow
i_ex_fpu_underflow : in std_logic; -- FPU Exception: underflow
i_ex_fpu_inexact : in std_logic; -- FPU Exception: inexact
i_fpu_valid : in std_logic; -- FPU output is valid
i_irq_external : in std_logic;
i_e_next_ready: in std_logic;
i_e_valid : in std_logic;
o_executed_cnt : out std_logic_vector(63 downto 0); -- Number of executed instructions
o_trap_valid : out std_logic; -- Trap pulse
o_trap_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- trap on pc
o_dbg_pc_write : out std_logic; -- Modify pc via debug interface
o_dbg_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Writing value into pc register
o_progbuf_ena : out std_logic; -- Execution from prog buffer
o_progbuf_pc : out std_logic_vector(31 downto 0); -- prog buffer instruction counter
o_progbuf_data : out std_logic_vector(31 downto 0); -- prog buffer instruction opcode
o_flushi_ena : out std_logic; -- clear specified addr in ICache without execution of fence.i
o_flushi_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- ICache address to flush
o_mpu_region_we : out std_logic;
o_mpu_region_idx : out std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
o_mpu_region_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_mpu_region_mask : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_mpu_region_flags : out std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0); -- {ena, cachable, r, w, x}
i_dport_ena : in std_logic; -- Debug port request is enabled
i_dport_write : in std_logic; -- Debug port Write enable
i_dport_addr : in std_logic_vector(11 downto 0); -- Debug port CSR address
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Debug port CSR writing value
o_dport_valid : out std_logic; -- Debug read data is valid
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Debug port CSR read value
o_halt : out std_logic
);
end;
architecture arch_CsrRegs of CsrRegs is
type RegistersType is record
mtvec : std_logic_vector(RISCV_ARCH-1 downto 0);
mscratch : std_logic_vector(RISCV_ARCH-1 downto 0);
mstackovr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
mstackund : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
mbadaddr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
mode : std_logic_vector(1 downto 0);
uie : std_logic; -- User level interrupts ena for current priv. mode
mie : std_logic; -- Machine level interrupts ena for current priv. mode
mpie : std_logic; -- Previous MIE value
mstackovr_ena : std_logic; -- Stack Overflow control enabled
mstackund_ena : std_logic; -- Stack Underflow control enabled
mpp : std_logic_vector(1 downto 0); -- Previous mode
mepc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
uepc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
ext_irq : std_logic;
mpu_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
mpu_mask : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
mpu_idx : std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
mpu_flags : std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
mpu_we : std_logic;
ex_fpu_invalidop : std_logic; -- FPU Exception: invalid operation
ex_fpu_divbyzero : std_logic; -- FPU Exception: divide by zero
ex_fpu_overflow : std_logic; -- FPU Exception: overflow
ex_fpu_underflow : std_logic; -- FPU Exception: underflow
ex_fpu_inexact : std_logic; -- FPU Exception: inexact
trap_irq : std_logic;
trap_code : std_logic_vector(4 downto 0);
trap_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
break_event : std_logic;
hold_data_store_fault : std_logic;
hold_data_load_fault : std_logic;
hold_mbadaddr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
timer : std_logic_vector(63 downto 0); -- Timer in clocks.
cycle_cnt : std_logic_vector(63 downto 0); -- Cycle in clocks.
executed_cnt : std_logic_vector(63 downto 0); -- Number of valid executed instructions
break_mode : std_logic; -- Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
halt : std_logic;
halt_cause : std_logic_vector(2 downto 0); -- 1=ebreak instruction; 2=breakpoint exception; 3=haltreq; 4=step
progbuf_ena : std_logic;
progbuf_data : std_logic_vector(CFG_PROGBUF_REG_TOTAL*32-1 downto 0);
progbuf_data_out : std_logic_vector(31 downto 0);
progbuf_data_pc : std_logic_vector(4 downto 0);
progbuf_data_npc : std_logic_vector(4 downto 0);
progbuf_err : std_logic_vector(2 downto 0); -- 1=busy;2=cmd not supported;3=exception;4=halt/resume;5=bus error
stepping_mode : std_logic;
stepping_mode_cnt : std_logic_vector(RISCV_ARCH-1 downto 0);
ins_per_step : std_logic_vector(RISCV_ARCH-1 downto 0); -- Number of steps before halt in stepping mode
flushi_ena : std_logic;
flushi_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
end record;
constant R_RESET : RegistersType := (
(others => '0'), -- mtvec
(others => '0'), -- mscratch
(others => '0'), -- mstackovr
(others => '0'), -- mstackund
(others => '0'), -- mbadaddr
PRV_M, -- mode
'0', '0', '0',
'0', -- mstackovr_ena
'0', -- mstackund_ena
(others => '0'), --mpp
(others => '0'), -- mepc
(others => '0'), -- uepc
'0', -- ext_irq
(others => '0'), -- mpu_addr
(others => '0'), -- mpu_mask
(others => '0'), -- mpu_idx
(others => '0'), -- mpu_flags
'0', -- mpu_we
'0', '0', '0', '0', '0',
'0', (others => '0'), (others => '0'), '0',
'0', '0', (others => '0'),
(others => '0'), --timer
(others => '0'), --cycle_cnt
(others => '0'), -- executed_cnt
'0', -- break_mode
'0', -- halt
(others => '0'), -- halt_cause
'0', -- progbuf_ena
(others => '0'), -- progbuf_data
(others => '0'), -- progbuf_data_out
(others => '0'), -- progbuf_data_pc
(others => '0'), -- progbuf_data_npc
PROGBUF_ERR_NONE,-- progbuf_err
'0', -- stepping_mode
(others => '0'), -- stepping_mode_cnt
conv_std_logic_vector(1, RISCV_ARCH), -- ins_per_step
'0', -- flushi_ena
(others => '0') -- flushi_addr
);
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_mret, i_uret, i_sp, i_addr, i_wena, i_wdata, i_trap_ready,
i_e_pc, i_e_npc, i_ex_npc, i_ex_data_addr, i_ex_data_load_fault, i_ex_data_store_fault,
i_ex_data_store_fault_addr,
i_ex_instr_load_fault, i_ex_illegal_instr, i_ex_unalign_load, i_ex_unalign_store,
i_ex_mpu_store, i_ex_mpu_load, i_ex_breakpoint, i_ex_ecall,
i_ex_fpu_invalidop, i_ex_fpu_divbyzero, i_ex_fpu_overflow,
i_ex_fpu_underflow, i_ex_fpu_inexact, i_fpu_valid, i_irq_external,
i_e_next_ready, i_e_valid,
i_dport_ena, i_dport_write, i_dport_addr, i_dport_wdata,
r)
variable v : RegistersType;
variable w_ie : std_logic;
variable w_ext_irq : std_logic;
variable w_trap_valid : std_logic;
variable wb_trap_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable v_dbg_pc_write : std_logic;
variable vb_dbg_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable w_trap_irq : std_logic;
variable w_exception_xret : std_logic;
variable wb_trap_code : std_logic_vector(4 downto 0);
variable wb_mbadaddr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable w_mstackovr : std_logic;
variable w_mstackund : std_logic;
variable vb_csr_addr : std_logic_vector(11 downto 0);
variable vb_csr_wdata : std_logic_vector(RISCV_ARCH-1 downto 0);
variable v_csr_wena : std_logic;
variable v_dport_valid : std_logic;
variable vb_rdata : std_logic_vector(RISCV_ARCH-1 downto 0);
variable v_cur_halt : std_logic;
variable v_req_halt : std_logic;
variable v_req_resume : std_logic;
variable v_req_progbuf : std_logic;
variable v_clear_progbuferr : std_logic;
variable tidx : integer range 0 to 15;
variable tnpc : integer;
begin
v := r;
vb_rdata := (others => '0');
v_dbg_pc_write := '0';
vb_dbg_pc := (others => '0');
v_cur_halt := '0';
v_req_halt := '0';
v_req_resume := '0';
v_req_progbuf := '0';
v_clear_progbuferr := '0';
v.flushi_ena := '0';
v.flushi_addr := (others => '0');
tnpc := 16*conv_integer(r.progbuf_data_npc);
if i_wena = '1' then
vb_csr_addr := i_addr;
vb_csr_wdata := i_wdata;
v_csr_wena := '1';
v_dport_valid := '0';
else
vb_csr_addr := i_dport_addr;
v_csr_wena := i_dport_ena and i_dport_write;
vb_csr_wdata := i_dport_wdata;
v_dport_valid := '1';
end if;
tidx := conv_integer(vb_csr_wdata(35 downto 32));
case vb_csr_addr is
when CSR_fflags =>
vb_rdata(0) := r.ex_fpu_inexact;
vb_rdata(1) := r.ex_fpu_underflow;
vb_rdata(2) := r.ex_fpu_overflow;
vb_rdata(3) := r.ex_fpu_divbyzero;
vb_rdata(4) := r.ex_fpu_invalidop;
if CFG_HW_FPU_ENABLE then
if v_csr_wena = '1' then
v.ex_fpu_inexact := vb_csr_wdata(0);
v.ex_fpu_underflow := vb_csr_wdata(1);
v.ex_fpu_overflow := vb_csr_wdata(2);
v.ex_fpu_divbyzero := vb_csr_wdata(3);
v.ex_fpu_invalidop := vb_csr_wdata(4);
end if;
end if;
when CSR_frm =>
if CFG_HW_FPU_ENABLE then
vb_rdata(2 downto 0) := "100"; -- Round mode: round to Nearest (RMM)
end if;
when CSR_fcsr =>
vb_rdata(0) := r.ex_fpu_inexact;
vb_rdata(1) := r.ex_fpu_underflow;
vb_rdata(2) := r.ex_fpu_overflow;
vb_rdata(3) := r.ex_fpu_divbyzero;
vb_rdata(4) := r.ex_fpu_invalidop;
if CFG_HW_FPU_ENABLE then
vb_rdata(7 downto 5) := "100"; -- Round mode: round to Nearest (RMM)
if v_csr_wena = '1' then
v.ex_fpu_inexact := vb_csr_wdata(0);
v.ex_fpu_underflow := vb_csr_wdata(1);
v.ex_fpu_overflow := vb_csr_wdata(2);
v.ex_fpu_divbyzero := vb_csr_wdata(3);
v.ex_fpu_invalidop := vb_csr_wdata(4);
end if;
end if;
when CSR_misa =>
--! Base[XLEN-1:XLEN-2]
--! 1 = 32
--! 2 = 64
--! 3 = 128
--!
vb_rdata(RISCV_ARCH-1 downto RISCV_ARCH-2) := "10";
--! BitCharacterDescription
--! 0 A Atomic extension
--! 1 B Tentatively reserved for Bit operations extension
--! 2 C Compressed extension
--! 3 D Double-precision Foating-point extension
--! 4 E RV32E base ISA (embedded)
--! 5 F Single-precision Foating-point extension
--! 6 G Additional standard extensions present
--! 7 H Hypervisor mode implemented
--! 8 I RV32I/64I/128I base ISA
--! 9 J Reserved
--! 10 K Reserved
--! 11 L Tentatively reserved for Decimal Floating-Point extension
--! 12 M Integer Multiply/Divide extension
--! 13 N User-level interrupts supported
--! 14 O Reserved
--! 15 P Tentatively reserved for Packed-SIMD extension
--! 16 Q Quad-precision Foating-point extension
--! 17 R Reserved
--! 18 S Supervisor mode implemented
--! 19 T Tentatively reserved for Transactional Memory extension
--! 20 U User mode implemented
--! 21 V Tentatively reserved for Vector extension
--! 22 W Reserved
--! 23 X Non-standard extensions present
--! 24 Y Reserved
--! 25 Z Reserve
--!
vb_rdata(8) := '1';
vb_rdata(12) := '1';
vb_rdata(20) := '1';
vb_rdata(2) := '1';
if CFG_HW_FPU_ENABLE then
vb_rdata(3) := '1';
end if;
when CSR_mvendorid =>
vb_rdata(31 downto 0) := CFG_VENDOR_ID;
when CSR_marchid =>
when CSR_mimplementationid =>
vb_rdata(31 downto 0) := CFG_IMPLEMENTATION_ID;
when CSR_mhartid =>
vb_rdata(31 downto 0) := conv_std_logic_vector(hartid, 32);
when CSR_uepc => -- User mode program counter
vb_rdata(CFG_CPU_ADDR_BITS-1 downto 0) := r.uepc;
if v_csr_wena = '1' then
v.uepc := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
end if;
when CSR_mstatus => -- Machine mode status register
vb_rdata(0) := r.uie;
vb_rdata(3) := r.mie;
vb_rdata(7) := r.mpie;
vb_rdata(12 downto 11) := r.mpp;
if CFG_HW_FPU_ENABLE then
vb_rdata(14 downto 13) := "01"; -- FS field: Initial state
end if;
vb_rdata(33 downto 32) := "10"; -- UXL: User mode supported 64-bits
if v_csr_wena = '1' then
v.uie := vb_csr_wdata(0);
v.mie := vb_csr_wdata(3);
v.mpie := vb_csr_wdata(7);
v.mpp := vb_csr_wdata(12 downto 11);
end if;
when CSR_medeleg => -- Machine exception delegation
when CSR_mideleg => -- Machine interrupt delegation
when CSR_mie => -- Machine interrupt enable bit
when CSR_mtvec =>
vb_rdata := r.mtvec;
if v_csr_wena = '1' then
v.mtvec := vb_csr_wdata;
end if;
when CSR_mscratch => -- Machine scratch register
vb_rdata := r.mscratch;
if v_csr_wena = '1' then
v.mscratch := vb_csr_wdata;
end if;
when CSR_mepc => -- Machine program counter
vb_rdata(CFG_CPU_ADDR_BITS-1 downto 0) := r.mepc;
if v_csr_wena = '1' then
v.mepc := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
end if;
when CSR_mcause => -- Machine trap cause
vb_rdata(63) := r.trap_irq;
vb_rdata(4 downto 0) := r.trap_code;
when CSR_mbadaddr => -- Machine bad address
vb_rdata(CFG_CPU_ADDR_BITS-1 downto 0) := r.mbadaddr;
when CSR_mip => -- Machine interrupt pending
when CSR_cycle =>
vb_rdata := r.cycle_cnt;
when CSR_time =>
vb_rdata := r.timer;
when CSR_insret =>
vb_rdata := r.executed_cnt;
when CSR_mstackovr => -- Machine stack overflow
vb_rdata(CFG_CPU_ADDR_BITS-1 downto 0) := r.mstackovr;
if v_csr_wena = '1' then
v.mstackovr := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
v.mstackovr_ena := or_reduce(vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0));
end if;
when CSR_mstackund => -- Machine stack underflow
vb_rdata(CFG_CPU_ADDR_BITS-1 downto 0) := r.mstackund;
if v_csr_wena = '1' then
v.mstackund := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
v.mstackund_ena := or_reduce(vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0));
end if;
when CSR_mpu_addr =>
if v_csr_wena = '1' then
v.mpu_addr := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
end if;
when CSR_mpu_mask =>
if v_csr_wena = '1' then
v.mpu_mask := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
end if;
when CSR_mpu_ctrl =>
vb_rdata(15 downto 8) := conv_std_logic_vector(CFG_MPU_TBL_SIZE, 8);
if v_csr_wena = '1' then
v.mpu_idx := vb_csr_wdata(8+CFG_MPU_TBL_WIDTH-1 downto 8);
v.mpu_flags := vb_csr_wdata(CFG_MPU_FL_TOTAL-1 downto 0);
v.mpu_we := '1';
end if;
when CSR_runcontrol =>
if v_csr_wena = '1' then
v_req_halt := vb_csr_wdata(31);
v_req_resume := vb_csr_wdata(30);
if vb_csr_wdata(27) = '1' then
if r.halt = '1' then
v_req_progbuf := '1';
else
v.progbuf_err := PROGBUF_ERR_HALT_RESUME;
end if;
end if;
end if;
when CSR_insperstep =>
vb_rdata := r.ins_per_step;
if v_csr_wena = '1' then
v.ins_per_step := vb_csr_wdata;
if or_reduce(vb_csr_wdata) = '0' then
v.ins_per_step := conv_std_logic_vector(1, RISCV_ARCH); -- cannot be zero
end if;
if r.halt = '1' then
v.stepping_mode_cnt := vb_csr_wdata;
end if;
end if;
when CSR_progbuf =>
if v_csr_wena = '1' then
v.progbuf_data(32*tidx+31 downto 32*tidx) := vb_csr_wdata(31 downto 0);
end if;
when CSR_abstractcs =>
vb_rdata(28 downto 24) := conv_std_logic_vector(CFG_PROGBUF_REG_TOTAL, 5);
vb_rdata(12) := r.progbuf_ena; -- busy
vb_rdata(10 downto 8) := r.progbuf_err;
vb_rdata(3 downto 0) := conv_std_logic_vector(CFG_DATA_REG_TOTAL, 4);
if v_csr_wena = '1' then
v_clear_progbuferr := vb_csr_wdata(8); -- W1C err=1
end if;
when CSR_flushi =>
if v_csr_wena = '1' then
v.flushi_ena := '1';
v.flushi_addr := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
end if;
when CSR_dcsr =>
vb_rdata(31 downto 28) := "0100"; -- xdebugver: 4=External debug supported
vb_rdata(8 downto 6) := r.halt_cause; -- cause:
vb_rdata(2) := r.stepping_mode; -- step: before resumereq
vb_rdata(1 downto 0) := "11"; -- prv: privilege in debug mode: 3=machine
if v_csr_wena = '1' then
v.stepping_mode := vb_csr_wdata(2);
if vb_csr_wdata(2) = '1' then
v.stepping_mode_cnt := r.ins_per_step; -- default =1
end if;
end if;
when CSR_dpc =>
-- Upon entry into debug mode DPC must contains:
-- cause | Address
-- -------------------|----------------
-- ebreak | Address of ebreak instruction
-- single step | Address of next instruction to be executed
-- trigger (HW BREAK) | if timing=0, cause isntruction, if timing=1 enxt instruction
-- halt request | next instruction
--
if r.halt_cause = HALT_CAUSE_EBREAK then
vb_rdata(CFG_CPU_ADDR_BITS-1 downto 0) := i_e_pc;
else
vb_rdata(CFG_CPU_ADDR_BITS-1 downto 0) := i_e_npc;
end if;
if v_csr_wena = '1' then
v_dbg_pc_write := '1';
vb_dbg_pc := vb_csr_wdata(CFG_CPU_ADDR_BITS-1 downto 0);
end if;
when others =>
end case;
if r.mpu_we = '1' then
v.mpu_we := '0';
end if;
w_ie := '0';
if (r.mode /= PRV_M) or r.mie = '1' then
w_ie := '1';
end if;
w_ext_irq := i_irq_external and w_ie;
if i_trap_ready = '1' then
v.ext_irq := w_ext_irq;
end if;
w_exception_xret := '0';
if (i_mret = '1' and r.mode /= PRV_M) or
(i_uret = '1' and r.mode /= PRV_U) then
w_exception_xret := '1';
end if;
w_mstackovr := '0';
if i_sp(CFG_CPU_ADDR_BITS-1 downto 0) < r.mstackovr then
w_mstackovr := '1';
end if;
w_mstackund := '0';
if i_sp(CFG_CPU_ADDR_BITS-1 downto 0) > r.mstackund then
w_mstackund := '1';
end if;
if i_fpu_valid = '1' then
v.ex_fpu_invalidop := i_ex_fpu_invalidop;
v.ex_fpu_divbyzero := i_ex_fpu_divbyzero;
v.ex_fpu_overflow := i_ex_fpu_overflow;
v.ex_fpu_underflow := i_ex_fpu_underflow;
v.ex_fpu_inexact := i_ex_fpu_inexact;
end if;
w_trap_valid := '0';
w_trap_irq := '0';
wb_trap_code := (others => '0');
v.break_event := '0';
wb_trap_pc := r.mtvec(CFG_CPU_ADDR_BITS-1 downto 0);
wb_mbadaddr := i_e_npc;
if i_ex_instr_load_fault = '1' then
w_trap_valid := '1';
wb_trap_pc := CFG_NMI_INSTR_FAULT_ADDR;
wb_trap_code := EXCEPTION_InstrFault;
-- illegal address instruction can generate any other exceptions
v.hold_data_load_fault := '0';
v.hold_data_store_fault := '0';
elsif i_ex_illegal_instr = '1' or w_exception_xret = '1' then
w_trap_valid := '1';
wb_trap_pc := CFG_NMI_INSTR_ILLEGAL_ADDR;
wb_trap_code := EXCEPTION_InstrIllegal;
-- illegal instruction can generate any other exceptions
v.hold_data_load_fault := '0';
v.hold_data_store_fault := '0';
elsif i_ex_breakpoint = '1' then
v.break_event := '1';
w_trap_valid := '1';
wb_trap_code := EXCEPTION_Breakpoint;
if r.break_mode = '0' then
wb_trap_pc := i_e_npc;
else
wb_trap_pc := CFG_NMI_BREAKPOINT_ADDR;
end if;
elsif i_ex_unalign_load = '1' then
w_trap_valid := '1';
wb_trap_pc := CFG_NMI_LOAD_UNALIGNED_ADDR;
wb_trap_code := EXCEPTION_LoadMisalign;
elsif i_ex_data_load_fault = '1' or r.hold_data_load_fault = '1' then
w_trap_valid := '1';
v.hold_data_load_fault := '0';
if i_trap_ready = '0' then
v.hold_data_load_fault := '1';
end if;
wb_trap_pc := CFG_NMI_LOAD_FAULT_ADDR;
if i_ex_data_load_fault = '1' then
wb_mbadaddr := i_ex_data_addr; -- miss-access read data address
v.hold_mbadaddr := i_ex_data_addr;
else
wb_mbadaddr := r.hold_mbadaddr;
end if;
wb_trap_code := EXCEPTION_LoadFault;
elsif i_ex_unalign_store = '1' then
w_trap_valid := '1';
wb_trap_pc := CFG_NMI_STORE_UNALIGNED_ADDR;
wb_trap_code := EXCEPTION_StoreMisalign;
elsif i_ex_data_store_fault = '1' or r.hold_data_store_fault = '1' then
w_trap_valid := '1';
v.hold_data_store_fault := '0';
if i_trap_ready = '0' then
v.hold_data_store_fault := '1';
end if;
wb_trap_pc := CFG_NMI_STORE_FAULT_ADDR;
if i_ex_data_store_fault = '1' then
wb_mbadaddr := i_ex_data_store_fault_addr; -- miss-access write data address
v.hold_mbadaddr := i_ex_data_store_fault_addr;
else
wb_mbadaddr := r.hold_mbadaddr;
end if;
wb_trap_code := EXCEPTION_StoreFault;
elsif i_ex_ecall = '1' then
w_trap_valid := '1';
if r.mode = PRV_M then
wb_trap_pc := CFG_NMI_CALL_FROM_MMODE_ADDR;
wb_trap_code := EXCEPTION_CallFromMmode;
else
wb_trap_pc := CFG_NMI_CALL_FROM_UMODE_ADDR;
wb_trap_code := EXCEPTION_CallFromUmode;
end if;
elsif r.mstackovr_ena = '1' and w_mstackovr = '1' then
w_trap_valid := '1';
wb_trap_pc := CFG_NMI_STACK_OVERFLOW_ADDR;
wb_trap_code := EXCEPTION_StackOverflow;
if i_trap_ready = '1' then
v.mstackovr := (others => '0');
v.mstackovr_ena := '0';
end if;
elsif r.mstackund_ena = '1' and w_mstackund = '1' then
w_trap_valid := '1';
wb_trap_pc := CFG_NMI_STACK_UNDERFLOW_ADDR;
wb_trap_code := EXCEPTION_StackUnderflow;
if i_trap_ready = '1' then
v.mstackund := (others => '0');
v.mstackund_ena := '0';
end if;
elsif w_ext_irq = '1' and r.ext_irq = '0' then
w_trap_valid := '1';
wb_trap_pc := r.mtvec(CFG_CPU_ADDR_BITS-1 downto 0);
wb_trap_code := INTERRUPT_MExternal;
w_trap_irq := '1';
end if;
if (not w_exception_xret and (i_mret or i_uret)) = '1' then
-- Switch to previous mode
v.mie := r.mpie;
v.mpie := '1';
v.mode := r.mpp;
v.mpp := PRV_U;
end if;
-- Behaviour on EBREAK instruction defined by 'i_break_mode':
-- 0 = halt;
-- 1 = generate trap
if (w_trap_valid and i_trap_ready and (r.break_mode or not i_ex_breakpoint)) = '1' then
v.mie := '0';
v.mpp := r.mode;
v.mepc := i_ex_npc;
v.mbadaddr := wb_mbadaddr;
v.trap_code := wb_trap_code;
v.trap_irq := w_trap_irq;
v.mode := PRV_M;
case r.mode is
when PRV_U =>
v.mpie := r.uie;
when PRV_M =>
v.mpie := r.mie;
when others =>
end case;
end if;
if r.halt = '0' or i_e_next_ready = '1' then
v.cycle_cnt := r.cycle_cnt + 1;
end if;
if i_e_next_ready = '1' then
v.executed_cnt := r.executed_cnt + 1;
end if;
v.timer := r.timer + 1;
if i_e_next_ready = '1' then
if r.progbuf_ena = '1' then
v.progbuf_data_out := r.progbuf_data(tnpc + 31 downto tnpc);
v.progbuf_data_pc := r.progbuf_data_npc;
if r.progbuf_data(tnpc + 1 downto tnpc) = "11" then
v.progbuf_data_npc := r.progbuf_data_npc + 2;
else
v.progbuf_data_npc := r.progbuf_data_npc + 1;
end if;
if and_reduce(r.progbuf_data_pc(4 downto 1)) = '1' then
-- use end of buffer as a watchdog
v.progbuf_ena := '0';
v.halt := '1';
end if;
elsif or_reduce(r.stepping_mode_cnt) = '1' then
v.stepping_mode_cnt := r.stepping_mode_cnt - 1;
if or_reduce(r.stepping_mode_cnt(RISCV_ARCH-1 downto 1)) = '0' then
v.halt := '1';
v_cur_halt := '1';
v.stepping_mode := '0';
v.halt_cause := HALT_CAUSE_STEP;
end if;
end if;
end if;
if r.break_event = '1' then
if r.progbuf_ena = '1' then
v.halt := '1'; -- do not modify halt cause in debug mode
v.progbuf_ena := '0';
else
if r.break_mode = '0' then
v.halt := '1';
v.halt_cause := HALT_CAUSE_EBREAK;
end if;
end if;
elsif v_req_halt = '1' and r.halt = '0' then
if r.progbuf_ena = '0' and r.stepping_mode = '0' then
v.halt := '1';
v.halt_cause := HALT_CAUSE_HALTREQ;
end if;
elsif v_req_progbuf = '1' then
v.progbuf_ena := '1';
v.progbuf_data_out := r.progbuf_data(31 downto 0);
v.progbuf_data_pc := (others => '0');
if r.progbuf_data(1 downto 0) = "11" then
v.progbuf_data_npc := "00010";
else
v.progbuf_data_npc := "00001";
end if;
v.halt := '0';
elsif v_req_resume = '1' and r.halt = '1' then
v.halt := '0';
end if;
if v_clear_progbuferr = '1' then
v.progbuf_err := PROGBUF_ERR_NONE;
elsif r.progbuf_ena = '1' then
if i_ex_data_load_fault = '1'
or i_ex_data_store_fault = '1' then
v.progbuf_err := PROGBUF_ERR_EXCEPTION;
elsif i_ex_unalign_store = '1'
or i_ex_unalign_load = '1'
or i_ex_mpu_store = '1'
or i_ex_mpu_load = '1' then
v.progbuf_err := PROGBUF_ERR_BUS;
end if;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
o_executed_cnt <= r.executed_cnt;
o_trap_valid <= w_trap_valid;
o_trap_pc <= wb_trap_pc;
o_dbg_pc_write <= v_dbg_pc_write;
o_dbg_pc <= vb_dbg_pc;
o_rdata <= vb_rdata;
o_mepc <= r.mepc;
o_uepc <= r.uepc;
o_dport_valid <= v_dport_valid;
o_dport_rdata <= vb_rdata;
o_mpu_region_we <= r.mpu_we;
o_mpu_region_idx <= r.mpu_idx;
o_mpu_region_addr <= r.mpu_addr;
o_mpu_region_mask <= r.mpu_mask;
o_mpu_region_flags <= r.mpu_flags;
o_progbuf_ena <= r.progbuf_ena;
o_progbuf_pc <= X"000000" & "00" & r.progbuf_data_pc & '0';
o_progbuf_data <= r.progbuf_data_out;
o_flushi_ena <= r.flushi_ena;
o_flushi_addr <= r.flushi_addr;
o_halt <= r.halt or v_cur_halt;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | d9d32425ec4ae75ad3504a320d7b5af4 | 0.544166 | 3.1959 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/kc705_gnss/top_kc705_gnss.vhd | 1 | 13,644 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
-- "Virtual" memory banks
use techmap.types_mem.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity top_kc705_gnss is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end top_kc705_gnss;
architecture arch_top_kc705_gnss of top_kc705_gnss is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal ib_clk_adc : std_logic;
signal ib_gps_I : std_logic_vector(1 downto 0);
signal ib_gps_Q : std_logic_vector(1 downto 0);
signal ib_glo_I : std_logic_vector(1 downto 0);
signal ib_glo_Q : std_logic_vector(1 downto 0);
signal ob_pps : std_logic;
signal ib_gps_ld : std_logic;
signal ib_glo_ld : std_logic;
signal ob_max_sclk : std_logic;
signal ob_max_sdata : std_logic;
signal ob_max_ncs : std_logic_vector(1 downto 0);
signal ib_antext_stat : std_logic;
signal ib_antext_detect : std_logic;
signal ob_antext_ena : std_logic;
signal ob_antint_contr : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! GNSS sub-system
iclkadc0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
adcx : for i in 0 to 1 generate
igpsi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_I(i), i_gps_I(i));
igpsq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_Q(i), i_gps_Q(i));
igloi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_I(i), i_glo_I(i));
igloq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_Q(i), i_glo_Q(i));
end generate;
opps0 : obuf_tech generic map(CFG_PADTECH) port map (o_pps, ob_pps);
igpsld0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_ld, i_gps_ld);
iglold0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_ld, i_glo_ld);
omaxclk0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sclk, ob_max_sclk);
omaxdat0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sdata, ob_max_sdata);
omaxcs0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(0), ob_max_ncs(0));
omaxcs1 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(1), ob_max_ncs(1));
iantstat0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_stat, i_antext_stat);
iantdet0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_detect, i_antext_detect);
oanten0 : obuf_tech generic map(CFG_PADTECH) port map (o_antext_ena, ob_antext_ena);
oantctr0 : obuf_tech generic map(CFG_PADTECH) port map (o_antint_contr, ob_antint_contr);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GPT
o_pwm => open,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => '0',
o_flash_so => open,
o_flash_sck => open,
o_flash_csn => open,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => X"0000",
o_otp_d => open,
o_otp_a => open,
o_otp_we => open,
o_otp_re => open,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => ib_clk_adc,
i_gps_I => ib_gps_I,
i_gps_Q => ib_gps_Q,
i_glo_I => ib_glo_I,
i_glo_Q => ib_glo_Q,
o_pps => ob_pps,
i_gps_ld => ib_gps_ld,
i_glo_ld => ib_glo_ld,
o_max_sclk => ob_max_sclk,
o_max_sdata => ob_max_sdata,
o_max_ncs => ob_max_ncs,
i_antext_stat => ib_antext_stat,
i_antext_detect => ib_antext_detect,
o_antext_ena => ob_antext_ena,
o_antint_contr => ob_antint_contr
);
end arch_top_kc705_gnss;
| apache-2.0 | 5bc8efdfb4c2f14f76e46377173f743f | 0.624157 | 2.783354 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/kc705_gnss/config_k7.vhd | 1 | 2,739 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := kintex7;
constant CFG_MEMTECH : integer := kintex7;
constant CFG_PADTECH : integer := kintex7;
constant CFG_JTAGTECH : integer := kintex7;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
-- CFG_TOPDIR & "examples/bootrom_tests/linuxbuild/bin/bootrom_tests.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
-- CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
CFG_TOPDIR & "examples/gnss_fw/makefiles/bin/gnssfw.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20191125";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := true;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := false;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := true;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := false;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
| apache-2.0 | 3fa2dce5dd2d63dd226aaf3628707784 | 0.686017 | 3.879603 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_addr_cntl.vhd | 1 | 41,879 | ----------------------------------------------------------------------------
-- axi_sg_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_sg Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
Use axi_sg_v4_1_3.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_sg_addr_cntl;
architecture implementation of axi_sg_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
-- GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
--
-- begin
--
-- -- Format the input FIFO data word
--
-- sig_aq_fifo_data_in <= mstr2addr_cache &
-- mstr2addr_user &
-- mstr2addr_calc_error &
-- mstr2addr_cmd_cmplt &
-- mstr2addr_burst &
-- mstr2addr_size &
-- mstr2addr_len &
-- mstr2addr_addr &
-- mstr2addr_tag ;
--
--
--
-- -- Rip fields from FIFO output data word
-- sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 7)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 4)
-- );
--
-- sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH + 3)
-- downto
-- (C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)
-- );
--
--
-- sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH +
-- CALC_ERROR_WIDTH)-1);
--
--
-- sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH +
-- CMD_CMPLT_WIDTH)-1);
--
--
-- sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH +
-- BURST_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH) ;
--
-- sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH +
-- SIZE_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH) ;
--
-- sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH +
-- LEN_WIDTH)-1
-- downto
-- C_ADDR_WIDTH +
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
-- C_TAG_WIDTH)-1
-- downto
-- C_TAG_WIDTH) ;
--
-- sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_ADDR_QUAL_FIFO
-- --
-- -- Description:
-- -- Instance for the Address/Qualifier FIFO
-- --
-- ------------------------------------------------------------
-- I_ADDR_QUAL_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
-- generic map (
--
-- C_DWIDTH => ADDR_QUAL_WIDTH ,
-- C_DEPTH => C_ADDR_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => mmap_reset ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
-- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
-- fifo_wr_tdata => sig_aq_fifo_data_in ,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
-- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
-- fifo_rd_tdata => sig_aq_fifo_data_out ,
-- fifo_rd_empty => sig_cmd_fifo_empty
--
-- );
--
--
--
-- end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
| mit | cb3c2cd7b5b4ca2b8d33cfc40adda5fd | 0.389861 | 4.802087 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_v8_1_synth.vhd | 27 | 68,532 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
FAkw7gRmEwDx0cT0lLfFXgH94E+u7pXWs5ahSt/pzljIAtlVd5PhOu9ztNGUELVfoO4Gol+zPLUh
TN9yRctY4Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OsI56UKE4Z4O4++RpLw+Gr7y1Sd3eUkdDGmGZYBu0aWjoj+iDwzKGBcBG0rF5D+4LwCAgnpAGiys
xLyYTz/ObATK7L0zNe+Mx/H+/j5j5SXpNvpcXkGCWx3Mtg6EpqxneRyrD34svh6fn9QBg9AkFvdb
eTcam3dZU+Gacfm2Ivg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qc1VB803xD7sVBXVT5KuCy+daGAjeSNtMgViDKH2bpJoW4aexvjdVOFa9Cn3ZQUudsfzbRtbOfND
3qwRkfwGKGa/rWJp/b4u168LG7R497q3mKgxz4wZrw5VVWth06zATVCPkvVwwcP1aVCYV0wxe3+F
BcZo/LoE5dzRftELWM1hbxUlZMlSl/apI9c5DLD1ZPtssPXqyfH8yGBCJ6IwpqThHkCcKlxPWOFY
XBErOYYrcO+fou4DBovYWIgQB0ZKOhCR4cvN3q6rg5XOYT99xP70Y8jdZqXKRq3PuDDZEya4uwav
9zgp9xA7sRjUN5/fcIvFMcfDutvNPIc7IvkzWQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xeydwtnivo2IBZhciZFfy3r1qoKk43zuwlyfDAWr7E6QmSwqVQF5VHmc7oNu8/L6oqsi8CW2guof
n3LQZ6J8fPLN7CBNStOEImWoOU09vnECk8Bwe5gJEo2CSwnqojJJlM/jtH5jKtWnMb5YecjpsAkT
3bnS2U0oIgAvNLFItdk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QglgmN/aSMz0M17AlWb9oRKStkdBh5nVOwe4/WnjlbCHuTNXWcMIzqLlv5JcAmIdzL/13EAMS4W+
LbXaFXFMcWHAzC/5AZxX+CZbwE46qfB6uGUmUBTFEckk+Ba1aO38uKX6EDual9TqDkiz6OPrjmC5
MifvdDzh7mlaB+rYqb5sjxUWUfJCpXIOgO6lavL3535AS2e2hAYpmi1PB/ejGTuva2r1NRmDkiUk
Uq0oiyBI4sQwmU7gFF9pADJRyzpgRQuSICfI5NAGRTR3by64/5TeOArBdjuY9arezL4gMGXoOIu4
E5vrAQOLZikLF7X3/wpaihrUarYdJnuPPVXNaA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 48992)
`protect data_block
ALca4ZbZQm56On3bvuh5B0WS2btoLMeZbel4MsS/dwMbEqvPrwO6pq97L5wc4EmhtS/RA/5CtXS0
C/KdIWC7BkAWl92/ez+4/cbcWd+7u9DrpphsTFmNVafiHzkS633Xmj5EI1L5MokAFlz/7qoPK8XF
uCmJORXnRP9WqVtN5DAKcMyDjAXYfIHl2oV5D/6ENsCrGMoa9Fxl5JWlLXlVbtFdZXiNEzAO2YOs
WmhWGlxmSQcyPv31c+Xy4gkwYEF08+L2utwShGYQ5JXcipkSg6PO+U8yC52LDJazFtR+N1T5Vky/
eubJxwU6PMG2TD8v3hb1hJRn2YaZAXV1m9EibBWmTng7Ymbl3W491k2gI3wApODYTEc8/k/Knvf9
Vbp7ct6B/gjJt8UycvRJrm8l+AQILxR2gLj1w0lLMi7i9dKmp+oCsjTiNCjoE9cu92epiyx69/JU
HI2dNM7AUpjhU6KPrOnawbSUyR0MV+IPPbkVGBsPqb88VLAmG1gwh7YPx+5QePYYVl3gZmMWiJ4V
56sXjlNKYqfkB7eldyPywnd7jOY+QqR8I4OODMa4uHxACyozIiCg/7DDRYXhyCYWrRpHyDrpm8Vh
DmJRxUuMXwwYVvWNSuvAsCnCrFBdXg3ReeXO2yJw44+XgVhiIO8jRUDRlnWHAE2m1nrW+CimWYJv
Tf1b+Y3nDflswoTr82hf6JYK51yDq47R1LxQMh/5T+wIcfD7OUFYJ3zRoJ9JIsXaEBJ9KHkj9jsz
yYyo404FUOEziELp68UywAY6lDyPx6sPfgyk04upxwLP51cnLwy2QcQxKZOPT6v6ZBPDSeRbptHu
/DZ5iBy6VShj+ylN8vcURYRbjMtnH56etbifolU7n0y1dTa4C5uMdFfwWnwyhOxyaCPmYXwnq04B
cY6b1Dl2htu794iGSBo41Yw12LZSYbr+miyQUeLrQK/sVL4pxuOOZ2EDRwZFjda+Jv3Zd/zUmatx
+xAsvG9GAv3F9yqhalThADdHufEq6C+Cw+T0af/e9LszcL/b7VofxbldRy0w5V+rhSBSkTnF3I1a
ARZki3RFkt3gFCUrgzcrcb6w+/F3XnwlsN4dgrysKTtzxbFuw+dz+HKcFt3uIoguwhusiNG34VL4
vAKHJmqHA0/Vx/+7dCEQMG87aWAa70MHd1OI9md6aOFUIqe19CrUmXyhk3M4XXf/kb9Q/MF35p1C
H4i6/XObXaAdPiaJMK24+b6LKeVbapy0cRRZeGMwPMvJCGC21Mde2JPBge9FUSfCpIkL/2JjDksD
LWpzTtoLnS5fpPTjKE13OAYPIoYaS8nYmtgIw7/Nxs4FsbacqgO/2iJdXuyNugIOxpomJ6boBAo9
sYqUyiDmdymApOS1auimjrWUhcDMsWUxv1/pmmF1LrT6BN4LnyLVoTT5kpwNxY+kelNGVXSBCx5v
19eT/6TQ/te2rfhTECMhuvDd9NCpzGAjZBHB7XkRC+rvVwba+y13f8wNQAPS+Y0ypM01Tellvt5p
P7lMKTqNZFELLUeF06fXmM2vMbumbbSTtnT/IBXCW7sbOxVqoUrSCtZ2CNNtWso/RnFvf1yVFo2g
UUpykimRpicia3Wo9IoGyw9Ud63WYOiHTBG0i7aYzcUl7oNfnxtVWGa/RhJ1TGplus1NfNwpGDBk
amGmbFQaVHiLUxV8XY+fbedmbgZ9U+GEM6xeN9nRaC+j75F3LSOXyDCHN55plhIFjk5jt4ImCb2Y
/viODwcGF6jjsbEIGvlNw+BTGHQoFic51RlvqnBttmq5zs4gQywjc+Yh2PIhe1Amj5cwuVr3rJIC
s4VzAby+8LpLKMyubMqESnnEnPcGCTbmkwtjy4PhztEErC33rQ2ZxdszJ1AL8+JnHP5h1/9RfvCt
EJPpkq+2/RxUFSBhwrNcqTqnkH7VjKlj0neoLQpc7iRPJ9zllQh2fE/Em8rTUFBDbzZ2IvhE7M+h
E+yxGUNsUejNAhg0EpwwE9Ua13hDCjYFCcOxKjZzoEymXKUeCNpp4lNjQHssaO9CWPGbJ7XFqBP5
OKlnsMzaPLJ4FWgZf8RMp//3Wp1gb+tv7o3+vp3Lfk2w2AZqZRH+RvuN7sRnXlbkpWO/LFzgvyB3
FHkNHn5LtLipcr12t0/1LrpfP5F4reg6FA7orVoUL8ylaGZAj0eu0mwYwy14GmPjXqtUakr13uVg
fzO6a0KsNNr/TenRKJfFT0l62GSc8wX4QyuFaNQh3MLqHSBmehCFz7GfPMw98PGflSoA/FKXURr/
mjBhstDqfupUPTbboft4s7dETMmuEgUe2udSh3qk1+S1LOtcVLi4g1l4jl+vgvyZOKoZYXX8oa9v
+Qdl5PTLe+eQZvd/yUZXgrH2vUOV36F55ju/ma5+yRvqNgPzyv8ze9et9mxouEIyIs3pxt5bpl24
cl5lD00j+L/agM5azbf7Ph/XeHenADsv/RAiSjGUwTBlIBswOJ8k7eh99wpOe9iyV8fMnkd41RU3
H/AZyQ8PgRy5uSJvf3IPIaHd6Mk1boJirPuNuoG0a9eD815C2SlpTCXuov0sHD5XHw2z+5aXXnYN
lbt8NPrGICTSCf8R69P2JAVughLP6YAxj4j5ubQbaVHIf9pkaoaWItdWnbHj4+Zz7euXYCbMGo5Q
vzsO6rkD5QzV5yCVbf9Ovmop1cM06L8T9B5S1jqmyN/5gOtYAeokl/yHjjY/WCUSvyznCNvAGzsY
QRtJk9sJJaV0dE1f/VNj/CLlkJ98GfEu69uDtNATpVg1/u0BxE8LjSjysgimjPccsX2bin+kgcQT
Eu+PAa5OY4GyukBvZwYZ9+6BW//eDd3/r4Tln5R0g4erFQz8X2ZammT5MwCyERksLQ9po4bmn2ml
NecRqHubA/Hf8SlVLydbhqVcmi3Sjmgu36EaAi5N7NwgUbcJYo1EF1idYsyoGKyPmy2Zs1+Zv9be
HNQOFM/NNnUOWgGTyXAsUBjt3gBeSOYkc4PAjilG9fJzxrh+mNEskJ+7ItgWvwVo2HHrJa9ZL6xm
W6hEpiqtEBGtm17V5jdDZ70jMIZ+KIKk9vkrgdS9GzvXIwIJCVufMJ6dVAuHG6VQqhDw02kvuqae
hYbz+JNuDZWmE4lQNBwjdFzq9wkOFvgPKW9yUW3jZZ3NOaFYwaEemD63sTU1FQRt8GjUO63ZmOLt
BmMYZ298N3+O38N0LjFnSyCkKp/RLNjMn5zsKp549hA5eUcHWL64dimN5cu/h4kO1zCef9OaTRL8
zm0PCUpwQZ5QBKVhBIUEAgK9GwtU46Gi9fc22c4HpTya2owqZih59E6iln4Vo4gaOzwfU+a/lTEq
jZ7JWWCllgp221tXjPvXOcmCB2D+d5Pl9/KvAGlX5Rcfowtv3ilvj1lS+Mtjm0Zou8hpSBCHc+UV
rn9OChxDPft7fowtE86eu+LyfPQXQK41sUi2RKwfTIuqu1jLjVvoBFYK8exmDmWPmHp4HbKFLnnA
MjxExZ2QpfLnrQH/1rU3eFTCS1QZLdUTD6hg/HBlWcK1DR5nNro5E7r6FJ1rQdZ2QWH+YM87xYvr
qyBmdzTPqDZZtVR2Mlip0F3Vli6+KAjGVimC1qvBDR9Ckw8WqBdIeIxEa9Krm31PbNwYn3uKDhFS
WlDhlfi1IeJyHO8wOBN9wcSvRmOr+IfcWOF30q7GG4KzgkrYoXBX8sC4TnEsFTya+kV2htE8lgOy
7ZGYj7OPC/xqMp3ZAkXVlPoYIevJhhFfP1VXBYEUGaSnmznC+PbO0KcIKe6CoO6sbnz/NYgfaTaQ
jqUFSUAD6gx7YTO2/P9+soX3PvBFVhFv1fvz6gdYdt1yLb5m6HMadktuOoY7yFaghzPaCtbkkZKh
qgSlAXRbuqo4uYMmMBscddJDuGiv959DRr/w6Ge/BP/ctup7GV/JgmxbNBef9qL0U3CnVUeTDaoS
rUGRZSaPOiNl/fkNgFintu28HJDksqUcNI5rTBDg5Ri4EdUZdbAo0VXCTKzAwxZMxnUAR0E3yhqF
vuf1YlM9TR8edADnEh8UnrGKTaYem0GxrvPjoxwyFsFO1QsFaiZXJxqnmNCIQghbhzPkD1bWhz24
7oJNYn5AnQ/6VPBoCyfxYAlvLS4hW3rRPZzhDjxmdHOXhIUdusqTSdDbhTXrKbJLTgMKcPGFRS8f
JgeUioFs+lu4MvI8q5f2c4OSfY2yaQJDNxbXfQ223ypEIf69xYt5bRvjUflpxByBZ5dU7/1ky8E4
Qo36qtA+XeXGEpEEEr/dbfou+C+aYjBSAAkTgwIdhBeBXKowyftuJofN9eMYpZta0PvkHq7NAhxD
Kym0mV7kXrabt/EjGgApoIQjbucyFXpp6vVyTJNzgDCclfhBWSLKfEvejjYUn/ICjcKBbGIQm7dX
hFHwGTcXriRSYqaRE35oyGVMDYZ3F8sMwqPTTbnUROSqF9dtQ3qisGx142QAiF96AIGmAHITzLg0
KwUEmCXxiuVH1d06ApuO1JFytULrEQfJUdEsf2t0Ixo7XxYjJ4en+qCGaAAw7hOWC0rQI53ijrcs
rwvUFF2x41X6bP9m6zXOdI5WmhDebisFzDKZzVv/kMIANlvPQsTd8Pc2VkMDH8qknaQyxZstV5wU
pE2tsuMbU+CIAoBnfc4gw0zDkh5OyBwHKTtFEACCdzrWxZZ/eqRbXEeUfr/bSr2wj/PRA1YnDJpI
Y+Qrwda8TMur6e66cJzWj/oBzJRdq7YP2+X5/sPa/tN9c/yw5B3xFPSqCAWxMSTaFMC9VRK79fTZ
lvTF+YotY+PcBv21N3wqCEb6iWkf/YJcuU1KZc9QGCV8mM+40z1Ni7QPdnyoSPUuP66vD4Tn0tcF
2wBMauhQnsB2bElI9n6utOiBv7DPpzXyZgl0s0YB9+ZSfjvFHDRecO/Pjk7iLCS/kqf1TJn2ni25
jnvDpJVnX7l4eR3OwlWItGrPFMQ7R/pneuD9oa4K3lSSZs+Au24LfZDZQwgw2ew+x4SVLUp9l/s0
OOCqQY/577d2C8zjWLW4l4JFmAqdqotm/48uRqVzJXcFHwtUt94e67pBlaej/Piagpsi6fq6soP/
3jdfmgvMRo58eGMpooQReVJwxq1x0Wtnlt8OOMM6psBbJXpiyra99lfFrQUOvQtgNyioADynmrcJ
lz+cTW0421V45wrWyrPQbBCSSZLvM2tWJ5HCJjRAAPsWJGPtkHFG3v2HEUvE+mdlCTWK91o7pVH0
6z46V8MvPEPyhm/PtoN4C02AKRjpwSGP0L62TkAIWSPKW+IONeUNnlCErsbtpIbV6CFwjestqIYm
xRE3ZNeIc8lehJcvEIFRdrUJ+p3D6gqWCxYh3RDsYqy1CiXuGcg1apazd3xTyApHPD3cUTKS8OD2
XkCeK6m6JJn8tR/sznVLaYtg45bTuNd90Y2J9t5Lh+ccpnUdidpjEsP9oeHYV7c3crUaNcRBWysU
o192cqX9RH7g3cFp5UddEkXRWWLE/AASWkQ7N/Uc6aUlS1hxmSvrkaJUX6zUOO4Nv9l0+9kjr8nq
TEgoT6RS7IumOSruMcZ78upSlKp+uvVG8Qus/XSJi84zp1MI9R1sV7mLDV/GQjfFkrx+IgQHgZOR
GyEVlXRVSBaInrDCRn95gFCpmrtjkk750Ele6S9XVbu1kMiMu/rQuGHdZhw2R7qSGiqF5wz3pQ/9
gwK/1TidkxvMwLg8bItbtTFUGhRx9RN1oUe6aBq4jgbR1oMUj5b9Ak+kcNvDSBvwDuPqAKQ9ovQR
/HOHL2AsBBUgPismQ2brZnHHX9qB7xPNUaHka1+gX1zNShFlwh/lyNGHEufA1v2wTtupRFWuJ3t0
BKCoCWwu3STOuVzbqNyxk9+40w6ZEI1WlFk60ydX8ge1y8LFfPRry7gQ8eZko0S5iTV1jiZC7zmU
uT/K2IcN1+U37zwBznU7Drhan0QKUdQIyB15p8248hiz3EKlTrNtQ4KsWlUq+dmkn5lfxJiVzu28
AccVG8HngY5tC2c5PMezOQnMh/4BdPu+6eNudZNN8b/ey5Nzomc9tk+O8xTgNaKpakHO4FhmcIeX
o2GdDy6OpytDGWlmh5g3Ieke+Z0n0aqvniAoCvxqRCxd8p1HVlRqgiPzEMMFNweiyPDVypaQH+iM
84idfzIRIQnQIo0QXXbNUYbb4eIhlVvw3Mh+XXSfbfIpV3LOTGRfw7ih3J06xqvm+Pi24sA+VUx+
Trk4mIHX501MmP9Cx0TSs5NTUDt25v8uhoeLdgpkXjKRTeSeIaUoiKwm+vkSu2+dMOK4GTgZaPMm
ZqQ0tix4PuN/C+C13ZtOFWMUNv0St5fuvG86SXVpv/GDsy5nvMHq1VwbYV3SERSJaLEOtKckT+gE
myC/rXKj/TNO0noe5h5UeU1Mq6R14cTWUgATsQNAYbn6EISJZ6jLez7jij1d29Q13kfLAy4c0VqT
XRt+MCNb57aHeA0baCaaLJiqJyFjwa73hLtiDeGqdA86KuTjrNdGbtGmqbwwF6yc8fLs1j9LJID8
BMRmS2JUwsk8Ky7tVPRo37X/+Yz8+H7ewce8MMsf2qLdvXwa3TdrRnYGDSxsD65sDZ9mRMfKHMn0
16nAcXupwKII2cG2CADNkbgjyJqwALQJtJYxL7V/ACHkMFYyS/xd9hm4oEO2KUH4sRGJueeAB6RM
2YeExxhc/NzT4GyEK61gXLeaOvsDFUZt8SbfICHC8rdMxkJeO/lwatE2K++hfppI17aR1fIVCVo7
hbe+1bZLmw3zmESyKbxaR8VZzCERvC1DHoSVodxdNbkMaN+FPf2USRrfo2zQUFFtW9DBaQvm4f5K
1igfLVyIfe/OwBBN1TIVy7eMyQu3z+KqkT9wgSkAbrn1vguKIEBMmHC1BQ/SGUIcr6SqhLrlMvV5
B2BsHCvw7ucDuYF+2cvGSWZBkwn1rS5FNv7/zRvoVfeWfu+2VPzmKor7oz1TynaIotyJigDnR7nH
EQXXf2hVuIcr85h5WcsAkwYtIrwAogXD/1pGEK547VwPXp4vDXOBflF8myuo9V3ktOKfnCwU3rBl
B1ewAc3LM2OibpicdYk41gt7mSotKIHoY2KEjfYOWHDTru8Trer1gdqCcJ9MZjQHaODpegmKdlbm
wng1bMpbBiVGNlvV4ycHl3VGOGrjb8ohBLaoQfMn/0dg3LgAelRDYw+ihZfn4ARo5enQvyLeOT5C
5h9vCIhFW3xYYH5A2SUg07Ci5bmw1xHkPpdr0ex4abF5fsaseJplhnanLkCsEOiG0VIbRULPYWww
2rGYBJU9xveE2+J9YwUQpFpDWBlNKUrPBopNNuG29cQZJIgfhj0loZQedzbXBhlOqQhfCBbf8pga
s/RiGnW2RRuuJPlwI+D0TaxMnd+PMrBji/Qnh70M06tmkSFwDdYb6TL9NlAZnPdSR04+t6oHzdLR
8dxraLYBYNCuQ6phe3iRzYUs27XWKKN20avtkl3oyyFXPg2+Cihahr18Lth4MdxQVhnpLT79W/cl
Al5yVfb9UlvmF615kh8kOScVZHhdHtGNYQ6mQt47+lC9SiTLcW4NFMrlFbgd9yXqbB2OOlZkcTgJ
CCgneH91Qy54HIP8ebdULNXSpDuds0bJ/jjZ7/Z1U/nM8ty7yBY+A4BBzq1uKUfOoqhL4wZZNUP+
QUnuM8I7CQfpaVrTbKKc1RVr8EPS4SJVgD8zLwbCVYVd78IgaqpRDD57pjYNjmDLyU1sl1uh6dup
oTytFVJe6QBt2hRIAI/YMs9vbbSa3Y82WxFklhAB5xrmjrUhpbRXdWBKXhM4SYLdm8wFlDpYo/DN
U8G7M7+JZhZxGo704qDgTltPlrSQSpujqp6c990PrPpwvtZHIUTQQk22H+Xot3n2h/KiQ7fYo7XO
hdzFL4ujisXwGQQyEozKcjyVfFYoscCpjMYc1TPtAHrtbVnIbQgeodQP4cEmwMxAFVPsRaN4f7gU
+PnQSUPof+T91/82yG0B8IYHkUHhm7K/U5G9ZHkuDE0OBXchBBFRJaXesSZW2iWct1fJAu2UycS/
nRV6L4VwL13TszRfcoTWGxIUPc/g3c7G7lR/2dQRIiItHSrh7oSJhXUEDeyjSCTYhMyz328BQrSk
zXgYo25TWUgXM/fWJhKcUvPf3qhfsKKlJ9hlLJ7m5ntZ+0FyAzESD/cNvKGtbEp0jZ7asb5z71wk
ngmn5uqZ4btWVhYAZlxJhfbmphoMqj/0NF07vpvBOtUZonAZGXaNEgqXoCFjtFW9b8FSqVYG0+RZ
pyE61gSgxBHIcr/EAhX1FiUiqGQpIi3iO/WbduYQpvXT8T5vpQWPF1uLI/69Rb9zqIQIyJ1vk6Yc
Fkww+xfnbMfl/LxUx5hoac603SIJmI1v6cQLrDjZoyklvG4TfcHvaesbXiyQguFG/6BCjl3zdI57
OT7tmofymNjdV1uF1wJ+iimcaJx7QVlGUyJ0dHYk4F1w6twxYoVfd7vocR530WW0E4ytbdUHVil8
E4WSZbE59ruyPW9mRAe46p4XQvnjE9Y0u1tLiOJdxhec8cnMpjPCnA2RQ0obah1IJ3cPXdF1S7Ud
jwKOEBYfaFuFwrLjWt9K1p5hm3CKk04ge+o5LcXDnU5yyshuwu5YbKWtx8O2Hl2wdj1YnSLAFvoH
Bjwl1U30P5xaodxC6H7TUaJbrtZYRhr0IWioP+ZMWVIW/kaEhabTvL6vlQfhrcd+yTFFC5xUr1YF
g2boWR19o2Jq7TeMVBPuSC5siQFIL4KrSzDRSE4tqou2d1OQOnE+NcjclYYgpIlLvInBH9xZlscb
6KZlHa85fodCnaJBTOgLRO+hPU9P5+X6+p0s1m+1bFNluMKQmWN8el3PDSil8xggsKG7f0fJBuzn
Yf9KXYpUB9ukDWnSaYu4hGntFdUTagmY8nWI4AiAh7ervKe0Ch1njIM/En++5pLdaDOHPoZFfamr
DML9uNqj3c+voVP6Q5LSj7u30cVeIdR+vhnwNRFy2atgakfs3KJAAAVPNmUARjg4EIqFnulA16K/
O0zgX1/E4nK6Ksg80y+kJmiyPhwaV45DyNxdik7o00JUtcfgHzHCsmHZYCs5IiXDCKzmKNSZQ5xI
6WkS09vew2MBa4kDwA6Fx2sxwI6/4mQJojFu5SrfqlVCDMK64e2cjBT3JPGXPtQMKBT41Lz1E0mu
0TUmTD/6syDnP3eqvfVtTb5OaO45vh6xJIgCaROuf+2jMQM6dUCeUddIiHaSy7dW4mdP7vQPgdqL
1b0PL2RWGUgbHrk2SFEhAqUGgMz0MI0nC3QaUnpAfa4Y3f3uJgIXSZgprsHgpo9TN+TClUdosbJl
XxoMxaSq4dPw/7vePgyKf/86l8UJpAWKm3bLBNNxItqYNXFMEFww6DuCDFxAJjm6FGHtij+dh5KG
iCRvQ/w1NI8xyjKsvh7nnWnVTBmNVKzqUx0KG7gBEEUG2vq9aYgbYvLU46910VIt1rpipfwcEv+t
8oNpUI+WcYAf7GhbE2EQFFQTvK6O4u2bmW+rCO0F2V9+m0uTaSD4NTbEPIDT+4RZ8hvQYxHrpI8s
HYbhfrS4MIuz4V501uUlPHxB3ZIoRkQZcufNowWCB8HslFm9fm/6O8P1e7kLGk7JmLD63g1Kjh6m
n0+v4msBzhdvoAN+I2ESGPexXMgWRKZHcG1+0ToXmVlbKyc8lQvsmSfpoWrLpi9HogxIfUcKSafs
yat2jus3E0u5EfuOlodTIEo8O6cJh8yET3i2WJZPxbFck3LI/nbsm/7L7Kl9kE+1jI35yC+o2CJ7
0wCuOsd1Ybv0SmFPlnRmDPmETWiRalO09KxDWswAwiK9XjlGDstLDMyecccPcvqVPkA3C1cxVa44
znrZa/ccBHwvbttSbvN1XXrQINl1C113m1TelIl1agBhOvPE8G0/qAS90+1XZ0pi2pMfbkgWBDRG
qgc6f8nK/+RqvPvWrNpCynm/q4cTpDd1u2Sv63oh6HgYEN/3ZNBt9nbI32mhdlLqH3ZfmExypaI5
EWe3jO5AIbMBwPcpM+Iiw816xjFNtQvdYZZw4X3YCmM97ClRXlR8tIcXswAHpHP74L9D14bLgV1l
gqVYBxFrv0f+/g5kKPisEq2KcRxl/AvzDzuF07hwpSPQYTziJtW4mXCsWtru/0Ctnh5ywV4Sp3PM
CPoRoElJ51d6r2jl9ZhGTTn2+vmrmfuEm9S8RW/B0TRrB6XuHSPOmu6LASuzc4Or2OoLapYte1+l
vynsS+wm8Ppnwt14kvoGddjKrFJFtEDOeUXNi5RBoouVG8g+gX5Jp5ipZfS0NS06tj+2Q9g51ZCC
w4oodXycXwxbkAq1ZNP9BaaxdcLlG4jajKeZcxIWkcO0dKJThN5nq6IrQjhuaMPLsmWgaL/dal3d
gVzGndTkT+HkA3P9dbipfGNjd6eIIxNFeahhpfukUO6KRBZv6jnDfycmV33PfjyrqZt951XZJZ2u
rlm/k4qxsGUMQatyI3KXipfzFGHrLc+LTTJeL3OIyJ2Tybtvcq0BPy1BjNxhCxu64OfVw3VtP7JR
Giujk9F3uR+IjWGNFdEPdVUxcDvlUCKtIRT6liKk/5RZPOcQUErikHKmZBj2GSO8st7NuhMjrB1T
ExiLlvO8hVFMfckeBApub0FKg3KmRs75Lo8Ob5djfZdWko6zAIZLMyFgQcHXnUpYikJseym42My6
ubtFWrtAXtRhGRhsRb8MwB6uvE6Mm5I/ZlGdM/PXbXjOAbnYc5CfBTEZ96+rZW8Om3d1EVRPm2Oo
4c5oPSX+v6w4qV7MBRnMZm+JYEUSTIIwoU+WUPKxp5R+Ne5rmJn4h1HYNlWTqajHLZmhA0xMfJSJ
3JYRMX6wMPK6k3M7IAqikwboxKPKFO8462zA/cjJ3I+ig+rBaX2/kkOwUzqWO89pmwN6wR+7CBZa
xrCjeoEFrPqP1ox1WV6gMnLIvQ06WAbGlp+KuODcvaPsLinUYjH9RuuBpJAZWI3oBUkvBHXu3YH4
JZSjAZ7rjHLwLlNSS7HR8tlLNb1QKRRDHbZMJdJnEPzUstt3ZYOeT3QXN5MQsRalslzjtYM0tHE7
xHU3xyvxHKTt/Ik1s7fGTZ31Pb5rEL1ZzMq0x7cDG0C0dsCR/xezMewUmdOd516ft2YQgdeE0jOc
Ldvc3lvS83TbwSD4/mYEX3Qqy5krYiCzYKvHmJTJXDlh0FDS5+SydczCgKo/SeLxDtAgvUM/RGbd
kof6CkFXU4swFM5z2s9UmqCLnXQ17Dvvy3xBngjvZlPsNROCFecCU7fGaYp70jW8ULfvz7Deeuku
qK8918CiUuS4zkkkNX5iBLJS5FwXGBMpn1tUdMZvh90E8evKoGg9osCP5MAnh4l0AbKgVeVN02RU
eHeTTdECnLJ340I2bzVlZ5AkB2KgsBoLHS1flsShG9akJqGnncN8D5uEkVJ2yR96bFEHWYPF3Y8L
zdKRh4iXoBVOOvMQ2D8ahHs5E3EvOMHBoQ9wWhJQTKEylc44z01Xfy+S+K1Vc2ht3t57J/SgG3vY
JxgzpmqwaCsdnWjE52LkMIQByIAFAErd1JeMqPnGhyRZ/P1XAL26ZPmFgqf2jMFgJFVIXv5H9bp4
K3Mc9QWUikt7aUqfxajTpfIFRKIs+wldaYyqgfL5B1pUWqOLR4SCEGb+H7Nh0RhpPPXN80qH3t6e
QdD9/91LN27JMe9uA3GIq7wQx73bcaFCcK5OloGErQ9T4PgYv6u+IEOlYSuwoI2bUPJQW0RUBGdx
9AjPQ/LQFuKjtMIWktPRJ6G4VA7EtWr7LvE8UkcCxbBl7u9T1MQnrLXO7njSP2mdW7y0quvrtrJj
kI0c6FdnVSTeKIhwElF6z8+9KM7WDGGoxqC0U2iibLfUCXJ2s68LPWsOnQ/5TRSaTEow7XMj91ie
vIfTnKtQqyuGoXOGsPnh7s75xjd5aT/vEY0tRl3FncwNCyzVJHNXv3vXavB6xhzKh/I3E03PQVma
VYDZ5jzzuZpwg0R/hy74SxfCEtGe/9qmJW9nQRSibl3BIfmgwajKk3Mg8fxUIBCknPlsz2zZw8vi
qxmDDEtVglJSsCYP5zSnEIsEz+09F8bSlKmGwWqsf3DEiNkWmSh/FCKRZ5bve6qYjjenSBi1leFi
3sAg1usuKjFmOqcDaWu+UumVP2bQHXxB/6tLVfBazcBFrp3SegLlO9hnZeMSCfgxc08mT+a7Gn4V
PYNR+U5Cpi7ycsWQAlbbFtJIwfaOdQJE6qSYmIFAPnSOjYzZB1YviW5ktRTDPAQUOInHXsjzg8Ul
z2thAUmvjuJH5DXUPpH+cbvSNnzC8064hjEUJsx4ZI+37dLg9JiNIti5H+JvBsO1S6QOszfUeuBp
ggB4lYlXM7mK3oj3M4rfsNrP50IiehhE1EptYJYVjL/WzizZGJMU88zClEwZHEZa8SGwnwdY+IAJ
mqfTFd49lyiCyTycjw2c6SgYJ68848/QAIk06vZYkgQwTQU///8nUgSsStapxqfjLqunckyezJW+
00t3J7ic0tONwP/ZTulrRi+vrL++mMjXUfifCc/PqcPNwOXhmh3qD9US/8xWh3YNFc6S9QS8jl07
GA6ubXZVP1b2ctGotbScCffYkPKWGK8hTE4OmN43Op4Tkjx7xrMlfBQeZw9B1LnR3ZyEY/krlFLI
JNI7hw0RoH9iiSGkiaBGOMsDKDb1KADwiyfCk06tur7RNzetpmI8CFWEj54oKTJn+5IxptsmDlEz
m1MnKPfF83rb6pRXG5OX9z3+E1KzFCgpJFOGtXyGbpgtAr1wZa7k3Kit9LO2KZfpzl+iBfL21sAf
iR8V9p4XGlBKinjMfFD8xVOZEfy9APDJo42wgXHucL/CNe5573g0UGrtCetsqMFupqOZuX6gDaPK
rU9+G/3wYiXKDTA9fy2sm4dM6am2ahzb2J+xvWhcRV3nqZGkw9TE8F7P0z6y9qe8JwVoA/ZEbx+4
n6/Mh31tdOOrSD9WUwyk63LUQK5XUwMqHyZOowjPieYpIaApKLr5BLOTbBM68tcvHW2UoI4vT1rR
tV2TsezKN+rxwoI70Q5wI3vjuC+qd1ji9r2A4hxxuFPxVX6NTq3Fj/GNHrtPNMyQnDMUoc8b6r9u
XibjG/+rlGf3lywEs5RvaK34WBDk/ZIubBGP2Ry5GGuvCFw2Q3PO+nyu04ZM/gJrUqfZAjAlFSlo
Im088+W4QHO85h1AxJkQhzJTgmur1c1cDmllPc7sgQRSw4y911+x4z5XLkHrShXIaE9OWmaucQ2r
bCdoEWSwT6wGq3a8rxjL3qRlRbOWG3+GthlOqQKyqwv6li5VFGOF58r23F9JBNgchg4nKTBDw8su
6OpLtfBObd0h74IrkQJUU7xiiZG6kFaAPfc9nAMpVuFxZ3tZd5gpPLM0IOCZNVz5kD4yWmXSFYxU
j3NR0Sgoade8nUAGxHgWoeg9innMySrqu6HFgTtPoGvP1DPhh1yFyxGOUhHzxYWRPX9gQMdnQkiA
JhOtFQrzTjVFP/7DvA9zQxCFgokKWhT8GOtKaSNCJeW2MKCrwCAwBuXPbr7r/sE4uedY3KFPrAHc
V8t9c50W+qsH/2Zf4ODr+1RqBEqJRg9qh2aXhRjne2ddFPoXrCRXGNylczn8jjRU5djQ5joB8lGE
Zx2SiZxhVXHeQ1LPuBiBAyuRO6WdoloDnh3cynBiwakn4RQvWCh41IPEM/RChg2EmaApHFqfIslY
hRvHI/qBZG46EV6V38tpi9oNOA9v29uy6em8IjM6pkBxZIUWuO/VrxOIuJR3pX6ZI9pSlYPPKIUm
WErXfZqhKAq7xl/+mBCqlMoL0KzrNlCEEMyxJ4JkgO7rzROth4U6sNLjTHSeYbm9qmUfDre3eIW4
LXppa4LHUi5njqKT2lVQV+FgXEJU4HjM71t3xIfpLVDsQBa2V+qHQp+bXSIjvAzqTg9fqtvVhJc9
44NjUOzKPsIGsen2mPk2uGCi1BUDhryENgFh7LNK+p7P6QG055AwEKobnAZ68EMuJBeh8AgGaWXh
tJM0JDmdimetJXIOeA4vvhmqAAgQ0CZ2l9gHehu0bCG2E57gL3KEfnyRVMTteha6e2jrfX5b7oGi
yydScJbnVpdF2MKuHWrr7gMlxrwu+5gipYxJRYMbDOtgHk1B3P3BKLL0XBX3kV26VMznKqfnwkie
rQ/yJaYMSA0stNKHyC9iwxrS0eaYVQjUeZaM1GYrPUgpf1PLHeg8+rGZTqhLgezbz8oPGANshlHz
PGB7E+IwlQXFnB4xwMMWBxqozXw9bTLen7xkhxVWiyUerID5NHomuEVzeGKpEVLPkgPn7d/em+D0
kbgYZGG3J8vkHz29mUH0u7wln1/koYvZmtcRPf8VYbk1YVR4rd+ldH99qNcfwdxuyzTxp9r6ggy8
V5C6IYDmBHkOsgkJ9o+inHbTKOHiHPBSCkINMRqI1+XolHVf6KvyPXHfM2vUF2ocbpJyFsxgibws
zZGwNU3bj5T0TsAC7MJJrtE8HPoG08K+fIqVSMuVy+WzBh/61iAjGMStNY+KGE0IQ+HSFn19ONur
Y5z4TyVH/t6yPtn0X5APf/pHD4HiCyxqGhTiBhmgJ3kCMMev2V1+hf+51n2YPTI70wwUgncuotk/
SKeEucRMkIJO2rtOm+X0AC5RgVkVC4MDutTLQDEpnaptBwdGDs7dUdGmT5MVmDzFNXPzyANS9soX
0tTvbgoOZlULO1yWUk5egTkmPhK7MNdUpXnJDhkcnyeCMEzsKQGqfhaYB2TfSTaPTDfRVPzD+vv4
m0oDumhl6gC/rf/2pDuEF8Zv7CiZDpMqBzhlOV6cmT5tkUzQ8PmBVXbu2sFvAkEtgQ+5nCvBBTu0
5En2FFQHICbO4Sr8dss9cwd8m2mR7Jtquq5RYUoQyA0ANo37QX7s4VRLoDnugSpNs2/OSBY9f5ah
pl/4wpn0aCSSHzpgr0zq622NCvUsVcNp5Z/wFWDzzlLL381wwYRiOTPHvEJt4P3/bUV4hcfaZA2Z
AfG8pUA2vP3dR2P2vXbB0EY2+0yBtCTn9zIGlzdjSjGpOnl9plnzfQoc7uReXVKrLBK/HY4kRNb4
YLlIpMEtceXaF5lxnwFyjfu5Jz7uW73tWQi3ZyJ6ZgCUwGsNsI12q+ZpWnSS/OsHQrXgL/SYrkNx
yslviOY+Pon9KYfTbL+Pj5Ru2tXZmIWwZ1YvR8u1fn6HRWfGZi36KIpBsnp08PtsQBGGzJcG4p2V
/wkuHeWpGcBn3kUYvPfl9G9qqSRi4yhL2JaVupCmWu3S7cvAX4lE+MtffWyekGDpyNv32Nk+gtyn
nOmb2skBjQgECEE1zle3SjrEFZLB8jH44Hv8QDThx6W2WayADdugQZhFe94vMrvH2y7AZ70JxUqD
GPBQw7rn/wq6PzYfzwk0bx7yaCxVh05WR2h1bbnh0Vy5vxImOKIxNQm03H4etBQy0oGNZlE9q+eG
JqywLBR4wgUY883DK8CADYo5n66yOu8r0ScI4Xv5AjKYspfUZ14hQCLy/5FsM8HmwVhESC4ThakQ
jqHi0DPWgVFSvdmIePTlO1yG17P6o1tRvUv7a7HNG+czC2YW89eURrujgZWUDMBgpVElfg1VX4AR
W2TwaHHIHKlQCmH0IV5+6/v5NHBWEQSJP0YpdPgELky6nL22MYfCTA4lF+mrk+o5uQZfcFr7Oe/4
TfYdsPhfMXonWbxrG4tvGoNK3kMQ61/6Gti3CCShOXhyxtTJuiziYpw0n33V7l/U9F/PbXPt40Qa
BC7vtquJ5zmXudON8TZag6ZQV21hOZhbBWwZbcF2EOCk/BmQy2UwAbPsddtZXvkViBdfenf8e1P9
Sn9bH3HX9Dz5E7y0RE6qJm6aWFhFXmgt4SWyEj77gshu+xoPHJgZZu4UZF2xSbP8XwpbjSZouCTa
Hsj4ksgPHV4MGNKQBZE8wkFBwhCiwSzUDCqP+WeWzyMlPxq2EZb5SArElXPthtnQ9xFkxfXuxKj0
5VnUmQ6k0FeaUlnfFTr7OIvamxIozkq06exneASElI/gppDQPBTjNUOCP0nu23VQzAnI/of+coA6
C3yjdhaCN9eNdJt9IQ5TlzLp8yrFGXAWh7/9mdhouAgtyW3flSZX13lNG2eBIgnEtv/yhFv9zm7F
uEOpECb2doAtoRfPfWA7SSTDavto+NkdzMqcQm7D99yq3lIxb4f7NMkWONBBZ7gdlckEb4c2YBRL
lU5WS1a1NZ5fF9zlHOPkyB6YpTE3lnRnbZnSiH8f3vN3gOUafLYM7FzhC0yQSBhRXAj8igC8b7X/
BrzuRWHiAILHS9RhQyjylaSPbDc2ZUMmW0faXGqN3FKYq9JNcmnviaKAQFHepD4svApQRWfl0vZM
mvn0n5j2NxdEmhAlAXrpcanNHz9TKNFpQy1reEhVT91P1XHmUhtqASaH8Mjh7bog1WhHw9E/T1mn
DGJ9lE33KVyCqAwz5xNkP7ZH8elB9mFjygojQ+flThV6CxhY7PWg1ahpsvas4dJCRmQvD5ioxdNT
64VXX7sC1MO2ZDwxGheI1RrRJfW8XjWD6RQq8OFTQtRvQB4f9xWYXNH3cHUhbIrb0dwgIvidsbdK
drjjN9StMRvnmNabDLLrwWJnXd0fRqyfeSgMw/BF1mUsyDYQHOQpdNMzoUNPrs7YqH6qHFNUQFwj
wO4c4nubfPxW8e08A2PbGj7OuKQzKoRuprvU8McxLVBxMxqC1En4zjwrxwEOTk3cgsozDGTV3P4m
2++QR6lqai06XzUtkS57dRlbasyeJtAcELOZNZujaoWSfc3bBaOX5/U/dCdXbG9nUwuXIEl3EA5C
i03y5DgA3VNWudsaHqtNqb2JOqUKCTJenBUpZkmyY8bPIAVluosnDXQNg0ROIkugZB+C8zk0eLRt
v8CQ1LNIGKkijdke4TcDs8qL5P7y0Q9zF+dS7p89qwGxmwdftui/SLxOzgImcukxSDUVRdPQzyXG
zegBIGnuTMT10Q1qI6wr57vm7ecmIEw/zO01h/UsPP1hsd1/A43UT6kaCkQkH7gxdAGrSvJBIr8Z
DKvtoEkZvk9xT0VsmYkxRNef9e7Ap2XjyX8GEzekCtjkR8Rf6iDBOMc/6EkO+zOr7D145gUxkM8L
EFHLVTTGcWLAqpocqjwGOc9cz8mqwlecStqOXEGprkxG0LzexqMEHdJGnmtxFceKv+YGnQ+Lfmat
+ibttw6ylFptvk+XWiFXwqce3JudMIxpKhzcrp6MgH3LPAQAA8NO765b4J+655umlK22Bu2yCSvW
QX88sErkUyjng3TjHfcRedywkWJYDoxRwhvxX0UNbILWW4Dpn41o3sCGOZ9d8bJV9zcwDNm7RITF
mMQlWguLnnob5Tv9foAK0gd6BVcBmSevkYVz3978JfwlQUHre15wsGmWpKOIDg1wMLo0+lMFdJlG
/0V8S9FhaZXjOa27Yi+0O4KgkHW1aKGuZOa5VpX3pJ5Qp5Wkby78zJo4+Dyt4bGUX9MBKMykbhNu
3xBKZFeqmFJGbn8tVBJJTNgaW1IMFbXpmSgWfKN0r+6EnoKFhOwqKwIjdu3KJ0PaaqqYtxhiWASn
pwSSi72y6DP+bXBnF09EAVB8+Q0cEhqK0ZEiDYhkDgpH5DO3236QCJEGg87zkZII9yGcvghorZDa
M8yOGiO3H+45ChV7xfPlwSD8AL+WLFZvPoEpVLVhttWyv5Qsepmvbj8l3HfiJHE+Fug0nEPIOfac
SpilA5YfLjPLBGanP3grHvBjukNiH4wtaEOu3GhNaIHbmn1Jz7+BEzlgk85c0hnuTEjtEHnXBxff
5nkN6u7A1PS8NwTCOlheNDbBwevD8wueByhEREa9vvzFyd9wb+Uz9COO2yppTGKVlXiZlOA/j/1R
cCYtf1+6zfVadpNlGKqRknUmqE+NOMvatOlH87n7eKlYKI4Iq7keLS3IJxoes8j7vn45lPJCBtW3
q6y8HikNr/Vvx0+0yZDQfdHFcDzARKP8DSPQY0JAfb+Ns1mhJRzRaGeQhhtwruEMdBKhgAmDfXrB
74OnQhMkU6ia9D3LkDaU5/0sBel1vls2MB3OGbLvdV3atP5/7TQHMUucNjqZqAF7XBj6Q6CzzYDo
aQDvoK12ex4q+idihECBFPCQIizdaB62x6i39Moql6jd88zAitYKzj0jOeH3zHGvp0YkC51AX4iA
Mdt0mBcB9IKgZyiPubH9j5mXXZASKVXzRbZ7QrHH8gTl0w1rI+GPSiIXkotPVxVwVMiez1bX0dv4
53Sy9ozfB0gqUbfGjYR6P7FkTA2Sac5lwSb8ZjM2laxt5ba2Bdyzhe3EszgRbtwF8v749tX5X662
HVS7+0N/5P4kDQYuOwbY/IAs5Nl/PZivTOL77V8ccmaqQAQ+ThSHiJDz/fvCnZJFP2WGT/swE12v
wsVpcLi+nOn7KvMLtDd5USrFRJtKeI4lmn6zI4kZROGEA+VqB4B/EqP34Xw3TCdwY7AG6CFL9qdM
W4dlzEvNfiShJcwMK51jC10D3RjFTf0vV/4tMVXEKebuftjEBD3V2DFInfY7G1QkzrAcEPSpf+kM
5HF9DGd9kgzGUJCatY6GV+iUNraCs+hd2pg6loFwRbiiY3ldgznFyU3WsHO6ndcxzLlhMXfAb81F
zjiPI/NALfw4ezhiO06cn8hLfTb5o6biGWB7Ny8NbAJrx19c9hGzz7kSjLZcxIJmEDQgRww0nMOV
6tXcArmJBi66BrTarZV6on+pBdmgFMwP3oE8gfqLGf9kCSIvwrG3poeYzAotC98htUGfNLJikHDy
Wv9J1KUeptkBU9neSRzc+Ajg62greD0kB1vaOH9l7aImwnQe3cTwyTNUbpSueD+G3sLCaO3RdKqr
OgEOvJYrOY1qwJHM9WnDavm8kRSujKcDsM5NEk3o4YbOY6akcGj8UyaH28topZOTCsv+udmLuq4D
bEc23semOPMziNKOMDMGtEq1fuQW0D8fv1l7e9MQfZt8In3hmnMvnHAqu9oLm+/qCjl+G01oJk2Z
YBbkGTRg2d+zWBcxK1crqbnRBSKcGWf3htOnTfzfiK0sacQW7SQPfjq216mUOmWPA78H596HqOA8
vsb+Le5y6EnDZV6XYLW1EECa9Sfsc5e1Y7yKpxRJwvPwqn6mTPezmjsya35bEu82fORHEhyYUSrV
FPDTegzW/DAq5Wynz4MTc0EkLShXeEw2JAlHm8nK9G7TTKmAEgA4s3Yz4D+Do1KwtuFtetAz+pKp
n6T8xNJQZ/4w09jptSBHiy//WVsxqo3loLhMe9RoiiyGuU2s30Ns2lPnZd1JCzoYnSVj+afQx/+Q
B3CdBpoH3pYwWPQ9ayEvv6PkpNMH/EYxIlMrMBOXDRKDXY1Ate3nIa73c1WbWuwBa/GBQEUJ4gpf
966lBb3kw1kJfJWD7sXrgafEHqiLybgJ13Cl95W2RSzpBS9LK6TwjG0SE8Fg+e3UFudb0Nsk3O6K
zz5MH581l6/0cmlnYmKpK2vVscOS7OnRiQ7TXwxFH3/zVqcQV2wcoQKTi8CdRC4bvQv5kECM8GTV
1GJGqNJVaGTUr9SKISZc6uOzcXyOFFHlHMiW/hI7+ShJUDIPy1kXKgFXynlpk/1YEuEp7tF/Sqb1
cvE+8UixgFTp+pMtCdh72VI5PcUl9R4iaZZfQh5xps8i6ctKv9ICrfoE+wuoHMafx/IRYUqdN1WD
Ih32NhaGzaSwZ3yk1LRGsvUHrXZdNATdPONTZSkWqkFX6rl1A6b6tSglyoh973c58WWmFiGF89bJ
xVIWN8m7GR/8t3c5Mw6CL9f3HwaDGWVlYVymYylcD5MgRF0VgqlOnjVUqvsNGjmCTpWQPF21pC2W
KoNcv2qhX0P7vXriu0A6F1IYLXZqvaS6ufLNG2Iro+sSJ/rHTojySDdOLxh4krTOPSxLXygpPqHf
C5iN3sHgNue+igpnM9YfnPRcco0O9rAp1L+mVeOwUdB7oPQgiVcJUKrBGTQ9gQG88SkrwM4reAvK
F55C+H4lBtF8r61ASE4zDw2cJyx01dLeR/7PMji1ctNgA9TXtVdTB0LgTTqa7MsAfqeuNLb9rpXf
LUTu4nAseJF7E5uIB2aGRnojV4pbQdRuNMk2cbnTp0xgjSiyQ6FJVniB79t0/JpR5Iwo0xwxd/SJ
IIuu1i37uSy29DQBWXzYR1nhGdN4a9SqRz3GePemCEXxwUUFE9PH39+BGw+7yRiLlzH9h/gRvldF
HFpAXOwmSwtmyV3BMb2f+KqhaQptVzevT58Hj9DclbEGlkjUu5WL7hhVOCEKT8TDFP1J2ZgAVqjX
KJn+YwQUCn7D6344wbC5+HtApJbUMxUkB0s5sqeQOPQTlDPWFFua7kA44mSn13upFqjP6Z65bY3H
e/KSkrjN9w2mWq9RAtMTCoLbiszmBfjDmb34ilVlHa4+bj1m6G7h0vj1Rc/AftWJ988vt1aJAms4
A7btD5EZIQTUIr4Bz4l54rhOVnNRQTrfmJSZxWrwDPygJgPj0il1KjJh53c4vBlLBgyYBvYn+q5w
MOBeJnML9FMkkSUbMFENypdd9uUoRx1J57Ck/YJNUEGclVRT0Z5D5hmtV0LD+DeckXD04IhS8IvM
GbKFxc6QKHRfW8ZumNgyGymE1Ulz7Vdnxo8W8kPZnXyw5dINXUdmA0/Agl3SpecUFBRgW6EIIxwU
bf4syIQ2jlwR7oC93Y6eAYcSbSSJE3fv7UAB8ELmQDtaqZhs8+HfIWFjkNjsnA+ZUX0AsNK7iimD
28V3V/mQV0UpUwJCoe/83yow1+zXsY+du4Mu0wCvP9h6LS2MC/RlfQadguVqlHremhh5ZK9TfQsd
S9x9MV0Z4mJTOPKIpWO25FssyFBwRgQKaLfREqxV1oej5vG7JRXOeXdZUn3yU3JUYaAm1QiLpBm3
kWh8G60/1D76wAotE1DKUM2C4jAAdX6a8936rfRPWyDDBcg0ojZmrcbLuYh/daDNy6gAvoRdl/DA
0x4FIuLJ9M3GN8uywQoLTl/mMWXXaufYhKYNMfg+sZjWu8Z8K/lqjosdYGf0EGNkHh5FVAbWI5L4
fAtyr9HVUUpnqzKIf0PshpeTFxNpKm9s+TARzmsjDbhLkGi5nkqOglsfIPIhOFuPlzxasB5JxZAA
z1Bg43T8NGoE97Xd2QkYB1ox5gKVN6rEkhH9CVn9dCnBaEQs82NQc5XVcnjG/dJm5MKrwiNNupu6
r7TpRDr33xqFf1EzFo9ga2dR8QQl6l5sBQUjzfVG8NBol8t9n95vhQih5Ge+v4YZMp3cU1u24J8/
dNfVyVYkg7J2kO/FEANfjrm3aW1jphLcKqiWaPdEHLzCazkqAHC8WNfsqGkIC5aA0cSdqPDH62cx
a4/1CRoD7eS3zDrt92V4jTv3mzqNQUUuRr2wWJ1KzJs1N0c8M61bFp5b9BDbnP5QjWhdKxTdMDJu
hITPLXmhNU5BGWseuSSHFk/P0WKvzubC0KOMCGp0eEtHimpaW5z3yjIAnfSELJ50MNkE1QDCDhUy
apstgu9T/xrclLMA3Z8xJxUxduQtkUJBSbb/p8MLFwm6ds26r8Z265bsddujIC9bxkQsEq4qVjac
DavFpDz0JRYquGzC4YZbq2tMDrqIGas/BH35Hefc3TZKuKpoK7c937bW1scaq4SeG44PdlmDgd1Z
KUfljucd0Tc81J8MevYSuuzcOeFqI3dJska14R8S//mrswgXOWcPFpmEVSl+ySeTUCrPrqUOoNxE
/FjuymlLq4lqYok2K8D3H96WkuH6hDjVLh4DxKk5InDXkY93tY/IhzdM9hz8K+Qv5ywIngLBdd4n
QuKYDGkwbh2FLFtJTjCSMDN6978/ATCoUNhIE7aSKGk1A7MO9VchH6B7JkCIXF+Pz/9nm990vTmS
KCj3HFFU9o4fLbn1njiCKTyuNFwHaYs51gX1IBRNtzG5mCqCH1mwty4KH6h37ZRH+l+oGI3m/tes
WGeRP0bdrth9UXCfxvdKN66HcmQMJZd29MMxd9xe8f+6zcUmS1yQv8AT4kQL1A3+lLwYN8o4ZWDg
c4gcdaFZcwlfSy/NVSqx+7bdrSmxwELWfpHDyEnouXnNi/8+7gDK4svWwChCbqKLmnow6doAl6VO
3wfb7DtzPyZy/GgeX25QPzweTS9dE8/76ththZyiFs8cXzS4ox/J5UIjl6lAjJxhLvUlVFGNF6P4
EdVKrMoc0A7hgpA5rulEsm+vEaV/UaYJ7ClS2EAkh+gzYFoWo6Le74cH6cTrF7eXpuqOe6kwTn43
UA3hmmUvvaAqMC0nK4h9FhPXkbWCpEnmBicB0mOi6KdrmVTQ7wLaAw1Rqo2nrVhYlk1SKemCH09N
DSW6x1hmJBuVd5nACj3LJj5bMp+C1/vUNiTFr6xnN241N87Wkd2ZyZXPATIo+hsdwOXgGI1+hg47
8ba3+Q9IdTMSDn2ucjJ/7NaLT3qlyfMdofxV3sMNqOZJ57bHebpV9t4AakQrsLS6vodr3oCXEJVv
jLl5V3U+WaRec46DdnigyfkgSWeMQ+cDgxNGBlmWn4jk4XNUIJRLQ0OB6x14c40P/U3PdlCCMvWB
QUvIJv9383PfruPwZxLHcwCfFBTTMLSEx3QdoHDqqiIniWQbCm+oRuQWNcOaUvYm8sNb/pZU+cMF
P62OUuX6kUM2AWwI4fYr6rzlsc5sjSmZXh9nbcqwZEF1wTGdqcHUgetKtWSncVbM97t0KREcAWOL
WFVNrZeuHK3dSmxgCalDKvh8XlZaOhOuHgBlWZvPDpn6LvDSyJnly/aelcDFd1Z6aGGzLH0RGOOy
9nTYbXcZQe4OYssB53LVOxZVCCt1mZ4eWKlcTqlH3W59f4omRn0lFZkAVvcG7WYSen6RipXC00dY
TKwW1awWMlLY9tvJCkbEH1/NZ9V8t5jXMFLbne+h4XJoBVQucX3LWvaLr2k2rxnpbr1qoHuUBEe7
zPaBi82TSRkBYCx5vYk4kwkns/8KArizuqg8DRGrmb5sT2KT2vm6VHpCdDgrcPLh3ryasnmn4OaO
w13KFOb5WlFHZj2zX2sXSFcUVLauGkLfs+2A+7iLGTcvpMF9bbG5FCqiqcik4XEpEakyQpMe1W6w
WttQqk94E0miW6hMiOgVzEN+fwDPcnu3CrI5fFDsXXuFdE20nvtfTD2mfAkjjB2mASDGPKVOP5zX
RAfEgR4BjjeNjR0jb9f2ojbh8p5Qh7aTxXjvg1OiNBAQfjcreGmw2Xt504bFBtYqhJ886GpduCiQ
IZB5zC4/++P+AmeVOHcrSqqAPMO8C/4Ms2zDGmGp9IoxHaZsrWwBxrE8P9odGsxNjt1YSy2fA7PV
2SituzdeVND/AGSCMNYHEapFkKMDyL/UYWAO5CuVEkp5o/xBY4898Nvo2XJzdQ6EpHyI+3pIOUXj
fmkIgyf9fnG1dMQStIAlR4gmJY+mprmbAReOSe1kTrXv3ARsCglUXa39NpY1JYfuISmtun4aAylo
RXyNXnCzTRfY/RmG2Ylqxmx9n7E+MXgS5uGrNS6J3UzZex6n6dMHR62OHS8QulZlBZKBNwDcXNoB
y0dAysWLLWJA7cmEu/S54jMHt/0mIQbfVDmSSApZxQ9ZhgxWF7Kvy/ha+VVCFOYTbUyeRqOH8TAy
BCefEIPby+6i+pyiR8jeguHu9R6HulNkYnO46NdqWeNHtzyDyUbzNDuyV4p9VrFKiuRXkX8Bq37c
rB7NA01T9bXLmhJv7NIp5UwLqK4irJ2wPQt5Y83qkGhxSqmLSBAuRpkAp1dJTgeu+G3tRmSt/Nui
mRLjPjdXK0vOmbNP6VCqiAScuTzWhL+BmhQK2Ekyti4t97P2YymsIUXV9m8q6hGXgBDjHP1NdMPz
EVv9YDId+wSTyCD3nhB+FnTzqNXwwHm4gVRwgXqjbBnvKXVK9reOLOUOAgO7vte2lZ96gDAqMTFS
8B/Et2gp3trR7VBXDYOhQcIfsYxnFzkn0EJYYnOW+R64X4RkAMDlhIsDcmIZiBZf6twi793R2Z+j
FHptocMzJcqK2Awxvcp/+nMiD1qj+hhHopIQeB38wkGjb8QrW3YKwiDNn000S5iYJZWleyJyZ7dR
M8hUwVEPf11vqny/la/IQtiWZ5phG4ySVaSGnBNx50yCbXogcFkT0kzitB3Q3WrtTN75vo16kJrJ
oskkbjG8ckPHSjL3AeIWl64CTtYXhKMBPonHY0mImXYo4kaHFPEE7WfZoRQzYZ6nVILMB42gbkH0
p3cyYTO0MFITO/f0j5kgfqRmtJIyPOlpymMAV6vMd85gUGLUKyQt3IGUtdnlznXnMsYrjegYCRl6
L4lptIaW/nLUPM8dFxL34wh/PoO0z1pEc31Y04i32E+DThxgPVJzqptZMFzzTHwNSXbM3GQL+z9h
Hx+5m9yVipro/LbIskFNzD9ocdG+DF9yX1O9Vb9Sf8OHAkWwaz4YUdLB+/8BiuZ1cKiMxlxT2wUQ
rIb5oo3BdipjjTrTk6PAgW4qoyNGsxvsUOl1r5F6Ot8XX1+liJgSzkc3NRZgmbidJtPZbFM2ubOz
7ZU6+kQYR/xZ18aZKjcT2+21n4q35BUz4gnfT4JUaz9fyeuZHxGns3I0jxtfesXAy0z++AZsmiCU
dSdW/EMw7fItBsPJwZHtEXWp/GyXqHEbC1ueu6G9W1HsANIBiZM9WJKzrw1UaO7BbEhQWGRyPJOq
zvmNu+pgTX+kGju2OjrsqPb/1eLeE4ASnCYMmP8RYlO1WtLtSoylmzXVjIZ6NHYSqpbGZxSu9wmj
N7s9skSFmNl5dT6ZbgZWKpjTQQLKQcMI/Py5Gta4eo4rorolnrNkB7oFnmhI0UnWvxa2cd3G5CGU
Qx+EZfVQ7cTOKFR4DyoHmBMWQ2BujaCyEX8JkRKOPDc6cBjReLVwQ7Lrd7z90QQ0qzvyHYtU2CZ7
X1rrTn7zalN+xXVbPcWBPUZzuRoJ1AFMNK/+BHEHjMnr0lV5vubKVl665QX4mv1cw+dQRTJTNjgO
lqnksGaWawZu7pzADFd8luk6shARCO4K7DAAnN5ro+NnAq4oXjoG3HO/NFl2wxiIUJdio+y948rS
wJ9aK/qImApG7ZCP/uwhxBbc+OIQRsU2m10nwYAg6MJa7rMrNq5q4MPfi7ghpXhLcgCyDYnQsmIg
j3tUIlgFanOlY4eHADM7aYbVUcg6lkjnk/E2QyIFUv3ZddpSL8m2pg4encWS1uT7zL6XMF33Qv3M
t1LPF+8yXPjRTR9sYW+RSxk/TjIh1on+athDGCU9eInTRBwFtzPFQtYW40Dfg7qzgfpOkimPj2wC
93zufRjBxVj1rpHp5ycjVHOm8RXK9nO7UjRagiwdQfV0I3P51Db+vyCANAYfc5YR7b/Di3kvBfaw
jv/PkyZOD5dlTlWrtOaD7wHZIAvTt2EFR8ExuyA7Qa0MtpY3JM/rgErwDhhj3lIDabbVRM7sAr1Y
+08y2oOQW62MBEdEXQpT8F36XOPXNnglkPadWDLR+scmM01jajIAoj+VaF8SS/KNsG9zJBxveIK7
fq/9iHTVg32a8e3Ryd1m/oIW1T6eHIhUAn2WG/A82cgRzkYsmyj1bZcXtlrLqu98Jx7sjrfbPsTz
1cwRyE4QJ8oh2C8gciAHGUaWmH6oVhbbz/YETVxf95OhXyf1q5CtgNkLAW7WbQmRCkMAEkacgPr2
a4a4s1h1J+DwWhi2pZmUvuH/qb84jrrvih8CMB9+O2odJZ77bTybosSSVZPKxy/rcDdh2aVcUXCZ
aoBLpcXqOOP6cRcJVznJ2okFrEr3zVutrW2Y9Ra9isTWjUHU2gOj1YTVS/Psj1yo2Oi+5udbAkEy
ebqNP45OZxqZZEOA7eN8B2us/7rMZiGHDDRZxEzLZOeP47nbjJ/jZmsNg4D1pxD8PBrrLNpHWZPQ
BDO0Lns8TKmN6/VjQF7KJrXzDxfAXIIasTA3Q+AMUaCZPj/zOAMbwv0NW2/9X3nDpWwQ7t/MY7Rr
rGTG8A7eLD2bBjhMNm9TVgb+RpGBt05yC96kSbp7/A47RkmaF0VHVphnVuViilV5Ye/8nFLKac8q
Vee11mgsfzBpyxwGEXNeR7e++kMmgQRcRT6V1jmkSQekpgXZ2PqkDnOCJGM/IoRkxH08KxJfbzu1
Slw3ULYLio5S19j9tnQnruM2D/Nf6iV0O/0EAcPgjrpeVICGrApbsxZNqlH7V2Xk9ZXjvw1UwBL/
XeJRU0CAvMIS5R5OY21Kr6QV6cjnYuyfXEFXmv1XYBKCeO+/m21qq5xbVW7/Cski/vFn+TETmI9B
uN5Ma/9FV9ME3Nki8+dUDwwvONg9kugkZBrFSPgpF+JIGArzHD/I4AKWYyOfjneJorc8HSgcqgb3
06tYrHboFgjOBO7q5luMkz1jDbXBnUOnZS08fhGWsoin7Fosenb4+E+GMNndLecDplF0E1CJWtsx
MLZXm1Xf8U9LuLc6Ule448FaYcxhfU4h5l/XVn6y3td8AltcX2Be3GZ1t4I4mVuu+93ulGMOfOeT
QdsN6xxiGHZGetjH4VI99j/x4MFNrdMCZUdq6Re72/IIHTcyBeLzKhIcAM6Ido7iI3eRQerOE1i4
1lyoHA9webDMnuNOmrKXTmEiXz+IqKTXXi409CIAJrwJK41DBxDoIXRp5HbAvkMko9o925UIM3Bo
QSUNHpkPOFGoRhvfWZCBQxMtPnKqZQvZjqS0p7QWJe/iVrIK3DqC4ylsXWr48uJQjU+Pdy3EeeDb
2lBiNL+QOcvl01Dw9a6MWDHuZxgFgaDJqVffonb0TELeG6B2fbEoOG/HxJqYerbxJh+gBVOqKV27
7Fqk7c/M5y7EX3jBw1tn2pJIA8IzLmk6eECeMUKJva8NrEpqvl4Ng+dLFecS5CR1PPKdrEHITLtq
gxFYf5GGzr2gjOK1nUy6t8aN2QQESoJbrU7kBhG5IIaPHpcdaS0tytBx6kJeaORU58Yw1KPB+xN0
GyDKC+6NMEywSiNbEo7WO0jUtV9/qrgSR+dtzg70caGsBqPctEF+DY5/nBJNgpR4oX9z8zIXnv28
JnP1Cl3V1UWG25VXnEjinzT4kGySky6taJthgTJZAhthJq0CcnuvEin06S2QGliuqn8sRa+DT27n
+xI20MRpTaZXba+xd27KftlggfeTOFY6iVVBNNzy+YPUZSfNzHLqylBMRn9yPsKExGD9ONiNFueh
gowio3Bgbe46yUshMDGQ9Wu7LNK1Ss/BQOcRfV5qcJ7ZaHRz4SUDF7FX0cT6QnNTPF763NOxn0/M
L67GRRMhc80g5vh5qWpA7ItP/iXCUc4e1LfNLhqkcdp9ke049yw4qO15sDJX9ZRJiJmKbEuZ1saa
xCHn8WjkcjSc/NxjOoMw2YRNBD42s8AOziYKIDsqSUsUZJ+7/ZJ35Pm2JUxnumKEpXDiteJuHKj9
OdkLDmI1Fyy4mRMvus7ijf40XiGcG7CyGMdm7QKurWv3KiQNTWpHYpkEhlqMcyXAUb8yhQzhs3+H
rL0GGGLgxzOP43mLaMsvjPyN+WY89K3i4UkfrtDB9XXyt/dcziQlg3lzqlOYbFWLApIWpfvow5gJ
3tTHVlXIBM/Y0IerpJfpErBhd5keN6YtTJ/O4PobCF10JgIzulXblomt5hN+2cOyK8GHL8V39OLZ
dzz9I5YV5pBk/5Nw4qYfe5L7/NaNIeWFZBxL2K6p87REwbFsZ2OhrT1DvEw+v9qslw+mUSs8sR1Y
eRF2aQRIPPkeku6IQUvzx2E1VjEhk24DCGxVjXN1XIDHTR5FiIOzD+Gbl9ZFstXAPluC7hkWgKOj
EGnC4VUfEfZ5yvU71eywS5tT3zKP+JzZphVbhuBOY7KSxtlqcUWfJ833b4JpibvDKwT83mvRl8Do
iCLehSD0LRENma8jVaCAWS0RIeqoDzj/CYeJs0oMg9X1zpc/nDeshTpx9RQV2ck2dlm525JXtNrR
lWAouEv5V11N6dQ4TPe8nKcZq9nwCS+m6asWc8FVdSr/PkqsVL/PtZPuOAyzTK/LXsOhdMb+XPPq
V6pl20/a7w+OD9SDhetVOGlS+ldTVWvC/PmEcF8nNlznIklhiPbp2jTXOPeNI1pF3s0pTsbirBHR
9s/lnBqHg2j0/TybiqOlAOJeR+KHVPJQ1Y64B2tn5rTN1uCbYLqTuNnhUdD50o/MTZWpN331AJ2y
Bs3bhBsbUWOw8pshhEN+4U8+qJkMviWTeQKa5VggjslIaztN6EkwQbAe8mx5asXNnCuohZMy0YCg
IJEXKSAw8dGMdBy7Uij/wXPsIpZmWDgEa0ny6Y3aPa6hA1HQQGDdMMDNYY9qXPqnW76iBRtg8gy2
cl9/aePoqq4pj3Qq9G2GPF0dSAvilVd2jcf97mXTAt8231u9ZVJNTR5WOmNLYYEaOd/L7NuQTpJC
KDIz9MrcdiszJDJIbXg6TW3dCoGDBTSM0o6ZBxxL8d8YNp4mXGQD/jCNC45aV5Q3NpWFMWsuPdBX
tSJC82NPaxU8Dr3fkEHGSAGCVO2T0BeKy6cv3xkJko1rJ2YKPtrMRsSqmYOOrS+/yLHhKKIxEuCC
lYCX5mUUl25IQpOU9dEC0ltpBwfvy2Yen6OoRmhOF+1Wv7CS1xX0j0lCEnBF+K2v9khR9kNo5oex
0sx6MVh7CxbPQ7X1VNw+FoE5BGv0LAi3aDMlDCDxmfyElPBGyMqv4VZxOBQRU/ZAsU6708FFcahj
Ko6cSbeVOT141Zfz06IzsWX0g9BGuywmPJQt0Id2h8N6i8JSdG+u7c7WRRAVO8uU1PXzkBiucleN
sbnDlcCaMpJtLpz1+0k4qm+YYJ9P3WmQETiMZy7hAwz/tV4XgWAgbBpaNVcLIZFnUcn1j70NppIB
8uC0mK2HvXPMtwjCpesAvzpE8ujntF8spDEZkAqWUc11xxqCNPhi7Q8yyYra+9SpMO+fyw0LY2Tl
kBNPoqx+ifidQww8PcSj7Eg+3MpDegx1tDQiYSRLuWtUHKV6v9fCWM0lhuhq3/i7MXi7L3Le+toA
HBIYNO/+wPMOH4guOHo+VillbRJ71y517zOBPEk2UMmHkntfksugmZkp9/rToJlElen7GDmmZSP4
zy4VVAPlre2skuzws+W7KZ1IKEMu2n/za4uj3dcg4Gq6nCAFtJDJRzxsnjlGqaTtjfBHX0E/+Jeb
NaSKVNTBTA2rGTvF14zkvRV+lSDQB2eYII3szI/iFCfFTSVeK18VtRQlHh7McBIdx9/MMChfYKby
aj6fFFyuvrjdUxAETmqG66zfTqZqvK76yn6h0HD4x8JfkAIKTMGW8WItB/gvaVw6BmCiFFr1iU4/
UNHHolha+3rKvi7KeebNE4z0SSVKKK5WnJPWgPegKgaDqUKc8EF+9/ltLL9b6rTncJbufAvkt3G8
zywMGWG2dVJYSwecSJ/+HQ8tC5R44kdvVVqwBSGNt6F+xYmuvt0xarQFoeAG7xlA3WqiiQEkxfDI
LbDElSnhopPQ3yiEEtxUxp1YFW7jrdQUmc1WVbJk9bjMlmd7ErwUA21s6FfILND+iJGAZ0/JAdup
+nq7jq/gxe+XNray7JT1WiT7ITj333zvPVZIgMLqpzAoChFDiPVayUAqP4ySD908RG8HPxVWg8Gr
IaoNxa8Xt6vueAyB6nWhmZvwV8iPkB4PY0IwSYzZl7Ug6G+Ga1hWDFCLdauu/ugsKx4gAyafAGbb
E27HlOgyDitNIwDCL4GWK/PmE0BeUsJl7DXv21D5QwTvntQesVPJ2r+QNlxZ/jnFemBZ8f1rFKjQ
SHmDDjyGICy1o7T48VbCpcQcXi5DflnYZwCmfaen6abLtHdLIj2swfi1/QxVrlx9GQ/x8F9m59jr
NDxdLXkWIPPbHOGD40tZMlPlI+V7TwdAVaxblZjN5FrvGY1DE+Sf7juKDd5RSOvZ4HSU08hGdXIF
sHQn810iOC7g1Yz10Ue5rZntVtrH/Qi8+0v+VT5kJKDH7glBpa63z8Bj5OMV6K8VuK34L6n/zJk2
2aGbZCLou02IvJ5iiOizuA3DxnwW9lIXkAPWNT9Oz8u1wDmV4bDjc2/QfVkwYSWxASvkL4OPLVbD
sDFQF04bOUf+sM+xzQ+oE4XDolch9mHlr3BRjkA7HSsf547LQj+Psgnc/XO1yo2mP8j28DJ/EB+2
hfONzJYQYkJALt5ocRmFVGNX5eMhLTW9NcgKIFWq1K+47DmPM9WWYUtGIJvpDrr/XORgOcK+vnG4
zG/D2m6eZgfn8cUrkXzK3nxqa9Hbp30xAGhhqPCXW5kFf0TL6vgYUBOwhCyvn4wo2aF8aQwRNXpJ
rQKT/F+djK5FdVEPOai0Ra+/bScImQUpdwbHl8fgzSCnVUKQqjg9OtvwRuqPdQHt176P5Roxfd+4
CM1Vk51VVZMrj0tkhxu/lsgh6+5e3RdS4NcB6itftay6HJSt7lymhFM1Zjda2zwN4NR8jJEf/F7z
okWliksvLNwp96Zq2n7ff0Ma57ZpIh7le1rEJbEpkw1bXzUA20KMHYwrJJfUS2o/4sCeSigfmp2f
E6CNLqsy2I0un1Fg3mAKEdRAtrcA+ij+X8obk0si7YL1/QGHIheQq4Z8Zy1qsl10EXHWut8LV/Hh
1gYsPLtyiPNCdEJvrKMSzBiH6RrUStnNjvrTYIV3AFymawkOZJDPfswfnoz3TenL426ReP/9z/Ps
wvuVpisjlEvyDIzHBXrFrMuZbayBh8ON6EGb/18TyEeZdhDCWUg3Wk/zyS9sjUFo0EKuRPW2ni38
PtXzU5qrZk3sFqgDUIHX+gaTkj6vvxAzVjMrvO4TjsDWcZWr7h193xYuOxts3/yenkk/VIjb9xM8
ShCxT10B7TqsiQbxmfElFhQODTlXkB273S0eTDkKC71COs4dvijwF7fpKkaSkSuD8R/4uT1sRFYb
FRhSVp5fwbZnRiHmn+M1XTEeVXW7DVlMTKmHg+HxE7tnzLLdeAGmp7/+i4Lb5902C0KI3V/z8l4e
YaQ6EQW9tOKiGw3L6rKK3PWdqjr8LTbMhLsZGxasEL1f7ikpgA948NiQICQVEe00GEBWZ3Cz116j
OzMuLpp4cvZIfjSAu6noiCi7KCdiw2zknT5WmeYRsVZnO5kebXbJxbQ4nzWdzwcvA1VDqEqubM8g
PLa0iw4D8oHPsLVIYCL6AvirxgtnAprkChjsIVFnQuXLVuqrQZANdB2wI9mJNDUzOqnMt3dS2maC
2a1z0Ax/kZ+E3wwjfRXq1hoSxQ5AzjDD5KycwBhpyzxXP6kxvOQKlaMHRc79+odOZ633tAwahEYR
xFd4VBJDQeMgJKNYjVCozt9pxf2IQPGNOtsBJK6oipQyr0vLIQN6Nl8n1wY/QX4syrXOPBd+RNBy
KFF1xuND6O6QPHNmGClR5q3H+wS51LfHl/K3xqFBl7A316rXHCPMYluhmDR3whPSChZYWJFi/Uw4
6gEHc3Ajw7m2gzeOzYGGyKnboTGucQyxPrz9KyI6oeO4KPmnqh352mugTbDpf1Owwy8LcM13fnxn
asPAWQ9B6v22I6OT7arE8oIvqBuZDvjH+IF/wbGHT+NaItQPnDYSllAK5SwvKGPBoITrJBLoGm7c
XypPZ74Lj5bxfpidPUftQBJKNHMzlXeZpJCBVrC2glUTFBd3IjvfBYyhsKxuJ/UgHG8c6fDi0Yhg
pNv1xFRSneF4Ewo8bYylu2Gt2+RvtIYl2f7PPt11yMNnYlv0sWqXjrr11p3sxo6FW+hCH6PYqHxU
jEEo6/bdaf/txlutlrfbbYAC0d1FN17yVgmYARSvTKGxMIhxujhM82jo+0Xtrn0sXDMglJfjaxJa
S9tfsRVgDgz9rPTmBoPkJxsVNIO4Dk3+MuWV5QF0+k4FqeG/Utkx609C+e/HLXfKTwPTdShQPl5a
F5eJRfO7bhn9r0KvqfcDQupPN1xDUiwyFiDSbbRHn7LpIBqFOqbeUx+VthXoUnP+B04+hUwho3Ib
Q9JNucFuirkYBQYRpbT+d3DU7oEnIm9JEuHzw0Yxl8GZPOxPsoz7suctGvBGMWBxFGHsJmCNzL2X
NfHVZUkMkCcfnnJN6UOTR1DjDJiAJQlU2PnnHLSR7OP5p/BPTMjK3xSKLXMKCtLR5aOVqOvIWD6C
/7/YY99YuaCytdPHF6QdM3lBHvu/jNn2C4whUDVr5rQxyGybVQWldwhi2+7/1MRM5GhoRvHHHcAp
t7CP5j+k0qAgTN6n2KVIlIHqi2V+YtA9T94RILh5zScr3sjcWbet3/p5Yeq+GpKwp+5Xyct18iEw
Rh3SQtbsi9v+AlkfBbAxM/EmFx80ab8k5ycv1Puz1PA2Ykr4hNrkqlJ+wGT4GI0iHyYm5VxGDwiG
cdbuY1X2l+BYc8HrTQxJVBlC1sFt2r6/5yUaqjOXd26dK/Xu9mGmMifjgSmYYPYpbSuBlJgTiVyr
1rBxU6KUKuKKjc/wPhP9EiYXuPFJdPQ9I1AQODKlnIdmhSpQ5Qc8zr5GyhIqgRA5JJYjOmjmoslU
lwTd+aopQDgar1Q5lWHnic8dn8ZX1q3yAxtdqztSxGyRrL2E5hNGiCjhZ7wBr6ji+qyKSwc8WRnD
6sYT5Io2DumOw6ckFCaAfpZFwLeM6Yy1F1H4SgsGQbTUTz4U74oIOfA4sw9UIvq9x+6xyyl3e/ea
A1yIGTW0NdxYAwfosDS7uMx+3gSgC0l8eHzrbNcyWKiapQmcA1DnoYXrYxBpJD47AezxRkHD7X5v
nGy1BlASxTRLAZRnJ5feEtPpyWRtPVeeI11kcMqRYWOQkJAon8eLvdRRNrcU9V2FcNNmvldX89BR
oYN49JrockUiIVWGsaXXcHE8nmVr/Lb/yI/lnAaiPoLyul4sLSafxz4Rb8Yizzd8uQ+mOgp6MOu7
2Q7Rv8nLnh8iA1evqHAB+vRpN49ZEGjNnuGA0YK/COAa5MBHnr8zE8escEf8FP/UI8+xueZrcQxH
0IxOaakzdPQpJIvVz1jAFjmYn1F/rnTA0vgN8vMsMTYlF85KeHy8lGoS+hmBPQVTLRw4OJ7Q+GwI
UEBlAM/rPWSjE8F5K9RugNFwoVyUKn0vbiOvnczUN1JnbiXfH24rSlt8glWi1oGH4k46XZQl1pYc
ZoLXVxIJNzx5zsGvy9mZPvtDnYHx0nVAFXv3Qq3F8mTB7yIjgImSqwsDJhmbBzPFsyt4DKVUxdL6
Mfyuu+6gspUP3Jyv9suJ1Fxvn28mkZl/l6J3nWDhchpL67QJ0LVLOElVkNHeDR1AAQZNZUna7hfu
ILw8vVhJPNFFwcyznex72ucl5rKGbqeTQLtAczD5INfWCkVfeZgC8mH9ZOsaj4FzFXqljaTnaFfv
qcFPunS0s/8/NdmqDYKYcs0OcpULl671wESVurLdxvHXIxEnBMvOv7AkTryUEHwF/iMMobvXXaUZ
IddgDqg5ufIgmFXDQgslsa+vJuzdPBTrDm8R8NR051oWl4aahHKBq3/8TuyQRfoIv8RfK8SSNijU
OxgFdDybcMCfTBaBhfAWiVBMwHm1t7JbecB65WCxNeyPlOoZEt00UApNY/tN/Kf4lo+CrOr5FNk7
jgR/WLjFuVAd6XFUzIpRbjyHST5boh4AFw0y/+d2RCldXduL4bEcfKco8jvQvlxwYYFfSfUnOdTY
JTBCpXGAiFSvBMuWVgwPSF4cqLJn3kX36zkjz1aGHSxxdl32CHxdN94XZMq8J8+11K67uQXgsQ5j
cvSmPuz2smLwX9EyitAmoQsprteQEqKZ2IylNK6SihCEmm5RQJs15ZgQ9ZcepyjDdMvX08S0Lgyx
Sv0gV8Cio/L5YYICFFfaQkS89b7Cnf7YhnTbU43y4GK2vgPBjx4MvvWPhkBjn0JsuqnOyg6oCaU8
hIAQv1JRGXT+SvEXM2KfaoLRRx+8gbr07pt22iZmZ52QKO0KM9lPtPcvVWJ4j+CMbK4z6xXBzlQ4
uh+JRlbJlW4Ixuviqfncvs//5JeHLV4NAavtqFzl3XM8MtqJc00tfmDLRFG37kxUUF+BsuBQogya
QxnaG3c3DeDMM7swmqgx/ijqTF0A8MXxlVDGGkI5GESiBPIer2GlKtCDjgnjVSqoUtYCqqazZv9p
i5UWViKcHjPOTll/pc5dV0myP6TimhXVaUAvxnNaYytNXOwaoZbnDGI+SWGzcPXCavDBSFeaYhj4
UbqleZcnhK9FjXwPk0FKcNrWUZh8Wtcv4CREmoQ2yrX32/XHXJQS1wRfeT++1mPETDXlR9QH6A9V
yjwS7RVscN5L1Kmy7yN0Y1cScikPL3Kxl1F2rjOlUf8AUePdeEJM2QX3+013Zm39zngcQZMK3ND5
MPSEWp56YIqF9L5OFTZ/iMXMPkuOwyzoaR1loL1jcnL4pE5adCp9bQRBOgG46gyQ7A358gKNAzZO
FG5dcf8fmpLeIbVaTqwz5AnAEbeHBSogihs22749hOGbaXVJCwXSWWVNCnjD+ZtveYkl2uCM4VvY
aeGTsg2rU7BsJ1we5h6p0GIinpBheSzfAoKrPUpue1BnuQph9JW15uIljqomnC6yNqlfnxYJfEwt
aphVD28K1GaxokmRA3skfCx/VgEJ3jKTsPGDm4AlDQNKFPhnUyEd1tFFrSp9O4WwLnzA/4fRAQOX
vvZs8Zzq3suMJ0cKyvo99k1WCiaWpzgceN5GkGM8HnqSgDlTlmI7NPNpzkEqXQwOzc7pW8L9VTTE
RiXGp3w1kGygEghW/9rCW/ZVYdDoes8UXC/3gQlUGgNG14m9igeLIP4K3GMKbM8mgVGxQMaQ4eFj
7dX92oTkJOJ8F3Vw0ZTYSkLp407imNyfyeet1wD1sx0Hpxw2X2j77//9flHGGYRjjtbCunrT5ME5
CDvXzCBwfofmSEhQoFczhxk6wU7MGEO3RAiuMMAeG6AHuC9gFjzniP52vUT1gCkxPBR/kYY0eNbL
qsK+IphUvpZAcG4Dsj1cyuk8lz00+dIaflpicjyFp/XupIqk5qkD81Wdk7723ywSKfW2uwaahE5o
77Q6xHUEgOLjm9qHTwLftCEpp7cKXDPWyUuvVxvxGEb9CpuuIXo5qRTeb5Fj0argmKpNY7sjj+YL
r745NTRjofpaLtqG9Jtnbmrg9LcADdyIHLFt3FzsTHkcpNAIm30F4j56H+DVlp/Ncl0blPXcWPtM
HXz3oGpVE+j2E9W03Fhnpp/nL840UBfRBpduZtBUvNJ01UWfyOr3F+MtPaMHJCw1xHQ4HbwpbJJr
vPGUwBgL+h+ATeiXcI/0LpDPGmnRxsQ+8k7VzXW9lvP/so1eDwx1sUK9sVVR1/YP3CZaE78IDlxM
5oiCvqTcNN6v5WEUVhlA/tslfPb42VOADeCSOTDxxlWXr7qLqpmXvtz9u5QYetBcuyOyNMAGWzAP
aJErQ9i8SLfDMXl38f6mLw6ydUaSMR44lPZrBHIH2N5s0OiZLgck8edVJvafWyhpKgT2Ksx3sw4t
whHYX5emC9g3fJ98XaTX3HZi2UV6QXcPhAfkPzXC6LktQ5y3boK9Esa0I6SUanj3pyvD6Ygnn8rG
jB/VTh7zbpPJUBLjCYlwWspSPoKJS22DsOtlFEwfL7hut1FlW8fZjaGIn4bu3dzaHGeRYWBpPGa3
AqawykSOHWn5x0y0sgYP+lqeCyuFgHyxJOqHUI2hunRwjay/wouZDZ7SSB1ibpWt1zBRqGa8Y8zI
t/wHS1lrF3cxkEpJCx+yG+k5UUcEnm33Meyg1HH+hMu/Onbdmy+pCjDUq+YxK6oDNaUEHj7F0yC/
XWsJFjzzhz4kXEjkOazqe1PCjF2IrqF4ZN83bCAVwjqcwRdvFQifU+gPBK4NpPl3RnjtdUAyVVK6
8SWN/szlH/05O9vOmD2+hR6ZRERZuwgd+oWG/EHov9sufD2nQ7ENohN5nF8SoXaQbm9CEOwHMiK4
1TanDFbocVwOnWNrbrlR6o+QhYGyYcG5sXcrI4qebFilQL7o6+XBzXxpab5inLS/1Q6SdXFheCTB
B1gUD647fAGVFfwlejWRTDSQCMXcprxvTCXYcT8xlwSUNPn7qTOhuXRivjGlAxmBqo5iUu+sEfFa
avOE5udSuWuS7kQKgx5A2aFPyjhVdGEeFmLBH61+OqdBRDrrtIJHbxLjRvLRP5uizXNWV6cv4SdN
YnmnKFTIakmKTTEY5W8BWL+jNjISdNQn7SIM1xMcgiJ4+zoJWOTtd8qCY8ZoQa8iI5OJM2Z8zIuQ
TWxGA1WCWnysYAZyNdgvylRrSJfqL2hTBtIr31Hj2KwCt+HT/nDE0fxD1AYh+0nxLbChhurPKEBI
M/n3fzwbg5+Ur+UQEv9NUyRCJcRl9d9cQSLy+yIOwTo7I0LGhnXFoB8qYGNHR35nqcKOjBqLLPTr
lKW8SjPtX3/OIX26+GSDYtRMmkHQiWuKnqam+HIGFfaObbhWrNsuFreTRp/AKlUlI3g2pF4jqF6r
EoQoF7owIm/bbbrJ9/V3ZawtlWfMzkRiQlsIKCJk1AL0kyQhWFu9xDYvL6zmSZPBNLolPHPsUsbG
Crba6pXWxVmq+e6LzHWzUWtAfOep1YTM3XHbHUYZLFpIEWohtFUjrf2eLQPbvu31k0FKYJlqMr24
f/F03dBhlUrSBtaJelWWXIZHn0jwPhrfsKEXBbUI3RI7xEEkC8YiHeAxFVSTCnyw7u9+yW5/R1Xu
7YnhNpRMyDe1HOVg8Dpb9tcowJMlvSa9slxQW4gmFZhhH4sEAt205R2xiejywgFucJGpilmAxRU8
7wycBfBwJf3Qnf2EkmsOSDx3rqX0RPcVPOvSjidOzd80cV3CoOoDDAdvKrNqDkXV3yLV9h1M4RO1
03EF4JYPCLtjiY5omB+MEfvzsBf4h2LWWGhpCKvqSygiq3U+un+dEnXXVqh/QzTb4D7RVpT9G5d/
yueVJT3GG5WKdI9RjgwUCagWEaiXdjjNM1+h5jAZ0mtVfh+FoRky9IQxLqxKNFazUXil2wwdSsBg
BEnmoZC7TGFKr90629KpSt5uJy6hNmsGQoYy7Ty09tfMQyH2CXlMJ2QcNCCRTvWcxEgBIARs1+3m
rx9NXefvpR9phCoNxzTevLa+SWE+eilt1cpHRyCiasbySnDOHpG6KU1VQZQhch/NZQ7VaXui31tf
6vLDf6IhCIhU72RSGYrMMFNbOYt+62Y+Pf5y8kt68G3wcwkFvFinQn5SC8rFuoBRemj7JV/cgWnx
kNGOCB4R5MPQp+xA57nQCgotmZJ8Z4Ewz4VL9PSFrJ9GW0C3YoV51e76kD9rfhwKl6vLHJD+RKTh
0xSere6PIQfJe6b+i7rBno4/OIzYfI2FCpXZC6kLHRXlOXlJBpzcTL0U2M3hMRQxzwdgFlCGWVCf
4l+Zk1iDnizvB5NrlV7nmvkoWyw5t04z81fcPtG0gb1dRRjU6bIXeEC+bMXSpRwWBThYnVpJ7UyN
i4vkY3ggsTDWT4DUULWSwzyp9/5UfiwmdkmiAZLbYMnpecW8q3q4DTOBoWxycK4xFZ1EAAMmK/Jp
lHS9VXO/kBr5ntP8OgZdIYi4sOzPtwV7FPOhVF8mg7qeNzTC8POEU/0WpAoua8Yfc7lEDYVR6PsR
XtI/E9KK4OAMbHtVVT7GhaPqrcntXFhRZFRdDsoAXjSMzD4JnXAEfgQUnnexNCrC/GHZCtttLcrC
bJzN8zyYgjtuQGiCiH6Ml3rc9WijQfQC+rUl30r29U7OEGYDTmeKqLF8p+0Lb5L3R6YQaH4+0iJF
aiSAnOBez58lcLg7p9OIiTg9V9HnCeEc2QwEFliPix+IBLRTMnNGDnixi9J/0Cpfo0Uh15eHWC5Z
8Uu24H1yp3VcrjT0Z84Lcbecejv6kzEdKplWdfUFLrPKZUX8QdaKoJC+dE5IwHqpx0cwk23Skj+L
Z4DNYEoMWRAJBLGp/lsEXADTMAGWtNc+fqHQi9XygV/rtqCa9+TsoEpq5aDfUU6cbKjhwCoOmgN9
vRjR3/wfaEcuzRUmC3//Ij7fYeE1Wg9A8uhlk40RJWrWAIyzk/01T4fDrLF3666YIx347Lmgc/OD
ssc4lciCrSg+VUyH2xwEoSmdmvj+Xpqa9q2rNxdb2pS9rfB02gRv69xGZeWstaBdd0sxL0uk9lv1
84NG82nO5kTuKBF67uZigCptWRfvy9l1zqh/yzkLhBIkSXtBl0oTU3jxX8Q8TmFmQCuHUs+3ua86
oZOtbeYJq1mcj+F/73TYZf17yiSjvRMrByGdajqD0wYtyp3Ikqn9UO3Zd/LwsH6XdBS6J8f4hj/d
JzEogZv3alRu3SPh6rKpMZahxiwDpxgrSFcQ0bD2Enmj950cXf3kNWKiyT69fSAxiAe1yScy88uK
M44OFH2DT9n7d3NxBTDcK3U92DG/WWcJv5Z+EqJvfJd3PNWxq+GJLnentyaxpWUxH58FtMTFmyCC
vJcqfl8J0mBvegF3qJDzgNBi9aeQEU7p48h3pH66mUizkIoz6X9v8uwygwU3d8YciaSmDhS1Qu2u
fkf4t7SYS/oG+IKfAJZsNB0IwmeqdxjcAs/2kHX+SW3AzquwonUX4mMKbR8QyPC+DjBuc+hoa99D
/D1t0QJsqYzjLbJv3gmkcb/puwZUNcPiNT4S4Xn9nPA1oZK/79lYG0LpOgC3I+yEGNL8RSxAabA2
D6uJKNJi89FTssTmZq3QQDproEeM2ROS+F/vHauRLQMGEgH/HzbJY7yHTEelziicjiwNwgw+LdOe
wlZLgY4Y3Nofy1zjaCX2XKGPVTmF+yyYQRWJ81MvaZL5Ro4uc6ubeDpjvPytOWI6mDLwX8lPMU1d
hXN6KkyOQ/HT4lZ7VNKiziX6geCiqAnTcF1I5foVblfVTfPnfjb/p+e/C8LTNvdu3uD38+1Uwh3Z
ve+1rp3+6bc6BL/JVCF+IU2G6tzMobqQmSYN1dbn44GSt1TMCpEKRraw+tMfD/rifMRAsHdHotEJ
88omZry/szNEHxNK9CfsU2iKPpd2PTshNC2EyZn9esFK4PqWw1Jr+GQ5lovlSiaMw640VT23YIRj
3BVptSML3+C58QZAQ7WLCFpBjj0y8iyOSsRt0//TDygYvSVu3iKxR9wPCxdFyGtTc6qvgTbGYJIP
p/fQEJQboa/cRKP13kQXauejC7F5IYKqkEXbYYmKXogeqMANyPhLJOzMc0RmDwh/XwXS3R6Pz62s
3EejYtxFnWylz8PB8vYCSdn+v7u6LCIKIsojfHyd2CbvhMMd+pVyZI5AG+3qYMwykywwx8pC2M3V
rewmwOnTfpqxAnjcCO/izfXtfJ/bx5t4r7309IVa/EO10N94D0yXjmGCNxDeL2ELiIISQC61qfv3
/R47icBEf2Djfpz5kYFA4aVe897O5zGjZmnlQiWxpKPTX0P+F1CatrUXsOOZ0eSu33J9C50xYk5g
IAI1y4yloAGyxaCXt4MgR7Oy3dsiYMjkIm3mo0Pzh11v8iiphtUv7R8dFQAMoHea0lR8Qh3Ft5bh
UafgIA9pH6nyWyNTJ/FaRfJ8l7X0cNoYlylaegikxK6IYWCWl0CVFxiXydLztVqlDUK8wKndagm8
/Uc1jbXSI6To5vqUnKE4ftAms/d4AVPn29IgyvAzvx03pliNQ5nSX9ZVxUj18/hBiQSl7fJ+9Y//
oHII0V+aFDJx3eEJnKpOuAS7kw9lNQLt0eGPUzyVq7Q1hAzH50tBTC1rlRtlKaukqJx8d0kUEAuH
jG/wuHzln+psnZZXaAOA17YiY+Pw3e0EZMwssvDaUeHGX7SFk1dNKiqLaTlnpiAp2IGtSLb4M9Sx
bJvLE/jx0F6rojL7OQMaA1LDiAjJLGfwMt78siBSqhGL1Hh9iIOuUul29XCzTbQBLOqYOh4MG/n0
Ma3qdDR2R+rpypl4A0qc/31jJYfmc8rIZdM7x5lMgIbpExXbo4LhZJLL45vL7T4PrxvT0Zzg3VOs
2YXiZNLLZtl+EIGp903XYkUe5pq6Yrp5dRnJ0+IPssqS7+wrrJyoKGILNS+dUm4ERWJWPpl1Q6TC
erJZWUl64R7GgAhwLhoRwacl6HxJO93S2yTkTkc4UPXDD2LUp5/hfmM8yadCp6bQAlq/fm4VI0Al
ifqatMrWXgIgEVbZI99nun3xm5LwFv5JCQ85RBd0TihZVkIxYjZBv//WGcve7pCvTawZTBmvviGA
lJlf43Eadz54Nvaj4/fw04iuzCyNwWmqkKYPCZYocbu6Pu87FHgzORKrfGCV3qyVp6gwe9h2yP+X
3rfgrXNFtRJA9H92ntrl0nf4S2HEAPPtT2uz2zJYSPOgF5dxTz9lkgZuqPmVHIm+GBGVblXtUwb4
89/JM74Hnw0RgwB0JfQk33UdaBKu0zpd2OagMj8VcDYAZruTBPcNE+uvUQAwyq1Qd/Uu6QQx1Vjl
0w8xYfi36EEKSgH+IS04uCw8WXFEXsgOzWP1RO2pb3XsWtUfAwUmVGr6y+/KiHndPW6Wa1c0IjgQ
prTp+Fc2dtamYjLoO22WnmDJ0EnizSD2mQJX1TMCl7a+V5BgFxiPO0ScaJdDd2tCxHYbCAUheSM4
7HI3Hwhs2yrPLNBk1aoCLY2cVdfoR4ifzm/tCrZiZ7PaM9rU8EGeX2f1l6nvt8gJ2cxottHGS6l9
XGZJS5Azq5ZP8b2YGNyPjLS0XWWfI9464ZyM77xB2eQ/q0Go7AevoCrrOdcLbvFik3BnA3miLKtf
Hf9FTBndxiv83jz1Olv+nMxpyTaWqkfJd9TPIsRLcb9e2Sz7F37JDTW3PWS/tf3kyXsnYfeG+PVi
CRfTAJ/x2O+u+O1GlpPLshWCiSeyJdMMeTrmdltfug9KtGVqxuzLFYad6rbYCrl2cEKPivKmw12S
QnCRELmkFU5uhmSQoW6PVdAQxeFa8YD+YeFkzGj0soPV0xAPX2qFJgwKgI5v78WWG88inBFO7Lrr
SJPY76j64wvNEdzHjV5wQGdT6u0x3h0E7LsoWx0ASMUifrVJ2tFWBN14o1NuwBUCxOzNBXvJuf3D
AcijjvM+knRtFaqtXpyZgLZzkuQFlHakmlNTWp5OyuyLL5IVHllTb72SNQpxtmBS1nFS0S+MdvI2
qkkX5TsP5ImZHM3pIIRgd5dFoGOKxOPmUJFwXSDUhwQ8ZZa5Wz1IEP5GziWLWse9bAbCmdpW9Evg
PHX7HtCHxc4YUb8FoV3pPj90TvKV/SrhvaMuNe1GzL0P+Ik8oEIPdCwyLON/Rb4NRoJb1XH8glbz
TmXzJ71DWFJJj/XJKLHt/OTX4go7Zq7HC0VZDoO2mu8nrJZ6kLD2NkMMQ3TUIn+SSztjggEJqElq
nvOUW5xu10hZaReep+6tRcQQq0Afiy/mVBLSN7eWz4C3TIiWtdtTnjr8FJYppMsIC+Wn+2tC7Qvq
pcgb9hIEoD3cQJqIsL1M46afZCotIf8cS18YoUG8NMfjIyQ89DMQParWmSvjzbRWY19Frh9GY4JY
kPdi8arRuLEoCLRZGDs8iCSNxU12V3cA8XjC9e2wAUQfnfHtQkl01HnuH3oMtPI4B46G/ZTXgAwZ
zvBlt8GkpbH8od83fiUVY6Wdnf/wOro2Zl9YH/ib2dCW3YgoyaIApYdcxvIGOJWctVlXQWDWQEe9
rYnYDWI98qiA1TmRWI+vMkqMUDGH53iCZ0Unx9iFl5VnFjOQQ4t0Hid66RdnEstLDZYZmU+S8Evj
9p4a3gVCzfgcsVjIXNmpECVG8W02f2Bz2blFLKpZapp/RoJnEg1LxmxTJsN3MXMxNnYCCo8qKIE+
/kC1UXLYxyMzcxCupkKsnCiD26b8pgX/ZGG435MVqmH58clNRKdT7pVA2Lnf1AUn7KUB4mYwvjen
NUiJ/EvWZPNX3X5FCVmjIrx1bDs1rdhrK3j6aFx07cFDH0F/CAORw38sVtzNCsWc1XTEgOQmEuOs
0ZsV3S7msJePLpSeSStz4MYKshd2VTA+EC4/w8+rR0XFeagRfwUmNX9ZkhwdyIyNPoCLVbcEiku8
uCBJBraqdKtPAb/LYX8OEKMk1ook8cqrAFv6wAOs2KWggON8ymvcoAoiCmFFok+G5byPTZYv6JGt
YTG2N9SC3n/Y0QsF8F5JuNyJ2PTP0kMOdvqE5IhWGNs6o4+I4vxiKvvK/qDKKruDlRc1ec+B0wnm
mb0jJ8uPiP4+4RwNZIJK9eUNjIfMgwn00ib6VfgoL8Kyx8yzfp2GDX0GEK0pAqZyE5yIawzaeNg7
NpVpSMWArQhM/n+iajslqn8BPaainhWXArZY7zAeUzKdd46gnjQbnEw141n6JnPCT2djqz449TyH
ajqxMaPyT6P+S67TctI5nQoPKcuPQNDgNlheQ0UEMBkYx3kilzMZ1BD4aoTkEd0RyFkAsIKKpOF2
Sfdeiy1pU0NIXe6nLJVN8HI6cqyDr6VUe0nlGO7mjFT4BXZyPv/H/yVqCNDqmgFQyMRv8lE8IFJE
ap58xA/ecKONMsen7NhB1Qt1wHj7YJppXnD6CLH3yM0kauQvaHrykNHirD0bnnnkmdWb8TIfdUuX
dsXwFX28J1IV1bQBbu5JQv3WT5EzAZYgkb79jHJFWXFPUxtg3iz4liowaxpFExb6EVxpI5Km5zZA
lFQJD0TMzubbHwUIfKWQKQA2mqEQrZOO4sOEg5sBGJc2udyCaur0E4eh896kl1NK1VBY6L74J82M
pt9smL6pTlOUvmjzmNK1FikGO25Ya5sAbWSUMJ3NiDh3+SZ/DwiELfe9GX5shmWYKq1DnLx4gazL
4SlmNIJPmayJGLuWlQTFNvw0Yc4hYaFUWcQ+3khS6UQKBHFvtnnYEGHLmIkLLZ4ZGMmaf3Zz8twk
FAX3N2np6Fjf+m+y+f5EAGLmtoVEzvc6YEPJU/QzvZvyWkwETIBz+oKve6ZNT6BbZtgW5cG23eSs
+C7zglfmUoYOhvgWIe31P0CbIy2zBap2RN5GzKpg+oCkI28L/KVR97zqunRlgJuVlgNmC0WGigU0
9DUV6Jernq444RDi9eBPzAlofR0vhCDuAT3mVFtRnBQtP5Vsj9DbOpoJTK+0Svzjsq9YPjo04E1N
5XrDU1CUZ3vZZoKj5/n316Nrum3A2f26I2YLabPW8LTpDY8VFZswZw21PGGhrQ9eespfjk7U4JXY
a4jaWm0ZcZM+bIMzS8aNLXjdi/WbNMleN4YZtY0vSS10fuvBVTJC01nwA0AQZmuErlNlCmnIIWYD
5IgsKG8mFSKsS5zv/Ib07rFU2+W8V7zpy5BPx+OiCWTPu1cyu99ER15eupeHTMvSmbCwrDPfh3o4
5D2LiypycKUbWPFacWjbeVOrsPFw440MCUjrwgHuSnFrpJcBSb2TBmLiHUnCbaok5g9/eT13JYyz
4nrmu01EMGFsQmS3joG2Eqdq7tYFljRfRfjWupkhlwDvvSSHV9vBJNBW9E6F/3iwMxnHLieviiS7
MIS0vQobPVFByPLaIa2Uk5I3iMa2SOxaCI3KWztG1fa2+dZtSfy1DXroFVc8ImzBuv6sHk5lOteN
Vjy+7aaCh3FRNS0kVvpwAjZWdzIErLjZv34o21djge4XKCxyo52gHYmtukmtQPGqhB8AKpIaoDXs
nnvxB5agnCHQ6aKe9H9Rp7KpFmojI2+Ovc89ukovYIpjiycG0bOT5RJ0SroMjlZuPQRrxuW2FwKb
P7/2+ZavNCHv1KetQfFz6zf1Z4meo3OMrmY3DgaoNi0YQzeOngch9ZjzkBSCfNzGfngINEXXcWyI
uOTiPaQRzqLpNCUas68ENwMlWopjI9tZR1IU08GriorjqJIBpqlZ1qB/3s7y7Ixl0P4IkelUHb6v
rEs+payDGZe8yxTtEjYn6pp05M4rFfJ8rWYAvJGQibtgBmsJQ1fcZhIZHSWo4cvVUEkGXcMlKnjo
PKQCAq539cLFyIywh+oeagmbAwVddGdeCNTXogRAkIz2/nKHMhR9UUpqxkLTevaMkd2WGMZL/Ffn
8roothMC7GQxa6MYIDQXhm24zmocrp4YpmKbigyn3obWCI3v8pKzKVmbgXTKNpS9IAdh2aKSad+Y
ZMzDH91mDTMRIHwb9OEkVh1+q34kFW88iwAAnnX99EWf8TsCKbUqRQuztcch6m/somsKm4ohY+jy
AB9/rYgiU6tL+cf7/PpHX3U6+e0XY55AwYFekQGxxKfAGM6DuuTGs8Zqx75sDUMetlfnVwOkAjzT
tCWPGR7tyZ7oSAGJ/7vxjBtVSLAdgwIbZAT8rekrxvoSP0J6vnUZscyP/9x2ggQSU2gKwteQYwDY
oedsHa2boFjEN0taImQk7QpZ0zciuWdqF6QPO63fxun9O+VZnIYvbxkE5s5pk2m2GnrfslYCl0WB
nP9Nm6kL9lOYqHt7DKSzADD+5nEa9iGQ2DXU88inqlHKLgUUNY3JckEvRZUYrNEwQ/PckUKX010Q
YmbOPkmL2T+gc0tfxLX1EevkVLiKIx7D8cRq2dDEdl/i8gCMyuNbKEtSz9riSP50vPtqon+3iGw9
CT8CxksMCpku5cWKpc2OX/+5HXPR7OJ5ntmOfxgnh6eFsS+/DvL27mLhXzbiZa//G3F0FhSf2BLo
Hbz+fhooIZIzfC/lcDJnPb9tJHdrOBQlsHj3BgFFzSn8uj6BnHezIySKlhgUY6TQhwslMstdI64t
EonwiUhi23VXj+I5gOWY8RaY53Kolzw2MK8ZivxFUsJwkDIEj80rEMrZAbnenjdz8iQWa2SqP+Y2
ZR97+bho0/CSYHJIOkf5dx1savuFbp7Vpo8lb5zSWy8WoVX40/34ebWTIDJ8zybMtRf63DWpksEN
aJkv0Uqu3UVtP88hynNW1Kl5Z3Smm+sIpEnWEdpGKVnBAKucWlLVNE54g56oHzQeUMpz30dKnbu4
CsA8rv0fg/wSRRfVUzas13wklPS54Bq5AFEZmvYu91hy652rogWUlNo9LEv0QhNaHQGJklYBXNbW
BIZF+Au7AehriFHu9fobFdgWR2xmF6zFD1pYSd0zQTCiJnJElxNuYSFQwjkPIQHC5NNmoh8Vgur6
o8agvv4qYMW0CXhryHFvWfi2JIMwAcyfsUB3/mhbXkntJvp7u6cdZfCK2Xaj0gMiqSLPZzAfTnw0
8mUhG3JKvmKBeSC0CyLeskFp5AzUpCcr+KdyTnIUY3v2EVBQaSQbLG0+8qJZKiwjW3NJ9LMF9vrz
mmupCGSWIZPiLsLlpOWPOTIHyG0keupP4vVpL4O0s1coxn78NqEVIinWx4G68chRe+1PQ5tGfq8Z
nN3zIFkL0UcpkcYGx9p1ODzDgMcRRCpm5+LjkfogIVs/ctnnzSBSvuH6lfNLHj7L7Zfw4a74eZJ+
A8xKUDTzHuoHyXlHZMx+pfVemdobELbrzBoQaoYJkLQ2Cvm99Rr2ek+DF8NlTFL89kSwcRi0T7Hw
+SHvCwmP3Nzv+HJAsAk3jwxKKhJZqCrudcsgOACx57xvWH2PyZ9YeXg6n7VZnolRwTTm5xiwLqt7
pNwwYQJlDHIiFZ8+xVGESMdaW/uALkvy9F9qPGBSzK37lgkweyyr9OC24xoXgSmBk9sB1RLbLO9I
nVlloc2xbApjv24Lj4dZCMw9GL8pyQNnSdYkSwqz4VhpT/V9HHj/EZOWtrBWVbFhCVehy2W4mauX
42qmxN1sZWDOmXns5s9bbTzmLrzT60GfJoRwbmfaVUD6y3s8TJN39wFgPjugdkTSTbMnMVp0VzPy
S4F4xMRApjX8ftpDgvqGLBunXkTdA6R/U0Lp8krYIqN/npWv7AONIhKzkhBAsLZ4T6FlS2YDwhnd
gJllV/aeywD13MguH4hy5OR49LKHGTXt5V30pcHBH48W7BGdBBXVOu5cjOn5xG95yNpqSIvkYu+H
DGkqwcG+Uzr0fkZ4ICp15WrY7ojJBqXPAi71aFCLDKh/4jemKrK+ItcPHViI4yEkCdGklJl/m5Ly
H8U77E5XYt/eFv7y+Lt/myrkI+x3h2vhrTTi0oYKfLiDGwFBuVp8D47mqVgGDjWRyr5hlI6IqTM3
aPrsLSp7pNzI8lITGR2Fg100a4nQ57+MZU+ehlRKwnmG6VZ/Xhnqd7RI0hrqXNgQAl4UnMNo/weN
i4zDaYmXZ8nuVQz0PUymjBTNawskX3QBctZ6TkuqiQw+ZTaZfasKBiMakTf/Y26PKgvOYvRDg/5F
SV8J66wevyIwAd39cI6A0eWUGn6ucVY7yhGf5pQ1mEBgBfh59ot3ZDASKrqoxCP6w0IfVk4wSSUv
hKjZs8yTr2SCH8LvLLQMom8mq+U5fK6aIPLsFwQ0jm9J9GYZ8G8snlks/yglLA83DwglnHLVcXrM
q9rjbLOsIeIgeYPcmJxOyPT14vOuln/quohW8X+AekFTyqfjVuF4TYslhbgTkjjESUMqL5l844jH
PxbF0eIhOI2PjpGidYX0x6H8oOE/hF8HDAxoZmxAhzkz1HB6jqZhSCylghbvssDaAPlKV9qksNpB
3XJhifuiK74OwyDWlwRMakOTt3RzeFRDDtO6yHAGDR7EbXNN+0QkbBnPxj/DbxR8epz5C8Vd+mGB
Sl/OYTbQT5GIwm8o0qq6rhT8+A2bBXI8ARgZrphi5tH/e7AOXO7Ar/3HuVqF9sGjWPkplF/xEQDu
k92gBIDuAeLZr1nFyesF6bVo+Xwm2F9RV/cqFSwTMTMTvQe+S5uF484rD05ajWBysGCeDfqh7pB3
XYoNNoWhxfpb5VpoCO6upoQjr000hb/fznSau/8Rp09DimQao73jRVCu/l61w1ddjQQJ6lUMAwlW
+qLmwWIbgqA1uJPecIbNmNA3JUWs5lq03ENKoavjElTsV1dFlJyite1APmN6dRNYuvf4SUSr7EwI
x1h/gwPJjhJoJepCjD+h1Pirzsg7vg7u9z8FZSui4AZk6t+kmty7w7Oh3lhc/N96GL6XF+2LbCYO
mW1FYWXxor/apWuAIUMrKHJhabtcLgYSBmDEEyl/hXXzbzs1mCVJ2iKG5dKsp6zfQUeaHnM6f2IJ
gRw4hFlbnv5r5d5ecrtD5UIJmF6FAjhwBLBellJmDizhnJBQ5gU2zueDZSriyVgPKKXGtK2MXMvM
nix+1Suk5lv+FibKD6ZuRjDzfehoecHKXgcKw5O3LW2PUOs8vQOYjgWuv0iOHiThVXYugkGo0fvE
xmVL1/zfdh3ntDDYs/RdpkgdygHbQ3Jt7C8Q1TGrvL00sLYSLB9ArNldJvlV4Dlgyv7e09PWZr1U
y9ic86uaJd/sL+slQ7ZIktSRvrZP8t/1qYRZCtq4Xj/xrw0BJIRFLQG5Yr9cTL/WQJWZCUe4cFZ8
pbgthlHof37fb8jI0vh8Qc+hrmQHdeD0p6lLWXqH7ZSYGF5ndwGul0LHlMci14WHMxY7FnJjIa7p
HaC8vwVq0umk68n6fJQ2k+9ZUbM2OFzAxEK2Zm1R/WGELmPBJxqRwe3DFulmvzMME6CPWDck2UlS
pY/AdHHtwHTohpFhGRQPQl83aTWAgkVd7O/xa4KA0b+ZCdkJdGpawAbWi1vCbTRT8LEoevt/NLJC
zT41B1JoJRWZTj53SNn+tMOf9g0MSavd9pA9AhF1eGAebxZbjiZwJYAAN0kA8Rrwol7f/T7KjY9h
h3ml7opL+6qYgUTTCaQcLDi27uaFOk13oWxFnkJ09bnYiWGJRP4ATc1W+SQSYAodLzgmyLG2Il2v
G7t55xG7mJB1Tnj/w3ErE+g4ud3ot78sf4seRY4oMOff9wX+2WGW2/JEfHFGmS4yr9FILBqzxAfg
2+mKsET5eWurXaYPBn4cRk7oRzAtQCgm6FgX/DBag7CYp/CkBdAhauZhBE6qGjW5JCF19q7hcsrF
njSIsqWdgp/JuCvx5k7ecqh1H+wWyDgRcUuUvoiRFYnztg9ruRoJAcOI9x0T/xlXwko6ljMKqKjI
j/I+S8JJzYbh8HylrU0G0FmXmRVY70RAfzFP+Qpb1A3yIRMKacC4UWxL5xIfTzO/D6swDWwYSkd/
ld25yIZs3q1u+hsw1zWUnyRCDiL0b3Lnd9L2VsiLHkTfntJOLleJeR7B8a7ArIKuPtvCfiNV1i3t
pNu6yplRUiBMBBylrNYlZg+GbDFXSo6ctJ1J8aiAJgoUk9uKqj9E5K9jC3T0pQ9KdbVqM2EWO/jz
vYiakEQGeAskQA5K3519QDHeX5wCuKWIhXbozcF24IB7CWVAFI0Hy8EFY2rdQz/NZE3ne0udaGVE
i2p8D/Eix+y3GcrB9WW2b+ikdKLNqNL0yDU6V9FKf8Y91mx2gomrL5QMyqqBg9oIEmMTgAwGbMSI
Shx3XLcCHH2irMhMnr/JCCeavBAECtHs7tlsvX+BzuzrmjyhKx2Z2nurCn7URp6xLufscpIEEzEy
I470HkZ+iJNpn093RDFMzcpUUvwGqvdtsx3EBJaMUtxrSxDLQzXJXJkKbRS4P90KjMW3gQapDJXA
VEkohs4C5vsaTanGWGwAPOGYlsiPKnhOeB7nYXAm3Z4WQaYu/9tBaVdSC9L4g0HOsdvJDi8cJ1i8
ffbG9XhtoIel3fqqIw/RH8jRfVr91+QiL2+xgDsB37x9C8mAcNE/pDqInmCAjPlZG3LtWOC3wRv3
M/VslWHPVMPuM1dFWEotZSviiueOFeGDl98sTn0SHVS31U7se3X0dbNF//ftW7ckNAQ85nsH2Ti9
tlJ99Es9bfrCa9Jy/mMzPjjjNxDiDoLE5xe0Qlm1xtXkYysKYXNCnthw48mnFp1UTXVYbp/38Qks
km9asKgy2qFA4QoD4bUDvT4pXZLmB7HTiACuh70uE9/5JdWvJGXNrrMvF19N4vn7O4LjObt41naU
m6dR+5T8yYbTwM56b0J8vuETFueMIDXpaRDUNDaDCH2cZ/1Hx+2f9N03Zs7xQ+A3NxaDIkQWQA0X
96mM2HIuZci3Md23xpSLoaDVbSYyT2PqrIS3pFBCxUNR/S1iMyktNVjDAsRd+0pJG9dRWbQcdSK2
w+i6VrFITDuxqOshvZieLyLxw/Vvzw2K06gyBdEUD58pjXhdyshVaH4GuOKzTkVsPqqUXk68pLqw
9zw8EPQiDhVa8j5qscPhsc2h7K9HCqutGyz8tZpsvMS3LNg+1F/4Rqfu0sIoitEUtNJjcWXp0Vt1
2gOAz5YtlfI1xWHb0UbGj4a3/bixBSOKKXM2sDOY/4WwU396SiqrqNlXqC4nnBIF04/KzUHP5xQO
EwNZwEnldyOF1M9qJlHemmsZiEfMOg/eaeoQu793XJg4C4gY9jQ1jTAF0mhy8U/H74BqfU4tWb/+
MV99Oxg6N0LyKpVm+OI5H2kQxZkBJ2zdvXeW7kwNMGiBwKPbz4pT9VUzwOWD2eG5+dMkfP4G73CH
reHFPZiImaLJ7ma+BKxj7419jQ1J2ofBs+z8WmvbwV4e64N09v9gIbIGDqWQ05JCHQcMwKYuQQY9
IAajworyPvmeaG1ze0IsONKXavNxB0ZTr12Ggcztfl4ZwHg/VzFeJKnipnqqilPh3RWAw2KZVi6K
Ped44q/J1EO8mf5+AM7cZwBSQ3x6HdlJs9QpdCRx0mVgLUxuV16AdqqEt+LKH3ITx6P++SiTDbU/
/M1uKtOaRR4ZuczX5iuQo98W8viU+VTvtA1O44BjXKaHKUxaq+aMetqPjcdfgYa6wsW9MI4siHtF
HbC4R/N6M+oBq97YStSCSVKVgq5g9a+U+7EZppJX6XBc1G2jSk3pkVPZ3QsqPbjBlkDGmnjj1tXh
AkLTl4T5Smn7SCFEzWeOFE3z7b/ScL93sTdAk9o7l86kRIsnG83OUHhlZKGMZep4Gf5+3Cxpmp+V
xg6YUBgf/KK+I4nJUK/OqiKhEM9FG4GAvOeDLCl8+7r1y0defUspJwadL9rf4RJp1700v+RQXB4i
S6OyB6Ld5jhV5gMPFkgaD9xci1kYd8nZotyxVD8ZIb1TCb9ApvvjBhuX9keqtJE+dSa7DPpfZbmH
ZZ56Tk65FKfTbFvnM0h+P6VS2jmPut1Gh7f+AoRKQClLoZc42YMuQgEXSAYKw9Ac7MwaQunkj7Af
x8OKYnzDH08CmZTkJaHqqe3ofLEHmwRAFVvoqxWbtB8lDTK40NQTU7T2M4EMCFfPe9NNcEK+LB0p
bijkl18NTp2xc9LgxYeJHnc1ibFDt9yn0TYPWxX0a2sGVEfXvTpi+ryBKm/kkr5VZrCbQQS93sCn
7lqCHMPfYxWjpZ7GTuzJsL8BHjzyoX4W17BGpTSeFtJ1+iihHBJmyQ5Swii5C2DXBqWnuelagBVd
Jpe8gomt/1J58Mh5iYtu/7taCYcczZd0eprCzTv8hN4oKrPfk2nIASt6gcvXFr3Krd0EAWjJqV0Z
CtpDO+FYsKyObn6VDG9Z9IbIIyP7uiq6kw4Nu0GYQD0WRhGg7uG+YOy6vc241K1P1dy4Qdn+rZoX
RR76qInszABrY1lQARFxqDWLoGIMUVRPQV+9GtU1tbiMh99/ZHXGlqouRRJ+YhYU0iD04CziwauE
LTmilNXj28XZ2sz72vmqI6816rTISFSIrBIUZuHYEw620cVfnoQd1aIat3zYP3iA89CX36RnZ361
Ic/n9AW9WvB/N8mdCoWu6uDRg53AxaZqjFAa9NYy4JCmoI44T0bSWhvJzvk9QKF3wLWgAgX8ls22
BC6u+iErwF14ky8Ed2s8vgXeQDhN1hpd6VbVChjz7igF8y9WoF1uxJ9XOg9CFTZWyTKKs/3paLk3
f26KUnuSThBjWpgiafN+ligcdGTzM1OgqU5PTRiJrF1hnAMoFY9pSXTx/2ASLRLC419z7SrN1PUk
/TGCP8lujQCX1cNHNPOWFfCkzuCddUVIlfPWUCMaP4HeGgCC93GM309avjmBfDD6dFLNu0UdDaVS
a1pz2c/i3VaM39/ajSSnqwy6QyZhMLfA+qzK9KUfZYiIReuMYTLaZjH+7xqW/nbZU737H+2rmg/6
IB7LWfiW2ggKllFx7wslCtsdu9NHT0r0u8pJRvWa1g8o+ucfRTz31bivHZtEryVihJw6rIYrNFoE
MHa+AaMK4rKc/IzIZClOS1fCkk3aj423w+LY0uB2+2hGEy83SPZw8KHwAAmOx0BE6USbkE7bl9k9
Vzgj2C/PANZR3XRuHo5nOQFhcRsv8+RTExx/WspOu9DWGl3j56+ccFp3ApY8qT6qvnbkqbuIece0
3+86hQLQEO4CQuWiMcRN5+FoaoLYuJreTbG4fa6qBvshe8aNzo0T4r6nKt1UI2nMWDv06sKa6jgr
qqL2RRsE4rJaFB3VS4szeOcPdJUTmjh3YS0yR03rRmiA8meWZrHPPq/w+zXZrcLARuhEKZm7lB8y
aJJxOGmT6X6DhIaDkmqBplADUb+paWSoh61dEpCwbuZWSJuV38nqv6tX4owhRwVOw/OEedNDh5Sc
yNgQm2HfPft5fCDXd1Sd5XAPRLOf31lAHUO5VWqDZ5FxKfbSRM3wOhWlrKY2/av3njW8+OqoQtLh
mv+jTUpt7PavFGkUrdQDOPTaYbEz39QhoMyn9Sxp+S8SriCmIq4bM+Ajb7Dbo7ZRzjwxRgP/IsRH
gVlEB84vtuuLl3rkoPWcu4ysogu+MJtGE6H/rEG1cUz+9OWZ9+0MqP0xhxg3k4H5HZQZ10H75Itf
3wpkIT/IhFZigTND26000ck0E6DvHxhn4DhoaZ9WyNpt59PeSS+xXSGUj+Qk/1IkzC6zViKPvCnL
2f4++Q/3bzYTaLRctP9sHTXAloO2sWoHrCIeSfh4O1u8yaJjLfTG4cZqQ/kcy8AO3saaJQedSaNY
j6Cui6TUXW2xp0DRHaYZB9N5FhNQT6REUaEVYwTVib2ODyMhWPLDKzQ4EQMmf7IYZQ9HqWgZo9uj
rbSOC2PRWQGjEproCG+FDlEJgsBRaWIq+ILS7RPhsOWqIJiWuOtgrh0qFvkp+Bg1uDP6bsJFaApp
vWAYv0LASeEHsPBOeoUjRFx/LZnqOPFiFYLYjUhctgIZbYZrzbu4kAOS8XnzOOiT1S6vJU5qzZy/
aGGPpGYHin6AXwtwW4jM2YNgXNs6hvpQUKs0C8wUacSBOyv58Z+Fl654ohCFxDc9I7eEuYpzZlpT
Qvt3pEDNZykt84R0xmHw8JFOlNo0RwTRcS+rDsstZubWfJDtKVwc0pZt3TA93/C2YuzuvXBH6GW4
o43puI6r1yn78/EWrjSwxnRlSWNesn+Q1jneTEy0V3cd4e+wWCDshehmagq0YDT7vIIuJQKr+MJi
Kjw1exH3dnk1JbOd2nEhGpdg519Ru6SwI2tXnNzL/nhTEoDpRTzjnvMbG3m2wSFFrv+F39RyHjnO
9TU2MRNqtjxHMyZp1LTOxUj44mLvPqcNjfqaXLjGEHiI3jtO9i4ue/ONnYWfEAj6e0rPaM7/JBY2
4tdPH9RdeoWRidCCcPnyylt/A7xD4klzXRO2FdHBeQtWZvxV076iF602UgeVvPKOvT8k9MRfMKaO
fFrefGgy5/c2aUe+R/cfuExxX8/oktks5o9eQ5RDBJkM4sMwGJkrsGdHcBW1/AegwlS8NM325aCL
iHWNrhM+5B8DdQL70yKoPMqgYIcm8St19fIEJgDc19QS7TIxpZuCCy1hbdYI0LRwUW3nihq/sHGr
H7g0u2CUpc0LdLR8y2J17AqvY2KP9shjFw5oZrchL+UrnPA8lLHULa2AyqKC83XMzQvZUjAZoInN
MkKvbu39hqIyx7R4s7xXFC7bw6ScEYM6JOnRf3566aKDuPvAaJXkFrqyPVLTDZaVddQf3Bl95arH
PIsPIEKelJ7U/4iXpGT4SwUI30H2kI30M9d9Wsg679OwrYazxhxqM50BbsN0/GzxW6LckNLSxz54
iMo1J5PaN7hRRa+Q07Lf9GSb6UosrjOMx48ZnvCeuFBtIrpVJs4N+jbz/++WdWKh0mY4RUnRUBvd
p8OX/DSseQuP921b2bMTtAyJyjeAXm91DT8jyjWR1JdnFnIJm5aRD1LAhlPrYBtykmR/etjFgJVo
DSQB4wt1PzC8cHie5E++fvrRddUHAIAjNiLMGo4gTFbgjw03HK6mXQ/txj3r/8fjh7cVNDt0PKrN
17dZ/VoU/0XciQyoJJkcFy9iGkEfpu25LoIxCZe8/567bx/xEF62AOGLsm1QFfJrIF7MWu6tG9oH
+3WGva+n18ig7FVaHjOrmVwZt0Hr+aR4k86fZk0BbRF1ka+pSzQ6lrc/9DnextqasTMENmxJvY4s
tDlQAbT0vnx2Mbn8ZR/oHrwa/e30M0G0R57SQe1Jivi1ZcMrI1OpZp1ZGDksxk7zI2xKGumQRgkY
v5uKqlpAXrXfuLmnI0Eoim7QhXJ5yzZPKU0zGpRbiz7VykA1s9tCgxm1bfw+HodD+ykO7HaPMaIS
1W0099ovfgV1SPrCOURz94J80TnODy2tc9VAqLleH2DUEhq7BmDzCoQnJUzVesrYm3d4A1olwQsq
CooVJBKsCnEWxh3IaReFj2lUxUWIDEyU+MnRS+SzLVwplEVgMlvrban06EPc0gnR+mAweitkgSrz
73RSehwOvSAJ7i9G0AUUKGxw4Qmuj/oqfJkZDEvrpmeq4VFRGBU9zGw79WwnpD+MWcjP9HfpIrls
a7cpCJuVDBazbGJJ9TIkNuxS36a4idSZ6+jcluFK6bGNvD+yJodIIxmabvgjQITMTZvwmSoJlyhY
jlnHok3bTx5TrdX2qikdoD//nAtQklx0fzPyBJUGtydEO/nVLqJ66QRKXsQuQ0nVBzDKaEowB+26
FgcFpBnzCVKNNC7teJlrN+YRkB7fXKb9LfdwA0EylfbWqkklvVt4CzE29wXN2wdKg7aSXZ+WcQEw
vye3K6W5SN6gS+x7kcGAFn52ga/aj/AJVwHbk42fRUHSYdZVpjRTYh6i29g3OFOn4G2Zbs5KKhlU
n0jYZK6a9NsKKVF9X+rBqFw7VYdADzwq6d48MbSSy1lg5WnJPM5DN5k/LiXeBrlXNXgj1D93Ll0r
6Zo2DK08VdVci/NTg/WJ/kRwV5YvQUxekdOLdI7zFMn+eM/aBf1+MY8EIsjKDu5P3S8rwKAF9j3y
Az9a5l6G3GleGKGz263dIlo+dgaQ/7MivFTNOXQefhPDS17hpS9J6YZAJAIyTpIqQhh0e3PRQdcm
W9DiYLW6m2u1Q/6QNyVga0MYXi81OXcfS5USjtXrsE0dfHJLhNWii9I1O1FMz6cpyfmQko4peQEY
FXRY93Q8ZIos/g86oE0pgN/nFRzuGeNp6YkkfKcOUseSUjHQ/K6fsMQuhFHD5gAfaKUyN1IBsE9U
5peMY0dqoXPfNaDYawE9M7S2GUF9IXO1OnI4Ob23oWUplpFLqM5zGwFlRlodpsPnrF+LGJMvCYfy
fZB6f4Q2+N5ohNM08e2CqpvdErX7s7/V7QdxEio2/aO2wmkVyRuaP4JBod7hobaNIrxOVEaWs7CL
ZrxS5V+1AYjkyC4nfhA3zqHDYR/JQNEpfyFlLzIU1Fl68coEUv3Z9mlFYgPYKsf4Cxnbyq1EtmKU
82WJHMn09C8uul6MYjT8KoDt6QIBGUpda5UaIEUpszEvDuMG+fhX+Z1oWUbCJ+PGC/2yw8MPlHBx
5BaV9vmA+zqjOmZkiMIt5eC8th5gsDMKExcsWgWfu+j9POOqvtJ2cX/tCkM7Gv0YHtp89CKV6CC4
SuGmFTerO2lhJ13MYAyy+yAqjuOBc8SIPN368K67byp+8SObAXRZqHl/T8kAK0o3Z3DxSaKP9dGx
tL1MWRhbl6ZqQKeso9ygzzALZmE++k+SZ3FlrQsnNonevMdUkCadJt7c3v70Tn1NZu7eVjC+yWNh
5sa7QJc4587p7DdJz4PRKA2+YmzbuoUfUXjM0xseRIBPiZ1/yixBFVuDuzBWKdv2SUGf3UZ/+69Q
whgwGwUuFxMdLxQ4EHdnnD3Ag1pGIJSYuBFdoH/9h/DY2qk9mCnPA3EpIHl5G2GJtbiu+VA1HQ5o
FbFqCSVBX6sXWESVBkypmhuyiPwQchZKqD5pbCgM23EZa9yDmYME3leS83DGlynf2OecbqQqq02A
A1SbgF8aq81PIBYAb5P1bUjczZiOGWI/F3Hz8OLp+UphCUbCl0BebGPZPhq6/OLp2WlzBs6JmZjf
g1gWPnqbSJhlKoCOUQYkSmcSYNAkEPY/Lk19WgF8+VEe4zopJHRpGC/Qd10s7aR/SXNe/+Miim2c
LztmaIFN89qZl3UlbMeFQEjMl8p1QBo1iYRWPCVtha39SAMwY6rpFFgiO2KhtVBgpYOp3zOVDPlV
sKFvHe6jtw2KhFOvYCSnYrqYi7vqlChi0BrY6uNCu4hxstdmRAKDPsORHi4pREoS5XYDUK79DwlP
I1Y2y50gp7Q+75fw+dtMVxoeda+oycvG2arMB4LnUyGx5TeW4fdhDwWI1485rgXVHKXuAP5L3Wuw
TdpuGztZjG9mjgNn6/peitOMEApPgnm0MWfLSGEXD3NVPA2pFcf2sg7HPg0PeWNkU9vj5rJ+xiLT
ne7pdBbSkG9/+Z+g5L2uAVcdXo46Q1Q904rQU4SZ/S9chz/JyobE4oBJTXlHKsY5LJW+eu9bb+jR
aeoP1tEHz0m65TVK9xJOSFLWu+jn4rvr32lsZFMAVRphRe2XSO6L0vIY92rdpTMRDD3R9iCCZ47+
oCw+94ETGsoG/X+jrm52n2mhocI9mk918YXjzgFoUYJ7Z4+3R4jly7ym7mx/TOcPnt8o7Kv08hj2
FaqXSx+QBqq8947kXVzC2ObqjtyLX7Ss4QYdtX17sYtILSQWBzFXo8Lf1GkuWqcaqhWOM4N3jiq9
Sc0RzxLztFUYrWmeIO3lHW92ACrdPDT1esHB1cTbB0gNQBpLycQSeSATm9uekt05SZ5c6+KlcvMo
gAyVTyu0tdOtSaw509EkkGN77+UsMGid98lUkTOz8NZRolAyHINjd3J333KoBBXw3N2uoOjQgb16
x9cP9gQ/HMPLTyvmcFn8uYVRZ1EjSwuS0lwdQYw0nOXdYk4xchfpH00PbVjlU9MV9ctTse0HW3To
KB5oZdvDmIa/Vu4UhjXQAn5Oz8GIflXd6kilg+brWT041n1bJyk5JCFTvxXiq4mVtxKNJrJV4VXT
PhZrN95ipP9v+AOv4xbjfpXX8XEEc2gcY3IAqpRprCEcY28wZ9Vu7SNAOV//nG2WtaPbT3kCHXNN
oqAKKIQPhT4yV8NMjTA72TzI6Z0IKip9YYsbkWj1DHNysX3AMP+HtKcIBjci0VKE9vwXFnq3fj3U
MJzV96FtOllrztUoqi5kQPkh7s8H/8MA266rfpOy8RPuuJUz8bvS0YsKhpwv5bC8hVlgrpkpKSEI
c5Qp9s9t4zMPx1+W3H1jPVaQyLYMBOzSmR+dFENMNwBXPXbgqtarRnRoeX2etve4hRgK9uh1FjhS
PgCLa63zaenBzSDaX19fjpsDPpSQv6R6n7E8+ywypqinbIN65rymqXV1jnfthUGX/dAALSJBkE9a
NzL98cmWX9LykXx24mUWlr2PbNVHS/JWLAvTDmydhUvBSdE5100Zw5RIFO/vMxysXKFDefjHr70H
eE/ZF5Ln2UB7d6wtN7/icHOG0Y6y6dsYDg6y8mV8XDoqFQjcWVQ8DMcR6kflpN4hCUxtLp9k0PQ5
L0ASeiLz1u2oZi4YTqDPzU6lrK8Jbfuf4JrmvgOsZCwodmHKFgnXL8qWgBJWc3hx8hJ429b/ZHaN
3Zg5/Qr2/g3p3jtdpXeV1P3wSRBiGHO4KVhT+YG4W29ChrqOm61I+tYa3tSXS93ha9jQxzMfzP9u
qXlMTs+i7pprRmfWLcjaq/v2FI7oGDAaMDMYJ4kdibuHDDZqgmByDYEOM7gjaBaPR2NaLqUOtUEc
42K8QcT9nsQFkMjMaUBwTAHc55Kn6d/AdihnDe+AWvnknI22EdNItd5qATgxGSgLl8nWaRdwhYvC
bxqK+XNh2dpnuxtykw/SJumVjkLu7t3t53jEv0MaCG3O37wJU7JoxdpoAtMPltSPVSU/7f1CcegE
loRTmDJwWaBPLz43ZxFq4vS8NHp54+aE0G9fI93DYGXCwBn9k/CS43FQM5ah1qxd2oL7sg/woGFS
yORN6etCfe2n6gXhwqHz0Ld6n7P4SMsOPQkdDBKayxicdNFE9H4TkYrl/VHVBcP8Sp9t8d5llJxV
dNOtnAtANAUZA+/p/2gnHpkidDWnxxoMMGV3M3Ad+qydCUHNgjC30UNeEyOpV4mUbWrWF+wEzF83
5NIEnLrK+2/MwxNd6/1pDWtRqsSTFDtcdeYK+KJSYUK5gU5nw9oYV5v75eCTkJ2W/f7/ezBR1A92
iuRL9qNVVUR5xrpAJYB1HwZ5GNFuDC9HnZ5s3wwNvv4o9kAfZPsPVLoTNdF2jNI/CfnTmiZkJpKd
HAhbd4nq7TVBTApgrJCgKNH9g7P6HNNtifPwk+a7qrLMsYXb66RoNtjGqys6EqfDzuI5WoshPNQ5
ihJ1S3avCSh3ikV2gpGlZfz6JihjbEK1i/p3ULlBWelN/a+NBWrwCgzTOqxrgWYLxrcTSZ2qu+23
Ht/44EEQTzbI3bkWgkE1yvSNkRxNXdzpcaisJzoTAQ4uYwGh2gexUzaFPloRN4rDRzu69+1hcF3E
JcO+FfGmAHgCheWgx+97Q53+hClXE9LZ7VnJ4d5fvYyP7NCL8+Afq7zpQ+cvGasH3iWLiy0MEFc5
TDHcLCqImWmsxtSRexHSMDNXhtqhKUnIpZSq1hhtzPCb10QT7NDdKnJvwZwT+Iox4YDlSS5q28W3
1Ty69vTztY/bT7OLv5X0N5kDiIEtyNgjNkcOK+VjMt1OSQpU/VVG8zNoDNrkCZnPaQy7WV/f9mN0
eje7b+uWQGlTYwGIsiUK76AhKegvWQtdzDi55Ahh0Bgle4h4tWQnCkG4RE/OZ63u84EvehrTL6vw
VTpeoUDMs6Xtpz5GdzutsdjFONGH64GZWfYumzgAdxKh8b0XZAgGnSVHNaceGmMIviUDKme6lUlt
eP4ddZl1H/qnzNHDl6PWXw4A1tWo51A6+pYVrXuvA2Enx6g5D4uL0zvyHjSZ8gJMcJSQ3aU1DQP5
2s2NzKQtcoSAAmkctV/3edXU+vC83bwpCPZJKhUwRk9nVJ4B4SVylPyC/FNH4tJDdDRI62WQJ/iw
DbuP2A3CrjEP0zVW20TLT42Y9+0rS1Qpl+WGkQbCMXKKQJsx9RYuZaEKnlir1OU44B/Qqc8IoCC+
nRNLc8kIrAhDBi/XXqo213TEtez1xgr+Xy10mB2aCZCaSmW5PcDXNTKc8CZ2xtO5fk6qoTdsP0/9
J+fak4G95n4tiEycxz0C99M9XSDk9qP2fvtIlsuXfxR4ODLXyMRSjuBYmIgQ2NIMPAeFkONTs3nw
Px/eO4jaygFiI23mqt1+sY96rcMB97NdUAFPbL++dX2A7TY9zGKqmMQCrWkTJrcN8qiRtbet+R1y
gE86/fIyQhhGRhl77jMqbaB7wYRc3XsBqvJre9D/6AEf4oC9BV5oSswV6k51w1rGTIfijozcVeo4
JeeIN2bdek5hTLOohHFS8v6n7Su1RBoD5PasHIcmTXSiYMsyxKJIvJaJBnz6dmkuP8MWDeGBd3+E
IgEY65q8rk0TRWelO6Xz77l/Dimtz98Q6DhhIkPrsCkfyMCY14SNOX9VPiAcUR9Y+RRXUYCf1Tul
2jSe/T4owZnDiWye8BdcVNUYMAx4IK7LsvZaOSCk+R8FmEbyB+YFmGHgQxDnEYgD2lc1cp9YPQqZ
rKPu2MjaZ9r+z4n39pu4ZTXBevf0OwZ5hB50s+Jcad/7irKQM/ET9ILdLGuZkWv6Ftq/aSJKrWpv
sM+YlfY1tRBZSJ7+3jyErbuB4KsVi7VXJO+nrXXG1rwbzoh96cSO3l72GDoiEdGZ5FkyQkyxZHgW
6sHgQ32jpR2sc3RabyGWZS4JbFubkJ8d3+gyx60h9qMwS1iGOPXbwkDHkgkPFPDjfwWuZAvmq8ox
QEaQms6P2nNZdUHbuao7pw8Bx4qRASANwnK5cYREQx0isFCecwGZFh0lVKKxGaJmMVUfU7BWEi/I
rlmROxi3lbDt6Y7HdXjDHDUWmIsQ6E9LWo/eUf/Q6DhZ+EmOHgAvPJMMsuVv3MRtNqd2va/jDA+o
gRvqSDYnRQGj6etNGCZLcuITHeKfdnC7fC/U86VI534mlcLktbSENUB+Mf+0R2sCeTP8EXfc2YJf
vP+pJpOdql4Q/QrsNtNUgNjewq//LdUv7dk9gS3nv7y9t+GVCk0Y3Q0SmvcFBhDDTyiHbYk4ZEAu
Z7ciDFJlgWGTeNeY43+uc8XLXMSQnZYsSK8pY/edZwbV8W+iFj0D5ShKkbZcEUr2IlBJhCiXYFlT
V7xuYBmL/iR1Ve6qlDcXJiprt0GyeJqnm2T/VC6AUk0f+7ydtqRiBXsz+6WFfJzMyd8hfboy+Kpb
TCCvVerzqnUiLIaowYiM7oozAAbOZFa3A4M32s5JHwfg9enY7yhd6eJgE8p9PYByasssRnHgm9xg
YkMuCd/uX/89iy4aWGvOWLOL8QcO63fGE7js0CrUr+nCTf1sfeV4Floap3XhGiTke65VkM1Svlwl
7npIjv4YmxL83wXJeETyRhKA5HB11ZETtTmq/bvab8ILgTLxAieEp8xG3wiXGFkP5nzmeoJ6oydv
Z+ri6uYy3L019/7QYy+ISkPpYSZObcFuuX5B8vZCpk1tHyaV4yjKN041erpDyZ9ygZsb/gzp71cm
DObgbe43nVbywiWXKJpKM6E7Qd3f7CyWSzfT9CMeXpW+Jak6QirlMtOG1xxgCEV3kGzQ+gc1HXru
czVg6IkVV654EuxRQEclnJph+u9/Lh/XlO4bT1KkspbajntZPugZs+hhnwmhDAtigG62tbUJs9S7
yiHmLJ5eM1ASgOH0ImKSPa1O12TMU4Vj7zem3vMfCBPAumMHddgJhZUSmb5Vam7GzyClRhmXonDB
aaAqS6PdCUMwo/rFlOVfQljl7i334zPCYz5cIhLOolnYfrl9BvdHEZPW5yGGgAzNgFlQOg792RMs
aU+5mQhGHiLU8FhzT1zFEJH40KEwABdKJr/8L0jbNwxiRKfD2xf88SKTeZOiNc4DOMAyuB+8yf0O
WNzhqrUMgP+ALcTVXvS8EAWF450l86aWvKaqwVbmTAL7rhmjsLm3IH46hUZ3/HP9diJpJB4yEYV3
3caPJBA0rpkbgZgb4+ioCu9L1c9+fEayoxH3rKQflOJHHUhThviR+6vE8fxjrLONXHCtwtdnPaNq
ym9c2Cz3A29oTJ1jSaDgwmnwSzjJgp/H48kXPm2xIgesmoP8ZjL/xJayNXxD4Hs4Ykx+nl8bVt+K
KdQrdkd3h0mHjx5K/SvkBylQeP7d9BKTj7UnXoMeOKMjTrzkrVQG2DXQBu/O0CjTVLi0WRRUcv6p
lxVh2diz8IJg8wtyLiGXawzbwmUjfp5Pcy/SAOHq+7Cdv+mRRa28cbXxM1p+Cncb9lIDYBI0ET8B
RWGSOIaArBt/DALGFoonDl/P/mHQKBJjftJ7AF73EsHv+/DDEBh9yG4mBD6w2dZe3GBSuKOtaCbH
l6sqFvRUgy2WjDK+etYqhgnvkVUAY3P2cm7BHMpltMSmpWOU5o40mI0yQ1yClq/KQBhr4D2GXlXX
ZKu76r+PFcVT2+S1Rq3PxtGMIkkvVKoxP7/akegJjBhrGCwxErUD983Q9pZQPe9/GtKtDQfVl1no
j2PF4KXBkqPHI7jFpQEtmfWwF/X2rUuOmyaMT5A/GfDA5kzPv8OQ0zUZYBy6WHka0GQLGx3gzNDD
hLBdKjRb/dfifIla4zdAWWwmTcltXaEY61a4gUlM8Y7qe0nLGfp49nP6KBCJarlPA6rFoy3Tosvf
bi36Gd0yo9dT0JewuWPJ1OdZchoarYNV967anGs3+xrYaqZxb+a6euVT4iBw7AKxRH+Bc3Guh6Fr
7bdbEoGVlzmoVgms1nktMmSbEw9ioHhqoIV13puwZY+rJ72PW2pHiz4gFy/6C8jI8oyOjtbDJjUt
IRornPeC8PtN9itu/ooYFD7I5PEmGg5cGGQizScZZ1x0qWcKA4UNwo/okYWCApHHjwnXEP+nGY8X
rNPa8jXJyc9xzd1Ha8N46+yalaTVR3a7TrggXhe1gUz8MYIN4lOjOUj1+qmS2kZ5uC3pRhKXV+L7
hkqVmlaDfihkUT+C4StXUP9jCqmdd16sPg896qHricRaS/QXBa39PpT6C26kZ1vGDYrJBob2peEm
G5S8l3+XUAMM9yk33/7Cq/BvgjR1OEAq4ve+SHehGTMJRQRvZqQ7+Pxg5eEg+6t4tJ+XpvsHSwk+
VBLUHk4q8XADEM9+hGB9htUw4itEnN1wrwYwdJLvkpucuAf9fDQVqJMMAvsZaTQqxsBf+ywEZ5X7
o5c1GJ+USK8Z7wIZAScM4NEzS16n/yahWrSkKNU0Z4Wbj2GndewxmZwfE5TUYlUvYgFhdDbkmr5g
LOZSlyD5eYLA6eKYsFmfxhx7FEgS7ZKRwxLf+AK4iGTiMXoeZM/272jKdTY+L7rqFqIIje5RB7xo
pSGdR3dpNsLujjzbJ6qG8x+xm7ah2vyFyotJrGYUmQ4DX2ov1Mt4fz4fuo03Hi2BnSpGfkfzeNz7
uAU71J+QjnRt32xsTzDsaI8GQY5SpkjCCzBjzyAcfKPCdnAILcX5pw5M2xvewiTj4AasSrHcBNdU
d6E7eziygfRiL+hjY5TkB49c22/LpuHZbegPtp1/Fz70nX6mS3uH5aGH3LRv5KTL2XuKHb9Tpasd
dlCU23wqXaZNZuCnv4yn5ybLlMnj/rx6MdlFMeOUyQ5dwMdRLcfKzBwlNuWBPFfqvibyESclySoK
mDtXZi01Nbk4aeezthTjNecCLwRGHSNfT9BDqM99YfurSCoWQt4TBf2OQ3qNNXaDsS/adKMbAR/A
mHDy6Ay/ucK8dw8suLgnLJSM6/ICEc8/ThcvQDAy5EKmhb5fdKdlqTY8OCGp6aum5XHsIXZwK47y
VBuKo5NPRnGS4s7aXgJonKZ3jXU48G4iUwAM7WcOqRTAaUorzgJV50uuzkmlbgO67jQHWUI65JP6
KFO6AGKw/w/5R0a29RrDy5jB5gLZMsIobzWQ8Trl/tZP07M8Pa0nP0/7+4eFe9Ilq5kOi5olF80S
E7s8Cmkd5J2rC/SQZ2x9XXPTm9ExikBLtMiUJam1a5BtsVJrvwPIHid6c7KwyENP94olLVNGaWD8
BaKm3el3FA0zm/1pOCvHE3Y7XPto/UlcrMRmO1aEUzqMTRaiD4dkKKqVEkL2GKiKwO3+DOAnPhse
xESpU+Apy+b0pgCmEnBK1tjBCsc9rz4YpdMWj0IP/U7Tky7HR8F8yEKvn89W1yr5AECSDVm7pshk
+a19r+D0sEjG6TpYtFcY2A6WTOeaQJy19WSPc0wukngLwHfWyts/jKgPEpmtdr+vXBdsagC+wTJa
u2b6MkykS6Cuej18xmx8Im52sBvyrXwjvu+8Ok3ajbPWgF00g/8zDgkQeRFKEs/88zcPgPYwFvKb
77PhM0NQ8+N2COZNaIjK+YNdUZ3x6V82ozqRuQNfKwUEY5XrLAvkSFODlLq+z1wYyGlCq++xAuVp
6lADEa58CFgD5Le8fh6tOzvVKaD3fHMNRTCK7s81K44n8nvVIfR8xjqqHeP5NALfz61CEvYOBIOC
wk9Od0xjfqgbP+WvIyw5BcbxiX1iVHm1k820R3XQPkmDddpqH+AvBIVWKDzKCsePINv556Y3J2as
Sy+E3O0EO2dEkGhyKojcV8kelmts8p/CZvngOiW/S/HGGgjsjs51Aexc8kWLZK/h3RyfYVEfp1vv
vu6EASpWKXWCyRG5/0CgzfxoEi1U3PA8k21dgNS9QQOfTqBMaYFRi7oMX91XbvZeRIZFjGEVxaAw
UqDg0r32LeZMrbdQGK8SpijMtnsDNdRg7mG4+Dzgm18DNlCgqDelhdOKRf5XwrNg4TFLQNytpmVt
Wm/h5P96wuHUTocq0Fju1MMpSP6m9hz6m09rTaOGorxLaisGHajSUmZIo1PKaTBcRCiyuZcvoi39
0FuTE+gAYmWPusw6RV6osr9B7etns9HB/3QORocep2PU6MIUXxG0DHkeR7PQZq56tU/wFTN+G7+n
6ZUJxm4wHVrRkZrCUR+5pTptI3KAjxSZYOPybHQ4tR/uIPCzyIYEEv36K2rs6Vn4Whg7oGs/anaA
gFMqxbdizRhbWq/VftS0laCs4B4PujLBrNXBsmCs9Fh4ZPZFBFhovoxV2GA9VoGn6xD+rBJXi3ps
TGt3Ye+21risnE7xyHde9bpkn2kmHAL4oHgErJb17ywxnmyHvSYkR56DHWlFCQmNxkv4ETp0HE4x
yQog8SWDwUX7Or5hXbJq+Itu5t2Wfj5XFPo/UxORuO8TQ1kGSNs5pClpwOPpf8QfOvr1VYZxU0kj
JuLlkwQeXQ8RPYG8E6HibO9BcEqy2UvfEJmRFNg2VKYoc8VUB2ak8/BFWbKYO35WkW3SqXMye/R2
jvf7oMIMnZRuiYNSInV72r/aNfrPhzq0587ufs7BBSw3psz/6/tC3qEYh48HXYQvwFv3NG23DTkW
kbVKYg0Bj/WfpV+RZ+U9KtJdptrZWurwiVVc3wkNfo85j7+wPD5+88L1cTf+B4eB7AZnJFCCSIpQ
5HFVK97AnjHsG8/v2Jcs4mkFEQG9N8momOogPVcR/54bo0lXmMhLdC5WSDKbjtRGGf+SRxAGgLj5
hwiRJd5FxHUozgv4Jlm3Zka+eHaivpRYKPj9A46uMoBOAL3UHwc4vugjy7fHC1r37bOhhfIKWw3z
cmXgc0Dm611lENrEftmVYohBElGUttlH0FLujduYtg5+mds734ahIMnQUgqikpTMFaZWmTcTC/lg
iUrDFGcxGKDhnT6Ex4ONiLVxvb2j8+Olrd1iFDlTAs3PrLXUvbCMR7PgsDFDQJgcV5TD/XiOyQyl
YGSaPAcbFkalT1G5qgNxnwJbDXp3w/V60vF105LMb1tF7yxwlq6dk6qLrj1oKxHFdWx4aElDKDgG
QC17cHnwLZ1kAhSMNY5eYmQux3vx8aRfSRGId8AN6nOAiizcSXgSsWr9iiTcns45jXHIk0z7FHb2
hKl302VApT11wbBhrYWRvYVuu6r7gywnwvKIWx84MlOK2tliIdStTf3ZAOeZdEHJO9FhYQhtoUQb
/GBMbhWbGQlbfV8Q+56F2705mf++is2bfPgvz/FHUNsvNZpy/3iilOYoZgaaUwL0WDvwNRQxCLET
pHJRQTfkHXUZH7YsZL9/O22p3kPLLUT6zEWg2J/oFFysAwHzkmc2XfJyi3uWqaHfY/04SW7PrLCG
VizAoDsketh8VWQDYSOWQC8PCnBreraTD0c6EQlIb2QKFQ/FQ6eDSh3qcPTG4Z1eSoMd9c7paGzM
O9lBilGw02Nx9x0NjMWWRjWjatFA5dSe9qk9eB5xJ529hmXSPOqAX0BbMedACg7Epr+GbcnzNYHy
BVd8/V95rXaPsK9jD5fjGyltXlaRiKRRCzZhq6IfACiaH3lCI7Gd/14yLcLVYljlLot+VqasXnc8
y4LukvpIK/GVgTzKtLqMBb+FsRVnn1eIY1c23l8V1MBEE4I1mSUs1nIGHYJc6I0TvUtLtOQMnakQ
LkXbuWEhnVb7xRMGtZ4kR+PvUmAxda+sCwbaefUY9RFfFKcTaETRtdLEmdK4NBPWNrNgaXtAwsJP
NLBdjBSnsPlXg/394WGbwE5W9WqXwmGGOymrFOP0CpOy3dmWeZWSzpoRw2RYBr1eJH0uauWu5vVc
LIvAjpeAGToyvyiP1WYrElb56iiy16UkYvspwjEezbd5l5u2xM5wOGBKGrt3A7//9m+kWk8lLkpz
T+vHMtZDm8A6WylJnDIWOrIzqwC+wrd6YVovHx8fbknUQdFAJ1789nMuPdxtZAdO7oxvbzVM8glE
kUFxyYO7/AK3elVCxy+G35nikL7G2f4jq5MS9o7lsI2q1vuxDOhdIN6iEv5BLAkc7GKKOIGblBL1
9eFG6/cmtTf1oLDJSBqV2yAM1BeB60UxtGUA75nMNgyNbGTB0iM9zJoArKVOQGRMvA69nhGAHSLw
5fzcWXG5A7iyJHTyHjWJuG5r0jbIvgRaFWJx+Q4=
`protect end_protected
| bsd-2-clause | bdc8f6f95ee26f9eeb81cfb366957917 | 0.952095 | 1.817102 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43,742 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
L9EbKuxxzV/09pnAb0OGW9DxPQ+o+m/MvX4x5f3JCiR63+KWt2eYB17k+9mGgVY+K1VLxoYz0z6V
YvlDefublw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gJD53XIM6IXGcoGao7b+pChhlJwhGxOuVwSTI1iU+aaEVIG37JelabzUSiGlwgboK2Zv8N9/EzBK
Y9pDSGcMvhlTABOa75VEGmta9QvVzRVMjXtd0b/jrdUkZar600zvkPbB8+QESNshxT7B96klkdIo
XvMdlDR/SEQxmh4Mkpk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
uMh613zg14bfl9MaiMXKdALr5q+gvlBiCCfJpnudkmj/VEzNaqE3gABSgWbIJEk6l3XEblsHwoSZ
2eueijgOoGBjZq9eDXqLeir52M0Z4RoybrJFqX7YgYE+2quggoW8XJjUPK7bExWH1Wd6un6XRwZo
+XQ53VUhkTgctFKNHRr7bEqxJa0qk8dm+fTRKVmCc1Tr5X6rd28yRrr4koH3+liBwEPKquwcMKJL
zK5B0g+bSiHJvGXlQQpKzQNF3+4MebcveUUQPOYG2FAjfRJs1t60dgE73q6y3I1DMI/3MguCuvoX
78TA3nOFRYGLkISVFXDX28xYA0EnciH3BlzGiA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
2ADp5V47yVkwRII2+UsRY3zvclviExupZdil2h787eVOjYg5odQlZCOMnldkarIbxDBoj52vjMGc
rG04pAKa/Z3oDUnDkDe8ZMmBI29kynugqgc8aGxYPVKp3KD8EvhnicB6/4Tt66g9A8WsjHtxXLuC
0ImlGHU3T8u48JygeUs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
s5k0DDcwk1Yhkk6mc4rW2ITc+jBCojX0QPFrzARjmvIjcmc9EJT8pAYSdJK1ykoSIGmT8u4U6vaF
5pchZ1NWV4+0T78Lu7ir0M6lHPYDFRgXZTR6CNdPGqAe+Si56W7NnXEM0Yylf/w4tAQ0u+05yvCg
wK+mPCq/91Em5ZiPcvKOHOdJBSTTkSYC7/n0QNniR1mBmd7+dgsFr5yshClYY/q8HngDDE/aNYfx
P9AT4ECjL+OzARXCnbTA6RjbHEjVx1ewIc83WIXkwbZjUYAzp9rYNjFdx68zjq8U1XW92RXAEXCc
AYKv676uVGq/WAryucxGApaihL/izu2+HGUsYA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640)
`protect data_block
TGoYSUtq9QXorwtXYAiku5PRRrofa1QO0tKP2kJaj3QuzD8XFFlvgmBxexyLYDE6gDfD3y1MimNL
y+GFR4k8uGqsTU4X/c+yG7qWrgec1Z/r4nV+jBcL0IflUtTCMpq+DQitly34B3lyEm+/ewhdWbag
sQU92u1xDPqyW4Fay+CZNGjpJEW6bQ6IDAJc7vACSdWHqRQ6Wrr7OvEkDQEjVx6I5FstZJSKRDyM
kkrVQ7wugbCgqedvuZCna1k8+ZH7dyRcyOIbqwtOUx3+ole5A/bpTq1405Z8HHOPnnLBzuvKN/i2
h3Ik0stJQYc41NspCzWtUqxX9Bi28wMdEtl98p6niJJJspPsNRs/+hdLPK8mB93Edi4KWJ/uhRqS
yxZFf7LkvVi+N1jLa10d3keQqXfEUiWSaCDXPOWY79DklbnODKMFO7yWaBJejaztQDzeKsm65LPQ
Y91glKNdw1T9F6Q0eGTfDji1Oh6STnGcLF7Q4+ft6I3sAcFoa+GYAMcQrxcbYV6gPRP/sHvDS/U3
x/6yx4C33M5MP2lMb77YET1MfVMdENnCd+z/ngchRAtQtgE9fg5naOmX5BLqRMHmsj5DVEciFiRM
9Q2PPHT1Qjue1AjcxPnr77595F06MYAipT3yiyNQUYDWEWMMvCiA0DFt+QLyVZD3/1MNiyEQf3FH
Zr907KKaoTMl1xF4Yv18UQDSznABhvA96BcMNpT1h5esJcK7ItvTbfgEWeyOA5V5Yz8+tR8sci7C
pNVbCNrqiJGQqZeZ1EH/K24sMAXcLfjDa3GM1U2aNCNu22TYqw/XKixHntS2NQpSiwdvOmenWtbw
GivCdLZtIXa4ljb4VUy91tWUSdz8zAt2PbUiCBtSRd039hzHSdmTaFIewFsALp6CMFqAmkz50reA
XmQf5KrBDyqp5TYB41NCgltZKr2YxvAdTkIRfsZROAbF0gSraAulVoNdx4iHJRjXJtp4jDe5/P4A
ImbYhhVcSMmqZW5yilWcRLwAH7RsCrGoQt7Rnf5PK4FCKZ/HB91QUxs5jYlwy2C0brNaw3D6r0u/
aPjaIjX5UYhLBF+qrrxRiXnv/OR5LZGSUkwXKvfrj6kAae1s/up3gtdS0L7SZDcBWmvCps+zxhie
URaAurKOkd5D9miHbmFaJwnF8D28dFPSHcUH6O99UiuNgDbNHJ3QAZanYKOWRTa4sILwaHcGaAhO
4J1kYV58zGQJvk0EtxO7wqeP0ldw2qJIfrLOyT57CVvHU1yZeVx5YGakuNvFZSJ+JRtLWT/IuzK5
/k9qNfBfWVu8IoE9VS8TS5kH+s8Hjg5+Qyvvdj56/ZqN5C9R2BdDFONDEhVNPzv9OYQ9bZjPcLGm
7X+s7R/QMCX7MAgFk/KGsYmuNUrNdkfoZojYQa6jX503LHuaAzL5h4qUGHnbMKfqZN6QQNlwlpoa
NKz1kMyED3ybDh4pLlVxvj+WUM03tEEpjZA8UInhTtsQW2AO6/cAXDmA+05f/P8BZ/v2zdyJySVF
lqWiFxf6z/onF0Syr7rENw2MqlwysBHeRhhmtblDQqlzmdAQIiCmVVF90KuXeJcwx01ae7RwPOsi
6DTfuUDOYh2EakpUfAUqKekEUX4SrhSHXGEiUy198AvUQyTz0eOsf3WHYKH/yjasn/4n93pQ8xAz
Vl6qLyqCl1MGp4seT8wPilsm2U4MFNIPX4NWd84AYv2QtqLwfpRPK7UVStfosKqBNDfk0lOJ5OB4
FgfH5tIlwSnqlJUri1nCu428r2/9+Z4Wa3VttRm0szGwD7FSTcR2UIpJ8XxNz+SErXlg19nXWK4A
4P/Ga83z3IcITvwrGdoipK6FnLwOr4YJqyVFMYdzeTBbgnkIOcGDbhH4P+myKi9UM+e1tLA3Evxh
KAcFsV2qWFHtrwySV6c4Gf66w3IGbGXe4kiahq3XXSrBzR4MnYzEvCcPWuczjwbB013/QiXFxy5w
cTa2TWgJdieJaP1pHEqGF0Mf6npoWD00lz31JWqDpIJk8yEPB0wfkerXQmbSOVsgjbAJOqGqfbUP
hxBu8VBTRZ1T5QzCTgSJhSqhopqqowHl3IkRiZ7F2svu8sFjMbHaQvs4VNofyULsCe8G8i8Rze1R
YDtncIsDgERqpZKI/feDLTI2rp/Jo6JQ5bviikRxE2nWKFevLgQSwDD0wvB9eTBhsFe9dHP0lyjE
4ixjvHSZc9EygzYAFrZdkR6AgUF183PVKe2SHNbz1VdJ9HGcux04kk0j+Exib6rj00guXOB3bA8q
ZLg8Rh1aX0K96GB+F/jWPWP6n1vCrcD8PI1GwFXOixPr30aP8LQMWE9Ugyfz+Wvenr3bjF0lUlGQ
JMjzf3OotTF2mxJoTnOSEf/iL53/gD97k4HKqRniMrqcqmJ6KVmttoetm3VopYOaT1TNbpn3Plpl
vaViAQI6dNtQkJO27IF3bi/zJamZ7Y70OeP6VE6+mar3UiiU0kdO2sHDMiK9awHiZnq2PeaEtBiN
55KnxvUnN+p8SyagTY1YeImKTk2Tg5DXDGrpBshLvT9rBFNWwVE5UGLBfV0s2FbgxSZbdqJEyXr3
jWmYBeOD1s+inLRYM2wm1WmGsuqeOZqve1le/8Gzr5fqRhHkVFLqELxEnfnvdGKLP+wle1KSyslW
mVylpNhvgzE0utV6ceJk/yYDtcJXn9YBAfWhnQInYbAORTgcEDkWBC8jr8NSM5+3jpANsWDBZ/yR
gT78qJCAuvNvbLDCEbsmQGFg1518J+2glNpcE8RklqB6svX24Cz2uclo3n/bXyDFASgfSLEkzJvB
9oY5rca8NlYzoAYy9DdlrQ6Vu3GWRAmhf+QsP2HHp4QVL4KBH16YEeycvdYVpy8+AWKZUEOCQDRc
ge0knitBMwnOTbAqwuyEY+gfmaGQ+sRWeW5mm4M6br5HIfz/PHjS9IOnywHOkLHkPnH/jKVnv4dm
sA1HodHPqK3Aj3jl+SPoyGLK7jpwlbKrUvIylrctEx/Fh1idtsjX/OH0jyztyzNW26O46MqwABzY
SYsPvVkeLWEMgGlmyOztG+zxCwuQ1yBL+gzn5qqH4Umai0MooYuwfbgWaekV+zngNUSxfjnjdALl
M871nLkSg1IeDMJ7+oOpWofT3zh5kE2avJInti9kCY0Qy977RfsqUliyAmMy334n2R/ApIVS991w
HuAR1BHV70/d4BJuQi/Le6jbC53YfIa7smiPYqmh5L4l3eVcsuhTUlrXu/FCM+tddtGtqAgjTbDH
95+ajvLbGshRUxAqnfLyd5t6EplRzI9eScZ5Qf37tmPWl+RhKhz/TduXvOGYdZlP3dI6jZ3LrQ5y
yOaAMB1tATpHTrROY8UR+Fd154NjDfwjLNpnuSfMc/zk/1WLVjIDgMY6OAY3TCD0xi0auWNBoeD7
h5tdUf7Xa4cuIGwgwMtKh9T0s0Jy9WBtRTcOMfq0nbJ+9tgd+zPUp469pmYqFeyJIIgFr4k53E5T
CPAeWCu5dBGcXFJesqqidpxzdyQlpm8dD7T8gs1+mrEAm/xcemVe1ATdTFwNxKh+6O5yso2dTFOR
fKPaUdN5LdKJZbiXLnvJ0/lHkkDsxNIj9F2uHuKUfbX+Pe7GdPJtI9mkc/Mb0VLogkoXvUfs5T41
yi7yRnXyAtT6HA1X+8sTCmRxuUUPIg+sNXqET8hWH9NQfVEXbNpSbCtqJghJsQoErl2UeDmT8buo
mSZHpwlbp3CSZmq8f8mfEramnP/Y2NxlpPKz75gqcnqx55eDzA5IblKd2UAw8J+wW5/lNi/X+pm+
RjrK2oE66sU2MlF/oZfWVImW/BFWOj7BAz3cE1yXawUzh48T2zbcRbZAoe3T8teaBIh5HlEEWIZr
aK92PgDTI0Gso4a9JxEUGwiIaRKgyjgV4L4saDQpoeczI0n9kpXlSOpaiekyTSeevk+Ac05wxyb2
oM39FNwn8WmOnpjAS4J8SIUm87TOotKSH6gCy+ohBeavPcxsQxIH7j/9nAyxzCQlGxYtF7Q4xeri
KHCfRs3ryIkGnTmg1saA2HurhpCvHCUJshFbFHlET6mGs4OqBu2fnvYvrF9kAf9c4fPzd6ZiThZw
8Y4wqAtEvQNNcHVn0FNZ6Eb+EFrQRHMVHOv3LonoGbog9D5J8KGXPJZ+Md3hyrCCCZ1Git4sXxii
L/N2NTr256VJFqjqj3VrrewhH9vZR9UAgmjoKp9Jz+NliHpAvNenmkgQkrlY4nEMwv5B1kx/wtVY
yqJ/o7lFG+F4BxBlDnFkqAHeAV0GA7vYqaK2Uv4Te8nbe5p/Foehu/Klp9rVo9+sszy3ru3w90nw
kxKeUY9jp9OknHi8i60fnRsn9IWNn3j9F/MTinR5cNgQjwugr0XUv6Ec3viOS0mn7VW8qb8aCSjN
lQGpux65BrnQ6lYVVR5/p5B7WsEcjkcwwZkHmDgS8Im+AGsjCm5JcFNJBbJBiVfBZ2LnwdCI8G7m
vNXdMfqK+6/dpVATWgCaEZZj2pOQaUAlhDUKJOM2SjnGL1sgTwZ9BzYDlvT8k4rQKkQPN/igN0oU
71JUm2SG5IIHfd7/LK0po9zS+Nr6uw1Jt0GZJSn3+8v4mlPjytuyd43MkgOj3tcsGJR/k5SMqLUp
tNJ5Nf+Y1QJDonBnL+YWKnUJkqb/rUq3kv8CZce6KN/Ci9qYfcxlich557zc4O98XiBPOcNdOzGh
JoUKhV2rT05NfrJRGt/pNibySgGKkYSZBDMva5eTI3L6DUhhXtg7FZh8Vp14KsCe+IC5iuvmcvTD
6c+IdCQfAMiPidWrErtl90RX81o5W+zqXBdfmzLpWi/aVF5gHUF0mlGdUKvjjagQaFcsaPmAyEbt
lJHrKShj05cr3YYjCll+0m3Vj+jbwWdEUuplOb20HYExLwJJo4QwEP2omT+wu0rd4/7yHOjKVF34
WtBc3K4ahYh6dayIcJwic6aBgjFWbFYzaIwQUq/jiX+DF7AZHlMVatOiKDJ6pMhsEMwR9vCUdVSv
6y3o8DC1PthJm7io+7bJD+H7ubiHyLs+3+fyX2Rl3GkLtjVYBw+opCs+BjBWJxxormB4i3KatRHK
dXurWsq7g4ixaHZe1fEuWDKQEAy6A1qNFIHO4MN28ZltrhzAdZ2FFWU8KxQJgSdFPsC375yz70iW
FR87V8uAWnXkeqolZ+4lb9E4mBihCm1Eypqdq4pUK9E0HMvqbf/+kCZNgkq27NEx75aR4ISwB1iR
yXX3Puyu2y0w/PzeY70DQgF7mBLMxsHAI8I/3eCor8GEBVvGL+qe057ZeT4+bfG5138ImAbgel+g
q83E4TMUtNmVQbtrATA0TDmKCi5pkhfqvsOlnNVzCBlOfC9Xj2JVRyyR/hSMKtQonEXOEmHRpGRB
w7KNStcdz6wdDh+8xITFUssnAeqnkAheJxAMLlJuqQCTTlyG49WhjXjBhRopPSrKRz6067ky5ZBH
AGajA6YTodjNNrB5ucOp4jtpzMSm7LvL0IeUeZnHnbIKNO2XjU0gsGPV8mghzjQZTsZ1HsN3L5uj
y29CxsiRb/pmmnUA+RX51e9uiItoTngPJSn5cMqvkYOCWUC729xmUqB5D4ssHZXCQhUVkkVxRvTv
ivbXATJpUmfYoAubq+HwKx2F9O21Ky2kmt4nOD/8EApeVTkEgchE/p1YLT/T38NlDSsEzaKYQeCW
iUL0zSFgLseNbQBUwJE/B8sH9LAEC1pO3Xa3psCF5oROyIWrffkJcE+G0iAhMJnzFhxQPdKE35T1
HTPIDoO/Kiz/qKIlLWLFccGieF10JudKFl1/aFGrPGy//4h4SR4KUt1nWFy1lkVLB5mIUtVtHdne
ki+gE3/kgRz86YqfptvlLLvOeXs18aQB6w0TZYarvYuphCUcRBlVVZXHUQiCuGPhvmXDF552gpRs
nFs26+qNYYsK5vPYTOXC32bOpf2ZFGserZtB5EdzMhKJUXSFwll/RiApitHu60VUlAm7PofH5HW9
QxHS02wKVU0AbJ1hvQVPpaTlF++DgP7vFGNzb9cWjOBStSpxCWcRE3AHCiAcn+9yKR5tdDapYss5
sIuCBbrI4LkdJzgJeLb5FcCl31jbXfRJfLK/w6i/kunqsBvz5iZMB1O2RIlzhcn+ch80aazjR3wb
COEpkhUiAe79zTb74s/NB2oO1JMnduKe4FUa+UHRI2yKqHRZE3odWWxc19axUVi9lkwK+JGb8YfG
sYvM72lP4wKdMpGLkcQ5ViIW2a2TVbxWYd/CUKLDcV7g23+I1sP9G+AkwpbjZfSKUrlXryJ0ddLB
hjGo556eBsFegvE7k9Mbz7rAahlkYVHWQYbdUXaonO50ExdPsQAGFWiP9Odnsso0Vh7RNffmj6Hj
paXR+XuBM8fPNv9BjbIk4ZERi/ZQALCP1TWmet0v7Wp+Gbze8ZAbByfCSenbSsq4L3tl4Fkuewvd
hUrXrO+9n4kGNcwcAvJEZ63oEMI/7h7ZiZ0b+PO7UoUIqEGuPlT6/5ojvqBqvhqZZ9n3dr/+XlMH
UIy8N0tp0K2WHTo9QwOLQxZaJReaRov6ElmjTP+19vKtL+fQYUbf7x04j24/iz0E3Bh63Jz80oMw
7O/YhnzfM337k8bfzNwWcSFYpQmYm6xn1JIFCihbpCSWFQNDHxF6bNPx79HxhP6i9OXq2bvJn/im
CA2GUXnLWb2WVMMUH2msUAm9EvbrDkxgR4Wy65ivIj3hpC4EdiRZywKyDi4z43xiO2+YxSZsRvo4
M0nj5huxPJVYI5yu94LGNs5xiNB7LyT5VI5m+mazs702nmBJg6Zs0wIB4Zh7z+etFd5P+P1405cV
N98TBmYpyz0+E8BkzT4j0AqqJmi7v6yqL2VosECHytAmsGtXYps4xH/y0LvSDApXc3X1J2RhAcHy
ynkVfHBV2d2wn0l9ky2JwboSOZghQd4peAUUwsoK+54WI5qrCU8oYUmjNAIszJlPVtrzunTodBTr
Dmw8xG/BP/evShahEtryAKqs9FN42drmAT32gnY1y4i4RxVveazgELV++vSQqdqXJ7UXRKq49pqw
U0T0fgnsy2FPv+/acDaLHLQ0YU0LMmprZhxmjcuwkbDhMg/r6zVv5i2VWxvTpJpFnmUytm6cCLJV
ZVaBRLsIL7JhWMunQwjRm4hX0PZ6yotYm1OYCFnDWLUurL289yFYQ8J4xa/UKsTJSl6ljRxIFivb
1yBYsLzfwO6eVyyYIBWRqNRcMjPtMeRHlBVRQo8443UNdQc1Ybql3QjPEP1/9rt5PnFaEktZwOCS
pMQCHKGxQj+RlzOndc4l4KB6Q8bazUZcNGWkrLf9aMpIUqJuLWGrgoILroiMowoi4NmFAqal2JIr
T+GYRKn27xcF6pEAz2bNuB7itWcae8eGEtNFOAVs9Yg+bqVLDXt/0Gn/H7Hl2CRJZbtbvhF7QK7d
AcK7fHAnWZDPFUMjUYcTJTKmT7Bxg9DQB3gmdDrm6EvJ7ERI8xamYq7uZzi2xe6zXNtaZe0gRwsk
kDGPxOel/8qh/59FPOn6i/a/Q2KdMI40pCg6Ms/xoL1XkYjo6b/6ADyiAmuaLC/8qvNg7lyZRCLo
lOxw8Yh3DErNmWop0jmoSHgz7GrozlmiDpHxHtdYK1xLhGMQc52A7CLyy+cZGFneBTj/fO13doZ8
mfu7D+KQqxWLuKVCNRppCAAqL3zziPujlLijRE6X3QyA0wX907m9/HUhNJVg5TIv5njZGAueHxFq
8dad1eK171B8Jj88+ROAme0jWs9jlSgplbU4AEU/dfylM1xQrlWyfNOtzrgFeeOyJ2oOmMFgFl1L
5lLnZfB7ww9KbXh0+g/eojwEuhcem8J8AMDl5151xwNJJXOYhPmrUbJGD/tkN8dcsY/5CnQJmBPt
Z+IS/Z0O2OXovOnAgxTpeOHI43l3l/Lb71Y5Jni5E3egmkW+Ja6ZuqyRMx0R0DZ92EjyPPyVMyHR
NYWkB+lDHt+6mkUidgYxxt9RHAf0uwhH2zNT3A8JGJQI8CZM76c2cBFkLgBsiIfKdh9djuF72GMc
rxmJFspzTlT/Cb4fKUW5HxGqYUWK6sCnI1hQNBDxtQNG9CLzeXaclw7+EZffOAxofg1+uJrhpfRD
wMSfZJkCV8xh2rG7CCRzEjPgwV6wK88qlCm8Sdt+/ZPnsvmfA9w8e4JEB6pl5wyOcZFiiBKWr3eu
jkGFrhOnwZHxs6k50xAl7dGp0gYRcgV8uP0qHQbm22bOHnu1ohbvMHWbjFg9+yIzYoygQlEvL5n/
Ouojl00kgURmTqKgxQLduDaYHsgDu/jj/RZ+EtwWauZoBxeRrcueOISw6XQPBzrVl0xqEK36Og4q
gg4LbG4UMs2kgseKE9tVorAg/eCO/LsU/CXZcgoEFQRrAxA3G4NpacywrkWdzp4r6FZ3kZQxN266
NXzDh1JkVhIp9HW3b8wwG89x4FmOOVkZXxUeANzyw4pPlQMuBjHYPb+Sg7hAJdA/MJpb9koOlg+5
nAB5YELjVC8HEZuCKI9k5xhLAFqxhnndL59xifMkEWc9pwAMuz21KQA4Dt79DvedYRY4xV5sM9Bl
pe9iI1Vfrt4/yMkvLoCpIARN8MpEGf2OZQlsieGy/h05kmRF/18+Ozxll9sN1fTX5FDKd/HvExTi
4ed3QLkIyEBiXCvq3rlFdR1lsU1/u8z9PhZWHgrnPlOcavoDLTSpI7wEKIitRVTMYT4kW1I1M22Y
XKWMciYGomrKsS9z8Vcwe6jOE82ho5sdlDjElJLfhKc/QF3bCBOXgOFl4nUBb7zxbYZ9M5tzZPaT
rHVKJYGt3GxEHSyN0jcTWzeP/q5M2KgdUXcCAp122YZEMDx/DtKMw4ehNJSPeOnvQFRe+97JRcCS
jnn6DWL8wYKJsg8LfhlzOTSFEUUI1ysT3wJdFa73E0vFbIZrIj9juKKttE1ldywfqJU5+yiGT2nF
y5N6iIRw9vYJIoPte6mHvWlu7Sf84gtco3s2IZdE8YxUHAhfA6kMZh7sEgtxhFiWgdb4zPU43rFj
NAuw67zVorjuL4Z2h0lOXyHKgWokn8ZYpHB9kCUhST9sm9kQiJffrWEFcLnjBGU8aZoivQxWiuwc
tkHfLUFQoXSdc7yBB9us+EDxCtgmyEPy0AU0r337rTQwCXN0n0N1fpAbA2fYnIe5fmQmE2OSXQ8k
QJrxJ3ju0TI3UEEY7RobS25NMAT8ts25YiaozvA8GOh4CStLwnJdAuAfEpAcppv9LoyTon231VGU
H3mmldGPcN0iHzitwcmBYeADiBksPN1YD4vItVG/rZGdf9J0aaY7PykOZ7IrjelWfm+r2GKuJ8yW
pIn/QrvyBeX5A34FBr/DfyxhzQfG8yHKu0mR2XmTJSLqeMIpEcwBayiMsbg3ndfRaaO3MCq20RY4
NVKAgRnV1O+OtUGJJYhUB7BBm3b7SNXjFAaUzb9KDOwVV5B4NDNLEimPxWMTadBnT2VxPrSUhOY7
ezjSELppxST1Okxzh1rDnWslq2J2UziZT24brOqnsKUDNTHIH4W3wRBa2pcGd95R+hz/Ev1Ig+Fx
Vi7nNCJlgGSUCpVrwXAQUzdFEk9YqM+5/kgp55D01+3kRj0sPzv3b+MgPG4Jo4bzJJW9vFXi4Ww8
r8sIayL840HWII1kuN6p5p5MPzZ6TaeZP9Gv0LxSD3lUUutJiJbbUa9aSk5HRb75dTPE8n3gkuxf
ilXqzkLngGDlB4zuOZXylr+VYLB0rh+8i2S30RgMHyd0VGTWbOj5eptQI7gcyI5oY79km2lp0vAJ
u39R2kYooC1gnR26OWa7IR13vVnYt/CHh1B0sjLvmOEbrrCzSr8UQSMoBW5JeeyCifs54vyBfa08
LCiEnU5+5h4S0ljethY8Dl/Ri6vb8oSyMSYCZjnZCYaTekqzldN6lY9/3//9Yr0PAhY8xXnGSqx+
1RfUiHjYVQXuQou1+HC09cykPSkQy+QKAkTaEhBnpZhpAgoGc8SqhreANoWJ2mb8cSe7yo7jS5wf
4ZbqNgS6fCp0qNNi4lf9PIO3QqNHgnZqvKRd1uPErCsBPNdxHhb1Dlg8EvwVq0Nn5xEqIQ/ut1/D
4SpjYdHBmDW24JLtD98uo08D5Et6eyuloy4INoP3t4IgTbZcCO6iqqCiQ3g9cjvt2KYdCg0xX859
ZZa1dXTool2QrYYujfnUMHsnPsioTQLh9dQySy0xpj2fqKpGWl1Zzj/InZbuBVsHsRGHQqAufQuL
Mp3K4JsArcoqZ6i8P81eNW9Yqsu9wRYGQ0VwkwaMqP+fdTFYGxoemmu55WleUA3kwKmv34Svqu1r
AB36TYk312qJL+1U5P6IUyVh/65AFAjMJSSJKrF+cLNtYhU7ohjjn7E/Yo5ae8UvWwbneC4LaJ9t
eNOPOjKIeIrHPVUCJP54LMkDDrPI8xEyqSCDKM4jtHUn4XzjT7HLYfUj6gMtkrcCknnn7XPiEbbr
XtC3Q/jeTz0teyw0vXsDPYyVUPpt8KujbQ5qHCcyFt0xN22OEs0b0w7trMs7Zo/doEc8w5JWXjig
QDCwI4zN9juOmnNopDvpoXlcFcEdJpiuzo4gE17QpcYrmeGvRx/SZPqJ1nsEl9wTQZKARML2w9pu
uPnjd5II+uCx1SVb9II4q4PhlDV6LZ281x4w8iz+tPr8YfSubg2KprUU06SL91kNa/vOyPN7p4SJ
e+ScRT3e5FCfHlspx5WqGt5r6ucybMetQTksX4lpYkJhDA726KfPqH2QEjpZo75L7DZcf53HJXQq
ahg++BnFxEp+MOMDeTiM3H/AnC/gojFYf+NRiz8pZl/6e8IONF67hZjSGHXYM9XLP40BOMn7Rv7L
jXMZgDpv6smKVKlsjZTXvpCEaREWl3uhYN3/+NjBCtmAfFbuQuVsUW+lwROm3GBoAwEX8DZ4HPBm
iZRA42zUG0KsaDA1U1Gf7+JrkBflXiCcZWrlK9cid20cUKb79uZ+NPzjQOlUnRivOUlZGOum69mw
o9bVM/17o87hkNd+5D6o36gC30lIXDdt1uwCjGlw6agsdtPHCTIBG4SfqIl+M8hzKY/2JKIjeNoN
xBsbHpsVXBlV6ZijBEuDIhWpgYFiBCtVtXxNRMtOfuAxA5u6ia0wF/uGAndAsLVovEYrrQKNWSkH
V8lbtB/JzLrOGM/Vc1v5KZUzjoVsS8qTLymVGrZyytAH3y+O6YuGqj4l21EQpZnn8cDPlNgukmki
f98x62qzg4qPatKEnBU3OpY7vNS5HzXgYDqtJKem5lwQ1jHlyypq1q7oy/mwrbIE7yLpxI5qbb+l
KWOB+gKrPpL8HXBKQpMavvby+136p04XrjGGVSsiIh/VSi60L45bhLy6pijXXGyefhZR2+sT/J6K
2rbb4I3iqLATPm97J9+TdinJSaLmJEMyFjdD2dOPqxeFdz9m3UFzYyfstjBa8mDdxGENP0YI0V8m
xzEaXmgJQr0YPgUqssMYRlkEyJm4U61oEXuNyro/J3G3BC0PuyQv5fwlC5v3zuFMyLrJJi1B8fXs
/2++SD958Sk0xGLC/G+I/PrYspRT7wqdTNfj8U6C2ondc4hRvJnAnqIiW5bMnE5k39T8ibObDbxv
k/8oPvAQtAyuewFciqi0NAtEVgPaRdZ+ejZ91z1D1N70t4C1n7TtuMQiuBqwoQc3/xZur19LuFUG
uXeYDohsKjS0Oawr5mIABa8OamOrJjnvCn0p9clnnon15s16HKG67V7rYYvnRbmQLVY9yWMAzwKj
FOTdfQi0Vbkkapb4dHXYdt/H/UtJGj4EQtRfKAzl+wxbWAOhV0+8r3xWwZjPmR5OzGUQRPX7roJs
Q2owRlXJt01eZh8dbEteaWpA5TnBKQdT+7nJrPUgAYcEQAxM2h2prfbpwv0VIHNa1UMqFfG/P6vW
OJmL6eUKwDw5DAUlFWFTfJpJ6zckzPi1cONRWkMKr9YcH1lcA4OHQZ7MB4e9V8qVlhWwexOTj2co
ZJimIBQMkHzORpDxRBhN4IaxVmcGfDZMB0haB8rblnxIKtGFAlxOk269nI4slWvhyR1R8WFWVTUP
GVRfak2z5/8mX6nd9c8gp19duYndNobRCPcIR//NT85mvfYYD8HljwzmPXsnNIFHOzQ+a1fg62lT
vaRcO6OwWnSw+zK9EBijvJsUaSvFv2/oaI1nYJE9eNVBhy3u3Bor7lvzeupqd/nBVhx65ueILiEZ
kf2DE5qX7zIxx4N1xnAJyndThHAGHQKq3uKNEA9ao11fxjJse4sJN29e4rpe60WQv4wmIZcDkv9R
2yzgQDIhZWYE/3GWDpeUUZNVO45LHrqnip/wuGWZuXntFnfZE3UwRJoSQxLyYQ6IiAokH62cFtrL
cOL3exG7yC3xMbAt3C+IyOSHrkajhC6xIumC1y/RYgB3ydhy83Zs3pn4YVruhwvxsOtX6NL5Hg0/
LVXnOeuLxlO0CK1X8iTQaF9E48zrUPuCWUuuNg/aPnPLTPC9eZ7xKcvp4kFG4YmYNevPTjcL80Ve
Gzox0jXIXx6YhiELET3hG7EmxJ3Q9UBpqDpwF0BXexmRjt5IWchDImS/c0cmOr2nfAwUvbOygUfn
Jq9jDhpeC+r/Wi1W3adCvAKhFeIa8ZrIpfJ/SLSnmhWrr6BnNmOuqtQIZcUM1OXb7sbOIuRjgs0l
lV4p4HHklWug74CWRUmgrEJBlLm3FswkqpjyIWbGhQlq3fWIAWvhcEWo7y1CPZxhqV4TEYBYVrSN
UApeqNnAW6aJvlgAIbQZjvOC6cU49vGdlooE1ujBphGQtZDcSEa7X/ysKa71PAktVxBrObI7uqD1
+g2NuL6pxbuuNmVaIwy9Gmswdp7Gc20EdLvZd+agwDoLcG1ASC6A/7+3QpnonfnNHy1oQTca3qA3
rEyq+4mepyZjJXFNVhi7/p6yxY8T1Rh7nTz+5T++NF8zJ420Jgk3R40I6A6072fG7aPZZAQpvwWp
PrKv2F32zx9KLKd/+a043rUVCmPIeVZgLj6bMiX/FPOGQ7TNFfrNv/iMviEuvZNQ3qlIiOj9JR/F
WvA9MywpBKq8J1evhzjm1hBNEZIGgyfMxbO9tuEg03nt6gw7aU0Svd2WvQ3nybAtueUTUPvoJ4cX
2j4SaiWtcuKo/9zNr7eTndT/1r+j8f6xDJMU9XvYDgY0a4YL2xnsky8SZbrsilbvU1fruKroDpKu
k4wJE0oY74OIjfIgHcHJphJPZvhnI+4NS5uKo6yaMjG3TI2cjngS0ePLsZMI+OPDcgwYHHYzs1Vj
pXgLKVZTuVRIpQlrK/a/tMJkHOvfKpXDBMuhuxfG9Fvai9+mxMjjMyC3A6vyk2B6zRSswRsAGV4+
olznfpclD/lbOv2HSLBrjePUegwabQh1PrZMc6KYWYfnUVarLBulT58wmFUEo3NqrB/zygGaKY2O
F47hFdfurcjy6XgL8RYus+ZNW704cKwhQCw3D1wDLHCbALNgVMg+C+bR15oAdOrlZwzRMRZv9Jg3
YuzsvwAP0Rrq4X/XWKq6qTWzcUxH59+zsizBMnItQt/9tXPYO6iw/umiB/xdrXkRbawFI2XczDAv
bdfzn/mhTzM6dr7J8+lD8PBoL1D2TRrUVQTpQ7sY11nHgL97DnEZFZdWqpG68d3XKpobACZP2Mte
jppDE3T9OOD+jpaq2R8ba7C3uwTCiK9Kh4uX+uRjVnb7Zw6hhi9yo/Nhj9z82tKm8t84Mu7ByRXn
8qa70XHeqx3J/OgvxBR3fi3/KAMp+aXca2USfwBFcWzHsC3SdAIG7Lw3QV4jAbVpmBOK0SVqWE3Y
9UBKNhwHsSLy/nA32jsDjQUYUQDBE5e35hfgdxfl4r5FqzOVAMN27eOuX0E7mh0pl5JgLWAyvvwL
uVjdan2aRpQf+4NqRPj50x807hoBCTJYziEy6sZbLMqGgKgVkULOUCz433f1qyuSB64Smf6/Z/pb
2E/NQnHc0OlwA8/fiTpmO1rJhXQur5aOhHF6/JrBMVDjDM+vd/B/GxGr02vWGo4S2vNBkhh1qBLR
YZZMwV0cGYYB7RtvYXOQxuvYLrxURwxI7FHkAeZnMB7wGSBHqryJ4b9BB1dUzPHYUzosk9CYvUWg
2Nx4A+JEm/i3107abP6ONhfMMPBlnvcQfGL/TFa4RcIN4Zk8XsNe0FtP+DW/cArZ8N8wXC4QnttF
fiXKyY0gKb0R8iVk3pXm7KHBhWUTVmwxscRwHnJG3W7H3MesL7HmS091FxxE2jHIjdzJ5eHOscT2
kEEGfQ3D2eeL0gS3OQzKddiN8N5iQUg4D95Vx+AG5FHzOi1KhobIO07cT11cCo28HtR6pvGqJdwj
fjnb9zdBSdtZyeoUzTKVcsoEokaAYdgNpuC5Oah7v1aO3ic9tm6aIX8PzTaaxAQZPclLMnQp5+Ja
rbnISugkCcAwvUqiNATgAKDfqlzgGMcWtM6eOA1hU0gECfVNc92UkssxgRQFCd81j5j3GoZJ0po2
ov44k08SRTnRsmWb98lym8793srV5xl3pS+s9FIV5oC5U4m2AlyW4r5S/aPwRfiEcjoAm9BK0Dan
fm9KMwqNLSAUYUychFPThu9rMEDXTkDqeVEZDmc2i5wDTtrtIdDAyLrf3f850So67uoON/egsm0D
EmIjJzetZoq789xUMfw7utsx3HBKKxLEYWkA/D01Z01umEWYdnvnTKSbFAWXAm9IRkXItGyHLyYe
iZv7n5IEAWmFhtmrz0DM+eP4C7uEfcAofjh/kVEkaEBfPAeKgfMr6W9jMlZ2mmvAQFmc9uw1x3E3
E7tTmUhKurYqSzmBUHfP34UlR0wn324orTozeuiaS0fVMiohnz2PscCYZNhfBJuDveYt5vzImjXO
pn7nk+pcg9vnu0ilC1rHTFz/BIe1cLqj0yUjY6/V88ZAvS2MNA9jU2RiVO+D2pUAfgxe/7BXlCVr
pEslLJmNFncJiFAO+Gz6gWaqU0zcDJNELMwBF3lv7Kp7xfQgMwvEf5p+8KIUKl6awYWciMHiEFcJ
Ubd6qQUX7950Dw+9WcYsiSx2UgDttFo9PAJpY9ZXpAIroChhElKgCT0OodieThT5cw1v3GUQHOFQ
kcSUoyGTomggZ7nAusxev5mx1cAIsl0SSzxIm/oz8Vgestx2sMs5D1mNZUZ0XzrKkeczRUcHW/Yz
yQszcgqNPTSWNV1VaqwGpTTJPQpEHJK72LRK08rQH8dOw48NNEwU7eqGwZuFOqc9g8iMOlqAdTjJ
TQA/NGCQiTKh2VU8O++4dKFwL21/C542yUNGVZiPoQU/kKMO74vfW3Hg9krWLP3skH9syKL0GY8h
RSgXP7DDN+mugCeoiNJg81n6GlvQOkz4nCR6HEQcvzCfXlmEfkMaZzcVJt9LxzFe9+iGRb3ydtYZ
SMblEc6buNH6Q8zSgERsAE0ZjvWybmDheqRz+BBPqZw/164rA/Jdfngr2av8HmXqqn/zPwxu1lMW
FOqRBTksxN+VASCQDRAhcTUqDYlzUejXF1FrV82bs4Z5huYXYdltvfGciqXyMEPuRmRo4z39Ct2I
Yek40cyu/5lVFeGy2m3d9ZkHcpxVBW05cI4iYtOUUhZgq9rzL+PCChZ8J7xfC2Kl6vAqKEM0VnIL
Arq3KCmlj96/c9bSNhIIl0PamWixKOcx/1RI5IPz615X+N771Kg5+RE/MjXwXVVkTBRPdiz/er7K
87NXNAKh0w7otpcLeUJBe/1/ScWfJZBBkJP9hIFzIAYtGQYtxR8ctIOvO05uxvb7ua+xG0gU+Ted
ymjmJRnIfJ5oi185GeyP8PNcC9Ldl/CEL/tft5N4UZzCYBnvnGbVqyUO2g3s7u3HFCFDQIVHr7rs
8r12W3kNZzHFuZj1+OxpLuQ7GdkdAH7tbLQusFf3eBn4Ld9vpgQLayxrU1P7jKAAuzOddJa8eyNs
MU3dxifBjugXA/jV7/tdpEPZ4aQTpMksklPJ21GWgLQ5qcV3X5dj+ylscUzzUGzKWFznAzariR+5
1TEGF0WEs+dwNPBJ/F4iJwLuBTUhFuZhqxJHtZjZyW5mmBU/Jw5kKtCSFpYw6Olzg0EZJCRhjs8K
O7QY/dv1CSiOjTVmx+Z6paFZUrPwN5HbUeRWV+CNdaNwrSoRRsXZq5zycZrH4172k+GyC/XBt8ow
WAcjpKdfqHcgMvHbi7DDlKVHL5st8Agbx/szXlIJfu6MmsJwzNxxuzvg19ZryUXDUkFoa1Q17Iqc
KCs4G7GlfYUEhNlqgzwENNaGiYu53plO66DT5NYOA6Cv9miGS1XKBI+wxXWqtC3bSvJ3/Qn/GRjV
uZQdwSRA5rmSLWCtTGX07+a+us1y9/oe52BOOufrs4vb9XIcrDTeP4cPm4DUItOFuOoYooC3dQXO
fTwA977v0rLE/MNwiaKdJkhmmpbTJm9jsBGDH+ULmxlepKglH5bI0lGMuH8GUJV2AvFtaA3cgIyc
axP+CUJdQBexfkffZsf+DNFmFG7sSyuNvjojK9ipkpOl0b0UfUrHnPJVV3RoZxN58r+dho9BNBhV
ynxYDldRGDEAsZcHuRPYDfUxlFCaXMN6/4jD/49TtFA7VXJ7troq87YbBwVVUuM0ajX3rlfIbNgn
C/4eVQ5hdlmyVvJeMRrDoCIu5Oo7je2VQ9eHDZezbLOKn5OFuQQcWz94C+6JMemE1oT8WMuOKsd5
EDRFC645Ub+8ifYBsMsugzV8xOorlr22coU15rkPLxsihW6rcl5wLtklu5/bdYEsXxPrAg1H8Tqk
8Ms8ugyhSb71k885eFgI68Se1ciU7sGCFtmofgomvPWDoeBXFmkzcWKPuUwjRyU9eekpbj3R+uMf
M7j2bYJZUOAN04nrAEKvdkNumxrNgRjMIk2vW6KvXO7Q4UX6346i9/KRk+YHrtWHCW9zeQ52LKSt
uzr8i5lQBGBei+Lql9Ca/WDt/ZGS+poUcOv0WyqnARiK/Vq0ZK2lrvvdalXgHcZVp/qWWBdhlCBL
VZMJV47gGz1Ol2gu8piZPEscWy35YB6vr9wQGSPzLYicHdDYk/SLsRSJm8Ut418ny+CkPn3Kg59A
I/9hWmem6Ji08RTAOP78dTFPHClHB7ARzCweN7Hq60xXmxJYV0Hs+/8UwzzS6/bzgUVJdvIXsiFJ
0lifsU0v5Qub5adsUd/8F62QwcnTmrB2KU7H+9L8SfGaiKRZWbkZ0Lmc4N0XXb4FqkmItjEGFdmN
vTGHEVDjFzS6x78BouPNKwVv11RVBlHTnqpvIJv4B99CD217NltZ4KIpTHqEr4hI+o1NLusEud3q
09SYoR31HJTouuvPXsJCcYkJlMsC0hEGWFc5e4+w8hLY3A3aB6ASlUFjrBGBB2UXR9mB9ikDlTyI
ccctIaDW+KFbMELR+LqSVJyrD8PGnp3oEKAwIr/dPaRpIMfe9xC0tOZNS/AKBfkmzSRPHJH7QXaA
DUusnh1biVxabnWrMEtvdFWfJv5Ftk53CU1TRM+zdiYuPCgK84pBMYXsnkF8qyMLLNLsxFsEj/S3
Y6IdAdLfyFMeHgNOXpl/9ln5nEozxROUp47RyVBdhyk6uDZTIVoCq4O3HnmraKpkMxyseIgi1yG+
YQ0L7EfFCwZD9MIETGTuIc/FrryIrOvis0teaMul4DAcIJqMTlzFovQRqh1iDOf1mzTcT3wDf9Ie
qZ8zdFSsFmC71tyygBsij1NvYtGaqGdy3QiZdVHCI/TVCHgUJjmwngsuoIgRCBLIMHgevP59UY3l
+l0drfy/R8sQ7NhxqY9Gm46K8PL07LJm4kUPQ/97PDAYwGt0xzqE00q+2NfLO762VEiPGtY6c/OA
g9WsXCEHTvWm3N6BHiLlNZLRRc0UYIfX8XGHxcjeWHWYHPSDx0EQfqV5yWg9zZrFOds+NfxGy06C
tB4+Zmvbzyed/x7RwjYzVAmOKALafH87fd13luC454u92aZ7QQ6kUUttPpYaHn4yXrFEr5C+LRIc
XScPXP5XQ+6uhrLNMJttnyI4uG4/rZMknLAf2w/xF0cysxVcfoOnhQzW8UwtGYJdNK6UnxmGXZw4
ViHBkFwSnOG20QUet7N6Hjk/A4AO7p0hCjWdmGK6/X83wnjFRs01PuOr4hAyuELxL+kXtKRn1tGk
prW9Ex9aLlv7IgABcJxtugFYQUnWrQBTV+KKJhy7VDAuIg7XLAOSeYkLOsrXrbIwnTxQeQnqleuB
vPXnP1fdnznFMmD8s46UWcrXShnOmLZAzKv2CMsfdDfK7SdQIif2ct0AtSZ4m+NU2yLKOk7BeSLy
izMEFGhduj/zN/FFPPGQAgD7POsazwRvim9M6vtMqXPr5qLHvwFlLtdQOyK9nC2ah4MPeS4lbk3O
IPzGxnvwtqFhfwVnqoE1IZqHOTrOJeNdWYbWd+bdCV7c8hL9m2Nq9K8igq2QMDFXMfwPTmkput6l
ojn7D5VFfSxIZymx+fFXzyoqCgtsJLgJ7VfP8e0A5CaRPhNwnCs1hpS5Ivt717cu6I/9ga9XQalu
ACsf7A14OZ8P8hF4iAhccw/f+LL5uvAzSvpQiZDwAQgACwxoOyZBelt+aMNylTdqoQLY+O5FGk9/
IrgkW52gElixWGWLiiQqH+fsdcMkV8sacdX+K60BDhYCYFXcsuy78f6sdknSt1ku+czmn2v6wQuQ
FmufSYFBhRUaz+/8MxUXXHiXWfnGyVp6/thTg56821RKSlysHyt7vunC3VlR1TZUOa/GT2k7fKm6
k9Iyz/nHm4CKCcjVJhoW9aNPuD1j2bWHX2TS9N3XJrV80m+A5CoJQ6h3y1t82oIYezx634JPGe3t
XqDeF3trcrcqIlBBuAyf5H/1WI9vfQxw0UXStHlP2zMcWdQKvT2JdaSAC9RchjJMvmE8clhpsuUT
atReYo7DM8m0/E226eWXr25orDXHtonYw+eN9AzVUQMqE1P+LYhvJY4k/3jxN9qC2uRmFMbNey1+
1Niv/xrUadmNrp3vZMKep5RYPys4nTtUaeDaptSCvTcsTFfKNP53CFJTWLi9WA3f++8UvabjFuvb
G0pwidFFuV1hXcienQFnwjfhSkZ4veovTEwdih3XPoLAlQ00JT13/Q/Ez7APiUL7jmjZNHZK1Io5
UNSQBORWobuPVf4L3mZTL6w8vhgF5kdhSxoG+TfDYbaXv8aseVn/zzSN6LuQJFHR1UksUHCHu5Hz
Zi7tPLHPLt4ZFUNhMyeYOXrzGqqNKkFmsc/2D3ujGelCAHeOj3m+Ecprvvy9vMitTWvlX0H3Kuh8
hX6f4lCdgymD8mN7MBbe8cTVlmPld17CVCVxGFGS5Wr2lxC5WxR7L+o3VBtP21KZ6wGRnaiYzDJc
LHIo04MoGj2I+bhCG0lS0qgsyWHo9XWd0HcQo2ck0Vc2TmGAZX66qUmshVpGe7iXLJi2mTbPMiSs
rBLa8M4dMFayiqbkI7Qc5LsKdljUfUR61RDeQ5zQq62LS6m7p+v2cAZ6Q6Q9/FsWHxGzgGeVxX4x
uSdWczGrtY7OfZq7EVxHQ3rs33C4HVOdRJ3IK9vrakHafeqcEfbArc07Y8Xf8CBKvbZ0/mHrajFA
bLh7tCSOgOTZT1sfYLorGr90J1PrtV/3GWtwZ0MLOHMwzG5uKSW/g5uYMhjhWya6j1jVqC7b07+9
ORFPGYL15ovE01ejzcwzNqQo13J9yNj1SS7skB0AKRElrp2EhzQuneLM/72ayLnHblmCOcdp7FQ+
Mgbh2iVGL9LkKBVwZ9mK2MkV0/j8gyAcYMVNboJlbk+10sCjp9w54s/oHh6pMRq51v62jBIIiZyh
4xJAYY1xjAoJZeUz19HWG52dekGx2NR8ox8NVo6ZULH0J+e04Mfn+IFQImZOdldOMsEFrGuUR9Gk
PwraHqk1/HrZ1Sc2I6InmDfTiD4VmeLlwUQ/1TKIXPejuQd9a6E/eJ8YtcltjG8pmYDa6NjxZF+M
8/9k3Wn1l8F/5l292/9z6e3a28dB6cjCE0+bRnGYvxdqc254sJhuD5aAtJlZW+4RAJEnipWkhwl5
keyQzvWUHXgY042U0Hl6rGbvYeFED6ENcXiRT3EInmJ8dhZmWilSuXJFk6PtSry3uuUktonZwmV3
fykTLQXRBYKJtj39gumV3vALvRC0QfnjDA8IWCr0hcYIUJlq8zPo+wW5WMwoxW5G+LVbckaDQwea
N2qOSIIHG0pN0M6iwk2YRjqMn1xIYMPpe9Z1hK5AGR9o9BMVkSczoUFP6M4lJjUsLGT4g/SH0HDn
0kFOhJVSbg+IifsDWVHkKzte2UFvvD8kXgcjTwNn4+uvQHJm7hUkG8siuRxCNrQNHY2F9lWaJuoV
OOyRXjv60+ahYs4FnKRmT4c8+6D8rNMbjv1W6V6GYKXs/9ENWvc7V2e1bGMmXdUH/aDizgT/2QDe
bOnsqwRc0YKG235fw97g+7BSpExQKrUxJHD89nA+kptuBeB8XOBbGfGBEGDjuBz67OylChs0VrUX
NteXi1IUX9yXlaABoK2Gb7CMe2RlGPsWhwN55aTBgXpC8kieeMs+KGxpbVH5MYy3xQ0ICC+OA/so
cV/hxtxc7pKlj1SbJlvviHuMyr7Mr+zxb94qRagHqvGjp87YNX8VafqHB/Ka4xJmM0ktskRG5Ph+
XciUdFj2U/hk0PWXYEWeI7LcRHd2u/+lbR7GiFVTzhBAZ+jzJVIiP7lTrBkxBHVUQ8TkgCKAM5YP
dLULS/FE3c1pGxO4TguMioSXF/QJjOpPbA5q5WBH1gNACjp7Ond9ISI9iap6SFBL0zxy2XSaGG+z
eanLvGadvjNlhxjzdPjLhiUsJh076gPE/h93UxNXq53h0THbD1BYncSD8xoPQ8y62pFmm2+wh54V
rXEJgkKTgGeW9dIeBXW4xF/aUsw3puXBHOKcbXtBk9En62xM9PKKxR8FTnfid4MOQuVTMCfemoHu
w2wT1p1K0Vn7OAsHfHqDqefR4JouEyvjd1u8uXKiwIKJ+sK02GWX0BgBfYdv0PN7syzwn1Ttt3AJ
Rtb6btRpb22eDN7ZNxlutbQUZP8IZ0U1ZG2bnfbYrXCykPf1SBg4401ZV+FMNXQeE9tBTU3G9vLY
iA5y9uKlwd90BcqWB5CpA4+Mw4Mz6ZAtIOqWz7vTWpgncQJT9uwVUbVHCQyfkieA5Mgxb6L0Y8xR
Y0RG7VQIxhX15fp28GCxVBEteL92h3Lgnt5Rhq6bVuYrNPfJAezSs9npw0EGFFgM3ujWeDJmj169
HFaGpQeQM/QlPRkVYSbGaseaeXsSuSYgTPGMQLE5jtX4jGGk3OqfFHbSyyhE04v26s1b+hqWiQzv
GPUlotujSvJwTHTPstUG9d8jGkNYnWOxRFr5lvdSPrAMq3mVMTFgTTUpE06Z3GN005WcQpfSFgYf
98Ink3APLg2vlm4jez+pQ/2wF/mCFxNdlMfypPy0TqYztkD4zdS5UeK58BSGbDVIP0oCUetLovAh
w/cLKy9EFHu6bCOhyjkXl0jCJ57TaDPs2bL3C7pQUbGM/FJhKp/J8Qsb9eIJmHmjCfE1WjaGgLq2
k3HtvW6HfG0KeYRpLLvUXKSPn0PjCSi2wRM3rZRrAwZXAP4sdzWyFH6h2ZDtjreKE++t4HJDdl2j
t4y+vV1274AGzOY+IUAmV6wLMlTd8k0SpUa/5+lfYMs+0aTUjbH/DbNxtRoNm2eHz0o9x9eykfiF
fImmxMNdU9SKcEEvkDrcyy96Ngkwv6s27EXO76BfcB2TyLQMv5BqmnFBw9ToUUqlBiCJrr5uQfo7
MW9fcRJ4N+OP6OQH3Qc+PWyhyFLY6dBnE6ehyMa2ZBS4eeZxGeEhErbHyOjzwA3GCuFzB96t+QVm
szK5EDEblC376eS0WGm2uBXwssZI1UaU66DCB1xlGtxmh1QGf28E3jaiECwrgUT0UvR0wDnNty6e
kmTZddFBrQdGNkBnDlZ4tS0WipY6tknpXugLqW+teHUkOlwS0rWLFN0ireqahiO743KfV9dzIkL0
y/fQ43bFjMgPmZt3d4oYZv84DxIG665/x8BMpuLyF5OJsAaGyvQnsOXutg8ggXm998Q18Z1SvGu7
zkYbD53IxqjqpW3fyaI2702gB/SYWkQjU+F6UIyam5emmlcgkhChHasbJcGPY+/6tt1hVCP4Blco
arn9ty+xjeZooAtoa4D9veu7mBVBjCB3Uc3WMn5eFfex/V4JX6d/P725pNhej4RIs0JmS0H0E/cf
niXmZKaLhPJutqcz6sfKSKucVoSpE2/5BllRMJ4d2gmZwPePDAAtBwvi+j2O0zUWq6mG0Bd0BpXV
eL/q6RiuBdVo9rLhSSX1jvqmPCUqvrWs/I6DZw1dNYmmtr4hFe1H6alN24S/uEUx2eaptx/w7Y9T
C4qg4KgmHbZ2hHQCxQEvQrxd628I8zBnmiuEW5PnRMQOl+FyttqrABQhQmVj760mIHdFETGF4yHE
MPhrbuDLOSLQR9eJgcGE5Ym2UfQiFsZWOhR5JbZp/2NcOT6287SiO9ilo2lUlxgNExxqggdy8vOc
xMtHl16B1GQpxuu7NGrgJ7pulcNMLayBUNHPttnpKuCziY9nmeEKuiV7x607GGzH9kTanFuUzhO7
n5LPZaB1fb568BCh1MF45M3JzmM/kzxn+ERby3vpf5WSqNfjFpqUsypINWxJRfjJc11z0soKuQI+
08Jec4L8tY93qD547RthvNEuvI9y8o6x35sPdAazIwfGz8k88H4oD7yxC6On2oJyuuLarW7yFRNH
r/ufDS87IWYiLirJynSLopx1kpOC0skF9cfBv6uK9q//XQC+mUuCEjrcF6WpvR3LG/unDu6rupLW
qkAHNyRKl2LQJuvPtFFKr9bkRkwRWEUP+U0OItqKZBp+AsdVJkMioDpZMR/IXxwQXi0uomAW6fok
8ktBzXvodPU3roAJo8F8MSE4I72Ucj43Eq6Z+Xv82Dm/LyafMJFUOT9zL4KENZ1DglL9Sz3AJCag
f0RLyq7ZKC3QNWTMEfY9btqmaE9/40l6Par4vRzGoJjdVXAPRMTVIDD4yeoAgRFxTkwnceKO2kqX
+V1O6/vXhfIP8rtNTZADzBDj5DTi0BJtar+374eMGckRNKl7PrdsaUZ/H9DvV0Jaq26nDHd639Xo
/rREDszFzSj08iS49o+CRUOK0KSeZUlfzfxPyyQ5Q4u9EjEPSmbdLochUUz+OFSPoA3esFmM5Pfk
6fp17oQWoQQTNCh+apx/d3lvUBL3BZJXnuqWSmy5KgevcjCoZwVlk6FH7ARKNsOlAvwIahZNTu+m
AhDuo/LqYVxhg7eNCwk4DZlA/opw1xm40i26B+Qvr6t+etojmT7Tnr5DtKCRFeGBfsBKlh25qXKJ
eYbNr/yj0YxBn9cO4Z8jhcBXoD7rZhHtP5T3eHMT0Hz4rdP0jni6iq0FVg8WQ+dt+D/nTniclBKM
CJHy9SzfeDEwY5NgWRTmadp+nUELxhXvy7Kk+VgZxpW7JzS2eTLgxDa4o7CGnFGA8sa9jU8RpyFz
0YTcjmkvgbwxa23L/KK3IQX5antoBVpcc+d4g/0XdYdlM2rZq8GRo/pZ7NtSjjSzGYtmzVzx9WaS
t6nOERQyT25Cdykjm+5CJSlUpMYT8db4Qk1u8MLcTuOlGvqN4P+O+RVS4BLt8guqZyRwKCWTWc4p
P12+7U7wCxNkJ41IZlc5YISK7E1oKZBjCi31GOdx2PazIayrVzQFhSdhS59Y2kTYpz+yZefk4wqD
vxO62W5BaDzDy4REJEjY/uNYPnAimlePZSfm3r80npC77AnuxOLLEcoWArtx27Rnqty0yFf4/XVf
KfjPslGypVDas8FlNk7l2Jp3X0U2jKGb7ey2w2JLErj5OY+wR9BAc+xiYbJSSE2iR4/d9iZgK9XZ
O03+aRlUwzgDiVbQBjrq/WIHMBmN7P5aO4+bkOjukjmsC1fVd7W9dNR0SrF2xBX/hoTVY/ZXskRK
jYWs9dXXz+UrRSXcVoSxF+fAGBo++x38RhjA2qe4z8MMWE6ppg3D8QYGgw4XRQQ2Is+NdmhtgnWz
npdOJ2/e7NYpEV7TaVE/UDQmcnaeyBYvukx/tJlIlfq+Cg3Q68rjLkpIp83kHvO2YkDt31jmEs5m
eWAQSymqMKnPmx46H3bOT3jikzoeRzb/hKSPxZ8cv3OnLjoj8aXfbUP3voPrXIQwBCmKVOcBDIEs
Nb/i6ps6ZyZ8+NESrTYnd6059aNLjopVxHK5zR6lka/xF1x6Kq5DtBWz5k2z88EaPKA7Qfb5LVOW
5NOs+DB1tlF4u90xP8xqM5DXnxExpn/SDCL0l3XT4jfhI9Qa3BHKauCByOXqnLgVwHyQOqQh1Tvu
lHVTiE2ZWgA4GHR3ZkZ602JtchLpAgDBR0EIspScjNIKMqDqKtKdCHUR40XfqO5D0/UWhCjnR8qx
h+2ebVvW1uXOkZDZuCtolMbrSw9hPKD72t6+f7WyyTmdAax7CXU+lzzaytJdGATjyOA+f18dUXg4
BxBkh6Il8rsix9FVEP8v5lToWeXC2hu0BWbjTek6FXKqC41MMKPGvO3ypUQ4sBbeKghAk+qiHnfK
U+7F5y36FYh8yLpqZ3h/uoR61pdAjJZmXDvHYxp2BIOYTHvK/4MAKttthHnEO6zDYyAOQ9qp9vEK
NW4MyMy142ar7y/xaO1s1l5bHsUCniz5G5pzu6DE0Wm4DCoKjUKkzVqTUsPq8ven+MrSLOM5NptI
wI18rmBGadNdTGBzM4cpUcmYyqy2h2F+SrzRqyFmCDB58MLbCm2ASPluQnPeiszVn+iHOeuCZRi1
onglYrvUpgPUp/Wsm2Be8y3owl06YJhgD2BYGDZHYQL6kfs6qTc8lontRjRALnk4+7qXQu8txsb0
1u5s+shITLgfUsGccoI8DLn1Nc07ziIDc6GblSP711WGcNb1M7Bp8MzWDfJGRAfmEy+dQVuQ4Z+o
BfmP+cze6teVmAoCik2unjhIF/PRTlExV0yu4Imk5aaEbpceVMpDeHqs3w9mDc+EWU6ZlAq0mrF4
DV8Gpd15Y2V2L3LHaXWO9BZ8li+cFajE/qT4dTVIC1cvCsaJK8+ktj7qvAZaD5ACatqveCeIVoS0
0gHu4xX94V/HOT3aVqHyAjZC0Pyvwgnxl2L01qzxPKgZRGbXMekafiFzhXfwxPDmmsMgQACQP10U
CtPA6HwqeCPn9LE6qk5fAFJ7B+LCrXPx0g4f35n+CLeOf7JafZC2jSW5SJKFnZJUj/wmKP3XoyP1
Ocro4fgs/tlqrKHm/V5Zdn1s1tdfu99JXTstLhC7KgRhC9tbyLG381UUdVLsul2C0W7z4lXI1iCV
9GlCy0UCG/jGH/3XOu5uDu1MMoFOn+kJNC8GTvFTcQEJ3jWoeANoAeAKZQVl2nFS37VMHN8K/L4V
GVhtNGkSsAI/XChJJPS4BXPC4zFn9bw88PIglxCCu8R4LcYxVZcC4CvOlGeVJeyf2cCjFD/eBMol
c7Pp2zucJZShw+k16XAaLhmnOwYh8yzEuvhm+DZWP//ja+JYuzbIxgT2SB+3q0cvrz9wXEfhiPJx
7Q6bfns7BSlGtD70FL+VdafgJvz5p5lo0joAb04FG5owtvEYGGA0p7QpPa1ORN7zFC7YRpwCgRkE
vobqyoExAO4XcjJ3xUb2ddtVtL9So46tkN4yuwvneC9lIy7TLijVEOuYrJ0A19AFoI9I7HlWQI4e
prNB7RLpfYv0GYcXo75dORHIxA+rNoFAwu52mJFUCmKaGczg6E+DBdcUM6ulChSWzUsgfsWS3YHt
wm785BbfYbl+mhVHEdDGQrFddv1xBLgnAq/UdF0WIOB6XL3cTJbYMWHuj0xCWWBMZcUE15zEqjj6
HmesxfF0WqIgTkt0hFqQq9L3aHfVM3CYwcFU36SSE4SYlX8OiOSRCl5JqoriH7z3sbYyKLKz+w4T
gi+Px9sULx36VvhgeK+Xk59XZge8YlxDKow5zALfvacrR2wudv8ic36yS5NL3UEjMjWreSJIU8eW
qDubFL32s1iVbyI8hT3EwQeKnTEJnz0g9D962/BMydH6KubgijHomwjf0MyECDeKEGUgAydIzcLV
N4EeQBIOw9nbz7IqLdwKrQsy9MaxLLpSVdI5ZDRpOHbnJd11eSBDL3cDkyZmWPsWBIbad/lsFggA
GPb5QPA0YUpk+DGi5lK1WmtG7a1AwmrAk70q1jCgUCbUE74f6hEgRk/UytBJEGKMTlqWm+ykqEJn
85XX/bXVsk+RAuF21aFUoUcWSqi3ZTXOjjbbCJHbvECXmVSifPocf9ObV5YZKNeEKzntartBm8fP
qe8U0Ll3X2QiGx+ufdli8BOeHaf9dlw70vlfrVLrYZqztqKa1M7z9ZnxtXFiNaSegj/5FaXzVcfz
yBqWwEVGyNPWnYM/uDJOdlwUPssANnDq+L6lgH7rMxRadTLEYra0+Sgj0Ijbzzqg7VV4O2oonmj1
gbN/QTjfmSekAUjCbIf7SykNI5CURt+R1oheMGWuxhXYiJ2TRLkaub24sH1ZVCNU8i/JBYbjsQij
+sCsv4GeBumqCencsFUuWY2lx3E13AhAMFZYQIFcRenrNfJpkA+qV2lC5IuOZnjWhhRQg9WBnhBj
u9pipZ5EPr1gu+HoeNuSkRyygOpdT8ln/kkF8U5pLZAo0p0GD/SEsJLqXSfyDQGw0gMYxePjAzFd
EYp4zB1xqXzbumtpbiywh0i+feqI/gXwmJzoVjkDWDvXJCSM2uhxW0MuWNLzhJ4XtGbYGruNQBZU
PvcaevJrRylHDSGVuQyz1CyjaW6M8ccGzudYK7mk7zTeItTv7YLXNqJyHxxQYBIzWy7cLFTQR9Qr
lKp6IyshUpTVwxt6JTCwBgk1tFr7OS0TqNwjgJzy5XWmiq+MgUthVoSfJEQLCoA4skdduiXm3Fa7
SIqhAXf+QNSoQB5HrJbxUPHfGnNmzXP+VS9xOjXd+tmBWzYw1uL/KuWBWmIuZG4dn2upjVBgy5n6
+6JCvjNl5rGIdFMgCLCLwruS67aIrutPmGdPNfxLN9hU/7tYbvmyPQpIpSljuRWArIOBZpn1vcVu
jHh/7KSzvees5EiVplR7T1asqgDclK/TvtNaVuy2R3q7kZHFvPyp2KNjV2jJFF0B+z9fJRAGjylL
+I2lqDYhHk6sLl+m4SV1qiBp+Skh5T8g9Y8eUrtF6tfbHM/mEVeVn4464q4ca9VS0vbjLij6cYdw
VuYdEvmBunnPXPiHd3EVMKnpU4HwvUWlr1+UErzEnMnQa4VBl/CYBLY7FYyPF1Fnm0UQ7RI26VP3
jmSqD5t2wZvMVct7edDUyXhbeC+V7UdAcMALP7x/v/8TPWiDhrFz8B/T6fx7DNx9gydbW5owXtpW
JE1cIwIwAKf1T17MBbBy8SNRsOcGUw316RM7mFcqHi92L3LwGrdfvCHMAHsijRTO1P8870RpDBJD
m6SLLXzSBdDJp/oi4ryTQKM/2ZMFzFw1LULe5XAHASQmsvotwbIGdVln7IhkgH4lEgNC2BITyOOU
TxSFbWOROavC0NuV5X0UokCnzvERs4LrgRH2qak5OkpPKIarj+R7WvpL6Nok5uMS/eqdOWS0qEPg
ldSgZIoNMOKZ+DK8CzEEBLbL+J/Buk9u3hqhaUlPHAgabjCjnABW2aC+K58hdwyi9yuD/7z3swEq
JoBoYwt6hEw3De7GsxXj0r1O4y3ydH5Jkcct8cZTuZPcRaB1HcZsqO69JzWWIuWSC1XEcFYqvBn/
ilXtUuslgUhFpJHLhAUsetHmEkO556Ph60pXqQGhIFgPoQvByO5jyQNchCgKjjitcWeWw3O70nN5
5ImLRSmMee+vCnOdH5IbZnEnb8eu8mtv4Vttwoe0pe5PX4tOCOznzbvgB/ylOohgnYm4FOQfpvtP
4dI9z0aDBmz3GrmlmsH237gzscM1piIkpIFLxWA05HXySp6mGehem8yIEE6Z72RwXtOZQtEE1fRr
+hu3OTQkOzhS5O+tHwnmWVFmWG4vVSqbPGaZGsNopxiG/gPXDsHR9d4PmgkMb/m2QDf9WTJi2YSZ
QwZJtzpnYtuiy7PhQ2QBH4817QrFn0aC68LMnSYNK+Rz4VB2M/iqIVBt/5OOh+ECjaq0UsEio3v1
YLpxAUTc4Lv2eaK0viDPiPrqu3FJfnRcAq6wi9EsvCwiQWSplN7Cnq0drhm+ZM4RrShYaMMCz+3z
heaRK+4F5GsEYTDHReW7cIpCShGHESriKvW0QqdDsfmUrG+xYo0eBNBv3ypoAFCo64Jm4YnhsLA+
Ytcoajf9zVvKBxHEwPyumtrvVxODXT20U1nzQQ9fiL/Hi/mBKHyjmrU7qBSJXjZyo57GSPifRZmR
OxZHT5W5nvA0+2+HX0y5fgZxlhaX1fDhbOUS4/g8K5cjs+9x5T7S2MsS6F5ws89ZY+InbHKyo78d
DkAYcgMT6XgW9ui59dL0QabK5MJD2ZOAsSOch4ZmjRIf5cTU5ZNmdEDAR0w+NX62kVCP5aJWDixQ
8jQC+j7sj1ODD+iraPcmv6+UULeAOlRYgqGa9T6/cjvmy+SnycWWuD6W5oBq5pjBE3N6Qq/nZqwF
48u1O/6OwKIq4r3FZ8OpwV0ELrpcTYm1AM8r79OALDZp5U1mlZLDCzBlrlfQryWPtEmHpEdB/hhZ
uoVS9PAbZ5VaknR6mjkTp+DEmEfCGczlRFP3T4LGulCxYxVOsEBl3rbevOkuUvXfHbjFi38Jc/oP
mxdIy46COgpCWBmDsEpm719PWZly/GA2FCTDK8ZzyFP/NKFPOTkfjaeIoa+vKJ7k8zbxcO5LVKxR
6/K9rPsx1Qec4xCTwVnfrgPl/Qbuvwdj0gUAJMtZY7wjerGkrkthnLlUG71ka1FP19AiJfvIdG4h
xBBHeIzlRL7+o2uleI6G7tvJq+9v6C/ZSl2AVTB2vjDMpVGZYbdkVyDDzV5XNZSzulR35hbdSKjS
zEBeJLt9tqHwABFuxS5EKqNU6fku0Tig4ggeaAzTA3NE/99v5NcS5UFz/stsZTqQc85kYzKzQ4pH
7y2jSaMD0vU/MvfGNMJZt41nxF/yl32iNXM6lGeG5GQzQmNueOeh1CYD7SH08hVbp2c/LgmisllH
se7P1TW627pev31H8MIJklJf/OEjr+KpTC4Ey6dmslWLV5IDRlgTjPRGiERl0Cbe8yZuSUt59lzx
wl5ggzjuheLikJS7zYn9Ezit1hffQmsP4ShDJvhfKNPb8AuV/mlYUC0rF9iDYJv9GAOhC076M0a9
yK7sRExvyiqwxMw84OVj9dWIN5pwxilB8K8+xlOmbQf+1CPOV9W47amHBFK69PFJB1UjjOPZfu/u
bm4UeC4VRUaLmBVm4G3XVNti0Ul5MumDmbUWd74TLFNUFG2XfTPBBOG0Z/gji7/9mvDlcjnNQLPx
Kiz64RV/5kLs/GQw1YU010i5JCibWiFJ11t6wfFjN0QZlqaJ9YU0SDeFFAmA72dX0nOQJBwDTWqC
QtdQ/ZBHtPQtO1OfoyDMTMe7DDgBSzue6mZeJOYyY9kDUrpL8l9eYXQY7IJaXffC2tek5amAuZVL
lyNyxgHsutR7PL+npb1HJqSJqs208S6N+QgW22Uccw0AWfzTjV52uc/Xn8EdN5Cn3p2AsugLLVJK
hFTlJI35jc7r39LiBCiZk9n8quvHPRVqi19wTcD24m17diVWcVnQHCFyDFZUQ1cTcd+7AlEEjARn
znmr72t4aUVtN149Li/HPQYD/8hIL1QgtPO4G6ModqeZanxfu6xGF1WMJ72kkuX9e9BfEIEl4lSV
xypFIAzmbMqE05/aNWFmVEAWB6kbjsVrPnPPWJsgTovBS+K30jiAZ8h7Wu0D9za/zl2B1vetgoaY
mkfyrLhfLBOY8P/GJ/YG7G1M4a6yJ0bCXkDDBpLJwzBLH6QCk4z5V8e7VPUJTyFTks7VsiDPzLJ/
U0qeJOit4DG7TFP1544AeQT0Bf2K8E+OVfXo60dDCsuazkaI17OEP2Cz+AUbwjRfA4CjCy3R1KpK
BeIu0rwUcgpQhKhGdobXkiL37YtIZiyMmIOxyeIHz3F8U0cecwsY2KAM6iUDuf+0OvRjYmtlKezK
SF2trMWwT3Tw9e7a2e6mieE3suEmhguJ0o+bCzdXDwgFxD4uf2m72X2Lc8m6hOdpYYPRU4QfbCV5
Xwsou7CXWdxmXTnfQ3l7+RTRe/Vt97h6li9C91LT0NvswYp6UfjhLUweVRnJuFt2tdmI2bbT610k
IEcK6AZWFqL4TrlTbB7rFe/MjqStOQFLQQy2FNNVcIWkdcbUlVt1vwwydKROPV7SPTFdRsn8jKS0
ST0eE79qmwrFHHpL9vl4SZ9rhdYPuZGkv5blSf2cMTuq87H+5CFG7OlyrUSCPzk3wQsny0/9z997
1tLgYljjHnw5nCf1vm0wEWRgitbpqSz4m6smUoJOEEtOpG6Wi+IzdLvbhnD6Kd3yjH6jdNzrwkb7
Wwv09H+nnVrl3rw3rha4KgUQDVyW2zIyeEEI1mjMeLahesNctfdoAPw55p0lSEFqIDzIL4YS7w4B
6wH3E/7Z1sI+LVLTfySYShyQ9oXJukj86dnsatcfqD5L3f8QXvjCpEKLAKlxHYHscBT2Yw/9uvBM
KHu2Pkk/wTNavDu7Kv+lpunIWrlBFQxjz7+io6axqMxXu4JjHnppCTuBpvBHmnRMspKij7t6cpOW
Lhdwye3nS7LNGZe6v/TawxXDRGuPK0P4gf5lQsff2CBljPNGXM2fDWaD7ga6bm40SsboYd7wEN+z
MdUnEXJgM6LgjMlpgHyLbwf9coLW1hPHEvE6Vs4ndlikMR1ZtsaOR/Ph2jOlBM8tI5KbUoPobqN2
mBsgKrTRd9J2OFnM7LEVkkKoWaPZ/mmwTxcNuqc7/gGxpXCVhm4xlWFZNRFPU9M1S4VftY3vfoLo
w1pV1imvFvlOX0wzFw2gJ78V3EHh0QBbcGerEhphEA3eH98RqHIu4vlYMpV84y3j3DRx6e4Lkg3q
uBO9ANRKTJ1iUQWsyXSHK2UGRJ92LtdpRi1MmfDnytZHGwgweObaquUBEpYhrWbxXhOr/Mk8rRuB
aYiggw1y33YvAK4G8+k/LEoKUbd838ZvYtt06LkDaIQN3cPYm18AiPhuGItbagn+L15vYhWoZPkl
KPufvoEtNwhvMJMLr544DNnUrnU+3Igb8B90puftRpT7mV6a2FWs5gO1wonCNHjxYhbZtPsalY6/
tQfP7Gn6JtuTkhErulUlQvpmpFcvzHBuZxlYCXSR0OxE2OlyldouYClcxgaA807L5ex0xUlgcO90
HAr2U5w2dLU3LWkKSHhCeMESC5G+LWIwDy/jGfMhMuVKMe63GZQKWdnMCkiguTrVCBX7q9c5yIlw
890EpM5oPP83Qb15dcnBeQW/w5uYF3NLZCtBO+cAPjtjAPJYZXkA+gMVa3QCzNnvPu+UhQVZZWen
S2YRJhzt4LL5CIAnm62k2I+FsXULNaCn8BNQOKOSXSrT4zsVmKvaBk07nefS9iWBbeyy72t1m/4m
szQyH0lJQLSWkTwKzpKI1U9tDxR79saYqj+WL82JtyYY5NEiaZj2i8a2IOABF/yV3iL5JErfGgYk
Hq0Rcwgw0Eck7IyhLUcxomyVrMMPYWsWKMURv88hOYYCW/37ZPoVTumBdrf1lrpSybFSUasn3TOv
mTGrCB0b9bEd9wBoqkGB22CN361paAEGsIR+7i6QeEY0PFjMhyAkWeFQEaxXCWlifB7ILn/ZHHL7
91KpHWmgSj5SfdfDO/FG6cHJyXUa0NEpcrhhZgSBBESKIeJUiQiOafvoulrqsSOY0LKFfSJECTSs
I81A+sybB1IAuwKwvPc8po4g9V9S11q3/vSfDHKXTc2Lks+yHr8Mz8YvvXGfj4IbaZVihZtuctxp
Gbn8chOMiJFtGhDVNhUQiMhlonHs3J73MuN2gBna3mpJ8S4BIU7J2qNP5ftQ2yghuVkHXp7OQyTC
uuy93GqiT+0smnbxGdumKCPbG2JqGuw7YUHLKX6/nuuvHY1ElRin95uYimf5VoQHImSc//zyFcVU
gd+VeFBt/KSCC4Vw0ZzvwchZu9gF/2Xh3JCnNmvinvL9xpZhWrFyQsbjdJgpVWU+xRDlcXn+CeLD
ZTBltdomr7Llep8O4b0K4Xy40Mc5YDZuyhmHYtSuVNMx0G4fxd5kQpYJzLQEFvQ7i6H5xYmgTf28
xbu0PvI5GfkGpM4HpgLLSjLatjBW1Km7o+pgHyOEyHVSapcAx+ktLAuM3gvcWMSoZRthhLBig5h+
Lhp5aocrZpISOGRLYegxKvMQKvXfed5zH5lACvN6u5p9RuJQUBbHD7u+I4rejz0WzeYVDO6s9NJS
RG9O+UJRfu8qZgs8taFj0lB+RPcBmQHjrfMZc1xh5AgG8EWvNYInk1z4TdAL9qn9fZiGhfPCNdHV
hYIDEqFVOb70kBhHuLYrLzSUJ8e9F7rroseafAzT77czcEwNRUFddRJ9o83O8ifxLj0pEDpjNDP8
nhTN2zwlJ33OAWCGW6hStFLbdJOScEaibNgc5N+BYaFStLTSe7D5+SLfvjULLekQiUjv2nyjOuyZ
FyPEj+PxgRSvilx9xZYNyTw3oLBVoiEhTbwVemtflSqB7n7NlgrWHHPmEB4jt0Z26SUDjLOkgGXb
c1Cobwgc24AetGmRA28irlpJe4UrE1HSmLXIqdUpuF5gM7STOAeEb1Taw1R4b+NI6ddQ5r3jYsb2
7BK7UFLG6Ulq3Xy47CbyhU0yYvgkGKZJvXpdRWj0UcGJtx0xbKZ67hDCltM9Qq5u6B084++dc0Tb
S04b6fT8XKR1WIZl7h8NVm68Gf0yThh3QEH9kt9xYctJdUPunzgzU8wUh+ZUgwQk2wOiedeYJ8vv
PsjRgvSY5vZbNg70ejnOwav4ozKDaGQXZToa7of2JzvIdgINA9YAKuO4mtLotcX0zZb2xkFxrPV8
G7+Wuo2pODfs56rBa0KiYFjTKryLUroMEDzfBP7R+vmjCbQ0Rn5T4NVbv/gxoQOKtZH58TpfPDfD
AjqgNbRUbRQ+uQtUDRgcq6hNCEJtj7SFXTzPbKiKwQ/5d/y4c+eLjOwHrEeqP9fBkh9QICcF2XLZ
qszUDRAELNI6hakLyn7h9IRzTr2iWEzER/SlgvU9QIcHY/JYDV4JRL0SQjInEjwx1/V5yE3q50D/
de2e55xejXVxV37B+5DANUrKWtGo4drxzIWnl/nXsYZQ2ARzEYWGDaurv6DkFydV77YEC3De9Tg2
QsuV3T/3AUte3vbJ+WYdkYautI92fzmQf649ClAkCzM22008zdwHJUTLt/TJHZ+/85v26uAMMb4N
1RLWBrXEiNH2wyC5/5KOhzdkNTtEOFcsuAuFbSzItjNHJS8U+wd2zoJVJciyPSdH0TaX0VCAUF2n
7SnhoYsvVdmbW8Dl8C+FQ4XmpgGmW81ZOyvSJwfBLDPfZQLL9zLCHK8sfyFOeOPP+8/oo8FTwQUq
M7nzEs0LcMD7gVraEc/ZdzWBTb7B/XrPLDRhWJu5bQY9+9OaTGRn+o+sPQhMFlhBmky9qcEC1LjC
Lft6qGkc3WePcpmDbB3t42eLgZ8RNmpqd3A+ryDRv2396Gi5iXs/r/ZlvVjNN+LV8lkUuQIFhoOY
JSC/H/PNCfpP0/R4Eqh+eARm1iyUty0HNmwkdJfADhRXVGUKThw/PIFNhbF8+FQEO/V+6CelDd8T
6M8FcSaExXVduu30ZtM+7eHp0oqQJlmaXWRyiQLIAkZrD76BpB9e5bhMCgDpHo4qbch6NTXrWVY+
eh4v3xMEBofVCTkxwOrkU4JP2NoOvBJAHoEBOoHToro/bwII3UjQX2FM9nL/apD7ae86EcCN9iid
yDGKK5GKkmTlQtP3mgaQ9JCGNh+rYfRNX6Nm9xufoSXIOXW6y7OoQ937uqjpdQ6UqVudbFKE4IxC
sbc+YPD16q8nrAwezaoy5xYBFWBUd3HUtKiTEGslHmnIbdYgTz9wLxCcBNjS3VXQxAs81sdusw9H
IjpP71dWZyTSjtzbdvZ8LK+h0+9OlvlM2EZ7lWXHd7KMr2aShzbJK2wNbtcXo0GVUbPX0T10zGgb
mfxL4LgMlQJVjm7GgsyZAPiTHlsNwSCvCva/9ZCuHMMDlppFMU+qo50dxyDD0AXPB9zw+ZSBQeJ8
3d7T0IY2YUEoxnNd8G+kq0Xt6rqv0WOGYhaH9VDK4vvjaP0hcq/m83eEBmnf72hauQ5YuP1nW12Y
B+iBgahzGY9u2601MfPHqgcFfa1A3KS073BeRrpl0sgEq3YCWBMwG09YUwIjDTgxwA6Bi5vdLqGB
LOgAFf8FrgSwjtqd1PSwrFUbjnik3p6/DkuqKev4AiV0Sjm51gdpa6/OcnoOOCqHvBh8SAakAAXt
kdUbDF6IT4wuaJ07TXVo6DTtSkIUVx+a8mMHIhOVl5n8eNDY8KL7+vviu7avkCYh/+emRhis7o9G
9v0MpHZIehcqNQTs7+9d2bPbmZqDs0HWWv6k6wpP5vs6l49vwAM8MgzBlZNqf5vURHVn/ABpFki2
hT08R3XNlZ+bQPtMcn1Bea5pCyW/KDrNGqh8Qi5r7DwZ80+a6eNw8Cfex+YwYJTth+C4oilEhzql
hVsMLFf8BuxxW8mD3PZ9FtIO+5nZzGB7NBnkU14rTIt1rXsyXAplapDpmikxZpa3o1gbLYymzrPu
tavHXd5JVTYRqSNw/KWJiMsN0FLGAYHqd2eyLHqj0jNSN28b57AcuJ405GVRQEFP9hGeSCeKuVX8
m4sEKU9xkkQJCjnH//7ef/vGxN1jDJcagS69wPPkmh8phCpnOw6n3V0IVEfZWG0/3mFR+lEzrvSl
+HXTb/5m1Bg8YywHXjwCKyEgIx9jx6QWWMYVI2jTBiYScStOvEXHAhsZAwxr/5pXvAPmQZuqVH3t
vKzbf3/t4iQrUwJbB4WHRDLx+O4wbKno+g23V3oU5CfSRaYtqAIcAaMEHzwveigwHQr4solMW/ct
IIUv8pFqJ/J/bSKGhv/M4HUbP6nOYPo0E1c2PUAF9XL5gPhVGyclva3FZWjLTQyfAwx6rIVYo8fX
IqmHmIwqyco6GNJjV0WKN+B7jTuZgpRQE4NKl8sF0eyf/7B/O3lnoW/+nPhzqnKx2MMZWHK6Ms1J
pXS1ZrDJ8tNiWV0aExi/NOTtPXevLPAQXSUVtwpP9iE83L8mr1E526rgSvhqBNEYfaBROCY7LCmG
qZ+hhL/HyDQP4JD1D3Lg4688gSpbIu91pO0sSNShsG9ODVbczbWh3zRPLUVTTFrl2bWjWz11j26J
5sYpV0LTasjjTu3Jwt51wbSJLSre1011WFSnnnCrQbUsIqOBfVgJtp7R968axgbZdvYC5Rt/Xq9O
4YDaV9WVdYbYToKEjjbjTKNoIdkQswqTcKwkxYb8qJ+909jBs9g79AnrhgmdhpAoAr8daF05Rgb8
7xPHKOgmLgLSMTNhDEFK/8jndmH+JXu1nvriC2x7yMEpkce1VAkLekAfKrKwmGnhjKHn5pUKYguB
vwubOdYSi5YlILYrvQH33RMKeBen/LT33kendoKeuNMg97sBMQ0CRRS4hXdg3QfRcH9Wyy+161t2
mepa49zyxF1FEFa4EGTYhv3WIw3sN7sjXESNjglhJT9U37Qa2YIJQxyYZezgkhl4+FeZTLwlOsJM
7o+uc8hKkj9Yxr8F1eigVA+9iCnXdCEn1KYFZ75RnDrrtzdqxpLhlz4Pw+wCCZQ0j+5O3Ly700yj
RmEo/LWprH4J0DV77+izDsjLXschVNcxqCxJ6AHLUamJ2kws8pNfmAi7KAuEAyEQ0qRN7GvUl8hR
3vd1v2lEJjamt7iuya2WPT4O16H7rdGMKTu1rfufcoPZNId8SC+L5U9E/Sn7EgWXR6eN4lks5bhe
RFYRNtrClQG+/fz0a4jFJ8M1BIwvbizo7bQ6AgTbMFxCu7SWgR1PURpsvhtAkhRLGBxHeU6Em1q6
NeIuVAxUOang20rtBeTXBBzTwWmAeOnbH0sEzV9d8Zg/U8G3ZO4oSHXhCv0TFPVtfe6aXaE/MRv8
DafwbGuio2pnSbWnRtjYf+0d6U3/cqzQxfYnvrP/C4VkgYPGAK0+b2NSo+oUCa+pc9fWr4H85pD6
Y9PD0mD+UjmSajjDky7oUsLjm0lydyPb4pRcJaaiVeDq1EU/JbiDn7+Sl+PYHsVoXtW5xj1LY0iR
4A5UltHxo8CtGX+FcKLQYMOkpG5jtACekWrOCQFEIU+dN0gdkr39Nqq+BfQH4v13pEOxBbS4J/61
9W7IdY/FqgAJrE9R+yqbcZ52e9wKrMJf5jt7SOWtsAYYUPXWxTOjzI1vUdPtCoWmkXIUfAFSG/qV
x10+NQAVTVhHw6ZOT0PV7UYgPCkmK4qnNHsONfDaOic0UZ46vOx3o3FBg6SjaWYIvCnl5280ginr
hidV80vVObuCpdZPiky5//rYUSzic0cb1LZzoIREyehnrnOdoCNHjSIcGpmoPrvStUXkQZcU7hvf
yA827Rfc6LkTxQRXVTc2uFAe60OubmFKX3+sr/Lu4XvuOyNR6exC0+cErX7qsCDiYBXghrfwQUDt
5pP4aKSUlWQhNEAuDKrSkZSTZAFalQPJy7dvfHvlmLlQC2N+RGfpD/nXNTRBz6qtalIfKGWInCKD
WTDyWjgbEHk0ET1oI6G0oVYYDRAovJlCplEiZu0028IlS9vu+SQuvYc5lTlSckCHi7rwtQ8vgElq
iBKPh8xHzRZJI1665KJfjAr+lSY6oDACEU0T4XgBTczAxrzq35Ta7G9tLso0bYlz8sFcl4sAhMwv
HkTGs28SB5+pxF+mE61FAjUdJbW3Ug2HZfGalGUnBSBJ+Fb6Ten00wE79eRC5BfoRBTR26xPmkMq
S7bTYcb0ZZWQxvg2oTdjqDQ9MY/Rhs1fd8JMPV/2CloaGn7Hg2KKSXKi87LAmzeiiuDHsTqZv81F
PrHT+CNXwUZZOYXS1I10jSktxylQI2G90v7rl6CfYpWJDyZPEfLtW6AUVK08u9BR7u6EhoJTvfOO
nODboVLDomxmo+MgqxvVmWgxRLE6cC83k5vpP51uMtc0X0XofnCnNH7W4OUeEdupk/Ps/5WtzTAg
pzqt0J37l2pGJ55CslGsglqqofyZ7AfeLC8YDP9p9erfH7bSN7JmPAsIb2FqfJU/Kc2csEhC7dKs
7Oim+9I4tCUTX4TLyqu9//XulL5mHhDt9mfXneoGojQNN64MGntoiK7FMHVBnlVmR0XGXkHRnlGk
aMTgwdl5eU+dZkKzLrql5ba7gl8+gmMxukJX3611Ka1uAvRuIeOfx0zYlXPWUKTA+U+skTAGvwjj
/6Tc5mmwt+IftZbNpdicIcjB4TywLDemeVj56ItLUG8kpHd6O8ZiwBcSDWUT2im6X/f4ORva7yo6
gXP9qiJgMwNA/B788b9R/x3LLVTuDQtsWtrGYFLH1aNJBFsk9Vyoqq/t/qiozeXn0h4yarLw15vO
q6jeQrMti65ROYtvnsnMKrZ0XT3sE0BjQxM7KvV4hoTPPTNmCu7yjxROYFnyavYZ19/K30UuRc1U
1UUPWo4K49MxrwHR7JH0GTb6juEAFsKUAqhHDEbSpdZFRll0UpnybsBrqdZBcT77iskviokyiOmR
1LQgyvRvbEgF8k2cRAxLeWf1VRmypc74ZK78btoPS9zINiS9/qMnGnxBhJySr7V3qF1o6RvyjFG7
1YxjHGNJw3ybvDqdI1xgRCzfkPDuoGpgqSTGpoed+XR88H4nY7sr3YVxCH4ieDGk+6hKa4+1scSS
wa15J/b6OZ3p9tyYs0SwNzj83f/sVWCfxpesy9vNRhssctlky4Huwcp0/f3drZxBbaQftC1ZMbhW
/aHwOE8dgQF/avK9dsPhwaP2k7jnstKj/KME+eENB4vQuBDB/0D5FESkAz98UBwYbQ41RLQXSA2+
LpmSAKG7+oLYb0GlANI1ZsYewyVBHOSHnwsMQEFf8isuaok8Zfvionfv8dtA9AR2mQHY2IE+ucPl
hzk7Ho1K5jIVLHwq4YYh708YezPy/DamfovQBhW+1Jho1lxVWE4zN8LT3iZggJdr+vQPUdbxT9BD
yvBF3UngFa3fNJkvUBqsfb27XS5BfoYxT4BhFklsdQ7zwWg8+IuUcbWlGTRBwm8z6xlvy2X4pdoX
tLbZ5kXGJUYArZwKOiwOXg/HHi6bz5+9ezmK/RdnvhDzhwz5gEoso/emr+UoH9jzeUndLk8Cg/qL
6+gems6rOTy0PckBQ2Zy1/w5ec+rXr5uSlCypXaBMdhhxZ0lDmpWHi6YIGP9cHzvuZLNqOtxiSFD
AxLWTNr54L/mbaFw7IGLR4odX1WTrs86TyC/40TNoXThDeRsYGDMjhjb8ij+pA2RlNUjP0L11jfn
E9kCBN2/coeMmWHUC+v2CSJ0Ig0UiEghGjvGQvjZB+GfPAQrfDZwzYrIXzuBpVuQVlG31oWqoG8S
MTqwy+/FaZcgT8ZRdr0bmrHOSRSMdeMvsVQneJXnBcDNTievGYewgyfzJDW+7q5JoJphKiB6PeWF
jRW9XvWGsyuHelHAMy8LQxN9IoLo3z07qRUPsHXaBSNcnSpHsDOozivCF3JmdpzwfjzQGx9r34Ie
KNzwZqIQKik6gDOX2z3EI8/dJuM1uCvimPN+Wm6ArYx1z/qCwsGxjPSVXvgBkh86Ch2Ty1cN8whK
4Tb/JNrfX4du3nXwfrl1l89/9Ss4pKtV8BdDd0EdZMOS/w1CNRdZb3Pjb1NTAaFAkIZzuyXq/HMT
p02DY2vFuNnceRVsepbx0t2RGY76miwGFTtC8qNpqMdpGjuDmOUn68vkuYi3ma7xSq+7FA2aEfWL
D7RlDagO2U52ALPIdrbY3grIiTTWj3XZyDOdNxmpysb1pmWdTvple8Q0nYTtn22rvmJAbDPjAvkD
cuth1nmX2+GuQz/ed7YQuluDHazs8I2Rdy5fOsGzcwjDO+UCNCuBXOe5sGJA3/Kc1A+0I0b/te0l
eVWPF3VhpIr+ZTL7CEIFSBRgIJ4OVKCamwNV9ydlByPe6QiVRZ2n55+I7B0/i3AljbzbvccnGSNa
pQUGFvecyRakcpu3rDhyE9KWALsHFNoDdUWvzBZTJqJeUmSSW8gnP2Jb+LE30FgM16XLgOOdUIma
irg7KHJhNVcsts5MRjQBKeuttGv0F1tc5wkwOthKguDJAuY5MSUL6gsAq5gA4nTt4oE6uIoSeRrr
4eC7EoIbJHnHLqTDcEHH6pmk1BH86pf5W2ghmMHBO/AJt8sdmSHuD7xyltRjuAmFQtnKLZ3/66PR
MnajYs6Dq1kBAeFvQm99NC+/s8GOiaEL3toNi2hZHXSe5+j9cEI+Qp3ROFosvkyV3gUU42Ha0hJ0
Kz+47zvxYwED5ES1+S+RwOl8LgoQaTcoID80fsK69hIgsyXRio376j/0pBPujGDZEx2b7ztyGgkE
lb0n8CKYYc2VHCJfpbK3DXzoHmHuH/AJXod7qh5haIO4o2hqToH+aj2a4eeECjpQnwjhE55QMg+a
u5VCUHb1JbUMi6gSfwKYaZR7Jx20z3LNAXpZ3LPW7HSjxa767OFx8JLHvgQwp3G8Rjdyrq5LdnnO
ZRo/5xQC67IoWIYZP092zNtLwo1hkGmFuiaQR7yIofPWrwTdXKkZQFjehMwco6Qgv+67ehOenfiU
uIgHrclA2U6mwqasjek/KmryjgMg89H2BtJfaRznIBl2LwKBfTD2AoQJ/zhopvJHABbGA2RXFpMu
8g4TwCuWUAAqLFLdfdr+FhQWl89mYozDJcH3S9PBfMmMVVa5Ggz8lURVjKcg3yY2+WuTnV5ZEPRx
qiAWz57P59V/ATUsXfScRJHvvOFf8tC/gpLBKe3CbMx0HfUh9vqexyKahjnOUlNseCxATV6cDbf1
N/hdbaERAz+xgz6Dh5LENEwgUjNIn4Dt/uSsfXbNnliL6hdE0VaGkL76HDfjrdPm1w/Uol1CyFvE
0zjDNrUjrptFGzi7GHSsJZ32+sy2JF7b2w7Po98Q08MQIRsuvSaRx6vYjg+UpKZvj5IAbDL6lieY
FdU94SqqWa6XBYHCDFhn6VLeX8tM9yB/pNCUGgo753py0FrkNiaWTwuttgN0v4x8kSXLIAlxe36+
YN5ohHQBmLr8IBDvOuhL33n4OexPOE3DVlshLZC+Ec2g072gUjhhMhVS5uOLU3DzYST8sSxqFxn8
KyZuK4ZzM5bfSfGlRQXRbV69AyNMAlkJsFj/7l+Q9TTVO3WwEaldE7rTA5oTj0j7TUqtZk0ohjvU
pXF1jx10/a7EoJXC7NMaonRnaYrhoeiu/26jrH94xXKqHWh2pFJtz6GOehqTbhy+S0NiVmI9U/HR
3/QcHFv68FeJie1zutQPA+BQcYr5u3/i6Rd7Pjd9NcMOUEMUwtYBgsOwMLVvD31IG8Q00X/zaPYK
y27CRGvB5MeXKNNWgeEDoPWEa+gVI6uKKMM110VIuPgM/Jj2U8Tbi1I3VraIASJ00IyR414Zrw/B
BMi1MNquwOU0tpxorrhFGP+Sh8Bym/X9DtcHR4Svp7TjvXiABM87OFMs12iI9HFLxXh+7NH63bYP
VJ4PoEYraNc4671+i+Ny+NPoHbLhr5yi1tiW4YV7YhaXdmMKQOcJArkNnEJdKSpQ9gHag97UOv45
DlzBfCYHVpqqaLdhkpP5sQYsflbHiRdSBjkFt9s1Pg==
`protect end_protected
| bsd-2-clause | a14573dcf1dea6ca8ab39a88cb9dbd46 | 0.949019 | 1.826999 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/ram32x2_tech.vhd | 1 | 1,876 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific RAM selector
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity Ram32x2_tech is
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(63 downto 0);
o_data : out std_logic_vector(63 downto 0)
);
end;
architecture rtl of Ram32x2_tech is
component Ram32_inferred
generic (
generic_abits : integer := 10
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
begin
genmem0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
ramx0 : Ram32_inferred generic map
(
generic_abits => 10+log2(generic_kWords)
) port map
(
i_clk,
i_address,
i_wr_ena(0),
i_data(31 downto 0),
o_data(31 downto 0)
);
ramx1 : Ram32_inferred generic map
(
generic_abits => 10+log2(generic_kWords)
) port map
(
i_clk,
i_address,
i_wr_ena(1),
i_data(63 downto 32),
o_data(63 downto 32)
);
end generate;
end;
| apache-2.0 | 16d5dc039f0e618a20f6c1a709706d27 | 0.54371 | 3.56654 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/reset_glb.vhd | 1 | 1,951 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! @brief NoC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[in] inPllLock PLL status.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
entity reset_global is
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
outReset : out std_ulogic
);
end;
architecture arch_reset_global of reset_global is
type reg_type is record
delay_cnt : std_logic_vector(7 downto 0);
end record;
signal r : reg_type;
begin
proc_rst : process (inSysClk, inSysReset, r)
variable wb_delay_cnt : std_logic_vector(7 downto 0);
variable sys_reset : std_logic;
begin
sys_reset := inSysReset;
wb_delay_cnt := r.delay_cnt;
if r.delay_cnt(7) = '0' then
wb_delay_cnt := r.delay_cnt + 1;
end if;
if sys_reset = '1' then
r.delay_cnt <= (others => '0');
elsif rising_edge(inSysClk) then
r.delay_cnt <= wb_delay_cnt;
end if;
end process;
outReset <= not r.delay_cnt(7);
end;
| apache-2.0 | 339c4a936a2fb74789d745fbced397d1 | 0.669913 | 3.633147 | false | false | false | false |
szanni/aeshw | aes-core/inv_cipher.vhd | 1 | 3,263 | library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
use work.math.all;
use work.sbox.all;
entity inv_cipher is
port (
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
din : in state;
rkey_in : in state;
dout : out state
);
function inv_sub_bytes (din : state) return state is
variable tin : s_list;
variable tout : s_list;
begin
tin := to_s_list(din);
for i in 0 to 15 loop
tout(i) := inv_sbox(tin(i));
end loop;
return to_state(tout);
end inv_sub_bytes;
function inv_shift_rows (din : state) return state is
variable tin : matrix;
variable tout : matrix;
begin
tin := to_matrix(din);
tout(0, 0) := tin(0, 0);
tout(0, 1) := tin(0, 1);
tout(0, 2) := tin(0, 2);
tout(0, 3) := tin(0, 3);
tout(1, 0) := tin(1, 3);
tout(1, 1) := tin(1, 0);
tout(1, 2) := tin(1, 1);
tout(1, 3) := tin(1, 2);
tout(2, 0) := tin(2, 2);
tout(2, 1) := tin(2, 3);
tout(2, 2) := tin(2, 0);
tout(2, 3) := tin(2, 1);
tout(3, 0) := tin(3, 1);
tout(3, 1) := tin(3, 2);
tout(3, 2) := tin(3, 3);
tout(3, 3) := tin(3, 0);
return to_state(tout);
end inv_shift_rows;
function inv_mix_columns (din : state) return state is
variable tin : matrix;
variable tout : matrix;
begin
tin := to_matrix(din);
for col in 0 to 3 loop
tout(0, col) := mule(tin(0, col)) xor mulb(tin(1, col)) xor muld(tin(2, col)) xor mul9(tin(3, col));
tout(1, col) := mul9(tin(0, col)) xor mule(tin(1, col)) xor mulb(tin(2, col)) xor muld(tin(3, col));
tout(2, col) := muld(tin(0, col)) xor mul9(tin(1, col)) xor mule(tin(2, col)) xor mulb(tin(3, col));
tout(3, col) := mulb(tin(0, col)) xor muld(tin(1, col)) xor mul9(tin(2, col)) xor mule(tin(3, col));
end loop;
return to_state(tout);
end inv_mix_columns;
function add_round_key (din : state; key : state) return state is
variable tout : state;
begin
tout := din xor key;
return tout;
end add_round_key;
end inv_cipher;
architecture behavioral of inv_cipher is
signal reg_D, reg_Q : state;
signal inv_shift_rows_out, inv_sub_bytes_out, add_round_key_in, add_round_key_out, inv_mix_columns_out : state;
signal data_in_ctrl, leave_mix_columns_ctrl : std_logic;
begin
inv_shift_rows_out <= inv_shift_rows(reg_Q);
inv_sub_bytes_out <= inv_sub_bytes(inv_shift_rows_out);
data_in_ctrl <= y(1);
data_in_mux : process(data_in_ctrl, din, inv_sub_bytes_out)
begin
case data_in_ctrl is
when '0' => add_round_key_in <= din;
when others => add_round_key_in <= inv_sub_bytes_out;
end case;
end process data_in_mux;
add_round_key_out <= add_round_key_in xor rkey_in; --add_round_key(add_round_key_in, rkey_in);
inv_mix_columns_out <= inv_mix_columns(add_round_key_out);
leave_mix_columns_ctrl <= y(0);
leave_mix_columns_mux : process(leave_mix_columns_ctrl, add_round_key_out, inv_mix_columns_out)
begin
case leave_mix_columns_ctrl is
when '0' => reg_D <= add_round_key_out;
when others => reg_D <= inv_mix_columns_out;
end case;
end process leave_mix_columns_mux;
reg : entity work.state_reg port map(clk => clk,
reset => reset,
D => reg_D,
Q => reg_Q
);
dout <= reg_Q;
end behavioral;
| bsd-2-clause | 85a826dcf8b49726ac8556967041f9d8 | 0.605578 | 2.496557 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/ml605/top_ml605.vhd | 1 | 10,864 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity top_ml605 is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
end top_ml605;
architecture arch_top_ml605 of top_ml605 is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GPTimers
o_pwm => open,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => '0',
o_flash_so => open,
o_flash_sck => open,
o_flash_csn => open,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => X"0000",
o_otp_d => open,
o_otp_a => open,
o_otp_we => open,
o_otp_re => open,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => '0',
i_gps_I => "00",
i_gps_Q => "00",
i_glo_I => "00",
i_glo_Q => "00",
o_pps => open,
i_gps_ld => '0',
i_glo_ld => '0',
o_max_sclk => open,
o_max_sdata => open,
o_max_ncs => open,
i_antext_stat => '0',
i_antext_detect => '0',
o_antext_ena => open,
o_antint_contr => open
);
end arch_top_ml605;
| apache-2.0 | c48e9b7dc21cfa3df6f6e9556187600f | 0.609076 | 2.810867 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/PROFI_9P6_50MHZ_REC_BYTE/CTRL_9P6_50MHZ.vhd | 2 | 38,993 | -- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 19.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Vektor
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
-- ST_CTRL_05, -- entfernt weil nicht gebraucht
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
type TYPE_STATE_BYTE_CHECK is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK
signal n_SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, neuer Wert
signal SV_BYTE_CHECK_M : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, Ausgang Master
signal PARITY_OK : std_logic; --Signal, Parität in Ordnung
signal BYTE_CMPLT : std_logic; -- Signal, Byte vollständig
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant CNTT02 : std_logic_vector := x"1E84"; --usw.
constant CNTT03 : std_logic_vector := x"32DC";
constant CNTT04 : std_logic_vector := x"4735";
constant CNTT05 : std_logic_vector := x"5B8B";
constant CNTT06 : std_logic_vector := x"6FE4";
constant CNTT07 : std_logic_vector := x"8441";
constant CNTT08 : std_logic_vector := x"9872";
constant CNTT09 : std_logic_vector := x"ACEE";
constant CNTT10 : std_logic_vector := x"C147";
constant CNTT11 : std_logic_vector := x"D59F";
constant CNTT12 : std_logic_vector := x"EE09";
constant CNTT13 : std_logic_vector := x"FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
SV_BYTE_CHECK_M <= ST_BC_00;
BYTE_COUNT_M <= x"00";
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
SV_BYTE_CHECK_M <= n_SV_BYTE_CHECK;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
SV_BYTE_CHECK_M <= SV_BYTE_CHECK_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
SV_BYTE_CHECK <= ST_BC_00;
BYTE_COUNT <= x"00";
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
SV_BYTE_CHECK <= SV_BYTE_CHECK_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV_BYTE_CHECK, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV_BYTE_CHECK is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --Error, vormals ST_CTRL_05
end if;
-- when ST_CTRL_05 =>
-- VAS00
-- n_COUNT_L <= x"00000"; -- Zaehler nullen
-- n_COUNT_S <= x"0000"; -- Zaehler nullen
-- EN_BIT_0 <= '0';
-- EN_BIT_1 <= '0';
-- EN_BIT_2 <= '0';
-- EN_BIT_3 <= '0';
-- EN_BIT_4 <= '0';
-- EN_BIT_5 <= '0';
-- EN_BIT_6 <= '0';
-- EN_BIT_7 <= '0';
-- EN_BIT_8 <= '0';
-- BIT_VALUE <= '0';
-- BYTE_CMPLT <= '0';
-- n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_12; --Stoppbit erkannt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
end process;
end Behavioral;
| gpl-2.0 | 35b0791f88f2c6a09b994a1daf5539dd | 0.512836 | 2.524309 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/igdsbuf_tech.vhd | 1 | 1,496 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual Gigabits buffer with the differential signals.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity igdsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end;
architecture rtl of igdsbuf_tech is
component igdsbuf_kintex7 is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
component igdsbuf_virtex6 is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
begin
infer : if generic_tech = inferred generate
o_clk <= gclk_p;
end generate;
xv6 : if generic_tech = virtex6 generate
x1 : igdsbuf_virtex6 port map (
gclk_p => gclk_p,
gclk_n => gclk_n,
o_clk => o_clk
);
end generate;
xk7 : if generic_tech = kintex7 generate
x1 : igdsbuf_kintex7 port map (
gclk_p => gclk_p,
gclk_n => gclk_n,
o_clk => o_clk
);
end generate;
end;
| apache-2.0 | 72a59b82a81b9d46ddae5e5ac0082d00 | 0.53008 | 3.74 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/wr_bin_cntr.vhd | 19 | 21,890 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jAc2elpDF3eoKND1/3jp/zR+PqlylbAiYUxqPEeJkonmmMj0p4wWQxczZkP8HQmv7tuBnI5hb1Re
XvZ7MbtjgQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NcCSQniKJvfmu7+yh3FyGy0Ym5XaJUypJ6Y0uQPsa1akcjYi0ta/33mMsV5QsYvu+JmAYVNroROq
Kz/qydAoj148DuSUxGpr/Dh6K6KFEJQ68T8sjkHECM7M9i1ksK/n3u+J02M+jecJiy0HOyxQBNjN
TYNC60RH/oHr8eLrkFk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bUAhd9meaxo49J9KB0t7maJQYPBZ/miilGsGpP50LlxHKsJESMzras37N6FY41fj0BrwI2d8gwNc
EAnUne+xYMqJWaUJpkx5tkU3/Cq7YHGk19i4FrTEgtDQCfuJmvvnxIjd1KLqJ+tz2Gc83+JpCcen
LoaQjHQoa/X/vrkqv+GBi5yvXYw3CmPRVPihw2cyPAHh/aKqVK9U2rN3QsJFh6K1GPjF0J0zEoGU
HwvENWUy5CJqY+RhFtoI4cFMx4zvZ9LvGAYIaSHNcjGEuPxJtjqEiRDoZaxAPs4fPiQgVWKDuDze
FLb5NkzGHVW3Pw1VKV9puYBInovkYfTC4nb12g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
yj/twyTkVkmohkM4L+pOFWHFJL5INTv01+xvkfId4SWEcQdYpyZZSWwRohyHdzU487emKgHzTSTy
GFDvnAvaZMJxmURlvGRprcX/FxMbqrYJ/QXjtyclneLv8hDwZCLiXegIMxugiwW4gYlZjMaOoPQJ
gs8ya5IBC3x9kMPV5rU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
tu3CqLR7y72d6lMu0BtbwhwW0WER0YZdVAODwj27MZbWzMWHxGpAy3KeDW2xQMQiri7N5lQ02ec0
GWpokUjyJkcJKOv6cAVA0bMYymP9zM81k2IaifDaYhtB5Ah8VbDj/ArIWXDmp920Nuuu8ntuPKBS
17ifrJikBEgCPNkkESl85/+YxK58m3UimCI0iHmw3WvHkIj/sAUsakbfIOXt9rbFyqcIak6vi6kx
Gi83B53duhddmOvXqbhgzW3SRCCdyG0CtC/tlZjBXsJNv2kpjQBMBZf4BiACBpRjP60jLswfeEZE
bWRI3cRILGIwfm5V+sLTGxa0jiUVbd3TzGM7gg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14464)
`protect data_block
FdStpe6/X30kROMRaI3imz5vsf1fSGJ7B/mOY1jS/nmGaA3TTJm23Ny+64inV+SRm9cem6L7Oa7i
iWUTXwggHUdecTXDuoGiuzlb3RQMdZgoLutZOaec97VsXyKkVD1+8z3kgzfno2XW1Ldc6hB+ZxYm
0KMW9judLZGzCMNMQ7Pk1kVkjZpuSEor7yKJc81xrJpsN3FGlAS7VBu1YUw/AdFSrbr6AuwISFV9
4OmfDJHn8sJrjgzU5OLqSeke4mWR9VxkUlvE3mV6yCRnGC4RUj42fTqjoCD1CYuNGVYPPmMSdCPd
rDLY5Qt8PCxuuLQSFS22U4v4jAoc2IwGoswFfClL0IyNuNeACyxRBDCACypVibFdN4A9qThtB+Eh
J8sTZ/i30BopnWZTwryDi31ZrbYfZrFqhKV+z+GXAVhOSoWN7PNPJ0TLK/P8MqO2F6MmbARuXVnu
GlDPfKSCr+vIdbW1porJbvdEoN7WqR293NSTzfOsp5lBqBQP5CyMMuHkUNBnfnttLRs+/OmP9tr3
kyfdvvevriy+LVM7Rq4xwwxjvSvqaxvdeX1ekFh1WrdGqFGLQBGyoI0NzJA2Ndwm2Vv2X0xBf4Vh
4rtErqTJ4zV2haVm/Q3WFzqETZ4gTu31DT6+LuqoMLQEDAO6DBOCVr6hNHQRMdO76p2cqiYHX7ic
163wZ1mbdH0SYwR8FXEmz24OUY7E6iMNaqesGdBpC8k1CEBcg6wnzDSy1yFsldwv+FhFkBgc+Ryc
58F9aX9hXpvFXvzVyF+4QJIVKqNEaGQuDDKVAVRwUeC1J2zHg9bNGRFtENUCjYmDwBHQROACW0TB
rH2SIObCdIuJRCB67+e9Cg8idhCJEvy5hByfLWxbA6eGyle2X+QZdSAfIXp6IyYZuPG6+tg7s8IK
qMeu2G+/pTzdVmUNtyMy9SgM4cnHIVwaSfRvSe/jQDj1+07Bqdqig98nlNzfEO7gl1izoW51cEiB
fuje7vkqkoT6mzhpsXfnlTDvkIP0ceJFJQ2qU5h0yFDSmFwxutOXnT9qMXTbm9iSZZbDhbxoPvkr
KaL9zMG0fVBTSrcZUBawaRHSmpXZMLCItkf/Fk309hdaZHg4ET6K40s4afBlF43q7pSod0JCJ36R
f2RVDBWDRbvOYg72YBFK8keRxyzJr50ewVZpvUemJ9AblRG3J3cAdTMrMYFav0ukO+f3YMYZm+4R
pykUt4YGRuIWFXEUbaDCRpP9JU/oB0vGyqnAUWQRXYLhjq83BA5mTt63+xYhVCAZILIutAYVj1hb
YgHA24oL+uDTswjaHMTV7MC7KfiBdxyoGU/RLN3buzgfm2MXU3Ck9T7osnoWvk3BMGPYlDySYPQ+
wQeTSDCqQNmj90ILzBhMHaIl0y83PsrVd6pEcyl3RxZYjtVNbLOAfZuXqfuVNrUOZrXRCz4B9RnS
ZMSz3kaUXpqSvHCXqVIzy6TsKRScuBnzrvtdzAEtd1XMG3oMQ19kNN0weEPTjLnilmX0T8sYDEiX
qBhKnD+7r7Uivhn2QUCM4OypUH+eSao3e4V7dWa9l58iF5zaW+3ZvnGe6SEa4Xe8FnaFWPodFaPC
Drq1ejYN6v8KiXEwjiAXXiI5GQ6A4xm6n1uQlbMZcADvvypdUFJ8LB0EcrrLUhSjVewou8ZYzztf
22ANuEDQHrPUN52xXJ3P7nUJZfs5PhZqdqgLkKlTZQegGbCU58F39IjpOLmb5Fxc7azZ5nEJpLz0
6LsoaKN0uboRcTT1lfEIhMW4PZOpCq2ipnKaff3JqGj0nmMN3+dEpYlGq5TKixCWcDcvzUPCcihg
f/EETKWZ3ckWU84YKpdeghbl2MDCjKw4YsRNivzCzbfcClXaSgi/YXY3IHodddg7Z7eCEbVZ1oc7
0EortIPDxUP34UfSCBAZgoX7LJKp+kBhykbw/hhCFOfHyd/jfAMxZPC1rVZmpRVmPGTIDVE2uH2d
Wpt8g1nviQ+8xwRROtrGbmMgt0rHWqZ1X/feNj6V2ULVxuyDgGHF9yKmiy8z20QbpAQJp2A0tUBO
3xp5gtN09MgKg94xsDyG2vgRD3FQaB6S99loRryFmJy2TdAGhzT3KyTk7kuqaUGj+LRmBauQk8sM
kkkBmEigi5nqzrzt5W1HLlcan695aNxL1idFEOtJ4imxe7HzYkSwr7meAo+Q3VdiKnCIqDMLurQs
lIHNi2CydcbYUGS+nvj8rlDyZ8c8dpcE1tIaTu+5NliuzLcSx8PgiNBgVbRSjfvD0V/8AvNX4t3d
t8aVX5W5V/CBDEFxnQuxi67uOcJUEMZu73s+v5Sha4+mt8FEA+0kcpF2n2Pud3J5YmdqECyIyUFV
hlRfl9bia+e1KS29V6U2oVXFBPeMU53mselWeOBGerX8YwLxWEyD0czN1zsCDiEj2z32xdzXpDF6
gP/lfntFrSYWvxJemZCdd8tqBC4W/IRAcTn8AxE+a9Fiwy6MhG4LGhL9H4ol1xQIIYHI3W//XDUz
QTXAHnHRcIZwxvF+coPiwQOfuroeSq7tkT3Ps7w+/xgRuNcX5Z7YZbFnp/bWRNsKYJd0eZ88ondz
WRpQkdPNBH3AoNzgg0zOvmx7CP4GeCOSjfM3Bhs0JiKKmjzZggoc/euJxVxdOr6gt3mNAqSZRYCO
SvohpuLllmsuWNjaXWFlCyi76P4772wUPbMXSqgrK9v/FCECn57uSvHFGg7Cvjpf8LcyANmaDKAy
+FRDxOsRA+Q7kkZSi8NL4aNlpjRh/zFN/eQQuu+Oow9lfleZ4TzE06KDunms0mGCwbPStn6/6xsd
4FDf2/ZcbxybgbnlChVE+FeIBJJcSJvQcJkHVAF6ugYRxrvMOzX671OiWsQ9YInMhBegmhHGp0en
lHxRw/BH1dla+PeKm8BGUogU8AMNj6HA9apF7cvHuXPMsFGl7vlr7GqVbxSUA3fPjhd+XLkW19Ws
AHTIA9eL0qXML1eedpB/KoFCcDh2VFj3IXvWuVWKnwpZsALeCN6jcfCQcDDq+cCyUR9P5GeTAPBq
0vlKP5Vf5TsNxyI9V6hvR6OfPTsg8yyQ0nmF+7mfv65p2Pi7CVXQ28eIZrmlKqWFvHcQ7XBho+qY
mMceonAnVuVoc9rALOM3u48zIzcPD1HnZjWXbiB9ZUvL6hftVoA0BCmIhhdpR4zyTTTA2q6WTwox
fp7IdkmSTf7ReDAIFndG3zp7jRkCXww921H/NKW95fN4RQgATl2Jm52ttjTLEhV5qtQkEp3+1tCg
6PQTkw1SxHT0pEcKmbYaRmbMCRPunNWYTyqecpNE9lFUxKMZVx7RQojwvbiw+00ymQ9RdnZwE53Z
8u9FIN262IVuBQ66Ls0hQ/Te1Sd7mnTTQU3Imq+HGjLiXUgwtrFbjObIz6xlkuOzl06ZDRao4KPa
ZHjthhcuaXEy/cV19SAB0xwJUrE74qhILCX56aCDM42uM9AsqQE45tQnM0L4TGwl6pnxQxJ8CI7K
AKTcA65qn2ZHddCv5MtpOwOBb5TXSVHLUftLvqSFRFyrNsLZA9mI00QQOwerAqrD1kmsWKFa9LOF
+z0zjld/6jT08ZlXj8imgI68Gr/eWld5EFSR7vCLEMl2d+l9xOdv57WTE+BqKKM7XfICi3K/M9rO
lCCup7aCUqUqXZfO74jk7C3Txa3mf4gQ2Wq0NKbux9XFcJh/ooi3sMDHBFG+EuLur/Uz7CITShBE
aTdOfA9H77QIUpfDGbDw+1FxvhzmJ4cI8m9SjMrQh3GOJ279wsDoxv4zqhpyb7bMWZQf76JLrtSw
1NyUlc1yV9w1Ino1PGSkIgX/vtIepnTflJne1P8CPz7TEg3zI+c0urOZga9huVI9aIfq3hjiyQBn
r3gBmOohW8Sd7lzKsB17amZDjAqQlESD3Q/e8bObzmlTQOYRrwX13yKdUbUeCyET1Z6gVFELNSsA
Zhn/V7eCJeZuPfHFVXe8+gMRLFgulEoxta88OpriNzUtj+5gnJHohkfNZU+WUcLFBOYWHGrfzkxg
dAX8UV+LHX2wZj84C0fM/OFeoJHdjsCaawCzGuJQfEVsZLiVX7dFBwUiAJiRUX0Zxw+gwA25sB1u
pGeoQM7eWen2MGDPoeDz0FjzUgF/9Cz/8N05R21pPzJvVmqa/5SRXIUwFq8tQQCgBJwdnzx5v3+E
NyEjj9UJt+IJc7x1XLy0JnZ9EPt0V52KhzT/2QhOMsRCsZAb8DA2XDFB8m8NR1Z7ZHw+L/R+vIac
ZgtbH3DQcJ9KMzYsxWzdbxh8EMpS+5EXGHY6jKbHTHq2USVWh6Qno5INiit4l6SywOOV2uxSsi+o
G7NbQRapP7Seg62TJiWN1BUXb7V7/AGmGsmIIGKZ5y/b6eRqP0sEvkd7N+t/IMcrf/iTsVLifApI
YS/ZPJgg6h2p7WErVuoR6WK5nGVBOmPDuKI96W4OH75KtnXCa1qvCpIN7dh9r8Yg5zGsVkShwlWR
syu0DOXNCCDkCk53htO3xV0z4dZv5yK/LZydBleIsjGMBLkaZM2AFh0ER3WsM+lJA9egxL8Vu3rp
Ps0VXykiIJJocvPIU2gy5wHkrbTyqVDLyRsDtPK83mDHO4/YCyshVsQB5lBB0lceZgGJpDN5x/l1
HYwA4I4l2zuOjnOdwlXY9LHs3MYHMFyO5Kh4D7CcG7QRCTlIcdCfdk6sjLMmKyJMOMvuVfRz/Krp
3TmNGjrR6RvhIksKKIopByf2oINjC7lN7Z6yipZx97opqIAPqgj/eBSPqKvO6LTiq1wyP9XKRaUO
jcmgnoS7nz6l5vSTWuuedoF3PW2KSfJBKxn6IkE3GFSgV8iFh+yhTUaGdDtlJePclOVe3pbQ8f5S
tsOO2930wWNRwooLCocNPq8HsIDOid5BYyPZ7z0AXM5dIa8f3lvetsHA2L7DzmWXFPWRD4lJleKM
Cfgk+o2a9jRjwys1Q1Q7t7WUfM1EDgGeW2q5lQBaBS31otHTk1Vb6fsyTOuIgrNucO2bLCzmrIXg
YXLCMi7ne3vxZWcxq0Z9TituMvXYIDZPataAxsL4WxlNagtJxqNrxz3QIZ4exeHYGDFu/mNWwXNf
QxUGHI+fouZsCc5SrVRJ4jR8owj3Av49+mrRL+3KPHjoYT2bIZsm5Bs+VYWlxhjXqIkkBmNT+JYL
rPee777BeFYibbD89bQXKibW8+DXcx5seHgWlIX9enuJnyJ+4jlMY0RwvwemTFKCYPGsinETpfL/
t609g22HNCr5LaRcOHLTE+aRzk5TqO967N1KIuekccx+6umesVFXHTAVzFNSufbiFaEduv6t5Mjc
czLrDxGr9es/hkav/sFnKwFr30AKDCa0g+mO6gFr9l30ZswrpR3LyfKSaZWL8Do8g9Fw8/4g4X9/
4B+ykET5tZvpRYq8OgGRUuBn0vHsEHaV1zWFDzeZbg4e2IcxYyejnK3hfF8BmCdsRohecdh+2p57
PJ1L2+lB0DMN51nY2or9WqvbWZIGeZya3xKnSSynGWzBxxuKoTxl24jMOT0LGA3WV/zOJ+COOYNv
hEv54h46ZGmF8V0Sm0ohEqxW9kgpIizy4EkkaGRFr7sFlPWAQzbGXwbKbdI+sEzsCNXMOlbX3eY0
ZELmWa6Qq7/ybIrISvdJElj8t8rYYbOMGGFB3WcF5PXdXH+K6K9PbOTX+v1wzW2MtRSYIbXuimBR
lyFyeSmN4f4LK50ez/CGRQsbRTM0aG6UduKG3he8QTlFH/CRkoiB8+pIHJr6VFSqs0Kl4WNf3nvN
mOSjLrQfncr8F7Eu9R0fABQ7ZjMEihu2EeH1enAYrIgcsQfBkO2UY2EIOJj5KZtzron9sxmfNl52
oxEkNWBzvQ1WKNAfiBBqYUZfIevTAphgNEdhUqhdFnZc0uBSQ6MHAJ4FkymSxpmJP9EdVOD8naM6
mT7qpgKorZlm9UH2U0/O4aar+EXQNzd8BZzSoojkBLS/HFo5QntLoZp+qzw4+PDAWVN+qD6EnxDA
TSEVZy4WzLi9JvoA+2vcExlnE0mZzyHHmvCAsrhmo8mrfb1JrrOoDpOoSzdcUPvjad0ANv7bXai6
LuvyjMrK8HD8uRVeXpBSZVWeYeqcJhqHIjp2rRDGt8BlLFIS7qyKljVXZaU1QLCE3Su/Wn7ha05i
a1qh48w+O2njuTXJO8JeG3cY2sJqETsHJuzj+EtiIFeK7I8Ez9onChn37CvADEyl9X1O9c0HRQp2
JNprJdt5Ld6I2Z9Sx5nwEAHUoJ445xPi14+MyZQe2QeSk3l0tOduf+JwBrRgci+nQ65D5WxUGXtH
jJiStrLv8qhKEMuWlDcgHvLQmalLI1ATjFgN6YvmMIFvkd58XDlZl0V7LUZt6+0E/DISt7hWx5cL
qzkqJIvQc1SDkvuLd33vcCekIxigExlz3t90ddbg6PrgBdk3lo1gJ15Z8W7vctd5LRQ66wD7twbP
X+dOQwel5D688G0P0aK2QbFptpi8PIaaY5olIymlThnrqGyjNewwayChG4BeI1mEAFqBPzizCRnO
ZNh+eYHEk87ZBRXgv1Z7lKeVcNbQH0QbLr/ZIyyQ6/Yww1x3xD1bePHR4rBCgzqnl3jcH3zp5uCW
4ec/jwiUgplWNw1XaatBHpih26StPQK+IivvUI28CDqAdtkE4Qjv6p9C/oLOpev2qgzzoDvxMnnK
xKRIJElMtwm/1dDliIYZNa6RQDLNLH8z+aqCtLzPLlQMn5Yl3X1SOomi2NXdNM44p0/1JVnEIb8V
QawcPCz6idnWsXDUd8N9+rBEyuRKRY2e5ktES3mauaOIs1EJbGso9opd/YSPDgYqSrKWFuOzB+uO
aEjlL09zeTN0DZSQFoqeZCD0TGW0j+Iatf4T6s1ZwAh2SzJh1VS6dEc/fYrMBQqkmtDTuyGAcO8s
H7di4cmUZtWhoSAPZ5RzcN5aQ9IggZYr6RBnZxir3WCURk4CJJemrvbfrKPPu93nyGLobPFsuqaK
r1pVSbWF8rekAc17E1uNqYoMEOgXfr8jACHEj8Ei4pSNWMLArO5wXn/W+IWZPimyBKz4/5tGShiB
L4xsbJnGvGRUb0GyPklwzb64JxfgemioLV5Nn73CmNqJhtUhKSZbJ8V/h7dpm2o5b6RpoCcLmFeJ
BfyAng8nlRYyBkNFOrVJ7JNnVDOQ5kCegGEQHlvkjighowKJSxP+G10CBY09sbLhirERviRe3GHV
/oxuRay4xVHOctEtdDmv+sjxRuGZOBa15naDPrjEC6YhZULLimTRl6T0CyOr8H96w241O6djKfW1
OB+9X/DRS/8a/kxUktIcn+NT0+dBs2D2IzBYn94jbBd3WiezcU1V5gGnSlCTLttRGZcWOqTA2+KV
9Ihy1YNXTq/K1bVcteH6maIgXzKxS64czjZwL9Z0x+Uet6m7r6C/yhYIEAeWbFAwjtZGZ5U6nXZV
WRO5ujqz/7Vt/LiKwilY8Af0AOpbPrPeJslsxycIz3tZtZqQOfArWE1X80YV9ETxfc6hx8X7dko3
uBQr78VGYiobMGxYYQw9DGHPQG/kepwt74as0Qu4b5NfFziujxDVO3FKeHQR0jzAMQJw+iXsuxgP
kO0CJmdkypnnuZhIj0nL1VGi2fPGQDjd1W5YGWRVsLyIZBFFOttTVzThVmbFQXWoqujPBvq70+5y
5cSAb9hkZJhVAP/t883awtj6rNPuS0oCa3JeMFKBSwZEkCzufFC0kQDC8YLUKXWOWtl3mqtl2DbQ
T9kfevlpE9Y2/8fG2mV41vItzbuMRHEj5lvy+QkfuRGPZRdLf6PC+YxNXoBEpb0AfpkGGtbmKNZY
4jwz7Nfz6fU6dOHBpYTxiabff/PGfRQ04BQ1B727gC0Yy0uuhh0K+pnKjDjz0oOOEXRC7hbJHJoU
xyHEwdRF9AWkOipcuvIVSeaK4PviTr/Wy790E6ENf1lcZimcP8Je8YKNVg0SdVpOAfgEDOnNAZcW
MLmk1a7K45+j7xEcfgljzz+siIwcxdF8Pi0IgDvzV1Qr931kSi0LrEYqTlRCm+t9JRgiiW5Amhie
AMtH6Ma9ENh5I0SI3vH00UBEnr/M8W1ltdUd76pNRbMRys9UBVJchTFydu44IXJthO2fxbHMNhAI
rN2mm88VqvT207fEJeFu9OySV+fjWBcI1TpOCtBPk35/9qlLowIoC40xe4LO/9LIA+7EFoqeNYIs
ZaW+Cu6iqk+qiVFllcF4VAGSAOlkGrsYvKrQ1G0lx6/dfFxecFG+TQxNIeXyOVwKq8gfrNda0YJ3
Z+bcIBnGCrgBl3QCMXWpXCjRnsKx+SN46S7DTlra/8XrC88wVcKILbJ/dtZP2fUWkaSTkkDo6FGj
mzh1QDObLowySO3CV9/MgN8u01K/31L3bePWzV8AjqV4xqDUDkRuklQLt1+IVG2dWpnALuUtk/AR
Girdk12WgWy1+F8R7H6EyaZPiujXzL5Fml7AI+LVDrbIwxVhzzjigJW8vJz8MNzcwj5Gta9dDds2
UQCrD+LBeJWbLs93DPFFOiN3UHjZSsO+IrGVhaatldDBfmpW4dI8IfQnCs0UJNLJbVicTmjn5IRg
9jlhNMgMxsoYAHUoA1qj+uY5t31vU105RwMmFvdVyPnkvgykdkh/c2oYK6lsWzja1sebVaXS5Qhg
/W00NWtHqU8VNlcDPHyiXFosojKc/nonoqo5/1fch5rblX2zSedfIBXIRTVX1iQaOLzJnpCJHT0G
QLNhoTyKIoUq2lR/mxB4KME7E6UJNAvl5Vwv3n6wcm7dAN6dRwx+QjGMfVIPDYcJhmAwzczyRqmE
U9PxtTBmTGA299abt6IY0kJKsBhbzX4CWuF9bbhXBaUAZ8DtBTLSmhMerT41XeJMAR/EZ+S15Wlh
xqD9pxXLY9pjxdB4WhaLpIfiUcrr3/k2rVgZSUaPo94loi4TFhQdWGA3eMI904teDGrAya3Mr2ZJ
OBHuss8ignWLvlOkRFbYeydtxfs2EWvy4nl3IAedjsZcb2UvS8bg/TNIcncOxxGMipXf6E56zuLk
GMoFee5vg2NtZriyWEi/osv24CgUfUtpMcPs8CqZTduSlFroiJpRLlqKxvq/yHWlp61U1Yi2Ke3O
RUe4ikGtLnQrB8udUs1R0qejQQU2xceIC9w7Cuy8NXGXXeucO6njnH21KFBUfVlvRhzU9WPWW0gK
fMYr4sZCBVkfqXkezUiPF95mwKxmImaD4eGiI2grKj8McQ+bUBTuYi2yuf301NkLkfuikkZCVleZ
nF8C/db3Wcsj3m+Hp7QdWf60/aejZw8T/kC2MoXcNI+aqr4m95J10hVqswVN8BZFK1E8BUd4NH7L
1XhHndwskob0Zo3SuULZNK6W6oN87bQe+hivTOGefIu72ZpBwPSArbzkiQXpcbCgzC4A/bKTaQWu
8CcdINFcIDixi+CBs3rfrWA+xhjmgUBxGtrUcItmHGaq/2QhrdyjfNWsCgP7mVEOYXCOV3+XQQtw
e7Ej7MoWcEmfTEUaEiTeEy1aVrAKJvKFQnYrW45bG9seDRmswh3R/kjgTIIm9S5E+hIxWRXTmrdx
RIW4o3qyLhcn7uI1oUEB5LYY3XZvQ3NKEbf2MSgWCoUtT3i35tuX1RtsB5zAroFS6p0KYwFsYE4Q
xVPRl/b5YZfCJhY+pG9ZVqes+vCM7TNp2sxD3Lfkb5VInSAb9DNgOJ3dJ2z5LJCFTzjVGVtQcfmk
TKDvdWCX22hlbnS3GA9oQYwL/OYB5yWXRNTLzUi3QBmWCcLycVMi1ySfoSeaFyK4eDJ82QFnWm2n
++jagOG5d8XD3R4FUsrHRxLVJWXVlBhZ1AcYjVBQknGqpwougYljl+MkV0AZTd84LBQO4OM59A2H
SwvvTu9vQFzSXHH+8UCAM4v+N1Me4fItCsVOBT5PJCvLwGqFXcEr7ViMEu0NZJqzJkDBbOTO5K1E
rJgHfLieIZxF4vDWtHxgsug9QnjpaMgcPSoQ0fgsdsP3wxvyTiAfeJrcoOrRLuZo7bKm+qJw5AUa
VpfGJV/PQthB/9rSo88Uj9T54AS990ya9r8VpZzmQRrVr7vcrdkBbY1NtsAISlpRQYt8dA9UGqq1
375UELiXnVCJF0j0250iaQfa82c/7fVeVVPrkt4p2BmpL8mzNATvO6pR89RVuR9kGKZsVPWBjMXL
wmiq/njRYUTcvlQ1O7QbF+uyJ143rRaTDCy0ll/wKXihYhh58p+R7JW2eOJ9aNNRZ91e7g7XdIoo
LlGrhAdTct3HWaDfI2Iho7nb8TjYLR5vGuhvLBcGCYEdVU+lXLFBrUFJjdQT91gVAkvVlSHsmDCr
3B3M5H6dkBQPgvp8bnnpOEmUH4zGODFUtvM84/hLSQ137EW9pKRghsGDDxj9d3y33OUgfmKRV+Nn
62YPv4aFr2HNpLJYX9hVJV2DrALC5Ogoe3KYc5YVB2YY5lI51n0oeW7IEpBaFkcnh61dKsSl3RWu
z/J/Vd3Dq4Qk3uLGbEyKLhLulGeFQ99Jz8lP4tMIKBh/h2E5mpy6vomKZgEY8xF+AihuEu0JNtjA
6E8a5VPCUzAolFpF3mefOLyt8vQ/FJhT+1igyU5av437IntQwgaBi8ci2qT+BzS0dE9QBJI8DiI8
Ud5srE8vbzh8n0e38hZzh36JZMOrSC7byFI2mxDiqkVoy+ZxdEFn2L0h4xb/nvpb7CsRnnOhAWLK
Wqu6dlSMqK1KSjg+IzZtfQAdCzEGbbP+l9YyTC7tZT+rHsdq32KA46e/RlHlMevymaFffne4/VhH
vj1sQSsDf+dE5dX5SILL/9K+hc8FsYNQ5ZWlbIbD8FZEFEVNAU0RYWWpktrBmPpb2Jee2jKWF3v+
XU+azgfZxABmtoCwgruog2Wk/Hkx82vOSMKEsFsKt5FjNxsDunnXWIExrrS/wKQd6XGbmJrkKtJK
xfwb9M007kXstUNgU7L+1Ai+YCdX1GUkP5pZN+zWbVYe7rIG0tSrHA67IBE3RYXZG/djWisRR3xt
miztrqgi2uFwk4wrIKkrzprTx3Gt3HCfqlsdJnZbO6F3fRmkP+1UxT0jNTsRwfAgzIlorOkpA2zc
bo8ZgYCYawQyXCrtDYtDTobfaYrF8Gg7qIfKXLFCDzbX6Kue0jT8YAa9qKR08YPyxxHlGktiHpDh
Mw247n55Eq52E5J3ff6kPADWoRnJOkqKx7lxBPmK3Oex09ZZsiOvslI3ewiEZJN150TmHgmgSgEl
3Qkh6YhjOUIEnAg3euYEtmbAkvkc/zhEG/xJFc1jIhQBey1EryO8oXWu3In/E8vXNOQb1Lx/ZU65
qECmHgA7a7o1/hXTvFVm37uXsto+/LhpyojlSo9B0h15RqZ5f0dK7uNC6SRl40KdWZPzoDh+kacI
zP9vZgAXarP1Z85Tt5YMUfVxysg13ZYSnUxLF9/8UANRFY5y0tKzSeJk8Mztto8KN+cutF7JtGNr
MMdImzfxwZr4dDdDxDFAgv0qg/HYNOFzacAOvjJQGY4XLes6nDiEZ23TjTQFgeW1ym7wNBvP6qDs
3zrNpoiLeElH1OPDHy8kU8u9DcyPPL4VewH4BoNhj/phKGAi+gJJoS2qKhU6gQymQ0966TVW9A9T
BGhXbmbIjdgXTNwOhCvPu4J/uvlQweTF/VZb3n/aHNNN7cKfu9upYc7R8zAoUaiIdNGpfb+y4HFE
GhkJV5oJ2R6HtE3zJ9Sq5hLDpQ3wYAUKmTy667PWCNrtC8wtfYYlZjWY77oavOeAXKbjZfwVf+N1
xxQC+gUog645JCLyGNdfrw0egwbLmzqB/42Q7KegUdEmfai5MXhW4B0SCmEdQDnZF/9QQU5rJ29h
ZsUI7s9rlUSNZ0aM3tZI5QlPvgCjhhf9T6d3gK1czZ0bo2fhnauzh37vzgpRLt64jFf2KidR9O6Q
RNIYWv/v0b/VLDhj5YG5K88Pq+0jdKecPSZwtjXfAOvgV1Oo6h/qIdhJaTAW+q0qOusGUjSFTK8L
nlNS8nTYOj3WIxcfoCXu6S0I9JZ9mdY9AX2eN0FomipkZdVi+oVE52Vu7ERFw+h1xxSxLTr2ITxp
WK5Jjq99dc7srzF+xkBGIVwZmJOckYCl9cAEDS3mVhLA/NUSR2mCIGGhYs5wiuwAscITtCZVGSXO
LrVFSV15yuYcq4O7mn9+RGouzVfVoD9NInbOI9fv+yjnUwUZ+lvbvaC3xmcxN1FdBlZcJTWCGzvf
0dBTxKaHnUB7Bb+NBWhqGP40EZoHcFN0NU2tohs3jVZ45Y2QOqamhF0PbYLK+9rYNYvc1/Lyyi+g
Lz27iOtnmO+TSrAkNaslROk/RzSalKrwxwlJ/OnmL9r2JBncj0x94Ms9voF/GLn6xGAev29IJ1kM
IBoUwVRmC7vZBhyCVD0dFvEfHvOJH8MLZtlqCEjbxIFsWUwdJJhXCU0xxstu9BzdutI3FEo5GVid
mP7Q+3PcgfE5YDipweY8/nCIiZyxfMr+kc43N4f6iPN3mkvPmZn76xnS8Su7axlvNPDPqbOvJLL4
bMSP9oKJjDpOSowKEJePrExvhWb6C7V5a87NNmS1bDuviNr5DEeV+3PrLXfiUXn4pWQmqKMIGCPm
PRhiU3iucDfwD1kzRTn5R9VFTInmNSaI0mgH/WFi6Hu2HIORX7TMhWyegK2vOQN56fjFi23I17p3
sVtXM5sdBJgnvyRfdGwntb4QLel7KXQjHQG2GfOw2fgh0pJLn7JKhKB4cfnaf5n/jDKjCoU+UF6s
OqSgnjeMOvrwzFfNv0lS3QiGY68mRwbM12LqhtYd4+gbtkKCfwmF8izVS+P5H8ezYLMgdoqtu9XS
OxCB3v+zu2QGYOMTfxYJ2DMW5GMBIZVXPqI2xU21DxeBIb600k0vCH5KQWerFGLvCjePL42E/QHU
FuQuslDl6UAF/8LDU8fij54Ay2iFDyHkoI6qcE53hTvDRrEXI+nYaGddxxmfC9E5XXhbn9JE1dIn
wFfGGPBZly2JxawSPE4Md1MhoFYGHSHk8DDML/XqtrWz0J3PF7avU0znUAecUcpzxKNKJH8tiEM8
f96V38EmdlgxSSTa+nXpMTIW8Fq1vaxGP6VTtM6qO5GeLIgyfvhSJ4korNjcSis/ET3bdMldHOZz
dq5JtZLZvVIo33dq7qGWxl3dNsD49RVqL7MX3yGV2eObBwNrOA36ZTbB/Fk+0AijkmQsbe64BdYA
PaFNoSZw7L4+NlD2sAKRVXOcYiPWYxhi8xrdgL/oG9waTDt4Yp4nPZcIFd5lVExoR+M/i4yQkALV
m6ab2gwf3AAuz/ZmJMpM9m+wkh9OyUhh6E9HQfAP/jrhH/od0YNJ1M2xDIEz2pIqkatWixRHEJ4g
bh1Ne5YWvuMJOI/Ddmxf5YztozwPHLFFp+vOZRaM//L5w3tHz3o8cd8QnuI7lhtMtI/9U/3qTrIl
teG8RfbDwJsiZEZm1ZmQ5rJV2gxARfFEenUCCds/G9tZ3SH3nnRI+LT/aGi9/rSnKc3yhZkaiFMj
Jxg+srFc9e/UHlKorSIaIATB6umwXGLjBrdo7PStEUZ2rHhsE8CqyqXtmH3NLYUUkbKRdCzQEN3O
KKz1c/YHDFGsWwG/IQOHxX4YhdxYezvIuHpa57zdb4BVoaKvGGkWaFkNTayCFkAFxwgxTUoSMIqb
nq7Yd1E9KVsfqCy7OFEm9cAD1KGDWcsuN45vM4xL/N42U+lGxCrNTJV3IJecv97ymomiPxHCWWTl
IStJcwoEDsWA1lbz6/sl0sOlYVczEY0jwz2/yDxak5YBDTQpAPEkqM5j0tRlSldR+HLEdyplXQM1
zgQ+xj8QscKxKAQxt5uBwqaXKFOEk2PEOu577JQ8J11j9eC5Eyu5WUbHzLtUjKnbTboZCK49ZYB7
dRdYWtvX0wgJ+5uWUN2/YQzQ6dku9hwWMZREskv6Kuh3s0dcs7HjiVZW8VMQBMhxrTknYB9vmtpv
sNfzyuhJ7TZxPnCUopvrlF51GGPLMvaiONQMMX2Dn7hiwWu/5iVk59gQ9BdG8YJrfhdDlmf0kVKE
VY2IZ7jHhoWwzYlqhVx1kO+cGgm1JOl5ZJvZTJdS+UBMjEbo1j0vtK8OYODhqWu35NNEx6fLdmUK
qQXr0EnYSNQyoHmunBzJ+8Rd7bkgRpztBhWrzmoy0rCbKWPeWUUha+K61mH7KoRrR+lXiRII6nBR
qPytdcFKCwoQ7H/4SB/1EednPabpoqGmzZ8XzQFstWyMsXTi2Nb7WX9L083Y4QbJie4w0FcJsN2N
d2r/HIWcaMrGvWwm0063dFOLPjYrjFOUAPZAx1PW7F5MMRP7MHuIEOiznaPBXhOEpwjTzMny8t3i
OKGF+q6TIFxnWyx80879kB2gyljY2jvgHRU5uCQMtB//cLD057jjbEQmR8c0SOW170qUak56/tAM
UaT5RuO95JR8GxUl6RyHfn6rohKx/8ueJXMRTHbG/g254fYTORa6BPx1NjgQ98+isR3uIDLW+9mU
9MS1cAgM9RM6Af4xeKo8MpUGNybyUH6F6+VBHz9JyNAZhw4INcVKnO+HJPP+bAJ+daDGOkLx9MkS
aHxmZTfxXgmqFCqH3lo6UXR17Lj3iH+Prp+GiWLUIeJyHknegf7FUipxb0SbLhr04EssvPO7Jny6
yuahscPhFhA5FntW8k95VkneST/U6N4JzVWb4pMIVL1Un0NstGTKavMdTuJGJMP/zHo4OvDntXaU
kmd8V6/TcQw2/HWC5IZ6LRbRp8WyWPX+G4lw95i78RJuGoM0KnpnV0ffrA6cadRzelCVksyeO0Er
pkwowaGcX/cojtrgnbMo4O1XT/y1TY3WV+Cvha/sOw6mMEr9w8CwzJvWzotsKq4J54++o32f+X7K
OT1BdNJmSN6mEmDUs8oMz46t1935LimIQafkJszsTJ60Snw1F6mahlPvkKqqoisuMYs9BwVlQMKQ
jK39N99SNYEAFrlPACr5jxOKvWZsrfAoi5XDxFFToJO1nVCK8oluSiFrp0/wW3wcZf/kRxuxImOf
3DDpGtW2ozwCCGVQ1JtjCzly8Cpk15AxertCKvXAAFJaCLfMWkQAugKRMr4c0o4Q6oQ0d00npFxd
8X96nyZPteNoA/vxTxHaFoKBlajq5hHCafsKWONwtKlH0z0clfhUkLPy015xegfviwbrJ4IvKpYc
QFZe6O8p4cKLavvZRWpobHxgocbuCGou1sbi8UIR/5tKkvZjI+P7FrWWrHBmKUwSAPt7VFao14E5
DMGb9/ZrcsGu9F1ZsIEKLNj3lhihVIA/bwJuedrrSpEyUX/B0Edp+NHHRXkKFpafMcLe4AttA0lL
WdaLu04W9IlS5YbzLPB5tKRr6VWX4VaIskQIw9AXxhw8dgRIXCfHXkYrjtFeqbOzD9xbWPKTUpLg
FGDpkENA/boKIkSpmggJTLOs4fwtl0CJmY0bX3cFbzghYBqHwf4r6+Kg68NV82Uo51w06MRDGNJH
o/Ha4g2tiUaxXKVCSRaH1OyO8q3vIxVnJZPuOEpjCsC6ipUef6HB08YnKRV6HbilrL/p9/by536/
42Q8/MEsxCEshEIpI2e3WoQD/OuHNPRxYMNMt0reJXJdMt0JTj24gDc2yENLfqz0lmln+DlZwFU2
l1qwOfSr4O6eeFCLUJS14JTU2oRpr2oTrf2y9O4Z+BHtgSoMpRVPCsLyXvtZtpqJromtAYZF1jyQ
aSblsOQ0J6Mipg9vxcEcJfLkg84yCVBwOB8BTPauu3QQrrHZJa/UJvRwnStRKBhRQ/ClHaD1+kuI
5xJ6EJQ530P1IFTJSzKWhxJ6SQcAY0fhvb2qDOv0xGKVXYRdFeptRYHTaP/qPlV9rZZEdsObTVcu
TsIzEEajcjLgvGSdFZ4RJD4Hk71erhMHfv3NiKMGh1yoHDMBGC9STkyA87uWzsFdUQvBUgJ4Ph7n
D+YKvxgYIecg+eMiwkUwLyxGdPyTXiw5QY3tbGe9bKQWnZlccilKn5niLxXBHJPKoeKWLHmesQkN
bhwFvJmBYIifjmE3Z/gCkqW5UmXTm8oVqJaUkycUxHFfMoDHqQ2bndQ56UkYHDSA9sDyzORr9FjR
zzFg96gWFGByXPnStptJb3Euuxyq+e/W7/ZywFw0eSWBOr+p19EX2rFFWcMaRbmpCS+HA4FvtdpI
wvayUR+lQQMfozRUSxVA2GjbCuu6Qv5/flPEqm0mWgVCktKHbwDytDqmUihwLhrZ6qxixHUtfBs/
es9nt7KJ1ITbk9cX4cZgMyns1o4eJQF1nhKRGU1gqdIQyuobXuZb2jvZ4nfSc7oD0fJWI6DaBU2q
m46tzTNkvknVZ2NP1cv7sSlwi4U9OBiPpeQp6SU95ZGXj8MDtmPkDrVlNPzvshQUuEXleSOnI65L
aYYJOlg0omRtd5Z37uebzoPU13qKso51OHT7mLldHBinyXZgT3ilj7fPpoxk/EWVL80MJcYqYFbI
jmGY7T2j15JvIUBNjQGU17LEzQXRGVBHBBvTBRdRn6YjhEM9abHWhii6vbqgJtrQhg5bp9pF8ko2
lwxq2jtaTC+7+JMogDWxu4U96vyN+fa1GNmAjbs8E11dkvsCOSZ98FMHR2KoyQa4phLuMTaEGKbu
7p7sNCTTfoaFOC+lvgrd9HXmRUQa8NwZ8RMHInaX3CcQrVfBuM1H8kXhJ3jhbmg8oqpRx5ATnYfX
yhkrDwMVZIuynsOPkk6n/IxIUL2IYlLoSIGf84FISx/DPVkke49GsX3fqkc5DR+zUC21P4OgxwzX
WB9zl3UYi5y0lasxMO1tX6PD5Dz/S0u8eg/YSKbj1BoF7GH73zBEdekKgDJ30KzLw7RhodbXKlOF
ni/ffNdcxzW8CbjwJQHPcdgORyRxiRwt6c0VGJmpBNc7lJGzKcua2sIeS4B4YIMJPxwJAJElH8wM
+AzL/+ptbokql+YGCacVYJCGZmh3HzOnbdWFJOEkBUPOodWPw4QwPivMpQ0iTtDs1PVLGIMMy7kv
WQseywv8zMJthYIh9tXNfDc8xn3Ws3fOLx4QWDKfnowZgwacgjGBXuPjp94QwzPrIPr6GU7TlO87
RYEY/50wwWLhEoPBitoXzpKiOGRXh7bq3hU2ZjLSLvN8n/2x0jyfRjiWLTszwq54IA1RlMMKwEON
JRlOEAkACcE7ZiFeez7qaTm3Eei+ucLwT1LjZc8Q/Pji+DLxP9iMJj9tohwb2vrtmtbQcAtOZJTK
tdpUR8X5bA2NmoevdwGyTGbXjATs/MfiterXBzEaUC+Nu8ysPErrxOxfqo0dakqYoUf1VtuyuTxj
CEkg27MGBjI6RpBQtwg98cNsJfx0vFDKQjkNsvbbdOLrbdeAKEL4hKM/UrIqFhDFH3qbAbK68y9d
EqDSFmICxr6DJpgwhpP3eMfQvSlqJ+0XV6sGi4ZOXUoWH1LuI+ZAhSbQrv5HGosN1+3m78U2alAw
uSRQa4gQDEkxaSYUrZRDg9uU8vTk5njgBxlyxRhmrWEe9YUOXf56zJ4zwSHw0PuLlF5fVNdsNKk2
w3igVsDgGSe/O/dWWkjcuGu6pzoCQsfc3jzWvyO5igyYoDc/IwJFjR0dahmNww1I/8pGVTKx4NzO
+YwUYK0wikK10LQgoSJJe0B/8OIytgrmPstixXU74cUAgsyYRqgmePDC9YaNhTRjZHvhvfpK2dvv
GH1sFn+p16aYSJGNZ51iFUrbK8ZVWQs0NWvMLy/Q/xo3BfqkfGjZQkcleH+fflGdh7A/IcW3iWcx
jsYmC3gErOrzIjmMpCUc5iLhGq2aMSFMUFYzzlZG8sWrziUNxUvjYi+FpQ2XgYgJ5mwD7hKlSkDD
XBTN9oIZOcyufBiMdrcCLvsQHHsFStLGhZuBdh8XDYH5Cv81NTlbfKUEnFcAGNBiQN2l4fE+dtEQ
tkFhPRqj5kF0wkuZioIdzNrYgfY4bPPW6msUGpFxFZQmpqhS10RIkoQrST+UfVp2iMGJ5vhZXy3j
h4CgR2hayGkV+17EVZwFaj21CKdDSQ28jkmNR6B8Ieivv70+hdmukxJ284txdxWtM4q9rfxsjMrd
KT99YFh1pfKLQkAVPMv1D2Yqn/YdRawzLT4vPZTLxGXQfYGpPM6LqWslTSkyD2uw5umCJOs1/VGt
v7zHrzti/K5/FYjdQzXYL9Pqv8gymWlfZ8cK8iRVCY5izUN2KaHqH7khgQZfkJF9ZiKwkr0eU3JC
cljy8b2thNQMQzcxTiHIuoJG3Vmr1R+1ojjO44WvMh876vlW+R+kygqiIV3PNhc9ceeqaJM/xNum
CXvSPHlQwhlNnwkMn9WpTt5VLsVwvWscfZGKWZ++vPDYWJZxNE8Y9BDg7iEnopuMCHL5f3xz+grh
70uBy9Lepp83NiwbrIPmHLF3iFq90reMPKG2UgcS1Q7mWU0mlz9gvfgqZAgByeNMxo3R0xwcBdh4
M5uoKBKnXmsLN/v8vIq5oZVT2bZRLDY8/GfYj3RDabBTOatjVrwoebpTYM4wkwvqYVHq8aTY7HbU
UWOT4IWrB+vLvwVL98+e59iWnTpeFo3KQIZzAZOL23Qgx9xRH0nz1RinTAHajb7drEV/+kt58mPA
YDlVRZdmQ4ksKKm2t4cSLeMDe6TzVo+KJRaG6QucpWzK+86j93Ya5sFc0GmuP9I+tPJeo2IroCJV
rIpVMW/Z7nLC0uCtXTiFm0E6ETwFzH7mNNEx7AJEZalat3NCglI2ffjLvEAPkyroLGF1wiRwbfnY
klGQjgfF/EhAVxJWc3Amn0/O2UJ4OgGIBobL0eP9oQOpoYSaY8+Vq0+8Dc078FJXf4IkpifIM3UT
PYJIoyJgJU47laYtFGHugxh/Lx99MURzRkxrlilIMRAnv1etQdu+StHwYk3V5Icw1yV21+wh7zWR
fq83ruvo99R2SSXjhsWwDpK5bM2yRHH/lmohrEMd+YHXO2/kBh4TsU2zsQ6LBF1j0c2y+ppKvS50
suydJ8QtCxnLjkOvEdJL3jw0GTRLjfxKl7Hx1NlegbxmJn1PfU5Tyx2gzGd2AW4kmDUEv8Py1ZTm
mDRkYjtLy9XY9v5yu5LqZjMee5u4rvRWGw5DFIdq+fwSQwMNgNc5AlMlns0eeyXvt3jPy6Aq+JpY
i0WoyMrSREG7lwYRa7GDSzLDUZz9swu73r7CqALcqxsevEwXN3jWJxI8VvqqrvAVJmlOWO54AiM3
S6dje71Pa7Q/LrZ1cGLh8je+uvrDhj7NW3D5pRwV9l1kYhttVfX/AIgtJg==
`protect end_protected
| bsd-2-clause | fac3fd3a082db1ebf423603d2b7d610e | 0.943947 | 1.864407 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd | 1 | 25,964 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1_3.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1_3.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1_3.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
| mit | c9c941f5f5fb2c24619520ea3225ac40 | 0.357379 | 5.116059 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_axi_write_fsm.vhd | 27 | 61,464 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
b5iEwcuh/jbBlgyw+948d3lvWBbFsOTNVYtA4pJb/+7lAHor6DKhd4akfRWg+MPGWaTgwtrV3Hjr
bBdLdBNTBw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
VtyA/tLK0cCJJRwkcmojHVnJYFSH/hY10K0O1xHrVFcESK6dXqpZL9jghTqU0K8Rgfgyj2mbpSmS
d3OjaMJOT/0rjwEIwUBTQhpYCQbUdyb5e+tsu6Jle32rY2EO1nN6daySTSkOW0tup2zZBsIOCr3t
+ejm/NK+miEBBu1xCLg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Sf+0xczGTqZZx6dcqp2GTylMp6ojNl/Es91rC3p2Qk7Z8FK5U8FSMHtByvmeihj5pitp5aOxAIcO
cjVP1mZpqkA9QTc6UkTBmHGnHSpwqkUrzOtsT2ws44zFj3ryr3hssigeWwtnVK13YgLrM+5chsUj
26gA0jBZIt1YnLsbFPdAg3CFuuIkHWQ39NEQDeG2BTbW5KtUVyDTnpctdLn+1GQ9lYJeC7lVtfwI
4B4xEL5dhZYik7uaLaobO+7jlipeHv29o8EQsg6BnOj1c1kxrXtTLsKozU5mRUSyPYYAw5cgAAvI
P9ELz58Fq2bFhjjPjC0ULrxEE7cl3R3lE+lEcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Qzj1t+dWRPGHMv8nVaAMZRu2BQPWmF3UL/i0LvBgsHGjHy3fNoKTLAs04wnbPCVtn8n3ytCSqZ9j
YDEGkJeQd/ctkBALil+9bfKGzVPGZiyWs36ilhf0nuaehXbM+Zt3Nfkh/wd1LKqVrJhOB/A/iGYL
jRkozXf4ccRU53dhQZE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eo3jj49OyneaHUaTvAS2/lR4/3L9GHwLzRAoxweYog0SBxlqFd2rrO0OlKoc3GfXgogda87o4tmz
l/UHxih0uJyK1snlhQ6A1EHKpMBpfD++gCN+S5IJFV1QgpWejKXt+0a0zp/A429l2cS7KMD2pUZc
B0C4VRE2SAMGJhfx1GIRczPJREH6ZIkDU1qmMs04rSp0PaGn6eV7+euaxeQcoqowg8QlRFnxfvHh
5JrqhxNCP2z579eEXYXH3AWOzWM/EnKEFUTbEaxMGP4W7RzgRCZvuM41apmXDWTVjEj3gQq6xKn9
0OWO8TXN0ID1dcJmFJe2x6yA91duGkuqWQQaEA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760)
`protect data_block
jfWNGfCyrs+vti6Bu+94ljTD07EXewZoc93xvKrueEL/5Z76UIn9W/y3zjWHKChs2BchQnyP5Dl5
UN3ZJ4XyJ1WDAGZXUN1lxidERMCeGEISnqIL+smKbpd+QV50DR82YghDiVceFoXnUZ+4LnESsqse
aKqwFsbLF7Z9qU1Zo8RbmNGmBq5CkDyb8iRnHbhtJT7hGauzb5txc+7gbluwsjbF/FF5E5pS2YpY
XISBTbMJwgG5cHk0T/jHEYQPNzpViht6RCtszfGGIEm5Jm44OQK8RFj47WECw2ro9JRzDWWA8XYT
XsmQ+Zh7Zh+iK0xZTSPX6fOYnYYmVzvvjhlWMSzj6HU6A1/gGW7o8L+GqQmrdzIu2Pa1KqX95xes
3k9NtQy4TEbFXbEkUJfkMNGNCOmrfdh5KY9AGNQ3qSdcEHHyq+FxxjMATT3NHRoPk07SbNSXREbo
Q4SYEIB2cSxkAvhBxRYxOahWb+tMSoxtmG+dLeoFJFemjA8CoyIVZH/u6KiV29Urnd59oAjbttvJ
vTiPrnf6aa7OsNrYFdrCqYPBD320AnVm6eEuRtg/00VWzjucxAbWwcJxK/JqFYAaGuGXnwkv9GNQ
wfWAJrFEqLQUnyCUICwFBXS19wLR/j7gFiDvT9d1IfkTaXwHZOB96ib4A6gEfhYsZBK9rneRsns5
r9PLoagy0Wz6iz6w809jYCq34TuBM3/1HcXwN1rGU8q/F3ySl6ycShHLfM47DLt6U9/Wkb27NlkV
8+9fwmlgan/a24XhRJSOrCc5UTIt67u081zWXRrsdPZngLVDA+NYWS5Ak37e5DowD5MyFuLCoEvb
tfzD+BhK0m0KXtJt7qYAG5FZrptryA7CJ0IHDxPoMBtmfEXefvrYQFBC5OgrbRccjp/+4z+0vUt3
YUew9PcSzTUBdDWNBHe36LSb0OZZaSbIiHzH1WKBjPorhzZbOzsMeVXkzEnq2iU+JrIk5k4cmewo
p3Gv9lq7KaacuUeehJq9v7gma1CLdllkA7oxV5qSWpkb3zlTP0edaPZebGmtsrsymULZKG2WJ05A
knVDZIONtfHG/ZX/qo3tSRBYtw1ps8CEyxTL5v/OgcV5J6+8vH+IJ4QkdiH5o8bM4CvQF2XWIg2B
QzpOH2jqPDCsQmpMkPuJ+0W6sBnixbmFooMa1TaAh+tUgE1KYesan5VaYBdAfS8njDWWDEmKHH5m
nECGTG0pRQucHGVyeOdoNLumjTTlHyYyqbZAYDrdqyvFGzDD5z7ieJ8ql7G/UCWt8XZXzSoRVpXb
1hqh2P5suheYCddGAzd9PLEsZkSEflJQQeBLtkFY6PC+VsKjXFdtJ6hMgsi2MHPtEyIJOKNCXooI
jcO9DKk62iZFqq32G4jSot7hrAA+oL+7tJdV+iF2BCjAkDfCmgnMXLJhBIfjLa7NYTaAPlGfe7AL
imZN0p2mc1syslAv9UmZ+ENwH+fs3jMql2E9UaEFlizItHrUiycme8c6Fe818Bh4dbzYzLIlc51I
I5bNlwPY/OHTbC2C0vhaL6mMQpFuzQN8CTK/G+sgjHm6ireBExcM7ujmSbz7ryOWb8XGnh3F+AFe
MvCF9yIOJxoyHH/OLFlrYFbYI4OMGGleU0TRc0JD1ECzwDF0pZMo46dIqMCO/DvwwTy2OmCjboM1
07CMXDE6TIPmD50nZR6sfEHPPr7sFIID9tYCuWVLSRSQFGvrDNYJf3M0KolBoXEmrWWO+oznWDlq
RZTOVynWA8qdGKOqMkjtIkTA5Yn+/gN2z+StWUl/UFyRM9Qk7XyLKhkcokgtVT+4/H9dGgknvjdd
TiR4J0ScOINuBFRExC55bYCqfLr9NKQ1WJ8WZ1TzRcr7zuoatrOj0ZmOmMnd5iquO3uiLOwB+K2e
c/84AO3xsRwf6bjBSaxtkw5KmetXM7m0YiEIAq4VQuYVyM0XyS5OddkrEFzNIOkUvTm9qX/1JOSU
JuTGO4REnIwVkPBUlEkFb3bAtNnuvQ2+igYEVE1LYi/+dun+9c1p3VolxupqOOqevQGvr+JaK4jR
awSxNy6ZiCuQ11busX5eVbDuvgf51VDgUX4xqU2HJQL1uzirIpcYHa+bXHNmSl9RDvrljIyNmOIH
rXEUvDyBfaGk49QQUbtRQ/vkLSedxMUBklD0LDOEc2RNcR0fZyyOnswaANhT0G4faFRBCvFm9yIs
LuPme92+0b4iV9/jaEWfiPtRvljonavt5hYfnZWSDA5doO6aF16uXh1flx1NloDXfLvfYiw9Y+wY
lTY+GtNwL2H/wmdpK0yosNL42Z18rp6uNJZBCPo0rR2CWLyORsnrbG/EA3YLp1e81pXV4gxgqFCM
yI3OdyzwMHsRgBVVwXvTkxucbcoT/I4CpfB5SpA3tQvbSyjL32mUGPCpu4mRBhGtmDtJCWXpbo2l
aOOqu5YSFc4Sgqu+ZX+AM9RdOSHhBWGKYtwNNrgKB1T0V1pj7RzAKKP53CGUaYE5IMUp8JYCzNL9
ErlnoHMfVz/BwpuhFGE0iPNtAS2qNdaaaUbuJggB4lcgeQHRan5xB4+oLK2P/ROjiTbUH7hBwquI
hjwl1sLl+A++YHUKHvbM8skhgqRUDqwG5WAy23lm/cTfXlSGyH84ypUuuyJABdPCTGc8tPgBAKdc
yg/4kG3kLPIxLIAYL3W6o5gTweAOG4HWa8n61rDkYvGxe7ICugw5R4t86s5QJBNxO4SJhsIVM9U6
oBi/GUan8NZ/PwDGPc6/7//PeJBD/ZLDPL29zMPqGxesJZCIIy8k3uDgST9CY41MumsJG2dn/YND
+7f6p1ltHWi4Kp7D4zM6RstTbha2ofQQxfox8PNpirGPPmfH9jSt8KjEG3q1IdK+mvjGgE7tXcQy
CFKulQCldtO/eAjF9uN84A0xfUfQMvhbRMXVIhSPIkepav8t5KjUKcO/GUwkmWhdjwN2VYooHSB7
yH6BLd5xXbJ47lM3IPZY0FvMe9oOpnmTxJNLBNCisbGkqLjuyd7mkQNhyAz5fbQVxvs8FKu9Ta7P
dEcjWHL+Dh5GTXQKa26kq6hrC+RrnKOdofzolCCn/KfK1QJYEG+ObkntDFLEq0CMPDYPgcj/A5X9
fr/AeU/ZtXg8fQrbcvDVh+WODfAxHdllm/saGa/oPpgz1awac82qVf4GP5RPIPhrn5PBMY/IWBVS
zfiXoACTrR5opMITZ5LT4w71bo7GIFxx9+PBpD2EZFUl4HZokHgCQ5th63ivX718cJltWXhagVxk
NXTrR1my9asve555lT15wrZR2xsfMS6oYrTClOv6zK1vJUNfvGLP/Xva0lZha5fSOHAc13B36Ifq
H3s7KKwTrfsEr3t69ppue+nI6HvdOmIsfkE4YCNcloCT/BiHpxIy3zZhjH304w7qudbxJoSA/LbD
2GpdghcqbIdByGPSsvYvUVAH27KyVHeRFuF9LE2T+GuvtJlrO6e5iaM+LLlXKQKarfgiZjGRqENR
oGygOL61EEtCWGFD6dCMF1nXWP8G/W+zlLqxxqaItPFEowrEiZv3okNnPx9YRnvSkgJychzf8BE9
CYYGGTBWmYbfpXyFliWGpQPF43FIRh5+6ow8ZR7QK/E9A3l3uEgsSxw9SfrdfSO3RLb0sOl21z0G
UsbaUSFZ5z6ucjlTZ3SwlwFi3LYmTdSID5AIyiKIy8o+sQA6CG8+8Uj24tYKFT1ym5ebef8+iYBX
+6A4BXce/O6QDhBgUelR4zAAMzSv/MjVrKHVSpb41d+U9QIorzG2DvDHRfUhiwqjTmtIZmM5bdMV
Xz5sUM61qoB3LT6wooGbpqItJg8T/Fxrvj3u+jRdU0IphfHDYT6f0KpeJdmxzbdaDZLLiQj1oI+o
LcPhCW4Z2TfgwBhQbJeivCtATJ0A4FKdLFY2lHKDDJqYpWTSI1qYOH5eCvPlzyn/gMxnBjHvWpEM
2uwZVlPCXg9e4wdwl2JKPgS3XGtoyrM/NRKMU42AwEo1VFkE9MzvWCvq2QNA5wF//IOkZpGZ+T85
yv+NlFwB3Hycsq2RGTH8Ihjdv1BTlRkuvyWsdxQBTGTtfqo1rVeJUcCYHKPC72/KwQGH+ZO8JY89
jghrFSq8ZNNshLLqNGRldKN6RfgmV4Y/crk7xQdqtxGmAZXrl5IhB9XQ9vg6f33JTT+jriTj7nJ1
LqdI4Ex7R8KzF3u/Od/Za3hBl4QG8VKFovESB68AFXzyDeAsGub444hrPkFA0NHLxyhn9mmRnlJ0
6uYQvEDBK6hpV7IYoMqZI32EtkgjVq8VBKn+EhaVFVZmNDBOygT51C9WM0+6kevS38jKH6yhlZWm
5Lwm0Bf1tO7+5tOWbWc8xx5ngKA+UuG2hrc3r3KVebgb0sbbSwQmd6gxvnfO9uEmuiQMI3hPlg01
T2kOl8cjBmEuAph/ok0UEpAzYA74n9Htp0FhcCQRsJdMbVqMqY1Ur9H5cQk8BTZoeahUmg+TqQIc
KZpxjfiz8hPm/CIWuZa+eGavGlIZ/PK7jpUfN1+e1TUx5ha7MzNQU6QwT++IySetuaFNNd9PwXy2
M2WHDvu/OAOtJzYzEWuMzlNHLk3p1kC8KdehZQhM/cNp15wZ0RgbdmfmjjI40TT6W7YK1FdGRVfj
lEWLz6zeaf8HV0foOwj4QcdZXalcJgkg9r3OSbbzJyRNCK8Jqk8VCJG18/cxzKL0OrXUzyC/vC0x
74VmSHi26vzHB/y2cEWLntkDN+z6PeLNie4Z6w7JRScFgwbNXUt2H9w2fjrpCF4YAj+5n4aWMCWz
DsAMVxEYTPWhZNgMive3dpLNYZGJh5uj6t5qya8o/8v58/93guEbPl43B1svG2iYP+/qIZxcZbg4
tZ2Sg1TkQWGk1L1KnvL4+sMase5ZGHXGYpRqYmjOboj9BfT0ob85tS3aYiaLEyMxazSFoAASmqp1
A99ykd5FrJ8O0mnePIgEQnane3GJb93BCuA9+R39IQc0UoT83+PjlnH6zy7ER6ivwPY2JuRog3x7
pLSYwe2AZZlV994FMn0A0/+V8RE0oE9xph2ZpOYtAO0MES1qDw0wik2pPcgxOia0iVJcV/qFDqyk
2A4DO9hHwxvEZ3ApA5VeQ0+EG3Zrsix5rfoLyot2bWlW+Q4GLkdSv/8A+lwoiz3Ln9hKJO7+HHiK
V4JavqGL4kazVIDfsnxmRVu9xE04jPyzdil/nq3nd+0duJi09sxH3zNKMhX75yLpRk63TvvS0afF
Wi35gqz4Ix+jkPBrhkDvghAHrmcHm367JT4y1qxZTrjC147lJpOKCRi1pFa7qWnpTh6BPT7SU22L
WreceDrxjnhcRrAizFdtUNBcf4q9mmlRIyksayXRPeEcreYz/kBBfVdQiuzwRblRN9+3hOmofsjL
yoek7pvjpKMqDbIE3rWWvntXYYrk8Xneg6cxICQxVB4W9fT6e7DmxWo4BFGzMgOIMW3eWHaWU3U9
F+7zH/ypyDOKFNTfjo3OHaNeeykeljpglKkCUgJO4VJO3SD2TYmtQ7vXOXEJ+DEKSuLb5sE7AAig
EbSS9VBIVrZq+paELsI8a1JqDqQZRd+Lpcq805VFhz4oBf9ItwnFYjDGd+MyVR2KzjHSTPtCEUTw
RMqifv/Fy5NTbKM7ERI+4dvt1rcL3gfSUMLBuKJ2hr7SwOzoOzeWMMNsJPJ7aWiho385lS5Vm8+Y
8aYKEbZ7CbGpQICf62dYTuIX8x3b+ulwC15WDRtjjIJinI5/RTwY+PlnerInkKJIbXoXy6aDu2yL
f9Yr4ggr5zhEWuGv79N1ox8nwNuPgLxjhI8przoVMiyvM9kxz9xe4xzaw+JiPgYchB8Ncs60qyZk
89Hn6xYvhHTIaHGn5mX5vMHpGfsPTMXKevIk8Uam99aXU4m0Xl35y1SyGIvJ6eH1wa6U2GpaTL2e
DoenWCPZBbCc9pXZk50K8giw6bLCt/dXYDEUTUONj15EE/SP8iJtQHDlhiTR/hJtGkXxE6pLGTwl
Xr+Quxj+yJKJ5o45rfdzFoiloI/a4TKyBQQgtg5CCOagtPfm3CSBVXuL/oyLKJwDGrsSav+tF/KO
rZ0UkBuuNAvKAa+O8Pb7TFdYp2szXOBCAEuwtReg9kqDTGL9b+BNCOuGF9ST5t9vwd7cvw0dGNt1
1Rq1AnhX2S/+KF01GcMW6IGrDVgW7PqcRZao2VIZ7louF1q3CC0FXHeoa8B/bt0GwGKBqrdeAjJn
k1R0nqzYgc+LXbZEc8R0NpfGpHvKpqpZ94vFQKzasuwwbH17GeC/KrWzhxjnMTU/9H0PNWrPf+rm
gZherS6lHBeO6LL+A28KYd8EBszyEWAOI4lUzKXVy+sk4WRmYzCWn+nvK+f5TeyeudEniz4fKGOj
2JVjEvO9PPYiW0tDaqRky0RGraS8RGplby1gRBffePtrPFSupI6wXGolysl8TUOGjXDGX+qoE612
8tuCkhV5/wXj2prkcddNHXa0YQBPTn/6SQvDhVIT039lo8CPTJmgSniV1glsVnfbE29kpbElyhDM
0Isyk9M4qm3gE6WIA1bPqR10nmPgd2LfHI7RkJRuaMNioYoB83a5iIChRAahpHC3dRINEJpEXNvl
d6T370R5NBRiiOGbV+fDpmyaeDQMxZxotEDYubAvML5fZ4lEz9q9oebsTrLtKKJCc2H++zUcnzUp
XVpr2Hhle4ugYbkvidhLTXaQWcWsIucjW7Er67M5bvBxGoYByoFwcQ9FBLGBggKODY5qBIJPOz75
vi4bcv4bqpFUE63p6oyVTgIVTCifnLYJWZYbNpkWt6STsdQwIClF3tswWi781VfeI+7VOC5dzHOx
T4yB2ZzjvKSL7XvcqKnMAJXkEKw5xjt104xxkHnCIsonnj2IFI5tVQW5OaSVc6RKSPocTyPAeicA
hVBtEyGmVHCByVsxpd3tg5a4k4bg4gsHguxHGMgBjCEq/fTrSem9t6G6F29/DdbjMZ5msaEG+Hj2
dQz9DgV8z7teis87q0EqHRD1LGfn2lYfVilYHFTHYx1Pt95kUpc9fSwYm3GECVHiQuP3LPtP6kgA
OiNPQhMbNms+MhK6+egsW9QgVDvkCu1OwyW+dPGMHqDIfqUGTpXDjTwTJ1wMUF2pNaCQ7alF1VC/
7xhWdlZ9VDUxXrWy8xdUUE9uzD/BpOufrEgc5trNsvf60eLjDbGWWyjuCYYKumdPRvxadmRGipVY
uP5aZqjd7nWBMm/p3ckrIDbIVuMn5An+yAT6+hqOh4vDh07afnSxT2VM0L40AbvqS+8x37/98AH0
hWATrwyhfR7c6HCfRr726Pdq2359rCyreCXUM5ijF5ZUzqAJAOeP1VqKj8xg6TcO/xlctwgXFnow
SnE5MuGXGzXc/Q7afOplYt7eKqRMjBOnmCFnWEiup6Cjk52fy5vxEc5d5RPNM+VK9zdO0y564Tds
XIHFyqSg2g7lpvqYZDo47owKLDl+9CcFCEeHqD/R8uIiGiCXOCiDqB/rCjYw9x95LSU0VL2yd4KE
GGprpBQZo4w+0zYGfYGcho1WhaN+y01EC/l7yvoq/HIpuLSoh4udv5X454ZlDaQ654OPpDO5gEeV
Wd13CjNdhuSqvJi0HCSIAN9tnee4B5BJBpL3abeEg1dilvx4y064aHqM72xKs7+iXJ73NOcMZlxc
ksNxSrc/+Omrr9vszuncPoXHt9gFAlMlZaLUfLIfryhvBPZTUuvO5cKlszAKQg1RAAbMZgl/LpWa
XZYAGtWJjSuPbnFZQuAuZhpqtFVuIwB9krRrkpqP6UtRWOPmyr8XcCXIx93HgPmpXrUS2ea+lVET
q+Hj0w8ZS/zoXyylI4V6hJ7pnNG4D488IP5VSgM9TUKHymyjWCVDPbrgMflvGj8wKD77y/yhNpTw
aQt1cKq4p0nlsUegiG55ZuqihLZYHdfzF+/6nCFzaMSQO0S5hJnuzCeXSLtGuKkfXkg9XL1eyVrS
ZQVCXORJ1Bn4l02LHftKf16bL6e5ShJjZ0C7IDVNkOCa26HalIyAu4OOOZqB03RBjo3Um3HkloOx
BHB75NEuH17+8gsp7euycdqvOJ+9Kpmwpt6XPCAn9e2k3yVB1oMG1Bt8Z5XsMeXQBetdn22gmHTs
ns3t9RAp3E3IayDDLA2jReb44TYRzZlBhs+F4qKc0wVH7SYwrJCQ90Ew1/EpQ5AoEGJdKfVe8TrC
AIFrJx5TckV6q01ZUs3wV2GuodH+gX3A4mpLiLl6PnuQ5yljqd3jWv49qRJBYrnw1Bxb8Kzc+4+y
eV9TU2F93FoA7CPJ7OQ1+l55nRonZ6Sp9pI1iFvzEU454f6MzDZySD7dfrhyjY3eH6cOIYWgWlRu
0Bb45g0V/TZ3KhoK4jWOoxKQj35RW0mzY/9+HUyG2/3QoukqhZblZPmEb25zOI1uXQMoMqICGHPI
/YuF57tG28SeJ2eLs4LqXFODP4ShUdGQ9+pT5R2HZLJ4gZguimC+pN94ELZc1EJ8k9bqordbhD4r
2/NeFKsISfzeE3RTUE9zZ8rqC1M4GRQGD98j1kxx9b5Dz+JftHB8Nu87tDST3wrzSuwMym0EmAL/
k/lzKGBrc3L07lqmtQziNbG4q4NaX2rrPfBXN7YA/nYJznHDsRxY+QHIv3WoIVra597w1JhjmULX
k+VxZ/NP/hTM/dt75f/5d7HDcBhHuVipOFl/EP+qTpXJec4I90J1OUtHJ0JR+VrHHQDktdrlAN3z
lqZ0vLw2WBFcz69DsvZE2rgetLxCan0K/oaspS5v+uXSY+QNhIgGA3zGBR1VXN0VFeqg/Vd60oEG
JT1NO2X89H6vXOTS0le3TRrsxTzzg9pN5u9d51Tb5TR3l03CxUd9n+bqWajIzd7oRH+c9B9Eavi8
t+nbK6nZkfWtu3azxpyDQo0goWD9+SPCxP3XMXcXsYnzM3iHP7R4fJgaFva8VTdhn8RgrZ2V3YhB
FHNGCWpdpMWrHVu8XtIKKycAApoNRHekdLtbxbs0CronnzMQAfaqmScoSX2k+E/saQfEqLJ2qrPy
5mQWgQXS363ITeB5Mo63qNBMsKfEdFqIAw9umuY+tfjedUlggid9PDW9LMJZbp2QpJz1A4baAEf3
BkNYO2IiqOcwoAvutp8Y1EFGkq6QHib1j75PjwCTy7aKvhzqBuhH45War6klRppH5VT4+mk5Kpfi
5D1GizKzrKfqwXVxy1rHD6nM7OE6H5FcGvmAzUGxUrEA9d7DUrwz09j8hrEIjo0VBvGpVcuwflF3
9EKljvo63igmGaakGAGNwARNxE5h7QKNala5V1zjzAEjeGfa95AW537VTTWrz77NycRoZ4h/VLYH
fSJEoVrHOFuj7NGz7p12UHNwc7NGzE6jJ5xuhKaNDo1qKYuHrcpqYC4IS116K9+oxxw+Q6gx/tF4
iqO557Nkh7hJouxYV7EJ7wMCKOW9RY3JYFOZDPQ/k7ECv27T1yvi0v1pEYbEWSIrjskP+9gpwtiZ
v9gAiUOMuucCk44EWlTX5fbpQF43JAPnRwjGF4LE0tKSETQLklZXukUcfA/KtZMepCiIKZODvoMb
fyn3ziYsi/Z9FgqlzIIaGVvCaob8remP6daHk89QsDmCi+1pdPFZEItcdn916zP7xfCpeMT5EaWA
2q+hUmOtOLmvLJvKrLEUWNXvoWTq7b1aMWR+KRPg1mHYUWKLVzz4C9SCLyo9Z+6CtHuqwaUoWRJ3
F3cHWmhKS8GaIEXwHSQhB670fclGQxEaxM6Bj7U4vpK8TaVCrT+tcncY9JkR1w4zvNQ385wmDN+r
2Smu9PYHe4pLxbA+zmfL3Qmglfv5L0px5pqjHuFTTsNu6tnKW0i+yS9oXidfmAYAt1JlZZcCUm2+
ItuVliWcJ2vDdlRkpgSL85PJxmLRzM4jtWc8H1tnnYfXlZB+dbab0LzeP4ghwFBzuGppjeDO2etQ
IRpM1NzVaSKTU5meykQTqtBkIIJOtqCWm1fZIHe+w9bX+XoPicYFwVGOxGJGa17uzVhGdyRrcN3b
0EG7m/ANL3gwHYXelspg4jLtoWn0x2+nHqpUBVlPa51pHsVmxO4tbxK9dfngs3PLu8E+EF+pZPeR
2fUQkT42q0f/L9WSgbsHwednEsH87s6jP2Dy8X1VZDnT0OZmP5tQxtTgnhsdGTsPuScikWOejpXe
BkjHxfSUwul2dMWUvv4IaiFOQyp2adlz9UbSdaRZicmx3lkTO0J1/vZtb0kPwVODvCO8IROMs+UD
aOjUBPRwokxwLhm86YtyHPLdk5gyKPfrTcPaN7ljsB4fA++6OkOeZluQV7Dtn4XE+vpZI1x7z2m4
ZsS59XkBg9qR/zxuAQpo60UK+3VkRG8SkYgifyZs7mPRFUva/1o8IeAuTigmHSy/E9MGjagbMbia
C0XqveRAYJ4/it9Ywdy3w8f9+K5lq7GehEIIESlhHLScJNvENn/M42QEkO5qIQGVw0rYuCjfBZGv
EfzQ2uVPdn4a7NMt2mWhlD6UuuzA6AdZ0GjtxI+ZlpThQkAoNe1VAFctRqzwwHsovXJhinIuaHoZ
2uHLuSdp1ZI9uJQfIad1vNpyMfd/XPYrcH9QvFV3ohfanJmbCi1nQMjGI/mI15LV1zA+rTbXBxPP
QiHdYH2ydoBmmpp3tk2GMRHPT9jQWW4i9gt1z3eM9ORFyl4QtKouIYI07+59kdn42bgqYKrjOmzd
SbflAWUWpm73jHnnzw0W1HvEcd8q8BEuiLBjPg0pA+ilQTVJQ5LiQybd2F6c4Cq7kNcSv3VVVrWg
/TlA5YslVA+/LsB98te4/eyLc9XS3eg8ZjrRu83F/TpLqu+H1V/k59uQfNDeCOiQwWLx5ml8/9MG
SWwUW4Vy2GQxYho47Qvz+QzLhiSaGpRXR66rNprkUqAGzJm1A9OID0tdU5mI3M4cpuYx4+5llqWr
Z+ClAsWeP0ovNs/fidEPnFlu9dV2ZNH9hMgYAchl+ktIIiGpMFucoeySPHoaumd9p4YDXnWdXjYM
uwxLnn9OwNYwQYnXp4qsd3Z/AKbeXjYmeV+S8VqFnO0V22WmT6Hj/D/PAWwDxUhd/8HMf/XsrvUH
8lZzZtn2RJcj1nQDAclAdNmFkWAsM/UxSdS+omv2HZ6UNpHVoDOrtd+nWsH5Hy6/01jEePU+4U3H
LVGPhDKaDU/7VE+8mJjOU1cmFbmECA4zyM8i+nFJ2N0PH1dum7G84wEjTjPJ77teE6RAVQodeykJ
8GqvH2EzhmebzqkpopjFv72DJcl9K8F6/l9EqZ2fBIynHTNlXkXg2BIrWMRO/ipw4hv0+S413uTf
WIUx4fV+PZnJ6Ldnp0uiAdYUvIg+g2WFLm4dPcrC9fnnXto1sVwwOrXkSAOfW7FONqQtJPxc7wyv
ebc7TXhOMZpg6SKVOavfHq9cL+G0G99NfD3b3igY+g6BRZRVjIezkx6Lb1Oup1dtrAofUsZ6HI/N
dDXd61gAAfKypE/7XmZL3DxiGSIE6xHgg5oelhis3GX7G0a3f0cJfiPs+zaqbl6V0nyvSqifBR1e
maAOyIhRzaoDILXTxnUKNzbRflgJhVKcluKrjCiVyMOgVYyqGtOReZuk7aSbZuMRfi+gRd3+JFvE
YBV2ufUcbnY8xsWBYb4UIXjIMsZcAihTrwMHjPhTRWhoJ9DyeuSiRPHjDTTYRk2j9P5d1LC/6ZSX
S6Gx2UaYV6LGCbT5KpidxVtYGsDZ3l3xLT3fmF09+wX7BDTkHuhaJW82xVOXM1eu1dlwkPfakpqG
fqEblNp3NEWbHWpFENSMJ9J/MvwUQY7xpUDZ8GjWqzY4cMgZiOvoK4swPIDFsaQO495aaqSwzUj5
ECK04q5I0jtIwT5sQj9T+RUO4hpHT3pe5y3aFD/9Wj8XCHLjR6kwsJrWbJcKlrDFkz8FrCJwE/h8
9lt3mCRh5lZmfG2R7StalC39sSZrp8Nmmw3JVAGf+HKv/MhCJBgPbcQgNfy7ly/uHr2ZI9xSUBBb
ww/U+W0eRFgXfT+Dv+dqBW5FVmPEbUIqJypU1WLKMhw9xOC8oCI218o4H9Kt7eyTyX+ikMKZKBLx
V38am+Mik9ExQIzJr3ZvAfVU+cVNnazAi3oF9Z2r7WwICjuvsQyaj0qZxNh83ATpkiLh9wUUhc0o
d5cS4jo37Xlc9N5a05KeDNn4M0l03q1OjqahMwNUSBkcDsycsWTxlLEhpWh8siu11am0PDT3cc73
pcU9WOuZBLGjG36CCUN9yhY/DYLSHcGMtdZfz4CPaL9nsvtdEzs+uXj7j2gi55EgThvZRkivAJTd
F8eJx61FqJRREJ/jXuRXMUMBMaA2QhEKMDelNThbVk1v9GuQ1CjlRHxtnIP4FbUPaKeToi5fnjCt
ZiRyPi+5+MKHWCEPpS9qpNP4DTkJtQSSuZ+xcDE943480YEgQ7Hui3pfwkGTX86S59Fd/mLFX7Up
fTuxAvG0H15aj9z0uaqCkadmfbLRY5dUrfGRko9P+KwHfrgxym6gRFuZFCBDQEBHoPE1PAHhP4/K
zozbWuGuuKbUfbNHnOYIpvIZGrt3bsUdzBDTliWjsBxFvVDknWtDHVrgvtr2TdDQgf4P7KOJlrPd
46v7O9iE3lgxDJOq+o/s3E+aCJjOsbeMwAR8PCWcYUqLJeENDfVl0LaGNkjB/hRNMe914qLsRTtO
6kSWoDghsiTpoLqSVec0qs4AqSkZLcu8WtR5BcpVXNdhfigQ9FVJRXJbMbErJjqdHBrvLQNV/iM8
DzQyq5F7u9Mk3l0ZvAjH2Gh9lXiyLnJuByZgxsC/zP+TlBIecnbqLx0g7OlXeu4+t1+arNhGMc3I
SuVge2FUrJeiQwq0kqtZY4NXSrBTsWEtdFV2Mt+r0tgLuvS9oN0Jj7ehdNQCwSTfMHJKgFviPZ2h
MraTZFpSH3w6cC+XFKVwUb1ScLNqocEvb/hkOFJLOOCzI88O9Zri2hz18ERmzcdPZpqcxYbfcVir
rntvnw6M6lhcVm0X/0rMYNC4+JqI4URkp+RcQBMiIX1FZiAZxktSIajQQQUjLEQ2mGDEhdfDdpq5
xHoqeJoSMlW1X8LIqDE2YKQVprFd2JFd6aChSmcq+Z/bY9ejc5pZKetmrVCfXCiQFFGmxI/t8E9c
KSO0Dx6z2vdqNgg0d2VC5aZNxJK2EagO/0S3ivQO7/0JKdYhtIdPMdLSzMzUq15SZqeRlgpBy4r9
4LAQuByoqBgLKbNdDeNLhh7cb7ME4MBjFccBtM5OZpHkHU+xjm5l7ww5wVsLg7eVUZAILPi42cw5
ZP6wMro/pz9Mkh42S/kY1wfMGiigbFtwh9A8c5R/4KA6wssjFXAUJbLBgsk9MBcQCAe65wGxWYkK
ZBR3oAytjban7ewECmJfolv2RvxrcspAMaUgerDr1knJMrGy1XbaEsHrcJfMtviOJWwc77eEY5iO
hEqDSDKgUgf9vG6esiD1SVN/wlDM0r1LJEmLSlpafYtX/1kBD1jFJAsxLpCcqIXqZgzRwuxnMHFQ
N20h51wZxz0B+sfSkdBK+mx/xcZ5Sa1Kf77UIbqXCKq6sHeofrOpKU2V0GUwfW4xueDjTgcl4B6M
Z+MIDh13M8s3uguOcY+7fWpIQRsGBCtUpoL+QjQcwp2BZD5EOL9dUGSEPEF0L46WqMqBVTIWcAt+
LRFBCdqnUFEu2szYuQs3wv9XfuOGgiGcxHJc2bYXnPIJFq00c5dA11TkGqstW9RB0FI79BNPXchA
KhBFcQWID+8uufAGfsFS9Bj1rD/EkDwGNEj5mmqznl29Xi2sFe29Z8ksxG1/RhFpbzMHH9tWLY5+
mfr0qGE6iHUe8k+k75Y3C4WA6rq6cH2NV5mklHU36yEPQRjA7WNRgrieUr0QWCS9N7PSJAmDm4ey
gZ+wMS3zqb5h1wXUP0kWJddij20ytQFec6cRuqJryl7plFL9lu+ARpvFbc+dOsl3/wrmWSIFTtHH
KWZpLKt1DDCV2gEaDubtT0ha/GRHnGQ+qbvwOQjxPXmxsEzvPxjnVtJdPwiaqwu9nLDkn5NoDP7n
clwxJaGtKQzcP1WGfcBkm8gOVqtSNGJ4gNU1/JJ52VFjwHIdrLv8j+oseYK5sL3/eimx2lA3RYua
j5DVk41t3ut/JqdJMSuhAPJZwedQnIfbKmWpNHSdyWsq8keB51t7xsKjnDET8gE5ru/CJWdlzvY5
4Gst+VI6HKVeyUoQQFCiPIE5HaAR26JCrnjTDkOx7tD9WKl4Mdupxyu4KpcSeXC5699KBmqGF3dc
RJCDXAT4ouB/bo5Q16WHcai2USQCZpyXG6HcXq+5dyTJxPuOGUQHfHxiLfba7MTvDgHAbX+Y3EFD
rTBBdImbFCjw1evaJF+RRHkxDFalTXopdJhapyNoEFn0ldQjbRdB0+JWrkWKRts2AjVWSQ787ZNQ
PrlCWMiihPfdMfB2XjwDNE/iNnj1gc6OL4JORN0UG/3iuHO/+PLjBRkFVwjyGk783QiDHVrYwfbX
lQiE9RPUjxDy0m2NpCEF8WpYZk9Ytw6WuiFmdIB9NxKNoPy/kqPliNrr+s5N85qulasib9BdufCV
Bu8Od3USm2iXhpRk67KLtLik7Olrn525S5zYmcTCoEHNTbylZ/1ui+cNxrroHFVW/k4aWXuiq5QY
8kevvUIbM/re6mzv9Vw3XKd0WPkoCw5E/S+h8G8DyRZkxBeiEmW/hZJbFVF62plcG+J+x5NXujji
Zluy7ZbX8w2l+t4QjvGTThLrQmBpeWLvzPmzIqlPRmQF6YknHWKsqw0tHTkyjkSg1EDy8wIeITOV
J/aUzVfidHDNAC093iW9Qz1q5qO9bVOu9fMGnMKjqtNaqyyTl8Xt/2Q+T/G6OdS2PdLMNZIfo+4c
S9Wl2eYNXFZCu1QIeT3VzRkhMBYzJnMvgu9sPk0VMfKlGLSEAcqdSx+xQbT531o4gNZLQdwds5MZ
doF32y0STlX3Yik+ror9RRG3ub1U2Eh9N9p5/MqPkX1M/j8BwQiXmNtw/lIZK74W9AwFGiYDcwzz
J4zQbolOukiyFRQb+iK3L4yTVT29Wp5MRa+f+PnUqBETidz9HavBHOCl06BQ0v/lngKoRHiz5mdf
ZuinJW+Sr2VR1CGO47IOu3YYUuiwSY7cJl15E+/jDwtCTxiVJGYD2ibGAd4HY9V3TPGUPM+2YWil
RcaqnxecKz7tHFGMh7fhFn4jUAUx22xRSw8rKjpa3ey9A297Uv/dp2Gb8xHPuvSDx5cQw2zkag4/
AavOHTtUtAPemQ7CdbwNmghfHoriy6H+2ShROEjcZZGK/uDXoRL7r+s+8gaqB8/uzJFFoq/yKrsE
aMSAoltkU5mENgpJevB+9Bba4YV5zVwbxneAkT3pMevbu1vSkkcQ3u3eyT9zK1ckXHBakiBmCQV5
wAGcscwAaZuDmRhGVbNSPdp7cUdFOiNpLlc5yFSbXuLpe4cfIS35Hu4F+1coCL0t4x+W5ZKTe/c8
sqofYZCIHdiYIqT0pXKYXxdONlv5RxRvhJT2cGM/OlkXHkOIemsLuGzgFKu9U4J9fXlHeR6VdE3r
Tj7VzUgEO9O+vwYWqSzprAUydrZZvDdu4WC4PD97Hz/BCuhfCtfNzn5XcRvIbZR2L/QNXpeThS4A
b8yC8tF02GoeMEhECohJ29USpGRrMLVNj0JEEcI6Y5RJmD1Vk6XwNYEoTaEvBic1m/CR6bOWcBy3
7Sz7LW0GEVMwEfObOd4ItTdH7C1Cw+dMCboj2Ql+PhPHlPB2rWH0RIKGvDYL9ntxORd84wgfOJ6D
224z4deZO5MHLOmGGgIdn612is72ubcFcEU3AlSNBEEpubE9J9bvJqBODpbxyB2hxhEW3ThDSeyx
NbdpFCU+99ZlVSYBAmsqpDZ+dm7DAQqrQUQTuEk63cOxcwrm9R9ow9aM1lUDqJR+K63Qwn5H+hWx
Ea9l4E8dn50hsaa5qeKyK6WkW7vRB6rUAiWxnmBPBMO5a6HAOFGGwLsHwlyz3r4iFqBeQco9nWIt
YZol2eptzFoqY8fbGg6vp67DxhyjShxog/bSIWwpYZAPvGeTVr7j+W9A3MnfTCe2fun0vifTWneL
cVJIDOd6NOuUs+833TCuqDsidlVlqLBucDbZ//NT8086h29VWnLEfgv+6oLGZNWRNZGFZKvhB0uc
EnV0CM6qE6V6wekT9LOFasnnLwOJDOKhJYiaDIT28qQ2uuMJkCtWAJHvdTXKcU3kyx/NVByxg3JZ
3zR/pJt5smxIKqju1lPl4RbvBpzK0XyHR0pD4hyxbv3Dp7TnfPOWBiN5+j8xdSdwf3UCY3BprhLX
PgPt0kG4eZRhlTzlgYFhaiG3wcjantOpaN/3wAjijzBxPd498ZawzEgfhERmOXxBKxws6BGxOuA6
e4LkqMfHwPWoX/I6g/6KjiHQ21wph+0LCX7lWDULzpX9dkY2ySjd/0X8bB3DG0yrWNLXEcDYeQKk
VZthmCXj/SvP3Qj5NiCU8q79RvCPehaSCg9+qAuhzlE07EeAPKZn4xbgWZnd83LHyWztsXIs5783
EDTdRlHmlQTin5WGd6qAEtOULX92gcogbE3+kLh7OXuFFFqDerO5llQVieWOxz5caWRd2TF3V8V/
iI0DvQQEZkS6/jHQ846b+hAxuiVKTonU1/PQAXLzW87RqL00K/Gk97kvK4+vKdnJaHZMufI/MP2u
Xoct/hmqSG5vHkmxHywqw1BrzguyfsGngIfONSXwO/AMK9Aw9+LqSsvwmaB10Dw5tbzf65uVzQjx
Y3fsg/K2YcLLruSpzBVaW6+mx9cLce8UUxnCj8H/jmrHhbvHIIhROmBDVcbNtZ/Rmh9+JYwEy6xz
JJ7XNXZ/GKHRt8dckUQrt+iYS9FwFlmE7n88UzeylB7aRtWS6X2kxIGP3+T0Ag4BtIcNvQVixFNl
R4X9DOzyMCwuvUEJYkHJ6bFmsnJ2CrS9XTUo7BRvUUtlVYryxGUfws5GNxzU0r4lNwUA19Ct5QNA
GcBTmqUes3L4RdJjJLl1EL8DQbrD5DDUSdsrfzF2tFZeD16oefDN87e4bkNa2QVK7tCVpnROU6Vc
tTpVKwz5g1AjYOAbmKCjKHYX6PPM0OHqLcgoQ9EzWaF363Ob44VDZB0WrgjRuPrfPPn2iA+p3VVg
kuEgdLUKdh/IhsFLHjEB+WYOAk9laRrtGlJIXj/4GUUjt4cTWirCO7dMVw9jMB8aM+CWR06WxRKx
UEAOjWgPAmk/M/n7BApAWkotv2chaLD+tY1Bi5qggAbUS508ucqLBn/h1B8tIK7A7fuqmA5sUurF
TzrDqHWx5hjuMNiTCncbsMAzIcOqPBC7GmyN6bm1kGgkXs8+O5CD1Sb1e4WaVXBCyhUPuAFhUxXy
c6U6sFbiGvsIcHV1eq0KrQ5jRkyo9/MorGu1oJQuS6OOUdGhq67VQdbWV+5+RDFUfvgV23jtEBMB
HamRQ884RiCohjgf3lVxcYffVnjIEuFtdP3kojONjvFvIpypXy/kKr3mGRX4MTmAN1LQW3af5dSh
CV55UOhD9CB3Q5QOuKcbyZQC3KXNy1MRw3Y/3VKfpvedOVbqVuTO0H+9ydPeey6rTQOgVkJuM3TB
tC5sKdUmdahlEYrvQavuvJAzSMFTU0mfa/nnKPLKdwIkPcXlV+or2BqOTXYXw72tHe08lW/0p8jX
Ec9fbTZ8+aY9yH7FoKeiKsL7lecyHIZPhO9p08by7Xsg0wuGWAgm1jHrcTinGv42ayxaMshc2X1M
2isjqYS+oDkT4/r3dAwTdt1e4Y9tXJ502d9fh4q2aNAAwE4U+9SlDxUa5jSuHmVhbULlZD5GlBJ+
1e68t+mrxYdrxFkmlE0KwXWmkRC9h60BCjxNXwiXDkW+RZg0GNGLXQJ6wNNfP11JQtCpCesNqS8v
XWzHbJESnRMHnP0KWeFdtunsphNhzEYldWT6DC6fVwdrypBJfRkeB21KdVUi0YZGJ0p/N7zyobz1
d9AEJG22JwwprfEvwcA/5glsnpiFrpUTryBpyH9SlkeyMJeiM+73UQhglH0TD9qDePhkAN/E2lEY
kuuogJZ5NC9liMbKEMQ8FdBcWkuU8YySnjFk83Rq9h5lKqEVLaskeajaTJaUy2FU1iGUBIlbwZoH
9iyVqNcu2Gr5Pjo2tRviG4O0Rk7eUEdl8QkUXJ7Woa4C3CQAgRpqt1MUIFoS5Fw48CdtMdOXR4DG
x1zJUDAHV/7x7tgy+b8H/bXNsnP8cwmRU0m9FBlTINDLCAyCe2sCHKtTomWXu/CTBm7Veftg5LT5
qKbcKoCxkxLq1UO5AqM+ND+W6HDDIo0aNGg7F8ohi+sybyktA88iGJncLdZJ05YKdrPolVWI8CKU
yw92DW9SihnwbVzMNA2w84oqbivXbkVLWywBbsNtHuTR5QEK/9DiysGahsZcjwEMvWjsRGCVATrC
9AFTGzK4oeYVYDxhTbMrniQp4OarQuLe8U8585tdOST9YmxXR0qABNidK1nTQ5wxc/xdW1FMpfWk
jS61+uwjpByV/rfTuhRxK+fZjPsbU77qU65wJEoyInmgQ4bUVfBJKTVS6CiE7SW7F6BhkYVgl3sk
3YsJDAhxa+x+eYvxgpjX+clH3ap3NVhf7GKhoYnA8PnMf8cCiS7HwFn9odekbhdXNd9ttPe6N3uH
6qXiJAlqaiMXXzi+AG29NEhSQEFg/2FqklfrUY3f5pGd/Go0n4eAfsLCDAeM3aaAkvOQPASjtRbJ
AgzUjIT7eX5MHZHBPwygLiejH+qaVGYN+pQe0YeARGP00pUMMYY3GdMLbPyaWFJUVX9ZQbVrsxac
+a5rihWns3VGOq9kJZL09sgJXC5eiZkU9JmRnMAJsT7TdOjy1aCBIC+WwIBQ3JymVGoQbNdoSEx9
D5RT0mfN40aVU7lD0hfMsSPPEnHmjy3u2MqhEDjhjdXFuQpbAmd2hlf9pFTbVOxkI9aYxiw023uO
yd5x2mJQX3tbW6BMtPT8Q/IFbMFycjrnAI6MD0ebEykYLH1bfhmSZLFbBf9wufDhclQ1VPYf75xS
gsSvX73yRPYtxtmHuajowNCKLg7Q7HudexhJfpyNuf7weKQYdV7lZn4JJjJv6Ra2Zjazpoy/cVqS
oIRPblG4G+Tnl+g79BdMGTm0QtJBKTa9Aq8bYJAnK6iusi7cbiHmcSjsAdtPjHo+faXngkLdotA5
0w1ZblZLLpYo90k+b7MNO/6tXCUSe479mBh68l7itVeDuQFRaVshyTbnji0Zf0DrNeIz/xSwS0uX
0hlUJUsI1bEKBsIJfe9bU6FnA/grRov2s5WPu+6DXp/NxS+x0lt1i8wvXjwBiAx+q7/k04HzsxgZ
f21OllDdOiqg8dw43VeCjnxzwsXefwdBYumFnt9c5B591XdOeDZtO0W2KmOkwz/yPIvWyryzZ4V0
y4SA9tm26xCk+TmtaBYzwm1TzXvsFHUsbMBxhY59EucbsnvFCqs5LhK89sqSTprtC5SruHP1pSxm
4I5ieVbAHV/P8phUKBOuapvZh0d3hBoeJvPkzK+QErCosG8akCRZj2RQkZonLNxC8RvFNsFeJLYV
8nml7ML52wJZPOJZJBAoXgxHr+LPjcNiaN16/F1qG2nkrENaA99r1yx/9xmXuQhbQX6HD88Bayve
6adSSyNl0+yY+qzCAv1G2s2be+IYv1gCowlpjx4rWfwG4k88mm2CT/LW8NL8+J6sOksfvImxskvz
Uk3P5sywAiXURAR2vl9Ro1oytx9TUxiRk0hDFofoFHAblnYN/RSTqlwSNPQagLcUXnY0EtMV2IYP
oJnyCIC74gIekpBrGhuqtaTovFoaiLYbWDTdUakYOE9I2ClNDsw3O37kAc8bYiezFeoeGAn6V9bo
rRyXxYC64Ug02txFsvGa2dFhRnOGTLyqt8osHoQR/DIO1Fs7j4AVXbJ1e9h8QdQGA22hth0djzq0
ujGDJ1TaFVnbvA5EYV5+NyZ9TzKBAhdroUkzRLiWIiojoDiV9vo6bVE7DMPq/LlQenR5AH7uFMQP
KoO2FCjfLmviZxX30qlRo1zaptq3TFCXGSoplsMWzOKuWqqkGCoUk31BWzo448sWYB6bN1yx9zGE
rVfEH1ekYGpD3nvlHqlyWENFp9m1kaXnORz49EDmfpCJ2Jrxs79i26uJ56tNABpb8useIf5dVam/
4TXhsFdfRo506XGDAoZkmrt1Gmm8l+gdWy3lE4DNXpeJkNx2J9USyaz5Bz1na0uIuBtDmM7RbPvc
nEQ1EDW/A7Esi5vPxP9MibyGyAhZii3JUFT5Zxbt9oc3cXaq+aAwtHsJS3qPjoqTkG6e8oEQhwjq
xRNeDiZUWQeicEZC6oXzj3qZl6XM/hNh/GLPtrfCUMCHOa2C5sMYGtNyxexjv7yYeTHHMKZd3Hkk
C03jTATe82MmRsrmpqPvWUquhNM5U3x0KHdq/SIk2WjvaCeEIqUt9Xgz+Bt5vihCWFKT92sCMfCK
d1eaKlpu0sCcvy3vouFhj/atulPKpyzkYD3XaQYXZJNwauASjhf24TU3KJ//kBraDlNn6ESKgVN3
TgptBT1bUp9i2WY0gM7T7UGwELdhaPgf/5vKrwtsA49Bp4xakLTodrZSc0lXrr6QCo3otS22zdKb
/q6grwK6soY15nkc42R4v5BEIun0eQJZ6AOgo+QsNARDqC06GDrSBHJsFSvqcV/9TAm+dvnreg6t
cTyrTxi//0gfzA38LFenK4FDpEoIHG0kl64bh7wEWS8sImZR3BGsTPOgQkS6jNND69X0o5ZL9KYT
sLNJhypH/Fq4tivrJn7FuMwKaLRVW2AuBYUfZkxVbliyLen4CnoTISAYr1hyj4xJMF/51kY1vcsJ
nJi2JnE02/lTng59gHbZy1rdeWdutXna4zSEShQWszSaPHvtz4x0SZ9oc/5OFo38abmfi8088CrT
sMEvqbLCiR2MiDLor0xX1qgXJmoaCFyGZffyRutL2JzpblPBY8f8WN4gWHXKyaE4yS+PG7aFBzid
cB/nYau+oIN4l5yJPTkPsiyXOReKAsBpQtD/0aotfKNq3naB80E2jc6p4gQFbYtqNm1eI01VDytM
n9Xf9Ry5pjJ3/GRbViXqW9HAyTM3Ip6kAjmp7DBcmkSO88+X/cW5DpLG2NBQSI1vhgVs7enB2237
yve/NBl70FK3REDcxJvxkgiDfWaCl+J0/FjSddQEf85Wv1fZMxo8OnGYuzYAzJPx7YIXFAUFJgdt
jx/TfA0x6hh+V5EAuw9WQ6zV1i1P7UD5sCElar61QdmLyi/Jr59mFYPm7ygQw5zBqzu00Cu+DPzV
R3hNdUXLvPeK/ddH2WC3KKG+CME/xTsN4X+Sko46hPzjBYzHk9RCSbvp1PFmoKkbyBACo2jlr4tX
eeZEGSIcyWIy3qLA6tnhnHwIwBEG8/rweRYIXBOv7ZlS5BR7QsycI/i5WepoducrpjKkcTXMoZxQ
E+StdqRQaeYIoeaKHqFz9OXPHc9KdSV+bKX2/Zns4PKzyflVcpiOq0AtGDEqTF0DtSmL4PqK3xGE
TM4IL3ZqnLPvKfACEBkF9ZGxeryux7AqEM1lPvmaH5xZ9JKw9snKoVQgHglXk82oGcfQIV76ibzb
MeAeQs1jJCQkc4lY89Q8yetXR3Vb+GtsZyP9sj7MpvzLYQq6Jm8bz8pjHWDziBKDz7u3rXT2345P
pTmljzg55wRuOVDG3z6NpwlHbsoHN2RbiqiOKd4EbGKHTwl0/AKRATWsg31bSCHjbpJ/jOgPLgR1
1CdlC1u/q+0/wKp48IqyY6fC4sn+aIM8c25nUvXeStiTZmD1B2QudCnM2nkiguTMNbreMZy32lHt
H+uuhHGYHoIxkA2BUHDPPMeXDxtiwECNMZrvCGp4r3a9QX4R2bt+t9TqIHlx68IgjZk77umvXZ0N
3LE4Gk16jZjyArH20gIu1Izlh8cE0Ihbr+NMWeQwsPUAliG0qOPKKRQGrMpAfU2OC+XQRIscR2qd
zNhsBLUsak5PzooJACV+vqJGCMtC8kYZ05pXQqICTpfYVJ1nO6CWHG9Ijph4bfOCMn4btGm664ot
MaLK+bVFH+cUvXjap0PNtY6HQCc82L8IXydU/NlRwfOg2G51IvF7TqWhoTEsOZv05+I8sbfKJ6qQ
OSLrTo+FW0JamA8PLdyYsfINTriLTkdmdp9F6huZnWVnNj7Gb0lDdQSURB3Gp7Z70HMA98aeftE9
D5mavXhf7b5k3QsTtyh7AXXb49oiMggjw6x8Qr5pJM1a/3574hCgTJlWMQm74yzj8JfitTcdUNl4
yA7pU1lU3HUFaZA2vWiMvnNjPwy3vLbHbLJ/Ec71wrPozEu8YRf/N/T4I/izfYFEaPu9YxRG4vQB
woX9EqD9hxC4hX6Ojy6uTWXNz8KRiPQO80l98yO6PSA9O7oNbMi7GXMcGxku3JlACd1lV6rygvS4
2m+1IY+t+7G2721X6jYbxGXEDPbXlBdFPZJbJOfzH18X3ezyxxrh1kfeO2YTOIl3T3aaODaP+Xiw
c1Srp/wxUmn2+RgjXdMitYsror6/Q6WqN6kZNbJbOSBht4o7gqTeJtlC+eBrn2JpyjEIG8Ricvzk
8EfS/f6muqCQEXyKKz9eMfGWN1RI09jDuzYlFe5UoW6/cm4dx2qmpZfI5BeS1yH07kdpniOOMoUG
y1OpfueXxL2usA8Bc0S/uTxL4HYIMSHfKGhEOcUtmrZtyN9P8Hdr5bVefi1V/1/UxxAed14O8YHe
noGS82NljR/fpkoozqrBKPe5Laoy9g5dGSR5ednSegmRtUKaeVUH2CmlpLXfpHZ39NKfvhYgKGUv
LateIIKUFEVfn5EaD74zoCYoeAO+pJa9CKqp0cFuvZ6CdFvlLb9XajC1pgNGXEGpwLx5j1RCRowZ
5z1M1lI++ph4tH7bCP20lwiFnvSbcNXWQ2pvwmzsDVm1s35/LPOzztPhTmpwh/uBkNwMKucGF4RV
5PtGzTgS2lM9Ww01mgiXzRC6mnV5Jf+eBUJJUjW/ZBwujF41UlmupyLliWQREb44qCYyJeuj7cxP
q0WBQiHPe73445q3Dp/jV7z5R9DGtnS9txNqSLlO1DwuQMiY+cnrp7rxQPUV0L3v4DwM3xn98HXN
81Ac4qmNPcZ6KGJ1hBrvqZRjSIJZbpPMpJmHmHsS3W0vM0CNx2g/Z2JJPh3NsTC2kPKWkeK+bKb5
5/lfBsWeeSmbfdTdMdT9hX6jJ954GDQGZXXU13DpY9AZbwFgu3U6/3eVqWvNxk+dhp3WduZNSX2J
DCz/hQYwPMwPJN77WXMiqCfnlBgXeN7cmHaFPUT0R2NWyOv64SG631hsEnT9j+7ZX7rtWHLuHnLw
IK6Xhe4OHPw718xqlGFZYxFlvgCYvA7C+1mzH5z0TFMKVc/PCULEYEyNs+dZkSvMcphrVbWrC+r/
sO5tC5f+my+eBDzxBgnpHDDFLGVCNEUBLimntMTjd5TKB4SSAghNoJfvzoey4JgGzCmFdzK9I+WD
sYcPk3E7SZCe4jz9VDNn/al4B21/EBT2Ru444Ci+wUgM0CpgI/GWLsTH1bsaaTBOsnSD6mIPL3gH
6IzuBCv7L7++Y7grIrd81KFXbSDIOTwDPCDRRmszxEyjpd1n9Qt1egh98CWUNybJAR9E9PYA0XVg
2XQvoPl4rEP/wBHVsGLs7tzmn6nVJxRPLbEQfA8L3VdW2sXPv8yhomLwq3p8GgBIcsuemkjeQ2pz
dJRvn0mq0rmvPsa/HEUSxtA7b1cpEEc8Z21kNTgYAyhxVv/fiUQiwrGn4CK+5hjOjlL1PMuJrGm1
PJAeKZTrwyhtn0RdyXCO72iIVpDLEEhn6f4hRlGDfCFDvDkQ7Hd3CWW9eCmiU6CYNikeIY3QSIbC
mCSBxeTqbwLG4lGFz/exQgTGoS5um6fo6+sH4lefFs8IS93nkQvqJ0UP0iF7B3GeeHlzvea8gZmX
T2Sq8JDZ4g1ZgPhQ0R9JhhPThUfK4aqsaAHybnPqSuXVC4lASv0Byer0dn6CmKdCTRvNiy16ocbq
VAtOwScW7s78WlYXANfYTkSaeQOrMyvFrv6XxycQGZupOHTUko67GJUrGSz1XvtTXr7tKJlicEkH
CHisdSd8ckEmVfcmPwSwCasaUVq+gHjN9Ku0eJCqKii1UzWDlA7JiShmSknL1hXv5I4QD2jz1iKh
bsxLmVxKaxOwokO8cX2BQjBUq9wM7syNsBYVTxgs76qmTZT01MptLaUhIMAJfst064DRJRiripvb
1IiJORlvxyIk3HZ/MVzLxtfJQB5EgcUzc2XVbkY5OfrweJKkqnV5Ya274B2On5AXJjPq0FuRxCOJ
Ts9col6oUJuOieaX++EHisKrgqID70wp24U+8eVuEyZtg9x7GTkGCyGshgkJGUyaQ4jNOmp0mLD/
n3K0UfRZzV3m1vyubD0k/B3X9AgPRTxzrcB/kRb1bY2b0IHz9SNpBl3rFUHS9H379hb0/qVcL3ya
0SN/fSiPNNT2YhN0BRaSg9+r/I39EzGkHDoK4R+jEWNpkFLE3mM0KKcvzvkoISLNwF73s1UqhHN0
MyVbgyoV6lkpoRVRCJMl+y9iUGijgHXymeB75EtzrnH+umyjCJs26TtrZ4JNTbnG+B8pt8BQC6tL
KTlkPzuSrciJZGlY0idZu4HY/VP0tC0oOMBb/xDcU0YjJvydPzMtSPC56FT8CohPPXMg68EAdPx4
l3eCDCbpA4UQqUnL2xd0C4570l7OYZAlj6IZxZfiS+Uz2Mt1iH5QSS8xmsnZcFoy+BJ5dclLiCqI
MpzFK0Fx3B1dciDKbLRHaZCObCaRflfCS8Sla3domgfAJKpLwEd3sN3r80caTalW9ISENb+NOSOQ
aGmq7IESkrsn3V/fR4Dt+aswpflwjUJ4ffaamYiaQuMofOqeIbEWv7eBpYovrtSjJpS1h0BdtBcA
gol4GF3OFnK9NBNLm+Z6U2glIT8r4U3Vl0JXCUALEYUPCbDQvr5cmHPzDzZIH+ImL8VvLy5dBdJq
DpsA5+wbPGNSFwBqLk/j2hEySPLENfGO7J7fLvxh9BBDvKCvRzz/Vvm3rCTBptx6gfLjUlUjQlqT
Vhqe4+zyunMRF/p1fXca7SwfyzalqNEgX2L/OFtA00vh8LUEgozl+k/UmEUHOAJPFMYZeAsPZ3tV
nVr4DVEm5kLul3YGKSHFBbvyDv2F18FZYa+XArGRxVrvAXqi9fpFQ4q+goBgS4SSfoIR2GDEzraY
MU0D0i9sTbDVPJKBY/WS4TojFdTJDTChKhzIcVNF6J3JLU2hFErl8kZygZvsTZlPABbPQyqJ4/Jz
n8DDeE8yLKOxx7oNdSBW6YfBQvQbwRkfCqBpjwPTNGOciqAXpDsvr5AIRV3TeJt2wWthtOPLtb1C
ubXWdGLM+Yr8SPTbyG4/Od9UntyyZcttsBo5T42SYiiSQMfuBXNJNSLH9IRUhcBJcceLX/8dducy
ZP28cI6qyBO3L/4XnMOFM3I2jfNXNu8Tl26dqUk3ArajHS1ydGCBOnAniY+ZeI6p/FWR9E3RxJQ7
VHAVSLrrvFLPHCBmf0Lt6jHAIjHjzbW6Uzjco07OhVtlrIp7UVk8oxBOWF3BJ87npaUrBQHL4lqY
wwyjfA1r8d/U99o2lhY0f+rvpcK3/Ew3adlrhPqjlZu5ChaupTUcA984BvRUhnu6HLWyLGh98Qd4
n5IylkoakSRuLKg0yMWeTJnNSkffmT95c287z2GtuXr4Vdiedd6lQJob6VZUO+X6qwf/uCP0TrX7
RICgHSOngjbwH3yzhUGh3dFxZRObPL5tvw3iBwdu4gOu1D6jmayZFMGkuuMcH4I4JravwRahDYaN
86+4bIHkV5OTszaFsgTNYgDq51JrhRipK69YK7st6+deqAAh+7mWzG2x51IU+SqKqVCoa+aVmE6H
QAfjM+6XnwOtwh6zjR6VuWoyM/O8Of4+/7A0Wui4i1c+RW3BUYtCpnbC0FUtpJYLTj3cbn1wvx85
aDu3UvAaKa0dtTx9baUB9PLQa+Idd8nE92JdeOPPUs0u7xA5x7D5Xfnf/BESoJodJKtyBaKj5dOb
3415r1M3nMDujeG3cvF8nJ64FFoDsy/97BOLKTjPDISPoQ1qQqvYUoKoh1QeCrmuUv83ZSAK8u7H
94kb4RC7VyrJ0GF5T40IpLcZi5EnxSBXvhJ6kBQXoJ0NZupe7h0mfJSdfUIzXvR1l6YzbwQm/aVR
yowqUW8PD2EmMBexlABBm3yWGsGIyyL3pY30Y+IhGcIWWJTlSz8ZqjHRp2wq1bPzYOlUos32W+W4
wjnjx7b9wtgSPHgtOvO3lKiplcjTZVvJLKCuXwdcWIyUuy9/iSYUGsCG/XzAUVX12jsTxyWc9nvg
7eSDzbeH3qNAq45o5lYhHD7TLAu37bzUF6F0KxJHu10GYuHsUJxfSGXmZHBdQd5GXGTFjJ5qDwZr
RqJw7FI2l4eCS8n6k7KPIFsDkuYZiXpOdv6k/3ocueM9GSWe/2ZeanTM7EXwS8nFLmYwXxBHh+lC
qLmCVzy7zw7xooCsObyLQ3MdmDQTkuc4q4h6fXIrxCLV3AeK34rYJOoSlGEv/a7lGOjxkJl1ZnMS
jSfOZXnj17etgwcrvtyAC+9WZjdv9WJ97W0iFWwLb6RynwRNvVkmtj5GGB3zXmsgwMgrx5arjPol
+tNiFQgijEevOinsjMQaXBcWAgzNuFFsOnfkt8SXbFm9eeN/VMH/wq1d+P86BHGiUn+FW5wSXfsV
P4yFdVbprAb9f6sEyQugfqlGh034zWDy15EbNvjW9ggN1n2R+Aawdo5L7BSFq6sEOqcbk5654O0r
6MXxBwJN1C11OybzzTgyKZBm+ubMnMlpZzKyqLXF2Rjws/AUSCNX/DOyrWLTrTOobCAnkayP/w7E
A0QPkM5CiFg6S6F8/Xu+AecG0pRlaPbSTPLdD/VhbX/4OMbttEqXyUdjwe0OHUOpSrOmFrKMOcmE
NPC+yf9Q1n0siNB/mqrr0S7enkD5bk7iesNtaUx9kSQc++CPxyJASPEWcT1yKqLAcLQj8BcDGSrt
3YDTbZrAAPHGXz/z7c3wEQqbtaeU3ED6YBS0Snwds4BxiEWVuWmMxxsrrZK8tH1UrM7DBt7PS1Tf
vh0aBiWUw2MM5FR6eqzuMVmUkk17/ft3kxQr+EP/tPXgtWTumq3Yfeoe2B5yaVaKxpP29H5zrEAP
tfadxp7QC/D1uKvMNiywMqpjNatQZOmz3WHfsEndN8MospZPn8NBUYP+Jz+3Be6JbXYhU4M8GzED
+ABD5fVPeiHqecaToqIq2pYc8lJ1E5qfB3ZyqBbSmgwpxs/Cqsknx0VDC4B3GFHMPruLHY3T/vew
8F1VK6WhhrjHzovxWMgdR4ZARdu85dV19wFSdg2C0qTtPDMmHAiMTt2RBE/sZQzc6V1iXDmyGTXw
Cx2l5sFuEfeObfgiyOq2RWz/tQRZY7aBWNTtHoGchz+wDPXokqKfwtffxFE8iW1RzwA2rH6nAMz2
9g3Epx8c53vaHU25/8IvimxsGnW7MS3YLAZQ/OA/5siuAbfi9C9UR7jQal4HCD70oFj/R/jJmv74
c1DtgXguhT8YupSvgnAoQMOJot3z94KERFOug6+P4HA3xaXJ2bYKcO+2Ez+A9mDJOH+Z95GgsYR2
COqyj/PfU75k7hJMnEKqkZ6bBhqYHsBuMY3SxMmkFQZ8auA1iKHEMy3CAvGKdDXrOEP6JJW5Si/B
oRNnt17QOiHqzy7oPm9tdPihgGfK9Aze50JnpYXadXNccHcNsV9iCYnKZ7uwnV0QjS2Yu/tOhA1o
mxsFacoBtj8PA+r/5djmasQlXGRZD50nL/lmMmC/mcmttumI/Y8A7k9Bt57jjScF/Y6pUUdxakl7
W/pJqFYEOoDdhxumBTXD4zss5OEgDgUEgT6cJGGVr7NfKNr/9J/nR7/LjhHdeF0bcBGFxi8FG6ET
q230fsHLJ6MxR1B3sWvK0m9aF/anJCCDzaL2k6JvXZ31cK0qaxGADIHUngxqOyrgDn9g2vLgPrj2
NkwewzmF3OUIlYN7YJc8iEtvZeo/YROvSjAmqSKHoaYGz/Gc7H68r8FlmxJ9X8UiIejOiSxBBrIU
LhTV/DNjIPVfskwpjXq9bwqGkpvenHjOtJjEkVfXdjlXhRtgIep3OGT4udOYep60mFoWMEmfMEA9
z4Biz8ncxKE1ErLAREdmYyMsmnSGwU2oIO6rFWYg6Pq7nvTn0e3VI7JmD3mJNw0NKdQFgzlwzb4e
bomf6JCmzZqYaDRPKoUosUBSYHwS1PdXtrTxSvTCwjlh0/LsjLQVMOTBkpVHX0dKueDKEoBMFj1q
NyjChm0UlReuRlWUbnIBoYV5wwTdknQieHxahiGI6im/aRXjwN5dPMhfLJwfDI3Jv7QfWY6uz1cn
WnX0GuhTBC3pTe7BnFTW1xdPjf0aC5/ZJeKUc8rbphDvUOzPgEA34orEi5O288ZKdAAGaq9zem5f
281hzY307mSQIwRr6Ifq+aZQQ/jZeSVLwj1MoGN/A+aMOHI9Pv23nuih7PMSDkySJV0JaMuNxkrL
CKjFy5YCQ9NwfQGFR383DRJWlVk8hpsY91yV8PZY+RWZD7kNHmve0pUkAp2CtuWMWT58YkDGSBn5
bQsFe/7ttNZc2rVGDVo7GCl6Dra0GP4sDEyqil8A5SLlHRTkGEQagac9Aj5rVyLUvhLi3aJyjwkC
NVs8YR7yoxl4DW4gN/3TzHRJUg5srNa6ReW85xJ0LkOK6w+2ewBpnOeAHX9z6/4OwF+TIdHpkdGZ
vMl9+cTzntuiMVxCnvH8s8QNjpLjFzvDPweqqXUQD8JS2QVygQI8PXTWISXxu6urP1x+C9aNYFj4
F4j+pC+Fjw//0bj37PEU7n0S5+rH1RzWItnYJ4dzPJQtol0AjoiaPlF/EqNZqK3OpDHU+24bDRHa
qPmX+UEHlYGFt2u5ejYUecLd+8bIyGmlsIRMizKDuPdqh6Se2d6GdjdYnpnU+bTl/9jreCNgiTwb
fpTwgUO2tOXfuNKBvJvCY4G62cbR4nhFDrtm5z6ylTCVpCcurv1sjqhMjsZ1laoUoPuYXXGDgriW
nQxnqtWj3mXgIz5MxWhYzzP+LHcR3YeAMmjQZlOOHFydZcuWF68vA4bHW7UQbCgUaydJFPxjLAjK
ez1nk1ST8R3sKcbPuCOeucTeAZSXEsm4OA2X17t2a6UUmiY2oOaTqpRyK7PafRNAsFddVOR2JBqi
7Y4Ahg+rd7oyEioAosszOtWhN7wZHFfgw/W/X7BpSuW3vt6dLEyUQKemAjtRWf2++XxrLmo+Qm6z
IeyscRnwtn/DWUx/g8bqKQkAiNQNE5HN+f4EJ4NIm3/6+SK9moqk1AusLXaOyuc6+My6HCAztZ3Z
l658t4bHSzNcd9TupnN7XgWWdQWPgeZXDrYaFnvJ58lnIJIT3/Z4pb0jh/ag3a/s3SdCYsALW3hb
q/NnBlqTzCIlZrCsghznrbLpebQYgvp+Ikaw1981DyJyy9RuKySGfsA4qs9LqHZoMwklHTIC55FI
+4GQbwOFsrJIwwTcPafLh43V8lFDQTbaNXVXMBazCazioWCHKkiSDWaUsgAbrb7TnfKvgxIy465N
VSEZ000NdeZNcFmX4ckwtUOWtElaQyPM2eLJqTbvxYLV4VB9B6fnjuEdMMHREFVss2SdtEnqjGHu
rtdGjK68MX4VNNsm9O8pGzHdhai8kNpJefTzlHJZJjjPDx5PcgMb3riH2/dSWkfnck0AnL1L8yKL
kPLgxdOHZb0EIsyKYYBtWhNcqGjIdNidnHUbA346CefdP5jJ1qpiZabSC3XfkB2iOKaDjL2d0UYN
IkBOrexH8MFpXfODqnhPsJcIYS/M82AzJAtQD6TC0Z5uPO44Wq8R63BMo8BERWqbO8d6nNsHagTs
yXWKwNggkcztmQ5C8WyurI2ybMHO6NJVwSt5c8mZ9Rwuajk8Rd7wcJeGVqpnkQ/abBFdck7YWr90
QDvB119gGuwq5TyMdYkuDcKTxc+a/lxKzQqlxZCn1Nqx2QNKCSEwSbagnOO6eD1yDGKi7kG/w6Cj
zNIux68rIigq3iPKmdpqql4/UP5U6At0xA5jmHfpcMlBN7f/YK+oTbVr8w59/zv/ssi1nh+nCuj1
Ix62meIHePOMhdkSLbCQnWKaD3uKemCG0jfzXwUvjrwCnjrHENVeZxTS8l+G+f9L1jLHar0eAB3l
Ty9wfwZroyk8rfpUSpaITMBlH+fPmXwsMFY7H0NvyJWXTBG4RGCHy3s+eIEu1lHt+LmNDkXiMp/s
Px/tUllftn327/g5LS9P3E3kgVad6WkrHjwMT5NrDk8WvvzI+zIOrdUzzdw379nsYQwE2dCR4XPK
cFp9Tsp89yL0ZzJprCUL9nwXLkrT+0TrojzuONzfsP2+wdhUdxYQqElPrJdndn0yfbITItGhRgp1
eLLiahBgcPb7hE+nfk5RigTH/QQ5nBPNfl3vhAao5VNmnHapaSWmnSUa8a3R4iwd4DczOTDyrFHi
ZCBr0/xNzv+XkKoKHJWbOyOJEi9fMgJnZos5YxlOUEpW8huYgjPUlzivkScYypBt+9HjMG46eQ7G
pJ09F2fCwg/p8Enw4+/TUREAS5PJXnTMqXxZb2zuTN3hRTI4XTprQm7Q3Tfq/cD9rvtyhV6bQ6iB
p5VFYXxEdI0PUQiz95ByktO998iyiD5j1Y4ruCoVBJaE3DP+FDEsyv1a8hCpPGlTtEPMMj65xK09
OL9Lh/cYdjM9bcrYWbaWLHQIf302UG3J8+FCRcu9HmYs/Rv98w1pOFm0tAhSuMHNyKL62BPdA5n1
L8FydOPrEo707A9H+BxqeYu8DZGABmfJ4Zt45KXLIf7kxdITM8c1Ue15Noi9nPZ8jAYUnd3eMdze
rg83zgWZFDDyUxCweG+Syp4Im5KnkPvnRU66nlNde6sgK4ClWaMbNyaZWzEyaHGAOS3/FW5sFo/Q
xByV4wou2ceKXAE8vmx3uum4gulUy33cl9B9fekFy1Yj/RqPdyjJEr4ZUPTRCiLg0Q7Lf90oxtc1
2TDsttBo0KjaJwXWYuOLFZZ+idsHm/F6BDDv1ilWtwSBTdcdh0k0KEn1MgAoiLYw/KM+vx4VWUat
XEsugD0Dg5GSznO6I8YHASvb3oChd7zBNo7A/JEi7oQYFJRhs7Kr2DjhrFQjCbK5rfVp4SRpEMCm
oFiPlhRLN9hhdM3879Gg6PMix9h5tbC/5Mn/MMX4ZGNu90s7bRStJk+pUnW3QALO0td8W/5vb+ea
utvSYnFLPdtj43rrzKS1M+mHPny7AKlKD4OHXmIiJza3c65quwf8quuO1k+CvI6EspBaIoEQV9CX
DC54isNZAdn6K6MEbzWCJYDkXBnmYlG7+E6mwQynQTEgntruQ4g3tU7n/lUwv5kmBRL7Hbxj7zXw
38Gk9jlNDvn9iB3gC8WwFb+QRSwTbnvxs0fODDBw+vH9Bp/Ze4ux/3I2ISAZaH6/Sp/EJW01FoLA
eaiWu11EuR0gSZSaKE8bOA6O8Pe/Ff8s8xVv9bPkWjGc7pgmGcQ7ftnCe4to4OnblybX2ZYkn1Bx
WXun0WYRBLiF2dCs7xv3O9fEPOarJHZiVKpjq2SY8zPhfQkngMqdoUFUW6nrJEWnSn5BfBl7OCnk
olDIq4lMbczTWYNq8pZJXjZU+AE4jL/qPSeJ0kXRiyDSM/KZYXkq9xCGxp1azuQRsXKYYTAM7N+k
xvuH5w5wBwsaKf7DaxExXyYOASEeQjpCa0W2cpmNpAdOAoMgBuJxE+ELk6+y2ZgwjXFTtMp1DqWe
FA/w10kb78X2S3mh2lAheGcbmFuS2BQJJ6+1qo5lD/TOqQgyE2DKDSpUB6dJxYCEHG3yDjTITIFV
vSCzggBijI3kJ7OZhFCzpb5TPX/HqbBkBYpgb/yXTLonGDu3SnustpxNobqsSJpslKFsng6OiraK
IYxsDqkdqByI4vAGrAOVx2a/m8IO5m83vItNywCd8cRpABt0xp9IFEYiwmixZdK+Rc0H16EkC61R
pVCVmYq4n26i421/fT5SVDb0kwQZmzmrnV9pTYL5W0do0BM8OyYCB4EyUgzPk022BIMbdNLcoLZS
7we0tXuHrAGMNgtW1e5OUGUki0hHFSHRGybkcFRjPlIJMAc0oINiiE41MkxiHAgBP0GP9sYQPFOK
YCb8M8yLgTNe/PcJ3EUOiV5+knvTIcJUJY7o+0uft1El4u/fxu9GiDfj6YcBKqgx4W2LcHyLtasb
xnAlXJcN5ixKUn9BS9CedbaUROrMzabJ2EShJ2KgJ3d0KuRYtlBP26RraW9pg9/pQ9IVC9ExomzE
WX3yn0HBDzaSRfqL6C3LOz4Caz/NcOAu5AxT5IXpGuMXV/L3vNvrWuR99hYYeOZ2fcQUeFuT5bt8
IvKhCJlAD6XHD7sYiDeze8L4fVYB5SQ2Y/sCpLVS6/lHqZkks2a3YdU1uFi/M+8fzzFfVYJ1zbho
8phFM4mtOuPEwdNFVW+UbI9RGLVWkhZsbLZD6jmR+sH8UlE8KAp6zBp8JEhdm6uqJbt3+4SS2MA0
BAvfC7a/8yNRER+QQ+71Nqno4H6oIVNuCG60hCEvwSoC9IKo/VHrKrpgdtieCA96KAHu+iZLEz/r
eLAgGkKJAx65JXL+vzICzUGVbUZYrGmbf/iYv9oo07gjQ4h3ZkPKhtLPunxAqRD2c4ZjFAziNifQ
wrwwlBcgf3Mk1SY3x4R8G9iA13I9ENycj+4eeLwjKz3LOGpOscZvXmw8cfGzuHF/eIDrtKyroi7k
4Txzibk61mkbyPZhaYcebUf/+yoatfay/5TQ2kwMJ8zdLcPIBcEg1t5SKPisYzDOekJ+KIfkJ/AJ
AYKMWulKEW9WP5LLQcvgpsFYSl7E+kVq+5rrd7Frkzm0cbV9A/sIpfXClpt/+/oWo17uVkIF5KMg
/+hEaevfiTNf9+ewYG1JBO2udPqzToSyGbJU/v5UEWh4X5M7j9ASJfGzikbuxA+gQnulFw0eFAqF
FXVF91zKbWCFzPVku/88TQ/c5gQRM3UPh1rjKeo8HsRvmQLGjOE6sIlkWSt8U7uWLrshWAB8XPRq
iIr29gpSa7n08r1rHiS1mewdCE/RvdxoKUrqhIjy03b7GwBPy/8PaGkVyXM6N0JuOKpYQOPkGDF4
BpIaqn/O/yLShOD4ZgrLfHUU9n5YKwKNVMo6f26QTjKSSuIhAr7/7TAptxfBqKKNb4mTcgEuUslp
SGNpVliIACCkhYgJPr7Gqud4v2EDFkXIbfi6dYntmgh0q+JS3Himp+WRIde0GquVto7DMkwKx+pB
ibN4buskVPVjtdTUxtDxbyoOq/1CK9qp2y6ZcxJkuTAeDxvutgaeS/Zzf09H7Wr4pfl7A3i/9UPV
Siqks5JEw/7y80zxvrk3bEdN88FdDGp4Qb/zcF5qSqNQvW0BeHIY0EMy9aSHP+BGtTUvGF6v7YA5
ppTGPIP/pLG8d61kzL5hxeGpSYMP3E+yeFTTnoYvsAEMm733+qrb67JUCeOUa/FYjmR+NqdrLkY/
4CKpPyBGjJR/eXRdMfK/9OMYaQvddnFPA60eBAyDqWB9pCXJs/7jT4zqejns5jZkgWNLaPc4z/13
vYJqEBF+I7F8G8cuKsgEB7RqywXa4Gl7IBSLyC67hL8QB23gRVv7IH3TgsQsfPoaZ363sRm/wa6G
sdZp/bA40WR90Lxo2eK0QXD6cwTTxnlKIUISdPbEkCIMVN0X0Dpg1P/LUsbev3O+Mqn40YjYxDSc
eeKafze2FfnlRRSMYASfug9ZiG7K5BlFy0vw+O+5PHbZ284hBdErTRwL47guqo3BgXBzP6tV6TYT
paGUwdDxhYpR6+OMNr4ew3STH35qRzzKLc2Y2paNkUOUfbiSDU9wY34vOG6wHo5x4og5z1bdtSAo
GISXaxkyh7AyxtsygNQGdG48+/bb7BoWCbbUJZfF60vUdyHfOtwHXzVbgbF9XUdYjBsZiAFZrLdh
1YXiQlxPfiSGoFMwuVA8uZFHUN+2uU/i6oPwYnMhmyTTcPHef1YMrOcm4MaJSZMxZhfS6Ei1O009
DSVCQMe7QkzO1QfAGUbE7Jrtc4b45g92GkzaUCS9jRCYJWeeptlyuWJvHP9ku9kgtLsMjT1MbcYH
CMxf52LYZ4NTkZGN9z9Q5XlQ9ZujUs2/0X5wXs32sWPHaZbgbPQnB6p73mbLedPpIX/Jgx/1JspG
rIlqPMnhYXKsoAlgSyd3HFcRgbH8O5OpLl0qOTcI12owzZRc0TaMquIbNB27q2QehNr8YFMk87xl
9CeMbiXmyGPZHKwrqttJ3OkVAP5MAseQlQiB4UvHywrNa3qcCTpzbpP/PQj1j6v8ZzNYF0XcL0us
pOoX7P+kwDiu6wCtYC/Xc0Vz7V6GxiDhecP2DZb6OP2fSftB+4/0SjFTE30Vz9nF3TSjVuVZ6FMP
sg2fFRak5oOF5W5ivACgk6+0JbbGcs8wdVvoEmdmkN+VEwOnYy7sUfty542jOJwu8WKTdF4UJSjV
8FH6ecGerQt6JwpoGewJbHxrgzlKimNkFXeAHi9dpW0kYXUuwmVyd1whEMCRsNsyX/9KGeSzIaXV
H2YfZTiMex5YFD02sDf4FPST1usiVjaQxTR7vl5hwEOsa8Cc9wTbZgUv84LGlBfFYlxEokDLq8Td
gKkPdNIzm90+udY9sO0JocYKVE/N0aNCZtJIg5/c/SyH0tiRYbfOgxY8dNgIljL3zTdbREhjrSbu
fYuIBEY/k5qRatEQdFzbl4IYwCSD7MKoUjJ/BcYIreaP4kBRKrWDQzj/iJw05GCfu/clAcAZtZVd
XgMrK6wYyLWkMjJ1cPUUcPhlU5Zv06Kcv9PzgDCdKYtBx2PgrCJ3Nk9CZhw1NK5T4asmNBHY+0am
9JPWkaot763cJNZjcOUM3jnjS/CO/19GS3Jit7zWdpz6ZzNvBfoqFgzj9k8jJGOSDoHE38cAUPdz
SqsFOj8cOr/EXadXOxUdLM10HYrmCTHMkHwC1Lpu7JGeOrivg63NUagBByY1Pd0osjiGy+koy0E0
SAoAiPV/Hno/mrPNA8eR8yrGkHIihqJYsIzky5HujOKKVqk/Ql5gcMuWSfnDohHPvu6sgZfhfp5O
AAutesFBkAjqsQpmUXX7qKeH3ecmXfW2lfigGryHiQhf+2GJaGC/ZqM5s1QA2ISWGXged8k4P6uB
zeatr05bFh33fTNv4vEofNnQtWK0F5S6AP0Ude14QFSxzttZf2wxjmwX176NAQQzTWxv438s+BdZ
202581pFzLLlo5b4Bzxkb2RcQEko9taIe2YoL9ZQnBDawaNAM3yyBEJlrqgYL+Z0A/Zm+ika/Kkp
fIUPFGE9fCwnWDsRD6KZ9os9z2UJJ8f426bO8chAiJnBDNGOdu/ZArqZhq8ujdnl/n5+TQW6Nk67
LQAjC2FIdQ4rqT3MdhHXu9pikG0ghqLNx9XOEkjwupNPSBlk5Ndg4Od57VOs/84Kkz7mRbmjHezF
IX0JXPusiBpR++2PQkk6MWqoreiufJtS6bDeoaQAuyUSh+8TJdqb8IHqq55T8Rrdac+dJQnkOpAg
0IPRSgOm6j0kMQkCvLoctK5m8uV88okq8YBxoJuDBaqLPxg96o7a0KRzZlUHj8vM5ey4d3G+PQre
OQciMV8T76KdCORopq/omKj3+UXBoYKB8uUPfJQx3H7f46pTRgMBTnUeEj3tVUShO/OGOrAjFk/k
K9AZAOSLu47fbR2I9V6fuJagnvgDX/epA/CY6YgYAdSdVGsB5ow8pDfCpVD356m1AVyajNGv+cKu
01jGvAh/eri87ydDezQbVLCmJyai1eHZOon+wx7hDWXmnlc2CrV7NgQ0vLBbKSHkYmx3BtTmYLZA
gLVdNS04TVl/8Xpdm0savDRrKkNupfE4xKNANb9qMALqMOHuLvlnQUIhHqUthFLm/OMCL2Tf3Bqz
Z07o87C4sputUS8m46Od7JAZ6IAsEt/fK5eI243w0nX/mnYrFf007PIIu6CQFPuAn5tsX+6coKXx
TmbkJrPi9BkKB5FyldB9LfggXmG7Rrar+ZSIez/guozdjQfBYtWbKjUyCGVl55ZzRzfsegZvGjGY
/TkwaoG3L4m0lINEIML2uBlD+MyPgY4TXPnQHjNz8NLOm+bVlXmZMVXuC0dmex3tkutWFUnlo09f
eecpQ//jHh4QhwKpdEGOcogm+ZzLcchdVIeLQE2dLSZjcZJWHE4ylhBhonBP5aFLKCqWHgky+1ms
qwgRtV0xzH774LnWzsnGCNwu1IOd+r/wUmnCCbXkrXjShmRjgV/M56j62QbbQJtzUrhrWf/k+d1Z
qCmyBEXcn3GWy+IQWqJe8eepuoUDgd1+/uodZ8piBb0B5pybwQBIqPCdqLp4h/h0rmXiKgaykwRj
qTo1nc7c8aaEZZhBqDzpGWIheVhyXgFBjNMO7jdBXihcQCFulXBSrnquj+hx5zwO3qRNsyBUl7f2
ghDVIdOgrOIh7s4OxmK1xqvL4qK9/6farblM773tRc2S771oTX3gLtKdRHieF6UTi/cuePZ7a74r
E6Mj253XNvCJ19iYShxJeiw7RFKtAetiURHxRvQPqD09DtcGis4BhVZqSDFd5DxfPQb5ASy0/H2R
5xQYjPuPYXeECIxh30+WVhu7B54otattUMtQLl+CWVpV524UTSZSIiuRX6wgknosHBm0fnII1TjE
ntek8dtf26QOmfChXuV5YF+H4QRbB4FSeysxgvGRynlpSNzB0nT2Ki5CGsRKmr4zw3cPsLDclSHc
PiqSR9zEcrYYXdf/J6FaMNSgaSB39s/W2nNU/7tsu83EsZ1V2BFTBWkHp7BzWyRCZiW8hWCQEAiz
S5+/SzE0tRSgabxL3zhjjv77yhNx2z8Q47GetT6ctyAy+dOVLCWMNgpWymzzgzU1IIMfGKTcBXQh
hlai8ctEY5KmiNA3Okacj4W9ZVdrzd+VqDFQAmRL31NRAQvTecFVD/CtXoRXA61+IvKGk6njWfII
Wty7qhYl88TPxBJEynP1qNa7/Bcu8gomTRkNAA16ifQKPuBdifqjOd5XWm6kA6wrqG6YaLTr0YGY
l/FPhgDmG6IzJopHfmE/4IGax6rcgZEse/DaoltZtn6jL3cJVc4e8RnfXCE910Yzt/1B+x2emF5H
FKBCOfabp/faMj+wcYfQjid0MAiEluOyTd4kYqeNM72FTvYvbxEIihfGyuhM8sWyaqmAy0XZPdpl
vkxrqwZ9kObsAABNlLL24TYKaWp05K5gxG9VAkcHdliXM2b9idstftwMwbM9Ic/R5v2ZevimrzEV
6rvJgrmd/R9wjgJYX2kt6bzv0QF9226mR039FB/9YeR5yxlNH2WrvI4irLbp1zjR+QHgC0FFQEWu
FQF7DAMzYc8O0JKnnoPIPw6g66c76GAQpi+/vurd6lQVfz4dzHfDz+1HfHAfJBBiM5sQp2L0w/L7
S10tRWGoaHIzMGbWoeoXs+25Nt8gGb8nXtgcNlbnXS2uztiGzcJg0/C63viBacSbgCmRgYy5hdgE
jpuP4+JZiYMUwklSpunXYFoq1nDwCZV/7UXYesZjCQ0cVv2OxSW1wtQrRQXcEWd6i6vgfQeUfS+Y
/+/qiNwVpp1jEfueChrxM69eE81DKJKdxzELoiDcARjRa2sXJp8/k/vk3igVt5CztiN7Tcj6H9QU
LzjVOOSoF/XBO5ArZEzLcpq8CVSBAv8MBdCjrh2qz9z7Fo8+sqd25mlXwljAgaSMYeLiiqO49gXo
UKDE+SIR6tuomR+s0dprqiGmKz4wxFZxDaS3IVt1rfkGo11O45oJ9p7VLOp58sDBPzNzjG6Rlbbc
JdXD7YSmJGY+oJmsGJlLTXfvcqgRlGAyu4MQo7U/PPFAvGTDSvewtHUyHyO2UyQKkAuhG4yC6h89
1EXuqdkx5C5Fojbm406c8gUYvMzhlNmWUzSK79q/XXw9+gLKm2sHdO6/ZwscS/pz7iA2f4LN2gaH
MCOF/4UUuLI8rOW318RcC2zPhe1SIIKkiJrOZoJ+x9tFs1OaF7Sc4DDYXMQ3XefVCdnKygr+KqAK
8tWHOSKFBHgUVVHgzA7I/4S1FHhoVXcDSZlCbc/QOmOSK629lxF3wCwBh9keqQOJ3zwX86JfMsX2
NgYNFw2xy5XsmWrbCfFIWLokq+GRb15YT0OP3kjKPpTqjfptIzFAdVb6m3r5afzdkmxfOP6q/1lF
/eV2nkBqTl2ettKrGuCYZnKqw27k0RssENGfc2J9SpmiUE1/ZWeEwbWgDvL3UNOQ558gzm7i1rWF
LHskmTqBJnjrHAdnW5UWI+esbgfZxTcXe6MkTAu7XxtitxQUUdDn76f9C0PCWvB0ktyjFv+T9zwS
D22Bul7Bt3PWihYKYgA9LjpYtFg0CWhfXCHB88HViuSBRpxr/+M3S/W2lvTDr6wadehb8nh3Q7FL
TQczWerFbUSK9lB+UpLrGxWsxgfsHmS8WSm/hsRMNtV0Idv97HXKmGxytwPp5c1VQqgjvr2kY3JR
eXXX+cTAdV2sZXf7EbKQqLD0SJf7k+U86f9Cy0wkcZjWM2xs49wZy4k3mrWesgLP6RhDYnQsYhTG
SrkmBrVV//8h9T1R9rtMZ8rNBr1ankA4PGiZC0TgzDdoSq+QqPp3pCeJqOSLaI1ZumgYgIOhp5ed
FzuFTDff8qUeT9e729UVBep45WRguHhF9LgbCdl5W6yR8ogpLzFTFQnQ/Sm+KDMOwTy+E+wWHPJf
9ord7iuOtLOzeY5wDE3xawVEswv2M7PoZA0HEPcBHemYwheUsivt3yrnnXff0Y9m7JKtRkeH5E81
wBA7x1ILSORZqpxNdKBbzZxY7aTyxuTanYvEneILxW2/wvia+JCefzmova2grtGAJfLLugyygqE6
cCMkUbGvcSVYvsu3HllBN9BziZEDPKorab0cgEzVOfAsAskh4Nz/Pb6S/+AH3tJKlw8vyI3qWaws
54A8a1Vk4w2e/+TLeVDmWPTLmVsHET9MfzTKRHKD78dZKIf7vgn5yXEpDyqvb/5Si5mQXnun0QQM
ZhTcz4mqJ7K2xns9aXjQGhYS4qTvC7RhSlGgPQ+TzMdJ1+9FNMtiSV5AY8sK6R2QYLMf2enl3Cqt
inic4bTS74fi+7bFpVUCG4N62xFXU1DDz2dQq2NDeETJcbcgJUm5DGaO3mu1+CcWohMlZXxlJE0P
hlQnAkeepbuJgwsS/ylJeGgbYU1v9OYDZwHYFR9lBL78p+dQ0JRLh5RXbdIKQ2BHIIhE8wgOM9gG
zge3uL1KGTMb/uYUPu92qFmIVc/imGnfMp7qmhIUk1gxkMQnK2KOIvs1oAFOlEhQDj3+OGVhTayG
NxyeYLfOJxM2k5xBQN1hshQgxxe1p4jkeRbOpJB+O5+gltTQWozUc1PIw37f3FwgFPMzXl8RtCAA
p32RX35piF1mO9Yhhdg7rq8Z6GC53Iq1+rx0ik70jFj6iQRmTcjkn1LboFs3VMXOMhcfC///hLR9
neVcPvxEwwAACJ9fmW8hYmvfZtZhBexGfMDNL2INzPs7N+ZaVD7egyoTd7hE7m4RljL7Tv/o9doN
TZqend0be1p+CCoZ7ZclmhXfs7qd6aTJzow2PwF/ZEnUsU9tN7YQQyKJRB0g9Y/iBxKhaqf/w509
dj293G19mzB1gOvmkZBzKN4OqacRNOHGl9YKOipKzudtJbXpChxD+0tpeWlmK4RxR+aHhPLx2OfW
arYnoxH/hb2+28RIqqCWHzhPkG1Xpq0251TU/UMHlzsGd31v4aiTYEnMmAnrxk6s3+YIIjSrrEsG
Rs8vNOkEYtnKL8rK5kzCpHz1OxGOAqbtICFUSaBHZkfKzPLewpBN7JvZXnyyHVjz8hfIV/Svmhug
ESo5hZl5UUcgWiff+H/9ITPiOGuXUxBaaRmTj86yFNWQk7a7nyxFoOtIvgR3IMp+HQR1aaR5y4C8
kxiS/lC0XhDGodQ0WkVsW6b+BnCOdyPqVCqKgwjDMQuf6j0ULWSiLk83R3QFhO8dtXE+M1YhyUJ5
UUILLBfBkg2fPudNebnrGkfTwgMLY6CiUgyVCJ6TNNKaeKvSebCn/KXVX/uLs+yOzfB9YOEZsXsN
a4NSPKh4JydYhodAqeteX7kS6fFy1RHWS4iRrKEmnu6gVHNxhdlfgDYDfqvdOD/bpn+X+2PXGa6e
6YaVKzw14Rjy+Vjpy/4IONCItUeKM1Ixys+uPzuDDxxZj49gawP8sQs8nMndpCmJ6dQa0+7EnZdj
ydOwO+qZBSuJlf9OKGgH4pJay/3MVAeaMkxTJPWU0Gw6r5jgrIGR9pxSKx9f7raxt0eFeGuOgH62
lXj6vKj27SylHCb9ZGvwKVITXME02j6/HgGOwcvsi4g/XnF5vUuGvIVp2aqPeHiWbed22Zh/fd6P
1b3DTp0kebosX5h5OwB6aCg5HfyfcIBvd9/ER6H2P+FRDg+xW+CiY90bN3x7E7I87Sxe3d/ueyHS
FTSIxp+s8wE9Ifn3MVX7Lr1gF/aQZ7IS86G8hxU9926jc+NedbojKswWQvRjskxCZAa8lcNlFpFl
7uv9ILERYi3oL+c5jtwkSUuTLcmHh/WqRSt8l0uF0oaczEatSnxM31/SdCa7iertoKeNvavY4Aij
eWqD/oTXug7JecbRsE4ZGRSy5949oYTqMte1ONKnj2XMQaqYiJ1hx8m7MgEi8mV8zyU+dHwQm154
b42gFpoSCJVEoZt1IhdPI273wNLwXyKq6k/eOHFw51901TePUnXMAdDToSW4Ilj3jx2R7OXqH97D
u3qiR6aGI3Q2/g6Y0SohqmnJ8pAqfYCzwvXDithF8rMRUfkdFy5/yYERs0/qMOtXsN+ui0lnLdDZ
ScYSFEm4eRYA3wyytk8wJsbEbwXxZNa4WU5QGkcsLLpTDrvR7luRwgPZnwphcemPxyjP8FvQrcgb
lqWuxc1xWlrLIu+k9UsOwJm9Q5ezC+xVYsDL4mGclU7ZY/X3Lx5ZVaemBhC5xtSt3IVQB3Edwucj
MDoLLpNQSxSX/ljHMEFKIFBk4WBHusA40YL5HaYRX3mlX6lA1mSQjWPlcBrLqEWCq47a3sQUjJ+x
vfKB9Q+uQ24q7h9zMF4EbYluQq+dwkOApW0x9meEKX5VgNPlyH7wcwhRke9LRjSPHfAogkg3OeFs
ikoRWBUFcRtvj9Iz61cpqV736zmfXSBePj66a3MzSAKPuQYEHV+ZfTQ74rJ1cRj0qG5p3DEGy2ti
vxMevMqa0KIQHpsvNN1oT+V5ApmS8EngmEuSMqyr57axHCf0pDMDDZ2wh44zs3RQNJMlsa/qJh8J
zVtTvyG9CLdtTKee3r8Jmz0ucc9MZcw9Ka0xeckNwRMPwh2ktVwPDyHXpFKW7XeJpx8w/6+CrSaD
LmRIhhRSyOzxgoyOddOjju+RoyG5eDeojC7W3WMDv7pJliX9EkPSLI6aI7zzfT0X5QQ+UXlBVS7d
1h9u1/BqX3S9iUnVRVhLiKUzrq0Q7E7JWQsMjmzRv22h9ELgMDSUEFZ5Comr6FWAoyA0ADCK0P2T
6SA30ohuhbTopDsu9VEGj65ekauD9GRPojE/wEj3PZg/1sGqg1AvWRsovSHw/dhHkn2x4ujJpKhj
weEs2Zm07iycvP1oqtbzJpjEODR8fYBXJwicxg4PQddS5RUpJEbvtPquihTaeCa+JZyTSs7sZuHW
9PtRxyfmzdSbmvHIVKFYqtTka1wVvkUHRT24PZoZTKoA220QRL9Pe0+ymZrfEWnV10NYFtO8mtJN
sgi7QHEn/MLBfrBuzqld6Hxmcg94hbK3SZk4EagYn6hWQuODE0Wysl8pQdtEyAEM2eVlJfrxQsfa
k4i/c5Wflv8+ouDZdAqLHzPZ15sbWqb9B/u5dIkUzLbT98UvsyGvYbajtvYqCpGShDzBAsKhsmOK
ZmJn/TAsFCyumAAlqT/FYz2rRcjmWRAE4a0UkWm/eoCdzNmdwxUh1D+uvhi6Cc2cgrEN5BOF0hXj
xnt0dQKalZgUxtk5cejdMkw7X2w1REgzdePkFcanSNt75heDZ9Ud4PlyCHTdxa3Wd0OwZttuZWrq
aOVkM+9GBtq9lg0UJN4itRKJ/u5nf26CJLKgCyGMqaK28EgljlhOhW73Sqf1nbsbbknnhqsTFkjD
+kdWUN21UFpJZ+4rwlOTeAJpoigLaROFcbb+BADErYD268UmAJbT+ltaFxjFRIgy6vzBZnxXuI16
l989BWyifkV3mXsIR9PFHmknH97rnHnhvRTKAv3gqWmvzCykeTbvSezFTbdm9PrYn8IzOUbb2pxb
usxTiuCZwpMiCE54h+sfhnkAfwrwhHQD+ja8scuxZ27FM8nQwzPXgBf2fTvqNOYlcYhQ1NqazKU+
KXexYKYiOyk1Xrmh8LUL4XSYRnq6IQjz2e6nY7BuHZrszWFTPdgSHg8AeCD2RydFiclNjc/7PqO7
V889Fm4HiimFtMoXcXT5rrkGIl08if+m3C3XU77NsYfCDxL6wJUL7FCF9hEWEEF5EPARZyArDqVC
sPL5cO1dhNQe/fwa1dh7zyp9CWpGBKUFvh/U4slxPxO6fAdZW2iOhyygYGQK+Iq3Up9ff2e3aIDg
7sRqpEBywoudwP6wzmf+Pnqp5A3E59LrUfzZXqI9QVbPSTM6FQM/C537XdflfcjEBfVdp19pERYj
irhuz7qqfY5IruAzo1Td74HvhU5T874S6y9q9dbcCYFxaY7xSUzErQ/ffs2S36ljy3kY0aL9aHNR
fb7ehQF4dDGkKkxdfuYo6G+J0QIu/GvNFMrYNNoR6H7HGNUgQ18db4p7O/pbOQedvxGvAHjb6tn6
SMeMw0bAJP1+VLkobCX+kT1Q6SYgzm0OPlxpbVL2yUdCtN0vU+7dydQuJFtkn49m/ABIQkO1ZxLY
+8SqKo9tAAvdnYAL+LP1cmIzgZ37lOa9Vf2wBW+pR8JexsNQJKfmWjg42yWQmyf1oIhsXkJpuZpz
eLVBykZIVMWFf3oHLYOeP8m8aVEdipPhiVKHHFlY9xtONyDA0Fz858vFoEi1GxRm2ZernVl1QCuC
ojvgIsE2Z+L5kuFQRzFSeFZMvnkzmVEwQP/nBNrQw6ISCWvKfaFi87J0BvyoHT6nne812hVE0s7Z
XC7e123ndZj6eTLUta8JR2Wevwyehk90doemcDuXvQJdijHrehOP9GAH7yHv+XBKuMAafrO12yPE
ZDKU5jth9POXBpFUflXc0LbgNM25+03/Au++wfXkdi3a5K2hCTnDDkWafM1QHv/thGXvoxwKQAx9
q8uNBVZeCGCH9+7Uod5FAKeLDs9z99wfTac09/WZMdRHTfspR/9mXlBVmncOcZ3If2xZug+Y1h0L
tTWwq2mKqPFeQsu4H7+INgr450CwjM41RrJs8B5b+BMN9mPqZmFYirzvyZNfUTvLZXFgfwRvlhl6
k5qMYxJKz9ELTuU2QPn91tpIQAIVOuL1u3g4xs/Mzz7HkTOjHmmdXd83OJv7A83ucNlyFYhlTboY
BH2aVYTDIG9Su8aNeo4096rJCv+ssjn6sfFjk2FcbLFnNtK0Wgbe2E4SyXG0jQ7xJGhyhq608TpD
Pg6ujYu906PUnemLTCImF7Zt4yYgWr/QO7hzYN1U7nm0SkpW5B+eNEFd2TN9FeEU8ZRiZUAa8q21
BWa7nAIW+03rKqSG+UJp1oQUA4a1NmBTi3QnXbXvPsQlWHJ1o29L33L+W1lnjSrPZqemDyIy2+q1
e1EP/07lGkMrmmFl+W1QqX9BklMPymr8ae2SrI+Hk+UmOMYrQVeduhMz1hL2kmgEn9eSwewANAGg
B67hgVLMCgwnFbRttKUuobr6wucF9EHMBbdEE3BKlFs+PD5fWFX/0EEgX1S0CeZ+UcjdEswMlr+V
+pik6ySprYBEsJeALtlDlvAdR6a63dgGt+ohe4dICG0bX3EOtYE6EIoIhqSiRLabAru89pQ+p5LA
U4guNAeHImdWakqe02Tx5sjvFGG1hQxxuerjYl/B55W59K8V6h5KoSeSE6hpF5Cg0u9VGcWpvNyU
IAMwc1j6ffONLSs3hfqOy37nVIIzeadv2gzg8AuecG8mmT8yzVKzhsLwAKmxPW0RfgBT/7/OCRrY
ZI0lVKo2fdFm5ktbhqcSA4H8WvSm6gPCHRVz9mFVfuRHv7fs3SDkDHXV3toUerGGYcDhO2JZcZfk
oS0pjAWdDGh+fGdPs14O7bEjgbqvcxX2XMeQ4Ie2IpKHqIxyfVunQ0Tedqkg5RsJd3tum3SwaHu6
mam6QCEATFxklDsfY5kktLbIZ9UC7xIDQGOfvJiwZh6J9Cdz2UUMrkBb7o06OPtMB8ZT4LlM15SG
dPtRtSYqTvCJO0QkkaOYXd1760b7lR6hAjZG9+6lwGsgTdhHvivUpoRB76iPme8uAEPcPKURodmM
IByetDmnojbb5S3heQba1AV0cmrm86GaSVLhGDr7yKDo2w1mLUKZGOhTYeA27pMnghBneszTOWGK
o2+qtzhVs0qwW/LWIGRP9HMgULar3lWBuDuBbwr4B0SqMzYx+qb0dhVc8VuhAcIRLrwzwj9ytuFG
cAniIq0jYcDveQQaVf7ZP94waFmkh24iKvg7yrE560Bvan64llN/TqhIpaJwUbXrn6VwL9ToDo+l
IMBRIt0ALTeDKchUuJokQkTTqRU019g3EdJTNcXk29LG9Ve1Q/IXHilLxB12rCF2HlAD1e5iyBLj
e53qAiJzXK3biYfy5uyDKzZ4skRlCJkJHSQp8gDQla8TzVGft3/ZP1lKemPt2wXUD8gFb2pmiAzS
c8VAbfVO0wag/iniXZXbGqTXjTWHxteeFaFu5TChiaoYeHQXu8a4wnm9/J/L40pqFPIdnlHUPrMq
lz1sV32Xln1JKLIfWu60LuTDFRLS6AG6EMXi32mHbGmAZs2bS9klowSpeLilCPjOx6XJAWK3oILA
2aIbhc0eep1NGerS9GVrgg/PQxRkPp5dgfzMx2Ufpi6XEl3iXblkqGSR7MM7aVWEqX61hQp639ha
Ne9MAmrHkABx6KwVRPjNxmaNuiL24DUVPvEE6uQqpbxnuY2RLqc1ayH8O8Bmv1DhNWmav55GDNpd
9OSz67VBUzkV0XqlLIyFKclnfjG1AYI2yMvd4FG6DbuvRNJtcUaEZ3buy8TgJ+ArYIiPYeZ4jqfS
tgSMkaFM2phx0KDh2O17O+QprJl4bFwOejkx5cXwq29un/RdvvZayCwZJB8I/3bDnEEuKJ4a1zDY
DBfFdhwF7WZ6csTwHle/inD+u683fvEAhdnXyBft3t5Tk2YqMc9ymrj9wDC0ULD0NckexXHMKuid
Y2wpmPswokA8vItRM7C9WBDbzauwOeLO/0rFhPJBfM/4p5gLORGnfkx83JgBhibyZpoAl88q8qZG
DweVWu2ay8V3lspYPgk6GWLMCkp5hmwzozo/icXwQ60R+TsqSh1YAkZmadoYH8R3uIVqhq1WDft2
LZ6CiLDXRhup48XAeYcpo39Ch7sp1MJ3HV9EJDK1p36vcBOrNNCPuavg2M8vYmE4jOxumxMruWfc
GsB/D5SbPv5nVH8JET2Wbniqeld4i0+1fUpIm/BYj6klHtMBQC6GhAFoCKmTSasJ0pDh4+uw/tnc
Bq8U3dm94SokX7uapCNfBfFQwJ2BpAnGZ2f1+tdwSw8sDaWZ3/SH79Z97VjJfo98oEkhYzO9lCa+
LxHLSmPNEVT/zmm571Gxi98wE9xh/58ZAh8TK/Cz6t/Y7o02j1sf0alEx8tBSCigp/Bdzhn91XYB
XE1QMKAUElDXy5xAwYuxf+Dog20SIXDMv5X515BJOGyHJFZlFgh3JQd7sPSBlF0WxEukeSYsAGZl
ovokybdnZTSzAvrrBfvinPppuRAhkHbxIiK/Rw7e2RGfmPV446Xc8iZfCFG0VnG4pNFDZsTugovk
GyjbL2ENBsuPyFpkSxH9vk/Bg0xNrRasVFYmsisGUM9olWYvg5isDgAd6nPISA8OLLtuhGfOg/Of
jMHPXgENFBbu6Bxn2Od2iqkB51suZcZ2RznurF3tizPxS4/qxC1r1M7Y/+7RAYpS44HtaaglWHRp
tn9pEXyvL1JG1buibyjKDweY0z2pnsoU0xsRr21IuvUpvUlxNfP8UH1w9+G03aB3gzC9X+IxQGza
NMpHcUZdha0J8ryCDdIS3/TPs1wD+KweSVZkxOq4Xy2W+GUdGw0nFudI07ibTMbDxSf7fvseUPz0
AFWQyqwDGjk/ApSUi5q623WMlkK41bbJE0ewy4Z0hWh8WNFBWA6/Dka6Y+inQLXODwvarP5Xljzd
SMJeZ8uprkcSJEr+3nR0GFXEFIJinFJqc2n35iqrxNVGUc51l1RjHS2pKzzHuKVa9w5Bn0rSfyRI
jMq3zkEBaV/UAIOdNEDP48wQ19qJy6VJz0S3RFojeDXiIhfjZwXvk1zdV1bbaj6e09YBOyqMdNYW
4KEry2fjRBl60jH3T21oJPPXYKZIYEvcDDkuKGNerqP5IloQP6GxjVV9gUPMwgkKodnlexBwaagk
mWUMiDrGFcFpk5cb6nYnY4dAV+fM4rvKiXc7UdI9LPrFwH+znw+i1YZgMxlFu3IJsqwByz4ljpWe
b0p3R7YygD0DlBgtXNMYAqwPGonanUEebu1iheaIvRsr5ztaRuC3EBnSdkBwmCFrHvtKP//Tn84A
ECv21mDOUFy/L24WLtekSHb0JyRYjfDsAbjqIN9HF8A0kvFZrn0+YCQmpTIQKKFz4RATGJU7IPxy
xvlOgjBx6tz4Yx1Vc/aPn7LER2TiyKY9EDYn9qgDAMfFFQF03pz+qiiBv77g3iP40kZtl/25r1t4
LVMqJWQvgxjtBjv/RkK9F3y6+reCRGXmqyDdEY5jAbf0Lf7hbsEwF7rkKCMRT3PqEqyvRAskvbzD
f8Tc3qrwZgz5/OU4DKPhnr/VLOu5NF03m/XNpRmUCUdamzwNa2+qGO4mYeNH+okliGzqbx35hiST
ziK5ju92i8nxUYzxdR1qfgKuX0L2uq549nDWQ1Gq+RWGpv4eHb01zLSeP23lTTns5GzCqwihnrXt
cJgggBwDz4NsWWjH70m9oqcZBP5jzA6ddxBPydnlUMRgDQ3KcJQ0w7L4fZUpE9iH5oX60Jov9VnT
SKpIFlw5kGs6rnBiRsA8YGzNIXUWlBZG88xAcYEKAAOpBhVioe2PesKjZzABzfUY1Zn874mPiMgg
gEgEjm2Vs04b2gwf9DC9/YgikZxbvSXHnJI0jn/VfBsp88LH0d4ntZ5kSag+TENtj3aw7Nfw7OJl
QfiKJ7G3cyS47WGZYZfSr5+pQFTsFcXr1RDgZTSc2VBIs1otKovQ0p5kmOjpulm9UDzbZUQRY2hu
jMwUOnwrOuTP4wEXm4NrtujlS1Y2pY5lWXSUWGWVREX0T77HFqhjPnUMq+/SordpJnF9cWf7P0AD
bA1kyUF0Uf/189AYY/hsS3nNq7cwawxR9ghZQ5T2IEKitChhesX+hDVq2Uq8Yp6cstJQtv5oHIz+
/M7Nu9WOglgT13TenIvJneRldfjT9msOoIcUouif/dZW/PeOAyKdFFYQgP7+Krbu2/xE63fKVtWk
VzZdfFhtxMUq7Mhpy1hlwxsKXru6vgp1GNKR8gaXf6C1zm3Wh1cvErT996s6udJgOUb8hFHEsgcM
eNdJeC00tn4cG7A1I4Z/z89w3yi8QGpV0maoHIUvDsABiFfuxHDwPBwoKMes2+6l4p1r2nKLwz1B
73/rzQ2D45wfBTYvMGSvQ6yiBpFlKDfZ0kXBFthldBJ2XlDgBGbvPZBbf3SNGV9z2DnobzoAQwkS
Jb71qomL207tdyLncecUKhkSrQHQE+CkKo/QP9ix3dhfEipcrzkNSUtl1UGLOSwhDQxrXK0OHkEU
6RRxUkHT1SVlbeh1aE6XxfjHscqp1dMlDhfvr36RSRifaheYyE8L1blY7lx5+WG76kWEB0VddWF0
WSgYLc4ZxWMyHfObhL48NF87M2tAheYb+fXFipeXFcBrIyu2ADwOdky2S4mT4ywAhy0EiJWDu4zu
VACMo4JOZZXNTDosB/TCo3g0jamP5yTGtnMoNVaJ/BRz7NS2OTPz6NWfneqbD1mBROCRcfYQvgA1
ZHjYkAYCZRFLgDwVgbKFIJDVYW5mhLuvbMHbe6hMYaRn5vv/D2qT72OIiX0FzY5C9mdCjMeHyCQh
ulQIhTSJ64DM5xfa/t7rDbcXr76CTfWI1o2xyI/LmCcaKnow6y7Oa7ebrhlkWVdM0TtPJu+i3SLR
FBHwxfnRkE+IjY4ebhqtN70mq4wz23zhia5w4nvsppea7ua6AArU6HDyt/cytBPX/CvG9/NI2P+H
J0Hme+zwYHW4ipZwIfdmhF0YeTCW6j9lKq/kJzmXIzIl+4BrxKL9EtmntuAbrFbP/8AjDZTH5qM1
eZgBYjt2J9y5XMjP8N9uLq90H55SzGtr9RCuQmIT/sjZ+9mPEdzXteopn4x9HBTW7db46Mc4NzcO
CpGhj7pQQ9F/1Xiz/1WutpkgSegCQjv83iwYmnAvnIeklD9ta4VeoDqwneQ0FooBdU/slWlM7edX
boY9L3GasPHLEnDp4bGtkCg1gc2LcESghHHCBmNMtwxgXc3+w3aOz5tl8gO3SEI2LK6NyDr0TDh+
Gj+A+u70nq1QZQb69BIIV/lqcoUHTI/SDIa7BuLrjJQtOCcEalsZELKsqlJFrI8yyPeOJyvVCXUQ
7tXxlkT9V4cF15vOvQC24xlwc2mKoLdPnJ8Ip6boWWwd2IFNn30W3i6zqitOiYE0e3r6LV6A5cF0
Wq50aqnMJpZuUw88Ps9Er1MU1dA5mD++fJWhG6HhNVV4pvow+0bcpxNnUnVxu62vgKlctTGmdDud
UE82IdV7w2xFePGk+hZJczy8k6zot1CUpsqmGKNr3yrJ1+H8pQSyAPc1TLZT77X/ZaOMz9PoJEvl
yVRqCej+h5YYAf3ejdIGWapzZ6P5xW1e8LIOzvBsV/pCL41NJs/GY68OpYxeT567rDHINzmiYTFx
GRL86Pnv8pF9YczNX64tLUG3DZAcGfzeKPq9Y8b//YXh7Ie9p1pj+ygTuvgwLTm8c8i8H3jDX7KA
+m4BBopgMGtQdSG/JgJ7yAtR6nrfYOc3Fl9RUr2DXAxJiiyhiZRdGkZ4E2twjUVXpsfEcGpQMjvh
hMhikiGIoEII0ANzURLatr0uUoM8/kj/IR5HcuVnDj2X3nUFxn0u41g1vXB1H70MKLB+5p4tA4Mw
KP9gIo+LF5IVUa6bWf0O0LcG0QA5W1gGG1ZyAYuDMRYikrTGRKll7fBoMbcDvYsWwVZDVqTn1XwE
KX0F63rINjboUSjCfW1dtCapO67kSZ2tqC8YCeQhyw3uxGXKAVQnjXa+vVD3r+edPrFhfhg5emA/
R9hUW/oZi+v4KIRqS8Wn5dEI/772VuNiuuSevUr7fdpn11LhfpA3yLQYnwTjqHZytmo5vYMl3Mca
JG6RsIIE496A06v7cb+SzuPUliEKAjOo9bjA5jsKJx7knLdyR+Uw7VFejKQMbO2/9Xbp70680NCS
6jO26ib9ixUctukngxXp8YkWcIxhe6Vg5bpVl3E+SV1d57dMLXgQ8ni4lc1G/fj52g83ZwDBYITF
BqiGII+Obnu0Rd6MECI3aeWCTTY8zOqXO2kOHaQhHIwVrGWNUpHTKne92imFDrowoIozH4DrriSB
TQVrJVK4AWanrCVBP3j6FvEY3SGfAj6f0SfuE4oP1+MaHX1KP03LMzYPPPkF9vOm48FJrzreyS5d
i1MNI249iMaVWTm5Z/pDDMUEKQm/LI8HDkd5/hVu93WeJPo5dZSU1Q7HLMP107aHu9t0FTAJqCEh
MvHWPzVzLF0sfeRYAtSl8ACXB4VAme0A48g3UEp0ZDIAcvZ+Nv7HSIee2/zX+Ob5TBopW2CviAaW
GCQtvuGv8rg+748LXM72r8FV//OeCHBz6d6y1pw9b1eHkhjMv+mE0AqSB5EK7soZaLHFqmJ17u1J
mSrCmGyV6ZRXntHUihnoEGDqEgdctPRUV4Hkg1CmcNNPySe4DKnIKC9csoTZbz2eQllPnVERtMQj
VhFHz9tXbrBo71ez6V4mE4/MYIbfsz0kfLRV6Cm0Y2W3AazPOAOSSu0qPAsq57F2r62kq0dB/bJP
8K5aWALnTKZQfRBmHpD+scax8PCVeXkeXa6rQt5UArq72n5QjUxhu58tkEIoHejNelsvaSrvr+H6
p3KeQlsneiHxgfSCdVMVfP4DMWkN54VWrBOFu912NYbsXT9dLOfs8uYdsWEN+hXj0nUd1ZGGtqVY
brLEKsSUzrYJ6j8fADgwnCYN9B8AHrlKNSNHbdvpOCXfs+hqvmZL+A8mZTQYPqyil8+siciP9/6X
shPg8Qvwx0hiqP6gIdSlQI1siUN2pAMYIM7dq53bnQ+v8Z1A6IT1XkyqBWrId5JQPOcyECUrmD+v
eFVgZ6IeDLpfTU0Q3T190LroSdtMaKjy7As0BnS6fGsljL5n4G/Oh8QPT+J+WgayuEkICYl6fk2f
d9ZsAX9YvSc+IOBlOwNF8tAaaOYpwmCG0DhyyS1XFHDDo1kCUdSN8sCE1ou/Gr6YYwzoul7pocOE
cZA7b+i0wn7sAZ6Kl+VNzApCrnGxniKeyvvMod71DYobmB5OEKh9K6m6zX504NxltIhD0gRFIC3L
X7Sm+Ip6pk0aEvkwaT07rlP7uvgkTcZ529N28VVHY+ZQMMFn+Nx8zX86MB8T3D5NMLYy01cGPKuq
m06lRmlnaZl8lQ2CuLctgmQP8nmcuS2q1q/Tg/5yXJglbr1yb7cbcdkC35XO9GJ0Jvp/DhCCTHFH
MxIEGt9+gyL+rkUIQ4Z3kJ78LHpQ+1JI0kQrHGNvyeP+sZVN9E1AdSolksLtdJFfQOAQzo3I7IHJ
IzMcXlDWu9PWCZn9iPEmcXNk25EUYVHP6f+rDkAOlwScZFayVpbhmfCkjBGqLLVYV4UTFPwhn8wa
xWdFwGGkWVBL+q+TMRGaNGRH1g+mXuzHpQeFy1maTFRBmBuTSOviWaSXrtzZh32RLraMsRf0BpOY
ViSjFnN3o1jgkc351/3AxdZOkRRA4MBgnozAkq/dohg4C42kPmDRG+troR2NG2T3EeHqYpOv0OsS
4M+g04B5E+29Me0aIs+cTlnF3naELk7UMnXEde8SUKZ+fEWtxEfiA5Ilc4Vs6/3o40S5SGHFIeqW
OKoMuo+6fR5lpQWaTxiUFfH6GGZgKwuwYX3Ys1tQueKGW6pj1u0si2vmLYCQf5NZWLrHTkkFRuAv
mhZcwWd0Yu1pYKK9Q7D6buuF/KHJjgq9L8/jqDTNC2FME2w4Pzo1h7SyF1AUnvcKcgXunt6IE2Pa
A1fGl0Jdf+CPnUhfwXyfQTxiON4InFIaNCs74D0FCuwpWlh2gO+f0a4kC5iCKbup8aNjxu41PiwY
dxKSBAHJhFZKkvt13JIp77BNBrSKfP/KWG6Opfblu+XmTYbqjYo6gAo4qPhXvgdvhlParv6gHgNd
rBZ+UhXBSpxsKLqwyJxA1zc9AjHVbSTv7inPOCdQJGxsT4t4lt2r+kqllkoDHZKoTBMM9ga3j+W7
nGqOSQo3PtRKaVF6EbO3aZrYMnDG1a5RkCkJgNfiJoWdpdGKb2gP0YkyqJ18zSN+0xe7unduoR1D
/sRaRG3ygmQhlTHowLUV2GGg4mxvQn949UjV7k7fSm5yciSU9MU4Ae3ansEtQhnWOh1Zt8DlAx3P
2Xq1JLhkRBIi5KAzzqwPq6B1if5s7Cm5Z5Ha8pYI1I2wxQ6b1VqkH/AOqLACyskFMuCGUMSdGvT5
PbzygkKFpsGvlp+Hz1opRoKO8sO9TQKss0dyxQeYOMuD2hri3lNGg2C5e932Y/cs4Vu5fKlVz8zz
Q5MFVLYSyHnFUWOs4vjuYO064mWJUvFq43ZyvPInnyxuxfk24r0m/DKDzXGrmgqURVYc0BnDA3za
TTkcw0MWrA8C22+fbcr9aWCwJP8D0n9lrzRLEb80Cjw7IEFHu92a/0MaNGcuASTiYQp316dLmtSt
nfoVBF5weheFSGIOL70Xd1TNYdEOG6rYqYt6NfUG5f1sEmfnJtAG1TJEvPF4CPHE1S4r9lQo1wz3
YZRz7pEvZy4Pt5Em27XIcJZX8gOG/BaKz5OmIXdVqm8gUAqy0dQ2SPyXe4ZzomdbBUFz7ELyujO7
oaAnqcAjtsRlCLpR+1+kDbW1igIAmE80mtUx3TutxohYWnK4H8QR70yG9cYq7IHnhZjmt8ROiOmc
FFnyPbiYc4bfNqay2WDLZdjjOK2sm4bsdo8Zpetf3tjtwAwXiuD9F3OV+HluxmSP27t90obxXv9f
omRFvzNTK3jEmeN0HR/feCRGkJTbCKGnnb4vpA7Bn3nSiEbnGNI3nLF5k6zRkVcgsX7jd5+E5vQ3
yXBD0bZtinwJSn6KGke4d6Z4ZoiNoL+jInB6MtjqsvFsEYJtbEz3ekvlWwfdZplv+NfBdnEL3r25
0Yr5mgj7qsj+a8L6TmbqTdK8tHa7t9Pz/9JUN1xjhOQ5Bi0CIiYJtabBk4Hl44ltZS5XW2kI6Z/X
lqFJ0HD1FxUq+XoIHIXUMfuZpu+uA9xUPVHn/sNLLyIXKL/c/V632POKBdqfffy4SEDEjQwyWD5j
6fZG9KMrhZKAHAU5lFvPDkRBjnEjSX1geu5JCi5mp/4qLxoOg4vkW5ZLpcDfozZxGw9S6vCX9L7M
0cPF3nP4LXzn5xBlQ9+R9iQi/AbHaxVEIxgqPK2O33Y52HpOFGVQ/nHuyl8dUv9+Mtwm8KI70k1n
i2bbCk6j6AFlvyxGnXDaCYWpwAzcVvz2nqJLADYFmYtXRaTaTqcbUoS5Uw3zwILVysV4K3+z08v5
aeNJVZcC3KXIhlyK05kP39LDfQ4JsKwHfywUTeqfKwpcD/7lQ55IFb5Ah0s85eB40z5S0kobr50L
B3DFjirH5qG4cmrpcfNIy7H6hNwED/UYt74tXZ64yHOWCiX2Dp4hHqXKaIDBiEvJHvlt99vJEmZB
xsFUg8pSDCHZ6cEft5uocndZmO9HTWrKHuvYuUkmmnw4d79kGu/bRjFFxmD5/cH/Z6u3HHftOAKT
90B4IV6FeSFJtyoD/TwT+X9RaFZk2KMn9qWEyGz3JsoQzgJ884rd+tCJDps9+Nk4VRQkUnaWIZ1I
V/IQ8jHHNm546VdsYIz1PrRt2DEzx+0/Sn3UUwlhD39RTQ/IAc9M7znA9+5tz6cXomG5wgkQv1SD
KUCSd/Db9hnm+C+E57VJboynZezy2Kgb2G2VM91CXgSYM/aXrTPJaqPx6+WGTBB3Ph7ttsNJNONM
iKHSEfhRTjmwSLFi6nTYcMIGiUTD7/1Eoiz5KCUXdVelZZl2vALBjtGYpxtuMS25EWu7shOaP82P
2CdveVm+Wx0tmBl+UKQG/yfk1FNwMQpq2dcK4Tfr3cMjSdKj2YG7zOCwc4pozXWI7lz0TCCRKZXG
/7sD4QI9gSaE1XjNEItyMd6LjpU9PVOCffpkSD2FPQbeNPWoP0lA7FvDlA3TnXa9LEH2+Ml6WofO
ew9zfa98GQvFBUykUr8vAf+35CATo7E3oPsT7y+FAfoaUqvBZ/saTcO4/Do6AxdR8fjGN60Oz94W
TJ3W3C8B/e0DnE9jn2hfXpf67qzfapnztI0V5QbzmuyrEJqkOqwu6gSjGqOezdzXHA7UrUyygwu5
SJ6mrxfeB3hp01Tfa33+WSLl7YqFV6RRWsrS4ug/oWP5mqN6J3niz45HX9HXIkW5Bw7kEwwgYqvs
PdsJITLDj2eOk0mwryPaIJlnlPUBs8jKxPJQuSRbZ5i29Go0ArnkG/86BaBxmlAVCZ1niOkAmT8X
48wLSY6G7O9Yqb6FOoz+b8tS1WdFkx6Oz7pxwLKnelEHwy3AZtKxKqfDuCd5KgGul+3w24+7h5Y6
N+4nesuzCQM2tzdIxCVaTGj3IU7MT6CKBgBbBFl5pC44KxIFXbl9iWpViGmgQnG9J6cNJrSNRWOf
GWziuj7MmYplLEVRr54RKSz5hYhFz8Uig+Hv98GUFYA4ubIf8Sfh1vDzVgj7AfJeJaCrZriwPTgZ
Ga4Mqfk/f22RvjTszpW+pyAtTleV5VagnkQS5S8pepwKuhQKSt7Iv7RwA4rCNDfYZ24evx0z2EtI
63q/Iz1FeFP6i2Z0NlHkuvYixrfKqmgUdWPxN7Cu1xIed1G0cAxrVfiL+wUxS775LC0rybtaP+eN
EihrdGUHmI6w+E08oBEunAUisNuN2jE/XSw8r7BIH4J8JgZGCp/fBQ9vWTe+nI1j92897Cd0b+7I
pj0ksYWLYkFIEHzn1s4IpKrKtwY1tM1W/M/7Rhycy8QyRtIRRo7UpHmSNOovNEbljLCgv1IiR/cO
GP3KZu8LK1fFWWL28LLvVXpTN7KDIC07/Pz1yIEVXTrjaXwinVVBsyjvBOdDek0EPXdbNrbQlIQU
SvJi7Sr/TOD0ARdd62bD9wLWl/foZbrMHQUsUF114MA2qdVT/0Pidysn5vMbzJ1SeovyLwPlCnZE
tx8XkrG9qZ6mm9FG6CjYSuZgHcQijar56TUnA7c0dTsjOSV52bqfAbodsRn0lyk197lPrWsCajXt
ATcfISyxBv0oa/No/YWbF/lj7X+U3QEHZ2LkY5CYXHkP6/mGEahkVWVvyUCXCEYkLtTyC/dVx+lA
cFQo0ItSFBqbFAZY3lMm5/kLxJIJ///v96J/jNijidnrlcu8+SeGKMIxkfCgVTGHyZ4eMETupGGy
6QesywvxnHjJl+A2VQmcCmgH7XHbmNa2GH1jBn/EKs+ONxkGjJg9V082XHodrV+w2y+vFuUKGWIM
efwFsFIbNDUnJRhPbwusEqdrTugXsVYZDLsT9ahXGY35w1W5tx35iPwbjjyqsGhDiexjLt9zegDk
usiRE07SM+VIvWRGKEfBnBK10irUV3D/2QbQ6x/Jr2abDxfvyItcrvgvj7yukDKw7W1V7mw25yZd
cOB0ttqGu+j0V1AAaH6LaGGxD7PTsabR0ZKUzdhLI6Kacgur6nSKDIPdx3Wjfm+bQxaP0Drlrn8P
6bT3dWDdfQp9TabwwUimQNB4jxD9wVJTkOobIbW78r4l7jLqwrrhiAmdGirwMxATlUlkAUPbTrqw
5Ox4fE3k4Dw4+mYJnflsCqJmCSvEfrdO3XswRRQbIauYhWCZ0mtbwSmyVwhed2M8OSLZPVSfAT9O
2+UZUGlJaXWgBxfUJpqFNMEj/9bZ3wHEXLVZfOf5PKobkucGTpefFgDJVaohqv9DmMbDZGwDJb2I
PDsl+m//XMufrvgm9z6ccU83lnh8akFkPrOFNS1lPhJqWUaGqrTPv5bJzKyHGnRg7XiY+mi1V90Z
vOKAsiyYbkokAnxd2MF7aZen/pPGvaF5dHYRnrTCo4qN1p4uz8e20SP7dS2Q5SmgbHaciCbRKIcG
xjSMTCpRI8SVs4lvUjV+lNfzWCjL6AAmgKsvjWVQsJhHjsU0ooPWdkhXq6E2H/cjjPpeaAtWX3OP
SVJrjbOFq9T1aA5wapp/yRnSBGqvi4HufCcU0+I1JmUs1PLqrweabeNZko2ZeV1nCpyn8KF09Jgv
7EbY+9Kn6zaS0Ke6PbxKXiY5xGkh6mpZqIN4t3tfHdAVTmW3oNx5ttR1JpkufbmdUO5g1VLo9dwJ
72KcmxQj9w1v7v0h5ilqNqqTmMZQjODRicRqdOZij63mJqDkZHl5dSrO2IAjuevhZSvHI46k1226
AjuQu8rKRf6oPIS0FhQ4c2l6klVPQ82QImnKLnlZgT+LwJT6v4g+SzLFptnkJgiCrNn5SVrfJjSM
TJZncV7TaE+u8jgwx1LBTf8phVlEyTmUdF60/nfpnqWoV/aoBnIxFUCYOYXsWJ33n8cyH41mi5kV
uHrDBZwuoiLT9zn01O0whaO3LwqaZGC/LiXhin/kKSm/utcCuCy0x84cESkMiE4K6c9STU0SFqqm
XmYLroaBjCdzt13My9UgT47hnnumKvvJPn/oE9cTrh/P+pCR1E3b2Qr6MHUnuhqXKZW7uy0HPEK+
dmbsqM//3qd75rI762k+uTKQrBqgXk7AaKjmSY75vWhfA2FyIOJU8YNyV3p1FrfTwIPAXiPWcgNv
jIVE+rsz7ODpExz4+bS/cf7oz93YT9hbKJpEhTFaTHCPSFMS8RvonXMNfM/WZd5sYUwLyvNTEl44
HIONdo8UyaLeKvYnnG2ni2lpkNbJrilj0+AcurY0PCoYQ+GsUkZfRstz8lJSGiB22WGp3uzj2IoN
Pxng60rgLERg5zw0w+jvQW3KIp8zE9As6s5JZXpAjFstMBscv4D15aKXH4mHJyAmyXQHlB9IljNb
k41iX3+ly77mnU785T5XINrsKT4xjay6l2+SqyNCe/s8lX1ZjXoHSebXonh5p9dNCleQPFZU5ELb
Kjxe/C6mWH1PBeYtX/mZ53sCBM8WlOQ5yAXWJi2oFickWPNDjvH9as48zdj2pQI+7PS/LmbwyDk1
khURYfjEc3jc0ckWYcKiLx3nA31yhslL1RXtu4dIAuqkPL75kOSnZI6oQeLfVGfcxHaOoshKI60p
Hujmq+AXOo4HIfUpA/H7MQccz862e6uZMrqQeggTHJBC8f7GkJRPgD33xLAM/F6xiyCOUYKQaKKZ
anVYdBGKHQKNNxHTEX2UvZBJeaw1XGvyT1udW889as4wA3WAED4RKS6b+VJsVFUMmtgBz/Hfkg/v
VFh4e8byv9RayUb3aJHLTDMgYnyMM+1l4Rf9jiEYA9cf+2trsyDtNPn+I/lq6vvv96/jwlOnytEs
csSSOgsBEseSF78B6WGb1o3zvkj3YqKnBseis1j5WtuAUad9Gs4EHqMt3xUrMTwYZu9u2vRKBXRV
06k4q4LvO2E1MGBVYBvxiu94xtG/2zuO8MYr3BCbiSktqcTHAxKYuF3JUM6mKv+91vJ29W5cW0NT
rAXKpqXn5WFrtazTbw1GHJ0r4rjMIj9Sgat04yWRqYuPV9UAZQArOLgq1egnQlfRUQH2XGQ/K7Dd
u5Wz6b5YFhSdM+AT908VXaasdpyGAEeX3nisp0VEog1VZn+VBjEO3z6MCJS+4q32C4F91ipEkxvh
mBUBgPEBUuYqOG6RcsmjbYWShe7C1xY5qNlqp8Pv6+u7FWEElIe1NnSjFRsHayncavqUFEHKqjvi
GxdzQOzeo7hc43hnOjLoi7gWNBbd4IFVH6k7Xx2sHDG2hJ5aUT5FWPV75CfLBC0gLe+Wo7xGpZaM
+3/sMKs597Ahrh5JdpDwJFlSl5ttSXruqh7siUxJ8p1dhr2HV/ZnAjJsdHl3vHBZ/m6cTlvOuLnI
KbLIdO/0I9dgVLOsr5MnRSDb/SUfhOgU3YAAO+xz64An/LGFYQO+zQUhFbuufd8XgC4NTeRCFDFC
yNBUVt0KOVL5m26ywY/VHiL1M8RZHTYxi2WIwssumJG3ccPOveo8QS2tUsnb8KOPsMrv6erQnzdb
GQkr7B8GKlCJR3uzIiQUc3eImUxjdHM9j6yQ8iaVjfKC6kPHkwcnvnLGDqWPjaOyDzeNMLFgLiWY
18pR67M43lj/ygvqniAX0WhDpJf715nEiCHivg1WkmFrXKtTXVkmR0n9KMz6i8VeLTEtzYFDRHpA
ugj7vy6lG6DPIsEVr40lhng0SL2cfpUXU2EgsNK1bS9B4nR8qXgQY3f1xSFHInzCp249Ld8BLWd4
ybaGtFbXRqlW35KPNFxPvRaD/1+G07e4JYA4J/N2jN9lBPM74nbdG52OMG+OIHLv6LpycdPLRRT8
gUPFk3uaFyqIc6SX+ZbmjSVgBAj/NhMK0JVcjFubOtfab254DWIt8xjXe4wYyBUCLqiluhaTbH0S
Uc6qxON3YE3jae7pTtzqF0vnFyRhFnkQm1A86KEMjNOB50Ylj1V7VIOn+ilvVW6UD5IPvfmdN/aK
N2vxYDoYRTSxGqpVJ9M46YkOao67JFv5d/NF08C3WL+BOOWJp14uLqpjBMJ1h34DyNL+VUrpO+Gu
OmISyarE+IPQmMEqyirR/OhtoyVLLXA6eRtboA8I5ji8F6FfX7fmhvk=
`protect end_protected
| bsd-2-clause | f65d772d3c47bc57b85e9ce00cc6b357 | 0.951435 | 1.822614 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/sim_gnss/asic_top.vhd | 1 | 15,310 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
-- "Virtual" memory banks
use techmap.types_mem.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity asic_top is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! SPI Flash/ext OTP
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
-- OTP power
io_otp_gnd : inout std_logic;
io_otp_vdd : inout std_logic;
io_otp_vdd18 : inout std_logic;
io_otp_upp : inout std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end asic_top;
architecture arch_asic_top of asic_top is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ob_pwm : std_logic_vector(1 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
signal ib_flash_si : std_logic;
signal ob_flash_so : std_logic;
signal ob_flash_sck : std_logic;
signal ob_flash_csn : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal ib_clk_adc : std_logic;
signal ib_gps_I : std_logic_vector(1 downto 0);
signal ib_gps_Q : std_logic_vector(1 downto 0);
signal ib_glo_I : std_logic_vector(1 downto 0);
signal ib_glo_Q : std_logic_vector(1 downto 0);
signal ob_pps : std_logic;
signal ib_gps_ld : std_logic;
signal ib_glo_ld : std_logic;
signal ob_max_sclk : std_logic;
signal ob_max_sdata : std_logic;
signal ob_max_ncs : std_logic_vector(1 downto 0);
signal ib_antext_stat : std_logic;
signal ib_antext_detect : std_logic;
signal ob_antext_ena : std_logic;
signal ob_antint_contr : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal wb_otp_wdata : std_logic_vector(15 downto 0);
signal wb_otp_addr : std_logic_vector(11 downto 0);
signal w_otp_we : std_logic;
signal w_otp_re : std_logic;
signal wb_otp_rdata : std_logic_vector(15 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
iflshsi : ibuf_tech generic map(CFG_PADTECH) port map (ib_flash_si, i_flash_si);
oflshso : obuf_tech generic map(CFG_PADTECH) port map (o_flash_so, ob_flash_so);
oflshsck : obuf_tech generic map(CFG_PADTECH) port map (o_flash_sck, ob_flash_sck);
oflshcsn : obuf_tech generic map(CFG_PADTECH) port map (o_flash_csn, ob_flash_csn);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
pwmx : for i in 0 to 1 generate
opwm0 : obuf_tech generic map(CFG_PADTECH) port map (o_pwm(i), ob_pwm(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! GNSS sub-system
iclkadc0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
adcx : for i in 0 to 1 generate
igpsi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_I(i), i_gps_I(i));
igpsq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_Q(i), i_gps_Q(i));
igloi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_I(i), i_glo_I(i));
igloq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_Q(i), i_glo_Q(i));
end generate;
opps0 : obuf_tech generic map(CFG_PADTECH) port map (o_pps, ob_pps);
igpsld0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_ld, i_gps_ld);
iglold0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_ld, i_glo_ld);
omaxclk0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sclk, ob_max_sclk);
omaxdat0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sdata, ob_max_sdata);
omaxcs0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(0), ob_max_ncs(0));
omaxcs1 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(1), ob_max_ncs(1));
iantstat0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_stat, i_antext_stat);
iantdet0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_detect, i_antext_detect);
oanten0 : obuf_tech generic map(CFG_PADTECH) port map (o_antext_ena, ob_antext_ena);
oantctr0 : obuf_tech generic map(CFG_PADTECH) port map (o_antint_contr, ob_antint_contr);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
otp0 : otp_tech generic map (
memtech => CFG_MEMTECH
) port map (
clk => w_clk_bus, -- only for FPGA
i_we => w_otp_we,
i_re => w_otp_re,
i_addr => wb_otp_addr,
i_wdata => wb_otp_wdata,
o_rdata => wb_otp_rdata,
io_gnd => io_otp_gnd,
io_vdd => io_otp_vdd,
io_vdd18 => io_otp_vdd18,
io_upp => io_otp_upp
);
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GPTimers
o_pwm => ob_pwm,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => ib_flash_si,
o_flash_so => ob_flash_so,
o_flash_sck => ob_flash_sck,
o_flash_csn => ob_flash_csn,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => wb_otp_rdata,
o_otp_d => wb_otp_wdata,
o_otp_a => wb_otp_addr,
o_otp_we => w_otp_we,
o_otp_re => w_otp_re,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => ib_clk_adc,
i_gps_I => ib_gps_I,
i_gps_Q => ib_gps_Q,
i_glo_I => ib_glo_I,
i_glo_Q => ib_glo_Q,
o_pps => ob_pps,
i_gps_ld => ib_gps_ld,
i_glo_ld => ib_glo_ld,
o_max_sclk => ob_max_sclk,
o_max_sdata => ob_max_sdata,
o_max_ncs => ob_max_ncs,
i_antext_stat => ib_antext_stat,
i_antext_detect => ib_antext_detect,
o_antext_ena => ob_antext_ena,
o_antint_contr => ob_antint_contr
);
end arch_asic_top;
| apache-2.0 | c3a0feaa8e5ef8afed741b886c2c9f44 | 0.624363 | 2.775562 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/cache/lrunway.vhd | 1 | 4,499 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity lrunway is generic (
abits : integer; -- cache bus address bus (usually 6..8)
waybits : integer -- Number of ways bitwidth (=2 for 4-ways cache)
);
port (
i_clk : in std_logic;
i_init : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
i_waddr : in std_logic_vector(abits-1 downto 0);
i_up : in std_logic;
i_down : in std_logic;
i_lru : in std_logic_vector(waybits-1 downto 0);
o_lru : out std_logic_vector(waybits-1 downto 0)
);
end;
architecture arch_lrunway of lrunway is
constant LINES_TOTAL : integer := 2**abits;
constant WAYS_TOTAL : integer := 2**waybits;
constant LINE_WIDTH : integer := WAYS_TOTAL * waybits;
type array_type is array (0 to LINES_TOTAL-1) of std_logic_vector(LINE_WIDTH-1 downto 0);
signal tbl : array_type;
signal radr : std_logic_vector(abits-1 downto 0);
signal wb_tbl_rdata : std_logic_vector(LINE_WIDTH-1 downto 0);
signal wb_tbl_wdata : std_logic_vector(LINE_WIDTH-1 downto 0);
signal w_we : std_logic;
begin
comb : process(i_init, i_up, i_down, i_lru, wb_tbl_rdata, radr)
variable vb_tbl_wdata_init : std_logic_vector(LINE_WIDTH-1 downto 0);
variable vb_tbl_wdata_up : std_logic_vector(LINE_WIDTH-1 downto 0);
variable vb_tbl_wdata_down : std_logic_vector(LINE_WIDTH-1 downto 0);
variable vb_tbl_wdata : std_logic_vector(LINE_WIDTH-1 downto 0);
variable v_we : std_logic;
variable shift_ena_up : std_logic;
variable shift_ena_down : std_logic;
begin
v_we := i_up or i_down or i_init;
-- init table value
for i in 0 to WAYS_TOTAL-1 loop
vb_tbl_wdata_init((i+1)*waybits-1 downto i*waybits) := conv_std_logic_vector(i, waybits);
end loop;
-- LRU next value, last used goes on top
shift_ena_up := '0';
vb_tbl_wdata_up := wb_tbl_rdata;
if wb_tbl_rdata(LINE_WIDTH-1 downto LINE_WIDTH-waybits) /= i_lru then
vb_tbl_wdata_up(LINE_WIDTH-1 downto LINE_WIDTH-waybits) := i_lru;
shift_ena_up := '1';
for i in WAYS_TOTAL-2 downto 0 loop
if shift_ena_up = '1' then
vb_tbl_wdata_up((i+1)*waybits-1 downto i*waybits) :=
wb_tbl_rdata((i+2)*waybits-1 downto (i+1)*waybits);
if wb_tbl_rdata((i+1)*waybits-1 downto i*waybits) = i_lru then
shift_ena_up := '0';
end if;
end if;
end loop;
end if;
-- LRU next value when invalidate, marked as 'invalid' goes down
shift_ena_down := '0';
vb_tbl_wdata_down := wb_tbl_rdata;
if wb_tbl_rdata(waybits-1 downto 0) /= i_lru then
vb_tbl_wdata_down(waybits-1 downto 0) := i_lru;
shift_ena_down := '1';
for i in 1 to WAYS_TOTAL-1 loop
if shift_ena_down = '1' then
vb_tbl_wdata_down((i+1)*waybits-1 downto i*waybits) :=
wb_tbl_rdata(i*waybits-1 downto (i-1)*waybits);
if wb_tbl_rdata((i+1)*waybits-1 downto i*waybits) = i_lru then
shift_ena_down := '0';
end if;
end if;
end loop;
end if;
if i_init = '1' then
vb_tbl_wdata := vb_tbl_wdata_init;
elsif i_up = '1' then
vb_tbl_wdata := vb_tbl_wdata_up;
elsif i_down = '1' then
vb_tbl_wdata := vb_tbl_wdata_down;
else
vb_tbl_wdata := (others => '0');
end if;
w_we <= v_we;
wb_tbl_wdata <= vb_tbl_wdata;
end process;
wb_tbl_rdata <= tbl(conv_integer(radr));
o_lru <= wb_tbl_rdata(waybits-1 downto 0);
reg : process (i_clk) begin
if rising_edge(i_clk) then
radr <= i_raddr;
if w_we = '1' then
tbl(conv_integer(i_waddr)) <= wb_tbl_wdata;
end if;
end if;
end process;
end;
| apache-2.0 | 2cadef37846dcef492c750a544dbda36 | 0.610136 | 3.16831 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd | 1 | 21,804 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_5;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_10.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_10.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_10.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| mit | e5412835a52a0145db0d2b95b0f533a9 | 0.439048 | 4.352096 | false | false | false | false |
szanni/aeshw | aes-core/counter.vhd | 1 | 1,712 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:57:31 07/13/2014
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
port(
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
d_out : out byte;
x : out std_logic -- boolean indicating if the tenth round is reached (d_out = 'A')
);
end counter;
architecture Behavioral of counter is
signal reg_D, reg_Q : byte;
begin
mux_3_1 : process(y, reg_Q)
begin
case y is
when "00" => reg_D <= (others => '0');
when "01" => reg_D <= reg_Q + 1;
when others => reg_D <= reg_Q;
end case;
end process mux_3_1;
reg : process (reset, clk, reg_D)
begin
if reset = '1' then
reg_Q <= (others => '0');
elsif rising_edge(clk) then
reg_Q <= reg_D;
end if;
end process reg;
comp : process (reg_Q)
begin
if reg_Q = x"0A" then
x <= '1';
else
x <= '0';
end if;
end process comp;
d_out <= reg_Q;
end Behavioral;
| bsd-2-clause | ab9d35471d04477b658c591023af380f | 0.568925 | 3.16451 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_TELEGRAM_FILTER_SD1/CTRL_TELEGRAM_FILTER_SD1_VHDL.vhd | 4 | 6,302 | -- CTRL_TELEGRAM_FILTER_SD1
-- Profibus Telegramtyp SD1 ermitteln und Bytes ausgeben, alternativ alle Bytes durchlassen
-- Ersteller: Martin Harndt
-- Erstellt: 23.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 23.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_FILTER_SD1_VHDL is
Port (BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
FILTER_ON : in std_logic; --Eingangsvariable, Filter einschalten
PARITY_OK : in std_logic; --Eingangsvariable, Parität i.O.
FILTER_BYTE_OUT : out std_logic_vector (7 downto 0);--Ausgangsvariable, gefilterte Telegramme
SEND_OUT : out std_logic; --Ausgangsvariable, Byte senden
T_CMPLT: out std_logic; --Ausgangsvariable, Telegramm komplett
DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_FILTER_SD1_VHDL;
architecture Behavioral of CTRL_TELEGRAM_FILTER_SD1_VHDL is
type TYPE_STATE is
(ST_FI_00, --Zustaende TELEGRAM_CHECK
ST_FI_01,
ST_FI_02,
ST_FI_03);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit
signal n_COUNT : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_FI_00;
COUNT_M <= x"00";
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_FI_00;
COUNT <= x"00";
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_FILTER_PROC:process (FILTER_ON, PARITY_OK, BYTE_IN, SV, COUNT) --Telegramm SD1 Filtern und ausgeben
begin
case SV is
when ST_FI_00 =>
if (FILTER_ON = '1')
then
--FI02
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= COUNT;
n_SV <= ST_FI_01;
else
--FI01
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_01 =>
if (PARITY_OK = '1' AND BYTE_IN = x"10")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_02;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_02 =>
if (PARITY_OK = '1')
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_03;
else
--FI02
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= COUNT;
n_SV <= ST_FI_02;
end if;
when ST_FI_03 =>
if (COUNT = x"06")
then
--FI04
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '1';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= COUNT;
n_SV <= ST_FI_02;
end if;
when others =>
-- FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--anktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT ='0') --Original
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
else --Telegrammzaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
end if;
end process;
end Behavioral;
| gpl-2.0 | 8b811cbfa1f7470251bd97813a406b5e | 0.559188 | 2.965647 | false | false | false | false |
szanni/aeshw | aes-core/aes_module_tb.vhd | 1 | 5,087 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:06:23 07/21/2014
-- Design Name:
-- Module Name: /home/qfi/Documents/aeshw/aes-core/aes-core/aes_module_tb.vhd
-- Project Name: aes-core
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: aes_module
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY aes_module_tb IS
END aes_module_tb;
ARCHITECTURE behavior OF aes_module_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT aes_module
PORT(
clk : IN std_logic;
reset : IN std_logic;
din : IN std_logic_vector(127 downto 0);
dout : OUT std_logic_vector(127 downto 0);
mode : IN aes_mode;
aes_start : IN std_logic;
aes_done : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal din : std_logic_vector(127 downto 0) := (others => '0');
signal mode : aes_mode := ENCRYPT;
signal aes_start : std_logic := '0';
--Outputs
signal dout : std_logic_vector(127 downto 0);
signal aes_done : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: aes_module PORT MAP (
clk => clk,
reset => reset,
din => din,
dout => dout,
mode => mode,
aes_start => aes_start,
aes_done => aes_done
);
-- Clock process definitions
clk_process :process
begin
for i in 0 to 50 loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
end process;
stim_proc: process
begin
-- key expansion
mode <= EXPAND_KEY;
din <= x"000102030405060708090a0b0c0d0e0f";
aes_start <= '1';
wait for clk_period;
assert aes_done = '0' report "key expansion : wrong done signal" severity failure;
wait for clk_period*11;
assert aes_done = '0' report "key expansion : wrong done signal" severity failure;
wait for clk_period;
assert aes_done = '1' report "key expansion : wrong done signal" severity failure;
aes_start <= '0';
wait for clk_period;
assert aes_done = '1' report "key expansion : wrong done signal" severity failure;
-- encryption (first time)
mode <= ENCRYPT;
din <= x"00112233445566778899aabbccddeeff";
aes_start <= '1';
wait for clk_period;
assert aes_done = '0' report "encryption : wrong done signal" severity failure;
wait for clk_period*12;
assert aes_done = '0' report "encryption : wrong done signal" severity failure;
wait for clk_period;
assert aes_done = '1' report "encryption : wrong done signal" severity failure;
assert dout = x"69c4e0d86a7b0430d8cdb78070b4c55a" report "encryption : wrong result" severity failure;
aes_start <= '0';
-- idle (hold previous result)
wait for clk_period*10;
assert aes_done = '1' report "idle: failure" severity failure;
assert dout = x"69c4e0d86a7b0430d8cdb78070b4c55a" report "idle: wrong result" severity failure;
-- encryption (second time)
mode <= ENCRYPT;
din <= x"00112233445566778899aabbccddeeff";
aes_start <= '1';
wait for clk_period;
assert aes_done = '0' report "encryption : wrong done signal" severity failure;
wait for clk_period*12;
assert aes_done = '0' report "encryption : wrong done signal" severity failure;
wait for clk_period;
assert aes_done = '1' report "encryption : wrong done signal" severity failure;
assert dout = x"69c4e0d86a7b0430d8cdb78070b4c55a" report "encryption module: wrong result" severity failure;
aes_start <= '0';
-- decryption (first time)
mode <= DECRYPT;
din <= x"69c4e0d86a7b0430d8cdb78070b4c55a";
aes_start <= '1';
wait for clk_period;
assert aes_done = '0' report "decryption : wrong done signal" severity failure;
wait for clk_period*12;
assert aes_done = '0' report "decryption : wrong done signal" severity failure;
wait for clk_period;
assert aes_done = '1' report "decryption : wrong done signal" severity failure;
assert dout = x"00112233445566778899aabbccddeeff" report "decryption : wrong result" severity failure;
aes_start <= '0';
wait;
end process;
END;
| bsd-2-clause | b75bc6d105bac8788cc6e6678780f056 | 0.63908 | 3.520415 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_sm.vhd | 1 | 47,596 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_sm.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_sg_ftch_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
updt_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_sg_idle : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
ch1_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_sg_idle : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
-- DataMover Status --
ftch_done : in std_logic ; --
ftch_error : in std_logic ; --
ftch_interr : in std_logic ; --
ftch_slverr : in std_logic ; --
ftch_decerr : in std_logic ; --
ftch_stale_desc : in std_logic ; --
ftch_error_early : in std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Type
constant FETCH_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant FETCH_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- Required width in bits for C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
--
---- Vector version of C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
signal fetch_tag : std_logic_vector(3 downto 0) := (others => '0');
type SG_FTCH_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
FETCH_STATUS,
FETCH_ERROR
);
signal ftch_cs : SG_FTCH_STATE_TYPE;
signal ftch_ns : SG_FTCH_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_ftch_sm_idle : std_logic := '0';
signal ch2_ftch_sm_idle : std_logic := '0';
signal ch1_pause_fetch : std_logic := '0';
signal ch2_pause_fetch : std_logic := '0';
signal ch2_pause_fetch1 : std_logic := '0';
signal ch2_pause_fetch2 : std_logic := '0';
signal ch2_pause_fetch3 : std_logic := '0';
signal ch2_updt_done1 : std_logic := '0';
signal ch2_updt_done2 : std_logic := '0';
-- Misc Signals
signal fetch_cmd_addr : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal fetch_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal ch1_stale_descriptor : std_logic := '0';
signal ch2_stale_descriptor : std_logic := '0';
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- counts for keeping track of queue descriptors to prevent
-- fifo fill
--signal ch1_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--signal ch2_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_ftch_active <= ch1_active_i;
ch2_ftch_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_FTCH_MACHINE : process(ftch_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ftch_error,
ftch_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_ftch_sm_idle <= '0';
ch2_ftch_sm_idle <= '0';
ftch_ns <= ftch_cs;
case ftch_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_ftch_sm_idle <= not service_ch1;
ch2_ftch_sm_idle <= not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
else
ftch_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
else
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_STATUS =>
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
elsif(ftch_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, fetch descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 2 still ready then fetch
-- another descriptor for channel 2
elsif(service_ch2 = '1')then
ch1_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, fetch descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 1 still ready then fetch
-- another descriptor for channel 1
elsif(service_ch1 = '1')then
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_ERROR =>
ch1_ftch_sm_idle <= '1';
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
ftch_ns <= IDLE;
-- coverage on
end case;
end process SG_FTCH_MACHINE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cs <= IDLE;
else
ftch_cs <= ftch_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH1_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
--elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch1_ftch_interr_set_i = '1')then
ch1_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch1_sg_idle = '0')then
ch1_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then
ch1_ftch_idle <= '1';
end if;
end if;
end process CH1_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then
ch1_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then
ch1_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH1_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch1_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-- begin
--
-- desc_queued_incr <= '1' when ch1_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch1_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1'
-- and not (ch1_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_pause_fetch <= '0';
-- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch1_pause_fetch <= '1';
-- else
-- ch1_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
--
--
ch1_pause_fetch <= ch1_ftch_pause;
end generate GEN_CH1_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running
and ch1_sg_idle = '0' -- SG Engine running
and ch1_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch1_stale_descriptor = '0' -- No Stale Descriptors
and ch1_desc_flush = '0' -- Not flushing desc
and ch1_pause_fetch = '0' -- Not pausing
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch1_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then
ch1_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_slverr_set <= '0';
elsif(ch1_active_i = '1' and ftch_slverr = '1')then
ch1_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_decerr_set <= '0';
elsif(ch1_active_i = '1' and ftch_decerr = '1')then
ch1_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH1_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch1_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then
ch1_stale_descriptor <= '1';
end if;
end if;
end process CH1_STALE_DESC;
end generate GEN_CH1_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate
begin
ch1_stale_descriptor <= '0';
end generate GEN_CH1_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch1_ftch_stale_desc <= ch1_stale_descriptor;
end generate GEN_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_ftch_idle <= '0';
ch1_ftch_interr_set <= '0';
ch1_ftch_slverr_set <= '0';
ch1_ftch_decerr_set <= '0';
ch1_ftch_err_early <= '0';
ch1_ftch_stale_desc <= '0';
end generate GEN_NO_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH2_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
-- elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch2_ftch_interr_set_i = '1')then
ch2_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch2_sg_idle = '0')then
ch2_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then
ch2_ftch_idle <= '1';
end if;
end if;
end process CH2_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then
ch2_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then
ch2_pause_fetch <= '1';
end if;
ch2_pause_fetch1 <= ch2_pause_fetch;
ch2_pause_fetch2 <= ch2_pause_fetch1;
ch2_pause_fetch3 <= ch2_pause_fetch2;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH2_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch2_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--
-- begin
--
-- desc_queued_incr <= '1' when ch2_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch2_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1'
-- and not (ch2_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_pause_fetch <= '0';
-- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch2_pause_fetch <= '1';
-- else
-- ch2_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
ch2_pause_fetch <= ch2_ftch_pause;
end generate GEN_CH2_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
MCDMA : if (C_ENABLE_MULTI_CHANNEL = 1) generate
NOQUEUE : if (C_SG_FTCH_DESC2QUEUE = 0) generate
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch3 = '0' -- No fetch pause
else '0';
end generate NOQUEUE;
QUEUE : if (C_SG_FTCH_DESC2QUEUE /= 0) generate
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
end generate QUEUE;
end generate MCDMA;
NO_MCDMA : if (C_ENABLE_MULTI_CHANNEL = 0) generate
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
end generate NO_MCDMA;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch2_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then
ch2_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_slverr_set <= '0';
elsif(ch2_active_i = '1' and ftch_slverr = '1')then
ch2_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_decerr_set <= '0';
elsif(ch2_active_i = '1' and ftch_decerr = '1')then
ch2_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH2_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch2_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then
ch2_stale_descriptor <= '1';
end if;
end if;
end process CH2_STALE_DESC;
end generate GEN_CH2_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ch2_stale_descriptor <= '0';
end generate GEN_CH2_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch2_ftch_stale_desc <= ch2_stale_descriptor;
end generate GEN_CH2_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_ftch_idle <= '0';
ch2_ftch_interr_set <= '0';
ch2_ftch_slverr_set <= '0';
ch2_ftch_decerr_set <= '0';
ch2_ftch_err_early <= '0';
ch2_ftch_stale_desc <= '0';
end generate GEN_NO_CH2_FETCH;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- Assign fetch address
fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1'
else ch2_fetch_address;
-- Assign bytes to transfer (BTT)
fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1'
else FETCH_CH2_CMD_BTT;
fetch_tag <= "0001" when ch1_active_i = '1'
else "0000";
-- When command by sm, drive command to ftch_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ftch_cmnd_wr <= '0';
-- ftch_cmnd_data <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
-- ftch_cmnd_wr <= '1';
-- ftch_cmnd_data <= FETCH_CMD_RSVD
-- & fetch_tag
-- & fetch_cmd_addr
-- & FETCH_MSB_IGNORED
-- & FETCH_CMD_TYPE
-- & FETCH_LSB_IGNORED
-- & fetch_cmd_btt;
-- else
-- ftch_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
ftch_cmnd_wr <= write_cmnd_cmb;
ftch_cmnd_data <= FETCH_CMD_RSVD
& fetch_tag
& fetch_cmd_addr
& FETCH_MSB_IGNORED
& FETCH_CMD_TYPE
& FETCH_LSB_IGNORED
& fetch_cmd_btt;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= fetch_cmd_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
ftch_error_addr (5 downto 0) <= "000000";
end implementation;
| mit | 0249eb402b634d92dd9eef253fefbdc6 | 0.423754 | 4.423009 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sg_if.vhd | 1 | 47,022 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sg_if.vhd
-- Description: This entity is the MM2S Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Master AXI Control Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
desc_fetch_done : out std_logic ; --
updt_pending : out std_logic ;
packet_in_progress : out std_logic ; --
--
-- MM2S Descriptor Update Request (from mm2s_sm) --
desc_update_done : out std_logic ; --
--
mm2s_sts_received_clr : out std_logic ; --
mm2s_sts_received : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_done : in std_logic ; --
mm2s_interr : in std_logic ; --
mm2s_slverr : in std_logic ; --
mm2s_decerr : in std_logic ; --
mm2s_tag : in std_logic_vector(3 downto 0) ; --
mm2s_halt : in std_logic ; --
--
-- Control Stream Output --
cntrlstrm_fifo_wren : out std_logic ; --
cntrlstrm_fifo_din : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : in std_logic ; --
--
--
-- MM2S Descriptor Field Output --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_new_curdesc_wren : out std_logic ; --
--
mm2s_desc_baddress : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : out std_logic ; --
mm2s_desc_sof : out std_logic ; --
mm2s_desc_cmplt : out std_logic ; --
mm2s_desc_info : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_mm2s_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(4 downto 0) := (others => '0');
-- Used to determine when Control word is coming, in order to check SOF bit.
-- This then indicates that the app fields need to be directed towards the
-- control stream fifo.
-- Word Five Count
-- Incrementing these counts by 2 as i am now sending two extra fields from BD
--constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "1011"; --"0111";
constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "0001";
-- Word Six Count
--constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0101"; --"1000";
constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0010";
-- Word Seven Count
--constant NINE_COUNT : std_logic_vector(3 downto 0) := "1010"; --"1001";
constant NINE_COUNT : std_logic_vector(3 downto 0) := "0011";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal desc_fetch_done_i : std_logic := '0';
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Fetch control signals for driving out control app stream
signal analyze_control : std_logic := '0';
signal redirect_app : std_logic := '0';
signal redirect_app_d1 : std_logic := '0';
signal redirect_app_re : std_logic := '0';
signal redirect_app_hold : std_logic := '0';
signal mask_fifo_write : std_logic := '0';
-- Current descriptor control and fetch throttle control
signal mm2s_new_curdesc_wren_i : std_logic := '0';
signal mm2s_pending_update : std_logic := '0';
signal mm2s_pending_ptr_updt : std_logic := '0';
-- Descriptor Update Signals
signal mm2s_complete : std_logic := '0';
signal mm2s_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_xferd_bytes_int : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- Update Descriptor Pointer Holding Registers
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_64_reg0 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
-- Update Descriptor Status Holding Register
signal updt_desc_reg2 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
-- Pointer shift control
signal updt_shftenbl : std_logic := '0';
-- Update pointer stream
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Update status stream
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status control
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal packet_start : std_logic := '0';
signal packet_end : std_logic := '0';
signal mm2s_halt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cdc_d2 : std_logic := '0';
signal mm2s_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cdc_d2 : SIGNAL IS "true";
signal temp : std_logic := '0';
signal m_axis_mm2s_ftch_tlast_new : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
mm2s_desc_blength <= mm2s_desc_blength_i;
mm2s_desc_blength_v <= mm2s_desc_blength_v_i;
mm2s_desc_blength_s <= mm2s_desc_blength_s_i;
-- Drive fetch request done on tlast
desc_fetch_done_i <= m_axis_mm2s_ftch_tlast_new
and m_axis_mm2s_ftch_tvalid_new;
-- pass out of module
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_mm2s_ftch_tvalid_new
and ftch_tready
and desc_fetch_req
and not mm2s_pending_update;
-- Passed curdes write out to register module
mm2s_new_curdesc_wren <= desc_fetch_done_i; --mm2s_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch1_desc_available; --m_axis_mm2s_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_d1_cdc_tig <= '0';
-- -- mm2s_halt_d2 <= '0';
-- -- else
-- mm2s_halt_d1_cdc_tig <= mm2s_halt;
-- mm2s_halt_cdc_d2 <= mm2s_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_d2 <= mm2s_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_d2 <= mm2s_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
packet_start <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_SOF_BIT) = '1'
else '0';
packet_end <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_EOF_BIT) = '1'
else '0';
REG_PACKET_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or packet_end = '1')then
packet_in_progress <= '0';
elsif(packet_start = '1')then
packet_in_progress <= '1';
end if;
end if;
end process REG_PACKET_PROGRESS;
-- Status/Control stream enabled therefore APP fields are included
GEN_FTCHIF_WITH_APP : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
-- Control Stream Ethernet TAG
constant ETHERNET_CNTRL_TAG : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH - 1 downto 0)
:= X"A000_0000";
begin
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); -- downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65);
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 5 are reserved and thus don't care
-- CR 583779, need to pass on tuser and cache information
mm2s_desc_info <= (others => '0'); --desc_reg4; -- this coincides with desc_fetch_done
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= desc_reg8;
mm2s_desc_app1 <= desc_reg9;
mm2s_desc_app2 <= desc_reg10;
mm2s_desc_app3 <= desc_reg11;
mm2s_desc_app4 <= desc_reg12;
-- Drive ready if descriptor fetch request is being made
-- If not redirecting app fields then drive ready based on sm request
-- If redirecting app fields then drive ready based on room in cntrl strm fifo
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
redirect_app <= '0';
cntrlstrm_fifo_din <= (others => '0');
cntrlstrm_fifo_wren <= '0';
end generate GEN_FTCHIF_WITH_APP;
-- Status/Control stream diabled therefore APP fields are NOT included
GEN_FTCHIF_WITHOUT_APP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7(DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
ADDR1_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR1_64BIT;
ADDR1_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR1_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 4 and desc 5 are reserved and thus don't care
-- CR 583779, need to send the user and xchache info
mm2s_desc_info <= (others => '0'); --desc_reg4;
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_mm2s_ftch_tdata_mcdma_new (31 downto 0); --63 downto 32);
desc_reg5 <= m_axis_mm2s_ftch_tdata_mcdma_new (63 downto 32);
ADDR2_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR2_64BIT;
ADDR2_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR2_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- As per new MCDMA descriptor
mm2s_desc_info <= desc_reg4; -- (31 downto 24) & desc_reg7 (23 downto 0);
mm2s_desc_blength_s_i <= "0000000" & desc_reg5(15 downto 0);
mm2s_desc_blength_v_i <= "0000000000" & desc_reg5(31 downto 19);
mm2s_desc_blength_i <= "0000000" & desc_reg6(15 downto 0);
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= '0' ; --desc_reg7(DESC_STS_CMPLTD_BIT); -- we are not considering the completed bit
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_MCDMA;
-- Drive ready if descriptor fetch request is being made
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
end generate GEN_FTCHIF_WITHOUT_APP;
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_msb & mm2s_desc_baddr_lsb;
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_msb & mm2s_desc_curdesc_lsb;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_lsb;
end generate GEN_NEW_32BIT_CURDESC;
mm2s_new_curdesc_wren_i <= desc_fetch_done_i;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= mm2s_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
UPDT_ADDR_64BIT : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
begin
UPDT_DESC_WRD0_1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= mm2s_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD0_1;
end generate UPDT_ADDR_64BIT;
-----------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg1 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg1 <= DESC_LAST
& mm2s_desc_curdesc_msb;
-- Shift data out on shift enable
elsif(updt_shftenbl = '1')then
updt_desc_reg1 <= (others => '0');
end if;
end if;
end process UPDT_DESC_WRD1;
-- Shift in data from SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_mm2s_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1'
and s_axis_mm2s_updtptr_tready = '1'
else '0';
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
--*****************************************************************************
--** Status Update Logic
--*****************************************************************************
mm2s_complete <= '1'; -- Fixed at '1'
---------------------------------------------------------------------------
-- Descriptor queuing turned on in sg engine therefore need to instantiate
-- fifo to hold fetch buffer lengths. Also need to throttle fetches
-- if pointer has not been updated yet or length fifo is full
---------------------------------------------------------------------------
GEN_UPDT_FOR_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic; -- xfer'ed bytes fifo reset
signal xb_fifo_full : std_logic; -- xfer'ed bytes fifo full
begin
-----------------------------------------------------------------------
-- Need to flag a pending pointer update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
mm2s_pending_ptr_updt <= '0';
elsif (desc_fetch_done_i = '1') then --(mm2s_new_curdesc_wren_i = '1')then
mm2s_pending_ptr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pointer pending update or xferred bytes fifo full
mm2s_pending_update <= mm2s_pending_ptr_updt or xb_fifo_full;
updt_pending <= mm2s_pending_update;
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
mm2s_xferd_bytes <= (others => '0');
xb_fifo_full <= '0';
end generate GEN_MICRO_DMA;
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => desc_fetch_done_i, --mm2s_new_curdesc_wren_i ,
Data_In => mm2s_desc_blength_i ,
FIFO_Read => sts_received_re ,
Data_Out => mm2s_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
end generate GEN_NO_MICRO_DMA;
xb_fifo_reset <= not m_axi_sg_aresetn;
-- clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
mm2s_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= mm2s_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= mm2s_sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_QUEUE;
---------------------------------------------------------------------------
-- If no queue in sg engine then do not need to instantiate a
-- fifo to hold buffer lengths. Also do not need to hold off
-- fetch based on if status has been updated or not because
-- descriptors are only processed one at a time
---------------------------------------------------------------------------
GEN_UPDT_FOR_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
mm2s_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
mm2s_pending_update <= '0'; -- Not needed for the No Queue configuration
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_xferd_bytes <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
mm2s_xferd_bytes <= mm2s_desc_blength_i;
end if;
end if;
end process REG_XFERRED_BYTES;
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= mm2s_done or mm2s_interr or mm2s_decerr or mm2s_slverr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_NO_QUEUE;
-----------------------------------------------------------------------
-- Receive Status SG Update Logic
-----------------------------------------------------------------------
-- clear flag when updating status and see a tlast and target
-- (i.e. sg engine) is ready
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tlast = '1'
and updtsts_tvalid = '1'
and s_axis_mm2s_updtsts_tready = '1'
else '0';
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done
-- or datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- -- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg2 <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_reg2 <= DESC_LAST
& mm2s_tag(DATAMOVER_STS_TAGLSB_BIT) -- Desc_IOC
& mm2s_complete
& mm2s_decerr
& mm2s_slverr
& mm2s_interr
& RESERVED_STS
& mm2s_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
updtsts_tdata <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- MSB asserts last on last word of update stream
updtsts_tlast <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive tvalid
updtsts_tvalid <= updt_sts;
-- Drive update done to mm2s sm for the no queue case to indicate
-- readyd to fetch next descriptor
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
-- Update Pointer Stream
s_axis_mm2s_updtptr_tvalid <= updtptr_tvalid;
s_axis_mm2s_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_mm2s_updtptr_tdata <= updtptr_tdata ;
-- Update Status Stream
s_axis_mm2s_updtsts_tvalid <= updtsts_tvalid;
s_axis_mm2s_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
s_axis_mm2s_updtsts_tdata <= updtsts_tdata ;
-----------------------------------------------------------------------
end implementation;
| mit | afdd655db51f4bc026da0ac3e558a8f0 | 0.468164 | 4.02758 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/idsbuf_tech.vhd | 1 | 1,076 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual input buffer with the differential signals.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity idsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
clk_p : in std_logic;
clk_n : in std_logic;
o_clk : out std_logic
);
end;
architecture rtl of idsbuf_tech is
component idsbuf_xilinx is
port (
clk_p : in std_logic;
clk_n : in std_logic;
o_clk : out std_logic
);
end component;
begin
infer : if generic_tech = inferred generate
o_clk <= clk_p;
end generate;
xil0 : if generic_tech = virtex6 or generic_tech = kintex7 generate
x1 : idsbuf_xilinx port map (
clk_p => clk_p,
clk_n => clk_n,
o_clk => o_clk
);
end generate;
end;
| apache-2.0 | 64e3b28aad22d8f17b6a06bc0d21facd | 0.525093 | 3.842857 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_min_area_pkg.vhd | 27 | 20,310 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
XHCjR0nUvMBgM1clzO9mSr8YEx9qhDtoXdaphp+J1JlsC9lSFtsV1/eTy/jaNsyBimTHmHB4CLra
VqfCr1I3uA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ebEJK3bmI2t+WsBGbhWIt2XB+F+QW56z7Xo7/vGiNjxPbaq48cjkY2KIIwhppzuYFDUdRDxp9Iva
RlWujqNPGUrxJ1F5Pa0zN6dEMkhKPrWWxZpAFto5e5cB6DM88tJus2O1hLy9PRfKWKn8u2fBqIhs
zvXwIEX3Rz7kU3GI+Wg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
oZLpbXnbPC0EfiuqzOyPqmT4FdlvB20VtdO3P1fZux3uAWynrmGeEUk81RKG8dIjeHdSPnugG+6c
jKeGIJZZbH6MRScqnz2QBuupQkeYWE+dCLOq6/P5LV7F5481QZZ3bx28u0vHGlRYhLiMW8KnJ8Xs
JLZ2IP5YULE4cFTCCV3WAM+IdulnwSP3p8oyM0uQffeAJkOTKR9dl0lslKFBplzuTZ7EnXSmYYXA
x4iYEfwbmUZvdla6dJXCCjtKnKqL5vI4L1nHOaep2f0bW/K78py/TJVV+vsvE7+Fi81aNwDFBE3d
V+IzN5VNKD8wM+OpLL9AD+xsAbJ5JCLz2sqFWg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
YaruXmtmo/2yQOaZLp6UQc/TTak5F2uchK3/c4SsORqNnQQMwFmjpORZM2++MrgqzkHH5KHH+0SE
PP+ha/JFKIuufLvaAIVDYgMKSDFaxIIvD/8aIAhw7TgTE10+TXTruuPFiw9U65VaBnD/nSEGkP+6
2M+aqBTG/2UNkEELi0I=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
SWJkuOmi8gVneMbAS0rfK4gI+24fr/0jQv+b5sUWbuvKyCco423EdTDwW7ROH+M/MaGP2QTzNz1B
sh1p0mypy290KKaGmvaZfJU7NOmSNGAsA7Eq3zQGPHDW45/4GXnri5xLLNnybO7r0Ndv34V/fxH0
f64f4NRroCys3EmRDJeCh0D+WDA98E/EHP+OtfmYOGeO+CDzxS2m3FIcGKs7pkeR5dgt+S6srqxz
96yb5/UwV2cpnC9ULYZHZVQa9WYc/XM+Dk71YUYpaEFd7osc9zT0azChQq+XAkJsqukhufRg3dQK
YVPZotO8blEly5GYlPFGnRW13eEh9DRYsb0pSQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13296)
`protect data_block
HdwiFh+7q6VKXXo4jZsgnff6h0l8JDlWPWOjLvS0NqmI1inJjFBOopuHm7m3G5HsyXcM8JPIJBr0
SgFXDHqNzksRoC0CRa3Sm/Q5BWeNC62VdSU1iJwTNaxY9iak7bkj1XRKtIVjgK2T9+SoXr+pt9ar
qGhhoh6rtfjLwyTh7AWiiGJ5q4aseLEZoGLTEQeeAe/+SlmuzPILVBYLSsEzOxkijaAvw6C6oSBL
kEkdgqQmwa1zT9X+y5gxnOSVdOuu+zhiw9EWH5riPTNqUI18bL7rVceyRzW6QNoWU42DtI4o+Qsb
ylyjSDCjEfFtuxPlq7red0bhWOrOl8F/MMHm1k4Adlhnxr4cGmBCxkdHK9+51aPgx1xXJ5guqGpc
b0cLp/6WQjKoydkN0ixJgKtbHnFqDFBGYoUMNMQSqTW9Up6YiI+jS/Hy85UoxnbvfK5JyLoYQT04
eLNKXSiSWuWAF5t/cqFOEZ0m2TqFeW08ePLk2dwZGG3ARbamgjuR+84UDgwC+qiGfgQ3lbC5/lao
Me1N4HQRqqM0QQIBk4X5a1l7Tk/g3DdohSZeyEePDlLtyip8gWQwEUnWxsgjvDPYZ+NrZJ+dHqR7
V3brN1zQweldETecOP3Sz6o1UN2KzrmE06fmohn6UfVOBu4+0sq2P+BTJnr9NP4F44BwrMXxDRmR
XjlATx3Fhd08L+8tIF0N+gWGIf5+dlPQrtNMmmHHCM19awr+BqholxmnJvIo9eStJTzJ/kqbywgT
qzq1m3VsnVBuHRLOJwDktXrJYOyC9y+asvtff/GHo4EVtVgOlu4Z4atKs7fibGjkGbZF5f2nQCg/
aJhMuxMvlA5gRVvWMvvQjRr5bN/uh0NM71e8/qy+1S+fxwdlVn4QdIeQHTtDGOXysFCyF1dzF/VW
hH3oko1xLQi3Fne6Kv7UMGWl5u87GlVLkaaqP6nXg2G5OfPiyN0LLHJMKKfY3E8bfas5Y0ZesTvJ
gvpBemHYyY59/7qX+MjCz7WuYkomLgQmBkxT6ul3esaViP6Z9VKtrZHU/mQvJ3MAGG1fTXiYYRKb
0CvzegLAvFpE2hwXIgPGxbqSpeGm9KUkHpL4mlNCyPjD0Munw+H2eP85xTk1TzUpXIXsoGS0bChp
5fqoxcUxkFpphZI6Nm4FsDW4FlvSjIe2bkmjTnvTLE+ZjsajxpCZdWI0+vtfwc3nER8zv2PW1LJF
jyCTsDnHU2EKrDWzPe7Sh4DcUFZAwB0aIVi1qV7NpfDOxEMn0IERniMVNYjVpE7VPq+F9pco89Ht
S1U9x3WHsc32Ttc0ri0ya+X6EJV0zfG2W5XAWzT6sUrwxVpNdqAJSLXBn+FdklBohmo4jjARokLd
Ytoxh0weeC/Y5pmiLnOacCL9tUmL8gcd8kY6gUCJzAm2L5UMaLuh/+zqIYcmbrESMk0f806CbaJ5
UHTObVE40fVHUGNAMGVVZOshwP3HS3DFB/x1h9JcTb3dduFLmUtynfjZXuwPtmJEPoZVCoVvqYuk
C2fvBUk9Wbi0yNUl0NdqEyVTTw3ob3uMDN7+aF2oNAylpm9JDhJ1Iv03rW+4BULl/A//FdPWWVvY
tb0m55ePDOqZFMUfPySc4vN/Tq96TSXnu8m8Xr5NOPGUEpoyLe3t/l1sFbzRCqRyUg3v0SIfN0Nj
p55rP/gChUZhZREb1t43wDaO1uZAU0uPKYWHa44CA7WgMJMgAS2NuuVKN66pFg9xK94OcTlWMRV6
uiC+KEbWuT/VCJRb5T5mda2PrH3ioj7gkEv7ub1BaQYwE5QkyCZpkI+D3hbJUHtj+t4bDOfTDHbx
5lnTfzcpLgVmAlfAJA+lmAzxke4krWKnz8PCIaBhGij6hpfe9pPNCAd8pp3Vy2dqVGwMFEOgOU7W
CpzB/Y0s0lBRImWJUM3DJquCcpRK5VrTA4ynSZHi/9tXs2By7OP1IshGzIpBMY5l9rUvBajqtGhK
ZuE0DY32Rs91DsfkjrqZ4M67q8KHe1MsBzFImSdZ/9hHrGajHb197ZALk5ux7l2rCtZjLvJ5gkuq
+K2YE2Z4xmsiCsmgM5VZVnUcvYLhxrryayZ6czPoUhJnSNzzmFVA3W7mJiPjr/v2MzT/TxY/7a3E
zyq4g+oG5jMGYH9okY3L7BTjixY7YSaa3ysOG8Ql7sKVg11TmCbLggp2B8q2cAj0W/ozzj7Nc2kQ
CGCpCGRAs3QcEE0m6V8BBpUBuak+Jd/Mk4nN0GNsLjgK7IfYlUSLfVaqllit22Kw0XA0CJlxx7Cb
TbVTBYOTgO+EmtaK8DHzIZNb5FCI9DywhFdfPB12gFD09rFBLt+ayR9dVp4L/ydh9MnE/LAPtEbJ
02JS7zHY+6NtqxtMWmqpYvJjU3VZBhJakrQedkA4TfpRXCI0NbpOlOdswtq/8ezfT2mThufsCPJu
gjetJg3Uii0fd/hsKoTCn3/EXb/+ejFgU8LZIiVIfSDneeWtmLTggQoZyb7i2i/vrDTiwJfCAauk
kbn4sYFfFBAZIx7865qsWrd/Nixj6p1M0D4tz8cNC9f4DsklzpMKrV9MQvuW3lwSgqpX7uY4QZxF
m/6v3wr9p5RbkvE1qwwok2eSwWDrVyh+mfQPlN7MAkyGtnaSICDIdYI07Uko3rANmck983KpKazI
RUfCrptKjZSmPA0XV5/q+vjYcAcQPmlZVEZeeoBLTPRG9pn0T2KyMPFjBCH8aY5ZQ6hLpvrd01Tm
G/IW0z5L7YY36cKmdB87+R/igoKvbLLYWb2gJUewqTMQEurE5xKE8v2wfWDbkjxoTXYc5ObYF+R5
C6XGsH0JNt1WzUKgI9Q8s5EMA9NkgIVb+U0I9mY9BpvL2YCv0FtPsxdLeLajLq/eUuAcJ0wKG1vJ
aqs41Z4tRNFKcOjMFVn0yxjZfQWun94Pvx1rJEuzTIb3NBVMx8cgCEhkG/pXJ7noZL+xaUWrNZQ2
JtuYT7O7gWRfcmYalnkoeRGII8ouuLf5GOdw28chYv9lzRKFJ+dw8nDHewwXZhGndl4WK9AOUfjo
r5i4A8xMOSZONdGNy7im/E6+UuRUXCciFVkvtd2UjOyvjjG42ck8d2R/E9jJBvUXRo0m7ywM+kPE
I6syiCV0WwGNKgj8YqW5UcpYCt8vzGmp/kndJW9dTaAb+FshO5KelBFI310STbd71C0gPxaqp+OC
yruarcb3HmjadLf0R+snrqhdQAJiI/qIelpRQHNbb7pvGiBgVhLQs5uXdxEpIuts88BQQxHfTlBx
sz4h2HkZ+BJH1KkPN4iCbbYhbHm+PTocWomtB7zMqFT2uFJv1t38pygdyvW72wEXc/w00MTGNtMD
lipyGlKfUbmihHTl0COEOSocNoYr8x4cmMSIjazYFeseEtNlFdNJ6BS7N4JOhHVgK+LwR9pYaDp3
dtEBGXiMxdgYeDkGDL4srDvcMNoRPUFdV3E+SeC0hplXkjAzH1sbG7rT6BGuhYxxqgPCsLoB/9VP
w+W1qM8uZTRZCF07DYKhc53b1vj0PubQJjG/TroRPQcUp4GfLmdvHY84ct5cOIq4r1TdSuLr74rw
MPZqz7OJldzkf0YHU8Gu6H6IVCqZzkuhJY551CnukCg+4j37+FAltZCAsz6xjf3tX9UkMjzUeE53
tXjGHZmSuw+6HEfxeN1n11TmVCDMiaS5xAXFNBxzohn0hWUcbfARvtGTCfzCm0g4+6CPqOVLTi9R
23SioriNDruL0435fNfg8Z0FSLOxw4Qt+hLLAO2bDFFDzqxNde+IwpRFg9H50XWeFsbs7O6uVswh
Jc1dkSc4hOvbO7KrjleuNntPMyi2ErGBgLJ0PCdruhLQViKVa1GPiM2wbCZ2FzFlEQQvbGyjpEBV
kWms8VcEjC2inpeA0Dq8exynF2AZKRBv4Wliv2izisyYtULqgW/czCexrrM69ZzXak+fVkLfFkvI
IhQS8SSgD4twtFMj5B5UF18dwLljLlBgzZ/Dov0BKPBM756nVr1NJjyAYKvKFkUe4YyK/PZnCH1e
Ie5B68Ow8XbWi2VsDYWGJMCS6vf9bR1kWUZ2MlugJd8k1MYir3aLTafGizmhyol0QTSSrz2Rl1Pl
9zvJwEdxLX92/LckMP4ruCu+9cRzABOd22N2ul0BRyp+pzgp8dxlX9+1O8Hf9UU7GTozjqVFeErB
dwNKeu3srth0Is+Wz2FkPF+p7w0jvTO+ufGLUAU4Ib9NNclhbycI9gwNd1OfZd3YyBT3CzZ2CUQt
348XExgXt0662jCPnNVPiMyOcR3Y/RiT6A6O3T7H3YHuPNgL7AEt0dU3ARyWbcZpscrGcE1ocm2P
seBYD8cgXAhOU47p2KUmdUonevDAakf1RYZUWdr/RnJE//cDLkeI9rVItWbeqcKtRSKLnRZAjXeO
x1XeEH/yzk7A8egcN6gQ4os+Bwa5pt3EnnXQ4awJEpuxvdxzlW2UEKCoYQVXavRW1kmpw9iqBcZB
QxNmTKPQGZ27en1lMpWQcDHMEK9U936XHIxpXUZtTnNdZd3XYK3M1nfwA0UUUIg8SV81MOBUkkwC
MiPpWocUJda5LD1MaVBcqeF9w+QV4HzdDERCEGk5Popj2PEgmZm9lww67ViPFOdhQ4QucvZMNtH+
5nE93VNLJpZvPzSvlXiIFiVjwl4x3oVwpdbNcXnFYkbTe/1ui3LDnGrZbZAPvMHOyhsxBBpip9sc
/62Il70l/dpbr3oEfQ8D/CZIXHsP9nq4r1P2Xn1Tvam1bQz3fng/bpqObbUW/lCZznED9LwGs68P
rI8nhy9+yy1do44j+CXe2eXTc4Fly2fXB8VmsCmr59t5wVtMwOFBvCoMST0dGAsb8Qmi4wbxdLtq
otFzppWEaWrum6uAl7mwFwLGkOm19mPmSEjt+o4AfjUnbYB5mAyX9VV5eTVDcLdF5vR9cLLKog12
KcCFx3N2Qh7y4/su5IMO0/ttxGPxI3ErZTuH7TxdALv3VKQfgJZLrE6to2E8s1omrHEt5gBs0Scl
OIcUaTxDI1fsmIetMUKcNbfWxTGUjOkO7v8jMGn+hJUDO/wGQ2qW7mK4C6L+IY5y4+AoJ6nxLPyL
0eo1vJoeDnqYVmtQ3FjylgR3etdrHb1ThOfPeMH4wxz9IPvPfjguBaNYaysFluGbRaD3CetuzU9I
bPg2J49hNTF7uP+W5tKIDb4rNxSA1qVikeeViykBEdT2xb0zvEk1wXblMm1QaG1YhE3c7INzvV2e
J+wFZnSacNF0YCCHHG6ogIfriZePdhp1Bj4SQv9MVPI7itFOkg69j9wq8EJm+O78Rz/+qK9q1XQf
beiOm8J8KVRNJHOQvu+JX+mbuQXHkaa53AaUi0S+UTITH9fdUbFTsgmT8UXsEjmyc6V26ShAxzFa
HvuRb1LomB2sGABGxaKOVf69asmmpRVpXsHflJi1Wtc53xv8SzMMt1/4dG9PB+ToQZZf/Rn/t0ED
keGOn5b6ROwOK4bgfp04bt50CzKYvfXeFFPzstSbp12fqE1W5KhwKQfLl06GxGps52QGMiA6Vi3b
6xOMzB7OQhQjyY231wZ6JH9zSDVzpRAQiUpEOV7/5UDVLcumzNCHl2Ujvm9MZvzNZRa9F7jCqyuZ
naLAnD/sHXKNKp4+sN8oZNSSdBr8saw4m0cHrtFoGA/6v5U70+s7qH63/i4e2w0kPil0mrAOtnAr
wevPZXhnMTRUFVL3SpBpuM4cDx2N6HlJ4kKC4DM1tJGetSG+jgqF+gplduVPL/G+7mD3MGCMYjhi
WGQEOFhmHg/aa0QSewHSPPbzgnqiwMwhcy3t6DdjVs1mtOESOXim6dUUxBjQCx8DuF28/Wk7/fCB
Plwqnaf9wUbaesOh2/KjjImvDrTaWfEy40efIDKVo7w8qK2mM+5ji2gVlyEXASldU+IDvy/b9xX5
nEn0WUIm19jdllRavWvH7iRC4jHUYMD4PwETSLFgouGoqA/wzbzXfi9v2X8RQqd32FlBbjkF1cHg
ckUkNCpwzgNjnEIxmL7g0RfrwwfFpwWvuZtq3hDiR+0FwEpwoOZ403pUyJ6SQ+AkEoYWVAXyqVCX
S0IOr65IWLRYOR0g/6xpNa9Wmj20KlMuReajnLalecEYOgtZdobEuBWhqbgpUXbO8jnStQ+G735m
MHm8mntWbh2jJfN0LNrmeslOR43p4YRDSIX2z8qis2SYFn0Ej4WZ1cjZV+4YB0Q2fKqJ4CADhlRd
WDkCTlYD+upwqfQkfOaMzEZejYvqIOn/Qmk1J49CF10odMAtnWHC1qdaRb3l5re3x7cvx3ILhszQ
NFeZv25cPVnQyIaNmLYShUemUEfsyfEqTYZB2smcYZmzXs9Bi20ujPsmVW2jNNne5FbsJWGEm0Ia
NSIxWs9G/2ydQKbF6FHeMSr0sMrYi8w/LAvsLWlELLfoM/mO6VNWLBC2QyaiF1WEVFn2v2HYycj7
RY4pCwIedoIFBflhk/dLYCiH56XuGIxqJPyYS+zBO3974MKuoskW0XvFpNGy6oEgMUz7cWend4IU
VjHOd/hEaZRoDSR/Oj1lmlxABsIqdWisKIYleqicvE0PmT2Jo2gdm9kVV44Gw6Z2wXe6XUfrjyEg
SiB/I20hA/Es+uxUiaTDQO+Zc1ZqOd/ueoHESWMyFMICaeaK1l/SD9/JmvCDpCQjdLLYw4jVrcOm
x82XSyfKdMIlApb6Rk0XdTzoVKiNkaaqs9WFTBYmntOjbqzZjKjtsAyOryTohZQW2tKFDS38Gi7p
yuMxgVKdfNZZ1Q7PU2RjazFSyK3OFOe275+0+YHFi5zhVwVdzJgktxulyBrWsnmFiB+30A0RHyQS
LUt4P6faUkXg0kJT2f7DPqFb9ay2wBBTG/HUZor3ZEBxPngcG+OZoK8Q8dMcGBPYDIFcZPFLmzYI
kUucMuOkU3Ult4YJ8TXgvhqskpxcRwZvmC9jpLgZdS+yWwTHZr2hRLr65IPNmu8eosbGV1rZ2VhX
6lHidoVv1pRyzeTbCbNYwVihIuOSMCNE0nauuDoRfhihyj8yfv2Av59/H/4hKd96d+XEzwDHUO5K
XW0DKvTT4eVvvvoINKklkw3BkOMMLlLAwAKj3HFGaoBNUrSuHzbu2G+N9Dx3Vr/+BSjcTB493IGv
6GY4PMG4KLgh0/haQXZvghE+485BdqN2u590k/y4tyfr8UolMOdwPPDYZ6ceT9c19oDioRIBRLRS
FqPnwliATX0RdBQaKLEp0azVExQXltkJea/Vd6nF+eWX8kpfpmaizkgiw/znlyUGGvXE0B2oRAGk
Qs2yeEbQACLaTG3oIhN4IdFlTdkthFlBhk02R2yb8Bn3vkUOxqpP1WbEYPHHWns5N1Nbu6ZyyvKv
Ft8lMv/0mBYZpvqR6HWU5vqp/MP0JAdB/5H+pXm2zDVIshHVhEz5PrgRzLABvwXI+TB2CAc6K8Dr
3M+dXhCLtoLXJ7FJQV25BKllp3rpW5OFlJMvXKSMhoOxXqOf8LgPP5Q4wP+ZlMeMgX7us3dV3QGO
D2bF/cAh84nF2xWjfFP+NpmfqDqA5VzYMsWz480fJKHQLKWmQsF/nXze4KMaeX87FM5I9C/Usks7
C4qZ9xhUUslBcqYentUf96s4Y7YMB+MjR2x253hPcnxAqzmFAHqCAgAiURbv6EjYCLDpOC3Q4ZQI
4DvtoSCd2TLpVRIxfZyp1U4JVxo/c2gg0gb82FTpC6GZbhG3yW1yQ0NRsWM2mzhOOFDbYDwcBHI6
EVMXgVE6SStQRGMLY979GPGc61Msv8HViIB28+5x/YSWnD7l2AHLkOyToXucy2XgKxw06nPOzxA8
0FZp1UQ9IpR++LMIEAvq+Zpk0ghlzAG2B1jAMpuMvZXsA7OvwK8VgpXjH+JRdebkFY+hNOe2b4KO
ahzupqF17Qink9fh/0yYegVy8YZmxTCBjY1bH3tgvHVqODlbgOcpOJUz/lh6vcZGnHWDQhIEkvuI
KVGLBB/35FN7i6l+U5gmRPPLttpRhI/ySFt8HI/reqBWa1oO+IV/cSoOtNY0B+YZ1OX3S8Jj53fh
tqZ4w7KcV11LX8F89Oy9Cn91L7FZlO12LHOeZ8tMUQyft2eGJOfJWFYDsTVTtB+oUcLeiVxYIywv
27cwhCO3vdfvjMOkJaZMj5JmBOz5eSX7nDuiofDn/m1pgPCMqg6I9E+ZlLDZ4QEd4nIp6+q1oNYj
NZ4RZqNuvY6VcxFiivRI0pqWg0KvGPgO0GEEQxrTznYIP+1lr5fBWEqQ1g7izszGo7uSOHLtNuOj
H/3OaBTMq/yvaQ+iXofTa308XtwQyH5HtcG5qjfGS84ESqcYPYMLNB07YzMu/TE5/7Bcizm5OxnN
U2X4Y3Z7RMqN2ZwgW0FpoalxIvgVlycrCc6WqzpNhb8SXqyd/iL4er6uCX408lwm+A/iexql5Soc
UAjE89woZHtrfnbCVxUZAoEldE8aiit7WDAa6TCB+XXFCQ/Vt3ODUiu16oP9r+HmmqL/JKBHgPIT
kV17/P41HubDXWxt3LcX0p4W712nu7m3hFsTri4Aul6S/YgbMhJ6Er/QymVHXobk+GUSAL3bmuHF
SC7FYKwQqjSRssBqpvtewdHcT02oOlCSAn5V1LWqGQS9WE/kXSXrtjKWh1yfukKfyIE4phVySkvt
LWHYXSNkG8C6RfadiqsABkhM56Wom8pVB3DLq3cX0Uwd0ZLRjH8b2LyEckg57raQV8fI2CM6fhDp
DbPX+o8RxyVFtiNl6lM+gPcZmmng/FCEruGaN8A1BqpXrhK2JLl+KieWl0yAmajFLkg2L4fb9ZSk
i5W/450idn+JsfDT8y1+AHhjw6jk1BmS8XavrolK0O6qwwHrIXj6BZFiNo5OroywUKlmX9KyUGzj
xSatJw7+4mYp8UxONcSiKWPPIXJsyTLsKvDVsHOsutm0mDC/61TpiJdks22no27H6BE7oBJ+r0Qy
ce8nCMcQzSOtK6Cg99ikP1tso2fu96dDFB/wW/NjWZC5ZNO4Riyst/TzoUlrp+PWTUx+AwDrv/Bn
Zx083W5a9K0Cv+UKIy5KRgfjc9YRq4/1am0rHPBUb7d8OlDhA6luV57e5eEaTgWAMNjYmySz53eH
3ADV2+reUHBSRZhZ5FjyxXbzy3RiihGAMmyxVqRNB/GgHCEF3JZoz9YAiSA1sQA+OlOEaC9zxLjR
c9el/mBq7u1id81mVMNLy97mqV70ASqjrRx7KNZNUfzwETBrCEInCeHjuptkzvH3zF5e9QI/gb1Y
c9muwitjkca4K8jhQNFqbJRTrjoqwGDvN2UTUUmp8cmPc+I/i2Y6GdImDaFLggApyet3o19lFJX6
Q7Waq8sp0pavRYqx4dF4KGBsnJ3QRSwTOArguotovvJcvJp9xe8SZiP8W/vZ25xaD+MwuYpomAOZ
IiRNqLK6f7JZtk0QM71YHaKjOg5ZvKVKIT/IlU2Wl8fCQGAabJl0lG2ohhprKSWJUZ2yaIfMNO1r
1czxzGtnxMfqs+Bwg0Hdxm0nQ4Ky5kofyqDw0oBlApUiTZe2I2BW+b8KAnr1jm3q5CcbpUtkfPin
2PgWhzxjIf3qq9IWV+y22ck8ixItF4ebdez6p/KbBa1XEMgAzqInHN391gOJ4LrRdgllhT7kaw2P
u5LdYDbcOW1OiDub63MomYH14ajBrWT6Vv7FBpF6pXq29oIkTdXvH8kt51pz0fuzfn8njHrVXelj
vbqMI0i+rY0gNs9xyzOwpVKx+dCos38vbFnIlazH5bA0kXZ7zqJ0tdqlv5Ie99llADalOYqfJPuv
EA7SxD2ieUeUmlMdQJ0lx9PTGfMsBEfHuVt54p4W4hbYysY4nW9uAnD1hUWeczRPxfba8C3T5ldi
b9jqyffnNirV+rmfEwNUnz7z5tnftW/p1dw4VKnCG3CEra8S9IhtbT7448Tr7lwky33DcuUWUFJF
CP4qAwIJC8scA7EdGsdn2KIuC65M4o1YHt6g4zAmkLMhbEe7qj5gV/oXgN7UN7OMoHpSOftMYdZq
a1iPME8Y/Tb9C+s5/u+7JvkLxts7ycAhYlS3ZkY3wVqt4u7HzbzGa+ZqjlEvuatWkaelZW/G1jUU
lKBtmsksT5l8CU3QX5AkS2kv3fLSUKw2pmhcoc3kYPWyulwU4O9rgEDeAPXKTSI+MxsG2IZJoqxQ
47BZ6ILjB54uaXkZmT8OF7dTJCFXA47GqFPM5py9tiULmdpdt0/uIgjLvfKwT2aDjtMI0coE7OXo
mLrOthdaujyuE+WS6MLx3EzGltwPMtCLCesvvkUFo6nIXGZLoK6gqpWVjT/SxSBft3fRVcu89Y9y
11f9nTD5OPQKakOzQqbHIWNaKZhQVhfDYo3u1kaFivP1UE0fXUibdmN9rPVASBsFI/i/X7f1XS2o
aMlEwZVg9hFVv5gbqyihTq5IadzK0e6cO8UcO3gYlsi1xgb232uGfJXOuBo7L2C7ypjdiye0X9yC
ozE0j+5pWLEwDybs3dyf8fKYOWEBcu1NEIoZhI8TNPxKhJRk9QM33IBzPIIlGCx8jNaHItua19W+
ivsyRi/EBMXosnpx9EvcNe/PDxx4i/3KpB2iEaVHa5hl+oW1YMEbUdbUabjeURp3YnUEy40KZJSY
JhLruaEh7AdCBOHQGO/gDSQccB2LBerFyHFj8F0gWNq6Uh7YAwQpucH0V9O+doy3f9hHZTdL/lA8
s9sT+V1L/NJxv+BnIF863Jyvk7BkzG/N6QRDRdnfVwN1Nzwq7wXRiqW+0rHmHf5cy00aQMucVUVs
KuZxzYXWywGrvRABgm+jokSVkiro5tw79MnSZKXnKrk2J5ZIap9eQCypWk8fU8Lf3NzoSzANF+da
cZM2Uh3gXvy9gE1vVxi/+3U5IZtD7ziT4PQeHxUioDjI3pwgurZzRWOIwQtpr/5KpdS7TZHWGIga
7riOR3gopN3jNaOe8GPjXJpCLubHJGI+uv/jcBMlOc6ZnoglVhfHwsug+FhZTRXMaCNY215f/riI
lH6eDXmhgw/Ofl+C8SUSJE5OAMVGvJfYZVAcEbuHksQSffQkRic+7ULJLSImO7WlVVt7Q/FK/KXN
/xiIsiz2ptOpYW9jnPkWOB0h0Lf4imlJIjfeYhqCc9lJ+AN1j2p1DX2to7VxPLrta5o7sgNu3uul
bFhPjT5F9HJ/7QfQAoS2dhMS7GmZAZYkhzj+xzoF41n+p0dbMnNcjVceU2QuOwgsaxSeh4EkxjO7
+nYkEskL7BvK2mdx8aTkyF/3c5QCAAc8N+9eS6FWk3gar7u6CGOCSH+809JJ8T1lChInZ35o/wbo
WxsjPKUaZlt+UokU2Ch90FE7zTjmzJehX5P0Isspk+Ig83CQ4VVlxlJYUFGMOt4QItub/h7BuGeq
8EmXTrvmdj9ujWFwmGb4JvaWZz16iIwDAhZTjKhw7k2GD4+dJxp67unleoULXaMUcTFLJlHSdn0q
Sbs01thgSJEO/1+a4zDvsft5vDTcBLnWzJqojQ2Btw97okagWSdVxgj64f2FAoJgwcu1As0T7lQ7
gbVcOXhc1hqMnjYqzXryi+One2cpCt1S3vFdgMATLYLLQ01h66dB6vbuWtTScfHDupto7ye8KUyZ
BrI8iZBsBTPviS7+jTDufVfrQJjR3PhlaqGUGfulSZwGY385bDcubHuzK6HjK92y+x7gpVuiqlet
IR6radRwU/xA3BIA7lkDYkNeBZpIMjmSBlVeNQA1iDSqexmPSsrgcOA68ttNpsJvTxxULlFbxwZB
5lTjsCVgKsSzlVsXuN5lSeUwvI1Knozjbynuyyj/mYx20lwvkc1OaQIhxg6oq4hWfk9E3WKxZ3Dp
L5croTA7jZA8lwpojhTMX8ywpk48O1Nkzf0buyuqTYgrTPubfNXh8yvelNj59BRtJkG26X91WOII
zbe5GysLa8ot5kiqJGY+mYAXwjQNUzzucffwN5+oQN/fV8otTi8F1jbrSKcUSNzA+WollIuqkeuj
nnVQDLOftenHRxdHIO0euU1WtvlUYU5MRP3w4hZI964fiy9ZoA3iBmqCOmLHzwuPwx5wv+xsNguq
EtycjduXq/85nHs4wxPRq43oqu7lTgb2i8qsWjN2wUHrqmcU4+s/a2cRAPZ9O990uhXaY9LZXqSR
I3WZiQV7OJS12e2erIC6CEnfkc/4v1YG4lxHl6F8ld7FOfDsilAFUTf1xs79NYp51xuUI64aMYCp
zWYvYVnMTodIY42ofpyp+I7qdcGItShel4fLv1ekRy8RxB9gl1iJFDjf3CS5H5obahUbNSPOqc9e
Clk8uAsv1bG3ZYyWYMYIs3tRLPQXFwHVuqbDTZE+DVLg6bCQEKTVuHyIZRIeN6cTPGsZUMAexwln
JtpBimEhO5CGzdjHfp/8pbiT301g3nt8qcFnCVr3OLQH9B0KvTl9wvfY0DYDwRrJiC3pIlwY0qBg
OBtuXVGCCfwMhPmvq+7O+vTaROTXR3QtiHg7tdTK7Use4Fz4n7kq465ZKHv1DpG+Bt0/mIV4YKyJ
ev/9I3CgvnBF/4YACoropT3LmVgXKJ+Zo14hs2dC3lUOL4Gmj8Fk9A47s2/uFyctuA1v3yajWLw1
nvoCfPS8Vnm7EKII1Eb0ia/PR4zcN9A6jWKzwemYIhBlDYTzxGNscc+8KZ+J4sji5Y/bLjsbksSd
E6Siz7tlI9DwVaVjMhztMsP1MnxizWmysj28Jz6Lv3blfc4/6MQZAHvQegFIVNXU372NfMHCeQVM
o5kC4t7BP1KbxRCHr+evmsqv6PMFTXaybOC51wbuGMjyrtUGbmF56k+VecpuG8U2NtvzRU0siAVK
2h0RkIENpsi2qr0TYrzmmZOawd00MehHequdIHM82OlO7J+o8p592c30wlkWNlc6ck41vjvxwy1f
5LigDGgSUjhIR0ehTAEajxPt2c9PV7eBBF4acVNzw5fzd4+vfO6s37tA3BTQTfMY3RJfH1dDxhnf
a6zmVYod3IVgQkyx9LBbwijNCjMLkBSfKEts6SD1LT4Jc0cB5jkLtYHOQ/c99If/vzTnfCBhBVcX
Oxv9w+khAYIFu0r/9yI3AxEyITfeQxpwQaTfmpBYFl+LjgodJimddsFvTDCPgtnr7ouuraBm6Ri6
MwBHFeG77KenvR1nxj0TUtZKUasTyU6dnThceHaYUBKKnp6ngVO0B6H+pH8BZ7DMWtlcaOkjszhh
EBzczCg1ZhleyKQwUgylR3k+WwOggyPy8lweio4Qo2tmrVjAKqr36vDdySJV2i9d0vLB+OMkex/k
xFl4tN7iFd03BoYOfUKYe4BNraY78Evwg+g4UUQb+skA0y2kXt5AC39gkAI5NlLMzAh2b8b+0kvY
NSlaV/Md9RoGD+rMrIcqcIddQLbju0uEbN4Dp21ltj+rrFDkzLBKvxfKnHlktTAKqHtFOSCL324P
LbXdsD5E3g6SsH5b7T982IK2q4xztU1E44EOJEhiQd8Si5koGY/EVF9CBwgOt2IN0h8SoODih1lv
R2sn2905QF1+QgVd7mLsb9HIAze4EbBaa3pk4k+UehIDfVZHCNrhlAfdLfsSkiXDDbcturwUjOx8
N4R/I2CUlNsAVmmvka1jBBz15cGpvamvwNynvqHIvVIjlKOl1Q+2Za+If3z98QhCBXdIRUDapbe5
J3StCpOr+EV8CpJEYeKSewVaKOlfwE07Ph4Q/K1GWTxAG0mrwWnN24kw1ghRM/LOPtqbpHUiNj4X
ZnqLih/37dioAtysMuXnVOE2DuWJp/vT7duW73iZAHeE2Xno/ptUpt1knMeNCL0bvUXf+dIuVoZK
eBZP/G3iseKuhuti5ZibcLejvCtJLdKkdSqgYpI/Fyo4EPtv4IETNLC4FjhbfZPzjSGymqxTamsl
/oeOYh3aikBQQ6Fc5JaqmVec3b2ClCE5YbZveE1IrOrdrNyO778yDns1fbEeBGZZMBLR4p7Zurtg
TVUExm41PCNvDlZ8BEsfB/ZD/m/xy5ojNvb+VrY66enNpZ56PEF9NkbixWQzE+qxf+CjBkRbSPQw
LtiDCvyp8IIXvEjgf6TwZdEABVkzCVL36h+npLYxDWTcdbvg00hnYv6N0X2yoojmm4DjdMiQqn9O
Y34tXU/4FIMgsnSSLs42WpRI758Qhe8oyRYeZA9oIizyU7ZnxYTZwUevMpoDtUqV08WlWbefdACT
W5B2o9Zm8aYq3oWMXOij1EtpwLPW8c9bCv74MMa1ahpBG1wnOge5GzHq+DWTFr4ONVXrSKSeHcaw
gjxYhkmAKpSBHIHf7ngx4/Z0/VRhBcuvIIkhvQc4BzdQjcJVlCfdLswoEoDnh/4mpwa9/UNkBM54
0Pl2ep3XUe0Sz/n6v38BigemScpks/GeqbSnZsqzh3UOYLnTPYXiKdhH9K1dgTzfbXvA622qqPjc
Sm7Oh8iG50hY1YceI6gOsJESUcr3PBSO0UvHQEGuF6dWhGAj9wX2xVLfjiSBy1WxiW9DpuNu6O8d
tdb66LSN7yq7p2VrNGPkn7EFAiWPdQqfDcpMIReRPaDQxC+QKH5tqcgdaZ5zgoUBFirfgWQwc4YA
j1v1BJ1CrpNH4p5+oHeT2IIHjBph7mwKviN1B8O0FjTTir8WQ/LfBkg/4ao2AgrP3sjn9nmW4ebF
NcUbX6nZhB4i28OVg69brEmlEusJ3y2cNkpMbSw6CO6MaVhz6ADimKNtxrvoWe8+whg3mmtuKnJw
u6ylsEW3TKcpykipzIRAvu0ggjhFCbXrODi74WtD/2zy/Dr+AoLWGb+kpMTK53c3PFGO0d2AF++y
SfvOu4k5ckwd08V9Avj4xJ59ni3wsgqXM6tRVgPM9WYVURMxTH41C74xCIImEdvwtAbxOLOUpl86
0dBJ9w9Bl8oTCC7x4sS8zz5zPVE1iw3wBkdp2Zl8sWnWuNQW+Y3sPNWK8d8j60c5JRo4MbhSLdUd
irSpU8lOwW6rBetdmjnGMCvwINmWFIWlOy3SaCYzJCLpb8LwLcN9Iy0EVHWtfSj2cQOLm98kt7n2
WmBAnUR01VPxoJ09o5L47FSsvzGZ85UuK13QnIl2Hg2JgT/RN77TeEJi3pS9k3ITLFr6kTys2QZO
2i5euI7Ustg7pbvoDmhwB/ORCB33xp1jUU78MM/Pb0vLzq7GRIWyAEgbMjQptkJKFuqvaB6VRPcJ
48m8XMAOgM5PltZGUQdPia/G/JTckCp93dHTheYxN0A2h2swIrvdehPPPKHtrfqbI0dNzG1wj8Li
ZVWPev66yuRwOpnHCy2z06rY+bjRQx0CMlaDip/7kbzV9fHTd8pv8cc3YmKh3SlWHIwezZ4goQ7I
3Gar3J5cg3B3wLCaNvo7bE4KiCalleKfcaJXNKe6dxl8j/APuIvA6qoEWEcRtVJYoKPioyhJUulS
cZt39OrBH0+32Ip7Tdi5x251J2Z8v0ajCg8Ga+FgUrxzejRxBplKKvVEXcJ3rFLpt0rqd2Oo4LMf
kVEkScLzr3pTvJ4B6+7LgIh5AwTg871VwS1WmGuE62h0PM8wuxMQG3S0XU4Z8IBN77FOKe3DTVCY
tTN/vKeSFBerEIf0urLVfqU81rFOs6lcUtFmAYKgOmGN1jY1e/+F2EcAqRNV8KfVBEue8Z+/81Hs
2f+AfrgOk7jcycBIONfpnT5fbjTfM50p6i5mWIOK3iCCouguichUwk/11BGBwYOLbUCr8Dcwobxs
INQv5/WgqJYYcfpia826Jbvr7heclF173HRYCRQZi1EodIkm9faw5paas+8Z3s3GZzWMjtRagM9E
wEsOq0F12Z/1UhjbmI6xUYXNnh6tSbFz55+PEYQrsohO9iYBcuQgfYjbkCf3PMNevPRpKvVsmZ3e
b7gRmDhLsXjigyoVZzbBCVsIonwzhFjRDrlb9fI5bMQt3jYi2dcHSdqcFtrYvM/1hfRy78Jhm/m1
gOqJmbAhY5nbm4LFHacsJdDYioqqncZ7uuPDpkBY55NiOiEQ/LuzSndmj0Uq+jk4CojHN1yUS/1l
heD6jn4yXhzI3q1+5RmJOmiHfJn2+TDddU8VBrpsShxMVoa+v915Y1jo1K3gOU3qSG2DO6/lB1aa
y7wfW1q9nJBd5OJInDtdlSBTxLbG5NyKuWDyRFEQq78sO1R/+hnxlJqZzA3mQ5GI8U0Ptor91yun
NB+wnS+/4+bWZE5v+EmyJr9i4oGVKe3ikhFGbF3KsF5HtzUqAt+huqK7WVNivGQe2V6Qn0c7j/Rv
MKtaRO05nHKfgCfLLqRC6zPRrpzjD/RaxbSdbnkXAhKAJHVwsLs86m0vX4dIMigwVwk8G0tjWU+o
GAIomsZQeMSmc5oyJeUIgfrOzUNNNPxp5wTLIaVMczMCH7dEzsQuml31eWTHZzuqPUFsMDlfsd9i
a48FioJSVGFZxcRy8DZU2x/jJxqowhcV7sECVBxPOD/bi0mxWHzZZdGXcRUyy2yOg9SsaOxL9Lpo
6bIc7buHYPISgGEGITVqesqQnkSTlGCDJDfC6uDJzMM8MbeUNJuM+c8EHa8u/FGc53iUHur2qkEe
cYymG+0UOpeBey0QwP6z/Hbl2383aN8+ycG2/qWmdGs0fE0qp/uIY8n50FOEPl1rDzeQXrKO36MB
rlcfHuNNKl2AM0M1TQPJYeAKtjYHzRATSiJi5uTSrpWbltwHpwKSDoo1XN1sAwWP0jFIWde/h8bq
ibAwK00jksfwlcpSu2iBT0xzfLBSl0kDoa9A8oPd8T3w3SG2yUsyUlZyHxOfRjDw5LeQ9dv3KtX9
mzmkW+jbkXikwy42kMLb13/btOu65vc2Bx7vPO+OLg5TPtFcvL/fq7zI3bfDbhXWxGtVMq1pnpPp
E7wjCfpOEhsf76imvuDYbL9nJnE+fuvmqu+mnfU2yqHvSaGd0WbTNYnIy67Qe10Ca5UthVHDSXYw
IIWUvGT0MBF4+b8RY89vrjGKfWIOK0TiaDP32MAM/K0mYSd3W4lMiWcenEROCCeWarJmTx5V46oX
GVu6ZXitEG8oT9qtj9TPgTApMklndbs1F3twyJ4pHfH9yJbiD/4NrI+d97PImdhD2kUfjpoaMvAL
v4ruwvvUZdbSXJH9rIjmnlO48XUq3CcR41otI0yNreAqy13PMNWroBUVcWGNL8Oa1QW0z4jVQRDo
Kz1DcOsWrS7Dux6u7FCcMcj1Zk8gai9il5cYhOTOYWsKOw6/+JiMbK1ngvF4zteEvcNj3vMTSLyz
MM80pwddMxRYHMLWpmnXgv+IQVn67bzMPpKhId00l4/Z+7k+mlcG68akqvhbQpXYOrd4bjjswOwF
QKBNHChTCYJXTlGmwuWX+2MY0b5OdSCRmIFKOK3NpwIMvpIuD1ABiw4yriRyMjjdbMpl4AURCYmP
tXoxO54dqcPyin+y5HadtWkXRSQkpUC95k5salWzy0VJIePM3tkstbF+K5zYXwk2aofcX9rk8cQX
EyfNbYzUlVwbRvSRuuDf92S5ygPSXwFKhgUX5GGUIIf/yX8+CZfR11K2ADzEwoG1sl21O2gi9eIV
9ct/vegpvr9RL+jSHFjHqHm7WcWDALs4z/FGZz2BGc6Q1zFUQGnaMPu8fGolndGIBld2pKCqXgi2
OVAucwEh+uRS8zHANNurU43l9XVM4hXCUtYEeSYSUC+mDwTajLyP1nUwsm8grJkV8LOhmItWqkYe
BOKSG+L4rO3J5yuyDG13
`protect end_protected
| bsd-2-clause | 6e67d6209d88cb36f1802cdad4f7e188 | 0.940719 | 1.838841 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/dc_ss.vhd | 19 | 8,726 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
nnA1LvIFtXuhnEgnrDveU5DQhO4oCdS4/TzHWVjuSWRiJTWamPLe1zKRcIJ3OgsD949QJsbaygaN
jpuk7BYNZQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Cfy8I58fHjYLB4BFaw/VxzidETwabyuF6c2nxAde+hbLnyzOfkymKdOr4Pk5oDTY4htTgTDRWzMe
dytGdfmZXjp6SJIGysindi/Logxabu2rWzFmbsNC3Q0gro5se9+3qoriCL3M82gnhvX/joJNLiXg
rsFmmSylhS6v32W24xg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Gu3bZVKL/oo3WMbeK5OSi9dLiGmyQy2yONRw6Nst9yei3DenlP6wnhfHYdkStFXi/uvWUBEeZ7hN
0Bmqlib8vQ0eJP09mki40prhGAwrKuqYt+2JunlvLYMjlmKGJOXPgQJfoYTNzbZDTWMAPlUaZkK1
oZkHNa3Wtk5m49sk7N6rE0lY6V2L8UfgTL/MmCwu7DKHNfTBd2W2KricGJ6ICGb/eh21T7mo+KTw
su5JPh2xN6VOnDqK2JFdz2Fe2UsNNdpq35qIZsc5dRna+xfhp64zhbzGUq3oNeTCYYFL7/rkWyjk
xMfq+Y7aGpW1qrNdKLCLUa3C0oRubzA+yEUHPg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CjIoJO7bPG0vgefcLg3HndCtGBfDCnGBCSVZItM/kv6K6ZpvJnvEpEF/v7GEKszxgiutC8bTrPRk
/jMI//klbN/ln/AMlW7lDqpJ5wXp83c77tloVq04bnPwc3DaApr08oK3Bf1H6JgBuFfaRFUfxoRB
6anIIq6YC6xrV65+910=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
D/ZhWxzQ+2vaiYn3/fV/u9o/WEb/ogG/V9KccsPCOCWeaD6JXzbX1wTvk2mHL3gwIIjopxpeK8ct
Dd/kho1WYC462ZEZ1ijvlrdcQ6jRucbVeVK20vWFMC1CO9YW54zFCdUIFDYoBjMQnJ6IU90guAMg
K2P3LVnqKNh7XA5585Xm34QBVEtkbFVGa/nBjX2k27AaOcjv8CeFc7ihUp4B6D6YzM34GhHkOxNj
NyMvVJlZ5HBA7JHakPw8PSgdpMIr12xEOrEcLpR4AR6H6hPW9blh2XXVPneGey+XXrhV6WAB7P2G
TGbniILS+ojY57htkmkMwgWfAakIRm5HfiYkdw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
HNY+SCOjRvVbNph/2TXQYH+8YYYEqcF6WlQuvQz1d5KZ3S5t3pc6Dim9soZ7UhulAUQmU5h6A1i5
bEGw6wK0JqUbwtjt1oqf9IlfKe1OYez0KNf0BGo4CoPMv8oYGngTyaMOik5FYJYNuIetFKWbQWti
p1t1EDcva/5HLfvIiizqct0cS76+gdoCJOjzBIBWoIHZM8IdNqzezWrhkaSe2cNcWoCpn0ZhV4F/
UZTbJAzwvIc3czV/YJunaG4IqUat65b+YmPdwWiWuPKBEEkEK7pRTbRfklFAW+3KW4Jf4suAzkeE
rz0zA/kVm/7mLiCCapdzG8kO2KrBiKvNLT3WUmqN+2+Qwyj9fRtg98nQjiHih0MMZofs4hP6lpJJ
vYgma9yQrE4TmlAcDKw7oDvbWG7s76haFdH7rjlNCcwOk+krKOJvGSo46rA33BamVeBd50Slr1sH
7T6kaTH9gpqsMPm+Kel1HTubYumZvi2uHzEP+LDb147scpSM4G1RVRJAeQjIbYX3CtVtKsBpMUW/
bkziTmeMdtuHld8bUYIn5DgJkBGXcsKV3RG+Tbbqu5HH8d3J8slfkuBlDdi7tb2UUDefkvHa1KjJ
nV15R5iuSPmC2f1D7kmAFQK+8afV0wKbXj0WTNvoEsYnUtAcVJCzi6psVbFTYmfhG1it9BdnbBea
dneWp4AkwLPIM8/g9IbX8TeFZhjX5+5PHL3bhUcnb4Q6MlCd+5YPFZrM4OYCQRyogfZRRhND0uEj
jGvEGly+oTBdkhugXH9yTKWcDYPE+QB3H77kpq3D3ZBCvlGXrIvNJlboMAIlEe5XMUeq0uVpKUL2
xa3te50wjocRb69fjcA/mfYFYPA/+R0MYXDDBv/vMALxXlG5h4uSA/Zzsw3pEmc6E6EvtQRjGXCF
muxKqwZnE1wVRu45Fn510aWxUhUyr3j4JRbSykfyZgf7ttqyFujF9WDqQJ2d2sCbbAZbujh2Inmu
/EPL5DbRO8uX4vz9hjAFJcQ+HmVGZ2aklfCHqpGK83J7uTe9gRL3do3UzQecmBpIWbSWPKBDbzy3
I1g+H6CDcsdbJ77+WeGDokFZNlRPGbeD+TWsMergNlC+dcF8NGuu7zi4rD/Sx8tBFFrtYrkGQpyL
2uHfxYM6Kxlyil728jseh1DmI4pbwgD8FiQwsw/wjUs/NewabpERwEph9ADAnMOQIXFnkhZDfCS+
2pcZCJY6EzTWYQwgnklCshEvEnTnz863Dv70xIYeAZ94rieuw62mr9lTEBr6VIOY6w/DpXRoeItD
msp9h2IFeNJkX+SUlhpyhJBcca/TKN87ruNVQ7lbEPle3Zu4xuZboIWvLjMxH1aacD2mj9QKDdDR
KrQ/NxA1pUZNxOYKvqlXwYdC0ryVsej3OKSMvauHd7IMYVzqpimXB6L7+2Fqk155SdQ3pb0nS4w1
7Qc3RO8plVfkjhUluACdHovxRE8SBLzYameFBmteP/UZhUeflmSHTStj/aDJDVRbMqWcwowl9R2W
v36PUSGMYBvEQ+ArNJM6Itke/AtYzJiwpHeCxoKQBWMdDpDhZQt+j0bLyBOdv4t8ffvujyGLu2OB
qth/K/5ceKZTcPMQi1v81Xp6RJFsajildLoGWvkRlhROFezR/OnoliAnfIZ0HGf7qXHopSwV24zb
Rev5v5lkVnbTLiogX/uOGQuMAjzXn8tyKGV9aQI6G0PKWEiw9E3vraZDdQyBIOWlnH2dUgVrFlqg
7HRLfJqzzhEMJIz05UhJMonpy9caS/jm2cE6viJVMV4WqL3eVAlG3K163W9J3E7ePxRDDPePKn0e
2Qiqk2qDeQ0+axy+QDZyWea0JKST6rOdIyiLUsutCL416t09CgGiqomq/XLyLN8tj+ODK/2Qfl7g
OlIe0nGrScIi2apGk3jHPVa0WMBGr8U8Mnfs1ngoLW6EBHUiVVvtvPsAkXgU/hPtrMiBvx/c9Cx6
zAKNT8mtWxwr/H1ylQOLRFrfj3scDB5TGxI/lX/Ls43ZdTxWqLF7qRMcJDH1Tr0miRKtEqqa3UBf
mScRalNZSaLGv1844ZZjA3RAvqs8Q92/n+b2RD/THdto7lbFbXTkdTTcAsr3e2EFEGvfpmPuMwB4
wqLt80j7FmDjk7PVTeYadIcHWnf2/rf8WHKIlzxUZKSMq0/F0sgPS/vcfu53XsLrf/27UTqMNtQx
1HYRHWxbYSMG3WsN58QFlaJ2qXKMqp7zG48BV1UH5fLyCBzDf3Xo/w/gOR/t57C2/jvwgErptDrO
/DqB4CDDwo9N6N4Lt2tNl0w91kwt+5fpLUOV2XIS95nYSX2eD0i4NcoHIPSM8aUmk3jtzQjoMGSB
fk+fe4NBnc3MKhp1mgjH57juQeW3Uhva7P8RMEsfrw0t/RbOMf/ViEXOMMPwUq0FoNYJMqoeIoAR
b5HiBAA9t3TgPdHDcYxpqZbdHRaNoLAYrduTuk4UBA8ivJnnUxR2LzOfBvqDNEnZulhsZv3vzfI+
q7TIJiq7LQ8yOK7arPCqlv0p+klxeSjE2Xe6YeirHzuEb/z3RGa4/tlk03gtnRLW/TkB3EtOwOrI
klBw9HjyHuuIjb7l+YZnN7cmWxlKwI7G6I0pf7gn1G8hl2KEHlHh7701lkh7UHL3ljDYwVKOcNbL
5RSTbIncz0KCZSFxM57l7ywz4hxsqliXpVQFWP87ILwhMVY+Lz1sRDC0uOjDlymBujpO02V3/0XJ
JJr9LYy5+HtH3fGlVN5fMdKc4L7gdpJvKi0XC8oLyczexJniAj+cMsrCOKA2esHuETBMmVIrHXZ9
5MEmc2M7rCANDQb4TfOIP/bYHziRwd4nnzf1tnL/Z5Au6+Mhf6weE3Mjsn/oormRVneJHOpq+0t7
nX2dCBcKYtjHgJbXNuS8FrphDyTMISqOc8Tzbc86p37z/Exn3fD0fCouT2mu1FNuh0BY6OBAHQNJ
idCJfzF/DLxu+H7mkc1a+K4tYwTDPQ1gITyhBMPmNWpmVu5Bo6ya4k2r8zCSiSuQQj3/QyCd7WMv
RoWkb6nDyH1j4O4RyRsmsD47Ptz0hH26uhOU5bxLn88Z4Wp1eqwpv5HOlo6noHnaeTSx8d2uY7XH
OclrNT73cDst76AhvuhDclpSfjypCQnvMQNh13Ie571skBZ2vCuzWFUwu/wNsm9KJKKBVts2WgqB
Vo/WZHExGsliz5Nf7LyaoeJPxSNoVXEM/biuXGZcVXsPDDq5cLhmmmX+KnhGoJLIcZy/Fv5y3+H9
YSOZvL1r+Uw66v8TKnIq4aoyVSTo9obpcehnyQ4hErZeamNtFF0Jv7W8KNKXhvCPq7ZpjUjzroJs
qzPcvuZsp+hm22J9hlg/PcsuX6gotz3xAGSf+rbsV8vf1vjCU1h1svvlFKJnH5mLBmgxPKkcOa5U
DA4JkqnN+a5pIZGX/s4kRNJz7xcqZafZBQCd98WZpDjthXU7SKnEHdKSbNff3stl7HH/sCFELwNO
mGwm59pmXSqAerrhqYHMILWXk+COAldqDe5iyvWqklhowyoKyWViEhC6lt8+LqLhB5B8OG4kQkgm
SAe936RmydVgfuGGFb22ZwBieURMtPC7e6CoeGna9GzN/40pBCcrZDEIk7uSiRwGDOldBUctNPQz
2nHYynvrZzSxdMDWd6e4EUvcmBMUz2+4R8ITxmBpe26igQIb7mfzGIxfomdISVx+wN1XH/wn9fub
lx2Je/gOXXRah1KzTveO1+YoW9Go3TL/sIJ7M4tPQOiHsKz2HV6AtPYzuoXsfMx1bfygf+oGFK2Z
GtqDv0mDIh1OwLJhel8541VS0sa1YlzRXDWoIhugwK1FvLC2nvneHxLKWeCIaw6CFaMYSB+6oKGM
YBM/PHkVf+jabj44CJePN/sf+cidZ8if3IsksSNhBe65jFXLlcZY7qhhdrzaINzT4a6wnnvj9ViY
+Mf0z1roXDQoEFc0+l3iZHBuVNZAsp0xfBBHJ+dGO/j7uT+J6NXzL0BS0NuqDANwOOTK74MT1LWH
W3+WyzpniwLAHDJChat4PfBiaqp0cl1FdujfGpSJGwZa0gn4+hgB+pQzblWg2WOTUGNFRDazSbbo
ExT0vyQ/UHpg/cHTdJYJKhs4OJMKG5G0FZN6gjCAfCZSfVho3VTkTiVgoIPyqdIiPyAWaNXCwh5H
WeHgPIbnsWt/Al8ikfzqYksN6MtMucjtys/S9MgoTgG7WfOiFoghIf2u6fphW+FG1eQWtGjQmnz9
qaqolciJ7OPotKkSatkVi9nVvMOnbxoScaoW6PFx3Ma60l5IvVVjU0SNVEBdceeaq9AIJy4s7feO
zMVYKd9nYp/neKjVTNECiFByB3ypYajx1Gz1sRg7ZQwPkbGHV8oltQ0UqYV9tkZ60hrrjodu0+uh
8cg9vOiTIFTgJXLXAF8G8ANMKpmQFHWPr/cevh+mOMPBJTl1XUl9ZSUDvznupY/2S2YDSSgfMjfF
b3WTqKEDNNVMll0h0Fiwd7maiamY3SHpQWqEaNNT6JOOPXonTFawWU+V87gcpNSBWgWGPg0/2rev
36FIEVgi1t6gWMBWT2NKYMyo6k7NFZyckrajg/jh5TlIcDrIzWtC5fHlaE/5So+k1ly39w/SSRaD
kikDwmgjunoPJEPxNN/DzKossxizyj8pmUCW2fkrZwyVm0VfathHcYoccCHPjkstzRW9iBAlGl6y
nXrm1vg5hKghTPMrCzMfJgW6pPYD2yqYY+cLfXgutxpfYpOsI88UFfFyAqPCfhAazwnj6hCZnJaN
QnDCOBTb3vj6jk7rmqJ0bL1ftnZOhAYSHnu+yAMVle0J8ZCEqMeB58HrNOF2ellivc3vJn7idWPM
E9u3pT/f8tgfbK2Rb6ObG4SuS4l5i0RZbuKpqFRKF/N5yBcbuKrhjwFkMh2yvSu4QdtPRK5f+ucj
aA1jSBnGGurHbaJP4Idqut2r7T15wqIn1ApOOfru+hMnAP3hf1Qs8Q5n2iTTlxJENXeBZzWYqm12
2N1n8t28xI6Sn33zRPe16kpa1ffP8Uk/oeqJuqZzJDp7WJQ1KLstfKEyv/KujaQhWKrCIj31KOEF
fIHmYlvhNtjx9cjrTlV96e/9bS3oHcDvTPJrLyk4GqztOiSFYGNpqtLwMqa09t7463LgYe7nqwmK
m1zqjIe3N71O9o7uZDEou0qf/pBV3fR6x8yG+dubIJX/OoYcR9gCkGOwrqdbHZ+o6MoxcM95cptI
3RE6NsZdphCTEgTVpozPpufBFLM4QJaUe9kwmZBj+g1msYMmcKIWU6w2GWtsrJhU0PKWYvfuFOGk
LShMeeLACbKpr19fvk5lU8NsQ5GmREXdNOG3s1qXA7OumXzkVPGS2Deg9xufD50buKmQPGxPiuvq
joPBej5P2RQujn/gTelJ/lZlHuf61NCaVVaG6/2+zln2kIvQ6mNfPRO55G+3rRciT7DTvPQ14bLy
h2wSaysVZ38jGwYZPdg/ahj6iKf/IOcRXBangV0qgpYYDICgVXAkL6RcJo7giKPmwxFVSsrSriuE
WAsyQGfAUD02UY5bodUDgTzNimzi+/iTUn48Xf+R1VZxTRXHBS8yFfgLAxvWokqdpJsKFXk+QIOw
IAqUDmxENPMr9Gqj+2Rgvb0qjYPLNqTIc0Lksr6qfsirnOgrRarq9TWtWrWWEskbp2oGu+oO2AvU
NTgddR8e9INabHZK3ba/x+OfgYn+gDs5WBlrYW9IH7HkcUMG/TAKG1FxB12i+LONoSF6pP3ey2Jw
OEO1EXUWmtUWJj6nIcME/qNQDeNfhT4EiJO4dJ/oSMnc3jbjNrfAdtun8GOzrmIN+jinJQFTy9n0
XNhSUSMGUelIFZh0s1Lfc6nN2ha9eToApdKeiXjOYXYXqR00+Bhl9SZDhNgxhjCWhZZarlXgoHBQ
G1+gcTQ4j3iOXEz44cr3/nxX0mtTmWBetPVrxCcLK6zRPTcXSHQNrxU8WG/yby7hqceH+HmSIIdl
XwNJXOZMDiW+PZ8Ly789xIwt9Qpv8WCJ9kFxz1adG8ngtdavviP9Vv1Eju1opE/eEB9HhyNtCWXv
PRGCJGHv+eWOJ7Nn74UVkXB9HT4+BxVNz86kJAOnYiPSxxEFPMDBLHH/zRxVSlxYZc4Lo9r8f1UT
EX6/3BthH9sTCA37+nw+naGI2wvWYo97OsnZX+oYSuNOSvJvAzlWZRo+MT9ccmPiYsNaUPleiil5
GP/hZSp4g+5LCw/xiULJNmK6WFzBILqCEaKE9EXIESs83Qhb0w953qQtQifv9g==
`protect end_protected
| bsd-2-clause | 1db40d7ef8e35d347346f2470b8b6abe | 0.918863 | 1.932241 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd | 1 | 11,869 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
| mit | 5c53bff14b411d46ae06269bbc5ab75e | 0.448058 | 4.460353 | false | false | false | false |
szanni/aeshw | aes-core/key_expander.vhd | 1 | 4,733 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:58:47 06/29/2014
-- Design Name:
-- Module Name: key_expander - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.types.all;
use work.sbox.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key_expander is
port (
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
rcon_in : in byte;
key_in : in state;
key_out : out state
);
function rcon(d_in : byte ) return byte is
constant rcon_lut : lut := (
x"8D", x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36", x"6C", x"D8", x"AB", x"4D", x"9A",
x"2F", x"5E", x"BC", x"63", x"C6", x"97", x"35", x"6A", x"D4", x"B3", x"7D", x"FA", x"EF", x"C5", x"91", x"39",
x"72", x"E4", x"D3", x"BD", x"61", x"C2", x"9F", x"25", x"4A", x"94", x"33", x"66", x"CC", x"83", x"1D", x"3A",
x"74", x"E8", x"CB", x"8D", x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36", x"6C", x"D8",
x"AB", x"4D", x"9A", x"2F", x"5E", x"BC", x"63", x"C6", x"97", x"35", x"6A", x"D4", x"B3", x"7D", x"FA", x"EF",
x"C5", x"91", x"39", x"72", x"E4", x"D3", x"BD", x"61", x"C2", x"9F", x"25", x"4A", x"94", x"33", x"66", x"CC",
x"83", x"1D", x"3A", x"74", x"E8", x"CB", x"8D", x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B",
x"36", x"6C", x"D8", x"AB", x"4D", x"9A", x"2F", x"5E", x"BC", x"63", x"C6", x"97", x"35", x"6A", x"D4", x"B3",
x"7D", x"FA", x"EF", x"C5", x"91", x"39", x"72", x"E4", x"D3", x"BD", x"61", x"C2", x"9F", x"25", x"4A", x"94",
x"33", x"66", x"CC", x"83", x"1D", x"3A", x"74", x"E8", x"CB", x"8D", x"01", x"02", x"04", x"08", x"10", x"20",
x"40", x"80", x"1B", x"36", x"6C", x"D8", x"AB", x"4D", x"9A", x"2F", x"5E", x"BC", x"63", x"C6", x"97", x"35",
x"6A", x"D4", x"B3", x"7D", x"FA", x"EF", x"C5", x"91", x"39", x"72", x"E4", x"D3", x"BD", x"61", x"C2", x"9F",
x"25", x"4A", x"94", x"33", x"66", x"CC", x"83", x"1D", x"3A", x"74", x"E8", x"CB", x"8D", x"01", x"02", x"04",
x"08", x"10", x"20", x"40", x"80", x"1B", x"36", x"6C", x"D8", x"AB", x"4D", x"9A", x"2F", x"5E", x"BC", x"63",
x"C6", x"97", x"35", x"6A", x"D4", x"B3", x"7D", x"FA", x"EF", x"C5", x"91", x"39", x"72", x"E4", x"D3", x"BD",
x"61", x"C2", x"9F", x"25", x"4A", x"94", x"33", x"66", x"CC", x"83", x"1D", x"3A", x"74", x"E8", x"CB", x"8D"
);
begin
return rcon_lut(to_integer(unsigned(d_in)));
end rcon;
function sub_word (d_in : word) return word is
variable t_in, t_out : w_list;
begin
t_in := to_w_list(d_in);
for i in 0 to 3 loop
t_out(i):= sbox(t_in(i));
end loop;
return to_word(t_out);
end sub_word;
function rot_word (d_in : word) return word is
variable t_in, t_out : w_list;
begin
t_in := to_w_list(d_in);
t_out := w_list(t_in(1 to 3) & t_in(0));
return to_word(t_out);
end rot_word;
end key_expander;
architecture Behavioral of key_expander is
signal col_0, col_1, col_2, col_3 : word;
signal col_0_new, col_1_new, col_2_new, col_3_new : word;
signal tmp : word;
signal state_list : s_list;
signal exp_sn_out : state;
signal reg_D, reg_Q : state;
begin
col_0 <= state_column(reg_Q, 0);
col_1 <= state_column(reg_Q, 1);
col_2 <= state_column(reg_Q, 2);
col_3 <= state_column(reg_Q, 3);
tmp <= sub_word(rot_word(col_3)) xor (rcon(rcon_in) & x"000000");
col_0_new <= tmp xor col_0;
col_1_new <= col_0_new xor col_1;
col_2_new <= col_1_new xor col_2;
col_3_new <= col_2_new xor col_3;
exp_sn_out <= col_0_new & col_1_new & col_2_new & col_3_new;
mux_4_1 : process(y, key_in, exp_sn_out, reg_Q)
begin
case y is
when "00" => reg_D <= key_in;
when "01" => reg_D <= exp_sn_out;
when others => reg_D <= reg_Q;
end case;
end process mux_4_1;
reg : process (reset, clk, reg_D)
begin
if reset = '1' then
reg_Q <= (others => '0');
elsif rising_edge(clk) then
reg_Q <= reg_D;
end if;
end process reg;
key_out <= reg_Q;
end Behavioral;
| bsd-2-clause | acd7a55c3c8fd326d63fa111e5056e98 | 0.504754 | 2.187153 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ethlib/eth_rstgen.vhd | 4 | 2,298 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: eth_rstgen
-- File: eth_rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity eth_rstgen is
generic (acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end;
architecture rtl of eth_rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst : std_ulogic;
attribute equivalent_register_removal : string;
attribute keep : string;
attribute equivalent_register_removal of r : signal is "no";
attribute equivalent_register_removal of rst : signal is "no";
attribute keep of r : signal is "true";
attribute keep of rst : signal is "true";
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
reg1 : process (clk, rst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstout <= r(4) and r(3) and r(2);
end if;
if rst = '0' then r <= "00000"; rstout <= '0'; end if;
end process;
end;
| apache-2.0 | a49a4eeca53bcc2f35b2ee9071869783 | 0.610531 | 4.045775 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/tap_jtag.vhd | 1 | 10,868 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity tap_jtag is
port (
nrst : in std_logic;
clk : in std_logic;
i_tck : in std_logic; -- in: Test Clock
i_ntrst : in std_logic;
i_tms : in std_logic; -- in: Test Mode State
i_tdi : in std_logic; -- in: Test Data Input
o_tdo : out std_logic; -- out: Test Data Output
o_jtag_vref : out std_logic;
-- DMI interface
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of tap_jtag is
constant ADDBITS : integer := 10;
type dmi_req_state_type is (
DMIREQ_IDLE,
DMIREQ_SYNC_START,
DMIREQ_START,
DMIREQ_WAIT_READ_RESP,
DMIREQ_SYNC_RESP
);
type tckpreg_type is record
dmishft : std_logic_vector(40 downto 0);
datashft : std_logic_vector(32 downto 0);
done_sync : std_ulogic;
prun : std_ulogic;
inshift : std_ulogic;
holdn : std_ulogic;
end record;
type tcknreg_type is record
run: std_ulogic;
done_sync1: std_ulogic;
qual_rdata: std_ulogic;
addrlo : std_logic_vector(ADDBITS-1 downto 2);
data : std_logic_vector(32 downto 0);
end record;
type axireg_type is record
run_sync: std_logic_vector(1 downto 0);
qual_dreg: std_ulogic;
qual_dmireg: std_ulogic;
dmireg: std_logic_vector(40 downto 0);
dreg: std_logic_vector(31 downto 0);
done: std_ulogic;
dmi_req_state : dmi_req_state_type;
end record;
signal ar, arin : axireg_type;
signal tpr, tprin: tckpreg_type;
signal tnr, tnrin: tcknreg_type;
signal qual_rdata, rdataq: std_logic_vector(31 downto 0);
signal qual_dreg, dregq: std_logic_vector(31 downto 0);
signal qual_dmireg, dmiregq: std_logic_vector(40 downto 0);
signal dma_response : dma_response_type;
signal tapi_tdo : std_logic;
signal tapo_rst : std_logic;
signal tapo_tck : std_logic;
signal tapo_tdi : std_logic;
signal tapo_inst : std_logic_vector(4 downto 0);
signal tapo_capt : std_logic;
signal tapo_shft : std_logic;
signal tapo_upd : std_logic;
signal tapo_xsel1 : std_logic;
signal tapo_xsel2 : std_logic;
attribute syn_keep: boolean;
attribute syn_keep of rdataq : signal is true;
attribute syn_keep of dregq : signal is true;
attribute syn_keep of dmiregq : signal is true;
component dcom_jtag is generic (
id : std_logic_vector(31 downto 0) := X"01040093"
);
port (
rst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(4 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
begin
qual_rdata <= (others => tnr.qual_rdata);
rdataq <= not (ar.dreg(31 downto 0) and qual_rdata(31 downto 0));
qual_dreg <= (others => ar.qual_dreg);
dregq <= not (tnr.data(31 downto 0) and qual_dreg(31 downto 0));
qual_dmireg <= (others => ar.qual_dmireg);
dmiregq <= not (tpr.dmishft and qual_dmireg);
comb : process (nrst, ar, dma_response,
tapo_tck, tapo_tdi, tapo_inst, tapo_rst, tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2,
i_dmi_req_ready, i_dmi_resp_valid, i_dmi_rdata,
tpr, tnr, dmiregq, dregq, rdataq)
variable av : axireg_type;
variable tpv : tckpreg_type;
variable tnv : tcknreg_type;
variable dsel : std_ulogic;
variable vtapi_tdo : std_logic;
variable write, seq : std_ulogic;
variable v_dmi_req_valid : std_logic;
variable v_dmi_write : std_logic;
variable vb_dmi_addr : std_logic_vector(6 downto 0);
variable vb_dmi_wdata : std_logic_vector(31 downto 0);
variable vb_dmi_resp_ready : std_logic;
variable wb_dma_response : dma_response_type;
begin
av := ar;
tpv := tpr;
tnv := tnr;
---------------------------------------------------------------------------
-- TCK side logic
---------------------------------------------------------------------------
dsel := tapo_xsel2;
vtapi_tdo := tpr.dmishft(0);
if dsel='1' then
vtapi_tdo := tpr.datashft(0) and tpr.holdn;
end if;
write := tpr.dmishft(34);
seq := tpr.datashft(32);
-- Sync regs using alternating phases
tnv.done_sync1 := ar.done;
tpv.done_sync := tnr.done_sync1;
-- Data CDC
if tnr.qual_rdata='1' then
-- tpv.datashft(32 downto 0) := '1' & (not rdataq);
tpv.dmishft(33 downto 0) := (not rdataq) & "00"; -- 00=status OK
end if;
-- Track whether we're in the middle of shifting
if tapo_shft = '1' then
tpv.inshift:='1';
end if;
if tapo_upd = '1' then
tpv.inshift:='0';
end if;
if tapo_shft = '1' then
if tapo_xsel1 = '1' and tpr.prun='0' then
tpv.dmishft(40 downto 0) := tapo_tdi & tpr.dmishft(40 downto 1);
end if;
if dsel = '1' and tpr.holdn='1' then
tpv.datashft(32 downto 0) := tapo_tdi & tpr.datashft(32 downto 1);
end if;
end if;
if tnr.run='0' then
tpv.holdn := '1';
end if;
tpv.prun := tnr.run;
if tpr.prun='0' then
tnv.qual_rdata := '0';
if tapo_shft = '0' and tapo_upd = '1' then
if dsel = '1' then
tnv.data := tpr.datashft;
end if;
if tapo_xsel1 = '1' then
tpv.holdn := '0';
tnv.run := '1';
end if;
if (dsel and (write or (not write and seq))) = '1' then
tnv.run := '1';
if (seq and not write) = '1' then
tnv.addrlo := tnr.addrlo + 1;
tpv.holdn := '0';
end if;
end if;
end if;
else
if tpr.done_sync='1' and tpv.inshift='0' then
tnv.run := '0';
tnv.qual_rdata := '1';
end if;
end if;
if tapo_rst = '1' then
tpv.inshift := '0';
tnv.run := '0';
end if;
av.qual_dreg := '0';
av.qual_dmireg := '0';
v_dmi_req_valid := '0';
v_dmi_write := '0';
vb_dmi_addr := (others => '0');
vb_dmi_wdata := (others => '0');
vb_dmi_resp_ready := '0';
--! DMA control
case ar.dmi_req_state is
when DMIREQ_IDLE =>
if ar.run_sync(0) = '1' then
av.qual_dreg := '1';
av.qual_dmireg := '1';
av.dmi_req_state := DMIREQ_SYNC_START;
end if;
when DMIREQ_SYNC_START =>
av.dmi_req_state := DMIREQ_START;
when DMIREQ_START =>
v_dmi_req_valid := ar.dmireg(1) or ar.dmireg(0);
v_dmi_write := ar.dmireg(1);
vb_dmi_addr := ar.dmireg(40 downto 34);
vb_dmi_wdata := ar.dmireg(33 downto 2);
if v_dmi_req_valid = '0' then
-- empty request 'nop'
av.done := '1';
av.dmi_req_state := DMIREQ_SYNC_RESP;
elsif i_dmi_req_ready = '1' then
av.dmi_req_state := DMIREQ_WAIT_READ_RESP;
end if;
when DMIREQ_WAIT_READ_RESP =>
vb_dmi_resp_ready := '1';
if i_dmi_resp_valid = '1' then
av.done := '1';
av.dreg := i_dmi_rdata(31 downto 0);
av.dmi_req_state := DMIREQ_SYNC_RESP;
end if;
when DMIREQ_SYNC_RESP =>
if ar.run_sync(0) = '0' then
av.done := '0';
av.dmi_req_state := DMIREQ_IDLE;
end if;
when others =>
end case;
-- Sync regs and CDC transfer
av.run_sync := tnr.run & ar.run_sync(1);
if ar.qual_dreg='1' then
av.dreg := not dregq;
end if;
if ar.qual_dmireg='1' then
av.dmireg := not dmiregq;
end if;
if (nrst = '0') then
av.dmi_req_state := DMIREQ_IDLE;
av.qual_dreg := '0';
av.qual_dmireg := '0';
av.done := '0';
av.dmireg := (others => '0');
av.dreg := (others => '0');
end if;
tprin <= tpv;
tnrin <= tnv;
arin <= av;
tapi_tdo <= vtapi_tdo;
o_dmi_req_valid <= v_dmi_req_valid;
o_dmi_write <= v_dmi_write;
o_dmi_addr <= vb_dmi_addr;
o_dmi_wdata <= vb_dmi_wdata;
o_dmi_resp_ready <= vb_dmi_resp_ready;
end process;
o_jtag_vref <= '1';
jtagcom0 : dcom_jtag generic map (
id => X"00000001"
) port map (
rst => nrst,
tck => i_tck,
tms => i_tms,
tdi => i_tdi,
tdo => o_tdo,
tapi_tdo => tapi_tdo,
tapo_tck => tapo_tck,
tapo_tdi => tapo_tdi,
tapo_inst => tapo_inst,
tapo_rst => tapo_rst,
tapo_capt => tapo_capt,
tapo_shft => tapo_shft,
tapo_upd => tapo_upd,
tapo_xsel1 => tapo_xsel1,
tapo_xsel2 => tapo_xsel2
);
axireg : process(clk)
begin
if rising_edge(clk) then
ar <= arin;
end if;
end process;
tckpreg: process(tapo_tck, tapo_rst)
begin
if rising_edge(tapo_tck) then
tpr <= tprin;
end if;
if tapo_rst = '1' then
tpr.dmishft <= (others => '0');
tpr.datashft <= (others => '0');
tpr.done_sync <= '0';
tpr.prun <= '0';
tpr.inshift <= '0';
tpr.holdn <= '1';
end if;
end process;
tcknreg: process(tapo_tck, tapo_rst)
begin
if falling_edge(tapo_tck) then
tnr <= tnrin;
end if;
if tapo_rst = '1' then
tnr.run <= '0';
tnr.done_sync1 <= '0';
tnr.qual_rdata <= '0';
tnr.addrlo <= (others => '0');
tnr.data <= (others => '0');
end if;
end process;
end;
| apache-2.0 | 5ec34d56dfcded3a58a7592685f09884 | 0.556404 | 3.183363 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/cache/mpu.vhd | 1 | 5,139 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_cache.all;
entity mpu is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_iaddr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_daddr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_region_we : in std_logic;
i_region_idx : in std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
i_region_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_region_mask : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_region_flags : in std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0); -- {ena, cachable, r, w, x}
o_iflags : out std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
o_dflags : out std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0)
);
end;
architecture arch_mpu of mpu is
type MpuTableItemType is record
addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
mask : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
flags : std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
end record;
type mpu_tbl_type is array (0 to CFG_MPU_TBL_SIZE-1) of MpuTableItemType;
signal tbl : mpu_tbl_type;
signal rin_tbl : mpu_tbl_type;
begin
comb : process(i_nrst, i_iaddr, i_daddr, tbl,
i_region_we, i_region_idx, i_region_addr, i_region_mask, i_region_flags)
variable v_item : MpuTableItemType;
variable v_tbl : mpu_tbl_type;
variable v_iflags : std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
variable v_dflags : std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
begin
v_tbl := tbl;
v_iflags := (others => '1');
v_dflags := (others => '1');
v_item.flags := i_region_flags;
if i_region_flags(CFG_MPU_FL_ENA) = '1' then
v_item.addr := i_region_addr;
v_item.mask := i_region_mask;
else
v_item.addr := (others => '1');
v_item.mask := (others => '1');
end if;
for i in 0 to CFG_MPU_TBL_SIZE-1 loop
if tbl(i).addr = (i_iaddr and tbl(i).mask) then
if tbl(i).flags(CFG_MPU_FL_ENA) = '1' then
v_iflags := tbl(i).flags;
end if;
end if;
if tbl(i).addr = (i_daddr and tbl(i).mask) then
if tbl(i).flags(CFG_MPU_FL_ENA) = '1' then
v_dflags := tbl(i).flags;
end if;
end if;
end loop;
if i_region_we = '1' then
v_tbl(conv_integer(i_region_idx)) := v_item;
end if;
if not async_reset and i_nrst = '0' then
for i in 0 to CFG_MPU_TBL_SIZE-1 loop
v_tbl(i).flags := (others => '0');
v_tbl(i).addr := (others => '0');
v_tbl(i).mask := (others => '1');
end loop;
-- All address above 0x80000000 are uncached (IO devices)
v_tbl(0).addr(31 downto 0) := X"80000000";
v_tbl(0).mask(31 downto 0) := X"80000000";
v_tbl(0).flags(CFG_MPU_FL_ENA) := '1';
v_tbl(0).flags(CFG_MPU_FL_CACHABLE) := '0';
v_tbl(0).flags(CFG_MPU_FL_EXEC) := '1';
v_tbl(0).flags(CFG_MPU_FL_RD) := '1';
v_tbl(0).flags(CFG_MPU_FL_WR) := '1';
-- (debug) Make first 128 Byte uncachable to test MPU
v_tbl(1).addr(31 downto 0) := X"00000000";
v_tbl(1).mask(31 downto 0) := X"FFFFFF80";
v_tbl(1).flags(CFG_MPU_FL_ENA) := '1';
v_tbl(1).flags(CFG_MPU_FL_CACHABLE) := '0';
v_tbl(1).flags(CFG_MPU_FL_EXEC) := '1';
v_tbl(1).flags(CFG_MPU_FL_RD) := '1';
v_tbl(1).flags(CFG_MPU_FL_WR) := '1';
end if;
rin_tbl <= v_tbl;
o_iflags <= v_iflags;
o_dflags <= v_dflags;
end process;
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
for i in 0 to CFG_MPU_TBL_SIZE-1 loop
tbl(i).flags <= (others => '0');
tbl(i).addr <= (others => '0');
tbl(i).mask <= (others => '1');
end loop;
-- All address above 0x80000000 are uncached (IO devices)
tbl(0).addr(31 downto 0) <= X"80000000";
tbl(0).mask(31 downto 0) <= X"80000000";
tbl(0).flags(CFG_MPU_FL_ENA) <= '1';
tbl(0).flags(CFG_MPU_FL_CACHABLE) <= '0';
tbl(0).flags(CFG_MPU_FL_EXEC) <= '1';
tbl(0).flags(CFG_MPU_FL_RD) <= '1';
tbl(0).flags(CFG_MPU_FL_WR) <= '1';
elsif rising_edge(i_clk) then
tbl <= rin_tbl;
end if;
end process;
end;
| apache-2.0 | db48a5e7d77ae49246f7f37af5d7658c | 0.58202 | 2.955147 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/fpu_top.vhd | 1 | 13,711 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library riverlib;
use riverlib.river_cfg.all;
entity FpuTop is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_ivec : in std_logic_vector(Instr_FPU_Total-1 downto 0);
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_ex_invalidop : out std_logic; -- Exception: invalid operation
o_ex_divbyzero : out std_logic; -- Exception: divide by zero
o_ex_overflow : out std_logic; -- Exception: overflow
o_ex_underflow : out std_logic; -- Exception: underflow
o_ex_inexact : out std_logic; -- Exception: inexact
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_FpuTop of FpuTop is
component DoubleAdd is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_add : in std_logic;
i_sub : in std_logic;
i_eq : in std_logic;
i_lt : in std_logic;
i_le : in std_logic;
i_max : in std_logic;
i_min : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component DoubleDiv is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_divbyzero : out std_logic;
o_overflow : out std_logic;
o_underflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component DoubleMul is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component Double2Long is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_signed : in std_logic;
i_w32 : in std_logic;
i_a : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_overflow : out std_logic;
o_underflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component Long2Double is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_signed : in std_logic;
i_w32 : in std_logic;
i_a : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
type RegistersType is record
ivec : std_logic_vector(Instr_FPU_Total-1 downto 0);
busy : std_logic;
ready : std_logic;
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
ex_invalidop : std_logic; -- Exception: invalid operation
ex_divbyzero : std_logic; -- Exception: divide by zero
ex_overflow : std_logic; -- Exception: overflow
ex_underflow : std_logic; -- Exception: underflow
ex_inexact : std_logic; -- Exception: inexact
ena_fadd : std_logic;
ena_fdiv : std_logic;
ena_fmul : std_logic;
ena_d2l : std_logic;
ena_l2d : std_logic;
ena_w32 : std_logic;
end record;
constant R_RESET : RegistersType := (
(others => '0'), -- ivec
'0', '0', (others => '0'), (others => '0'), -- busy, ready, a, b
(others => '0'), -- result
'0', '0', '0', -- ex_invalidop, ex_divbyzero, ex_overflow
'0', '0', '0', -- ex_underflow, ex_inexact, ena_fadd
'0', '0', '0', '0', -- ena_fdiv, ena_fmul, ena_d2l, ena_l2d
'0' -- ena_w32
);
signal r, rin : RegistersType;
signal w_fadd_d : std_logic;
signal w_fsub_d : std_logic;
signal w_feq_d : std_logic;
signal w_flt_d : std_logic;
signal w_fle_d : std_logic;
signal w_fmax_d : std_logic;
signal w_fmin_d : std_logic;
signal w_fcvt_signed : std_logic;
signal wb_res_fadd : std_logic_vector(63 downto 0);
signal w_valid_fadd : std_logic;
signal w_illegalop_fadd : std_logic;
signal w_overflow_fadd : std_logic;
signal w_busy_fadd : std_logic;
signal wb_res_fdiv : std_logic_vector(63 downto 0);
signal w_valid_fdiv : std_logic;
signal w_illegalop_fdiv : std_logic;
signal w_divbyzero_fdiv : std_logic;
signal w_overflow_fdiv : std_logic;
signal w_underflow_fdiv : std_logic;
signal w_busy_fdiv : std_logic;
signal wb_res_fmul : std_logic_vector(63 downto 0);
signal w_valid_fmul : std_logic;
signal w_illegalop_fmul : std_logic;
signal w_overflow_fmul : std_logic;
signal w_busy_fmul : std_logic;
signal wb_res_d2l : std_logic_vector(63 downto 0);
signal w_valid_d2l : std_logic;
signal w_overflow_d2l : std_logic;
signal w_underflow_d2l : std_logic;
signal w_busy_d2l : std_logic;
signal wb_res_l2d : std_logic_vector(63 downto 0);
signal w_valid_l2d : std_logic;
signal w_busy_l2d : std_logic;
begin
fadd_d0 : DoubleAdd generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_fadd,
i_add => w_fadd_d,
i_sub => w_fsub_d,
i_eq => w_feq_d,
i_lt => w_flt_d,
i_le => w_fle_d,
i_max => w_fmax_d,
i_min => w_fmin_d,
i_a => r.a,
i_b => r.b,
o_res => wb_res_fadd,
o_illegal_op => w_illegalop_fadd,
o_overflow => w_overflow_fadd,
o_valid => w_valid_fadd,
o_busy => w_busy_fadd
);
fdiv_d0 : DoubleDiv generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_fdiv,
i_a => r.a,
i_b => r.b,
o_res => wb_res_fdiv,
o_illegal_op => w_illegalop_fdiv,
o_divbyzero => w_divbyzero_fdiv,
o_overflow => w_overflow_fdiv,
o_underflow => w_underflow_fdiv,
o_valid => w_valid_fdiv,
o_busy => w_busy_fdiv
);
fmul_d0 : DoubleMul generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_fmul,
i_a => r.a,
i_b => r.b,
o_res => wb_res_fmul,
o_illegal_op => w_illegalop_fmul,
o_overflow => w_overflow_fmul,
o_valid => w_valid_fmul,
o_busy => w_busy_fmul
);
d2l_d0 : Double2Long generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_d2l,
i_signed => w_fcvt_signed,
i_w32 => r.ena_w32,
i_a => r.a,
o_res => wb_res_d2l,
o_overflow => w_overflow_d2l,
o_underflow => w_underflow_d2l,
o_valid => w_valid_d2l,
o_busy => w_busy_d2l
);
l2d_d0 : Long2Double generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_l2d,
i_signed => w_fcvt_signed,
i_w32 => r.ena_w32,
i_a => r.a,
o_res => wb_res_l2d,
o_valid => w_valid_l2d,
o_busy => w_busy_l2d
);
-- registers:
comb : process(i_nrst, i_ena, i_ivec, i_a, i_b, r,
wb_res_fadd, w_valid_fadd, w_illegalop_fadd, w_overflow_fadd, w_busy_fadd,
wb_res_fdiv, w_valid_fdiv, w_illegalop_fdiv, w_divbyzero_fdiv, w_overflow_fdiv,
w_underflow_fdiv, w_busy_fdiv,
wb_res_fmul, w_valid_fmul, w_illegalop_fmul, w_overflow_fmul, w_busy_fmul,
wb_res_d2l, w_valid_d2l, w_overflow_d2l, w_underflow_d2l, w_busy_d2l,
wb_res_l2d, w_valid_l2d, w_busy_l2d)
variable v : RegistersType;
variable iv : std_logic_vector(Instr_FPU_Total-1 downto 0);
begin
v := r;
iv := i_ivec;
v.ena_fadd := '0';
v.ena_fdiv := '0';
v.ena_fmul := '0';
v.ena_d2l := '0';
v.ena_l2d := '0';
v.ready := '0';
if i_ena = '1' and r.busy = '0' then
v.busy := '1';
v.a := i_a;
v.b := i_b;
v.ivec := i_ivec;
v.ex_invalidop := '0';
v.ex_divbyzero := '0';
v.ex_overflow := '0';
v.ex_underflow := '0';
v.ex_inexact := '0';
v.ena_fadd := iv(Instr_FADD_D - Instr_FADD_D)
or iv(Instr_FSUB_D - Instr_FADD_D)
or iv(Instr_FLE_D - Instr_FADD_D)
or iv(Instr_FLT_D - Instr_FADD_D)
or iv(Instr_FEQ_D - Instr_FADD_D)
or iv(Instr_FMAX_D - Instr_FADD_D)
or iv(Instr_FMIN_D - Instr_FADD_D);
v.ena_fdiv := iv(Instr_FDIV_D - Instr_FADD_D);
v.ena_fmul := iv(Instr_FMUL_D - Instr_FADD_D);
v.ena_d2l := iv(Instr_FCVT_LU_D - Instr_FADD_D)
or iv(Instr_FCVT_L_D - Instr_FADD_D)
or iv(Instr_FCVT_WU_D - Instr_FADD_D)
or iv(Instr_FCVT_W_D - Instr_FADD_D);
v.ena_l2d := iv(Instr_FCVT_D_LU - Instr_FADD_D)
or iv(Instr_FCVT_D_L - Instr_FADD_D)
or iv(Instr_FCVT_D_WU - Instr_FADD_D)
or iv(Instr_FCVT_D_W - Instr_FADD_D);
v.ena_w32 := iv(Instr_FCVT_WU_D - Instr_FADD_D)
or iv(Instr_FCVT_W_D - Instr_FADD_D)
or iv(Instr_FCVT_D_WU - Instr_FADD_D)
or iv(Instr_FCVT_D_W - Instr_FADD_D);
end if;
if r.busy = '1' and (r.ivec(Instr_FMOV_X_D - Instr_FADD_D)
or r.ivec(Instr_FMOV_D_X - Instr_FADD_D)) = '1' then
v.busy := '0';
v.ready := '1';
v.result := r.a;
elsif w_valid_fadd = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_fadd;
v.ex_invalidop := w_illegalop_fadd;
v.ex_overflow := w_overflow_fadd;
elsif w_valid_fdiv = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_fdiv;
v.ex_invalidop := w_illegalop_fdiv;
v.ex_divbyzero := w_divbyzero_fdiv;
v.ex_overflow := w_overflow_fdiv;
v.ex_underflow := w_underflow_fdiv;
elsif w_valid_fmul = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_fmul;
v.ex_invalidop := w_illegalop_fmul;
v.ex_overflow := w_overflow_fmul;
elsif w_valid_d2l = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_d2l;
v.ex_overflow := w_overflow_d2l;
v.ex_underflow := w_underflow_d2l;
elsif w_valid_l2d = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_l2d;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
w_fadd_d <= r.ivec(Instr_FADD_D - Instr_FADD_D);
w_fsub_d <= r.ivec(Instr_FSUB_D - Instr_FADD_D);
w_feq_d <= r.ivec(Instr_FEQ_D - Instr_FADD_D);
w_flt_d <= r.ivec(Instr_FLT_D - Instr_FADD_D);
w_fle_d <= r.ivec(Instr_FLE_D - Instr_FADD_D);
w_fmax_d <= r.ivec(Instr_FMAX_D - Instr_FADD_D);
w_fmin_d <= r.ivec(Instr_FMIN_D - Instr_FADD_D);
w_fcvt_signed <= r.ivec(Instr_FCVT_L_D - Instr_FADD_D) or
r.ivec(Instr_FCVT_D_L - Instr_FADD_D) or
r.ivec(Instr_FCVT_W_D - Instr_FADD_D) or
r.ivec(Instr_FCVT_D_W - Instr_FADD_D);
o_res <= r.result;
o_ex_invalidop <= r.ex_invalidop;
o_ex_divbyzero <= r.ex_divbyzero;
o_ex_overflow <= r.ex_overflow;
o_ex_underflow <= r.ex_underflow;
o_ex_inexact <= r.ex_inexact;
o_valid <= r.ready;
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 10239671f728d88410c3374f9a472d67 | 0.53417 | 2.941012 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/work/tb/jtag_sim.vhd | 1 | 7,572 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
use commonlib.types_util.all;
entity jtag_sim is
generic (
clock_rate : integer := 10
);
port (
rst : in std_logic;
clk : in std_logic;
i_dtmcs_re : in std_logic;
i_dmi_ena : in std_logic;
i_dmi_we : in std_logic;
i_dmi_re : in std_logic;
i_dmi_addr : in std_logic_vector(6 downto 0);
i_dmi_wdata : in std_logic_vector(31 downto 0);
i_tdi : in std_logic;
o_tck : out std_logic;
o_ntrst : out std_logic;
o_tms : out std_logic;
o_tdo : out std_logic
);
end;
architecture jtag_sim_rtl of jtag_sim is
type state_type is (test_rst, run_idle, start_ir, select_dr, capture_dr, shift_dr, exit1_dr,
pause_dr, exit2_dr, update_dr, select_ir, capture_ir, shift_ir,
exit1_ir, pause_ir, exit2_ir, update_ir);
type registers is record
jtagstate : state_type;
jtagstatez : state_type;
dmi_request : std_logic_vector(40 downto 0);
dmi_resp_addr : std_logic_vector(6 downto 0);
dmi_resp_data : std_logic_vector(31 downto 0);
dmi_resp_stat : std_logic_vector(1 downto 0);
shift_reg : std_logic_vector(45 downto 0);
shift_length : integer;
is_data : std_logic;
dtmcs_ena : std_logic;
clk_rate_cnt : integer;
op_cnt : integer;
rdata : std_logic_vector(40 downto 0);
edge : std_logic;
ntrst : std_logic;
tms : std_logic;
dmi_dtm : std_logic; -- last was: 0=DMI; 1=DTM
end record;
signal r, rin : registers;
begin
comblogic : process(rst, r, i_tdi, i_dtmcs_re, i_dmi_ena, i_dmi_we, i_dmi_re, i_dmi_addr, i_dmi_wdata)
variable v : registers;
variable w_posedge : std_logic;
variable w_negedge : std_logic;
begin
v := r;
w_posedge := '0';
w_negedge := '0';
if r.clk_rate_cnt = (clock_rate - 1) then
v.clk_rate_cnt := 0;
v.edge := not r.edge;
w_posedge := not r.edge;
w_negedge := r.edge;
else
v.clk_rate_cnt := r.clk_rate_cnt + 1;
end if;
if (i_dtmcs_re or i_dmi_ena) = '1' and r.jtagstate = run_idle then
v.is_data := '1';
v.dtmcs_ena := i_dtmcs_re;
v.dmi_request(0) := i_dmi_re;
v.dmi_request(1) := i_dmi_we;
v.dmi_request(33 downto 2) := i_dmi_wdata;
v.dmi_request(40 downto 34) := i_dmi_addr;
end if;
if w_posedge = '1' then
v.jtagstatez := r.jtagstate;
case r.jtagstate is
when test_rst =>
v.ntrst := '0';
v.op_cnt := r.op_cnt + 1;
if r.op_cnt = 3 then
v.jtagstate := run_idle;
v.op_cnt := 0;
v.ntrst := '1';
end if;
when run_idle =>
if r.is_data = '1' then
v.is_data := '0';
v.tms := '1';
v.op_cnt := 0;
v.jtagstate := start_ir;
end if;
when start_ir => -- the same as select_dr
if r.dmi_dtm /= r.dtmcs_ena then
-- IR changed
v.tms := '1';
v.jtagstate := select_ir;
else
-- IR the same
v.tms := '0';
v.jtagstate := capture_dr;
if r.dtmcs_ena = '1' then
v.shift_reg := (others => '0');
v.shift_length := 32-1;
else
v.shift_reg := "00000" & r.dmi_request;
v.shift_length := 41-1;
end if;
end if;
when select_ir =>
v.tms := '0';
v.jtagstate := capture_ir;
when capture_ir =>
v.tms := '0';
v.op_cnt := 0;
v.jtagstate := shift_ir;
if r.dtmcs_ena = '1' then
v.shift_reg := (others => '0');
v.shift_reg(4 downto 0) := "10000"; -- DTMCS reg
v.shift_length := 32-1;
else
v.shift_reg := r.dmi_request & "10001";
v.shift_length := 41-1;
end if;
v.op_cnt := 0;
when shift_ir =>
v.tms := '0';
v.op_cnt := r.op_cnt + 1;
if r.op_cnt = 4 then
v.tms := '1';
v.jtagstate := exit1_ir;
end if;
when exit1_ir =>
v.tms := '1';
v.jtagstate := update_ir;
when update_ir =>
v.tms := '1';
v.jtagstate := select_dr;
when select_dr =>
v.tms := '0';
v.jtagstate := capture_dr;
when capture_dr =>
v.tms := '0';
v.op_cnt := 0;
v.jtagstate := shift_dr;
v.rdata := (others => '0');
when shift_dr =>
v.tms := '0';
if r.dtmcs_ena = '1' then
v.rdata(31 downto 0) := i_tdi & r.rdata(31 downto 1);
else
v.rdata := i_tdi & r.rdata(40 downto 1);
end if;
v.op_cnt := r.op_cnt + 1;
if r.op_cnt = r.shift_length then
v.tms := '1';
v.jtagstate := exit1_dr;
end if;
when exit1_dr =>
v.tms := '1';
if r.dtmcs_ena = '1' then
v.rdata(31 downto 0) := i_tdi & r.rdata(31 downto 1);
else
v.rdata := i_tdi & r.rdata(40 downto 1);
end if;
v.jtagstate := update_dr;
when update_dr =>
v.dmi_dtm := r.dtmcs_ena;
if r.dtmcs_ena = '0' then
v.dmi_resp_addr := r.rdata(40 downto 34);
v.dmi_resp_data := r.rdata(33 downto 2);
v.dmi_resp_stat := r.rdata(1 downto 0);
end if;
v.tms := '0';
v.jtagstate := run_idle;
when others =>
end case;
if r.jtagstatez = shift_ir or r.jtagstatez = shift_dr then
v.shift_reg := '0' & r.shift_reg(45 downto 1);
end if;
end if;
-- Reset
if rst = '1' then
v.jtagstate := test_rst;
v.jtagstatez := test_rst;
v.clk_rate_cnt := 0;
v.op_cnt := 0;
v.is_data := '0';
v.dtmcs_ena := '0';
v.dmi_request := (others => '0');
v.dmi_resp_addr := (others => '0');
v.dmi_resp_data := (others => '0');
v.dmi_resp_stat := (others => '0');
v.shift_reg := (others => '0');
v.edge := '0';
v.ntrst := '0';
v.tms := '0';
v.dmi_dtm := '0';
end if;
rin <= v;
end process;
o_tdo <= r.shift_reg(0);
o_tck <= r.edge;
o_tms <= r.tms;
o_ntrst <= r.ntrst;
procCheck : process (clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 703ad9f356c59cf61da34d662e9ea989 | 0.479398 | 3.285033 | false | false | false | false |
szanni/aeshw | zybo-base/lib/Digilent/hdmi_tx_1.0/hdl/SerializerN_1.vhd | 1 | 11,037 | --------------------------------------------------------------------------------
--
-- File:
-- SerializerN_1.vhd
--
-- Module:
-- SerializerN_1
--
-- Author:
-- Elod Gyorgy
--
-- Date:
-- 10/27/2010
--
-- Description:
-- This module serializes N:1 data LSB-first using cascaded OSERDES
-- primitives.
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity SerializerN_1 is
Generic ( N : NATURAL := 10;
FAMILY : STRING := "spartan6");
Port ( DP_I : in STD_LOGIC_VECTOR (N-1 downto 0);
CLKDIV_I : in STD_LOGIC; --parallel slow clock
CLKDIV_X2_I : in STD_LOGIC; --double parallel slow clock (CLKDIV_I x 2) REQUIRED ONLY FOR Spartan-6
SERCLK_I : in STD_LOGIC; --serial fast clock (CLK_I = CLKDIV_I x N / 2)
SERSTB_I : in STD_LOGIC; -- REQUIRED ONLY FOR Spartan-6
RST_I : in STD_LOGIC; --async reset
DSP_O : out STD_LOGIC;
DSN_O : out STD_LOGIC);
end SerializerN_1;
architecture Behavioral of SerializerN_1 is
signal intDSOut: std_logic;
signal intDPIn : std_logic_vector(N/2-1 downto 0) ;
signal padDPIn : std_logic_vector(13 downto 0) ;
signal cascade_do, cascade_di, cascade_to, cascade_ti : std_logic;
signal gear, gear_s : std_logic := '0';
signal int_rst : std_logic;
begin
----------------------------------------------------------------------------------
-- Instantiate Output Buffer
----------------------------------------------------------------------------------
io_datax_out : obufds port map (
O => DSP_O,
OB => DSN_O,
I => intDSOut);
family_s6: if FAMILY = "spartan6" generate
begin
----------------------------------------------------------------------------------
-- 2:1 gearbox; SerDes is used in 5:1 ratio, we need to double that; The SerDes
-- parallel input will change twice in a pixel clock, thus the need for pixel
-- clock * 2
----------------------------------------------------------------------------------
process (CLKDIV_I, RST_I)
begin
if (RST_I = '1') then
gear <= '0';
elsif Rising_Edge(CLKDIV_I) then
gear <= not gear;
end if;
end process;
process (CLKDIV_X2_I)
begin
if Rising_Edge(CLKDIV_X2_I) then
gear_s <= gear; --resync gear on x2 domain
end if;
end process;
process (CLKDIV_X2_I)
begin
if Rising_Edge(CLKDIV_X2_I) then
if ((gear xor gear_s) = '1') then
intDPIn <= DP_I(N/2-1 downto 0);
else
intDPIn <= DP_I(N-1 downto N/2);
end if ;
end if;
end process ;
padDPIn(7 downto N/2) <= (others => '0');
padDPIn(N/2-1 downto 0) <= intDPIn(N/2-1 downto 0);
----------------------------------------------------------------------------------
-- Cascaded OSERDES for 5:1 ratio
----------------------------------------------------------------------------------
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => N/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => intDsOut, --master outputs serial data in cascaded setup
OCE => '1',
CLK0 => SERCLK_I,
CLK1 => '0',
IOCE => SERSTB_I,
RST => RST_I, --async reset
CLKDIV => CLKDIV_X2_I, --parallel data transferred at 2x pixel clock (2x 5:1 = 10:1)
D4 => padDPIn(7), --not used in 5:1
D3 => padDPIn(6), --not used in 5:1
D2 => padDPIn(5), --not used in 5:1
D1 => padDPIn(4), --MSB in 5:1
TQ => open, --no tri-state
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do, -- Cascade output D data from slave
SHIFTIN4 => cascade_to, -- Cascade output T data from slave
SHIFTOUT1 => cascade_di, -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti, -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => N/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open, --slave does not output serial data in cascaded setup
OCE => '1',
CLK0 => SERCLK_I,
CLK1 => '0',
IOCE => SERSTB_I,
RST => RST_I, --async reset
CLKDIV => CLKDIV_X2_I, --parallel data transferred at 2x pixel clock (2x 5:1 = 10:1)
D4 => padDPIn(3),
D3 => padDPIn(2),
D2 => padDPIn(1),
D1 => padDPIn(0),
TQ => open, --no tri-state
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di, -- Cascade input D from Master
SHIFTIN2 => cascade_ti, -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do, -- Cascade output D data to Master
SHIFTOUT4 => cascade_to) ; -- Cascade output T data to Master
end generate family_s6;
family_7: if FAMILY = "kintex7" or FAMILY = "artix7" or FAMILY = "virtex7" generate
begin
----------------------------------------------------------------------------------
-- Reset should be asserted asynchronously an de-asserted synchronously
----------------------------------------------------------------------------------
process(RST_I, CLKDIV_I)
begin
if (RST_I = '1') then
int_rst <= '1';
elsif Rising_Edge(CLKDIV_I) then
int_rst <= '0';
end if;
end process;
padDPIn(13 downto N) <= (others => '0');
padDPIn(N-1 downto 0) <= DP_I;
----------------------------------------------------------------------------------
-- Cascaded OSERDES for 10:1 ratio (DDR)
----------------------------------------------------------------------------------
oserdese2_master : OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => N,
TRISTATE_WIDTH => 1,
SERDES_MODE => "MASTER")
port map (
D1 => padDPIn(0),
D2 => padDPIn(1),
D3 => padDPIn(2),
D4 => padDPIn(3),
D5 => padDPIn(4),
D6 => padDPIn(5),
D7 => padDPIn(6),
D8 => padDPIn(7),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => cascade_di,
SHIFTIN2 => cascade_ti,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
OCE => '1',
CLK => SERCLK_I,
CLKDIV => CLKDIV_I,
OQ => intDsOut,
TQ => open,
OFB => open,
TBYTEIN => '0',
TBYTEOUT => open,
TFB => open,
TCE => '0',
RST => int_rst);
oserdese2_slave : OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => N,
TRISTATE_WIDTH => 1,
SERDES_MODE => "SLAVE")
port map (
D1 => '0',
D2 => '0',
D3 => padDPIn(8),
D4 => padDPIn(9),
D5 => padDPIn(10),
D6 => padDPIn(11),
D7 => padDPIn(12),
D8 => padDPIn(13),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTOUT1 => cascade_di,
SHIFTOUT2 => cascade_ti,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
OCE => '1',
CLK => SERCLK_I,
CLKDIV => CLKDIV_I,
OQ => open,
TQ => open,
OFB => open,
TFB => open,
TBYTEIN => '0',
TBYTEOUT => open,
TCE => '0',
RST => int_rst);
end generate family_7;
end Behavioral;
| bsd-2-clause | 9c3eb3d4c0234d22133cb014a0bd3b95 | 0.490351 | 3.577634 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/fdiv_d.vhd | 1 | 11,958 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity DoubleDiv is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_divbyzero : out std_logic;
o_overflow : out std_logic;
o_underflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_DoubleDiv of DoubleDiv is
component idiv53 is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_divident : in std_logic_vector(52 downto 0);
i_divisor : in std_logic_vector(52 downto 0);
o_result : out std_logic_vector(104 downto 0);
o_lshift : out std_logic_vector(6 downto 0);
o_rdy : out std_logic;
o_overflow : out std_logic;
o_zero_resid : out std_logic
);
end component;
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(4 downto 0);
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
zeroA : std_logic;
zeroB : std_logic;
divisor : std_logic_vector(52 downto 0);
preShift : std_logic_vector(5 downto 0);
expAB : std_logic_vector(12 downto 0);
expAlign : std_logic_vector(11 downto 0);
mantAlign : std_logic_vector(104 downto 0);
postShift : std_logic_vector(11 downto 0);
mantPostScale : std_logic_vector(104 downto 0);
nanRes : std_logic;
overflow : std_logic;
underflow : std_logic;
illegal_op : std_logic;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), (others => '0'), -- a, b, result
'0', '0', (others => '0'), (others => '0'), -- zeroA, zeroB, divisor, preShift
(others => '0'), (others => '0'), (others => '0'), -- expAB, expAlign, mantAlign
(others => '0'), (others => '0'), -- postShift, mantPostScale
'0', '0', '0', '0' -- nanRes, overflow, underflow, illegal_op
);
constant zero105 : std_logic_vector(104 downto 0) := (others => '0');
signal r, rin : RegistersType;
signal w_idiv_ena : std_logic;
signal wb_divident : std_logic_vector(52 downto 0);
signal wb_divisor : std_logic_vector(52 downto 0);
signal wb_idiv_result : std_logic_vector(104 downto 0);
signal wb_idiv_lshift : std_logic_vector(6 downto 0);
signal w_idiv_rdy : std_logic;
signal w_idiv_overflow : std_logic;
signal w_idiv_zeroresid : std_logic;
begin
u_idiv53 : idiv53 generic map (
async_reset => async_reset
) port map (
i_nrst => i_nrst,
i_clk => i_clk,
i_ena => w_idiv_ena,
i_divident => wb_divident,
i_divisor => wb_divisor,
o_result => wb_idiv_result,
o_lshift => wb_idiv_lshift,
o_rdy => w_idiv_rdy,
o_overflow => w_idiv_overflow,
o_zero_resid => w_idiv_zeroresid
);
-- registers:
comb : process(i_nrst, i_ena, i_a, i_b, r,
wb_idiv_result, wb_idiv_lshift, w_idiv_rdy, w_idiv_overflow,
w_idiv_zeroresid)
variable v : RegistersType;
variable signA : std_logic;
variable signB : std_logic;
variable mantA : std_logic_vector(52 downto 0);
variable mantB : std_logic_vector(52 downto 0);
variable zeroA : std_logic;
variable zeroB : std_logic;
variable divisor : std_logic_vector(52 downto 0);
variable preShift : integer range 0 to 52;
variable expAB_t : std_logic_vector(11 downto 0);
variable expAB : std_logic_vector(12 downto 0);
variable mantAlign : std_logic_vector(104 downto 0);
variable expShift : std_logic_vector(11 downto 0);
variable expAlign : std_logic_vector(12 downto 0);
variable postShift : std_logic_vector(11 downto 0);
variable mantPostScale : std_logic_vector(104 downto 0);
variable mantShort : std_logic_vector(52 downto 0);
variable tmpMant05 : std_logic_vector(51 downto 0);
variable mantOnes : std_logic;
variable mantEven : std_logic;
variable mant05 : std_logic;
variable rndBit : std_logic;
variable nanA : std_logic;
variable nanB : std_logic;
variable mantZeroA : std_logic;
variable mantZeroB : std_logic;
variable res : std_logic_vector(63 downto 0);
begin
v := r;
v.ena(0) := i_ena and not r.busy;
v.ena(1) := r.ena(0);
v.ena(4 downto 2) := r.ena(3 downto 2) & w_idiv_rdy;
if i_ena = '1' then
v.busy := '1';
v.overflow := '0';
v.underflow := '0';
v.illegal_op := '0';
v.a := i_a;
v.b := i_b;
end if;
signA := r.a(63);
signB := r.b(63);
zeroA := '0';
if r.a(62 downto 0) = zero105(62 downto 0) then
zeroA := '1';
end if;
zeroB := '0';
if r.b(62 downto 0) = zero105(62 downto 0) then
zeroB := '1';
end if;
mantA(51 downto 0) := r.a(51 downto 0);
mantA(52) := '0';
if r.a(62 downto 52) /= zero105(10 downto 0) then
mantA(52) := '1';
end if;
mantB(51 downto 0) := r.b(51 downto 0);
mantB(52) := '0';
if r.b(62 downto 52) /= zero105(10 downto 0) then
mantB(52) := '1';
divisor := mantB;
preShift := 0;
else
divisor := mantB;
preShift := 0;
for i in 1 to 52 loop
if preShift = 0 and mantB(52 - i) = '1' then
divisor := mantB(52-i downto 0) & zero105(i-1 downto 0);
preShift := i;
end if;
end loop;
end if;
-- expA - expB + 1023
expAB_t := ('0' & r.a(62 downto 52)) + 1023;
expAB := ('0' & expAB_t) - ("00" & r.b(62 downto 52));
if r.ena(0) = '1' then
v.divisor := divisor;
v.preShift := conv_std_logic_vector(preShift, 6);
v.expAB := expAB;
v.zeroA := zeroA;
v.zeroB := zeroB;
end if;
w_idiv_ena <= r.ena(1);
wb_divident <= mantA;
wb_divisor <= r.divisor;
-- idiv53 module:
mantAlign := (others => '0');
if wb_idiv_lshift = zero105(6 downto 0) then
mantAlign := wb_idiv_result;
else
for i in 1 to 104 loop
if i = conv_integer(wb_idiv_lshift) then
mantAlign := wb_idiv_result(104-i downto 0) & zero105(i-1 downto 0);
end if;
end loop;
end if;
expShift := ("000000" & r.preShift) - ("00000" & wb_idiv_lshift);
if r.b(62 downto 52) = "00000000000" and r.a(62 downto 52) /= "00000000000" then
expShift := expShift - 1;
elsif r.b(62 downto 52) /= "00000000000" and r.a(62 downto 52) = "00000000000" then
expShift := expShift + 1;
end if;
expAlign := r.expAB + (expShift(11) & expShift);
if expAlign(12) = '1' then
postShift := not expAlign(11 downto 0) + 2;
else
postShift := (others => '0');
end if;
if w_idiv_rdy = '1' then
v.expAlign := expAlign(11 downto 0);
v.mantAlign := mantAlign;
v.postShift := postShift;
-- Exceptions:
v.nanRes := '0';
if expAlign = "0011111111111" then
v.nanRes := '1';
end if;
v.overflow := not expAlign(12) and expAlign(11);
v.underflow := expAlign(12) and expAlign(11);
end if;
-- Prepare to mantissa post-scale
mantPostScale := (others => '0');
if r.postShift = X"000" then
mantPostScale := r.mantAlign;
elsif r.postShift < conv_std_logic_vector(105, 12) then
for i in 1 to 104 loop
if conv_std_logic_vector(i, 7) = r.postShift(6 downto 0) then
mantPostScale := zero105(i-1 downto 0) & r.mantAlign(104 downto i);
end if;
end loop;
end if;
if r.ena(2) = '1' then
v.mantPostScale := mantPostScale;
end if;
-- Rounding bit
mantShort := r.mantPostScale(104 downto 52);
tmpMant05 := r.mantPostScale(51 downto 0);
mantOnes := '0';
if mantShort(52) = '1' and mantShort(51 downto 0) = X"fffffffffffff" then
mantOnes := '1';
end if;
mantEven := r.mantPostScale(52);
mant05 := '0';
if tmpMant05 = X"8000000000000" then
mant05 := '1';
end if;
rndBit := r.mantPostScale(51) and not(mant05 and not mantEven);
-- Check Borders
nanA := '0';
if r.a(62 downto 52) = "11111111111" then
nanA := '1';
end if;
nanB := '0';
if r.b(62 downto 52) = "11111111111" then
nanB := '1';
end if;
mantZeroA := '0';
if r.a(51 downto 0) = zero105(51 downto 0) then
mantZeroA := '1';
end if;
mantZeroB := '0';
if r.b(51 downto 0) = zero105(51 downto 0) then
mantZeroB := '1';
end if;
-- Result multiplexers:
if (nanA and mantZeroA and nanB and mantZeroB) = '1' then
res(63) := '1';
elsif (nanA and not mantZeroA) = '1' then
res(63) := signA;
elsif (nanB and not mantZeroB) = '1' then
res(63) := signB;
elsif (r.zeroA and r.zeroB) = '1' then
res(63) := '1';
else
res(63) := r.a(63) xor r.b(63);
end if;
if nanB = '1' and mantZeroB = '0' then
res(62 downto 52) := r.b(62 downto 52);
elsif (r.underflow or r.zeroA) = '1' and r.zeroB = '0' then
res(62 downto 52) := (others => '0');
elsif (r.overflow or r.zeroB) = '1' then
res(62 downto 52) := (others => '1');
elsif nanA = '1' then
res(62 downto 52) := r.a(62 downto 52);
elsif ((nanB and mantZeroB) or r.expAlign(11)) = '1' then
res(62 downto 52) := (others => '0');
else
res(62 downto 52) := r.expAlign(10 downto 0)
+ (mantOnes and rndBit and not r.overflow);
end if;
if (r.zeroA and r.zeroB) = '1'
or (nanA and mantZeroA and nanB and mantZeroB) = '1' then
res(51) := '1';
res(50 downto 0) := (others => '0');
elsif nanA = '1' and mantZeroA = '0' then
res(51) := '1';
res(50 downto 0) := r.a(50 downto 0);
elsif nanB = '1' and mantZeroB = '0'then
res(51) := '1';
res(50 downto 0) := r.b(50 downto 0);
elsif r.overflow = '1' or r.nanRes = '1' or (nanA and mantZeroA) = '1'
or (nanB and mantZeroB) = '1' then
res(51 downto 0) := (others => '0');
else
res(51 downto 0) := mantShort(51 downto 0) + rndBit;
end if;
if r.ena(3) = '1' then
v.result := res;
v.illegal_op := nanA or nanB;
v.busy := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_illegal_op <= r.illegal_op;
o_divbyzero <= r.zeroB;
o_overflow <= r.overflow;
o_underflow <= r.underflow;
o_valid <= r.ena(4);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | e1c7a18e42b82e1663db5b0da155c2b6 | 0.562887 | 3.139407 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/builtin_extdepth.vhd | 19 | 80,613 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jjl8vAn2UJruW+pwbvMAIo6yT6bQgTl9+ZqbT+VaAP/dcMa9HxI5w52bG1uOMJkKjbI3shaTb5QH
+WA4TEmwBA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jY7USlQiP9PR+LALAEYZsrKak9VnF4tfhT9SQb5jLUPXs+eC5ZbIVQkPjdV+4wzhB7b7ai6shnHa
gEu6kUZZsMTRIotEQn7SVZESTAIMCGAU4lDLU7RT30ySc+gN3y2heOoScYVxVF3kYNcbErB9g4iU
iZLVkq3ZU0fP1VLA30w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
W97r968B0QPwlTs1emSg8mtee0qHNpQ+/n5wfXS0R66Akqy90VsNXhnqLJjbnGJNqaGSMTKCRNVS
ox1Z0rkuemlJn0dMgZtmRgHM/NeyMTSbsBwVvTSeFdA56k6PzciIIQ1S8150Bxbexnd+b7l/UMK+
JO8+KzzHPEIPqou3srZGn9dog9HSSfTUIqvBgloCeGmDxxwlsFwQ2VsrffuE8mB5Kk9lHG/A3rMw
tbJURgYaS/b69KLL9Kc/urEgbRWHU1HQCQDL4hSKE79WXE68MZJ00kcWMfNfAOR1zytQecSerjXJ
iVVvnEzEtzUejpnuhHCRhS+b62dMTzf5a1Q4Dw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
l6IXa1kcvqxcIuqXI9bELoLDvGs5XxFfhbXxOKBitloxuDBS5IYgW7AXksTedGB5rM+6jbAr+PVa
4ykVDtx+9n1RZQ3HKQZNsRywuW0+Fcm/MhmC5isxnEClP56JmzAEyD9l7nmy9JJJI11qQTy86iSs
hkUJMmO3Ph4Kz8ptLn0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gEbAM0PoYz0kTXyuDtZRhRtQJeO0ezbVNuHzWd2Q6Djxe3WZnx453sNsfBBqykQPTu/zHrWi/wfe
VIPTt4c20XjDHHTidMXhf5YGMYpytIjNmzV4g6PhJehJgJTQj+T/bAmaDaXLcqMDTjUNont0w58X
XTjVYtxQgjqcVftNf5PS5GCVpRxSTsKbT4CfmHhBwwsNC5rLtE2tRCpmB6tKw/7xf8VLLD8a23zt
cVvVNX0bw3bWCGFmWZjC/1fhYI19WFrjQO9Y/0zq8T/b6JCoxXV2HE4Z2dJ8uXvV5GV8EStC7VCB
DhBS/R4IfNLPojIIJPxvrbzkKlmuEkhgwflRRQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57936)
`protect data_block
WFEAIJQPdBjKDRJG18vAcLFd/8GY41Ej3Xjgf2FPbB74LGoSUViiPyCMiUX3CA/V0u1ze5GFPioF
CtRZc9HYAdUdgNz7rGArReH1aT02mTSkW9ZmCxpKH+ADhUm4Yln0wrNt2O4urS0mH9hw7HS/3OXs
rL1Ty9WlE32i6iaJu3tTCzIuxYf9ZnuM5WLniUuxtlKb4hEtlCnGbky+uhNaa7Gb8iIHb81zFhW2
5nQNKSN6On4CWpq/kPYk3odWsOszozdnFkDSKefYc6SyamZdidMbdrsHS4IsQ7Zdyo3H2pLjh6d3
Ku2UeOLg5YrQY+T0fFusFz5BmctTziKtbrM/fSTRTfdTCTPqioED1eJ7uF2J1gfU8faOLy76Uov1
2erJ/pb//9ypMrM2w1VLiDJiGOJHLO6GSuAST86c8f+K1o3EGTk4ZMqXSsMMBFnxVUZFdSjhZvks
yIAnFFIjZrWfRYqpdmK2257kZ+uYuBmopLrFlFG0/QB9z97O1bcken85MZJEftyaejLu5olek47e
U4XnF2+YHVpoaTJxQR7+tVM63smG36t0xj2mzP63KWLBHOrAZzL6ZAMFBfbGJ2PQiVdsqgogLqrm
EdGf3ugVUW6wk8bi4vyx03XE0M0v941LgpyJiyxEb8VgUWG+KNvpkHP6FpAa7fSx9gAASVKIOiEk
kmRG1+zYDL0hS4xqKAeJYWDpzoeCd+uXiEV+d5nekcX28XkJpDqU6LEPPkqny1Dc0OK1VJlakcFl
kf6nCHzhe05C98qX1KBKgdDZkWWUF+ZamkqEaEvjtlFVHfgf/vA3d+k/d7AnLkus6ztwsx5i8Umq
WkrhnL0hz+gyi6ldo9xxKUBV2XJEwSXDtvrUMOnxA0l593Dj7J9Gm4ejyp+tZ6E5kZONjjH0VXtS
GpO2Ejertw0E/OPZWcH7suMWqyZBLAlTZqD5F9GF4UqSH1+94f5e+m60p4v42pbCJ+1NwbJdUQXx
n5eQ6FkLR9PhDloieQgFHfTQMCLYrHAPbGs1maoUXWZjtU5sfQjA1wNIFpblFMGkSBk0K4fkMc7J
bk53wJWJ9C5K2s+cJLiG8AAVIyax64Ijw9cv8S7pymEWScIoVxeu26ol5EgvilCmCZkYGh6lQPMP
NpiRFObd0S5yiX6F8sLxSlaC7dx1HITtR4w0RMt+f7yyCNInnuAf4UenlHOZ3rTDcJg42dOqqDXH
1KsvLBCKKrNWTr/pDwJrBxzYLiM8OyhTVNxb+XdLNpzr8JNLvWw6tCG/dt6fPutsJl1kLYbDnBXK
FpRrDz4861lHqS1fNdiRLuIEAgA1QbCJyeIuBt3wq7D7BdYhfrdYXVIoXL7MQJW7ZYKjnJxVhlmJ
8czqJvCuEvvtfsaSnfeZBeoU2ESAb0zPn6EvNGlqETBEYhtEzRTBEgL05BlbY+8Kxpc/8twP2Js7
0flgJyBi5WTvbo984uW2a3oB8pUBgJPyHayT1ch+A7AylI4AtpHpcbb8mXRE3rWpvqE+zClry6f/
X4qMh3zSTU2fruuYu221H9uTLc/dlefdknHDgMRFw2gu+gl9sKSf9E/Ql1Pt8nxA7U3Z556SxphE
KeyZxhmohaIH/sN0oQfpUKW0ltOFSmJWvva7xkTOJxgTEZqkWbjf1pK1CCoav8XUCavIKaoci1WA
hUlSUR3JC9pQ24fW4w1aDCEIvlo+Ve1TWNL/4hRuyXs8v5DrE/LA+jLIp0vrjU+VwV4qgOgz15FX
5i7vi60Jqid5+AvXVYUNjaI6x67ZP9xK2wvKY0sefU6zrkWM/Qz+PGxGyXIXylK1u/Q7d1Mbt40s
QGrjr13eC1fHpXUpTMYWTTH0SS6qbVqqXeqtP+aZOXT2Rp0UlzVjdb6pxYBr3VcZVI48y4+rsfV1
d3/WvwSZPLqjMowf68e1BMOb++UpAOTertAyM6YBHurjOmHMsVPlcQMCjkY7/A+AIqEDc2ZvXG5A
o4a/AknPswVrHGdTrH6tbRkHBfNz0Xlfw4MW2n4Vk14eapqybnXFR2HOO6gCG3PP6nyoh4yVJyGC
zIFMCoOWxOixGhoZhjsXyXK9THM93Et1tl8LprYZDgSwYT8Xf6Hm7vHUtgT+HnuvXTPWTnQJGctH
Xu6cz9Scjesikgk/JhkTFrutZaWrTsXn/VwGlJGEs0zWnSadQDH8nVY6EaJ3nq0/dGxXNtTexY+J
mAm2awwxcoOkBo8AWNPSLOoiIJnyfCbAf8gQEDe4A7b6aTgC2BNkSEZqBVhBbxqzx2Q2iCSizQXA
2YxLHVw/LLy2y3tEO99VGQb98B7d/uOme2xEY9JxM2qT3M7WW2jMD1V1jgu1QLaajURzjytRARft
jpCa95TsIWpWDt4IF3je/WllyorQ5FoK68L3mbFys/Fb1x/8apxIVjoHBzcKTi2eYFkJoVxFnqDB
X4PhpGxhDRe2VT8yxJ9ewCwyVDAhQKa2pAFC49G5sCYpGLdNPzEhC3XcWAu8ApHByeP4kbHILt0h
T9/WjguaZ4NRA/fAO21ZcStfePaVIrP/Ca2iPKfA7M8IAt9zNYJZPiFhoIxddkoylojb/yyyeXcM
dOJ9bE2jiP+GCtuQyT5dYgyThNChaebevXcWGZe5IYYiIoPuJhkMEw9LT8NsZtuhy1KZzfO/ykry
RpMl0qr/pHVKzS6TyfRve5d4sHLhuMDvt5P9QfHBfFn61wQOglnEPMIMiK5+7wRNFRPyw3J2CCaX
jwFROSZr959euTOltz6jKslhriocEYAlNqRZ4fKZ+btsEDJ+YpGydI2//XQZFz+x+oK3w4NkWrhK
0FtkadL5zHWSMnm9fxFGGxxQyKu9qwEh2xrLA06kVLvIOA04UIoYSjx5a0ykL7gn46WMCGwA9NGy
HOOcZqluInTkhqoonnZBXHcZirg2JP5i2Hjojk4FHQq566uGHjfSKVVz1+89jlrER4YV2W8T9uI/
X0OX+xxwV+eWUkjWUjGFrF4i6Xmc01Ic+gS2Ek7DUIZa8bd+WejQFPKf6Rprjc++rfuLLfjShPFB
9wKxYTiRcmfhGlkBMHyKnPrPBoA7Ney9J88ToOh6GRtbWh3XPaV4a/zeOTxj3Cw+AgdoWUtbBGh9
fF6sCFQD6DaiSK4ofPzdgQtdWx58RsRX1DKCzFxXZmUcQjAYTd0Z5XIq/XuzHAuhjNOpO++Ih0rZ
6yB/5qe74aFVBj9w2N0XtboA9Nl40s7VbKjz0CTmAP4bCoA3nOPYAxt6leA3FnBFoXfpoeZlq6pQ
ctqD/fJ1I1hb2vGUTWH+dbmm+iGYCQtmDk+bazpxqoOkiZ1wTwoXyoHjz83fKqKHHsCSptVfTYtY
D9V9WnSJ8ZrJfU02k8BelM/Dr8TAGx3PKYcrBKwhE3Wq8h2oWFqtLfac8irxbx+Tc3PRz2Jt29hD
f2XP1zKs4jIxAej9+KRrKfwHfq8exN8HmZV32Q6083fK0NaoXpTZiICxicFqezrFTEwTNI2XkvtR
au4pQ4JbqcHes2Pln/JJPgXBSMnrUZBLWEUGvF3fqFM682uO5CAl1MEsyK/gARuZopfuJ6oWpuXs
/BhLzmSQxbUJS6u4+dTirmv9TXcW3p2Ww6LmSP/GkfKQWO/Fm/Aak5edN9hqN7Pdy7ip6vpJ8S3K
upttJtDv41d6wjWj1KTDASHXQo7KtL7inVLUChExv0Z7IbwktJ/+Q/+mIzyZNCXUiM8TROw7BSzY
l2JCMOCnSFeMkFuT0wLusTxdwwjcguQFE+Z2FNgNzjRxiVZtMZfyNY9xnwysJzQizQkL4sGRGFpa
MUYU2ATzpfkuealpLKZfjeVBOMGwx9WS/OC2W/Rp0JI8fA+UD0A12G4zWIrFBs1RvmRQ5rZYPb1W
mOi1usfH+lW3Y++msZxRVGqs10zqXJ89w8euHXjTh5HVEJcsUHkqbwvtgsDJU+WLKT1e3T+IV4Uh
KGcTk+KOKDvb7S2g3pTYIde1LgVPWO5dBw0LOyA5DCTIj6qeCmHNhqKOQmdvOwkYte90VQ61Q2j+
yxiLJpoadgGK8puwXBTH1y4QweduHDYtpW+b7DtREuwVJJbMIwnHgr+5QO5qB+C2B1/vtot/T3cL
+EAG7sEMHGUAschA89EwOKpLByH7gJ/WB5wlwem/V+/WkRTTIcPrGYxqa7KFidU65qoWnpiFz9Y1
z0bnIG4VSGn6ID46ompJGMecvk2MI4cfFfjpZTJ8jVw2PLrodPB8o7aCwI2DH5EH23fH/DAKK7vE
3GRj3w2zHjivbN50HeCn91iKHK6TBLC+SGr/cqoteePivhwu8PQLkzi+APv/uIUBlayGcF2oHYHK
tNu5Zt8miedndemeCd8x2pzuAAf/CmxhFRJJQqYtu4LkPKXoMqPeBFVGptsay4b3PkrCpsjiwuow
SWMSEa7izGDAoUFyhG4x7tQ2qR7yyJQx2m8dySaewMQju5DROmwFkgDKUoFzxR11QejjeEUuNSlf
nHZuP8FxVfxAg5dZegjKvIu753Qgo+12d8Hx5Gq6HE8L0T+AvkH6VjPmOj4TysT3xGPlcVGESUuL
0ex3f89onOgYK8Cg0A6K2KNRkoqktQesgj72FHXWJkdd1c3jZUuz118aSXimVlT4cGBToBmuoBBk
Kb/dlbY4W+Jh3x1koZhjo6PyHcW5JAKeUk1IpEoJMqX13pGy40prolqmTtvuMST+/sNcrjMXBAUj
WKCQltOvCGOSBqIuXdoDR+mNkMSOb1KGFYVF6Nl5LqoShOcZbInxyt3Lvfc98WqfHJtmfwFBFl4P
wtFUaf0zWxtlxbH5FIunWGweY4ur1OlbTDdKvjkYagcHTO5MJsILVgVtYyykJjZPva6qNYwqVTLf
qXBRm+QHKmCXiFJH7tMFF8eHe2cBRP1rXPH1O9EFjULoPKQiQiI/iOLQ+XTrgsKj9migEqj2Po+S
pYyueg2vlO9uS+njN0LGThkWMyDdJjXY9neJcMxhxstqh8VxfEG7Tg5HnPFETf3touMW41dSYfbU
NtJY97cEa15dKaWOSxts2wNArd4Q6PhBPcdbzoFOFRA21kO/meO3mC0S1zLYzr3uA0crjYYfjEyr
UMWPAq0PkaXcuFyj7TRBjk767SpsvZ5g/1nIOKxUOkgEyzhEayfg85Kykkv20bPJhwbMpW6Ne0s8
eQVfkFHfARJ1l4VBSyoDzHM+4oOPdCKjl/C/5T4eYSI4Zvhp4x+E2In5/pm77mZEjUaTCAgcH5p9
72vr5moP8rRdjMXTLt7MV6/los8anTdsKYcpZ2PenyvUnuaur4oykXKtjusRw2csvx4sEyjkB21G
DsWePxn5Bpp52xdKatwD7WUP628hx9B4XXMYnNBS2AI0jBwZTD2XBptKO2QKrB55vGVvy3jACoIV
eLxVeyYkZUifvaAiOMUCHddMhBuRJXvv9eG1ysaKBLaDdOoQ+1xJbK8RG2ePtSd6en+EkDVsHCwJ
xeRmmc+PLi0i0cdcmPuWT+jrf6Y7Z3+imc1ibazx7ZDx3mgO6KTiAlR7X5Nyandg+EhxG2XLhUvp
ZFgi7MZy6/DzMycZkAIz3qG/PC/20A1VSV9RClI2whwA1j3P50MP3HJ1jPCSbTX3qy5HgQwpznCj
KuehSe6GlGI05M0m7hYJEKlhlEG8vdKRBon8aSkELLihBwPCbFHcqqjf62gJMFOaB3Hjr0qYbaoT
b2mPVqSHb7QHNA9RC5EizkayW0nDXolbJ0HhAY3eBwZJrCCRqyjntljhxjQwWWQn2CEbB+pzvxTS
GrYJMnHvL48iamxi4koUxbTE8qXg/V4ZKvmSfNYtkoTkjKfzuIplAb4hTNgOMRfUb2HLQfJ5l+9e
gs2jQ+XG5qOMWTBc36Q7wL1fL0L/JxW17ddwM+cbAwo1y5IrcLaYrXKnO/gtAWl1KpSPPMXQtu/A
LPdkqfFwiQr1vAM7KNRWGVSlaaXoNFojelPhPu1IuX2B2JeHRXC4rbZNxN0GkaWf0wLKfMZTW4ii
c4Y5uCn+svJsewef/a7ckSo6FDTUDxYCY7Xf0hzgq+MHZTzdo29BaqJDdVVH9l37+bwx/6FzaYG4
AUQe18nd54a7/svkc5avS07rd5VTv52V5UtrZx4pxGyPtbRMDKS0WmKXCBdeqCtXyddvFmyVc9M/
cj9QWC5kOvaDlzxwLkJJ5xTmHFds4WVT0QrPQSvHjWjBTSEaSbqKds8LO5/XuMrswBm4fBigw5Xm
pze453uNc6TzVsO8bUqW8qgho+4YC9LumFit/WjeklYTAu14jqR39QxMOJBkZVKou2Nk12nFxwCq
b3OqJoXxsm5kJI2jjRvEvGEISL1ASmNzWV+gS2mLtR/X7LYT0DZyjWGTeDJJFECeeOaRrOajjbKA
WXvTgWc/TKLf3J8p0muynG1nldFBuGtsMJwiQ+6A+gkM6oo+hHG1xIdaLH7LzCbvUBSgnJdEAflP
P6J6kJk+9HRB+KSNszQd37MKbtfJKqI357RfXsFoo8tzUlF/UGkdMoIxoLPfZtoQTukOLKE0XjHR
QdLz/iNBFtXHy4N34GDvSLoDqENFwuzYPeKZcwWdt6tVq+snBydjEAMAl5+zaPCbaSucqHhnYkw2
aanXl9JDxkiUxNOzryNAHS6FOFc+2QYgSL+jlgCDXoGMHsVZJrYDF0hHeknmgb/k7XCnDRtXX75T
Z95ujU3EWlE1bcgNIBOunHP4CSezO4zfN8qOGBJingkbFZNP1BluiS1Pw0PhfqoXzmXrEHcQ3BF8
6xhWCh53ktEUfc+oQTJbMH/P6of2ng4RlDFI64fxHYP60AhNj/56cGqaKiVjk1r2V95uB/m/5Xea
gRPNSkosrECs2Yuxvmj9xUj7l7N8vGtwUUE53Vnmd2lug95jKfi3EgnVCOsyInDFY3pBLhsB+7Vg
glCi9KV5H/DrDbkxZYQfbHRBFudPbCIOKhaIuskqPZrdFMRkdXXcIuDPf6hPzIu0QgcQwEd0ErQl
fqXv8GUIEvf6Zl+sHFEt0uTsIB0I5ARzWfT4NZr28gEMrk9J9jomH1BAC2VjtTH1m1yhM0iNKwKC
y+dA3qGtDd1eVlmKfzoTCun7jHH0OUbhbNSqyBQWRhh+Rj5Anh4/PonC5ZiWwcRWdY9L2z9r/w96
FqaKa4zTUDuLobYAxRCAFCLMVRFaG76nCju2ATUcw17u8jKEOYyn3NsNWULrr37agSoLiS/BF0DR
fN2wPWO2rr+DrUmii7xyCCgNwVKinDwaoOoyLbhN3vp2pxs5dGIoRZbVc3YDyaI4VFHmoe2APGgd
Aam6e1PII0qvxLArekD5d4v2KFIh3fqoJesLzTqtwP1Z6bh4wHzE/kSaPh7iT+Fyzm1sNIeMQpMn
aa6kv/QN+xefta+zyt3aT0OdxZTNqFa/+LgP7oB6YehPlb9mPpwKJYGh9Qct1s7TTYluEMBBlfap
lf6/daObYj2pIzPeM1PaHrV2nAgafxzm/f+PLE1Q2kMRPSMV7NWTgQhVAhmmYOFprtO0YsJQ9GBT
vgzUQQF2CrEBGZidF6C+BMl3VsWfk+t4apjZtiMhUe/lH/ziq+Q1CGm5xvlixI+q7ZWHhmsAMStd
VppUv5mRAlpW/gGl+1DDmLKwbq6IymlGYb6Uw+eXkrDLLPrVeVlIdqkbAr3GV5xzxBhOIDjANDIo
4hHEGg86QQw5iVBN/6/YMs0l28lva+9LtbPTyHKGskJK4620ebG/bZ8XvW2PKW+AvPE6eXNHy1Mq
JbFBPrbdqLdXvPspRZFU2DWxbmz7/XK1XVD7mbCzr6qtYSbilPq7daL1Z0/UuqHI38tm1WDDjrIQ
8LeQi4oPWLfxPnG9anXAyQRUx24iwdTyt5xkm7glEgiEbq08lY4yU9OI3baHyIGxQyjtydvg9EWu
GS3qKk85bvs7mjs7f4NojmiLmtkkKDJFwIj4dLl9sFUzgV15C7M9ZJ1Z+b315mslkIiVIIVNeMej
Cv+UkH43qzBNBDgfFI7Fe7MwYm2JdCEWrzcTiiAjWat4Z5+5z7JCCUWi3aoNDQ+xSRpV3j6eBUeO
CyLl4xhjf3HfePXdGLJC4AcEiWr9LoRrI2lPQ5M8AycrcczbmqJInl9BRWZQgcyheOWKWduRq54i
/tFy6Vu5uY0WVgKNW6Ut68pbX/CjiPQTFf+XdOfwoiH30y2/OBmld5XKV7S/ofOm36ybUbwhEd35
KyB4F9jkN1wKGCRr6TB7B3I/szNR99q5WSxHWcfq76PGaNRzPaSYLrU6qkQ70lKQ/j3VoHeTNpRH
5mCDMHj6OEqivMooj0JqYbMnIKNhT+Ewt3zMUDijBmffbSmE7GdXBpIizgaYWT6s1lbnyudAmFTj
mjZBGPSRnJKhZyc0kNGiH9CEJ2GSbtzQV/RzTMmxx/WbN217Fx6Oll2wJ58ho7NDc7PpPjSkUybQ
9vmWWfQHqhH5bGyTz+5ZY7kavWpQWZfFnSb+17xDnjuT/bYyapOfxi5kOQrGD4JhSV5/mkFOmjiK
LHj8fyHT2lZkIB7w/oK0nL0O/3cObRD6YavFcygq6kCnWPDMBM8fCQwMQc3mjwoUlq8qk13K+qOz
D2Tax1bQV+vkYDO8tlEtR7+Es5KtU4DkRFeEMfJxgIFDvvjT+nc+fQFYVzp1JXnUKqNy61PpPYAH
kQA6o4Ji2w8es3nNd7CWZhjT5ZhGfxFRWpActLapZrMzcK2VhqH2ZCEaLnSKNKIYriI9wnFEhYV9
W56mxOVGa4EC9riLn+ZUZNLLf1YMMeqYXCtZtsINos9t9/Q4heD0g8og/tnAFpuacON2/9Xnjehe
fCX70l5A+H7DI/Z5cw03E2PuUugR1B/pqpIgbFz5ZH2WA+jDWeS4SDu33NEqbZJEJo1/XPuIjKVQ
McDywhUubv70OQ2WQjGS0vUyPHvW7T9bPntwfdiHi5bEBeDNFAUFPm9U6Pp/nPIW+0Dz8H1+xmCA
M5gq4vMBxzbEeWi8jhSWVOJ5SuUOYN/nbzuO3DjoyyAGjQxslzwCDgFQVg1gr3xpfdbvBzgfJJK+
BdvUqMa4HFVNbTltOE9yF0uT/93T4jfg6+T6EByUZe3E27DTKyWe/eSSVANIQ7JYCzCtqAp8Uc6j
Q8DZVbGGEL9b03h1KjBFcAjykoRnnIupnn46QWz3GZqnP91s3qj/zex1QcEx2CwIEivm+iYth8Xf
LQagM+pD9UkavMbKN/aD6qu1EB3d4tAJy3XrT76WfaSjGiafdprVzanbKGRL/sLvODgThfZN019m
bAtfRS45HSEigjYenhltYFLRKxTqxr+G1C3rN5gp+IuSXyjaSWVBh7HxO8MDI6GR7XwvJX5FyXbb
kwB3g7ztflXYqs00fLKwcjBPpOwHIH8abdrNWPnzXbOeCc+CNVr8DtUUrLgNBIM2kFP7z8Vpx8e/
uZZwbDy1vjP4bCWUEy+1GHz1+ALolE/bA7U+gE6XgB72hnCitw0EerU8SCpewpZ+PdLY4YUxQuQd
nsWqbe0uK+/EyiTT21YUJV3Xvlz6KH2EPBytFRyFffJ9ZygUsBjZbWDD9xrWtpu9V+WEckPvdZQm
lVfWmzlMEs9S1EDdnEo/anKzD9/rwWN2AEpe5lRVfUV/i6k4OfiCGKbSNewCbbkmJGHhYmuZE6Wn
TG6mvw8BYaQVppPtgpPwQv80tclHH7YrWIREtPYsoHNO2IbpS705Xto/ClPbPP7drVKnC5itWnFG
yvgus3Q60KA6X+FbtgBMJ4PE+11hbTNySTZVgZbB42cQSQCvzw2ciGGM/RS+3wE3Vfrn/LoJpB6F
qhGrXjRrtbqz58vg2gSgH9T93J7poPhgY/3WYysUH8fRLqb4wFSjBK8ujMUxDxn12CoOtOxtP4ke
/Dl2NGmhd6z/8o004qdVj/UfCUm/ie9++Vzv9WQW3oPjhgyxQR2YZzJPD18+mqe7m80zeYni+PZj
zvW3DqvJBxCw0nY4FhaqGg0s16C+kYToI2x8odUpRGAM7vkOLyOKhqoPPfmbgcgTjibM4HQo3Ek9
xmpCR9Uo0Xv/47L0mOSfBj6RRpnx/S3/Lt/6XYZm3gSGi4wwwlzjvUs3u4GIZnpVWHASGdXIIKlX
dYUnxp61mjaHCy/DV/7tkKZd9uP5GXKzJMDCLunt53mwm6fbNKBNwDcWvyOtHZcdNt2r8xo/BHZq
LPgL3JLsuYLQAmFOSBIj4NdGYQ8Mw4vRWS2+g5gNkIc/cfByavwKWMawwxpSywWWYGTYfhT/5A8t
Bhf0EYS5NOg8GnSHsGfoTbRVERCD/o90YstA3TQ0qXhd7VzuUN5cLPNNbH8fHp7D/HVUROGdBq1h
Kqe2yDJmGyn+Y5AhMY8tASZ7YwNz5XDXijkswFsUwms2UDfJM8U+s79RkrhYxeDywnEvDSjllQDv
pgzd2CMMVHWNEO67U+VCeODiOfz0EgQ6CDTeCn2K1CGMDg8OxWkKwru82yAynql/WHFwCXmtSvWN
+1Fjz+G7dfSFif3qsBfHR5rspbHYdbLilfiGHX4QiaR+Bt8D5XZrnk7leqLdYv0IclORodvw6pXD
RgvPu3VvmLWBayQd7KQiT+dV+Wovj6kHJaI/YezbYAi5ydhkrcJLgeMpntrUE+Jed0itefxoNlDG
mNUeYg5f+xK8QFnoTmuYGtW3rh7TI+DNQzGo6Epp8AwgShNqmKf0QXWCvEIN50GkHlw7mK1bObAf
aT3UN6EgVJ7qAB/8z2ym8JYr6nvBKKQ1hoMYxQiAAzksbTtZ19F+aenDT1DxMyPG9n1NMFaqTFmw
rtH62IDlANEoas8K7KO29YFp8c2fUc2+tJe8xtOKT2hF3zHw4ReXw8htzCYK/8KQuF4Ve3KwuItT
TjxUUwQSiCqFp+ANTXySXjeFVW8WaeIlWO/c6M6c/uw3ECxs9RNlmAuEBhzgw6LZVAX++mOz7BLr
K81hSeFqWo/jDapCJXBHT3O4wjjP29NdOvT30tGBGqjB0LJ2nPlPMMCRzoJw7fUn23GRHyf23nnl
zoeq11QFwa/IruMJwxE+gXfE33Qu8FMM4NnCy67PWUgXfiXoIgYrUUXP5uNI6aSe/YFlxRcRRBJV
39q8Tn28/8HefEPjRsqzoP4vZZ0wrjq9btL/jCtXRhqpbVaXlR2V3sr9FtNUvCv5l8XqcrY2ju/Z
f8c3puwDhFojti8gUWU0fSILbF+IF0i1304XhTBYO58GyiDmEUhn08uhd0UG57MUgRsUy1VubU9K
YZoyNIss/1WbiFC6qBq/iscpgVbwsHJkAOjsU9y65L/uVxyCpDIPza1jb//1rzJbeCP45F6LQwQs
CpCVZnradz4Vvb9Ja/ej33gn8SjmwdnHodK2Yqc5b9q9bfPlOIesEkp4OAUX6MAWghVyR/6Ovrpd
lFl7j26ye4CeIRzDIO2DY9uwK+78kUR1cMKWmEE0wNyLCd97X3mu9BlkMIEWg5tx+YdSxDxLbJAz
vaitqpjMhxIopWfC/FGoqgr0Li0x3ylw71in+3pmO4NIrX+R2SBfaydCv6PKdF14tXqXwU8tud9x
LsP2vZ+SUIMby3YBEO7j7jMcozcYmZKgX406tlkBzDQlH9Ui+iSa/eLiZ1pDfn2vJnXWYDq8INCK
0QMsfzuqdnohorbtWMVrO5rav8+8Dj4Oc/Gsw2UiqBX6groGA8HbKBQVpfRtc51CDi/VdDL9Bmh8
+2SE1/DXJ3ZfFpOLbd1TePKfmTWiNotguWolBdSERVDBJWTptLL3ZEzy8E3P4BW6tWHrCFq6R88H
ob0NrTbTn2W9ft2+MvTh8czXY7Lzz5kNB9Wo5SeGs3uEA+fr3CKJOtSKQ1eACQvM0IPCqYKfWFEB
vu8IzecoUhvo025LFj9OEixUZsZhde8OR3RRd/9QhhgKHbarCw0oEFAtRwcGqHz5h3mICGYkmfNM
HDCqI/ZWSCvD4wTKNvnpGuglqLubDApdO6otxj8o+JhJikvl/IFxh4vfgaXTiRoLM4myMiZ1R+FG
yOljO9vNSCY5XpkT7D/jm7tsvEqsX/s5AoVP4WzzwIm9vZBPUYCsxMjhrXEs3nRJPiw8XNcSnG4i
y1CP7e9ZL5HeVbchBn2H5NnshOiqQU64U+EJmK5Bz9OnIffzXl8xICglVlU7F1ws/n4H0SXDd4hK
Ut1eATRnvCgKSkthQgylcXXfcXJA0VcLALsGTDGu/i3ENSYDAOAugiDtM4gC7lh+8326rUxZHELq
mJtBwcGsXXU4IaChH1cQjE97W/aHNwuIDImbO2N4Fqb1R3vQhyaR0lBP9jaM5UzRSun2RmzPhOpr
h0wdC8oxIVLtOOqh5vdnil1+fG1+8SSoqA7MiFIJvYp7s0fEf8mNGhwWl6bW8tOEQXOHlSIrzqvi
JXIoFZmcOy6VWRpASSsY6608vDguI30L5KfJusSRQ871R5xqYUnHMrCfPHIheOxVmc6n/9HiaA5T
MaHXPxeLDd5GnuHgCDEd99KIOFblD+T9N2yMbhHeMVlMw29pXR2YSppt/6REsYMKv7qkv0iN/s2m
y2/P1Lg0QCdReMY/+/4Y1sgbT/w1hg3ZPRuo/BlQbwiYl70syaJtlr8zO/Bqf6w/kKka0ToUpo10
nneULhTmbPvOLhjbJWPS3oem+6WZaUOBYzVln9iaHOXcp1sy8ACfJRQ1j1Xc4G/4UYdj8Fm2hX7F
dafBOxoJnPP2gc3yZTl9F+L01wCFEDExGAzFCadFgjtfEA/TD+2eu+JJqojds+g5ZUH0pjxGmumB
EN3IVH7YmVWKM0CMz1QrAOfDWK9+uHAfwVreYnSw2lIgZ+W16EK0Ga7X4J/5r2XpDWeQdWwWqXbs
DbN4rAky8yWWtyRSjowZdA2/tI5PJ9+WjTQ+m9JWlXrkSqlaEB2ZBq8bC5HZ/0bGoMXIM0wG6u46
b0CIgaSTqPgjvO7+RRLpr83uOedHDCEc7+ZuJl7M2f5e96/t4QtPyW7/sQU/hnqASlAKXECMchtU
vDBE42IrXysBGFqspu5+x6uE5aYy91novQ4R6d7InaLR/zWy5V94M880gic2pChln6ufZQVl6n6v
ae23Lew5yN/ecUFtBjev/TmsLoj6oX7/m8jT4b05O7v/CVMuBwMC90U/d0FgypV8bArtPGMN4dvh
0LbEI+Zz8KjLxQ9Zz4a2RgZ5btGvhIEl7M7jCqciFietQJqNti0fT6VtL0c/x6/VdCwbLXmaxTNR
EJeolTNWMmSR8wNuxY6Gll9NLYDpUwDOhG5WIoIc3k6HMlhUiYLcFsVlN8UfyGTw92XSYdQD3ONz
HGaI28/dLqTv4PSwleXpUcXQhLitzllMCBw/7fWKa+glIybY7a7Ri6R6YbJaruaBgqxsYYUMCRu9
bXWVliYEqHlKHgHH+5fG6DvskQlJ96f1y12K7PwDddgiZGHzzjMEt3wUBEDR9Hjt+SK4jA5sUP96
rtqiFFcv2ozXUPt/0q8zVAj5ACVRXIr0kVHjjphfLc5CPY2y+pAV4n3hEYx4KD6bFOBVeu2Wo7i7
QV/IHsPkbQbvOmo3o7Zg96q2rypxfvEZZ/tfJ6zLvoNTypmTCw7YNL9yDwHkJR8Nv8kp2rfqC4vo
QTmmhEL4TM1nyNoXLTGu+PctfoCL8ib5SXt4MNlWxl4E2wMWhPvnjlV+s592k6ldFCPwuh6lET20
PM9nCAk5bPgz4swV8aTJ2X9F2+54T3OlPODgVDhM3wfV3XtxZYQRX6b9ZDHmQlO6GpmYOL7OCR0C
6H45i2lBY1EZtw00R99L6pCi7WSTfRCUFYzDeqjRcibuWu/XJHoxeyM7Ew++Aa4asb5oxqRI1UE6
0fl5Vol6vRnDRUbS/vDyaomke+4IlOjEI2TFb7vM/3BFnUCo9121SKGV6AibPDLtypSVShKrndOC
XQjP/LOdwe+7Q32SyzdNVBuV45OWpZ8tTSlOjO/H7iUC1bKFkYQN3j4gMJCU1w/UZDqedEtCTaeT
+deABiC356m/7cz1HSt8ClNEwrXm6UwYmqW9Y94XNa21n8A/pIc3kDmMQANNmSIsNVfwHqdm2l/U
2Ra3QX+qwOsmqAPTBWIWxuvLxPbbqcpY76e9e6M3jM+kYIam0m3AxNXoE8JsC4V0h6gh2N027FkB
SqTOr4H3bunGta4TTLtX0Ji7pNDs3rBpRFcPVyg7ctx79VcCxnbBmmg+KOr2y8zsr8nKeftNR771
AvqN/1LIUByRFA6SSd0CuAlTNlf3+wICtXMSYI/Z8m+gFkIycNzE1DWr8hUWz4S7sxfDatAnM5Pa
hAxk0namAkr16Ss52R+HMmkOiWVYC1XVXb1kHBMhMnsmgFJ9QbZVtFEaCIcg4dCzibSeVprleadE
b0t9RZHoVplbHGkZBwR2ifEElzFG/NtMDL4pzBOWjKpCwBx+iFfmCRddGUtg+BC+e2j7su8QfbY1
Cng7P5XsTqdj/gNQe4vVvHdBRyWvY6UHMax+srkv0D6FBy3KNaVb8mzSKWwpG9WN1KdE7/18R4DD
fyMYbTgrmpE7ytEPUB9G/KsEK1xFqb8yYedecgK8aF4CXJrXWJg2wF6LGQye8MNr2qdJY/ZozCpu
sKnjnLPaV/NrgoByz69VIl+hJZHiZDKwIw6QLZXzIC3Hd1Ch1sjVyM80SD4AaVnzCXIuk1OIEWMs
mvqNiCPQtQRdjIXXmliqA76frLx9mlmVCE/OOs4hrgHTuty9a4YXuB4EREQzHIUMEZsB4aKqb+19
A/bMgJ1OIW6kJit9yi6fny6ZasuFgl1AQdJ3LB/Rc1TgsxMmi4VATb5Z/vDPbmG2yG6omWpvymiJ
CYWo5l5/xZ63ffC3EX1OnOO+L7786bLfBT1U+ai6lKwHzbRCu/d+oCTfIyXKp3WLw9BK8VrHZd91
tLTz5rcGYgIaIqiNFsLsmuBY2YcY1UBkZ/84xwXwmqWdQxrHZUC7xNsphTDNPGfpPD++gunvtOek
OBPjvBO+6joGRqvaKD35zF2PKcRZu+0Kx9/xyIaDebWP3Div2I9R8SctxnG/Jb/khyAaVQUOVGs9
aRtzhtQAxlzqQw8345SDjxo8xmp1n0P0YtIB/0A+a9uJweGrTCa4sTBjbtT9587m9uwXwzIzKwS/
GsJOQsN4ju/xnUxlFMROSxjj/T+LH1dDivlBtZSffrA8lnmRQExfBiuAHcJFJgyHvAyqCmSMxyWf
zksuO18lRMOEC8gzbtkwLZxxmVBpDPx6wm50UfkA6if3myeaVLrHF00hcRKi7Z1COs2nQpGTvuFq
GuctU1aLK5vbBTTjRx36ELWLY/Itw+fA2AFo+j6Zy2s4O62NwoLoBSybw2s43rHkKfh0iWSuMZ3M
fI0+14iN90AioZJPUsSkKQ5JQ58kXq2neLnye3pbCluIJE5uuSLR3ZCWvh20WUi51qSjDTevXSpe
mCtsCU2EOFnPPLbjz1FbAY/JTvQ1sKUmrzQF8Pn5qxKj7B9kVOLgacgjm7EPrx1Etg+5k6RE5DnT
IJvfzMM9mpk+sXRqAcGeVTXdJYorr63lpdqiqZ+bdrC3LP4Zembyu/e428e9US/eW5ndTMKqQgwK
NkiW8RlsPnfBh7T95D40Mvb2OfCtgmVVYnhD7zGqSBIRudAY/a9PoAI46QbpnJ2rJp8TD2MaARLE
faR1t++YH+cW5N1v7ohBE3PPStCbVzdJow6AinjiRnWJpaEyFRssU184HaoczonwsGH1Hx3yLyFo
GCwc/vC5Y90JWgQI1MFtCDGiwunTGc05p8nS3tB2RW9JSZL176JtquQnOtdX7jWOtpTuIH0RnVxW
bDYgmxC7iFhOYdMaK4BSREl3qkJFfN6Y2CKamtcFiXuzXufQhOYbbnYBASkh9ImM74xBbRokx5ip
tr+r5Eui0wA6hTBBBtdAJR+fuVNOqW9A8NGXCBsb6j7hkri/3WDagk5C3sRyW3rUkgZiOPXFOzTI
ik1c7Hj8vtaNpFB7Tr4rpNOGXjv027RzBg6d5KSVZftSNiQBcIfmdaH+8ZTgBM1W+aulnlYf0iSz
+lTF+zRMvXyy0IU5Q0ERNO0Z3U07B9Pf2mJmNrVsobFBMVA6Yrj8MZSiY0ArETpmFjYtnoZwp4y9
VU0gD9clxU9zOuk9rvmTdmlwsDXHvFMNUHWceurzyR0FjZE9avrnD45PzG3Fw/ceYWkJhbDyZUoM
tDR7EYNlA9CyiZcWuj6QXGEwB0EluLmLUgFujxUDtue1OSNkBsBsn/noNr8FbgOJbUvppyU+NDV7
JWq2VqY6L06fhTPyK5dKf4sv2nH3M/lTouMG+DjDti7lfbmOcv6zh4ttbsPQo7044wNmh3uNgVDs
LCScJN8l8csVmNcL23LREZJ27P30/cwCwH3hUdTEgiayr8E+IthxDQ2E7aXR6lMvfCynrHrXvF8T
BsHNNlOvL8eE2EHjuQCVjbF/saqAO0koB3MIaxM0ArPBFfGS4M7YaTiwQhjn71jwceYxRAVliETo
4k5wrG75uCKev4zPhHUfOLmgR2xTARQeuEI6MS6RbiXFiS0p+JjFreF8Wt6vh41kLGPOSgVktwB+
d7syGB2HgoIlzOTp1dG3wo4SecuvIzgSsGfulzUuB/g0UqvaNrentKNkHClKBxWYj63/73VEDw1b
6z/5YyhkFEYtZsbtks0wFqaeWZQOYDWUSXfMNLKkJfGbhUlgB0YefD7MKRz6uc4m+saoI7cizqZp
TwCl4q2yoIqDwCR+AQm5fvAV0bhms+R75wlBr0JKQ92IrVbaHRftnohCtNbxFcray9aQ8wUmMU15
w/WL0Z/nQUoS7CnUU3y0hNcTEdoo3xkd+v22VQMLPdZlsY9juvoLZdmz4KjEF6Jz17TWSKXArK54
QHM31njh6t47eoWirJyouFRbiLviW0+28KjwCGw6vGgzBDWMgQXJhkqB+ucG+7CJOD886+Op7OJr
j44wiS8jXJ33Lz/mNuUOSCOF0oPlEeJmLOCyZh0hdBSqDQiu6Tl1+qsBW4Nx7/uiz+eHFdrVl3rp
ZuWwlsD29hbHB9JHU54SrOBYOkVJFPqr5eq74MQmr26t/nyOg0+Raczf5r7I10NeaYxrRnc2Aw+o
HWuv0vq+uhdqNOaqNg1JDPu7kW5WoAilWJ0RiayeuhFqmodXkkQVFDTVtSFfOn8cmve7AR9P0vgy
766oRJBcxnJHqA1DL5uJG5j1AsVMAF+GT7d9sWuwskYNQPRrnsKckTgzV0ib8Aes4FgM75WC0cdg
kF24Khp8ePqoIGzSVnA4SzgQyTRHSKLrvJE0B77kuHLHvTcXwUysmtCdgBWndakR6SsyZakxqm1S
je6wlgYaLnNXVCIV0zR4APs4cyiMsoXLShmsARbGGduSeTKPL72/+xiWf5e4ZsslVGCmvJGfxfUF
LxF1f/08eoXFX7k6wcusE+Y2ekVfsMn8cXu1LhbEUyADrePUwuwy6KxS4KSHbAeaQ8ChMNvSd6ox
u3SBgHSnK8hfLnk+75yr7+CvdzNFgXUJMpqJz8xTb0hPaS7Wl12tT1t57iJ1833kKBh8YjFQU1C8
TifcwSBZMsLw1jMCZzCprQkOkL/e/HWAENlKyqu9ZffpycGIzQj9yj0BiOyb+oeyJEZ6/11U6Mh9
XpBCypUtt+nTpu++teeIFrZzpIKkidFy0bw3Eor5slXp3uwwqhjsl6SbE9vklg1wHti3S9IsUiow
r2RLzUovpNhH1Jfi5Jmkacso9CsNyCk0RwTIoOEsb39atfInWjkR/8zDaAORbSEJ16CR3BS5xxf4
wWs0/wsPvp0R1lT7XM+KL8eLSbxYUyYs44D+yr+WV7WrSyQGVi/tyiL+Gj14Dzx8H5vo+EDJn120
MbAqeVbfynSaAgxQBO5NBXSRyqn1L032EUP+MFjLV4dP8HrwEfzvcpDWgKygiXtGwezZVy0yzwWS
K6G6u12QL3cLhDkK92OgfodJNQRSJCxOWoB5e2uaAuuEhxdAgv66Zvj9mpyHIhhJS7hy5iUVIfhI
N9H/vvYWv2NDVsHXaBxGYlrfWaGO9Mv3JX5jrY/yqqYDsTL4IuhO57ITqHNu9rybkOQ9kVBXQFmQ
AKO+2Ecken+M7OiFiI0WA6iNnMf074t2Xy4Q29q/UBfuZXQ4WHxwd8jUinvZKLN0p7+pv4oahsUj
/B6BuhLduwfC52yQei4MGT3I6GIqDL4AYJkSFbJaWVNKzlYhtWpI9j7sgg3fVuxkTM0myslyD1II
ap6E1own7kNIQ1GKtnjsr88ej7gV95JxMnY9raKgaeqji/2v+l6kfQcV88wC7C32MNMbBITEuIdr
L35ueRnwYW9sPFrGA151s91T18CFPN9U0/9x2Wlm9jEtWNyedJKgly7cRNT7X5ZJnZJCgXN5WUDC
CJF8XLXducdh8KMrIND1ds1B41/Q3f6rHsuS8IcdXcDXDuK+lmo2GACRUPzEbAXYujtjpH1H720a
UME7+LM/P9WuNSooMqr0bXiqftGJN1fgkqqPscVPLqLPvxpstb0pzHylNaisYW2JQw18btiwrw4a
PnKuSbNGFYb091HDAu6Nbzdb4eLHdL/v4Vxe5jhmninmOybB/NkNG2pVe/jnbdAHrdhlC1I7pAZp
u4HuAjd6dSy2624wZkgR1T4fKE7vDagnHS4n07f27eoTWFBEWTnswj8/US3E+l9S//JVwTvFD+3p
2XyeLUDQVXKYYm0eoEdUB0pea+37YErf6NNewG/T+/MmI3nyTiPF9GooGpRRVylidC8qJNNsWWso
6T1IgeWkexBHFI/rRz2HbjW2dvvYXSttK4VAlEd2Cu25dqDPEfbvJF0mUAKAGmqUj+FKzxQX6hC5
WLlsBVQJyPH0VlmCNOJ408Iw2P1RxCHuuErn4XRbw1JxlBs9xkHwEdm+S1q/a1TmXunhd1a7oYMk
WY4FRGfevcE4YGBRAJYr+2pmZ6BVFYxkxb6sjvddwrRBKGleOCeTY/Z4qrNmZB4MMuCHOI4jfhag
vUGS37iKt3RdEZnRt2sp82cadm4nZ2y08Fv7JDyefa8pD6HdegWV2CDWGli8Br55LGtXEStBHG5v
KeLUcvsHBGg020R4XsNZm824TNcP5t75yAL6wq86AfjOEMjgAHinve1EDIZXvpWYpetqLrNAWtFz
1/LQaXwe0s0X6CzaM+oVCnWHdwqxGAWi8DwHUyhMsF2M13m+caNBcD4aj+6H+u6XfBxNndozgYf6
x31zRcKOpZNxRtQEhuonQgrld+V6fXKxWSd5LKECgi+HdGgqXdqtpUql1I2dd3j7eZxB7Um/zPgj
osYKLOKcQWMZ/kN5r7uIGRdHjKoXnlQt517Px9yHevS2hAMtnvO0Ho/qH2C7HALNiVK7GBUzaYMp
j50qk/yUPcA4JhacBNf3CvKlh3BmQr0AfZpkgjGEsXIQbS9T/l90z1dWM6+3f0CVUhH1b0ibOKRs
/iMR1qt9OKFTNAdHGs8TKvP04leQ3mAK0scHOk6BA+c/MWlIojncWAhcyLTjFksHpgqEs+/UbAez
JSD7mkTd4XUDA4BE7jhfsDi0DGmDnMaFAkf9xuKKzSzvE4+vumf4QB5Ojylp0CgHfQqYMk8atjVj
S4jvzz+Np77OQE2wGFomIbORHNoeCJggXEFyjc+6CBc57BfiGSQZthfydVnYwEuWOKPmLKjnihu/
4z29QedL1RJ/ytkSpL2W6+CEmze4owdCygKyqJ2MOlDURlb3+X3AbngrVYMWVbENq3HO+BMOYQFv
YS0W/FNWCbCXcVyx5EgWCQjXw94+0rDnoLsL7SshZHWgzGALAl1mcBBYhGwucPCUGRs5AkT/PlbC
Ci76E7YEJIvawZjYtBf9Rcd4cJeWKIVnahhaIjw5QLjCTVHAUVijbQ6cKECdZtX5muzs61r6PQqd
fL3v9eG5uPLWGT+kqkOkDedyjYbMj2OpXlHDg9gyXDPrObQIs/C9gAei3Q1kIcwcQ9IrLZbrJX32
5OYGMba+h9h5XDx1fMM3Ekv1ij8X9ahkKamoC8sXmp8pN00j++X3OEUJM0h6GUxs4Jt23Uho/gKo
NSittMfFXAh5UdhrgueJPeIlmwr7U0I6+ZlxhOz2fk6mSghvEXy9cCDs97A83B9WKlx/QB57ef9b
JD/8xBF6J+0tTSJe39wi7wwZexbnrycA6lqMLL+n/KfUg3zVxdZn6g3BEefoDbWkxWmAh8ywCV/R
DWp4B26QaHSPvXXlR7Q7TfS2tSDsUmypipQFWG4jJSxRWgtgAhiBD55lZA9G2/HULr+8k+alWafH
bcBkn1cFuPuDYPV8tk4B/9H5HJ3y6IVCiWtSW4g6EiTR/Ui+IceNepzTC+B4/N0CTViSzNMk6O1i
A2GVTbs6ReYi4TpyubwyT64MUgu2td57DaTzhnpoJ/Mzb80K26Qz7cZs2LCa2E80faT4B5E/lAJ7
CIaX700dkjrud8INIVSNFOTqQJYw87yPFeD0NGp1mLCcB+T+DARqxVBYtLF6bepBjupsxBp9hzdR
2T1eHWkWhSxND78G7Iba9K/Ta3kZYnM5vChq0bIEd8vp/ao3D8jLUnpcBJIxRDtYS6ZWu8KlxLhh
en969EKbvbyP7XCKyB9afR2S9V4fuHuCITDntHDg62nzrrhGpGSbYdmcE2WD7g1r4KdEy21gzm87
KBybFj6RHzLN5fH0lyXFLnUMWkCOtDfSPysgH/Tjzpd2IKvNss7YXRuONrGXx3sL4aCGRJ62zPFF
4My0xD38Pd1ENR864IeAMoiFR8kEIPd94pYckJnjfDc6NbQLO59CkJZ/W6hAR0UPzdkt9PQPTbQx
/jwqJx0907fkHzlEHXtPbzKwxEeV+W28q1KEqfBZEyUlhjBQIbh5rCj1B+sZR28WgXPBdWPPFcId
u8xsuTbqdLP/KpYM75tlqyfbKRrZymuLXV2s4Pj/7YeYyTSWgev66zyXkZkAgpamNWkieoXH4Mj0
kwxVhnzPovbqwlA90hbl5su6m5jxrDWE8dhXuZpLx97oUBDvdJom9xE7z7csoRG2hzlM0Tji63C3
EHZbVeMaCg/gmgMmw4iXzny6r4z7WIdHTrskwX8CM2cP5fS96LtbxXgKBu7XR+FubsAPt3QGsDNk
ng/1eJ7Vu/QSXovf0KpUk3qe+o/25C0mHyygFOQb+kSbncmlrLTolQKRGG2PQi9XpomLolzBJZf7
wCLGUoO3/xH0YRkWgb1Zw9tSVsOtxHFEiOZRW8bEyVsQdIKbX5mADLKwTIVW9/KI6Ou2PQfyaV6G
smudpyEtkmnoUa5KALKq+DF8x+UAT5m9FRveG41j3GgLVtcCFQlgFAqX3p006801pfOM92zVhBMJ
47xCH41iOHZRjUwO009+Bw1dVW4KiYM6KwLRlZfbN6zWPh3XJpIQ6+LnyWrF4Ysi+v4P45UkS/u6
eRwzHjShxoUbq8Ksx/dz5QGCsB3hCbJP9OCQx5JOdMNfhf/Dhayap1xVOQxKRYOPkAHUGiLZmwHx
9oH2C03m6K5BOMBkcu5VMK0iGxlZxvIY2PL3sphINbF+i8LMbss8YSb9p9E02tUjHwmrw6LlPYIQ
aL/xjeM3INGK6o46T6DzyTb9IFUZ3u8iREpO2CM6NuWgWZWGu9+F7HG7SdrcY5xamkiLOhagKzjO
Z7Gqg9FHuUBo3p+aD1OHKelUS+ZFWkdMycEwNJmYnYQuuf7pd00caZP6bZGH9XxXXbiF2Bga0TW5
qRMxKjPokvCiDKE6fFTBST9LHWHCYDP9QSof1xujRGAtcu5pV3botFVMA1TUpV3g2rMgyyd9nl76
hGGE9vsmxJYLjiyEda/952YsBIMg+RZYnpkLAeHI4CixH0kNH+JkzVLkhq68E0+UvTS3TjDqXt1R
lYbpX6Eh+MpcO3mFAVrAcftp7W1EaH9yOzoKW6vJgTfxG3cIKDgNfzQ7vE/4PmAn+fHdl5ghmjpr
N9tNms1vFOEDaADHxmCpBw7BzzzhdFq2z4ic4s80F6sPwxqbdC8v3ACDe79DpFncOXf8LXZx/YW/
2jSHd/tJPrJLWMROlFpFhRZ6YSb4quutLjkBlmXEhvPpGJ/J3LZTReSDnQ7yZD2Td49katWqdaw9
TrjSR8J64TVR/ugZyOrr3vOfCsqURGNVJLWtOMHZV157G3sm7q5cj99mR2DixTMDdLU+wpifKCQ5
dTEDMDyJC/N+BQ4t6MAm+0npXPOiC0ywXwCjwXMmMfL7xNOHeL1RT1WbF2XFBBogyN8JrKt8D67R
xt8+/EULes9W8NNe8bnrlo2nZzJ5cjwiKl4Ka7dJ9XHvbTe3S4I/EPoSQdMyeLx6vCttk/Uva96h
eTZRcmMQ/YzAjdC7Riwq79Y8EPL3mWBpoSeTANqKCAgKMJ4dSNQyoHxz8vqnoIQrU68Z4ShRVmbK
dCQ9rvh5k1Zi0R6fumeznz6JOIpZ0nK6eaRbGA/YVebSFvmJpf1Ngm29me8Khy2YGn+OQWy9w1Cb
W5GvicDd4RLFn4h1d2SQITT7/rdFqpy3g8iiaxAxpQj95SPagQ4shnSYFUUNP4zxwlQ4UYlXnWSH
lTRBNGelNX1XXAn4JieFggbh1F6Mq8ZvcbxF5Yw/h0ereWRrGvZ0q45XIY5NA0Su0V9X94xcLEpT
p+/nq5Y98ieVAkZ7oNbBAqnAVeYKyffp9ILjOhxs+tQmbu02/zK/bexpLVh6+haPyFabnDRRRZPl
eESwGqX6/T/4yd6EIXG1LkeGi+UgxhSpOj4p/UaIoYH9jNtmedSTGvxihRaes3c0MFSsndD92Lzh
E1Rl4/uPNGkdWQUfEGdfApID0NzSmlpyUwIvqIA31qxAetGB/DsDXjRRfkmXuWaJ1T0wjzIJh7cW
Epd4vmtoKtKyY9E1m+f+RgOWLhVdGQdYmYLiKTAOgmwHP4o3qe7QaLN1Qn6qonGUauA5UzroWjjc
6o8b+bicNrhD8RKJwiV33yaGmcALP/TWoitT+1gdkJhppnttY0W1Ivz/PizO00I/f9V3AaqF5int
9AiXTCJ4kIEAO3Id4woWWnDQUfgZNCuPohbt2KvZx7k119qoy+WVRGerh11d8P0aMl82SXdfMvf9
xPV8ZMOKa6R60z/DgfQpOweDJILQ1t3td84GuHIaI1FPwX4hdoSlyAL4O4Xmgtli6qtaidKAA3xL
YAcI8QPIaZ+eN55CJ5jqpM6KUGb/Ok5TvnqPgCS4E1xhLoNSHbbE9pWYp9PMVzBG1WbtKALHvrhb
QjeZiCQfTMGfgFEpyLRvi3DkaydMg2z4IVbRUFdpv8i3Stq4wRSozcLJhKA4+X2YZgqx4t3CwHES
TK3/A19tQy2eqxKO2kPCZNrFUg99Wx+YB2p/fun0wjM7+TownKbRCcoTRfheubXY0U7U+CQrw2sv
4d8Z7F9O3nD6vy0tFWU0CycIzQNSXGXcccvxoCLNtexkNj1F+0076GRSQb569iuS/TyOfGuMJOqF
JV5jNSwR6yHTuh0whuOY1AdCvEnRadTIGmnjKoV9T4eLSMpbzyWK/TApG1bngCbLRoZ/GapfZtEU
xxgwkLtjUWXPfyDapjcG9aFm0WkxzFE7J7VKLdFIHzqtJZlWe+Rc4q0m0Td0JyHjy4+TY5xoGBQy
gqof3mqW2Qg442GiAB6Bpzqg0Gy/oKCvB+NbwppTZEzgA0TridK1HubvFf2LJVFejT33m7B+GzCh
d3eW2NYsFnYdRR94mCxmgBKblcsTgKk0bLNLZxzNKSp5jmLp2SF35aF3YMt1aJ3EYI3/TTY1JHi6
kQn0C3TQpKOTrYzSEzsJqVbRXFHZgyGqmb4FZR2Iu8iBIEssax5h6s3ZB0WGgUDVa+HiUZyoBTfG
R7Mlvf712JKFkXJPHHcp+vV8gyoJmhy1yrcmjp8xAUGvLqrW4v06W2Tk+gte01QEPWXAteBU1c5m
VHnyRmYc5UCZ2bF3INc+VrqyCpu4WOyU2BFpYdbapWA810NWT3huT0nKzkTJ9TQ/EW4ojW+7iRT3
IgPSxPokHrc1Sy/GigNmooFiflzU/5RUwEo8UMA+cNHQEZxbANi3bVDTz+x82wUZf7Bu52fuTZ3M
4XIa+luS75PK4T0JnH/Dy8ShEqw87iIqodO7l+znN/QcoTrunq+SRHZ4j9NCon05XOMa8CkJ2Ngl
9+/SimEnMxXZgZ1cjujSkTP/B+bkBTlZow42dUEBDP1qQBGogqBQrD2ygKMfty59YFl5G4tigJ/U
1sQCScSi6Bw2Kxn2TI1fBzm/52VGpTkIJ416nb8nAWV5lBGEKH+ktqz6JY9rbvn2as++hGNXbj+Q
ZUivMh1wnOa/TOHrkyK3nn3DWmvUwx8LZmFc+ClyHolSwAD9u1T1VgiQPt+kMX8hPGsV86RUnjaw
mzuuURYSqCFOxVrzZe48MLtemeJeKM00awcwKD3TfefXy0y3eRygJrT0GeuPL1olbFMsqAy6Pjbj
IC9AW2uJuSqD2vqjb3HeTowaVqIiZGGkk7sfCku0BmxmqJx6v8U8Cwqy9aR35jr20+ZBv5lz8f2U
gAZzOClJXzVOvvbVtCSzhtcL5BR/HF5cgP0q4QykCiNxIBeG3uHqbWgQXQ5LwpXCVqKBbVT3dfUC
3C78lUHXRzyBPAZO/kaxAudpcTE5tiqmxrUwIDojC7ctUzNoGpBE1rauWxbuuFvcHPyQvGblKfwV
3ktidDq2QQScMop946ubVprvUiXzAMuJ7H+kkc6xsJs+i7xbpHD4A+tGEHL4Wr4XO99nohmneIzB
6kpPc316aSbCV+u5z1OTKwbVfrIdAwOUdS3iX/AvyqkgoXKqvl4QswIyVbXFZUbaJ2hnH8G/dUDt
viGNWNEV/vCd/4IjLhcRz9FyaMzZ2k+L2OnKrND4eFQyoNrAOFgLMu2hDzpo9rFa5+UG5reAmbsq
9V04JTOx3NerymX/57OpHdcHs4AmV16QCIYXoddXahp7mGVGOiytrMvWvQj1eX3AnH2/pJ98aAyr
o+oE29AduAvw1HAWDUHftZFe5mOSkI9o57Td3VaWp1qzlCEVhBlHVgeXnSSMTOC2SsKn3Vp87LcZ
xi9jtW339kA5MothRtLGc//llRQ5AUsh+LxWvceJsLk8EX5oInQjX+9yHxTOaJH8aNxsp+5vmvp3
7ELt0ltYBQkhvx8vGWp6tUlCr3a+IjY6RknpPNxYQL9vJizcA3k/hz/gFr8wJReEm0B2oysyUNim
erbB5f5vNhXHaJupXjF8oIFpZ+zcXyTUUwpYlnPL06bLqjVCiK/79H+ikBdxXT/0mqHxAFYLFwi/
4TId8sFA/tBITjGS/ecgQVNrRVwc7ooePCji+uMSBydgHAUO1YBQtVSQmiSpxY+RIM+2xQl/Ps51
tMg3Bmg4aalTAM698NLYH+ciHJcX+RcN8EuuREjxAPDR/+gr882QNJQxHg8xHQ+2Dy9SX6C3YqCH
uLyn8cl0wkmniE+j+eCTGJ/2W1npog0gHxHg/Ggb2qzuudFXJuKVuQLm7Ks+iZfUNr1v8BwoVGF+
rwiaYu9BG1tSkLXkbP6MhBy3laRObbOv4MdfQXus/Ke+nFOHBWnGmD557P31WSt0AaCxeR3hdL5C
XhuVnbH6bzExkQ+c2EWgiT+Ozaz+ts6T2T6EEorEclGzWAtJVhmjCV3vHBxDqrwoMmS+cTaUxRXN
cSJf3kcuQgurVDWpENoydwT2CY7JquZv9M3dQnFPmVTwSq7pt6NpFbLTLMkfTaUy0gxZlpCU9E8i
0ocAfCKz1vlur9HJu5NwRudMBkXVsdxwXkxz15fqGj/uqFPSnqfL4v8gfkgklYGL7HXT0i7VCD1Z
itIC0aXFl7SrLSKjUcoKjV66reVbx6zNTVI4JunmINJ3AF//TBL3nl+uD4K/kWbFGQ6rRPVC+rKR
IkG/kBoOw2Fbnt9Ex96Ipff/BAKXiX2h8tG71g4WihiS74gIx4whmyv0azNjPCniKhCNkj0Z2LC3
COFAkGOmXW9AoiVNI78je5dYi3DoRmBRIqcSarEPusk6zM4ZS+PPMl2WjLRpgm33V0NTbiTL5+GC
gzAlZufb5hmegjY6ERg9MVB4i0lts/vcDDKyw0qVXNVyA6Iok8iMb6RHfSrGDo/6Cwz+oRjn79eL
GhdSmvHvrPaG0Kv7fhXM/S1KySpHj5SrmqtRht2ydsPIpzPnDQ3a/xGsm9PXcRn+YC3jd6z+OcPS
ScPCwC0bqRYbdGS4PExkju9vLmqf+aGWauQE2fnmse5qzdZth7idcsPslVB5A0gnM2OkF6hjaLkI
AGAgm62blW+AqE3WtGjK0p85zn1A4s54yeyUVzAwFj8IyHSOuocokicTejTByBi+MtMM0zE8SxWK
5Lbc9T2FsPzuJMKJasKnJrofdr3PdCVBBcMnUZW4pKdLjf17lyqBcFeyKXdYqeNjaUiu3o6cjn2A
bTd0GdfHLzSm+BzUlxOBGACrs/6tqWAcs7gZji8paQeQSw8voDtZTbF/xrzFYekHRtQNrTZbWUnc
+SvaGKrM8kM6MY6cyLQh2G7QhRe5yvY5AucUEY7RCusDaM0rX2hxI2ZtSxl+Qy0PnyPZ22cD86Ve
yLbaeHIESZ2aH4U2e6uLkdY76YZPZEIxvjhrKEe6vKvmRYp5p6a0/5OEYLhdXqjJudtd1lQXqUWt
fhLI2hAEzWXzMykdbfhZ/++7ZWNvSnA2j8frfado+Rb00Aqcs8dZ73HLMghDvWszMbMCz39U09sy
QHlc2tg1YsYWIT3jlfBbPyyobeHxvnuT/QSR8R+flozbMcnw7UpWMz/6ViYpmsKKrEUmiLlSD9nc
/rsuMh03CNvuc3BGbOOrctKtPZ25jtvDWOBWmkPX66+608uTqWr5aSuEmrkCq5Vex+IeXSZ8H9pi
0w1rNmbikZBSM5Av7N+qmxcg3cfPS29dvRl2CnAAY4M1ho19KragwiWm98XgUXIhb3vMp4CDtkkW
BXTfk8o/j4sPlT0AuRRlIYxsv9ns6sIX1lczdYW8z1+LPbuTzhCTgTzP2xuSom2XITbbgfCFrtnL
u6oNsoMfO6FV8K7gb0BFZEfWk0MBGHshuV9IccqjeRfNb/zyORuYG5jEyzF1dIENOwUPdUZ+0ZZl
NMhzGOOTc5M5eLeNkBiXH+VC//h/Fcl7VnQfslHjS1wb7GKlKtmOiDVzTURsh7vy8zD1u1VKlkRM
mrPS8Pq5xJzNx0LMW5zOrLXzv0OLJ0Ndch2KWm+z+IL+gXDeu0B38CQlCesBocZBrETq2+ClBoYv
MH0Mv2R02I4+cuiHsRRSS1DnC6ev6IkUE5dhR4FMW7WpQKmRA/RHTrEHxOWnXcmGWOP6LX0qp7Fr
B74KQOe9UVuMXBYdel1M/YKMJrgT+m9asfVWf9YIgYC/dZLzYZXukKIEwCY0tI0WgoD1bW96Es8T
TFT74h2QpzRskoNu3Du4sb3/dC663sj8ohwNQv9zbQhbiTmXqj9vJDFb9ygThbdIcHwZ8VhXNvFC
B/GnBBELjfkmCEvxqmjVvaQKWJe9+XJf07YlZzYxV5YuB/8t4COq9GEFJuZQapTD+5K3VNb0PHV5
wTW00rgilqaG83DGj3fnwFyhF1uPDuQQB2k3l3OpXB+OqSImYHWkYe8Z9kPSkMI+uNJxq/44Fozu
JW1Nk+l1+olXaN0mnBg/NqhRmsBPiqTSehNskWK0eNnflDvh1IwGp9Uv0IPUTK5d/kFY+KJO+EAZ
cWRdQT3Ut+B1US10uRC2QVIbb3fnkqe4qeetWiifTU312x3Fctas4gc2b4n+mOJTepGFN6ZUl910
1lOUr9PDQbTCppP6B5dVYiKAON82XrzDGgKKRiy71r7fwVyfWQS4fK4cIy49T35VmtmBYvMYGcGd
Rg9GKFnN8/zZS66cjniORKLGgKTq5XplS0CeEg9jEzboJLCgUmzMq5Kn5g+BosUDyB3eECdwmTsX
1XJVcLzmUykQE7f+OOtVpatnUL9HYRXsQVBvNxSCUc80kC48qCEFyqvSF//dFIYlxqNtSRl5Km3D
qTbbThuVbKqj34AEHS43d3nwpoUrLQIyL9aBAWbQnCT3ZwnxjBwTEsaUySDGy93pyG/nwo3lV7pJ
vfiqXhPN6Ed72DbuWunPbCMO1V3XdwxeHUmxl+NdwZ4Ucipp09dQ4NYY8spNowuXMJz90ibIsAqA
TEx0PhBMDMW3mEBpGjTZyKv/NqziCE1iUfc+jUFpF6s+5kVV3EP6xaama46V4ZNHfX/dXtOO3zAb
LpsRhmP1pk+kEAL/2Njd+Tr8rVhkvaDPbcJS03uHHfjQJAZYSOIr/iPeZ61CM4nL4/aELCNjc/SI
/iINz6vsJ/xE5OmSmiIQFLWhmdTvpjNn/MOZnfa8qHZQOkRZHxjTEJkDLR0+leMY3VRCFRG2pH5E
5EBd0anXyZY+R2Ft2HBHNRto7ZeNuV+motoRlc9YGi5wW36+8wCp2JT3S4WHtoDSOs7cPvetvInB
FJNswlcv+fyTtoG08+1wspU7t08Oda2AFhUz784DnUYbchUFtFpZixHSElctd7gHJVS0g+qudzl3
f5wY/45/fasgZOm/o2QgF/RLqacruVgEiK6+VsQanEnjp0224ozEava0cUT39e18qDlmJAazFryu
RPYn6xTgUKOozhZpxI51PXUvvcYFxGS3zAMOXT2FO0MFDPrNRjYWU6J1iLUfU0VWFZZU5SIncdSb
xESZC0y2JJ6Mq10pmItyj//heNXaITANAyQUNe6ZYA76O/z2q3DyvPdsyg+vJNBwP4yYoFM7mXdK
Dth/4UoFuuIxAMGo9QK7cbMACSGR7B19cylb2vh/IQV5suItQQYz6JdMtMbjEyw6FvIOZWs2bJDU
jEk9G2w+qnyL6ji4987dxT6mRQcxftvjjUs9HhcV3noA3uTzQ1nWe5uNM4YJtA3Mcfn5Wo8MjyQh
FEZXvwxzQ23/YnNITZsVZ7sKb+7aFcWvSHOigNoQiA+gz/EPEaQ67z10mYIq+64darHOg9DHnm/C
c32hm0ZODis0Zue5Q6m8Gg3TnfnI6M9C2w4lg/MXaIjkpfPj5faPdZ/tWaGIQw7aMSeEymxT90Cf
xmcimKfEpu9h+YcVdu/pSxIA79z9vetlHe9Sgjy6OpmCyIwsYQ3ck+rV+WPL4P+d5V1nGjRMkUvL
fsJZ20w4Wfat4jdQVx2hbnw62PdPjGW1umd7m8rA0RUGDZr/wRn57c788vpnSYhZr9s8YNPiOXeu
zgoABjBOUa1/nmp5he+4D6pC2GlnzDehz0o1tT+jaXoEqY9k47IS6bqSf3EAfAegxVP1kdAtQc6U
U8DM29RpYxocUvOwncGWIbE0v2At4/dyKsl+b2UalHWNZE24Pgi22IGmf+kQnpJhLTKqXK9D+GyR
ctpbJs7y41fcmWA4kcWEcN50AuaNOqyuFVZMrLy9cblmYhtgNS+g94/DcSfhNUskt3e0V8g1mMrZ
cZjRGMIPzW1ZoUKTeaWIp3AbhCiyJ/RI5npqRHw+NOAKEwuWZa5Ffo009tAmu2JSxMJQFlUBxZXi
IuKkXVS8Azslgy0TQ6OK5h36hOjBnVZUH0S7Xqc6Wn5kzlk29rY+tILkYC8zsmlSiZhlgE5BnQ62
BVPPmqAb13yy4ksB745+LrWX1vw/L3EvjtMUeb4dMpt/4HBOOnkORUya6opNNaKzQmql+H6VT86Q
3EvZcUGGo33aHqKeEvUbiHxUVh/a0Uz3kEDUrRYpupYgCkaGIgGa2FVnEwKh6vGS2VIP8CrAXWZl
IGZOwc8+DxiP/LSLZi0CYI71AQBROm1XshU+aff5IOydZrESwNkmgPk6SMGSXqaoafuBEd9j6yUO
hRTJ+uReuOdQJFDzTEd5GcNAAiqyL8FB1kWa5tcqIN3MVmbfhHZr2ipzIAaorfeZpu24PakiZaPa
r/YUm/kJ3S0LKEsmaMNciZyBMwx3LV7Qtlb4qrmlTKpD1956jVW81TKEc+VdTlbzBKlc0yjbKG1v
sBoAWzMuyqfOKFSOPRPPZ7yS2/9gfxQEvD1ui8pIb4WWn6XwiyLvM7cgvsSjWJwz+KqsfrxrElS2
mpp2GOqCwHQgz5XMbp0bKMJeXiUDJG7vA/HxuMcmzo5Vel+PqYSnCg3OiuwwadAaxj33cYgLTOUR
x3auslE0d1VegarSlj3Fu5UoBS9JmMwkKtJ6kubZjcSbFi+0RBOHETUZZ1ysgBm/Wv41lVD2VkWu
M+ozupsQxOBa151zBi2P+a9nYwjeaeYqyYwiGwx1TGGIlGfd2Q5vHy2QGMW0zNuRW0QRn4pmw6am
I0DXaH4JJEt4QWkcdLvDSqjM3GUGuw1xQoWvNIJZntzUirmpjYl85egT3a3r30Yl0uP6TOg5g+wm
v8F/+ffY/wMworf3Hnw+cN/VShIfqN/WwWmUeI1A8g7WXoE80oj6TR2aA0nQWXPMS/sA4U/YC0fu
0mJPluQPJXu/RzhzfHQ71eIgSPOot+kO7u4913r9nKxHpjiZwrZRb7F4JkJDe/25g8sjuQXVMC8r
MepF1PNsIKGSOLUkZvBQ469mAC0IOzG9fC4baxNH4nt/eFA8mnx4jj4N7pYxmiXz65cTjKVzGX3i
8KWaHVBczCsD5wXGzC4rLRAZKsHjCGk0Lk8K9WroZz44k1hAYaXcSWyuI5IIX+j5UOGKtEKPyog5
FIyezINbeoY15DmGp2HN3b5KoJRPensAJO0qFBpcRLlrDA79AQQ94A4w8akhe+AjkAIGAwLh3qxU
E8RnQ9qobo89u04C1CORk7iStn23AmJaKn+g+YFAlSerKF8j5kKuXJf08iTrxkle3QmZ3i/uUN/B
W+JJWyQBudR6VRrAvJkBrdOdUhdd7Bj3SEcOKyWu9RLaxJlMY498uU5GGJfS3Es+SZnyiqcG1m/0
67mNPu00jP5lOBPciaefddiUIcaT1FUP7sajo+i2u1x0JCgboB/QBjeY8yJpzHb8O8jHBo1ThNV6
hjqm8WDTNsptvB6yGFCO45PHqmuQ3hyJjY1kjPmg7lZI330hypEGmbImITohdIUyxwfOmP+OBZRa
UYYEkknEkbchUQgsTUzS0EKFKtGKfQZSVOblX/9wqg2TziofPCKTU6nKVcPL0HRlcFb4hEe7kiqS
bfg8gFo7c0sK+neluOCA9v8RuaFKgEI7WgumQOJo8Ps5Q7Z7yxoibjCKMPTWTRWmtWhuboHTLjLR
S7HArj7jWlwWbPe4d+qBLqLowFX5gsVVYKCjIRX+/Q5AEeiWIQBl46Y/cZ8dNjrQ0p7Em3Wyc/Qw
Er0KfaM/vVEjPf9MGQJ1GftUAmsW4JOb3cBHVC+QkF2agrRxSDj6SocQaSNbLjyekor/x0sgI813
h/HWMPjpMRh+ha/RsosYuug8bGoZ4qUUiA0e0bFjWQkCOXNYqUpK200oI6S8ZjXN8SBhdluUn3fk
l3K4Nb27iV5UAF3hL7el+1ir0Psm2sA06Z2Jw0DMy8ybgJO7PEuA/OGatxdF0gTKNofPdI/WlpEN
FkfbC+I8Z15tIpPHsPTRfot09LXza/fiqpK8NKI9gvAzQ/FkysMbBsBUoSKDrN8WXm+/HmSDPp4V
iXlQlaHCEu7IPb0Tc2VdvLBBNR1/v8C3FzTM7dfOXgu7KtpyihwvUDiEIrs94CvrzhJEjuwlslwa
MnTsD6NSLAxJLsDqWoO3QHwGpfXA5o4/s+Ol3B4RgtDOCx4fz4iZlltX8ML/6OLQlKHwX1VYE2x0
G8Ky035ngqajYI4+TBLXjS0z92vcFnb62osbSz7aivbzqxBVg2r0ZI+UBeipyosOnBCWY0ZTcBK8
5Gkfo8MkeX1EE0+x1UkEGQGsz8TifqQoi4GzANZSaudHywfIofHUQznvNsWqnP79o0mpxm+vSik6
tmPfFRr530h0Yx8GZ2rmDV9Ir4GFZQbeObrDn+RJ93wFzkXETNN6Kkg6mmMatbjlIHyFe0aT4s/U
nNxaJykbpw0mRd4oJuEMIHxsJF5Dv5XVEiA8KIlV4cTCMYnZPRuemVlblI9HWQk4Y3vd8k4v8y/1
QXjlTEMs18+aBm66DScroejSx9dEcrc48GGBrKGRlEujsnwbXDZNOlSduQ1uddoObH4Q94d2Amdz
M6FjAIp0c0LL8wcgKjpMHoYGTLFhazkTxNcQX5S5yGHVcU/7ZSkTs02cNBg6x6IyLUXkQUmHE1xn
/zf/VfDFS1KV5yEoratXoudfHOwtwQdpclwhc6Oe2ept2HDF2tBjQm2Et9uyM3bGji+yioDhYK2t
ShJ/AzgI02KPmb6PFKm/O7UO90tybF4u0jRWe0hhWj7QeK7E8z3pbsJyuAMaEcw/8HBj4hF+lTRf
SioVp1vxR0GfaiBhpwEr/r4dWT+CB66bLzj7bgdgB2sRc1O5vq7ZDbgacb+EAUIFhoDGarT0p+HZ
daaXbkWs1MdQnkIgXdDZajXO48T7tFB6WbXHUldY9gzk2BzCQAv4ZFSaV89amojOGWPMhhls31zp
efbaKqrn40k+eDZGQ/GWrqI3WU6yRatdif2lRlNZ0P0JS3djnETZ16n4PJOZ6lg1+LMgFrSSJU4g
foEinULYy174qbAaB+9LVsx9FZw1NAkt8+vhYJkEKrDZA2+Ep364zMFr8yHAd6iTbi7NPD/xvxMj
7V1xpED2aHMXTA/sDXRfQIcBY2kWVfG2Ve0FCqU5I+PHUptMB1BHSdoHcB7GpwaZ1vFTRPthx6Pc
JQ6OqHzSChGPZdMAspYtZCw+Js2dE0JeIQ/zybep6c53nJavv1Q12qUIer0iLl215XL88BoXRF/H
+UOf5rSLFkEWgLVFr7efuydslDLafR7lurJGnfoPHnhHc/q0Mq2UAKTZpmmpfaW0AtZg6GWxZFfF
R9ZzciN++ufQI8Yr9t8JjmgItmYYD5eRceTv9d5NXAYgt2hFOb/wx1FE/iXdGC5ZyJ9/Dp5aM/ZK
6RSUF0TN0x6DgEMHYIFe1w/4UeC5ekCpPNJB/cTP5zEXf6ClOZmU95j0CVBzxcwWCn9+jFFQ1+xG
FI9c1ZKV+M+NaHFT13bwePEiYctBbT4EuS6/LawjRv2oWnPlg2Y30No9giBrNEDxs6xMDsooE6dL
cpEf6aJqDn6R+d3WEu3x4PGJgRmfcPt+2MHTXyiqH8g+7pOxiLbD6gkjWqxk2HalrPMCEtmGu5oy
VL4yJyTUo7ShgKr7k8d2VqbWeXSiNdtLk0t8MsC0DXHCyCVOG5bb0eceMjCgaolldNW8Thr3h7Fx
cHWaGMX97K24GaQMbKRKsve3E0Yp7xdn8TgKf9rbcrP6BYZlCuw7zJixo3EkFhgRr4oIgn0zpMCF
FklAFNO0p1zrSWrkz0fx0pIYjepoMlsWOm07xAwUQRF+Uffe8VNLakjzVoMCrzd4AJW221oOz1xO
Io4xTNQ5x59d2gVKRsA2noMXyG1K5/h7Cdo+Wn0wwlvs75watygxc2Z9UXtJP9ti9XU1wZ7OnoJD
Wz7mGNZq5dSyAdTXExZekGWy89RHT8NgoEyASwK1ZRTlW8ADBgZGOMvDQX7HiPS/D8C4ZYTspWLw
wrGTc5URlt7GtpZkNHCTVNAtaPUp0GO/hUcn0CJHeYl+LGSbivZgcfeW/idxhis2alBnoEvm6mjV
GLXecDWV4ApGpVBObCvv9D/LeQvpAsVQ0K9f69m0rA1mUk2Og9AS+MIJ2pfyH5Oe/n9ylsD+6Jj4
iTXYnVpFwu0cXIZxgWK4wkmwb4exyMbHWpn/08zx7pI86f9OV1aZY5Bqhgv3RsxW9ArcPLvr5Afr
QkFsJLLf/TSukSIdaEEmF0KbHDptno7WUr0IvCxl+qa1hpY/LyFpDj36jrokJja/HijV8ChNjSLj
odZ/si1Px6rZF3p8KR26poyOtrIvm3JrHdjAX28N9htzw5QMOCgv+c/v5s3IbNH+hP4AcKWLc5q7
nP9QKOHHK06Dquj0+cCwrEaIr3tXEDz6OWXcZzzZNGjXIxKYOoXxL0BsUaUttRXG4Ek3w9Tc/b8l
MlHEljuwltzViCQDbsP1dH7ss5wbG9NM7MU/AWSZEcWCaW7PC64LNwYfRQMx1KHrWXdgEn5HDTdg
hdbGtDvvAMHoEF1LFrj0+ySI8hg/dsZiQ891cf2WwlEN/zQys2nTscAZAoguiWvH7y4cxz936vbx
VkqTcXveg4UTVypxZXY88OiLrZC7Zf+kYhShcPKyrcbdmTQFQXgHQMBpBjPfbN03z5sro0MmH3f1
Xmo9irSaQJc/VQ3/UU7UjWZfKKjF2HAozrcH54Op3OB0EC8VjPuP4xyL+uUTalEND9ldWyoAEeZq
I8V+e0bcd/KoWDwNWlPRBq58gpoRQ8SFw926zlCXf776z8l6uTkufTXU6xGYUqzfi2VQFFXm86p+
CVvciG7PGFVtuPOeBhmLuwYiBmNbTD5zkjtnkc/DBhB3GisgknPGBdf+3H40UOekWbbpclO7qZ6g
ScWwz3VRMXpAdjOkAMB9zCocuPCG30iosfHTeAZGQU7l5HNpQBtQS556fc2HIflUtK3uxtaUPaww
mGO8+b/PwIT5l7tSsBWdXuOC9c4G2kL6lMB8zIuCbReTYSRwIO5CU3CrB1gUCzO2inkToBD+Q7cd
Zx2zS0NAF4+cq3PcIw2PsClO/d+MOPqCPRMK/PbC/spZTimIZ+H4Ny+AbEY9K3TFRBHZzSov+eYM
/j+qLbhOx5Oahv1LYw7yNFrVDTH/5dzvW99sd4yB9LYyeW6UqSoO/P0tTUS2VwakVE6pER8pwtIC
1KbUg//uRYPk8ZcIQ0BWMUiO6C819hDabBQCs+u/oQCCUK4zaf/DkBR0AKfXT4rUibvITcflTItC
UxfY8yd/FjMA2Wq5lYpMVP2RWOhLGxZdIlYeApis5RN0VPoux2kopPTHPDCYekxgNTypw2BRloq2
1opl2r0kOR1ZNN25BiUDDeiiOfU84+X7IyQAUm8tfFUTBdPzPMK5Fl7nbeAAEJDOLPfbygP8Y2zh
V7ZGpXXx83DDbOgsr962a2lCuQu2KSNFYShNltOU0vSjMxv8KvNpsHtfheIuHXjNAWDKDqOibmmn
LuIKOtgMH8mAGWVbJiVBLbV38qCy0tV8C0cqoDabY3xi0O0pMvs2Rd/KRj9IOzsZkAOyyYKCWfye
6NM95vbgDP+m3YOJfLIuK7Ty5j9B5nMD/QF/8wfNX1fFxsU3Ayk9YXKrdwJvhxWe75ydsc7ZAg/H
Q1Tl35ZVZ23FN3xffon7LarPDqmdVs15hBET8eM8TH4ReVt6MmPL4hYIM3xlMKuq1Hwt1eqaUfol
s57KDVXtVABRelvDhtUmyY0hhAdN7wtc1geq2lgBwWRiC6okaDOWiV6JxSixiYQnAgfXlM0Pg1SM
06NwYGbZx0ymXMrwjG1JOXIQELwdEfgoLf5XXI6RbL3Cjvi8HMUb9u6vL7IFy+O/KQ3grwl/wcRq
wAXk2+51YJzi5Vd1zjbSF1af2oETcqKWL1WjxSuT2+Ket0BfeVgK6XMTf5qF/Myi0ftiKP01Q4zf
sBmmNilXKbgB88C7lrlkUlkROq1wxiK6/kqFIdl1JdDmbMBm5WWa42hGk2ihRE60gUxPz+UsXJwS
RTcxLLG57kM2jj+M7+whImicMxlXlunL0JdZDdcs4R5b+b7LB1nhoLFklLwgILOHk9RQt3bOvzip
uGfeXJgXzRvSJxLCOTTxoarDU2yqwdadooJWFBlY6WLeQlLvWVSbdQySLv1BVn6DxY1Ckg5XI07r
io9Kt1YLfWPt0fyOZy2ew7OSl5MtoVwcbGP4gco7um0/wRwh5k4wyfjR/xijmJSgASAu5Sbh8k93
moBiInArUJczARghmTLxuYqqJatp1CRO8SXVUhTwUSy++utsoDEQC1alhM09q/0sH0OSU/0xSLQP
UzADyKgTdpoUYjzzsmvMmpQU2MXJdN5YDRk7UB/JXUpxaBerMrKgpKTEW8ggebt8kOCG44J49Of6
0NcUzF9Pcu68ovUlAitRQQOyF5QxdtQIA0Y+4Hc87n6v5LYhSEkKGiHHQGHF7WGG3bBs/lXLnv3m
9SLrFQk/FBuaIvWNmbAcqb/sJbhMF+I9zy/3zPu2Bid226fyc0p6W+JTGNrq+FWIev3lMX+Eq6wP
LXPztFZ4SlJJYBUVgxnKslsbmBqWgbsdURK/gjHCfDTtGhFFtcrzippcLuL4tZrEegw/3Ekv9vKT
N2oKu9wR2WsSfxUdGXOeFP4et81N0nDMfU7RaHRfU6mg/L3NbVKPXO90538etUIWXhz73y61uKXY
KGhzxiexJmqTAArRbmq1AgrsuUeolyqzwWJaNa/BGFWNfycqwMDMM27eY3Q6soulA+HHAa0L1AKn
Sv16V3d6qFTD4PVhvNcBKoYL6DzDHeidXsEfOqwdz3fA+x5C3EdCtBBckEYNIqZpSS+M1IQUj6Rb
2ZdJJSirkWkJ0VUw1qJ2lQAldW+nbt7FaFXM4RiQDIMDXXKPq+qEPduATjmcjLtqKgjuwS4A6PUf
kBKCNYm1OJ4umDLbv8wgtPrl4Vb3DdabNs89vVZMKpf3KafzvOqa6Vf6xDO8i3ez5FIBNHn5ZfUj
rRlDhyQjyxaIOQ1eUqFtiIVVVGaniHByE2HAFx/5cLwFwIkOGzqH/uEzougfHCKPnybx09ijH0sQ
2I+xhKYkJKHMfVVaAr03HUYVCzZziy+agTtj9RqJQZmv0tW821dDtRLtsllf/WZMsJB3VQBOj5Xt
OzMyHjv0YunWpkiGLHmEa5S0SxYVtrvuoKZaCWuWXGWVKyzuvAuVLjTYps/GAroe9WR/0iAWo7MK
w6zazckAAQQBfW8aoZcfIF32r9Su8d0d8BP123Z1JCQ4ByzIkTi2Ija8qs38f0evkxshKcUsicEG
RRWa9qwHh5YckBGJOgR6QjS2/pYYOFmZRgoWqwty6NCvCzMeWfmEUiwHnYRgJQe/M0VVMw4SayaU
7yRl29nUTLSRcZIUb8dWGji3drAJ8Tt5i8WiXbIod/YjexYjhkzH4PsixKRsc4zq9DYgMEvNEbNi
gf47VcVo7ezJ4twwACAsvPOJZYRF00r55aARV3CbkiciJDTWecFZVNLrgwGpzLHmLI4OaiOQk1rH
aEMgUYydMVleqRxS1XdkuAoM16ivmjJWZW5EAeqmU3OHeNsUvQoH5sJYZJrqBSL21WJNMgQ1ALj4
mEEn95kPScB0EIPj8dXSYNRUJMS2TRwUBunbnRHTsPuB+Is5qZ8d1iB9b1JeyllQ9dvnOpCU8W6K
ES0YLjtD9RZ4ki5OrnSurHWfwnWv/EErXh914j9/d+MHg21SzSc94obkC2U46SCQPL4lsu9ye5fY
cGW6+caMiKyy9jN5BwGi6fiUplf0SgWNLhaLfwyNiepJ+jAactCjcX3B3QAMtY18Y+D352HZ8P8I
EimkibqgYgvA/Vhl0MU//p/pRw6sMZebjljzX1qSnNf8QqQN2S5FZSQGEOCMXL7C8GL1lP/WGZ/+
XbvTL4QdbCojIOjs5ukrjfXAc+QG95M9hcD7mSUVrqzqtiUlpvPp/7KFrURcBBSYWgjJdIn6X9ML
Wm2h+rV40fMW8dkTl01WdmpRck5JhKJrpW+guwad6mCPWVvDHtT6WIDAv+wJ8rOhhys3gy4qeAYV
I82wIK/lom5sEo6YGeopxWymFNL3kf6v67k9HpDrAAj8R/l90lrctTHSnDOieMNHfpZM8JXTeX7T
rLhk0DNAzr6DsZKvtfmGgB0WN+iw8gckDBypopcsenklM5IIExNjFGKRN0v6Wq2CdlHPdS1n66IZ
598umi2to7NkSpmXeCpDdkwJ/Wd1bjsHj6yyn5eWqExVCc7wXHq6tq6siWlPb693njX/m2b/pmep
oGH1B37Ytz0ndGNJPd8UtZtvEm8rCc50H7lYFH8hAvvSqAM7Oskmp6+Loq8ZYpuJfBAvQpPBS73V
4iThWEHSFsP0780K7ecbp2fI7taWgIRs35wdhYVBisbcX+Bpuj/bzBqINucVPzxZ8imMpA4DImxP
V4tgs0jFRhFCOMLB3mAJzx1+kiQPMuMQY5ovNmh7tRU3YR4rTV5mZbw8andI38PHyAxJUTfCAiVk
ufLCt/KeS0LLS7qrD1wdH8uZl9ZnslX9wwu3BFzs9P8bmoss/LYNPXHtG9uanPKvTGCvm6JzwFaw
rKAvUxPhLjUY1ZA3WSfxOI10vt2IH6HuAlqSeBrwgZL311KWDoI06Rk75Yckf5KYJmvS8uEJIjSt
Zs496lq80yNgroHEvoO1jth3rfxv7BII4GUpnL8LlQMJ6Qq2olftFJXkayRlGgXoDsLRbXkt0Uos
Jd8SYWgSKdvrVGx/hvY5vJjjlKai/x0Z2XNcrcJq4oy8DUODPWVguDj/wsZ99z69c7BaJHjKp51u
GugCkplqQrw1s/nhIusbIIxAbVtPgtKjAusU/4whCuLbU8QULQml957sG+uDuGl7pJLWI+o8+Hm7
NIe1yo7uSho2IGUSfZCelPPfYVtihjD5P9Otg67cMc4HDOrwvMpbpOJjfXuVoj9KQf5GbXEdDDD/
/7f8YiZ30QZy9Gv4ivNXIzI/7fVGn4njg1TFzTkRXnPJang2yCYEHksss8rLYgokSACgukYu9UAR
WIfsw11554LLaUy7pg/2d/J4W4TiGM82/8YC73vpmZpLd9z70BOm5jIzPArnzzdSwwP2zjUokyTt
/GX7WbH9E1TbfQOr9aSG4YlLt5ANNWkXgV/gbzbfYILmKyfwexnm2AKhdXz+77shJ8u1BoSSvKkI
l9JxAxNAQUvpbVUIvvNaQaLmqzbv9yZjShqzH3ZeVfaWes/k4nVoKUAWLFksONRWq7XACpDC75Xh
EZsvFxQAzt8GFXpFhhFc5yyQhfgyUkmd+FOwXmUPqEm55mRrsYue08jr+gddjJUolPbxc0O7V5Wo
tM0ZAiPqRzBBIHH68z2FABZ8Ias6gVbDePBFQQ4ORQHsRJASuISGWSzCsbeXXaqjhIegBOmFL5i5
L18yAm6mMDFdKteYG4GL8LcQLSO+qbpCppfQNd3FNFDHD6yM0HEXp8e99dDZpt9vzmRMtmUScKiL
pobDj8shtM/MBDCmxHgVI1ltdcVTRItUw9rkMBS2QQQ9AREAVbBaDgTfHno4yNjVz8MHvrEHH8N0
WOXT5DM6oAKBsGK784+wW3HDTvUdM8vHfPsQmof9Q2oLlWdfRKAIssDJegwOMG6Ix21phub305D2
amaEbVQ6MH7SirpMNtTB8XURsQG5DwJ9B4+mokhCE9bk434CzIOSIOz2d1MoPxszyXEeC0HhqP0F
+nXUHalhIYsRYxA1UyrtGklS2GoBiSzHTS+KICFxlXZtsp7YOKUCkOe5AKASZWh8ei9wEg/ddxzw
acPp+a4UXajoUAw/Vvu5UBDZYRGhBTfe2GRWPkWK3C/mZBFMk2FUsmem1BKLqXWj66opBEe8q7q+
yPf0lVWu3owXRV3oYN/eMsmqXjRRJBzl73r3UYCSAIzGbm0rTefsJlxLbRhLZevkqyKkwKavEwwR
0wHs+jrHQ9XyOn1wC3DXGdQbiDWrzAqMl4gAd7GzftVGf4h1GwKFN+AhQkJXXxdqPfbBU/+AmK+S
IXwr+VIf4mQQO6Te/QU1EaTG11QcGk0+qDT4Aag6euA0i94bX9sETkEbTfgbCLL3fHnN7uPb4oYc
moZKxt0IntB/hdZXHeJsJoQ6MJZ6AvS6orcXOg5ql9rqA4UUHX5rSruzeW7p6BVkDeg85yyKWa1O
cUneNAMd8YBVo1wAmzr/wkIymxMyRWJDTMkbdEvUb3dPj1Y3DYYsdy0rB1sA44O3wQyYsG6PGAlk
y0zKt3tdDIy/v8AgAVw0RWkYG0qdjuFuEnnqCAhDdmS/cyWw8wrbCXWq5WHnfDH7tj6ddo7072Ww
3MaMUFb0npV142n1yt7qRxluJ0s9R/0uMv0v06/L+U5YQ2mvBy7KQ7WOFtfE+eWdYDu77oPm7Ve0
P+rii95pOCA61Cga0ESRyUImRuga1h6Z83UnhmsLzezDDhTMnu0MM0XKlYuOJONGVmBuT1ZxW+El
tP+IafiBYGzx2sHw0aj7UcWaMWDybd5WIbtIqcxaceX/YsEAq3DIR+P+XFhItm/XM1IxWlP2ONf5
uQjy/QP+SNLHTCtlN2mMbnNqqKDAlUNcZbFuMK71973pzRu6lJtn4ymIKk+YUjsZUNI3ZzLH+4r4
4VQAMQJzN+8gRpDHOgJvqSWSrlJkHAsAoEbfkjESbSYDTq5qiJeLnp30APvftctc5MXl91TglW2B
75IRgAl+fgAKVAFBZMcuRKB3/zsIBGlzPpGGUX/oPSuRX0V0NrT9UNU65vBvbn/N7m2YDgcgHkyq
JBGdS0pdtaaUAb/l8M0ohPQMiPvKLBq+ZBO3W6XU9BBbhFH+pI9V/Sy13aKQ2MYFZLMKbvWw+P2m
g9Zvta9nmOLENkdE4KGJT+vBE/9SJKHA068FffOPb6ddHYr1OBtDluO3+64egMRoB5+h7bn+kc2f
JCqfy2uv0AS2Z3/cawNZc+HGUinY9v0xPb96+gKEpLfxlR0adyirK6qj0f5tyt1QwiTzJPEP1wLp
FjvWxn2ppIBimfWrEuMAnTYNoQVN0RmivR5O573FXYY5nycYum9WPXJvhC1IwQX/9D5B+1oIh976
CKj+LsmMkCJSDDviYu7SSLe8N8NdyPKCTimAgZEGXKIh9ikgUbo+xH7ju19MezSlgmBR9iHmr7Vo
1t0o4MlOPLQSE99pkxWPcKE3dybl8m5e87Mnl1WO2tL2/M55tLt0ct/h1sPxsYQmCzOdyjTq2MxR
1lfc2qa2rdbI8D7ntegb7ZfXQyuu5wH6ZTOzJPWTZwrV+1IFVUbx8jiKm3pp6rQUk9zXC1dvUVmM
ippYRgD77HDn23tqjQ8pW1EU5TPK/ju4KhIqf9cRg0+ONAIEXHPZBwyBHRoAIeuqWVAy1CDfg0tN
5hcxzW2AzL0/VzMQT5o8gY7Tw8SOGOXoJwBMnARY7PO6tiow6dOurZrkLqD0VGQDVtb/t6RENK2r
9hNBmysq6EySLoenlxie74ymF/h0XKOkRn/J8LN5MyggavM9MeNUtrZDihUnWOJGleKnaMIcLk4G
ICwoyAo8U8XClSDIqlPLGXEgr6vy2gWkomS/Mc5j8SXeSR1CI45P1fVkUVGhUtVi3SUPoSx31afL
6a/Svas2mDZ+NI+XTxTdvtXVeST/MgIZEx2ae13ioqkiCNnexZUl9ba8vkTwg4E0r1ALPENHV68Y
15o46jzjvGSoFpan8CAdbHy7TzTvj8SxAsdBGtlnUphPPtCfJFdY305U0THyPZZ1DEORFw7zPAKo
z/sv00nERH0X8adTwA3/JWfmDOIBSGc0vtsZrS7J6yeXSwBVjYZ+4YMpOQCajLhnCk0knvX1KFov
8EcP4tdYkfKg34TOQNraTP788v/Akk5h4ScftWgyrzYmfRYnrvRXA3jcS9Ydjjiu/U4RLPHMfzAY
629mi3s7uNOV3kobbEucjzpgiTG0/3GsU9yAhfcCY8QpWgso7WzHEacWHjBJMFQrQEQbK5ujx0GM
waOqdlA3M+clxWiUQGbjfk0mgB40Gg0PSm0RqIoOGnqqlt3tHukkdg/L3TchNY0aNH51zEFhH/IS
WkT0IIT/H8FKB0LSbRa5p3GjS+lXz+Z5Ie7b6/LgH1Qv+cjHzr5+30BpuJvshAlgUbxCTESM0r/G
iPfYPMgGqfCFPKqWW7Bfw8nvrWQzAHk2C/hm3R3uk7BwnvlcCHTFgT++/8j1QimYCCtRDJH8F+9v
twZWvVlojsSBgcXgXRucmnuAK0oZkVteM2uPkVeike/zvEgQpbbcTjSU0uu9IJ3k/MvonPAqbTsQ
Gtllw1zPVoPdyvnt4Q1c4AtbjsBa+/uMLjor5qhIPi5LhL4JqZcFCqbpVkhjJsRSWmQZqs9BshR9
yGTYfpbC1unSyChJs1FK5wxWVRUAqIPlnjqvSAtIBKqhBbQl5LDS9kESSYv7m7hVlVbELbo1p1ip
ezemXdWTkLR9P5c/5hiemaw5L6USffNgtuzwm4C3YSkXxm3C1dt17c4z1/87+NFIALeNzUADxW5U
b8yL9zB5QmAhnqA4Nw8M+GCsxAl6Zr2Of9H9ru+PL9a9QE7AhOE+hk92QXz27exmDjMayPbAQP/7
LUIpf7k/dfFaXffAIwKTVXncqP4WWj93YY7tgzNA/fR9A+6XDzAJ6+qfvRYiV8o0nO7QyLc3zZCz
JKj6Ym+8mG3xFn32wKvGQniWjybaruFW7TH8yPYCSRc/qfr9D8+twzOE83PYkZDUPUYaLrKjXEvf
OzE8mID+H15cVQRbVDpZk1yLzk3w5fz8kEtz/zkc9JhpvNLrsr+AmWCJyktFAId8bu3M9FggDZS0
FYLZtweBdFn7izBvI7mdHfV6e/XmafyVBOSttWHUPF2o1Ob13qcd6ZCSdKNpkYSxLRWfhGFiGDlp
0SjCyxr/ELfmi3ql4rL10gzg0TxOOBq9TDWDOfYDUBxeN3giFJ9iYGShL7GTAIODP0AQEIskqTV2
NT6Jm8V/swFRhSOXX0jEaH1J3MuE31CpaTNeMcid8jlLPrdC2aEKGR+RgfeoSlBMeQplaCBlIkxa
vw8+cyUODhO5frK/fDJd0SqNHtU+UTkt6gw5h+1kUDmz5ft+GArsg9A9/rgD6byplQ5cgtxz12JH
lJNcghYoO3FwHIJShRCPZavHUZi14xIEH/VPAck8q7u1SbQhaNnkW1c8UdTHVQGhJcwgrUodjoDz
E5u0brPFu+kVAyR2XQkfNV54qb6pNF5l/CeJ0G1wpVOtHg5RsTW+Gxv9HH9+42F7NhoKdFUMZNCA
dA1bAblQHS0Xwiv42puN2gcMXnV5MhtWRhUgqcEAa/Lsd/sLaQEj2WVvZRiLVV3mK1Hkj/2SvQ6t
xDCH6UbYatGrv5EsB2L7xzf5Mcc8Jz5JXrwWBiHcrt5nIYMS429cVJpfUTB7akhmYr40s8sHD5vf
9aRtaFHAPEl55TMgzc15AJFhoPjFRBHsJCjFcpmFv8KxKVEwRUVxqwOT4lbxpoHfAI5GkN20H1HW
J23bOR00/8tSZjK/wpF5aPHciDcNemsIQrASZ22SyYaOO/28HKsQGpljbTP1dDgwmhRppgz3+H0o
GQF2mJ2+cOGLS6mwppnPO8XRmlM57KUFWBY3uLiVhFFIr+5e5TnHGgnh3FknMjWFCJbAlqbZLgeS
+tTPyZ6uOHHziEvgXC0FIspV6N4vWZTBjZEuuECXpN54LeX3orSiQJjb6RxirbhGnALRbytGM2iz
yXedZqwZsMChVHDXpc/tpwIYuQa9LEZ3ItuCziFDgA3y24iIikR1GxeRtu/JyMEESOCQlBSihpin
iABoc6VWlbmA7bls50At4avVBs06p80LnQY9Nke+ixRXNSvvClvjjckUc8eq/x7Y1xB4Z+0rFWXh
Mu3gY9rp6hvOqc0N+g9p5AoYzHYXEvj95+VE3EB+WqrugoK6dO5oa3uSuvBV/pmrokq6c0PuBn++
/bJ1gL8yGuyEkbXEP03rry90ewSw0/Te5oceT32FBEstk/3Twz9wN+kJT1W+DeZtQGLLmlQKd89X
jb7z0kt6zKCcfJrkQuxzOhvyfkA9uAOCZKpzqG3o6vTJpbME7GiUKZL5znJnacf/x2bFfG5gs3EA
UCxWNO/aR0DUggq1wIb8qR10969brWmEhp1ySLCQFJSrQw3Ey8M8+xQ3qGs6/7GLDgsRVkqAGQ9j
DtBqyfH3SriBSr8IT6UTz38lXv9yTnW7b5TfFHid+A0EBohmoWPpfijHBrzG2acEH9yjQiK0Aqdh
g/8xijf0s2OcBt1XZWB71UfHuD675frzLN54LcyQatdDm3ybCcQY9wlNpLfiRG65Apk3c8ZwOS2T
cSEITfKq+f9FnW9ne6V4MV28g4dZ6hXx9eF69AGCk0SZxuBly+ZTkH8IHuhKX0Yb9ysXeUBy2nBb
iV0RevFOzfstuSyz/8B6PNUGXUrEahaDPC6NH0lletGunMSkZl0ghRE+b6pbekqS9MQkTKTGO4A9
uNOvBu6oMZDXLLpvqRS3ikQJYZ6CLSmZhC/Wuyq+zuGHj5klFIQaVO/nfh+ITuKjRgqM/PEmI3Kd
+8obocfo3iG6PhBpykqLpkstSOS0jxW6wlCY6aWFViwlKisCp+dW8ZNaV0GYf9Br2MmZt/KXHayr
A6T+hNSixK0yD2pUAV1FMDchh0Pzf1O2oOwrtdmix1AAGotGxGpxoqfvjpi4osTKKDrhaaQjBd7S
iUfDiIPjIcanu1H4CGHkHPOkHGRRNm2WCwAswMFCdtgyAsHAwAr7Vw3X8VFs10XwPEdRCC2W4caS
H/mr7ZZGm4XvCaSfuU1Kgi0K13PxkFtXsYYKMTxJIIrDj6DOxVwA85JOABjDEJw/S2Co6YWBDSLh
Hoe0v9ijG2h1OGeq2RzrEF46SiNSAR8KXdJE5zAaSeqSocv6OGoAi+3RS4ODnj+OR+UMvFWBB93M
OaxzVtyX+Z40bhdKYIzYQ+paMlfxmHxa68IWBDtH4O2WXqo6mQ781cYAdsB9h8nnZ6+w/aWna5ur
W4tSXuiFW/0j7ROAxVYvqZb86pohi5ENMaZA1lY5F+WU4bYUihNpCUhVfnsjzbwmxGinrv4ieOFr
FiYN8/H2RcDN8j59KUhrvn2iQhDrAKMCragzBU3hSD9lMnWfidUnJhz/O5LM/qhTNrbSxMtcVwmN
gg0twBzSHzQwV4Blnz/1iH9pxG1DRjkhxm1pLPM6BhqOUlKcC+vathOJIGB0YDrdsHnLJx6twlv7
NIoyY04vZw00eMOgBiDBkKLwgn1gnJGCNXZ03wcwsEqO5Bpsc5vVhmudCC/9Ug6B61qHGz0F+1c7
zKuhijIGHym+Wm8c28/GjbCileGoQwacK282aEtFHov5qWWNISY5nsk+cWkucIHAiRT81WI0/uWK
ZuoF3eFzSJcudZbkXvtIYNH3y6hayGRW+axLnz5eP1zyEvOMn6nkmVN6R6zepV7+UjyFrkjF2DLg
zY3mE4z65mFBxEX7961mnWf32PhSnijTsMD4xFq50oUoNNzBuaylmt081igCuoQgzJn+8ovHYJxa
cOpVVG/E8xsX4ksV/VU9mT72aOTCUziyhNCHuW1OctwDjReTbpnPlvQ3O79j/62WDRoLzbsouZlS
v/X1/tSLyrEL/dkaDfFgYdnEDVyR6eORarenXt5lMbIcxN3Pfkcefh0vk0ZyPhOJIqLwUQDEFAnu
a+XwEBvD9OMpQKM0vE0g7K2SWyJCgl/w/XXErfMMeZvrQThd5XI6lwdufVvzcwGnbCxrRFBi+2bc
zpd5B0q/GCDsh/pLRV83PdM6NwAcav0GPrG5+52igyiWf8AkbJnlbDfu5IS6qR5M19oM0ka7sB6J
DCSA6OA6HuGR2v6JTeR7L8a/kG26NhOzqy5yDObL3V4TxE9ahOtObn+aUz2nFkxOv9PGEanz3KsL
9VwtpUQ+88ZfgXZqTR0LQcT/rRYfTuOtC+ABoG3yffY18ZIUhd9le9UARE8AJkWvXkjqaFNO3stl
yGkexeJHLVsWwgYnFIgvLLm3mVq9r9tKEmQbyghUI7P0LLDKR9zr5UNO3Hm6v5XVWD5RLdmAxPs/
x7GPTtxRlLKkWjWal2APPv31MYOjj5f2UuknHLSDapoaED2K69RXApT3dBW2r4JCr6nlrwS9wecA
4wUO3a+nSf01EvtgP/4p83l4TtMUwG9gwKWEtxUq84xhLuUYSCFzBYTQJit7IBgs2VuSb6Ix8ah1
Fe+0JuTlLMGh6nYBZRthM7CE1CTtssAAGHNX8IvT/U1XNX/CcQshosj8aXcz+CNkj7XcQ6xBEABO
Bu79I/b/fC1U5Zfr6jvz/lSyN41LN0Ia0EzY7OYgNfH7Mp/BhFuYRdqhQHBn9tWgc4/2Co2Mp+b1
+wAoGyfka8MIBaIwJY+eW6bFF45hMgkeUqdpD12SnVyM4KXhISlTzhZYmg/ILVI01OaQfEPvnQrm
dqGwtFCWhzAoBAxZZZdh2fMl/cRAEgk5jED2U4x+uMQaPYOKTxzF81kiSKmyzzgrmuZ6evCN3Dq4
KimZDZzNwuIqO5+pYzhk9pE2ilo+0FGMICMPmau0ZGhKZwmII/h3lKflxbnLDJO3l1v2ZIACVCI7
seNCyV2AvBNGoTCst95gXTxidcjoq8cnXbmxC45Dy4UYzYHNH6k+95Yr6Gg6rlTC+StZ0ohFP22D
rOXe/zCUT5mui2ovAEl/z02WAPgGdGh41O08IX2JHqUgQSCSsb4zMGlqSQJLv0YtwzQX2mApU56j
uy3R+Nu+0lV4Ywa2Lxka7r0yvAQzjLbtEGOdGzSNKQko6IVNa6Nffnpofde6EwFLpjL8bSsHaiRL
hRH/8VMnM7wU0hMgDd5hhJSJZ4eO2KgyvQ+J0qgNl0JLPcjUzSuFS4Lz71njiIbyZVlAMr8Nffv7
Uug29xRfZSUlgMqiW1cyU0ue7WodppH8kk/AttZwhFNVzpJgFUmrZ27xQ0ycCO4zOZN/eRSU7T0S
Gg5NcRUNReiZ8Ighic7Fjx2uG4Ub/RhIFh38LLu7ci1YJNfF6juPr7MzsgKCW/48Vm5tX/xcFL+p
ggd3uuGBA42tjZu0IxSWg0os9uth6ycajALf3+uTmbuunDxznfNYia2cCT7/2BaYTlRX/jYRYmj6
f54xL+lsnLwB5DRwYv3VqfMXjIrzPqdctcmFcStiHLFu6iTeA2ZnOcSf0YPiHK4iUe9hkdPE7MYt
FDDScY+zhnC/Iiz67Xiytl8J5xgJott+a8zz7qGskwUnejQbyCTBZBMXlEyqP/EEdz+CdV61GdAw
HByZvRWkELKN14xaLebdXIOxiDIgs4v3LzKg5rjJk1pdG9+G4o/D8S/vCKFokhtXEQAj2fnZODC1
YZtitnCE+KTcz/4VXT2GNMO+D/9s0AKy3S/2yeN6QKHA/g6EzPyRLht+DFIZk24qY2zNertTdMwn
S1o7Tuzs9LXzQSH3CRl/pSkXPRcPmDdICMOPBgevehrHCW0XjnRsfQqOIiqOJVLluC/RPNQZ9BXD
76cMHFB7PFPkEs6LAEGBmOlvEYhPcpTai5m3ftj1SR/vRX68BEK0PCk9GMYBBic7Z/nVl51EhVTr
2oLZ5RynH4yr6ussoc/UdTRkVO3RPTvA6Q4RE6xqYfWjk3wtrbzlqsMqQZ6a2wt7loBnnDghCNO9
f5UhgdmsgDrUaCIiKOcK8Qs46QxL4DdiprdzgT9mXF5sAF+673FjtcKI9KPZ6d8IJPXpBQYEehKu
EPDEIFLF3/EEi5ojcPM4doZcc5FfkTVtur3gg6aMmtMRCPQAgq5sa2i8FC2oYrkddi1eWeFj9Mg6
saLTb73war9lmDBEBVWRpHJWRDO26d1LyD3BPhocwEd5XxL2XjP/fo7LAmqdxIaJb6rzD9klwLXT
k9keKckvbkf7HJ7kYijn5XCydXErSDIUKx9IqXG/IDvyPhIa/vKWPO407eoLzs81E7IykqpOF8c5
L8TQuHJxwuSu1lS+yaEgxUxbXju1qBM3DgMfHEcc9btLQPVM3WYCoHvuf3xuq/Z/tIJmsryyc8lz
KIjTOgqR/ZrsRZAmGEJmYrURFTvW+EZH4IgB30PwK6O+bjWyyHfeMVJmrPzsqiT3tIrpLaJ9znxb
alAFYltyfpomIzgUckgbxFLejfJI8+u8MpmDEK4lRTwVzeIk8LzRcySmKWSoVjse5Bee0ccXO2hi
xJmmkP7LscmoCa5V2pPo2SrRx2aY53cASbse50J2ojJfau/488qbPKFAReeC4cS+k+1o30lKYgTO
D8zT7s3v44+OaYVm8yctIeelP+NjK4Pkw3Dt0EoEf8OaZ3b4wvemIjCNTpLaHThYLYnyDM03KwYI
RBphBF5F9CuYxEqMHKuLEufDmr0y4LYKIkbr4QhhunoBm5nCc6Q6s6/R1IerUQEP5fRkdTT9TPT6
56aKrx/kDB3nRISAxmoBQxp4k17j6LasjyituDCpyryjIjTYHjR+MQQxqxTx1VwTvaK6FJ0rLH0o
kcazNwhwvBXj9FP94374xeaQB6Bls23w4RFGfGA6qRS3f2MS+oUun/BcGcO2oV+gG8kncRcbBzkz
JclaNgJp1l6BfDMzfOXDvJn2jKe8siyg59ZYGejfECdAglDfe0b42FQ1OeciHRIPNn2j4XlGDFe5
N/uRnAcVs+W3IncwMu1Soe9DtxcMA+1Rlhl8lgfj/XsqQheZtp2ucoaH49Y3ZFmQAfMNGJeRHRnz
9JGGygnuORxxA8WOHLqZWRG71JdDfU8Oa8tCah4o2ruqZow+vClW0cnwxd/Fmo2eZ4cuF41J/li0
keKJp2Vm/0fHk30mAHRzHaQNGnRQp19upGewUECK4hZomEb2WEZHOet8cKzcbk4SgktpDokzxNeW
U0udXJ0X9fpFCEnhTGMZ9dDBmgD4Fewarrp5DX6tRRYuZEKsku2lUqujodlFjRRjbh/3SyCyEenL
r73+3wMb2H4Ma/TmQa/HkNVk3ulh4TN3sdvCg8aPV/pWcEIuDHxcgE+x3pdJJbptNYIl0OgLAp3w
4rpCdaLVrtk/WP41p1TBh7U6c371AF8zA3mxW7zUi5FHuEqBYYzxZEElCuEGoPKviCAESq2gABvU
2BRiYh9fGh14B96hyu2KMufC2YYTr9in1yKxhtrSJoFYQLfAvck6WZnr6n4opDsV4tbjf6qjCnA3
w+P4YFFf4YN8Qr5qE1xZQxN+ol8D60diV7t6RllLH4Dz+hAWAHq2D9w87uOhLH0lYyrJ/3eXjnhV
rUl5AjOn6jaX9cysmic5FqA7HMlC7NqdBTgDP+ouz6z3i2BI8Ug0bXK/octECfNXl4AVEQX+DN+K
an+0R+Ldlnw9E9UpF+mu22vB9cG4PviJ/Rj5UY+kBZHqWQ/yCGuosGnZCP3hiQByMOq7mPBoBDBC
WUVAK280qJdY6XfahM9B++EvHxZZIQU4gxyCGCZDFNTTOC7hH1WjXsq2438lRPaV0Nah3LdfyzJZ
zTBq00//QjUmsyTNHlzATLrbOhFA+DhO9dzUvClxxkOvaRb/daomS4CsvOV5eLiqBY85DxIpKGPw
MXgzIR8rS8Ee5qxFPdcmMhAcz5TQDxhKyFQcjZU3vr9otTzyVa8q4YIre7mW1YQ5Os/Otd+gle4H
lZXdiX9wWYBXOtLL3xMk80/aOvL2kZau6/MrjXJz5uDhzClMkTwY7fEj8UPJE9M6wzIwu+BgUPzM
gxqjoPi2CefIeAauZrty6HAzG4QMHF/Spkm0f5lWMCyw1H/6kXHwdJtcsUPI4MLdiJ5JM/EzJLy4
3zsmcl/3AquE1reHEa73o7uUmQYLcadh15Gtv908iAjH1oUxjt1Q2fLmsIP3phc7JeyPzUH87zM9
lymvYrlN4bBCn7O0uIv9O5d95uSPzwoKp83kh6WwruhAJ9R/WpVXX3t0hgM3cIWN+sybhxifPB50
qmUZ/RyvLW8nBVV5Ox6qyxBVVuk2kPUX/fJ7cJhLxxpGgWThXyq5lIDUq2MJKluRErUqfQ3bdMSs
pCdOKDwek9WSd9vQOtyvv9NXp/4XpvFIODQzS4dRyswDJ7DxKqbFYZooeBEVxnAaa9X+KpMKWwuP
0TTCeJWoGesRWUyWbo9TeqLPq6SeEpyiCq75kk8zpyBIQlMG1oRm7rcyroyJ+uvuJfpOuwf0TjsK
bbel3OmVF1IPfZ/zOyT32b64CCqp91FuftpTvy4MSZeLeSgfJhQsodnlmSvNgk4mtJf8v9yDQoSH
hasBsJ1IdMhQix/OYvqV4RKgdNArB/aUPCG13Nzd0vPyAKvocg2IoaQsNFdFMNJ5h/YuL2afvqdr
3ZX2DO/Co/d3Ywd2bb7gQ026GjI2vpMcV15y+JB2himB1oWWCJ/PGnW/sHZIVN/JsJUxPqomHX2A
lFkDL0w5GM06UfI4OPzwYIowpfeimlukAViXdApCIrdCenoUygFgTGt505VK2lPsvKHEqt+UZgD1
64fzXlgQTOdeOd28GacZDnOE1KTMD5gQk8SEFBF8dsZwckAlPapX9ngOofBLICwlbC5nc2srPLh8
2Z75RbsQwwjRwS1J50VumVE0HXeJbvH5SrPQzx0St8gH+s3rdNGtHX5Sz/IocKMC2HwIs5yJ9umq
L4lY/yPhx8ythwN0vdKu1pyaxtnHFK7tWkHLooZ4TxZlle+haZgTkRqL95tgX8lbuWWbxdN37oiS
ZvTpCAfOIxOHdFdTyDr9+PXe3Bn+aI+9Vac9+ecDIv7QQTCWL6zsXdDhV8QWpzB6eXe8nIjqwFEG
1Tc6japs0S+qif3mR3GkhsysqdxNjwY2eZchJo92R8EhvXpQrt+HobinVjEfu9oOVTqDj54hIIg6
/SWhyfq/AbtR8rDHRJiO7rQbqdWFXDIlqy5fnImRujXDjz5AxdMDtQm+ZHLrPmPf9ty3TtbgUx9l
LlYKVRypoQzLl4ZFWhEvgSCg2GvV+l8PXdROXJxP1IMn16vr+G2db0okwuIn+EYEbGiaeawmW4mE
vQ/DCKuCoh9UVGhiQ4qic1f5ICcaGoSMm8kExhGul8c+48L9uZq7ZZKiaI+55yOz1RkqPinzfkWw
xiJNuyEMy3i8i8CanoAi7MPC2GdJwkGRbMZZwXI6S7m0DacC9Xy6PiZnPCw+FF8B6Vf2+SxYBVVY
z8dr/nLrYUdDovtvEJ51nErA3clZ7W7EQbt7WcJnrk80Qj4urpJbZSYgjdwE0ycMgrorVfQVb7U7
wts/N243KU01xOaJgW1q5yiKnwZRa/NTVUvzz1HIrZ2v3D+uR7dlvXxU0C0EBbHiC2DXixJ4dcqq
y5zkb1CMdgnZ01DliZ2SOa4k6rfzehnrBhOw+f0Z9K/GhUfe1d+zwg4wTVNTPYJlULqgR0n768so
Wy5j5Q3Jr4YZrHoOCxxc6yh/JOZyOPUwBUyCaPF8XilQgaBopO3aJBwyrJL4BFolNZMVBDXcRs5T
3gWCDGh1lZLdrA14RGB0fy3Fzr1xELJG7IpaZCPJpuuxm66IJOSAQPGWo4Me7nzxN3kvIxP5sXHh
LPUu1jXZxKnxy75djUXMt1BkaOEfW+z3+Oo3p0DOamcA643wY4YfrA01WKVUa62C/Izx+fJ9VRRV
G8aNohPMbldZ7msyIFGPodrMGI386X20E7SDU/YYeulQm9TR90F8QyYzbYoW2kJeOEZ2VLUSOhH7
TjrhEQ5OS9+nSvEZxkKGh919R49my8XFsBms7w5ZbLl2Yt52YvS0vxspafF0FTtJb55p3dw+iTbr
dJr5x1X8ngY3a42f2xx9gyWD6TdlrigvM/umYMVQN3c9abeIw1yXh85/Y981rtZmiEE67I6GxzK/
Wl/7Zybo28faRQXOQucAepA3FwjT6fBJ3E/u+gNSQ1Ab2JVS62L94i1uhhlHu8LiKb+wME7my/t/
Y8MPGuJG0o1gglplBjsjPZpbmBm3DkelLFMO2ZK8to+Zam9xv3g+OCdwcJx/WDJTVCSn7aBOFLkn
xsIMDRMvuFgRrJQJUAKV8oIwCmLyVexFECPvMCqX2wS3UGodXtVwzhKZrS1n8EUzIh95a+wFndZi
ORkXcwqFx4PcZKFhT0sOujZhYJOaJjWtteAcuC9UReH/jGI62SR/2GGArmovS9BGHXR4VoxZZwC4
nUPSWF5nvjaYUSKGMauYVlb53Mgfj/NsGeBh2ZxlSrBul7xCiMRG2S+xveBOPPtXHxZ1G9C3CrF9
HZq7zUjVLf3Zvk+jjX/F/Jm0lx8DUQV0BjlMVKiu8UbZHiyxd2/YsNsnVL3v85gBn+/tjqM4nGsJ
UgPOxQANrNQNMw7kJvsNT9xNRUl29iRWbSSL8XThmzm1Zd2ot+Ss0YKO7TMZOJUnjOlodRpabT8U
9WJrPK7utMCiuq4QztziTAZkYYM8OdAyQis51D6WqM1IxK5NqycQUBXrAE9qx88a6wfnyYNTQr5V
bAah1u+Uom2AJHCfGMGN5sQYExCJvfsYcOhpjO5i3TP+JMv+0pPezA6JSJeKEjqt+eSofScpSfpa
VS3naccH9Ne/u0KexIxzcf8pcKJsUHhGVTQuMVJgjd6LdN47zWK58UsV8bp7ml+oqX58MGTCTzr7
B1voLZzgOgN9UbLfs5Bkpz8tA+8tf1joxP81z00t/ms/UmDOOyAbmxZVlW/KH/kZkNiZUeQYdtAF
58hL9/0J1RGfR9LWs/QLTUPLSMGoOoqfoqGtyJcCDiyEQ33wbPxo34oyBSBEisVgCS4ffwcGFjdO
gi8fRHLDtqm5kmXJvtAJJ39y/CQUg1ba9kAKyqYaAjRku9WnpeFud6YdRbkZM/Z/oLF+0FkvGZnd
rwTi33qZcTCbUmLc8mjZjHmp+TZbhihmnsbRMyHkZue+KLlGSRWohtjODIZKtakWHG+335QcB7PE
ESQdvaIDaFbcvDwpjF+TBQpqe2iTOIBhGKL/mbIMNltTJ77lZdnzVTMGRyAvBynG4lyk+oU4ou0n
O8VZ4emIIBj8vPGkAu7yj3tTChIfQj8+sJSMy0hdCnX3BrYQ6kFhWt5bBv7HGIHrJRN9AHaQLBS9
86Qyy8lQZpIEX8GX7GB7QKoBIoiL72Nd5laqQAYI8zEw3s+7ZEbONY7GqaivYbhuizmoEAKbI3u5
FIfv4crEOQbtCLY6UZdT05DrKjtBP/hfy6rTYX4K9Hww9JIsoET7FFBBwjaP0K3ZtrW2vnhxb4Ii
Td0MuWkeZBGRpngeI1wHR4qGPQb2jsVD2n+8zlluGIxvwkJ1YNGIgz6BA8KA9axvh1bwXml4CHHD
S20gdByggeXFCvgiA9sjsuTLDwWUWIFwFI97ny8eVrANUwcaE5mTkWYF7Lp9K6xdMdvnYSPU07sO
Tpy9YXhfnf/RDgBwqNeRnxtUxjFumgj0q9KnOOPqhSrWdX67ly9CZ7uJ0aFadOgngwcWuxdbVUaF
+V2giviYjgXAnYm1MhT9tng35o257D+HtjuIgdQEcyZVEtV4fiXyDqLhjBKKppjMap8frHOA/PsB
PQxrm8kBuiSxod7ru/rmvjjGuKRxMi9/uIp9wGHwKX8TJ/tEnLl7Fdce84vmOakRGCAbvRMMg9iG
vYBUhw0SWYJOTfHxyaQtI/y7pqDwgY9BUCOx31eClbhnyu7N+B92o9Wxmmx5+rB76kv8pxmBDHCy
3h0E8O4ICjFiADGg9Phyr6YyGDsVbl3eU1lHvY3796V+0SSO0PgYhKsp2gCrGjI58AJh8eqHxD+j
d24fTCWmK1HoB+zapfRQwuKZvdypblut3dxHJWr9YNBBbs0V+SWO/bwO3EuIgbb/LzaKb7ea4fLf
1J1jw//1gIsoTOdzTKe5b6O61V5xx3hpSH5/pwNz2KvTfEryxFPL3IOPLu7SbBb+5JqvJ4CCEzkU
SJVes8hYWZ9HaOYoTpTzu0TT0RGjG1wwMQOOx0nEZFn9QJcsEQtgNnHTDMc8/QGwwxGjL3Ig2XMg
RjKPeJE+7vHOp+pHpkLYBEranFfstIaj5vAVC1CdMocPf/UFEw3y+Pkj/o8/zefmJD2jiUuLcvfq
u5ZCYJco3iusNWsHfjkVVcY3Zo9zgkuzDMOESUMZ4J2hQzdhKGVh3TcuVvvHz+NxrjEumXvj24Ub
saAxA5ZunxtVqw/FakJnz1C4gN3V8vYvJubhYEc5u2LvRisIpFcNewIa3C+GTZhr2izer6V+XAXW
ZDkJmbUUz/ukp9Fhoth1Y4yaOq+Y3SvfG5nWdKqLcilaP8WsqC29BmfAu4D4VmpzFfoFax2Oxwci
Cvjgt+U84fz6n6P4DrGaHuw6BCJYCHZhTsZUvcHRbhcjm3rIttsmQvbGXTJ/taDAJvz0V3US9ZlK
D6/jmIq2hEsY3GDVuciGPovL6j2zr2Ack6Aoxbolca4t8l6Y+HAaHlSAotNyEAHvJCDaiqXKW1KM
cKgNQjTfZjtSaL5B1HHCr+SP2fzvhqX9UdXwtB6EUnJd6MGtSAd+5sGeB9fehWHVOWXDoTEeD1O6
zBykWCsxZElVsoHyFQeOClZ98iToI3WF7aBBTnMXmFGglN/docdmsBSntpmmYLhiWukm4823Kqex
4ZPI33Ad4uhYi086qR5+nMcDhRQwxn1XinG/p2BXOzoPfFetqu3M+LXR1YGATKgleT9Nzz5LYQ0d
DsKeS+4O839B1jWhy643acecUNZUxPBzvsPJeOc9Sw3n3mGhL0df8WAXmI2Cu5TdX+uTxylEHz9V
eFujak4cAV1rafDVVceh++FTHNmOL5QSL/A5ip2g2tCeMy6ro2fO6lQNNdeLiXqij95SoJw07kga
bXD3+/CKla3AGf7Td+V+HLmo5lW7NZq3eLCo1+cqbWCDXCJ2MxsE0kvDE/2cSq15v6s+2lf1w+gr
lqJ3LSn2lpserYQGOJv+PPeZ5HiCNPiVuPD3Sav5av7TOZlYcs9/DgiszNZ7uOmf+CJqVh4JsZH6
yUqXpKIY+BddC3Tjbn8b40HX7MAC1uf0Lg+eb1SBgPSGFTgAKfKyACr9YBPb5b1zjxn2kjl7kGw1
iBZwGkZOY09fJ6YMnNffn8rZhBE2lAyF4MnSyV0gURh34a9+1U+x9yS4CTIQMCvTN0H7vHUNUWkN
V9bEer2tOn23Ssvs6eLT/8J9BPrQmQ+JgLkQhNwJtX+VKbjTdQV9nOTJXirmFRPZQCwBTWTXoT3H
glKhyeGHKDlUMX1ydz0WUs5xJxiooiEx3Qr+toEB5Su1K8DuR7IMVFCF9Jm0uHrv+P9/QUkd4jMQ
jJKIZDpPVOm9Q4DhqLrwJlpKHo8N1LkKST+uKAFUZvtfb075uzFL+TITfPKADgl/8kZtGml3ijLM
eq1XqmDP2axljf55MjzcF+GVl0Yfy/LySZSmkkSvGt+tWhAEFEY0KooVzdtz8Z/oJQwAaYyMQYma
/sAIIkodH22Dr0CkJ4EM2uBE21hHTt27kwgqL0zc5tLs9CBaL4oS3rrwDXuG+5rPgAoeHkqOOLA9
PYVwpw7Ckt1TEcEVlr4ihUj9QH7xvcKvJQDvORkawSZxuW/2Hsjj0hTPEG52eKtQMQLMF5XGz1YF
yssh5Br2Rypjt3/1n872GztT0a+QA9TdiBRNR59SM4X+m0TcJI8EDT1Bif8bJ/X3vM0IaGPj4XTo
JuOqC1jBtEQyFMyxA9nJZdJIq8IbLDprYYUFanLye/K5ZtN3OnLDUGEQeVaBlw277zcTJ2IJYpwi
fHPcPu86pucQfqfyo6/wUZlJVW7Oe4T7gam61iXpegqQcG884E7pWjnlLr6aVP7aXnorhV3XJi1O
U6E87d2k22iK3+K4KRoyRLkbxmEy9xMgC8wyq4TXFymF7MGQWKJje3Cc32KuOJI9UXclrO7ngS6n
DFbE0bkfi9lVUPBqfGP2qZvgerp7qOQ48KmFAhebPcMTaGOnDUwKz7cuE7mXtabvKXZehYtTAO3v
cAHBmr8ojY+GYS0iu+3Shp5L0rFwr1VQD+SR+FTavjOiIj1epIEb8NQ6/c0xg8pzgs5cI32dBdHQ
bFcdjSW6yrPsnLhIdGJGAVsyEfFfUFDlbjnZzvawykPcjwKq4cnh6LG55v+qpAITgXDtwE8V5tOH
leoe3FUwfFZfehy0ix5t5252OEjyRMISV4zVOoqO50TuM6SeQtYJK0ywy6tOTCHambyswHCLXZIq
GunfhvANQzsOOq9EN0wNPSHthMjNY80OisFrSmp7YzUt+9oZN2tErH3rd08ediD1OYtKRFypBV2J
vDzTBwCdeZMUMywWM0lbMePzjzRXTWJKXgEtra7nqHeRu2fPi51BsWlbm3BOMidSPxNREjNld649
P3bBRTMagKX2wDDxD2tDzoEbcZuis5FfBnr4zuFCFoEHhz0al67GutaCY+TQ28y+tathqK1VlQzF
Id1fazoF+81Zvr4y11dJlVAjJH4ipuI7aAib74TXiyE2MESqG2Rz6txcb3aGkuH5Dz/+JoxfOxnk
jZinFhdz3jH08IlGa7geyX5YniG4gZ5TQfz2OIlynS6hJPvDBDFeDotbA3xmH69WTmN8Z73uQLdK
zmuo9cK2XCVEy5ha5lIfJ248dB6R3JGEdifbKVMWs6N9iilKV6jqzS8GXvJU4h3NxdepA3ifo9Ji
RlxA2qwr5IviOxIMUQQyOVG09zc/l0moFUALu5UKwx2P7kIJi/mVzMEQOTlk2NosTzwjlFZQsuuP
obeY4EpqAjFlx1i2pl0YE5borF4T/V0dsh9i+xkyYUJINhguyDJbV7Ye2EmaY9jOsBJ2OumhoYWZ
BmYMd3ZuoDOtT8q5jW1Nf93k07DTNQl2NyAs+xFFQq85n4c0RseN8m+X5YsxNYOdoIeIPKX0vo37
pY2pl4nHGo0fLvoDWo9Eju/sw2smBgUEtrhOiKF8lMpXEyfKk+v559CrJ7D4OF5lsBV+D4SqUnoI
dpPFYMORO9hqO6tqf0awJrMsRbYFph8Gec8kmJ/LE5sxKhFV/TiToIHv+ACpAJVLxF10QUaadPwP
mI2681JmyEv+71hD7ay1dNueowKYyWSCsdiWviNXbxFVwPP5TsPlT4tSwxjKFEkJB8X/zVb+lWjS
3+7N/WGmjNn/pl0ut/NMY1sxxQdmIu5t1CqrJCRtQuSIXsCTQdafkiHppy++u6HZWUyvdpFFn6kB
LctILQeAqwBWfgFXoQnAe/u8GbscoaNiFgT/jHzWgihMOTJkiPD+jSYG00o4Q9QDpDkFClrznWjp
DIKeq5Kw1aCt4xnQLcQrJcFU2n3s0sZM6bHAGXIXL3nK2b4yo4ptwNhx3LWBYdb+EGJi+60BJdws
B4WZmIq4gW2o8QuGPmtOJfFb3eOQsg3prkgxhJ0CSW0YTn9oXqtkSa57tXTo1lKRZBzhHlVixUon
kYlWlgBdSdH0SXnSFViej8cM2mUTb6I030NXQv9u0fFZJxl7WcpJabE/K2qbTwW/+AAcWDCf1dvs
0biqAB9uKTYfEtzA90A5qx+ht+wP7AX3YfvgBa42D3Vw9iR63gYCGpsnvK1j14FP2sPhoFFTLlKY
rIJ1Myg1AUz90w0hI6V2I+liysWHgkrAXtbR4zZ9RDrEbNoW5Nbe4bHSlY2AeFg4rd4RB/of8eJC
kHD40fxhXd76K9juZ2PToG2QQedzNOxxpWEDUtj2pOIAS2nzcngzJUixyTRygc6jEd5Q4xDwEF2b
iMkR7WruvYs3qYa95zX7x08Ny+7tgfIsafKktOHohvOrX4AZJnxFTRKgo66E6pE8ieXu2ALUOmGB
Py0Uh+7djeqRfDeDSBrp0F2Ip/cwP4z+BXYYuxxX3ViXJZyEdCOfiJfvHQ7nugefNEmu0KFn5nDR
QSvPS3vsa4Z7O0dZeJG67UJt3+cJpO/73zN23KFK6FgH87MBtzrXdXUvCFnH2AS0ZQB2NvznHQ+k
bDoG3Krl7ONWJDp68XmCd67zZxdbjJR/f2VafXWJkPIkt/UIIgvSjcGIvHCbLqg5d339MXrsV8L+
IZtOnqVIfflY+4L2RjdiXfuituhBQIUDDiKQZa/aExonn3Zb9l5LByCKAz0MX/MdBh0mrpph0/Qt
QlH+0hTDfS45vPF4Kx1vv73aoGTpsXISjKYtJLLqvC/KV69UIXyhdVVtZiIf2MjgA86mt5ftoqqG
cUIGQzLPMxfJXqLZGrWWYfwFCp+1uS/qbksnnzNOnFPST9E1WFkW7AX9bQQnJH94JOXUWtZFMOxh
5fKnc+WkF1rkGmNKBU3ZNb+GMwl1GkWrAe3CD5mSHuwAVdLh4sTg/Eel6fG8tuWk026ySEC7OjRm
TV0ZI2geeBklTN1N1ismpFS77/9V97g0P8jqjLCfX8Mp4EzdEJFG2CND6GPP1ADCcNI1dvwRLRVT
jamflNPvAYD8BkitlCQQ4gdiF7bQLjecS/WZ7+65geM8++rrPKX9o+nLGjraPMBZ4TcbOiRJLMEZ
fBfHjM0fy0jIHte6Qn12R5Py/NLo9DPNf6zgH75icWiEa/SeHeSZO/7ZedC2zg9WrohvLPrFfM2c
BW9sgJPLBx8SL/fEzL3j1bKYIDxrisPyFZy/7yU3JXQAa5j80dKb3qLaiXZLEeTyp85X7FqLArN+
6LDUCyOhNLmg55fNRtYM6/gGQSCmqHPrZxJV/K8lCpz2I4gTF29Q52ZHedq/qXxmQ8kGeAFnqprH
/SXc/jn/KcGU84KQrHGsuvOFEwi4bfYtanhxzRVq0IAAQznQ2BEjLQbBv14ctItzs6dwUZaeuugd
j8sVgsEQPPV3rTR/pjUIpc1U7czhT68F85bxGc3Db2q2+d9g3XGULuSEaGQTVPIXA5GjFcCuPL4T
j+/aLtd34Z5bkXr+yXG+LHQepHqxk8T0rei/6SZelIVVbulbAMZb2qiBJYu4cmwKstb/kATRV3qT
dqECizAQB9jQdx0sE+LvFNWb27LF/m5FwKTZrkRowf3Ag25ncKCtnjaequigRDQ44Ik02cIgU3Co
lWpJWDUDh+wwkWQCDSZxAnD+4WDxCBIO8q5lybN4IAF4pt+FCUzKWj+eBGVoh0FdxH94uiXiG3dm
T1FfgQ8R1ME1Lfx7gdfA0w8HmmB6qTkjxaH+fNyhd2knVzkKGYqqbtIiQPx0gN8qzIBCbHdfpTR3
BvrPX+SgaoEBT5dlQ0Jcw0lhmlbaXqW0TIf4l7qxbQNt0AFnfzCDGyrRdG3fdi9EWbpN/eqFJVwd
LeGQ6AlBYb8qOPsyKljZ0GTAuLcFCnu/phH8nBpopshsb6tdeBgKZdV8oVj5FzG1l74GFY4QdqKK
PlzEsKdYTLu5Vt1cR2xWegOvevF0Q1bv91czJC1vUN+/B97BTvd4Sg8/nX/YGFgJjKdtkLFepzwW
5RxpdkGKcBboOHHRZ8vlrCAWg8KOJ8Ulet7r+iLgrdRADErJI/P9zHclNrhUskH0cRcShPc//k95
3FAXi4pJAUxP8NZAWp1c1pzqeCt1uxssi6DMrv8VzZk8C7UEPQicvAcrMvjTzhtg0cb2UttcpZCF
1pd01msRJApAdlj/AjcuHlJVbZ+A0zywUV62eG0BWQu8CKL1iXYLepi+5+MIe6WKij6cIaIiHu89
y/AwdOjQvplhiQwVWkn9WveCnTyAKAe86Ai7SYepekyo+u/Q2OVP1I9MFglPtTXjVMnamkWdPlAp
WYgO3FGBb0JWSE/Hua/dkhFHGvCsLnurI8p2Y0EZ3pg4jWjvKWtw0qm6kt7Xptn8kNdQx22y0Rz5
/KrjXV4U3oEWgbFwKSM+rcRMPpH8YH6DJrxMh1ERusUv9RJyhX4zLuf+KsEoSzstZ1G2w8l7X/2d
E5qib/l8tOMIc7ePzAIW3da0E5aKA5TtKotxzSZar5+lTpwkxz2P9MwGeYw5WHKX6hRaiDmhtdTv
ans35+McHbMcRJvc8lKMNDtM6YkzEgIMdFI4BYv20fUGlTDPx7xGN5cZNUA3G2a17lgCAZ0hkFie
zIUZN2yu0XIrM1tT/a5h7KlssJb6xaY+Rf0/ybTCJM1afmoJvPevkwqG3L3ieAN5soa7IIVFixZ5
j9T3bQN72DbO3MqynwgVx4iassoPgw5+yTPByLcDCOxG847u9rhzeiKoRyhnWEdsz0FIXhkSyVKJ
U/wuLHICu8JcNYdmUeS8BcHnu0Izjf/vkvWo+Zs7UEgrTp/pTMv+mzwHACmcIUAYf6A8jZc12/R7
VApQsUv/xRkZluxBpWoOdW5S9AbpCeCbjXREplz9PuGW+VTds9QvcV78L7yBJlLz1maz7qbFYcRz
FahgX7D8NsYXGvexLRVzYkQIWnRzN7sQ6eCsZgul0iJ4ahssbKAA2Ua4FUkXQWfVjxRICMIS46uC
t+2YLdWm/r2yPrFGuDo8a9mgm4OObCL5zBPSVzhH9THmLgmiF9dF2yGBj0WoHnxcOPKiOR8AxxyO
9GUsrsOrenB4//rOIPf2me7PBu24qj9Ve3u7DtcUpsYau81cscJZLDH/zD+M7vikqKO/SBdxqLmG
kcU/x4lwyHsgtPftdKetzScWQvG+sxQNoJzV9s0LZQvH2omuuwx7frPabiiolrFgSpS41zF682TP
rgWZ+VxsdJ60UtzywemJ2OVyu8m2MkirUsGLR4rlmIhQdRmJoc7zWpYE9C66hU0tHWcKj4YCR03r
xT2aF7NMV6jhGI7mCM4JYf1PND6jSJWOtn+JV0UhknJAKFwCxEktIMixlNtpAqh6gUkHtsgR9E22
EpDKXRXoDbCy5eeL0PadxPYefkBiIuR5CLAmZiiyIgREsebct/oxOnhLQy37WVGnF41Jmxr+vQq0
nB5arFkRrpuYssy+fM5ccRE8rvnNNOb076zrXMTxdZPS/lYdzp77DbQKUfmee3VGMh3dlSY4Jybh
s6MIgtIj9ufzzNLOfoPsDCwRVVy9BOa3IHaA0q6b86WmvMTtTbVG7IcOT+tjX8EIPe5AgfAIG6cc
MAUNI7+NekaAm2mtOQDSezr9puMjFegbJudYj0BM7/yug0JmFYgndsaOtfPRdgy5SeIx+hZEbxmh
O0NPet98cggtqZkFAN6xMium/JYjLQGJiHKWaj5Hm1+5HuEF2qGs+1W5ITAT8M5dNQawpzOXBibS
JI5/ECFefoGammLJQVkzlHD/FW/T5RhB7cahlU5YvfbN8AGZNvxecrMNV0kO2GXZ49yc4/X3MCU9
wly+rbGCBWEsi0qtx6Lz/WPl2FjEhjGsIIss7OlInnpo4QmGeLDP+fQwCzJEpKb1LWAK+Zbk8BXP
+ZXGFQOm/AxdXxDqJ1vs36rEaFL74eZqAw+O0+NV0WxvPKpQT0umv8mSdMZTD195U3IgC8XVp5LA
VdYMcNfW5wY/xhLmkZK5RxzDHm9yu0dE9t3BLcvuP144n92nspaiQGL7IH0U0EhjLhEPWL/2zphf
D+/qXwbHZS9yrgN1s7Ub/7/xnxYMGDXuRgUrXfnLHvNov4D9wMghgq7eVBxRbElT6/BMfdKeEEgt
u4Nh2itnVUBEtnkAcCHwEn75BxeUoXjy63uMgkKwaR2CvQlmgXoHeh2KGm7t5KSh1IG19Qthn3qP
tDlX4tha1LzrRMOAaOqQ0dob8yxNWNd00rN8Y60aPUfou+RLAi8qenEgm1tWvBY2c1xAMdYdaiPM
KF1G0a5QnH0JRukhS6modlw+1CaA0jijwXmqFJaro8FMgk0qaC5WGNl2vNePWFEmpQNOvInJziGA
dPO4U/Zoq5j2zmR3M/5KrvmTEFFZzBn3V9zzS2rO31pBhidlZCVXPw+noKmtCotNBnAmO+Jcrb7Y
/tAoqf9b2/4GqLdqPhiWgZ8VhG37i4DY3QsZBqQnKVLxWkQlCQebBl77WF3pGHOI8hV+QoF2sGQS
3+UlGtc/IincOHYMowsYCrcnIlH1O8tjQZKeY8BVY34f4jfIPXKtOa8iRcZtVqaRR87aE7qf2fvn
zzk0CL09ySfCdK94sopzc/CIqABOx8uiD1AB0FU0VJmPwoi9VPGrKvpRXpfgduOe2ZrrhZvuDMoC
I35AnhDXZquVsq5A2FMH1TGGfAN7K8BzSiXjchXbe+Y63LI2LzBh6oQTQG2qQfpLw1Wf50A4q/lp
5PvsJkZsuTNm9EtldVnF82FIlPH4zOo9MJibsPOD8ZiMJgz160LBTTlyi7jetzXIN8EdrH9Twftw
BiDZVGulx62sa9j/dwGuI6XuDdk+VUiSegipDRs43ySKnXKc/Fnxu50VSmBz78NDBDg+qIGhJGtJ
esgwFK2kZ6puBoJ0xbCYOX5NaJdMN0vOOIYm2LbIZ87EMyvSvfZRsguwlYoHEO3sGl+99aE5eUXN
vbYw+LKBWczMLhZyXuDwQnUmSVP9ALDCnyweyCnTXKNRy2r11L6wTriKaYrjbyO8skIvxz9q21LL
Pl8AtIJnM8ywEbpewpV75bShg/dJdE1DHHP9mSuwfhuSGsunRCeJvnCol2zd4JlmqbPuVzQOXObA
cUgqJcVwVRXSxdn8fac31i5Jvo5MQn8ed1v7NvfcxOa6yyHOmubkRDj64PH/GQwPqh28lCGn93Se
MYJoD2v2SNFauva65ZKbQEzBsIksbzHyje/kuDZWjw6Ai3zMhe1rD+7IC+e2wMCvzp80gehb7nih
esOsP6ngPgyVM4rJTDMY98kkUK+Xizq1rZM9HGxawMEL/C/MCS8jG5iBdYcG8fTA4SkbPI7VVtiJ
EnsgXGSiHuBESMKOBfDXD46v+XWNZLndwUtiCqJP9nequDggLPecsbNXpvt0UvQ2z52+e3tglSRm
7GnCOIpkHhjKnafX+TTYJGUMZju1SXVJ+6d36k6RAHFDYgYyZJUpneusTztSBlm8m1u/MhIWz0rg
2mqWuBTm6w6Z7AgmMqi6rP1+YQRBdBYfXay7JXhJcuiEl9hZfPQyx7LDv5DttyeoovyURkn0FuPY
hxe50s3C88hqgsc3Nzqrznwea9wDAy9SDx4CeDzvKMMjZRNzi6JqD/0SKR8W33eMp4kC7TM77NuP
erQKEXCOrKrSyKk1azp+plytqKJI4DLKNUFxf6V+HrbHD8V1P+bkRtuBmeqNh2e3/7sFyun0Nv4/
TxsRYSDVtVHa5A/Hqt7KP665MS0EdHVlodwwTxaY9VW6SYRp6YGH1sMoiT3tXB72zw+Za0UnogCs
ZbSr+9oOR6mKqqHXvx0h64ouYsOBsKV2mrwuun1+g/WDrESPy305Wwo71pCWTt1DfQ9m+/xoqqh6
yl5wY3CI0px6EnDpd4WhJSrUmFWCtJjIuZJ1+l2hmHIO1mIWy+PRgxa5mWcgKPr8WS6WgqcatRyi
tw6HB39QD7Fuws6tY3Kl1ksUMs2gpxuDexXCoyVlZgEsxaDLQFsd7w3UvYfb+nghkK2pgM1Twhte
5UeeDNXdZ2tntkfRBnHlo1MbFDntdSvgtm/LiQUNrmJ8vGOHnoTn5bQxgQPZ9xsYzF9HFl5+35nk
SuOIoGo9ullwdJNvb39jjIiLgpZPZ22zNn64RKtm3OpK5RVMTe/1IxspSGSZ+e0P6REsyORVmUZH
snbnaMC2s2bZ3KtFpSrf+/uOsAsz1QbuO/ZvRKZo5TCGApqZi/yVTYm9Pf0783gDp018U35o9e/3
wMFCF9WuXtRXpxiMQQS3+KRpTh01lpJ3INr/y3HfwDr5MeGVXtCILhIAZ1YhufWIC8LAoZvoV+5n
Tp8tlbvYp57yvs2PiCRsnqiDdr03VxZE62WNI7JgscoluauIuAKPtjicdLPzzXPhlOZdGqpgTd9C
Hf38HEVEfbjfSz6sc3WM3cfHk786J7SAFAruGhdMFtTPUxIF6onGbGiMjJ+a6nhPZ2BpJ/qv5loH
FE3J6ir9cRTpEE825qjA8eo1CxytkOMC7nUhF7EOGVQ+AL1pVxUcgSldGneuZFhJsUsP2YuS4LFO
sCH5fEI556gCK1ANUI8y0tjPbQQCeUtL8eGZAiJ6OtutPmrZfDgRRvZuKntSk3Zu9T587vXyC+z4
LDU/OHpIVTldYQMcEqpOA0igNFCn1o2U/JIAvMFl6Y+PZqqqSarA++M0WsAn9k+O6FfLxMvVSxSM
z6KervJrsDDCajahtFGhUr7HadxOq2FWk4Bf4+CSadYCHSVSw0fuuY13FkMeQRju8as6qt8GOlPq
9Zhz8164Asd2xeUeT2Vpuo2FC/wvaM8UHtkciSGDuE/qALByU/C0rD9GZX64bUWj1gu0RN3+C9wG
QPLLXHE0iPUBaT3IEtBEP0EEsI4xu0g4thESH3xDpCz/5mBW71KBaTEhbbc/AakH+px2qy07uDY2
OozNd9QAigJ4p/rKLrmrD3VHaBnp++DsOv3sOi8LW36KefVBwzVA1q6qd3FC60wZmpw39of6Gm+x
R2u6c682qP0gjIwSvuZOPbbUTLSMTMfBnFaTOeAdaeFA3O31BM41M3MYuMsaAHrHx4e00c8daECw
BRL+ruVz9W2zX6AtHsfZtnak0SG5HZdPQy2fsbC4XuoBmkE7sgVKDGDQtCCn0w6XnxbVlubU9svY
c3/ikOnboU7Bf9o6VqmKyxRIolWicrV8965DUgGJqpEO7nfew5MOL0f/gJqu1Q5Oj7WWW+uRdCZW
/WiUURrDNGs57NJ936g15jcb13f5fSBPimxdVcfxASt5Dm5xwZ7mIIlOtiJVeZSs7mBME5vOIbSe
HKp5Xt+JTkp1HZx6xSnrOXINumWukGYb4x6IYfySNWZvRVLdN3ceGL6E8WcviYMOz6dSLpY8ZqEK
zRxW8EuLmdKYr6nnbT5FtpxqcIbz52ATre8xrKBTU4NT+HElit86HVeBM6Rwzd7hUq77zyR+HUo/
S51svYazLVU3l2yotpp2pTX31c9QgaP/wacXi51+KL77cZtZh4eRWAQeTzQBWSDKzvKFJec1mVs4
k9tJGDeeD/OVNFoqMT1lAi7T4zZ6ZspZk9P1AgyqhawUu22zCfJZzXLwD7GoVjbcFNLChMtRRfja
KQK7cbxJQgiKpgNyOKyZO06SmglqqXpXFFiKvBBi7fN/2gF3Oc9MUW0usj/mxEqB4zuDAH3uJfdw
Jeso/FWIcTUwzPuqynX9FNkq1uUGuewcfI1QKjvfcCWOCoqdhH/AP3n3mg+9FGVT68dMulMhcksh
ISarDVsuwvtyWB0xL4eC9zb6PgrsWLihQB26Ng5BnflsHjKy9uVA8YxmRal7NtoMuURo4o71WY87
9qoSBWtFPaUtBAMeFqZliZ5BVzdx43sdzOqUg/ScTM7iAVX8LDAvyd/3qGPjggvXd2wD+Uo1PD4p
Ek0mejYnUDJZS6mVclsAGfKCEAMGf+z8KA9+dQ0H5nvxKu6UOF7WS0b00ICqct+Py9ssop/q869c
AKn9cwe0BLPfzW1dLzO4E9CzN+wbWHYe5d9QxVndNQElKUjGLdrbvZeZYA+P9iajaei4+XtoXXE5
uJ13m1bjsI7MmRNIqFRYPmv84cSoLIiHBPVYwRKKUQWAwv6rDO7drbYHlgCwnfaM7U7NOKnR0pE6
3HsUadiXi8VBkDVWfitwpbAhcLZMCbHrr5aGDyEdAiGjrhFs0Stp1Vujs7S9RN8pQqDjfgsVeHAE
cv65sBBtGG3hPNorXcZ4gGFYH/6/mmB0yIui2eQZtxLqcB31dS30r3qwOMKpjPpcWO6hX2GsQsqV
1/7T+7YhLS0kfr+I5wnbuaFXPCy5lAlgZFfCnBWFYKla5NrN4sQVz2GCo0/sZppjRNUS1osmf1eY
c+tW+m+58WD+6sTn+aRYXlIoQfI9lWuSZrcLSUZXa4YuH1Q7QsJ6CvHbpm6c9XWDWRX9M2EZniyw
5oQ7UuBMt0qIyLr+gl/CREfd9Ln1s08eLRk96n0lSzSY6QKHl6KSTufIg4BxDmGDxJmGPXTvTnZT
/FYVrmn8A9Sz2ARPi+R8pTwx8DkiFqbOBPTxiTyUck+JhgvQVNl+7yqtXTSd83JtmBqkRhAhfeU/
UiVLz2w15uUj7DhCcWPG6oapWZR0wVPQId44eSy0vRHTdHoUv0phpfr8n4YTZbR7rctyN/QaBAP1
4G2HmQBHqVrh3XVcbtrysA8JAq6nbP2DG4QnrdPV2dWU+rDJdOSocky37fgax0XwqlyCA3Bzx0Gn
PccDMZq0+ye2hlA6vhkGIdyZk+ivGxrco5LoWh2AUDqUET59Bd5UGXLQerxiMUqkB2ekwIjPxMkN
sMPt+pJ16rHlhzgLbdttJwf95uLSK+nobvIJdh2Pk4jqMuYMGvpjhnL+s+OES+gmKcJnRiC8RbB4
X9v7Gs7L4x4CXXg50jn9VVxiR/+qUJv8aNiHGnofKUyZW/39Y2iFOEUMdZfr3oZO/6HZRwUcFzRQ
StclklJ/UCl1zXvMLjS3aAW3SLyv3D56nsj91RzfLMvR5zJOxYICiiISZaRTMDHpEoqf4ViJ71DT
MBFGVS65fwWOHHJt4BiT+Gy6ij59CAPCBNLoMnkcVPEEH9Vfh5eMKZ7/7dYaoN93lWKuVFrmcbMG
GCBTJazrKar1TsL3Dk5PAEpVmTzZGNxgeHwmLB0JSrzIyMoObRHi7YwZBCtOKuRguAJzbSCku2N3
UAtvAgKdB4J/xlzAKws7jEtCaRIOKiBk6vEm9dp0J/ug0EtYxMRGNNVGS2cUn24NAlDplavloKlJ
SG8whjoouxfm10ar7TVYgXiG1orCbNebrsejlNT7JF2IvyFWnjtBffZCRLLm5SVzGo09yiVe5ZJB
Gh0SvX4QTH2IWFEX2HEN2Y+Mnzt7l9cFbpIL2dNXSO2pudvTOQS47z1FrJo9vsF/UKZVRrsgO7Vv
D4/IrGHJROaf61bAA3458+KDpPfazDQxJ8DiXEinsIX5b6uUly9SglmfNCY/hUvqhQRDwZy8oLc6
WRNRpeI0Nhjxl0auwrcZ6qMVJ7zSGWdnx1HxiJntOktTlkK7pB5sCAJuWlTOfHOHi3PSmQ4e5TVw
cC6LD8nzeJjrmzuOvsEE2BrDciEvuxqkdKpvDZEpTCs4PFzZvQPOd5lvet6f3g1CSr1s4v7vjJZR
fJYltfGF2B9E3ZG4JUEZLZqSitSGDiXgHBDxd38U5TL6757l3NWqvuziwa01hvTRhs9owkOYqwmX
tr4usRTIWdMwgLYZ+yUWFMyLuglE0az/qgkXlH7KDYztBfz1nFDbNprCb/5ge8xhaUAhhSHdFW3x
Iyj9dLv4r9TpO04/gbdFYdRI5pTg4ANG9qYjS0Tyld62wtinaz2YylLG7r1LL6HqYsr40xgFO5oG
EdOCa9vQLdVGD6tVcGTYPvJ390oirqD7NDKDeoCCBy4N3e1i8iv7fYxmY954g0R4Ns3dtwvrRGCU
v76ApxlMq2L0fi4LZFB/GCD/bi2Ss5TKrj/j5Au6sUxjDl/LZ+AU2jW2C8Q6wj7cFhF1G6tK5/PO
yyXwr39jOA7/efyjqu4cLxZZYLUeCNiluMvsVvhaaaHyvU/dY/2GiWmzWe0Yk99iW3kMiLYB1PhX
eRNIHo7BVp88z2Ynr01tGl/BGfNiRdxyWOptc8LuDdL1gjd1Bp1NzHfR6dC4PIo+GH6rctKRqPg/
sbAz6vC7rsaG9nW1kI4Ec4ytsUde1ywcumHGizlYVgrRzToM0UmlKUp3iUKMLqjc4FcneqIxhAOJ
CsbZJXRxP4FUUaI8YyxQnG1lFSg76aPeoIGT8UePl9lc6my95FrBJlf1CC8YE5Mzn9ywbb+s72O6
+dz/Sqfg61PVZCuOEgU56eJCyFYoSFqz6vOb3jlfZa8+Ws90lThndNU15bn24+iL1ISyOBcsSc7d
ziK03XzBxsjvNbg+i4+FtIyT93WwerefkCjCjrEcjPx8bG99cCDJPMN1HFz9ZC6lEMboQfS/wXjB
hgST6oE1LFDbYaLElEZm/MMt+PST4M0MjBthkwzKJX/ZSW4GKcnXp2dzkvqmbf0b7xSA9Vk1p6JH
MXLhbVprX3apN8THARuqxktPgO9v/PZADd4AeDE+Wtl9lG7tY+Yd3I90dxB19GhUNskYhhPsVvO5
j5MD04xWc1Uc3YbYTfmsdNfJGv104P6zQRuGF+vzB3if7aHxx16FylpdtqKfbnYClm0Ew2v56/pz
wDL1oZ1Hk4nz3dggBgbT3cd7aIIynsQR2mbud//0koTyjc/kBgQJGX8KDJ6Ine8lbzMz6DeoxHHK
EuRvNOQpt/PK2SoASAa63z9OCHBVbSVmsXnYj74W05k5Ys89cmASWmhubu16C7wfgHBB90ICQcIl
wIRpe1l3b98VIcaJc4OWOgsuxO32JZMvsAifZKa0bLBgoMfUY9k1OAYfYe52uCV3DaS+qSIB+IoS
WTmv0c4gw5TuTsCY01hKySnRi8zPA8NSxtwKqC212rapqRqud+Xm2b52dyq8jOkaKvzGoLnFfhQh
QyyeLSYCQ5/VTvF5GAkVkUKt6G3SCvmGUzLriKe13JdakIm0KdbJGaJthqaVrUrpoTWpVZ2OhVhE
HP7QY0TcF20nH/72DAq7uoVPm8oOBBZXbLUMMK/utHKHfH4IndQjs9+wD2H+UTR6Vgf3irSMXuKo
ORqGFD49Ss3yBFD+EtusPAAfJTGxX+KBLuFJBZGZN1AGYNjljbXrlOvMb1zoDHoYMCkRYox/iHL0
rgguln55EBRmNUnMSi7eYKlcHTrNoPfrtECS8Ph6zNN6zAxTUfA89x7FcU8Q3Btqw3Mem+BwA0n0
vdaOE89yJT3tIjBG1wJiwFIvkbkC0sXOhqcH/EQwU3QbiLFVflV0uIurfJMGmcl3q1hdQG6gsBf0
ALQFEtGmHm7Wtc1Uo0DP5ee+33cu9NAKn4tsiVERsbbnPV7F30J6XKQF3camMX6Ptze0INEZFKLZ
f2RxdhqsE8kADB7EhzASO7VVs7OPYnvhNpb2mJ6Q0AP+EUU7D/JM18aGc6C1qDu9UkrjHs5nfFC/
rAKix5vtpevpUsfeBB5U5igTLO+b2bJuAmEdqWFe8oHFGpnjLG7O59T/u2U5gEVCyYxVXvef+/+/
pj88cmES9vle38KGCY/eoh8M5QqXYBpNDrOux9TfX7P9Tkn1N1AWZM04YVAUpnZ7z82DpVQIVGYl
5zEOny/z0Qy1w/94jnw5uLKKjgG5OJusUanEhNAZLkUXUin5EZhpLaluFDH2yYTNxgzZRHyJtnUI
YHefU+pLB4YE+wiIpT9gyyfzP7IqN+VLhkNThsDNTojZoHHSLp2MZbUxRO1FxnzVj4OAstqovzjB
plPenugvWb36gir7ZRQ7UUAcQqLGAL4aq4kz4IZDXhyzY0yIG93yhsQZWn27N2biu7L23QdYCztr
T0kD+vpVUl8b4jRmp3loK7WBGXzUfXnLWu+cxnyBL03p7hNLq4VbtmssaFWpAaL9l4DcDCfc8vLg
vIpojiKxdOw/a3whzVsNM31KyrhobH7accXFb8APFUSqQbYt/t8R8r2JEgFEKAtHaP9aq9HiMjCR
zue+WtVpMLyovfVNOW/+wmZS3IaZeeh90fvejxGa6g76ycGoeCPRx2fitE5AeiKU1xpVSlmuMp6P
435emRDF5cmPkPDjMTTcCcSYYLQsrgQieNRaprrXmiDeXBKZEayiYXSiXafm3z0D/rCj6MhZ3Fjb
Mf/e0g2+gWwsWqz8Lgg13zOSTnWTSGcG9gEJMy9QUkCaaW/Tat8Y7ozLomKWDpt2C8JNd9Sosvfd
cfGrFDFTbU55W4IaG6dffqzfAYRXilNPNHJXj8UXLhJ1bEWKVM13dHmwR5Ht6+6rALFQcxKEePqi
mwKpthPEtW/mfKPPqF2aMdlUjCkWKugW7jUN4aigu6LWheV3RsXITs7+KMrHTapjS+Jq607LW282
KbLUt85MqKq1kdMHk2Gcp9vD/u0/h6A4WQd+EP6nOX9RDDT1HirRLAIyQmZYfpp5G09hdfENCpHl
PdVi+J6+mG1QPS3xvtDzkzthbYXa8hJBge2tBrtoWD6q97Sz1ir0PS0A2O7XndIvbSiG4Q7aOB/P
dMpk4Vwks2+S2jwSYgpSsNiZ8CcaqtV/YcHkQzbJw01LRhvYX6gPlUg4O+hdQy4G//3GTPw8Zh8A
t/Dwun1AfgOyEl3GD+0YBz2uuxpxDLap6A6waqBXwRzOrQuXifvlAWKwlG6Z4H25D9b1C3wjLKAN
xvIvB1ssZKjJdLpR2nx+yP/lQpbIjbwD+ay7zuvHejmq7bAd51GGsZNPP6/daUtdrQJx9Lfz5C/m
gj6Tn26q4L7YWdmx+Z/ndwc7nBxP80S3T+zCqFhp9Re1cQ0Y4H3U7JApDCiq0tFKt0+uE7+XVF9O
kl+gNbzIrlPNfkheLI11GITVSGyfg0C1hFMr12WBcjuQITq+Ya6XH19fQwFkyKUyg0vW/4Cmq4Fu
mYsjuMoC50PK/gaFwcTpWWTEjRMvxHymjHb+z014xGe8jqys2NkB+YEB+gMt5C5kNcmh9PVSerLa
XoX/M57F23B3DSdHKwGC/FyMxn7bnqimbOyKXXz1EyNauJF3BdzzL4ODoR91lz7JEfvYul+lAORE
u1znpSTZxRgqzHQc1RzRjf1c7K/LuAjnK4D2VRo0RbZofmoi+Lelbi78zfdXh2oqXLAx8VXhJpob
Ddax8bEGc8xXIgQKnrQYtUA8xn5RgoZGZ0TyCD2ZhRa9Xdwy8hFuapOGXzdrAPwq++FXqVty3X46
VXmxcxD6MPsXTSN41/t4ptFITslKNcLun6av70WkSsVpcbGGu17pciVnW0FZsjA0H9pHUXxqtlaF
x713k3iBEVBRbfBKiNqhp24OrB04wHRz2yiSoNMdaOKEv4C1yqPteGuf62OUjAq2q0o8YwHqaAU3
lUxjePjo/+t46Pg4yl+zLUEV+xXFlSGuvoOtWqrku38dpXKAT0425XRv+VP+WM3S9F5aX1Agpp1i
88k3S+9HPG3YhPfgPpQAjPnbby+UEjyge2BVabLo9b6GFI2+RxhdfbvHIWiXZx5LmEil0XENo1lQ
PwnslK/xEgJx5iOpcegQG//eBd1ludgR9bViKRaA7aogAqxS76U0B0mqfeAXiZHorWaze+ogpAwp
iBFhR+eAzCj05roju2E1h4Ahvh3S4tVaw1iiA9o+aaiNuP2fx0ZBZ/+dH4uUSnnVHI8ifv4esSWk
nXyCWF36/v2+RG6VZM+HM3TlWCwDZs0ODUXz3pLO2kTz8vlRnqgcAhDwwMgG9L/VWGOyZs3sXXhd
LaqkA7EPHdqMbLtpTZ1wDwoLy6JewbazbMa4pxQusLJlEqLp87sMrlWCvFVjJHo4bcwIJeY6WPjX
5OTgE4s5yZsZuXKnB9JJe8U9bNwcyJ4z4giQC3emNPwismHVO0AkPRSLMlAiS0rU8Z2ENqIKYnT5
4SrNTC5wQ4dyLbLOqF7a+uK4a6tPfL7hOAJKeULQ0WeBBbOZ6gAdV/fX+iO0rBu8XH0A1djW5MOy
Q9Llmp+oL1crvIRqHn3CYWotRP56qbUtQfeYpkdfC/Ry14aTwqXeEslMz6iekJPzSH4ns2Y/O3V9
LHjjM1HtCQCE3o9JcKQeCRaqwAFLlKgudm0OXgyg17Lcnpoc/wUMFIBDVlb37R7KPpmkf8aI7Y2G
Vp/CfgygHMpBEawPaX1g/gQIFYM48MKd6Ynl0hsQlO2IDluZjJcwCZxyD3evXRObMfkXSGZL5dOS
Uh/7GbwHBaG+Iu4qxEPiwdP8nBZ86iLOlktBGmd896BZc0KNDLTpXkbBR/HLwxE6BlWt5JBVLUJa
MFjoeH1NV+cNAdBh8QSlaJfdw+aKAAK5QPLuuMhKa6DevpQ2BLr7ufUFW8BfyDjGmiofTabuUZ0D
fWe/ygDfHVkha7wkN2TMSkYNAsNUshqcZuVmTmY1pDzq6vX2NQaxxmuYH4v2KugFNCja+Sb6llRD
B03RDrSrhINZ/xcrihZkt4NufghL4tA/lkXW5dvUZUgiKg0Mc+O/fYSxfzRaVOYotHmkE/YYelyG
RqQRoNciqfdg9j+4QNOSqibOrMMyfYmWvtjXiuLlYupMFqUpRUREcYVmZDMvrSlQS9yxB9kXtBoB
8C411IHO6B11+E0FZXtg6bPtOJdBB/40CavvcejVMUtXtchKALTGI7Z4StNrznh9yXY6fOmg/OoQ
jWxYjq/ZfCP41VNgCc+klZkwSQ9xOqpV7YIQeGNrbK8h0Ea3Lo9XsX67NFqx2fjzMnsAoEDN9nPz
4LAq2qd6AK/XhOYCoXIXvvsTYwHHlMcAihlTXfsIqiQk/cQsrFkRs9hR8xBJL7Q3esk0ybfz/vjS
nx8+iln/GpohFi8vQ9oOyU55A3tq99eXhFdSBQMiiyLJ98/b373AP/2QyMyLwldKMUkLpZaRenRc
2fYPahd0C4RXDGNKMDE1/WEDHuvQUgWjDj+Ux0VCHI/s7hyryh9zyz7ucN/8/EVIjrMIZ0OC6LxF
T9VMx78Z5CJP8mu+od/ojoXDvHgQNf62MhOpWKnN08ExQOS82Rxqd0cLhal54sfyQRdorbKKOo9l
ELO/Tz3ECe1dYyck4krQUdDLSohEgE75iLo9mjwcHhcyjGANw/YB0el9I6Lw8sXm0bwVws6rUAI2
hKhhnUOeUiFSmXW7XFheMa3c4Z9cOO8jdJCkQ4mOI8MflsRke0oxUnexj/7QC5nQQJCoKUwRnO4S
hPH4pe5lm32fIyJCxsjeNsr1Ry+a5Evrshtm9Hnq06kcdbnU0cT80R5Yc2rvNVZE6/GpgrtKUs9W
oLZG/ut4Py7rYD/CrIjyGZNpE9yN0GjOAqdsCLetiI6Uu5IDbKNDfBXkdrnoGE1cAQOWhAOMGPUC
peqSZQ+jjm3QSQctl/fGRCb8g6IIDwxL3oXAX9jyK8QPZ0aQ6ok2kWB9vXR8EdFeqPZ1vBIoh8IZ
XHOIflZwwO8n/JyxTpIZtPkxAY2vd/rWHFJ92TBAJu546YUwSlFdeoAkc4mcedz54EgH/4SmBc/q
jjbT3radEMVlLrNEpn/ocW25V+g/Oz8EZnt20bF1dAbMRpApnKQANuMUZ/dCKLCXUnUND8YtimOX
EORdUjrCwDs2wY6Fir5vOgnCGgyMPbBoX8xak3Hu9KZL4/yCG1MlhVyx2rBHxheZh1gxwoTjVroB
CjetnqQhZtVbGogmQDmiEB5eYTqKxHHKKQ+s1lApmk0tPPfVEjx93OLlrfT93m2SEiz9zlLkPW4T
1syBKH3qUc6PqWBYOZ4GoHfhvsAmUboifs9I4jcfZai+GNY/Akj4y82jma8L9ZQg6IOdlhRrTLXw
lZ1LZ98TYsijM4GukcsxMOtZiuYcLn+rkQz7YyGOOfuOgBSgEq5ZhK/be17+yVvIdBctoI1O1VQw
nkkgm4Aa5gAbi30WChfed456BPmdjqqR7TQmEkCmozDbIoy6DO1VbEICt0eE+zDK8uzAJuIakyL1
4SkdpPAZkITt4Vr9oymXtogK3gsCo7XkkocnDzLIBdRNViLIY+US8fE22fV2BdOLLs9+JSKeSD2n
hCgmMHiK2JXcmZZdhbEpxC6N0SDwaEPJIQPuwmunM2RAzF8rn6TC29xKbW8WE3r0R6dNDOPa0PLz
RvB3SC77hYbNXCs5otn48mcyGkhzdQZiiXj+h1XSMd588REiMqMYQ0p0BsD9IL9anjB5kwNhGSTh
MsPSyxNv8vbfBBRZtraiMAZWcyGyLBbEG/iqASGkON3Ug4T9Zgme5knQALXGllDt6yKeZriYlM32
p7pD53DX/TaQvUzxqz14ZRuVTcs/7KIb6PpOxlV8YQx2g90jFqoxSmW11wKGQ90+zQ7vmPfXuuqt
MbDwl+jLvHceLdJJ95p4u75bF+oQi+SOXHmkl/vf2cOdCA1IMHBi1RdAXvs5omwdMq8GqKEYouAP
RMGMLubi4iw52qcNlDW7ImbNusLnGFQr8JhGC8fbIqYSPxklgg1gedX2GheyXvAQvrrlZrFwuhwD
qsOJqwmUYlLXK9Hq5aTquiKkXPNFiJaRcEnWPtDqI23f3UPwgpHEJFMZo6R5rMTDxsLxFk+15Vrp
MF2SF4IIbHLEP477rwpDFzzUIYZB/+GnG9HTI0DbhQD19Adz6zYTJinJuoWnDreF4ZaNu1u1qjSp
2U04ZFmWJhnqwCNhZTXre3TSgBjSUTpf8nma8pYP/w0l0FdYXkVwaJUi6JHl53ViPjEkkbtWbZEI
uEkQa2oNmI6bszGqiVjFZ8BuQkkHkJGGT/as0RcB1KLcXstZR1AWrIe8yR22pemmnLvySHd6ZbLw
TDW+SRVlWg0jiatJuN/AZYvpz/FyE699UiVk46QyX4sHQKtoy0qiXZuRRGMQgv1jPHQoeG9CQttu
QxQPKHcIlcoTJy3ADSQqqjaVOu5KaIYfXbSzYNguTcBP84WysCnvU2KfmdJxRC4MQBgJmmSZsvco
m20ykk90BTzHB8tGH48lPKZRsO6dZMGcFZTuWxuSm0yBuvlWMUj+xkXFVjRffP0k/9/++0GRVeuD
XWhZQ1MABvtVBBPbY+kNFsgHs9dK3WgzBTqUWqMFho6davVhp1a2FvNY5Y16GwOGh0rw/SVCKWpq
+qPOoSU2yeN8cSNNboB8rC2lQS1F7jUEYb4tKCPBBlA46mRONI4ZqWtDXOqA2d6V3Sb3wEDnh4gN
LvM5mhXPGFj5Hg5jdK3AQe1efo4uJ3dSl5lRnzDy76ukZ7vywbtQFXOu7bVbuzlIDc7liUuT9Tbj
pfC5w70GHZqSIb1qvJqeAIMGpIbCPOB3wwqF4wlBdQgB/qcMQaE+zq6FO82VBC4VThnxC+G5Pllw
LqoOmH+fFrEIey68tgWE8xsCuCCW5cezYNLFn00gdrFfUCqfjPjTa424eSTw+dUH+7C6c7/VNWum
gKK5uuhFntYqkTjZg7IEL1RM7drElf4F7OobO75mh1xf21ByKQxw4cSbqRGL0GsuzTb+GDKhlx4v
5xWwJOnpQ8oPbcW5tU2Mn3a1H+OFzBCoqysvx9jgFaZ1ZLql09KBpj/K8dXfLnsEcScIbP/8vSrr
JLANRIDMPZNQudaCUDVm93FUMmzFNX43F2mcKgiNvp0LW95m/rTggab5mdlqjzoKYX/BegprHQk5
zpfeqOFRR56ho6apJCqtNZDqa6a1yZ3zD23ljoNurNgj0OSgyH11XtJuVBQmGk/fJqnILE2lFI6I
9xObzcI9KN/wB/7wiYntyXx+QPP7FS1GBO6xeXq5tNk4QGVRHklmEzYj/UvgXQFhTWxrl7LgxYSr
hLG+1Wyd1/VMZ5o/ANUbCE5Z4cN577mS5U9Il65kmTwVxxx9S4YKzR0QtJO1BH6A/SatSlsDHLrA
h/4bdblmlCVkxsdATROTQdXpTI3VowAdHjL04vCabe4UkD/ku7oAf7xVM+YBngxCgH1fPZpk3xcm
l2CzPZ+tPArfmWQCeBS/oIX2K67IEkkXF9SRooBe7aNqjOSqUk5TYFvMm1TgsF58XQ6Psf5g7nme
7ZjZEVhwI5D0qHVERroiX17kIUKm7kqEJ/MwP6Kb2v0+R3Q0rQa360pa5FIFCpe077rn9nj2kCVj
QH1KPE8FSn0PuDVfsJsHrZvy8+UfasDstXJoQi5orcvFn6DZK9rsRxrROiRFRaG6FydQOq+IgpA2
ACQKm6TPeFsH6zRCu5tYwu4Yp/a6vi97aIOSp9O0oqR3vb3UlKE2DY2k0tGonY0g2cNBOCRPpL4p
DIVGKBNxaxmN3gWXiiI1apHapdGDc9Oe56bEmLqYEG0Wb2jER/cNCHAULBUg6InXPNTlZduAuUFp
ke612anhCn9E9xneIYYXWs5rWhX5zu0S+AaOikvQLidVctGqK4i/Dh5xRiFXgTkg3fVy5Hz55dGO
IK6purSFJ7GFqfch3JW29UTlpxRpcNAuX2oDdDNOjJUP7iq6blaqM9NrMDdyv3NKTIH8hJDRMTI3
v5t4EOxBQSKld7oV9kt68LaIziKQR7+G8fpVsG0YXHwsaoUlD6UXuKATNfFbF1SRaA80Z6TOqwD7
Um6AIVRnqhIwSQPu1cw6seUyqxnFS8rNA9DoKPLxm4yOj6KvfLKOxhUQZAOPwTP7dW44N9M2JJJ/
iqNF52buQ6tAQdDJw37HJfXJqyXB99I5ly8fXawvBbEESlv6twF35pHOPhSG1SxFSMSd9ZePJ8UX
Fe7WRfBFwjzwdSIJaGDBHd7xJNAEtCT+gwplgjxOeMOcz9I8Ji8aRs+l04BZO2rk8Nr195Mzouv1
FbtWQBWW51tyPG5UMwM4tjoKf2HZCuUOyEJCWTNgqXpHHihaAAfoOsHE7BiR0mQkIpPetC57aFz3
lbGSS/0yMwhb4k8FQUSwBglIhM4j7yQeXDuQQiLuIrIw80lxoZ82iz1GutgzO1rofGXHStYCgjkV
gJOzx67iyw9J/e85BibavG2VeZzpWrKxrylwIJyRF2MZ81Uqt0tRIhHJVLJZWkJ2QOFhaFhP8rbq
IIFp+N1LFw9yOnxMrigwuPiZn9eAT/pU4yOlAirT+oYMuVQughCYyJEpMVAdex/uMhC/Dpov592a
va3udrTNMo8tg/G4xxxYnKivrytnH5dmfcW5v4f5ewR/6y5r1T/sO8lluQRw0VBj92FoB70neubP
f9a03WthMKKcZ1cvaitiJnTVbY3trClkdtueAZP002P9AS68Q29VvF2kCVPNPnCyr4+r1sS9fGVt
+Po/60C30T4p67u7AhG/GvQYGTXY8mJ8geoFX1PTpMULmLCIK/erVegpYHCfHxAMDr6C2/uLuyov
uA56e3YWLrYB7QC1L3E/zL5/oldU1kufj603zRJ0HrwB3C4ZqlV/StEr0anS0xFNANUy27DlD1S+
buUW+IAtxb+f4Uvsc5p50kF8h6EbnCEYb+bETNnJJj7aWZdW0G8Cp2hm8Y5ma8umvlJcWTT9haOA
owKMVnJQ4lfAZ7syL0sBSd8jicUDURrZmjZoctluLnAhdVG8TJsaEHpS25agXvrI6UdMY1XEW2z1
niLozebiP2k2LmU8nMh94n+PtHsw/dGflfpx+Jz1iDySRmWl+px0hmp4VPumbRKn0I6TTxqdK06J
JRoHep1OtRyr+UxVk/TBwQibwwZdlpPTvBbyCN9aUlOceLNSHO7vvEmOKhhwbTatzQ6NENbhDgrV
51Ge7xL8sX7MddRrd7uGGI46vAGKwxrKp8F5S49J8CRErrAJR1PiWYtzF4WZabJicWNo2LcAgL2u
ibsrILI0MbA7uwG3KOKgVMXPzwNfXxiu/6cu5w531hxG9fMiGjW5X8mFd/7Phr1tFCoH1OJ0+GFQ
LSQoqpaqZs800JCzksX7G8H5JOOQHFxswBGMh9cKaCTE5yx+Pp8anWxnVKycSPbvJ76F4xU7D3pF
8C7B3gzWRgrvfJaqqPYNMgbAKs2YK137kT2xTukStHm4VJ//aK2iRlYSKfqANiJiUHRrAFd/W/s1
NyKIFVMb3cqkkhsTKxkWVU82WVa129izplRqBmFYsKZ8yuG3wcOG0vK6iW8s+5IIAHbSCxFoyLSj
KX2S9pmEtPIvsyhigKWnC2aTG3BSVggo
`protect end_protected
| bsd-2-clause | 472a5e431fd561334b82a4ec5a74ed20 | 0.951956 | 1.819912 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/bp_predic.vhd | 1 | 7,855 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity BranchPredictor is generic (
async_reset : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
i_req_mem_fire : in std_logic; -- Memory request was accepted
i_resp_mem_valid : in std_logic; -- Memory response from ICache is valid
i_resp_mem_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Memory response address
i_resp_mem_data : in std_logic_vector(31 downto 0);-- Memory response value
i_e_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Valid instruction value awaited by 'Executor'
i_ra : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Return address register value
o_npc_predict : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) -- Predicted next instruction address
);
end;
architecture arch_BranchPredictor of BranchPredictor is
type HistoryType is record
resp_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
resp_npc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
end record;
constant history_none : HistoryType := (
(others => '1'), (others => '1')
);
type HistoryVector is array (0 to 2) of HistoryType;
type RegistersType is record
h : HistoryVector;
wait_resp : std_logic;
end record;
constant R_RESET : RegistersType := (
(others => history_none), '0'
);
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_req_mem_fire, i_resp_mem_valid, i_resp_mem_addr,
i_resp_mem_data, i_e_npc, i_ra, r)
variable v : RegistersType;
variable vb_tmp : std_logic_vector(31 downto 0);
variable vb_npc_predicted : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_npc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable v_jal : std_logic;
variable vb_jal_off : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_jal_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable v_branch : std_logic;
variable vb_branch_off : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_branch_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable v_c_j : std_logic;
variable vb_c_j_off : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_c_j_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable v_c_ret : std_logic;
begin
v := r;
vb_pc := r.h(0).resp_pc;
vb_tmp := i_resp_mem_data;
-- Unconditional jump "J"
vb_jal_off(CFG_CPU_ADDR_BITS-1 downto 20) := (others => vb_tmp(31));
vb_jal_off(19 downto 12) := vb_tmp(19 downto 12);
vb_jal_off(11) := vb_tmp(20);
vb_jal_off(10 downto 1) := vb_tmp(30 downto 21);
vb_jal_off(0) := '0';
vb_jal_addr := vb_pc + vb_jal_off;
v_jal := '0';
if vb_tmp(6 downto 0) = "1101111" then
if (vb_jal_addr /= r.h(1).resp_pc) and (vb_jal_addr /= r.h(2).resp_pc) then
v_jal := '1';
end if;
end if;
-- Conditional branches "BEQ", "BNE", "BLT", "BGE", BLTU", "BGEU"
-- Only negative offset leads to predicted jumps
if vb_tmp(31) = '1' then
vb_branch_off(CFG_CPU_ADDR_BITS-1 downto 12) := (others => '1');
else
vb_branch_off(CFG_CPU_ADDR_BITS-1 downto 12) := (others => '0');
end if;
vb_branch_off(11) := vb_tmp(7);
vb_branch_off(10 downto 5) := vb_tmp(30 downto 25);
vb_branch_off(4 downto 1) := vb_tmp(11 downto 8);
vb_branch_off(0) := '0';
vb_branch_addr := vb_pc + vb_branch_off;
v_branch := '0';
if (vb_tmp(6 downto 0) = "1100011") and (vb_tmp(31) = '1') then
if (vb_branch_addr /= r.h(1).resp_pc)
and (vb_branch_addr /= r.h(2).resp_pc) then
v_branch := '1';
end if;
end if;
-- Check Compressed "C_J" unconditional jump
if vb_tmp(12) = '1' then
vb_c_j_off(CFG_CPU_ADDR_BITS-1 downto 11) := (others => '1');
else
vb_c_j_off(CFG_CPU_ADDR_BITS-1 downto 11) := (others => '0');
end if;
vb_c_j_off(10) := vb_tmp(8);
vb_c_j_off(9 downto 8) := vb_tmp(10 downto 9);
vb_c_j_off(7) := vb_tmp(6);
vb_c_j_off(6) := vb_tmp(7);
vb_c_j_off(5) := vb_tmp(2);
vb_c_j_off(4) := vb_tmp(11);
vb_c_j_off(3 downto 1) := vb_tmp(5 downto 3);
vb_c_j_off(0) := '0';
vb_c_j_addr := vb_pc + vb_c_j_off;
v_c_j := '0';
if (vb_tmp(15 downto 13) = "101") and (vb_tmp(1 downto 0) = "01") then
if (vb_c_j_addr /= r.h(1).resp_pc) and (vb_c_j_addr /= r.h(2).resp_pc) then
v_c_j := '1';
end if;
end if;
-- Compressed RET pseudo-instruction
v_c_ret := '0';
if vb_tmp(15 downto 0) = X"8082" then
v_c_ret := '1';
end if;
if v_jal = '1' then
vb_npc_predicted := vb_jal_addr;
elsif v_branch = '1' then
vb_npc_predicted := vb_branch_addr;
elsif v_c_j = '1' then
vb_npc_predicted := vb_c_j_addr;
elsif v_c_ret = '1' then
vb_npc_predicted := i_ra(CFG_CPU_ADDR_BITS-1 downto 0);
elsif vb_tmp(1 downto 0) = "11" then
vb_npc_predicted := r.h(0).resp_pc + 4;
else
vb_npc_predicted := r.h(0).resp_pc + 2;
end if;
if i_e_npc = r.h(2).resp_pc then
if r.h(2).resp_npc = r.h(1).resp_pc then
if r.h(1).resp_npc = r.h(0).resp_pc then
vb_npc := vb_npc_predicted;
else
vb_npc := r.h(1).resp_npc;
end if;
elsif r.h(2).resp_npc = r.h(0).resp_pc then
vb_npc := vb_npc_predicted;
else
vb_npc := r.h(2).resp_npc;
end if;
elsif i_e_npc = r.h(1).resp_pc then
if r.h(1).resp_npc = r.h(0).resp_pc then
vb_npc := vb_npc_predicted;
else
vb_npc := r.h(1).resp_npc;
end if;
elsif i_e_npc = r.h(0).resp_pc then
vb_npc := vb_npc_predicted;
else
vb_npc := i_e_npc;
end if;
if i_req_mem_fire = '1' and r.wait_resp = '0' then
v.wait_resp := '1';
v.h(0).resp_pc := vb_npc;
v.h(0).resp_npc := (others => '1');
v.h(1) := r.h(0);
v.h(2) := r.h(1);
elsif i_req_mem_fire = '1' and i_resp_mem_valid = '1' then
v.wait_resp := '1';
v.h(0).resp_pc := vb_npc;
v.h(0).resp_npc := (others => '1');
v.h(1) := r.h(0);
v.h(1).resp_npc := vb_npc;
v.h(2) := r.h(1);
elsif i_resp_mem_valid = '1' and r.wait_resp = '1' then
v.wait_resp := '0';
v.h(0).resp_npc := vb_npc;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
o_npc_predict <= vb_npc;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | fe5dacd0563686cf0c5d83bc93fa97c8 | 0.56881 | 2.901736 | false | false | false | false |
codepainters/vhdl-utils | tests/t_clock_prescaler.vhd | 1 | 2,342 | --------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <[email protected]>
-- This file is distributed under the Modified BSD License.
--
-- Testbench for SRL16-based clock prescaler.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t_clock_prescaler is
end t_clock_prescaler;
architecture behavior of t_clock_prescaler is
component clock_prescaler
generic (n : integer range 2 to 16;
exp : integer range 0 to 10);
port(clk : in std_logic;
q : out std_logic);
end component;
-- main clock
signal clk : std_logic := '0';
signal stop_simulation : std_logic := '0';
constant clock_period : time := 10ns;
-- outputs
signal q_div2 : std_logic;
signal q_div16 : std_logic;
signal q_div300 : std_logic;
procedure clock_checker(signal q_clk : std_logic;
divider : integer) is
variable last_rising : time;
begin
wait until q_clk = '1';
while stop_simulation = '0' loop
last_rising := now;
wait until q_clk = '0';
assert now - last_rising = clock_period severity error;
wait until q_clk = '1';
assert now - last_rising = divider * clock_period severity error;
end loop;
end procedure;
begin
clk <= not clk after clock_period / 2 when stop_simulation /= '1' else '0';
stop_simulation <= '1' after 15us;
-- we test division by 2 and 16 to check edge cases with only a single stage,
-- division by 300 checks the case with 1 + 2 stages
uut_d2: clock_prescaler
generic map (n => 2, exp => 0)
port map (clk => clk, q => q_div2);
uut_d16: clock_prescaler
generic map (n => 16, exp => 0)
port map (clk => clk, q => q_div16);
uut_d300: clock_prescaler
generic map (n => 3, exp => 2)
port map (clk => clk, q => q_div300);
process
begin
clock_checker(q_div2, 2);
end process;
process
begin
clock_checker(q_div16, 16);
end process;
process
begin
clock_checker(q_div300, 300);
end process;
end;
| bsd-2-clause | 7ea21f18ccbea614fe6c6c5799e09479 | 0.535867 | 3.996587 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reg_module.vhd | 1 | 87,148 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_10.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_10.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_10.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
| mit | 34ea3486b59d3ff20be78aae58dd1f50 | 0.43884 | 3.702911 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_status_flags_ss.vhd | 19 | 18,129 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IVTcVKz+qqR6KelbIxn6hKss0fyLwIejVgwej+TN1ST/vU6syUW6hxZyGugx/VRu65UT+0QU+88C
5SDN434/fA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
W0uuDuJZlgdtFvYMz+doOP0vwnGc2SXfLiGH2a5FulZQF1GjNx3fjKnarWbbCm92Rksm2FFSGof4
SgtGKAeCq4Yz/Vqm5xuP6QHmdBwou49vkKDs52HUud9c3EaEYtdNlkb4+DCcueqZu76yWN8rf2DJ
ekmu+LGiL1dmyzv30tE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Da9hmR0COgf/nsNRjZU5mrjIzRjN0/ufJQ7crbPh82WrNgInUm192216ks1D/Quh1gQ5TieAOChY
26CHNdLfPPmjLAo5/cOIRsIuy2JD7JAEIDFhFO2BcC4GrUAhSArSC4/9FyqXrVJUKuDybwv0tWSf
qpHjmJw18CiVw84ne90mESBOJ0fW1ujayfbI70yaGaFjJM/DPm4Lq+TC+TFlaimxpTFNrAUzQNVF
VSkf44Zb11D7if2jaL6ua4hPGgYpPcisaJtcEYpURXS8Lw+NjmMExnMpUW39NqnMiTEPom3YBwag
JMKm6/EZOnBvVc8SljH7y69fXiGUXgw6Z6POkg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
1/llP5a+sEX6Ky1I5ak8Fr3e35uMro1bXNqkrntPBRVTqUhQPFl7wfr/6Abnu74l73YggylsZJi1
1Erm6sC9oDhL9IE4pENErrDQRZHuFnl4+DlguLd11swTlNfBwauGoCBXbTtZ8+O70UI/sRzXqbZc
NDH1RywyQLhMRmSOjCU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OI4vyCtRzSCtjYNsCqL7rYkcvPw30aumOHoxNPQx0NU0Kc5/zvGo5pjE7sDqPsv0b00mAjKXUE8e
pVllo+uquegdt9Smrq3DaiQC/9hKGiZzOG1rJH9JbLcfPMXDGpwm1inP51BNgkQwocfUEAVndeWo
GE1Y28I9gt/5q5Fs/OUAX9cAh1VoS1OcnYX2wbgJSlzuLqnGWRIxOHl4+NkNkBq5Q3Xm589bPnnz
m+d2tBEPyqaCTvb13xXW7hqIf0ahuv0AQTuiClY+KmF0GjLdJTWJjDWPuRd9WYhybCp/lrgDnhAK
cnRXJnAOwP1Vgr7EPuoyVc3UkNsZTxEr3wrouw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11680)
`protect data_block
tdwK5ZdqC1lTmlGUnRR7Yt2xC9sSxvluJ8GKoF4/PBy8cuepaO0uf0LYKTkNKeeHpd3Wema6aqcj
srLXXbWWz4UGB4hdvxBJtYqwadIfgGECjDVXp6uQrfP31vtCOA9+FmtMLs4FfxWATHXFb0PTQw3G
isIc6KFtVvVydNQmy1ZLPS6jP6h/lwbX8n/pnSL2WZXvrD1jm2jXxu1cc7g9OeoazdHUZzZvFix6
FgwGMXR3s27tEh4f9m5V/ihoSjMFOz87/tU/DB+DnLn7awHkl/wkbteyhhrGIUjKmzrL5F65y7N1
pUUhXTAj3RgbYQVgjkkS98xFL2X8ivYVa26+AF8gdleuWtFIrRpG06eNFIhnSLPq9gGIspbM+Ihw
+/YB5GhQ/v9g9jT6Se5RLKCmFbky/wpFSjcJLcsaM2PCKL11Y5V3YFUJ6xRDmvlC9enre5fbsqYr
oVKyuImicTyq766kky/w1DFftyYF+uDdELG/BJXjAVf5Dbqkuj+h9X2mDZCvDHV5eEOZOBUHv1HM
w1c3bMciXl6IirH9ceKXAyLYRMGE8y08oF+dc3esWGKi6HhUfyWgpLcJnlHwYq4Fb+giAnpcCxJ5
NZ8i4ehC4UWAkjVwL8HEAM3nIoVkqkkb79Dr+wwQBwujGmKHgN/mXEPQ7jkubQycywuiD6Y3xl5O
hsp0166L7MapBJIdm0w4Up1QZhpSk4tE1lfL13LNE+N2i529RDBoTe0Vit/LBVoyV2tlqhw31Ftb
tfUyjtFAvv8f0a5PcqK/r7TDHRo+aMD31KHzmO9pF/Nd9rA9wfacjLHDd2zBvByrCYa8rpHlEogh
TqP0bTw0hOmSogQYpzI0Ox0Gh+koPbCM+Fbmr8gLyYJDfJ4lpSryewcZChK61FlkGTR0jkyAgCDW
S6A0OzHQ3wMh2yg2fg0if+CX6+dD3C7PreGY4GCn6i+6DzsNTIqKKwZ8ddQnOevzjYMS3JVkF4ZU
3UbUrXI8xS4Vtvm6/RVEdqf7VlskrtbintlAQF0/xfYcL+ADJYcaijwDMo9LQwVF4T9HPNvX6s4p
GRr2VnS7WN4QXsCIc5y8zkTN+hROBRujh1e0YqNF/LULtt9SvYEbBQo0m1ujOQZYz3R0pZ4Jm1k9
qb5gVFPCQF2HUByXHwB4mV8MbvcJgtal+jQe+9X8pJf6+WV/grrQ7Dxmpl+5uiY6G9wP1ixVoT/L
sYaHOCQ2iKleCpslejQNJ6bat5jnYhNGSUAttQC1mYqXVxdcpxpTqNYsGnrEWUHwp4FJ4aqV79BU
NkfURkorAehgVCWZOc+z0DbGaNTvnuc0SqWJUgoinr+JONjWy1Eoj1uocEfTE/xGj+1r7WxQ3S9n
r4z2TeXtY3+VbZNC1kdXBHWUx8y9O80uGAHGLzPYK/hO18WjHr0tDjR+JxuBNXIdU2LCp2JtiX47
+6Z95G9t/6N7etlQRiG/eUyv5iEKWL8PU2T1Vo8Ny2sqfbwJV6y5zed3iRA+CJQYI1cv3mzSomfL
QoV0R/8i/678Uj31aTt8tzoAkd7yXbKXrdb4Fc/9k+GSFctBLy4OhHUi92zadkZ27B2ZaHudPUSy
LqRLzpaEf6Ej80Ply8DFJInCAVJo/3GxLqHfRcXA3oTyzeeAJEf4GplXBDcJpDYi04EdJt525a9k
3z/hew+ozl4W/+N84qIUV3JWDphWSPrzAJli/k9N2BvayDt3M873cpxowZDtdUYThQ+b/cotSjRv
HUzVRlrHgRQhEtpWyZvoN+Nao7LR0jbisuEMig5vnVvJ8UDkXKXHCfDHSWpLDqOtHHQ/iDvzdfUi
R+ftpt0VoWiU4lqgUpBEHEto9EdtXy7Vv4EvB9I3AuC4Fc2XoeH4ZNsWETe2Irh8bH668e7m5mmP
gUjc3OxnICCMeCyJQwRbIAxfZ6HHBlawdSxYSu9sTWnKiC1JOebMMQPnwdYx8KL7yUT3K0lvLGkZ
bjuqSRPMLIrOHb4/zPbZIGTElJSkvpras7Sgdh1Ie+Qp8MrGZIpGfccJ3G2tUh4OwdPcjj5xByjk
1l32Yt/L1/H5D398cXhQwytU8tvUvr1UN6AtAeTr6YWgAkv33BhicVQKtpy5eLuUoiM+AWofiIJV
Y7ydKSU3x+lTKPM3DXsOGlPx3uet+cCCXQGf6Ncf6WCyCkOtBi3XAbmUYyrnKih85SeWGK4WeV97
m0xXU52EHE/a6wtXNoZBWLCeSpgi5eaAtejXs8ZMeA9VvHFxc1VTC0HBoN7fuyTyEl2O8vn+vmrO
ixjaZAMgf6SjLBBp13sGV82vInPGC/xOLSNE5HaM9CvLDTKDo6MeOshm4FuMUZp/2b/B92n/Tu0O
KGG6iMJmd+khGegWrxfBy6bj9qITebx3c8pB8pi+Ld09AYi0DxcZ7OkiVlPFLZTlOHL5IejAwE6L
s0+T+QBJfSE69uKQH42canp3wQzbV0w9/RxRw/LG5o9xV8G5NBp/qU280uxfYyOeUB5jwrH06wiP
6ZWXD16uH6tvqrAQOnf8BETBG3VvY5KSnNQbPc82ZkuP7TciW1YS+iVi7NnprIsN1Y7UoI49nClN
BuObMUSDlCkP13roJ/kUYtsncaLYsI5O7PDku4/Tcm7j1ruauBlN1Y6ihcAAfkpE/AbPJsPfOZO1
JEn+wU/aIQhApPhMOPOvCnwwkQd9e5+7AA/tEHeBeCRFl1N8SLHzyOOfrmgYbH7lmN+CD0gO2m4U
EIwdNqCNLa082b5GcPRaSxMyNBbJO+dzWjLzH7nMYL7fxjzI2JuULbcyW1zhDSKNmSi3+1fJxO2S
0C6/saTsbW3oMLxIR5WSd4vJoHrMla6DAG4mfxeI/pnkKySFvtjb/ZoiOJTo80pd2Hh87lJyqBDc
gr/fn8ebTBf8snksxjD/r7KfaHc6Noe39nEnqS2jEt5s8dVYADEQi3ZJsBiSusyKLx8Ca5xEo8Fs
VIGdKSndheyin8lzRyI02gn+nFxdFb4vYDUwD8e/CzG/j+AycPxuv0MgnQKZyeHtAD9fJeLal/XN
1o82aEmBu+DFrFFFW5I9FHHcTH5gQMV8+5uLE3wtNBMkAc0f5u4K8lfN+a6EwNCiJJNzpHZNr04f
5siOgdC93QlJUgruIvtrukvy1tEXmFVHFmnIiW0067zp7cDkJ+kV8n1VY14bim+uRhhgd8QZw1hp
PTfBconCg+yYaye4/NSIFk0KBnGfM5Imosz7HTJ1Ae1DHXktFmMJoN7nUV0YIqfU+cNs9JuxgxkZ
8GekY9USUd0Fn+xEusdUPCDznmp2oETw0/6eZZXhhpAnbO7CP19WWSlNmB4DKVEN5mSvePk62+pD
YMwZlnre8JlOHlyptsAtnskjaZZp53rjzhn1AofmbGZiBOrkzPcVTOtcvVm9oODXZrMpUehcdR9l
Vg/COg1z5AJWw+2UKLU91GarmI3uCMBt04ivnpjK8MhQfWe8X1GSUfxh5X7PMyvcOpRtVILp3Tpr
8fjAjwi8YXlB10XHiF4SzWjg4TG2FA+bcqR22Exag1NngU2fEdrwNPFxQ4+4h/ZqtDi4oHoBiMce
74VuASYlkc6uc+K9lTL+HLhQBef/XMnVpkJxOFo4wotvs+lDztPO6mnRki3Au64+bO6OdWpNeZFK
uc6xHJuJ/c9ykXuGXPHdMrZiDk/i7qrj79PjT9EcYGafcsj74MZ+3TPD6GRAi0E7Gqsl60TpEWwe
Z0zLz7eBtOTosH+eQ9K6ClLpzlw1gAt1dz4Yy7AjJfKl1rOhAkiLlcm5DB0G75uDnRG/ppz78m+q
zw01AAqC2abL7ukVT7MKFp8qEQ7CLWE5E3Nhh9HPeH3HuM+Y05JWFWjX/ok6MiV9DH/HuI04U167
XbvZk2wNxC7D7KHsN3LfNotdKykG03cRNqkScyqQkXyd32UE58LxXLzH5LHGedfOSEZs5Z8KM/yh
XgZMZmYpw3iEXhmvPtkwLKyQCdovRiRkXqwJ2jEQg65M+Sfwvmp12kCobVltApn442laaz+4yTss
QFMPH7aB6zRpYWwh0YrdMrNlRLQAZ+cHmY85mZlHgp4BV9rPdZCimo6FeagNZ13uKjE4fbz7jieb
/oWGqv5imXMgD0plwlMWva01WxzWdfShex8wtAdVZtk9B47MS1Xh+zfLKTRo2RlZH7/pTDmjVKO2
3crzXes6nMR4ttwVYs2Y1hXWoD0o1PNoSr+YLN9a9wpJ0INFBaVHhY+GbU4fJXxDe3ydi2w9rMnz
5reFJdmWxJH6HBVJVcFOOgxmHh2xm2rbX8rx4obLfMxNzDUXJniKNUFAyIwizmw/0vMzBvdTPgas
bbu1keKSl6ndJF/x/p4yBNUo3SZeElYMU+Vcry98h+dbiX0DDItgxVEGrOPNecRXI4hgjzUpu78j
QVhGwBmysFD9beH27ubO98gvxNtgTGFEZtlfgOzZd6ZIYUoMeJWmg6x5Rs4YUzrEIah5lAnaY5+i
5txSY9PdnKARrmlmgvzXNqb7EqRokg3B+ZAakmNV9LQfjFTjKUB29DhGhQ6oBKR/BG7Hp5Hg5ue7
lBCAc9gAk1qneV0/PJfPhJaTBvGd4j5RDTxVZb7ABVzAB7a+GF9Dbm+c5U0HCg4uA2z69SKfhaJy
IP02mwiB25hfvtR0zfQtser5hHaD5ILBZ7betTurxvyUcZ65j8YDeuaK8oI4qK9uCU1Er794xD8c
htBXMGT/fQoMvaoTrjnoTmZuByMJPbEYD42XPCZZf5M84JpJ0GaSIq+N8n1bQY1VH8ypQ+dM3Gz1
0AQPaD3owA7yxz8za+WzFmLOBwG8y/01WZSqCcFGqXSJeqV1iepVdmcv5OiTLLPf7ObUV95TGyKk
mJDofdo/tZpKkS8vajnpcsww3NE4sCT2Fce2ioSOiSmee+9APRhlCEqv3B5kIXcxKk8ZvCj77OXN
yqJ2J3KigOUIs7T6uBoWWS0UaV+in8JlPGascUK0swMiz6HTr0u89sEuX4DI5TJ3S3CmQrmpbLTv
yeczJ+dnKzpn9JpM787xOqWHJ5DL1t8B/fnhLW7DSNB8xNBrufFISN3qjvSNFfBPUlCeliUuho5h
vmQq3ZI2I/nsNTkIQkq4285v2e31q2XDU/W9mzdXFLL92IvLrMx44y7/MVWGPfs8SuZ043BEx+7z
JuofAF+h2dYqReLTQySbcK6cNNnle4bCv6n9EI1bSnDqDZ6p9WMYbmF78t9YssQbDp1p523iH7LD
XXs1dV5FDGDSKsPQe9iZ3Rk6mRIUkmAqd0fmqbHGTsD5NNWV8AIUOcMN4fkPmdL/e+vwJPl67gzi
kgqCRLy9JPgQL/ZLC4PI3Fm5/QhpJ9SB5oyp2K2J+iOxuWuSoUEGdnUi+ot0qEhvrZStoygO1pbc
CpgPxvJdHoTNTF2Hy8QLhqTEvEOClU1eVUpgRDu6virzeEhnujIxeCT31Le1FkEX4oHJTxMCUd6Q
ItqZe2MMRS0Pu9imfDqfDHD7wIXukPIXG5myKGg96twbGi5SfbVD+3vaHAhLGaLLSQCSASSNQpmh
68fwBVCI2IpA5nt7/v4iWcdDCBRyW1koCCXRzgGm1SNuDClZiIGRknhJvYPFbcv2n9K4GXpw9fJm
JXj4YwXv7IBxckPIn4ys3M4Mu/cZCMP/pR4uTLiaEk1ICifLYv+KWUyqe2UUd6W+EzWgzs+1zQgI
N0xN6JEaMbxuKQ6sJQnS6ABIGSBIywd3XKwilalcK7iLb5ZdMeagPSh5ndV1GejolHZwMDXFz2sF
lIUpKB0mCh1r9gMToEzmsl+MVD3vIeMF4LG6799vpW8euBMl26Xmi4w4V4KsWGWXXTfLNy5kmlM1
w9bPQiH774bK/qLbxHNBJXxJPKK2pJt6jKsWNh2I8FzYnzoCrS70FqVx96Z3B1mPp4JvSkhvov5j
LpgCegNvsqdESlKcKsU/1xL3evCXjTjg12XH0zljhMOyGpAkp+PvEOIknslOE8q7hUpF8FsN5gfy
ghQ539vTsy8TJVUdv30xv8ndHQUHhsqcozD2MpdffZ5PhlP8Z2AE/2vrRBZWwXMFD+7xNLQ1fMEq
63aXQbTsoG7EtSPzwWE0CfdLy/oJsh+I/6VQpcdOJDLcg3dP3G5BXIS/198czt7OR9G57o4araOw
E8ilAQNi2t8KGiyyPQxbTGT60bW+a6pdJ8IEqJ8Nxt435Mil6nXPvJ2P8WaZdXVcrVzWVcJjMzyI
gEcQKw4s8VSIO60UYNL9FLAZ4rEDcRgrmjpemAUZEo/EqpdGoj4WatITG5oOXiTdlYHO4gF9nIaL
OgIOG+W/eevmoTCfXpd674+Cc+E1rL+whWlCGiwgX4m0SCLtyQe5ZxLjvbLNN7komRpvJEA16HjE
XpAA87vDt3Qn6BmNQH9R9nk+HYNfz5oIiOgIcwnfcTGQkUBR7xY00CmnGEoaie8uOQ2v1D7XxNOP
iSduSmdD1D84/I72gyJ569IqJ/ngJrkWT9kv3L0LiDgVxlDOwd6vMM/sbjdpg8RL6hBsYndjKc5N
fKXogtYiNcJvqEZTOQnfsoku8cj0jU4Z+g10qx4jP5dnUDzfDwx1WC6LG2cL5CHqJUtS0hyHN2nR
Do4RP1nytrMUIScEUx8ymIkf8Dc0QUU85ioRwQ5oOmUM+BzhZEk+Fa04DXHmk4FzAMYJaNz0uVWr
izWxyFBFn3LOleEoj2ffNnoWWSNLZYzcf1pnVO4RSPujMTCefH8iK/fboTHDVJiLd8qkup7q1onM
DfOf5VeVopMC+WDV/7iHCtarrq3Q7bjRJyWEZWM2/Ob+tHju8S0khQplCAsOZtnUQukRvhO2p8dD
5LhW24nniWXjotqlnb4wjczRQhEelWY1+D7vXN1q5lsygIrmxRlmRNEdoPp4d8+oi0PpkpkqICOD
hNzPAEiabJRXrO1w6Y3fU4y3/AvImo8U7jziFSfYF8vBFEQdDg1S7kWl/QjP5T3QbvS0rVV5GhBn
Law4487uZ5DaP4IYSt5EVXCpSVk/ncnDGtu7vLqMJ3pyihI79q/JqBeUhMHmbOYhsoG6I3ycBGGR
o4WQhi+WknLA6UPWJFeeE0Oj+7Gi/eXFO3DeJXLUdeSelgGGff4JOX5A6GdoNyVWVL7J/+nOnlfx
yLv0HtDa8kodWTVoW/gCXKnoqRcDVVPE6KsdEbcQztH9Qgn1Gr0tnaO6QFm9HsOzxXKHjHGEFtRA
hIe8dmHyD5CW87t57sUWzkopazJPPmJViTpb6lbsR8HPpa/I6SuHq5eGHxImRkVWNZQWrWSDYRBL
rEqoABfZpuIctlEXHhs5KUqw3GP9A8kTLi9iPuCmtoDMy/OT5rRMac+6csBjwj5E7s805jITswjn
qB+HIpk0qUNHS9SozZPrW/DntkUr198/JMEEjsgqlk6yq/kzjT3BjIRefT4lYqQnrFyo2n3dHn7g
01WbF1D+td80CdjJbd4e5e7BjA1DQ3PwcOdmJ7XndmnB/LEoJUrQYF43uAt0hRSnwUE0DQZjHPlb
jw0SiD2S949P3SBdnCVIbte8U7RzH04g5R75wc47LRR2sILzn1iQOttGVfVxZbB1C+kGhNrq65I8
T4ZE+k2D94jMA8viBY1QU2geEcsEThPvqZ2zXEf89qZneBqT5dzNSifWKFqLDhxqrU0wRUq8HZ1A
7mnweEAbSDX6z2uYi54+fsrvPB9T7/DODkzTVuXNp+KPy+6RTOlgcsLT79lliaaDoaEbaqZ8+Yu2
tdZN/ioGt3bvloUvp+yNgxycdXWdFLuy74erxnPUQbHUU2W13aZnF1rQnGU2y6MPNx7kbft4PUc1
Yk8byYAeKKrpkm2BnttHk55HAIhFf2f55FxV6XWJ5UQQA+PBGg7TYXgJbB2IkjnRhzDVad6hZiw1
l0x32SnUdsIlEEUJ5Npu5GVyvZeaj1DXIY80q0AnV1R7mWFO21ilrLUC4ow1YoO3XOpZI9+89yzm
KgJsbUXZeaIg6jkxA6/9+fFTiHZyy311Csfd+gzC+X8VjcFoEQipgq42yf7Kg0W9y4FV3JY0YRvw
4PllaNT2l1nEdtwTmeEjnBz9dTSeuTWi1+UBAUQQ+TBHho8eYgVaMXKJYHl9s1nbf9jCxLOojU6J
2Mkk4HjyVSU3scZohpKZs/RLGb/+DwoJcwbi53wQVPqI8BXSsKpUcc6vT6RLMNsYTLsqy1T3sJT3
rvob6YZy9uzK4T1dGIZrxFoO7TpLluMp8ZOiMPyhJzTD0vk4ZR/c0AIzs2L774dIitQKzEvf7yhN
bgdjrXnqwN/2H3vFXKevM6qn2Xha1T8buWUkuGJryLyGiJhZVk14EtZC6TGCGLZ4Kl64ZAR6+2EV
MS8hmAkc0ozs2lU4SffmAMqEvwu4M1glqDvWWNCTxopKe0RpzxhE+B47COrlWIu7Mn/lQfab4OSm
PmZcnOcW0DtUwXc1XOyX1BVXFOWkGw+MUr0CFJbRjkmOs0hV6f4Ty7R02gFG0VpTNyGDFJJqoSTn
AnlalsxtC7VKbtZc2AhiIfBDwmYRd9OWtg9zOttJ+beFJKLOWgQmzdYTGyl+dDR/2cBZN2+lKOft
ctThp0yFSpFyQczSzwkvjPLQxGwx4JQSEgi621f7ncvgXy7ygAkrFVvY26WdQ7mb/ugvoE21Wmdu
iL99Y4slqI1Bco2o3kaHVQN1aTwacbdLr3ZssDPLO5r5NuoYA1JbINAsylLYqXLxZpt405I7RfKR
yI7XpeNTdsj3gCSguGwnPd11PoL+q2yxMK1z3HfReTU4d0aMcZ8qz1VOIyQnW/JEzNzou/r8kJlX
aqCyQ7awvcxS5oXSfJzCumacqqOSER8ff1CPrDmakNuPQJABjFwPVpClgMv4IxITvxxChdDrKrGX
/m8SpKE1zxlZKVGkk9kdRlVnbwjCHmBgP82B9I+RhmQBzFM6FGM9CSmOZ12Uxt+u8ZsywnymX8oj
HOJ5zzRiqDsW51hKwTS4B2IZKV7BSEP3GqmqXaLA5NUaf7DDJ6a49K1Py5kcUa/+eR3vIY7Q2fWg
vR56WCSUnxK243BJ9B3P02YKZK8uzAjPx6NqM9XrV2O+mx+tcVnGBkgqBI19aobooKWJYT0KQdko
/5ZK1vmjrnHLb/FwWe+pduQDKJFZMVtXUWlVW3hDu0oe/pEbepPKnh/319Xp/3byg8yEqYcOf+0D
f7Qv1u0tHa5oG7nzk/wOfMHMgrmb/PZYIvsAYzN1QMJnW+jpkSu/Wlgbj8M+qdqrXQoprkT514F0
cp3howbognf53wG/OTcqWUJM5ZGnRWlrdJ8PIIsotUml0jyaWgVBexK3dXSWQ0xZH0y4FKjxtF9a
k3CX6D1mjL8eNWHst/V6ThKwHV3ebCTAxWgHS3YXu1w096gntDZRUra7pqc61DLGCNDdiolIirtf
t4QxAIah2dTt7k+AsRfuBx8nPRGuUQKIkT8YJyQ75wqtzO0VCQ4en7yV0zH+lcdjycLeIEtmwwzo
9SahCBqXNLBXXdZLXkPDl6GpRGkGXigmdGB4G3G14UsfexLOcB8XhwvZayMR7uYFpMhvNDCDf2Be
epYiwZLfiJZPvaxXVmnkFNMnKFTcB1vTQ/QOMccppu1TW1C5PQyADHvtrq+LGlsRWDU4S0X+pLul
HLAkrFdUCrJD+IbOZ3Ftk2ABLTAbZqNjmqeVjRqRdGBxkOyE9sO8rMy7+ql9CbA/Z0fUI2rQ0Msl
K2E6rz2R36JyLbiD3P/4TyOvAoiMSHEDRsKDa5I5OVL2jmEWl/o2GrKRAukJcGJIdeiIHpzXH57k
PM7TAMhFXDwFtAuHuqy9KnejIXlhds7ZDaspLo2uVA85vvm9fds1oNgX2hyNtL81a7HVYGcU4ykj
g9Y1BcTdJzn8cFAGi+xAL+pDk2mn+Odbk+0pq55wFW6eZSMs7eyLJEIy++Pxd+IJVVPbBYRKVkXj
whpLo4PLbAnNCSd+Y7EkfZRU4zCZ1Z3h9bAjmtdi3fDiJlx1IUYCDcTyGFvXnj0RjMZLKIiYNBZ7
3RFVWY4HWp0ykat9cPvfXQvTRItv4dVt41YdWLxcmYRtf8l0eCzXYXk5QTFigmBPOfBmQnxpgb9J
2IgcV1vcbRPiq8zLEq8ivBDCog6vZNeysPGrGmUgyxqH6nf0G8matPJDvIDkWGr1E8BhENlXXaJy
N47txnqYIoiND46mbDO5P5Rs99tttkkxpMbLQylX+YkFgbvwQ0j5G61gqJmuNss+v1uW0boZhH3P
ha5Qi7FoxReMkWPxbb+euxX9Qt022CvgIO0oFQ7GjRPhowfl18ZD0NbD9JDvMpZKALV8/xqVRv2M
+1kLAyQS9DwsH5mb6fCadCRYhLKWqhTfOTfbE9d1b4/wBojJIsAz1rSQM4dJxNA7PHPo+Fy9/kyl
AVhx54stPhbDdpCxstG/f7xpu9KHxxKWcP2xmgOF/Zz+//lecrJDELZCc74l0iJtokQVdHVcdxRN
1WG4TsO8/b4jJ6vWZC0xtwHklnOFiroEvA5Nr9GNPKuKIE/SdIwfLg175JZl2+Oi3lK+M9IIOCh7
M+ktv6ZigYbzxoMf6EmIiQc226n41SD68/SVbmeMMnHX5VpMPRQschJcxkT+VQUXxUVXVjP5DHwq
JqPPYiJQkJiENFDoggvo0etEOTxIWddTKL0lvIG+V7Ge8EspEmd7n0QlIn0Q8UU5hMeIRyS4fM6v
7BClmO4YOHVvtZgGvMIjuZEVzt7dhpQDfb2ni0NP7ixw5lC9K2tUaKJ8gvHnldgVredqD02YINbx
CaAQ91oyiKXUcHLDlOZv1FAThDmzgKep8TQLXWmkJx5VA52ut8gHrcMa/JkajlTEJlrR9lhb3+eq
BOfmI0cLIgjtx2/bgRC2SITw+G8jkBoIM6tQkiCcS5pDhQMPmYVd+KGoPRosyBW1tUWvacX2Oon/
U3ljzZjoo6ZLGMLAQQEMx9mUWKDwL8wb4hXz83zSXIrv3tV/ujAPQCarHuLhIKs41vvGsRlbCGW5
TSRw/wk45sA9HWtj53jmy2BZdYoKGQF18XIMaf1jFeg8n5hr7zMisxA4iauMI+f2GoS+oTvLenBX
kJXNuObAqx4DrXJvkioK/3bi/qFbI/EmY0sFHmPCvL1ReYF1GPMhWZV6ymAbpDEz8glyMEDmMBUf
f4HSFz6PxiqCACAa3VBN6uwBhY7KsglVuBKcaGd67a+/ZMP+u2TKtGH3Yb99V2CZ5fB7l4CnQwqi
YNffqC2MKi2p0GYXHNchqNPepC1ygbnIoKd0ZIjP6XmjkggzfM8nYuoVlBr7fb3Hs4yVzEgazzdQ
HL6SEepuoO+tu8S0LRSFYzd7MlFh0aFzrHv4KaQCcxKZREPNCUyzybPHq26qBwrg1BvVR9dTY/NE
WyT51jLifHp/uXHKyVwX32hu+7hQHGTDO9DLWeZTZ4H+0dgqM0EC11h9MsHVmK8pTPEa1RfLnz+l
BJOj1E6KiiQeoKeWH7UL9yN7oIcW+wYANWyyDE/pTCzqjiENdhco77ide/wzcRQBddp1+1GJkZLb
eF5sIGKU13f3wcf3MGGtnzDznxRK7mM80Bc54aZElBrBEHr0B7S+mhiuw5NpK+VHn4uwZ8eVdayy
EtQbV78BCQSpylskz78k7pKs1v8u0tamFs1R10ol2oiRSGJ/7QcNiVRVI6KhjW+KCW9MdH5/7GAp
QHEt2GZHVhvrTSS16stwFY61TupoXNq1dZwDA42MApQcTAEtpqIoIMHI2RVav/LcggDCr9bQd+03
sXOYNZy7OLxL6qUg38FeC/1lP4L+bOT9mZqWp4WGnBvWAfPjZHo2lkNyAHWUEreXvjvziGLDzAUg
rLkMQUzobPuBuKkrxZpewFVHlHc1BRCc/pCYA21JePJDzT4ydDfKeqC4slxq72i0yHMB7Sp9yYQa
fsq7ryDkkhpmmxL4r8nmXfCMg2pLxK5qBeaFy6PuwdYkQBO14aPlDMjB35ls+IELYm+G1t/wc9oh
/+vSIs9QQTCehFEVvIpgcDLzJ/AUNnMmEw2EB3AFb5tjV+jfSSB+rEi8QpnO4L55/sBnWlMIN5JK
KDrCOaE2FJGLromfJAvD9NvupSQ7h25HM4ACgeGqPhjVKldhJqeyGGX4ItI5A87lIVEWwICSP7H+
6g4dLXFYqO4PqFIBBnWnS/EohA21t0UECIWCQ8RyRdZHFb3Ec13xNAMUBYVcLl6q9cUElvzHUdPh
iFv36u293bkG01Nmy5bpnOR06WrLkd1uKK/N1hDxpDBxHVxdWW24KJYhwUSF25IRfHWzypeCIbh9
uKilKxNn7+WRDj1b7kM6nzKv+3Y5XGGDKDumPvx8jmNQd7Hy5Va73PBA5NtB/uJXVexF/3/LQW6X
ORFL6jTlcBr4F4Wlzggxq7b3tVcRbYit0P663UIUQelE/4UlT3zJ99KTxelkNTuJBZ6h2qx2zNvh
6G862eA0Uq1zxrH9D9gPQc0yUIHOMoF653AzYMG+WcMDBvr7wNbZadOpN9iRDq5qRmp4CtkVArEy
/Bhd145IDGnbBoWYXUbI+YG59LLH82nFLZrzC2FIFMvmfS7VMkbFj7PeWtvzcWhmmublOLgX3e9Y
6zKJS/Q+StidMbei9KZktLAqH0AeDpMpeHKK+lXuf/m8MF2t3cD0raK+J+sKbbC6qmQM6mls/AvT
xodVOFBHgQDa2y/nyqnwCZpd8fSwb7HjNMLoL3XZL6ZVFV98DymgJKnwVL/P88tw6lGACqiENTNh
EQkQgnWT4cXg4WDKwE5yAcZN0jbYgbUnsnCKEUxKfPWMJZFt65b3UhMpwOKWXNt3RmUNFZZWSIB3
WciWFswr4hKng4cb78vkkE9mt7omWKg+qzy2GtimvDcl6atqhmQbMKoY4DsHhwGmGacrEpYHgW3/
C+v+NitqbVx1ttuvtCiBOiQJuGSiM9W9B2zZIhWBRG2GLVblnhia/aYEQOk98yJ4eKKEnyoABhdX
Ldbjh9z1j4bEUUwPUn2pd4exsYOLEKqLXrTXKDb9kym42+QJGUyHhx4mFeLBOBuOvWk8yMb1AwFH
JFFYIOIR4mlMhWxqDG6gtxo3Bv/ZVNX9IJdL5N8N9i1bvgfD2GtgrpCgfiRUvasTNQyvrtYxXj/Q
m159Mh5WifPnsF1yR4WfBFKYIh4PiLZU5qFSXFUqUxAgam/KUbuC7/wdxmWRlpyv53WKyDY5yMIE
2zdSymez2BkUWFO0pdmBE3Bqh54wp1NEO9iKrGg86xVI3iNoba+XRnYv+Mmq96jG4MDrkwf9FV9r
pAwhFACApnDgF18Z5+tsoR5FOQNlxOFjIMC29EzuFN9Uwf5a3Plei8PRxnQuinBn/xVIZRTvFuo7
DEohRBRx5VSNpn9RqlkOFxyTcKBG18rpVAsIfHootUxAWM1nT9yEqzxawmpkyCmeSirJLXdopz2n
IVa6nKkcFhCU0gDZtJtFDPuX8ySXOPYgBheSwO3PGsQlOwV4aM4r17nUmqUrTlY8NlBtAS7D+nku
GQYB4adZDRrBX2+i7hiBJNMjt4/zIobAkOGaXCRaeR4wiQ2jYp7WhjMCqa15Ff+Mpkw5aPvIT3Ex
GBpM2k802SlOOBjG8ViU5NZgnR0XDedU5U0mJmf6U5XP4vQldHKtnYdY+YHUHc4JIvLZvNDayo1G
vvAHdfjssnr4UpnKHMErYpXqohhwxV0xhz/CIXPCZyz+kRUok0YkuQvTxA0sSuyQoJf51lN6t4jW
Hr3MZA+5X0WSWRZu+cyoUV9/vd5be+cwoFJSrgWo0zapmK54nEyUP7DD7B68XyAlWB3DrLAMLF2T
Zroxki8MsiBU+ecnYnwCiwD0ZaYKYrfIdVgZJP7yZViyoGTZfZ2VCgZFnuMiSPK7PUs+VPVxVPIy
B6GiV7n2JpjcmTjUsrJEJ7cZuNG01Lz1fuIRDQb+beRm6i487+bEIYKMsFj5cvM9o+zqxqv7G15x
CdvFrsnnVK4JFFnOaVvBN2koNyah6/yLVL9wFdsp1JvmIEEhsU5YLxqUNbcpFiNSELe5TuPdxsdW
klnyI6l2zLE8dUSgOJcUORdCTjJvgYAfoYRLvIZw6ZgPB7XTkEtJQ54fgXwkAIWfCu4B6ZwEm04n
UMdNu1ZcYvxmDLujC+uaKpX+SJWO3B5rc71+98aMevdwnLWG42cCPI+f6Qwprc2avfxifpbQefLe
Xm5R5gfzqMYnNL07FhtleqCSg7GBJTrC8t4QUgi6eRZzx1n9iX3srjoejcZ8O3LGpxEB4KOSOrGr
Okpu76b96KHfkZXhOFGmbvf5wpeIt7XSm/BfprZpdbvKkTDeBA1Jc4lE6QjruabZY6ZA25nX7JQF
8EwUOUmzhJtwak7htM7d35NfYBWpI63jKWkIddBX3xj3XNEfysqrHni0ELrE/azMdo6nksk6TTyH
vWiV0+2rCRUmqHbDEYJdYmMrj+gW0b+3x5QNtJN1IojQSKs0h5jVXOxxH/fKvGve2Q3IXM4HTeaC
evgZoxkSxrJ+vyaNGEIQjye2oQ+SWaPzbskY6m1+zXxykHihJn+Mrf0ri7yh49lAHcrB3jcU7Ga+
AFpyUs6rZhuUm3kpjtUIRELZXlDI6FKXgJ2tZ9Wr/DsoOjVx2AX/ehWlGo4KijNIQ0oy7P9savIP
UzozFg+58dy3BkELEqus+8eYfXz7A0OAxCic2hcrVlg6zPwosW9sQo+30emdtuaPGfqhUOjHE9nQ
NUlm3Q9gwgqP0rAm5bjzvzKvLwa0zvSU28RUKAjq9LInvpxeDed2r2QCpOf0kQH1gEEpC2/4oJhV
BzyvB1ZsBsd+mKu2K0s37FprDJfZIiwOAAzbVySM+rLeSoeQrsOiXw7zresRkcgWIS/uVzTSidRW
Q0Y3bLJ8s4Qmu9gVD2mLHm5JEfIMAJua2Fk5x7RwyO8NaTKtGyJC0GItTq6VDiGnP8mtNtmsoTSk
5GWe/+dgQ4Q2hYY+mn/hDTihSxXRo/0HJH9ueF591j3bW5GSLFeYhbaIptcx/p5GjjZC/49pY3kf
/XiA/tvpP35CeJXqSfvTipIT6+8G9dpBHP3Qi1763AD6N0/1XhaO8YMF6067AB9UcwFSAS/6UEXS
Amroc/v9/+yCrvDp3epMSCRl8rfZqAI9VTuaxd83mz6rzwwCBSRRJB2T0riBIENt1P7UX2CQpZ7m
yjexm6Y811AtzI/xMHkUkCfmrftT7pKCGrHR+qR5vMkRb4SRfjVafDK4R0DZnpQ03T+uX12IQYTR
DN0RaAVXQMuE1MS1rCeluu4N+Nei0W8bMPlQ6KumfagrXzfxRMgAvKgCDtOOh7pPgaFJvZwuyP0h
/0gjSPWqMYGwIRV9B6fqeEjWItRMK7BTgC1zVIq48Jhnm7EBjnvYB7oiJQUAvN9mULSGeZRpuYuc
ipTNwdPnp0qA8Sc+UDMUCMIKnNlzvBaXWoCnxLmp5k8LSgIugYwRMzrf8w2FNwpx7C6+wokHvhfu
WN/P2U8o56QhRl0UrqJj0Mo2F4haOU36qfFXN/OZo3D7iV6G0rwrEHiKRT72C1iWK8VEjg==
`protect end_protected
| bsd-2-clause | a2a42cb977e37050b6c8c5a3df625899 | 0.939158 | 1.859957 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/romprn_micron180.vhd | 3 | 850 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Galileo Reference E1 codes.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library tech;
use tech.RAMLIB_80_COMPONENTS.all;
entity RomPrn_micron180 is
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of RomPrn_micron180 is
begin
m180 : ROMD_8192x32m8d4_R0_M4_ns port map
(Q => o_data,
CK => i_clk,
CSN => '0',
OEN => '0',
A => i_address);
end;
| apache-2.0 | c2ecbc85b83a576d9c8892903dd2273c | 0.503529 | 3.679654 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_bindec.vhd | 27 | 10,218 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JoMCOWeb5WJCBfHoFXpAeueDDgvCDiGp3AckCc481MQYfkwqbKzf91lDJ35VGRkR+lnFDdba8hVh
ebdPAvk8sQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bZP6jV/nU5x88OLSeX17wUzGVM/1H7fFl1OvjJVlfPM0WRyEzOpDDBDAUuNgnxFvzLOKKYEuQdGX
W9Azus4jUwU+zlgsaiCb1S5W3YMjUJKtbRQ/PvNNulBlTlfZaMHLAox9gfCqP4OK4hzymuRCwSK9
PA7SK6I+FbKAacX9y/g=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
38Ya3DupjVbpSJ4i6CmxC3OEuL9qNwdAvGt4GnhSmvDhP9C+krqPc261IqfCwYzwzxzaeMibTDWx
/h5fHzYF2I5fsXilkoEoRxiVUecJo1YSbQfTJW8OEBtN5aYD4EfWNZxg7GXemsfNXYAT3IQ9OGaZ
Z3OnlMzYiNTbG4DNtpaaHWOF6C1ZcpZaMxg6JA0ZIcSPls5SVALLcDt5FUbDAqBNYpV4JoWo+qsc
FnhESB/fKp4TYpfMu8ZebNdGwLZE/v7NBBWsur4E5vgpE96o2V2PrhB/yUkeOaYd/sqFfOVAPPYH
mOxmomWznEckwZ7yWdfaca/+EES9Dh2xe5bnww==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D5raxCdsBjNBeucgp+JNk0QydQuZbfT0hk9FPoXi6WfKMKGXanrHw+M0M2EvNOZMUencxzfv6CtL
nCmVqYCrBCTP3KURzHM5DqNYzQyp0kj6XGMA+Q1QHtCCtnTEsuFMkRdychCBXeOcnfn0sPqhPAb+
dDkLPxvSvOkSf8WjYwI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KE84+0MQOal9OYCn+WiAXywM19zQ4xYNV40iodnIlowR+vSp+kbADs/ClNTsY+01AbPMnO8ZTgZN
CGRjsRjKcpFcdHcCbRqcEDPJE7OK/v9PEqPDH9NFgGw1pSJUkP9IpUNC9/uKTepjTRYkaMQQIcwb
MA905J1RyQ1JTo8+T7ZjypavwIpWqfh9+/OtTNQBqe8xPN3IUu4u+7M4P7P5w0QOtT0XGFUOVu4C
5WyMVCFrGwdZoGJ0XcMR+keGC+lH3zgKGf7XDuZwC5nPj50Jr/CWT4G590JXwyjmGrh+LuEInmJ7
dRdHoyo/UrKvxi9s4oal4X1UmgumWAW7Jj7wfA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5824)
`protect data_block
+i2JWEPcRSCfDheN34U5CIXM7TMebR1UsErZd2k4GyCTJfly891tZwiJYCO4c3zZ3YZMRtqvDIzx
sjbrVwcN30whDdYS6yF4K9+k5e1aAiIvd+oSW/m9arUHryWdsYqLE6C1LeAguwTA/1zfiD6YZoO3
nrXJ+indJ/Aw864XFEpkfRxb+IhMu3rIaoTNacR1LCZqlw0EmjbXHUHDI6FEM5RT4jFzufIuqu5C
PzWb4uxkWBQKWBncwbWF+f5hSzh/Vuq6XSHNKRszbk6UDBCDshWjQtNMsCH4jO15citOGI816TFN
0LJNOPaXZCzMI5dFI3rhbA6Ed8Hjq0TB1m24vhmCmE7uAwvYOz3nKXQrMbcoL5+eUufC/UiKfJ3q
MQdljYDDt8K6K9jI5AljGzCAkhcipmSYqZXVb3VI7Hu4HZzbMAsPovRBfNf8xvDQ1Hdx5Wq6pAsi
Cnf0hlaqE1J6R8vMVZ2WHD6cLc4ah/FLVxvU48TUcoeBlqH2Ic00BcuwWSrdBfuzzU/9u6QG++0G
VLEpAg6jUijvP68GDE2f37rWApeiDoXZcp5LgPtuaUHN2MOVj95ibjfbTxRp3EOdpLqBejkhqLj0
WJCTOayBP0mhDqqQbIwUUE+UZLh5HK/2KiQbAp/MNsoItS1v606AnoHqsCHn8kU10j/VH4E/Zep4
c1iAhEF+Tl6YWdO5s7etCGkdQTc3uAGY3xB1Sd2hWLk7yecOBAzEXknG44FvkmwdBttiFXP5cgpd
9/eDYbIK6ruHxOOMSF2CnlT+SSkn87iXcrvnTDxhKr/+MBnQaIpEG4U6hYGnoPQuLV7wPwyr50wb
2NR3tv0PFj4EjOTUR0ZH48QZCR7aqF9tKY0Yc5T4uA/wnlY8qxgsbeTGqo5cj+DxFZNpsN+rlJ3O
afgmACsPGSPuvWckJJ00SCS3SnaOqlxGHBjhvRrS0OkA6Df8LBJ73OY1bXURqZF3YOLTU5irkVJn
S6sKhToXzgZYZgjiOq7CGjbYHQWZbWPTCFPoprPNJUzP4AVFnqZfPiluC2fssd1fs6jBOBuQCCIS
n6Sm/15h79cTQim1h7YMNMA3oEdIBn2jsfL/VTnr0QS5cCqUn/BxtNxX1U+rXZ3hMKjuvmfEFv9i
Lh2y5hOPX3sJY4NRyiSWKgK6Vu6m79E6amYfLTjR2MjPmjKsHXuzwuwUuNV2TT4MTkxfksyNMTgH
4Hiab7WYOZQXKG7iQ/oyz5see0asjgyUnn+vDk9MDgbJ8H5mwXKfpghGrpfUPIeyUgD9pBRgI+4l
dOhN6Dj1BIcORQu4OGkNdQUOv74SNshH+w65lOz96LUfxxE2ArhyTOgmL02v2j8wixqKvIhZh1HV
XcSCbkU+ydq0uZkut3ZyGEWfjnejOzkjY8s5sD2OAF+frvInGiD0ALAzZogNeI6mc1DTi3QRh0jV
q9tXcpyqPXWH+kepUWTWusQrDITesILyTES6cbsaVBx57+lLKjaNWANiZNhuviO8kh3LfNODOw/b
K5ce3NPZl+/qrisHrLxJdR/X5v1NMsRPZ/Q2RkB+jNfuK83bGw3a7URdpjx3HFM2E5qWWHGUy67/
g7HOKATDAD1E5xgSUBhJhL+ZmkETwPmUy1QFPsWRD18jH8A8lgyKMh06Fp5z6r0ea91Zd95MOwWq
r4uCt2R9TuXE77auk6/w5iKY1U3GwSUGmrXkEMlrB+cuLZ7BZqJVLLNr3V2ZroJByZFqDI3GIpR8
fe8tHvmBO4zAc+dZAXREsOr3Tx0bqUbOrr1cOekgd4wPZ1qcqWtJh4VQ/8F66mRWozNp96fErAJC
97QHlYujyt8su97BPFTAAywCHGYBr+k7CMPSlFIft2MTaAWM5+DceytNfdiClm3bDuYlk5/9zjmC
ASzaDsMejOP+QqGL+UbYYRF3BjxZ6juRJqMj+IyG52hc5bVaRCfsEy1cmhz/YFPVa149rLJyQ3If
TVH3K7XPIp7zPkggEPCj2GFVWFk+zHMPrRR/axC8Diz+wTV/DFno87SEWxXERwNk47qn7WfHAQ3Z
UK2c9qweB9eMxhEghCWCjBKjuWsG8cbsAtrngtpmu7RvSF4YeDPmvQlGv5d0K9TdVzWKRZS8M5SK
BqW/nigPA20Cvh+NUMTH0v+Maw7AsR6qIUruX4LZ6HUi2PPhg4TpHn/Kte4/2mI0ps1HrP9vzlb8
jgWlhFVhr/8ri0H9WAeXJLEHIUqQmALtl15D7twXD242Kcd/Vi7H8sYO+WyAOFuMtu0mZL7aifav
me3a2stNZw7EG9gWCdvNe1sxa3Db8tCTX2li/kBNyZkMEZ4MhLU3MyosI2XOoB5Uh3K9PTN1x8xI
vGVKoB/+Scej6lvJem1NkC8mV7pgPrGFnxm3dG04H+nvbdPbytg9U+WDqbmT2PXte6/n/v4m6WzJ
+aYlM412vFLqIJ89NgEtzZkMhW8hgtN+XeJ6kM5WNe8LyujfISvzxJ6JjinoalaUuE2EKpdojjvf
fJTQhG18qObaA988oTPHkUmLclPWGm5PMKyTuql//6GeFUHFI7Elqe20UOOh2n/uDqldCwQiMK8u
ica46NHe22p6FZXhnG8vuKugGjW/Z+winsa0ZQKvnlfKGDB+DtLIcFMAj5Y77f0U+EHEpsNPdPua
fiVszKdPV/bFoChbpEHv2ou/gahWEbFz0ds0yB8wEvDv4PWf5Qkx/jiGAxSmlWyJ81GeHQOb+xjO
hLL+Nh5IjSkrMq9fe0pqwrTjj1Lx2d5wtRa39s3VHWo3I7KiNQa20f4WZthMLbe7dnsYcnJs7yeo
afs3DuYmdOYt6ObbM8E2F2qNnqlR4xz1IqrBQpqcH3sCjbnJgEucfFnMA9eekEIcDZynWcQTMDkE
wx8/TbpTqKownKkRD6H+X1Vs43aYk1ctEBnSONEgUbFk5L4UnqAXlWxy8P3/QF6c32roNoYU76qV
x47C/1k0Gvsh5fxhJ3/d8s3reDin58w2YFhVTZEjRPe1/zvSW1kg+4UU2SmBVEYZkTHvEo552jC/
XR5WxgJ5QlppIstGzFz6uJRenvFTL7YMpYyQMyYjCuaHXrMa0KvT/dvfAit0WfKzMxL5+5hEP8YW
XqDWg37UYgCuMCpGGEo/w2I5XVn0Jx+FbCaqpM/onCcafBaa/y+USpfH4X19LhRar/QGLlklod8b
5Zod2Ynn10ETeYtViV+8gWzUpRmR8VyAwSWf1lRj8ZaNHCvjYQJVkXbLgWuxLALgPlY3fwIslfIV
mrB+Y4K0mGFNNpnmvDDzmrYhHyDlhKogZQFY5zucORtpsMvrpDnhztHVSPlEB0/PZ2L1gDSvkI8b
V0Tg1umxma32gEra+VnwesMeef5tFmBaWNlWKK2Javi22CdIzrIDF4emx0+XrGPLrahKS6yxT1Gu
gSmcTFIn5Pqep+Hz/oa+UkKP+X/FWyiyv4+9HmyyIHYfV0relTT/ue93QTkzlam6z8sbNSX4s/Io
vomr9/8XQ3yDKfJRuUM7yhJvbAruAsLv1bf40cR0SyId14uOLe+mocIoI1uSUa67CkNmwsrqVdbq
cD6YigX9A/tbdXIMegsafPPO7SpHUQi/NFZb28hPPSD2VfE3QUgOcUT17Zkx2rhgMVIn+N3Ng2Ln
jeahpejXeVuydfH1vsxUDfh7URAnrEsuvVz48gZAm+fVtQxDHG5oFbjAxeUwjNOzQSpfz64yw3nz
x1HY9qCQnhp95p+XJwFKdUl7zp1cQg8aqVesAmQHQDT0kiHbjQoRyIDBpbWV2NTfVLhFRH8tqVIF
nWu91GKSB/lVMzNU9zOIaDMva9+w8klk0bnxUvjellxLHyF51NL5RUvpg1bcx2Hlr2Zd4W7Tcut9
s9KhPte9/iQo4i3+XrPzQyiMBD0931OC9jl8ZF0a6Vcjj/PK/QJXbrBM4fyBtBR8LpepXp1eA5rR
xTHMW3oy8nWLKoOIf+v6/Bc8wfyuZRj7Hy0mi97QVbOXqnw1gHS1Ra6VqW6v4DunVqM9n613oDPr
WOWB8X2hm9RouDS79SVDmrNSitQrEhRtZeHvMS6JFI4MfwdPgGowYVdcTAPBbgqlcv6GQ549jg7s
Qdcjj/FBHkZWB246kCl3pLdi2wjqpvc5FiICHBYBBWvm7l7b7lj9OBDlJJQ1ZfumBcLEPzh6o1lM
bEmc5CVeWaKggjfqtYGHIcfJu6JOevmo8F8YvPW9L9GSbX7z2rUQlYRsZG/Hz87NiwOPb4vyNj2D
yVFkzOebndkKvpura1V1f3s+7tWH3s8NVMHBmsh9w8NkBt5ISfduf80ViMZjHqsUdk+GiRXa8Y0h
VA+NENVH+73m+qfLbI6/bqbiHW5hOTcFL20D9zTWGO3+vY29DbQ095ZierV0db5xsoKQLmoCzaGg
Eze7UxOBzM3jYGZ1r/M3v/so1AUKjdt4OReqBUn78xq8fQBCyH0IzsF7DcBezUgZSjj8D0n6PInd
CU313MaNBMrO0n4qYxh4r8MkFatk0ousZEBpP9SZyZiQ2rEPWvmUbTrMZeUtw9lJ7AbfWdo5iry1
GImCDpPRXg1kgAIe06YWj/U30JthPFoEaloemg22Z4yXeIwOw5gSGyQOj6WyhD/LtiMVNyFWvSN8
5MPsec2QYLDxcffkyPhfN/Nonoa+PrYjJTGFsr8H5mdK2hODi0EdA9hjNWzOtugKGWI/2KrPmoZE
We6Lm1zJtUEHL5GYQ/651bOfEo6ztlEreA/344ttic+6hMGc1wnkbmInQAFqqBVIiRqaa2cfgVto
L2Ge8BoZeQGCo84eybj7eSEjCTfsELTvfqxZkwtGLPLTvl2rmVOqztUDE/8GPdLKVjdJUUcj8qqE
7H0BhPfKRxLUoNCO+1tCBVjJ4oU64b/g2AXQAb2daQzI/Rs0UuggAaHnbKp0Nf/81tN50NpzX++E
a7YHeNEP9UfJEThwTb8cQL2Ame7xYLvzxaxuisMYH2wUP7MWdDJHgHqC631ZOYjN0cPGlcyH0BpZ
Z5joSp8joNYOFdxeTmF0niuMSH9tox8dLNH9yBlgpFz3gBszs+vZ/kfIyIRzRn9gnWkV9bm0Aygs
5RxVtH+ZGdKtyN7RTGeVGvZB6+SLG9iO7kxtTwDoXL1mkm2oqECHWT7J5PQbI8CApFwHCqi8UaN2
Cy4jdane/edArWNiWZVi3OGNhX6LLi6lXHePpeN1ZAyyIW/Zp5C4SpMMYIEQlRzAK9wXccc5fugP
ACV2JQe/WWQby/GMmd6WbVFMPjkyeOSYNiotbsR+Ak93AgI7+xCbzdavuIN7V+8X8dSUdfN3KYNW
dgOo5hh2absqXnAKXqqun7JvS6ojzJcnqmej1wiIwnjESUOw8uYp9wK1AiwavcRN74wC9+pKuv4v
VQjEWMk+sWMXphiQc1qYd5q9QFEjYRg31Rr2IyRs2a5wdtaZfXp1tTxALJ9RmSU6Rgq9/TYT0U3n
yHEqdUCmlqk4mWUm/qb5js3zV7lOsCEWCiJasMiJc13BvKOEmM7LBIRX1c7claehnwjdA2MMaXOB
O+2jlO65fJu6hqtkr9KvMCXw6xCBS5tGQGjVYeHTTP3q8dGjyd/j0UH058uqqEPALgYWUITB77Y2
33Zr0p7cG5Tq/osjF9EvTtPA/3WnVOjh+xBPB0rq5afqi7c72Jm/9zS//cxN3W6M+wMem6mBFlG5
g3egYBak9ppxK+ZnWOfDQB4DZnQoxvk0zpjxV8eyo7Q2GpWy9u0cbWY0ln8iE2xoAFZ0dW3O5pDX
4MyGbA9MNsiIw5/FaPe1S5+qIxOWIAv2IoiFZi1GpUJJrgh+ALGn8N8ISJVjNipFOMLunpuJdTnF
a78n6uEAnH6AoZ5HIyvbcAT2mQRkZIVuCzq2cJ9AJMVmVdxvxm2V+n3hEcLiF7JOEJzLDUthKygN
rdRUWO1BceOCrL3IXTOIAExp8EtanSci4E4dIy9vyMRjSOob8S56DlAyqe1ZxJ6bev4MPI7tOjiq
XOR3GEfSkgnx4yVWXe6Cl/+Gcko+YmRKKeoNpcbQv/3S5dChRdEmxd9EgKv3I+MsjQd0ipbIZ7fm
7p9cfPzgzvMsj07Wzw/Fxo9oOke+ToFe4+pTkrpmtNj/3T99hpks37AZUM4DZG84ukfa7/xFzfdx
t+HekYTEfwAMTv+emELfFYLNwdj4ITjGwgnhUfRoiTd0X34pUp4ymnKfMNvdHTWD0J1zFLH5zPWm
7G3HH/CmJaUgb3+RvkhTsRxOA5MKYD5FSogCidFfGejOhAJw8SV8np3+KUY352fTFG6ZKsnai0LW
kQIUaSf6SQWfivjhbLzYkqWpS2F7gDTwD3o4f30iQ/jPyFvPsawk2+V6XUW+rH2V9bTyODZo5yHp
nSbRcIIvoC6HltAhZ2PtvP2d/956p8alpgidGKHxDKNzsQU7ZwaeWrsbFgzguhnMSTefHM1oV9AJ
g7Zxh5pa72ld9gEELd9AcMuw21OXkYvTSJlQ5nW4xpntknmAcb8+8mHqE3+OfqjNBkYxWRmU9Ufw
I+Jftyaz0Ux5m7QYPSSVAzEuftr5aXLsh6QRaC20XFE41HcEb67aPiXtCc84m5XSZkdmJvyj1xlB
msVZj8UkWj77lyF12ezIGfKrOTByMcMmXzoH7Z6tcLD6jb8FB5Kfbqe6naTTt3bVF9PW49vOXxIL
5i4JPdXbCnSsGW19T++RG82+g1ODIsxl9fM/yJNEtfbUDKDmdkcercDEKTyhOIiPbLw0VOH+yJTl
QLYZSzf0poV2AjgD4ndVElsY4ZPm6rYnJXiwnzKgOAtLnTQ8Rym1wacgcpCvRnfY3srbkjvm/AAe
25cmi3NI89O6eTB4kibdnyNKMqJ3USDxdD/9by4pDF+ZIFTJZxvR3btjBtv5RzY6cOHwB7LsSobH
A8PKE7wbdmfZwIcvZnlznud5dS7Zj2ZjDU/yMbM6+wbOl5fqBuHfkRfJPsA4eKBcVCsxoW8SQGdZ
EdYf3pmCmohz663VyeuigA8axjTPpU/C3pUTOi9tF5Ex8tNQGOXbWVCZKTR8mxRBvPHQrKphcHqB
ob2iuT/9UUBnx/Dj6pFoOTGiEAhNt6kSSOlI3/rGTBm+EKb3Z1oEneCqTqUGs0hHORjXAdIHt0J2
j9TcgjQwHQ6I/b68FVnyo8ywieVEcA3aX7VhGs/ITjoKPqhfUxsNd6ZuXnLyFzn8O3ulMTX4hlxR
CzQ1Mox+bEwrT8WRBz6sdnUc1Z3VLM0gJR8fiYGy0BWp2IwocXw9bu3zKKYF6pvznIROcUuIUTip
OO1Jx/iu7sJ9FzYLmqgL8/vd9B8YuOA6uKVIWIhgm7oEaL/zXS9/Ohyf4LD0dCA+TqXleJQqtI4Z
ZNWDRpPfeDNonWS76ykWWaePuG0dTQZZOPI7R3mbKM8uejAVkMlZVJXoPALZkzcxcC3YeN9hbYuA
HwvmxwrMUe7EENOzvXg+xSIAdBlWntWthsNeaKirrPqm38+NytbYYrdX+ISbMsollJnmorltFUCg
qv+fDdUbTnfS1rIXEE1YFCVg1VVQYeCK7k7Y5kkesNa4hzk55X+7yygPZPT8dgyUKg21zKMsCZ/k
xbUbBxkryuVRXoYJ9YB9lSWzXHj0Rg3NweQRK3G9sn7Ap3Z7AUuB9YoCWCv39+VJNoDB5dfRYT13
/TMJel/FVHMPbQvvMMd8+wfKt0QMsXlCTg5t/xUeCOlaS+eisd/vPB1LIsKn/kB71qxMoXECrEve
EqYRCqgf4vGAtw==
`protect end_protected
| bsd-2-clause | cd4ba297ca5103ad7e59eb70909a8a3e | 0.924153 | 1.915636 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_rddata_cntl.vhd | 1 | 79,652 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_3.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
| mit | 821c5c65c6e48ba676bec2cc6fab789e | 0.390536 | 4.438921 | false | false | false | false |
codepainters/vhdl-utils | tests/t_hd44780_iface.vhd | 1 | 7,315 | --------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <[email protected]>
-- This file is distributed under the Modified BSD License.
--
-- Testbench for teh HD44780 LCD interface.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t_hd44780_iface is
end t_hd44780_iface;
architecture behavior of t_hd44780_iface is
component hd44780_iface
generic (time_base_period : integer);
port(clk : in std_logic;
time_base : in std_logic;
db : in std_logic_vector(7 downto 0);
rs : in std_logic;
strb : in std_logic;
rdy : out std_logic;
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_d : out std_logic_vector(7 downto 4)
);
end component;
signal clk : std_logic := '0';
signal time_base : std_logic := '0';
signal db : std_logic_vector(7 downto 0) := (others => '0');
signal rs : std_logic := '0';
signal strb : std_logic := '0';
signal ready : std_logic;
signal lcd_e : std_logic;
signal lcd_rs : std_logic;
signal lcd_rw : std_logic;
signal lcd_d : std_logic_vector(7 downto 4);
-- 50MHz main clock, 1kHz time base
constant clk_period : time := 20 ns;
constant time_base_ratio : integer := 5_000;
constant time_base_period : integer := 100; -- microseconds
-- E pulse timing paramters, from the Hitachi HD44780U datahseet,
-- worst case (VCC 2.7..4.5V)
constant min_power_up_delay : time := 40 ms;
constant min_addr_setup_time : time := 60 ns;
constant min_addr_hold_time : time := 20 ns;
constant min_data_setup_time : time := 195 ns;
constant min_data_hold_time : time := 10 ns;
constant min_e_pulse_width : time := 450 ns;
-- minimum time between E rising edges
constant min_e_cycle_time : time := 1000 ns;
-- datasheet says 37us (+ 4us for RAM access), let's add some margin
constant normal_cmd_delay : time := 50 us;
-- can't find it stated explicitely anywhere - assuming same
-- as command delay (probably much longer than needed)
constant high_nibble_delay : time := normal_cmd_delay;
-- Clear Display and Return Home need more time (1.6 ms + margin)
constant long_cmd_delay : time := 2 ms;
-- init sequence
type t_init_sequence_entry is record
data : std_logic_vector(7 downto 4);
delay : time;
end record;
type t_init_sequence is array (0 to 3) of t_init_sequence_entry;
signal init_sequence : t_init_sequence := (
(X"3", 4.1 ms),
(X"3", 100 us),
(X"3", 100 us),
(X"2", 100 us));
-- user commands
type t_user_command is record
rs : std_logic;
data: std_logic_vector(7 downto 0);
end record;
type t_user_commands is array (0 to 3) of t_user_command;
signal user_commands : t_user_commands := (
('0', X"01"), -- Display Clear command
('0', X"02"), -- Return Home command
('1', X"41"),
('1', X"5A"));
begin
-- TODO: check ready signal handling
uut: hd44780_iface
generic map (time_base_period => time_base_period)
port map (
clk => clk,
time_base => time_base,
db => db,
rs => rs,
strb => strb,
rdy => ready,
lcd_e => lcd_e,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw,
lcd_d => lcd_d);
-- Clock process definitions
clk_process : process
variable i : integer;
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
time_base_process : process
begin
time_base <= '0';
wait for clk_period * (time_base_ratio - 1);
time_base <= '1';
wait for clk_period;
end process;
user_process : process
variable minimum_delay: time;
begin
-- note: we can't progress on the same edge when ready goes '1'
wait until ready = '1' and falling_edge(clk);
for i in user_commands'low to user_commands'high loop
rs <= user_commands(i).rs;
db <= user_commands(i).data;
strb <= '1';
wait for clk_period;
strb <= '0';
-- after one clk period 'ready' should be low
assert ready = '0' report "ready not low after submitting a byte" severity error;
wait until ready = '1';
-- ensure enough time was given for the command to execute
if user_commands(i).data = B"00000001" or user_commands(i).data(7 downto 1) = B"0000001" then
-- Clear Display or Return Home
minimum_delay := long_cmd_delay;
else
minimum_delay := normal_cmd_delay;
end if;
assert lcd_e = '0' and lcd_e'last_event > minimum_delay
report "command execution time not respected" severity error;
wait until falling_edge(clk);
end loop;
-- TODO: stop clocks to terminate simulation
wait until False;
end process;
t_lcd_timing : process
variable e_prev : time;
variable e_start : time := 0 ns;
begin
-- wait for E raising edge
wait until lcd_e = '1';
e_prev := e_start;
e_start := now;
assert e_start > min_power_up_delay report "initial power-up delay time violated" severity error;
-- check minimum cycle time
if e_prev /= 0 ns then
assert e_start - e_prev > min_e_cycle_time report "lcd_e minimum cycle time violated" severity error;
end if;
-- check setup time
assert lcd_rs'stable(min_addr_setup_time) report "lcd_rs setup time violated" severity error;
assert lcd_d'stable(min_data_setup_time) report "lcd_d setup time violated" severity error;
-- wait for E falling edge, check pulse width
wait until lcd_e = '0';
assert now - e_start > min_e_pulse_width report "lcd_e minimum pulse width violated" severity error;
-- check hold time
assert lcd_rs'stable(min_addr_hold_time) report "lcd_rs hold time violated" severity error;
assert lcd_d'stable(min_data_hold_time) report "lcd_d hold time violated" severity error;
end process;
t_lcd_init : process
variable cmd_start : time;
begin
wait until lcd_e = '1';
assert now > min_power_up_delay report "initial power-up delay time violated" severity error;
for i in init_sequence'low to init_sequence'high loop
wait until lcd_e = '0';
cmd_start := now;
assert lcd_d = init_sequence(i).data report "invalid init sequence" severity error;
-- check enough time is given for each command to execute
wait until lcd_e = '1';
assert now - cmd_start >= init_sequence(i).delay report "init sequence delay violation" severity error;
end loop;
-- when we get here, lcd_e is '1' - first user command was just submitted (high nibble)
wait until False;
end process;
end;
| bsd-2-clause | fd29a9d8c59a29bb16d94fedc0806dac | 0.571975 | 3.847975 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_mm2s_basic_wrap.vhd | 1 | 43,265 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_reset;
use axi_sg_v4_1_3.axi_sg_cmd_status;
use axi_sg_v4_1_3.axi_sg_scc;
use axi_sg_v4_1_3.axi_sg_addr_cntl;
use axi_sg_v4_1_3.axi_sg_rddata_cntl;
use axi_sg_v4_1_3.axi_sg_rd_status_cntl;
use axi_sg_v4_1_3.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_3.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_3.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_3.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_3.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_3.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_3.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_3.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
| mit | 20b73c641e40fa0f21bce82ca866532f | 0.443592 | 4.112252 | false | false | false | false |
szanni/aeshw | zybo-base/lib/Digilent/hdmi_tx_1.0/hdl/hdmi_tx.vhd | 1 | 6,134 | --------------------------------------------------------------------------------
--
-- File:
-- hdmi_tx.vhd
--
-- Module:
-- HDMI Transmitter
--
-- Author:
-- Sam Bobrowicz
-- Tinghui Wang (Steve)
--
-- Date:
-- 2/10/2014
--
-- Description:
-- Converts a VGA stream to an HDMI stream
--
-- TODO:
-- 1) Bring Family Parameter up to user
-- 2) Add sound encoding capability (low priority)
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity hdmi_tx is
generic (
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8
);
Port (
PXLCLK_I : in STD_LOGIC;
PXLCLK_5X_I : in STD_LOGIC;
LOCKED_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
--VGA
VGA_HS : in std_logic;
VGA_VS : in std_logic;
VGA_DE : in std_logic;
VGA_R : in std_logic_vector(C_RED_WIDTH-1 downto 0);
VGA_G : in std_logic_vector(C_GREEN_WIDTH-1 downto 0);
VGA_B : in std_logic_vector(C_BLUE_WIDTH-1 downto 0);
--HDMI
HDMI_CLK_P : out STD_LOGIC;
HDMI_CLK_N : out STD_LOGIC;
HDMI_D2_P : out STD_LOGIC;
HDMI_D2_N : out STD_LOGIC;
HDMI_D1_P : out STD_LOGIC;
HDMI_D1_N : out STD_LOGIC;
HDMI_D0_P : out STD_LOGIC;
HDMI_D0_N : out STD_LOGIC
);
end hdmi_tx;
architecture Behavioral of hdmi_tx is
component DVITransmitter is
Generic (FAMILY : STRING := "spartan6");
Port ( RED_I : in STD_LOGIC_VECTOR (7 downto 0);
GREEN_I : in STD_LOGIC_VECTOR (7 downto 0);
BLUE_I : in STD_LOGIC_VECTOR (7 downto 0);
HS_I : in STD_LOGIC;
VS_I : in STD_LOGIC;
VDE_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
PCLK_I : in STD_LOGIC;
PCLK_X5_I : in STD_LOGIC;
TMDS_TX_CLK_P : out STD_LOGIC;
TMDS_TX_CLK_N : out STD_LOGIC;
TMDS_TX_2_P : out STD_LOGIC;
TMDS_TX_2_N : out STD_LOGIC;
TMDS_TX_1_P : out STD_LOGIC;
TMDS_TX_1_N : out STD_LOGIC;
TMDS_TX_0_P : out STD_LOGIC;
TMDS_TX_0_N : out STD_LOGIC);
end component;
signal SysRst : std_logic;
signal VGA_R_i : std_logic_vector(7 downto 0);
signal VGA_G_i : std_logic_vector(7 downto 0);
signal VGA_B_i : std_logic_vector(7 downto 0);
signal VGA_R_padding : std_logic_vector(7-C_RED_WIDTH downto 0);
signal VGA_G_padding : std_logic_vector(7-C_GREEN_WIDTH downto 0);
signal VGA_B_padding : std_logic_vector(7-C_BLUE_WIDTH downto 0);
begin
SysRst <= RST_I or not(LOCKED_I);
R_PADDING: if C_RED_WIDTH < 8 generate
VGA_R_padding <= (others => '0');
VGA_R_i <= VGA_R & VGA_R_padding;
end generate;
R_NO_PADDING: if C_RED_WIDTH = 8 generate
VGA_R_i <= VGA_R;
end generate;
G_PADDING: if C_GREEN_WIDTH < 8 generate
VGA_G_padding <= (others => '0');
VGA_G_i <= VGA_G & VGA_G_padding;
end generate;
G_NO_PADDING: if C_GREEN_WIDTH = 8 generate
VGA_G_i <= VGA_G;
end generate;
B_PADDING: if C_BLUE_WIDTH < 8 generate
VGA_B_padding <= (others => '0');
VGA_B_i <= VGA_B & VGA_B_padding;
end generate;
B_NO_PADDING: if C_BLUE_WIDTH = 8 generate
VGA_B_i <= VGA_B;
end generate;
----------------------------------------------------------------------------------
-- DVI/HDMI Transmitter
----------------------------------------------------------------------------------
Inst_DVITransmitter: DVITransmitter
GENERIC MAP ("artix7")
PORT MAP(
RED_I => VGA_R_i,
GREEN_I => VGA_G_i,
BLUE_I => VGA_B_i,
HS_I => VGA_HS,
VS_I => VGA_VS,
VDE_I => VGA_DE,
RST_I => SysRst,
PCLK_I => PXLCLK_I,
PCLK_X5_I => PXLCLK_5X_I,
TMDS_TX_CLK_P => HDMI_CLK_P,
TMDS_TX_CLK_N => HDMI_CLK_N,
TMDS_TX_2_P => HDMI_D2_P,
TMDS_TX_2_N => HDMI_D2_N,
TMDS_TX_1_P => HDMI_D1_P,
TMDS_TX_1_N => HDMI_D1_N,
TMDS_TX_0_P => HDMI_D0_P,
TMDS_TX_0_N => HDMI_D0_N
);
end Behavioral;
| bsd-2-clause | 6bc1d314fa55388601a759c1224db402 | 0.604336 | 3.201461 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/dsu/axi_dsu.vhd | 1 | 9,997 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! @brief Debug Support Unit (DSU) with AXI4 interface.
--! @details DSU provides access to the internal CPU registers via
--! 'Debug port' bus interface available only on <b>RIVER</b> CPU.
--! It is also implements a set of registers collecting bus
--! utilization statistic and additional debug information.
-----------------------------------------------------------------------------
--! VHDL base library.
library ieee;
--! VHDL base types import
use ieee.std_logic_1164.all;
--! VHDL base numeric import
use ieee.numeric_std.all;
--! SoC common functionality library.
library commonlib;
--! SoC common types import
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
use ambalib.types_bus0.all; -- TODO: REMOVE ME when update dsu
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
entity axi_dsu is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_dporti : out dport_in_vector;
i_dporto : in dport_out_vector;
-- DMI interface
i_dmi_hartsel : in std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0);
-- Platfrom run-time statistic
i_bus_util_w : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
i_bus_util_r : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0)
);
end;
architecture arch_axi_dsu of axi_dsu is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_DSU
);
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type state_type is (
idle,
wait_write_msb,
check_request,
dmi_request,
dmi_response,
dport_request,
dport_wait_resp,
axi_response,
axi_response_msb
);
type mst_utilization_type is array (0 to CFG_BUS0_XMST_TOTAL-1)
of std_logic_vector(63 downto 0);
type mst_utilization_map_type is array (0 to 2*CFG_BUS0_XMST_TOTAL-1)
of std_logic_vector(63 downto 0);
type registers is record
state : state_type;
r32 : std_logic;
wdata : std_logic_vector(63 downto 0);
-- Platform statistic:
clk_cnt : std_logic_vector(63 downto 0);
util_w_cnt : mst_utilization_type;
util_r_cnt : mst_utilization_type;
addr : std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0);
rdata : std_logic_vector(63 downto 0);
write : std_logic;
end record;
constant R_RESET : registers := (
idle, '0', -- state, r32
(others => '0'), -- wdata,
(others => '0'), -- clk_cnt
(others => zero64), (others => zero64),
(others => '0'), -- addr
(others => '0'), -- rdata
'0' -- write
);
signal r, rin: registers;
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal w_bus_r32 : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal w_axi_ready : std_logic;
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => w_axi_ready,
i_rdata => r.rdata,
o_re => w_bus_re,
o_r32 => w_bus_r32,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_dporto, i_bus_util_w, i_bus_util_r, r,
i_dmi_hartsel, i_dmi_req_ready, i_dmi_resp_valid, i_dmi_rdata,
w_bus_re, w_bus_r32, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable vdporti : dport_in_vector;
variable wb_bus_util_map : mst_utilization_map_type;
variable cpuidx : integer;
variable v_axi_ready : std_logic;
variable v_dmi_req_valid : std_logic;
variable v_dmi_resp_ready : std_logic;
begin
v := r;
v_axi_ready := '0';
v_dmi_req_valid := '0';
v_dmi_resp_ready := '0';
vdporti := (others => dport_in_none);
cpuidx := conv_integer(i_dmi_hartsel);
-- Update statistic:
v.clk_cnt := r.clk_cnt + 1;
-- TODO: move out these stuffs to bus-tracer
for n in 0 to CFG_BUS0_XMST_TOTAL-1 loop
if i_bus_util_w(n) = '1' then
v.util_w_cnt(n) := r.util_w_cnt(n) + 1;
end if;
if i_bus_util_r(n) = '1' then
v.util_r_cnt(n) := r.util_r_cnt(n) + 1;
end if;
end loop;
for n in 0 to CFG_BUS0_XMST_TOTAL-1 loop
wb_bus_util_map(2*n) := r.util_w_cnt(n);
wb_bus_util_map(2*n+1) := r.util_r_cnt(n);
end loop;
case r.state is
when idle =>
v_axi_ready := '1';
v.addr := (others => '0');
v.wdata := (others => '0');
v.rdata := (others => '0');
if w_bus_we = '1' then
v.write := '1';
v.addr := wb_bus_waddr(0)(CFG_DPORT_ADDR_BITS+2 downto 3);
v.wdata := wb_bus_wdata;
if wb_bus_wstrb = X"FF" then
v.state := check_request;
elsif wb_bus_wstrb(3 downto 0) = X"F" then
v.state := wait_write_msb;
else
-- shouldn't be here, it is better to generate slave error
v.state := axi_response;
end if;
elsif w_bus_re = '1' then
v.write := '0';
v.addr := wb_bus_raddr(0)(CFG_DPORT_ADDR_BITS+2 downto 3);
v.r32 := w_bus_r32; -- burst 2 clocks (very bad style)
v.state := check_request;
end if;
when wait_write_msb =>
v_axi_ready := '1';
if w_bus_we = '1' and wb_bus_wstrb(7 downto 4) = X"F" then
v.wdata(63 downto 32) := wb_bus_wdata(63 downto 32);
v.state := check_request;
end if;
when check_request =>
v.rdata := (others => '0');
if conv_integer(r.addr) < 3*4096 then -- 0x3000 on 3 banks
v.state := dport_request;
else
v.state := dmi_request;
end if;
when dmi_request =>
v_dmi_req_valid := '1';
if i_dmi_req_ready = '1' then
v.state := dmi_response;
end if;
when dmi_response =>
v_dmi_resp_ready := '1';
if i_dmi_resp_valid = '1' then
v.rdata(31 downto 0) := i_dmi_rdata;
if r.write = '1' then
v.state := idle;
else
v.state := axi_response;
end if;
end if;
when dport_request =>
vdporti(cpuidx).req_valid := '1';
vdporti(cpuidx).write := r.write;
vdporti(cpuidx).addr := r.addr;
vdporti(cpuidx).wdata := r.wdata;
if i_dporto(cpuidx).req_ready = '1' then
v.state := dport_wait_resp;
end if;
when dport_wait_resp =>
vdporti(cpuidx).resp_ready := '1';
if i_dporto(cpuidx).resp_valid = '1' then
v.rdata := i_dporto(cpuidx).rdata;
if r.write = '1' then
v.state := idle;
else
v.state := axi_response;
end if;
end if;
when axi_response =>
v_axi_ready := '1';
if r.write = '0' and r.r32 = '1' then
v.state := axi_response_msb; -- burst transaction
else
v.state := idle;
end if;
when axi_response_msb =>
v_axi_ready := '1';
v.state := idle;
when others =>
end case;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
o_dmi_req_valid <= v_dmi_req_valid;
o_dmi_write <= r.write;
o_dmi_addr <= r.addr(6 downto 0);
o_dmi_wdata <= r.wdata(31 downto 0);
o_dmi_resp_ready <= v_dmi_resp_ready;
o_dporti <= vdporti;
w_axi_ready <= v_axi_ready;
end process;
o_cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 80f39bf15b769ca8dfcc34d739f0cdb6 | 0.561769 | 3.218609 | false | false | false | false |
quicky2000/top_chenillard | testbench/tb_chenillard.vhd | 1 | 2,820 | --
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_chenillard IS
END tb_chenillard;
ARCHITECTURE behavior OF tb_chenillard IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT chenillard
PORT(
clk : IN std_logic;
reset : IN std_logic;
button : IN std_logic;
led1 : OUT std_logic;
led2 : OUT std_logic;
led3 : OUT std_logic;
led4 : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal button : std_logic := '0';
--Outputs
signal led1 : std_logic;
signal led2 : std_logic;
signal led3 : std_logic;
signal led4 : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: chenillard PORT MAP (
clk => clk,
reset => reset,
button => button,
led1 => led1,
led2 => led2,
led3 => led3,
led4 => led4
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | eea0b005fd93c311c9ed3028a2177448 | 0.621986 | 3.971831 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ambalib/types_bus0.vhd | 1 | 5,156 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library ieee;
--! Standard signal types import
use ieee.std_logic_1164.all;
--! Common constants and data conversion functions library
library commonlib;
--! Import SoC specific types common for all devices
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
package types_bus0 is
--! @defgroup slave_id_group AMBA AXI slaves generic IDs.
--! @ingroup axi4_config_generic_group
--! @details Each module in a SoC has to be indexed by unique identificator.
--! In current implementation it is used sequential indexing for it.
--! Indexes are used to specify a device bus item in a vectors.
--! @{
--! @brief Configuration index of the Boot ROM module visible by the firmware.
constant CFG_BUS0_XSLV_BOOTROM : integer := 0;
--! Configuration index of the Firmware ROM Image module.
constant CFG_BUS0_XSLV_ROMIMAGE : integer := 1;
--! Configuration index of the SRAM module visible by the firmware.
constant CFG_BUS0_XSLV_SRAM : integer := 2;
--! Configuration index of the UART module.
constant CFG_BUS0_XSLV_UART1 : integer := 3;
--! Configuration index of the GPIO (General Purpose In/Out) module.
constant CFG_BUS0_XSLV_GPIO : integer := 4;
--! Configuration index of the Interrupt Controller module.
constant CFG_BUS0_XSLV_IRQCTRL : integer := 5;
--! Configuration index of the GNSS Sub-System.
constant CFG_BUS0_XSLV_GNSS_SS : integer := 6;
--! External Flash IC connected via SPI interface.
constant CFG_BUS0_XSLV_EXTFLASH : integer := 7;
--! Configuration index of the Ethernet MAC module.
constant CFG_BUS0_XSLV_ETHMAC : integer := 8;
--! Configuration index of the Debug Support Unit module.
constant CFG_BUS0_XSLV_DSU : integer := 9;
--! Configuration index of the Debug Support Unit module.
constant CFG_BUS0_XSLV_GPTIMERS : integer := 10;
--! Configuration index of the Mikron OTP 8 KB bank.
constant CFG_BUS0_XSLV_OTP : integer := 11;
--! Configuration index of the Plug-n-Play module.
constant CFG_BUS0_XSLV_PNP : integer := 12;
--! Total number of the slaves devices.
constant CFG_BUS0_XSLV_TOTAL : integer := 13;
--! @}
--! @defgroup master_id_group AXI4 masters generic IDs.
--! @ingroup axi4_config_generic_group
--! @details Each master must be assigned to a specific ID that used
--! as an index in the vector array of AXI master bus.
--! @{
--! RIVER workgroup.
constant CFG_BUS0_XMST_WORKGROUP: integer := 0;
--! Ethernet MAC master interface generic index.
constant CFG_BUS0_XMST_ETHMAC : integer := 1;
--! Tap via UART (debug port) generic index.
constant CFG_BUS0_XMST_MSTUART : integer := 2;
--! Tap via JTAG DMI generic index.
constant CFG_BUS0_XMST_DMI : integer := 3;
--! Total Number of master devices on system bus.
constant CFG_BUS0_XMST_TOTAL : integer := 4;
--! @}
type bus0_xslv_cfg_vector is array (0 to CFG_BUS0_XSLV_TOTAL-1)
of axi4_slave_config_type;
type bus0_xmst_cfg_vector is array (0 to CFG_BUS0_XMST_TOTAL-1)
of axi4_master_config_type;
type bus0_xmst_out_vector is array (0 to CFG_BUS0_XMST_TOTAL-1)
of axi4_master_out_type;
type bus0_xmst_in_vector is array (0 to CFG_BUS0_XMST_TOTAL-1)
of axi4_master_in_type;
type bus0_xslv_in_vector is array (0 to CFG_BUS0_XSLV_TOTAL-1)
of axi4_slave_in_type;
type bus0_xslv_out_vector is array (0 to CFG_BUS0_XSLV_TOTAL-1)
of axi4_slave_out_type;
--! @brief AXI bus controller.
--! @param [in] watchdog_memop
--! @param [in] i_clk System bus clock.
--! @param [in] i_nrst Reset with active LOW level.
--! @param [in] i_slvcfg Slaves configuration vector.
--! @param [in] i_slvo Vector of slaves output signals.
--! @param [in] i_msto Vector of masters output signals.
--! @param [out] o_slvi Vector of slave inputs.
--! @param [out] o_msti Vector of master inputs.
--! @param [out] o_bus_util_w Write access bus utilization
--! @param [out] o_bus_util_r Read access bus utilization
--! @todo Round-robin priority algorithm.
component axictrl_bus0 is
generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_slvcfg : in bus0_xslv_cfg_vector;
i_slvo : in bus0_xslv_out_vector;
i_msto : in bus0_xmst_out_vector;
o_slvi : out bus0_xslv_in_vector;
o_msti : out bus0_xmst_in_vector;
o_bus_util_w : out std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
o_bus_util_r : out std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0)
);
end component;
end; -- package body
| apache-2.0 | b98c09b7e3fc58c3bb87e056d0da1f8a | 0.700349 | 3.341542 | false | true | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/axi4_rom.vhd | 1 | 2,611 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity axi4_rom is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end;
architecture arch_axi4_rom of axi4_rom is
-- To avoid warning 'literal negative value' use -1048576 instead of 16#fff00000#
constant size_4kbytes : integer := -(xmask - 1048576);
constant abits : integer := 12 + log2(size_4kbytes);
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_ROM
);
signal raddr : global_addr_array_type;
signal rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
cfg <= xconfig;
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i,
o_xslvo => o,
i_ready => '1',
i_rdata => rdata,
o_re => open,
o_r32 => open,
o_radr => raddr,
o_wadr => open,
o_we => open,
o_wstrb => open,
o_wdata => open
);
tech0 : Rom_tech generic map (
memtech => memtech,
abits => abits,
sim_hexfile => sim_hexfile
) port map (
clk => clk,
address => raddr,
data => rdata
);
end; | apache-2.0 | 39d3f0665a3f379cf96ed9f72699c79b | 0.643049 | 3.413072 | false | true | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/arith/int_div.vhd | 1 | 7,894 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity IntDiv is generic (
async_reset : boolean := false
);
port (
i_clk : in std_logic;
i_nrst : in std_logic; -- Reset Active LOW
i_ena : in std_logic; -- Enable bit
i_unsigned : in std_logic; -- Unsigned operands
i_rv32 : in std_logic; -- 32-bits operands enable
i_residual : in std_logic; -- Compute: 0 =division; 1=residual
i_a1 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
i_a2 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
o_res : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Result
o_valid : out std_logic; -- Result is valid
o_busy : out std_logic -- Multiclock instruction under processing
);
end;
architecture arch_IntDiv of IntDiv is
component divstage64 is
port (
i_divident : in std_logic_vector(63 downto 0); -- integer value
i_divisor : in std_logic_vector(123 downto 0); -- integer value
o_resid : out std_logic_vector(63 downto 0); -- residual value
o_bits : out std_logic_vector(3 downto 0) -- resulting bits
);
end component;
type RegistersType is record
rv32 : std_logic;
resid : std_logic; -- Compute residual flag
invert : std_logic; -- invert result value before output
busy : std_logic;
div_on_zero : std_logic;
ena : std_logic_vector(9 downto 0);
divident_i : std_logic_vector(63 downto 0);
divisor_i : std_logic_vector(119 downto 0);
bits_i : std_logic_vector(63 downto 0);
result : std_logic_vector(RISCV_ARCH-1 downto 0);
end record;
constant R_RESET : RegistersType := (
'0', '0', '0', '0', -- rv32, resid, invert, busy
'0', -- div_on_zero
(others => '0'), (others => '0'), -- ena, divident_i
(others => '0'), (others => '0'), -- divisor_i, bits_i
(others => '0') -- result
);
signal r, rin : RegistersType;
signal wb_divisor0_i : std_logic_vector(123 downto 0);
signal wb_divisor1_i : std_logic_vector(123 downto 0);
signal wb_resid0_o : std_logic_vector(63 downto 0);
signal wb_resid1_o : std_logic_vector(63 downto 0);
signal wb_bits0_o : std_logic_vector(3 downto 0);
signal wb_bits1_o : std_logic_vector(3 downto 0);
begin
stage0 : divstage64 port map (
i_divident => r.divident_i,
i_divisor => wb_divisor0_i,
o_bits => wb_bits0_o,
o_resid => wb_resid0_o
);
stage1 : divstage64 port map (
i_divident => wb_resid0_o,
i_divisor => wb_divisor1_i,
o_bits => wb_bits1_o,
o_resid => wb_resid1_o
);
comb : process(i_nrst, i_ena, i_unsigned, i_residual, i_rv32, i_a1, i_a2, r,
wb_resid0_o, wb_resid1_o, wb_bits0_o, wb_bits1_o)
variable v : RegistersType;
variable wb_a1 : std_logic_vector(RISCV_ARCH-1 downto 0);
variable wb_a2 : std_logic_vector(RISCV_ARCH-1 downto 0);
variable wb_divident : std_logic_vector(64 downto 0);
variable wb_divider : std_logic_vector(64 downto 0);
variable w_invert64 : std_logic;
variable w_invert32 : std_logic;
variable vb_rem : std_logic_vector(63 downto 0);
variable vb_div : std_logic_vector(63 downto 0);
begin
v := r;
w_invert64 := '0';
w_invert32 := '0';
wb_divident(64) := '0';
wb_divider(64) := '0';
if i_rv32 = '1' then
wb_a1(63 downto 32) := (others => '0');
wb_a2(63 downto 32) := (others => '0');
if i_unsigned = '1' or i_a1(31) = '0' then
wb_a1(31 downto 0) := i_a1(31 downto 0);
else
wb_a1(31 downto 0) := (not i_a1(31 downto 0)) + 1;
end if;
if i_unsigned = '1' or i_a2(31) = '0' then
wb_a2(31 downto 0) := i_a2(31 downto 0);
else
wb_a2(31 downto 0) := (not i_a2(31 downto 0)) + 1;
end if;
else
if i_unsigned = '1' or i_a1(63) = '0' then
wb_a1 := i_a1;
else
wb_a1 := (not i_a1) + 1;
end if;
if i_unsigned = '1' or i_a2(63) = '0' then
wb_a2 := i_a2;
else
wb_a2 := (not i_a2) + 1;
end if;
end if;
v.ena := r.ena(8 downto 0) & (i_ena and not r.busy);
if r.invert = '1' then
vb_rem := (not r.divident_i) + 1;
else
vb_rem := r.divident_i;
end if;
if r.invert = '1' then
vb_div := (not r.bits_i) + 1;
else
vb_div := r.bits_i;
end if;
-- DIVW, DIVUW, REMW and REMUW sign-extended accordingly with
-- User Level ISA v2.2
if r.rv32 = '1' then
vb_div(63 downto 32) := (others => vb_div(31));
vb_rem(63 downto 32) := (others => vb_rem(31));
end if;
if i_ena = '1' then
v.busy := '1';
v.rv32 := i_rv32;
v.resid := i_residual;
v.divident_i := wb_a1;
v.divisor_i := wb_a2 & X"00000000000000";
w_invert32 := not i_unsigned and
((not i_residual and (i_a1(31) xor i_a2(31)))
or (i_residual and i_a1(31)));
w_invert64 := not i_unsigned and
((not i_residual and (i_a1(63) xor i_a2(63)))
or (i_residual and i_a1(63)));
v.invert := (not i_rv32 and w_invert64)
or (i_rv32 and w_invert32);
-- Compatibility with riscv-tests but loose compatibility with x86
if i_rv32 = '1' then
if i_unsigned = '1' then
v.div_on_zero := not or_reduce(i_a2(31 downto 0));
else
v.div_on_zero := not or_reduce(i_a2(30 downto 0));
end if;
else
if i_unsigned = '1' then
v.div_on_zero := not or_reduce(i_a2(63 downto 0));
else
v.div_on_zero := not or_reduce(i_a2(62 downto 0));
end if;
end if;
elsif r.ena(8) = '1' then
v.busy := '0';
if r.resid = '1' then
v.result := vb_rem;
elsif r.div_on_zero = '1' then
v.result := (others => '1');
else
v.result := vb_div;
end if;
elsif r.busy = '1' then
v.divident_i := wb_resid1_o;
v.divisor_i := X"00" & r.divisor_i(119 downto 8);
v.bits_i := r.bits_i(55 downto 0) & wb_bits0_o & wb_bits1_o;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
wb_divisor0_i <= r.divisor_i & "0000";
wb_divisor1_i <= "0000" & r.divisor_i;
o_res <= r.result;
o_valid <= r.ena(9);
o_busy <= r.busy;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | d6f5fba8eff91384e006c21195f4fae4 | 0.539144 | 3.158864 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_9P6_50MHZ_SCH/CLOCK_SINGLE_RUN_SRC.vhd | 12 | 2,560 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 07b02a055f33b05593c2b29f14584580 | 0.553125 | 3.110571 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/logic_sshft.vhd | 19 | 29,996 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ccZ+VLNSpHtEulGuEKVDJLwcsmbh6zDXYYsSS4iGpirAhbXM3BP50jl4c3979n2YR8HDHLXE3QbX
SjQosk5Agw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
b11dY0owYoWaWqrEwg1RlK8C89M14CAO8cS5xZSZiTQ60prhJpRDDBFmDC0asd3vpmdy6xip59nG
z+R5fGAzPFXPwL2mdZ9u5u2h5M7NuqWsd4/PSQwIb2Zc37lWRpOZZLKl9FzYzSgF2YNv5/jfYnLz
E/n1SJLECqBWTvKh2d4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NDjOIJz/ezAa2sanfwA4cBF4MUjfAWwRdI3fhKW6WomA0dTdlLUaUk3d7HHvjRwYAFZbgsshlvRP
BFUgnI13aIFlirt9v75NS6zbC9iHo4+u43o4DjI7erTR/V7n1KuL02bh7njjYqFW2TM9DCTV7yyk
HpE/bHTEqhTIUHhN3s21EIF7fvF256QO+AgjOS/tV7UeysPdiXp6gUoJ4fZfor+WTfQVkJeKE9LJ
0zpHP6pDYIRgknpLIxX5LP5O6x+a+epaip1DIHLGwD6CJeBzPxV1RVmuuHt0FXHAwR75O/YbsdQ3
OLvEz7nBONr7GpqlRI7TlZBuj6FdMW9zmU7ONA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
23D8eH9xZzeJ+Ojv/tdSxXVchNNJmk24MJAcRI99YbyO8+bv8JOBxvZhz4Qlt9qTY0ExdOGGGFmU
aQ35HO0+71woQEgUY5FOSxt7Z+X3DhAwHoCaoUzrhIzpo/Vibci8Aq5CktZeDbbFyKqw4AG3L+HI
gLdEde8Lyo1jpmEidTc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MgM0EI48WvFKRy0diETe4cjudrS6vIt7158toM9vdseTaMD0TZIog1UmAGNvdE72kJ9RDo475e8B
1F5FJia14jZNw9OSBZ6rrUB6Tjk4EmqoYQgrN7x0TfSl9ybfwnnJEUbiXZrL/obnsUVUxuBuPHw9
KwRIU7YdWp4ONQdRCD9vZVkexu3R144yonCk7ZQbQol5voGa98xXkFS5wJ9AioaVUGfDCcHlVgYv
dd/x2xkSx6aLm3qbkMFW3ZMl2N86VVdkP+mRZE7JGaPyJ93l/kjtm21dSkDxSaPAALmdawaPAmzL
9Uhkk9hs8yLNZbslAd/6iUfM8JK7nIIDO1E/WQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20464)
`protect data_block
TW/IethxANd1x1LxUanENC85J4mbEEcuRl2PechJXu3cPAkaoTjPT4jQVua1Vov3QlcPyi4f0mHs
vhvw3qEl3smG2Y/0W+5GsAWuExcVnj1C6QDwZdDGwt14TaQd+Vj6fiqaVdQJPjTQrnkZFgFe9oFb
XOHKb0AzCbGEVm5a5Tn6x8ZnpF6o/7rco3PavbsmINOrh6TPYVEfRg3j3zahCBmFZWlCl1mxa+Mh
q39JB6o1mFvWMOOrKrzpe2ea+GpfmFsB9jsMWbiZT0cqg3Xpe7xsQGE/xFcRYmg/SZQ0Tmd7knRu
xeRvkGqhdsQ/MJmFrEoXm9I5yb9eUtFTsSj2PIRGYFDpbsSBBCTW0DXMcZ51AodoQX54N6etS9eH
jZABDJzFoa8Y0IJSzCN6c8sH+D1gc38f5duucm79U9DTCCGyfa8RvBbVvwB6Xo3mLBk1J1jnevJa
teNJ7WCVNombKGfIKJDEyFW+l5tvHzlv4/tn+he3S/v9hJnD0DHZd0AyXVP9DefUYEZZBVuI5DQ9
P/TaCjds9E1L9jjaifoVawZ9Vy/0P02b4myTVq26zKw5/9HVJJgHkiIccW3ukvlWK/ZFySGH0mZ4
aylmLRt4QjOnqtfJg0JaNFrYNFdK6QeKCpR0+q2im3tVHqiNVVenF64M8NiKLNmqHVK4ZJCra7ZY
gaVXyYyRNeHbMwJCEm+dOOZrCepZoP44Ed2zEGy2eFmZGDz7pjYkQWOHL4cWYLzCxUFjni6qHLMQ
RlMWOdUzPwpHAJ9WfVLj0lFLvFWWNWBDo2014DzOlKfMlgq+J9TBuWWVE3Tzo+NXG+oFw2n1uxkD
6+8aWR4BNaVDvuYm7xzvLi2CuDN1taddnJ5Th2IRvovIkPGUGgWcUm5N57MzOXCDFqZ265z69hfQ
AzS27dvaduGyVvaQ+DjvCkcKsx9iAHglQ9Vx0XyKcSytInPobd8gGpsWGrUVRF820aVVLWs99Jo9
CJl2OuNcMA4AWYoi3ji/wnB3KtA5upFR5lUOYpzpCdAW2b2KW8DsjFQgj+wFdotiz3hClatySpB7
Ka1yrNpmjSTsbw4pe5UvTTvf7nbYJ+KtatwLJ3lDJw5uhQA0zUQr8ImyNR5Looar7DraFkmCm6Pi
yRLxc0FYYPMYvxRH6GlxCHOHvG6ZH8y4NkHDYhjAe09roBMvODBubT9T/Jiil4aWEaQxnnzgDM2F
BRyG0lcSWkgVM4tidyusDMDa8CdFg7rjBm4hBfs6ymDq79cKOiLQNJ2+pv2Lj9qOSkxg5HZaBOrl
yERM+sfBLzq8WhXW+LLtfvVNUaDBkRWs4HC25UOiUNrJpMvKgfwGbOnMeWKMZlFG4kCPFPp4RTUa
YC47ndKGfol5eVxIWUyakEDif2MQzT8wM/E4dCKqvMry7ICLOqwqeODHkqHIFN1sUunKREVhjt2h
+QhMwaQIi30Iaq6FlCI7s8+fJ+eUKf01vCIPCaV60nuX1fYhfvvVzE6UhZZ8cBaehAA9rUR38tQf
EPQVMQmA9LjwCUspKXyuKAGIQBde0PIosUXD5iryLNk1aKGo8CQTVYlt+vNfX5LK89GbLyRlZWtv
0dOHQEk+9Zni8aoY+uYq0wlphwVKOs/xBs+UniHgtVFx+RC2xfQeXiwlTLC32FOTAtyLpy9UPAfx
Gt1dqi59Q3J/9elngBfLWoWUEJsLhPP6jLN5H6VCyCTDQs6G9tsONI7FZfcEbeKtL22VNK6EvcgJ
hcA26ubc/s0ySqP9LBoZOtp1h0V0c3huvlZQJ14sKR1lRXuVXlVhaXVyo8CifebFCgsEzsj6JexI
E3KeT2EsG+JyOOVfopBEy3B4m8RP6VKe/jDXq87SAH+ITevtorky19egCuCcbHaNWpRCvApah/rz
EoMSXuuxERatL1B0Y6WlYDPQzbaOWlPdcOV2UhZjFrAFjkQtR07CkEGX3wf4FO7ulrFTzuP70LlT
umQ6gAt/La8959cFbJu7VbxSJJK1GugrMwdn44qojABmjwuFMmPBWVkDiRyHxWVkRbi8cl13ZUd9
FfaWgskCLNokIFpmmQLdYR7RMWQnup5uFxjtoQ+I11Yd37aorKzak2kthy+zE+y0ubc4PPzg8GAm
oKT25WwZUWjp+cthrelbKfNJBQdwE0ub7nmMPqsNbMSQYEeNZYhgGJCFRK/dqhtP+K1JwG7xpDGV
6k04y0MS4LyC2TxzmE/MNg2LRHXvgcHsSquaGMYO15hUyhGG+HykTmDwilXmQon8Mjzw8dAUF41+
2VRye1lfaKw+ti0pDpkXE5rXEZ3UTVQ6WUKcqwmklqoPBlFF0nV38sT5DG9a/Xf36ZLNhIGOCQC0
lwK+szvZPPk87Yl7NPg73Z+OHvf014JZ2gbSo2gRM1etbM9u3qCDjZjT0291A4g4DcmNL5C0Rma3
X3gzFGnS1N9H2DE4XZQEvTdhbzQlG1tubS1IyCMPoJ/09AC1UCK4LbAZgZyEu3w6mOVY6RyzikgD
hKv6vefi89iRj12GxPMBOjx0hwPM/u2tMHEOWGj0fiOthUIL3e7loIiqSHFdOxgRH32jJsUSaM3T
kG/+JkjbocDRZTTbuTWWnVl+oeSNihs07U1unbUDnemRZl2TpVwM0dmeGVJrvR49Y8OqJ9HZBCcs
69T05283D4CTdI/DRm884PbICpMrituZ78uy/oVJpDf6Mx0o9Y+3vS89RRdMlA8H4o5A70jPrwP4
rFtXsc0CvBOQSABU0jRsyHJO43yi2Yc35Sf05iTeDeog2lu6tx6pRlWrkVRClHGwCFOHR9iqNtoz
zQIeCvH8U/Q7duL0o5HWAisUdenOLjC5efveF4xBjpV3t6Anab1MWcQQK7q1DF2P1ntECj5Vtcfz
rNB9zKsPY5brHJOWQ4LFFrA8sAuPUDGSVnX6eR3vH4LwUCzZLdmUuKu6ucaQ5ihA/2TZ/yBvDWaL
aU6zxRfwBmTEtZ897RlFT0pPYnDs4omfpMgC80RiXxJ0TKONAokQyPMfSp3GOEyaoeOC9mBvxZyW
msytibpjdpyhuMho/RMk/b81HegQU1qb1gKtV2EcbwNZbMAtorxtoStynoZxde1SUpyNvQQETMGh
CaF8SM0ijlLiL18AZVJTGTDcRdVU3ax59nf18z5BMdko+zHY68zk54J7YNFPMJRrE4reoYaAPpxY
2+9sHDaJbDiUmZQEn4/Mbbx/8/vzRggNNTlrZGEqlCXgxF2bfemtCzfNtQ5uMbhkvDGlkyrnV1Zk
sfY2voF3eUuHBAy/8HbhZkl6Urm8UFMajsPnDXNos8fnl4az3BEsRRiWeJtF3c2L45USYB8ZsMVC
Xsp1t1yrcoZG3YrB9fMomk7vqWEPUOSWTtdiYVYuRo9i6hHIRIZKLn9yAPO9Xx9jCk5knv1zKRSt
M49AisWcEhCtODimBYRJSgEyxduBvhpOSxbeak/5gFddp8eGZDUy0cf8Y5xkEMfmgvCVNAvDq7iT
GhorvOM2MWtuVOaMedpLynDjLWobskxbLH7g4Oss8TfqWXFH1ptvYQ+xUWIZNqn0HEsQzNs1FuYQ
BcVpyvSXJFAR6BX3581ijGerwVZ4F1jX8a9ed/RYgPSVLmaXCv3TidtiYpuH1I5608wQO4ct+kMk
nQt4yxXvDYEm0Twpbj/Mv60d7NitNn04khLpL/tMedTTJq+2DdyTG+TFTobk2PqLaIKz3TXUdF44
YfIhBSMJGXCHR3AcA5zs8Qvr29BIdbe9kUHteAq8OB627n7G7VdKh+6XTL36tGSyqvmhVGXBKg2Y
SAsc6q6T8SQV8dD/aLwIkGcz4F/sGFfroT03bHYrDEKayBPAm4c1gXb3YKCcFoT1DDiVaqWR3Bjk
djkide4b6BHr8C2c2PwPeMbrfbVKE0nch2+ARj1wIuVgPFTwZBc20s9zp9B6Xf6KGUNExg0xq4i5
6z1UTP4Jj+YiOd+CbVrSHlS2/Ng8mxeF95Re2LNLdJEIc37KwOm4dLPNXoQDqKf5tEDlX6A4rHHH
odHVlEGJ0aWRG3Qk/UmYgJUp8AKBQKMUN8wh3FL1sZPHe+RCDQ9xQRgy53QCjwMgQ0S3Sz574BQ1
n0Dv/NpJpAmXmm/BNoRaCdXL8viq6Oa561ANRfXmA0HCeyF6Lh+hD+v0GZ/UtvHiR+CnJluUCDdm
mQEqbbH7AkytOs2MnYdt07RG31Xc0P3viczq88I8rsbGMzdFOTPVrguhDPQl6GuCFKol8fG9LMko
pDusLTXaxmv2ustBcWO40T0I0+Do5m5IY1fjqaRElFu04p+ORRZs3/JHtcbuUcjMprgsb+vd4luN
d/44FZD63qZLpHTgcF1jzEZeAC8H8d2AJ/h9uOD/C7I1pr7wiO/115p9vPclU7SXbqgXrIR/VYRJ
O078G6RnFBzjeDAPpEryrFSoFa8X4vE6Loh2mZWzBWla+hv/DgTWgRgRKF3O/3F/wTf4Y35I/vXm
QFo0zdDhbHTTETx03tNUU7mkGjyrWdEOPP9wSYq9vuROQiy/eBQ/lXdZS9KKDMwFa1x8pNCgGWy6
wVAF3IIUZ4q0pTpwsJ0CUpIH8HFERzi298f+b63kMESuE1pcKc6vXVYUwyPswO0a02f84hEizNyZ
QycVyi7bGwUscXUZD4OJdxNLOE3aWAxjyXlcM4bCMnqSFNzb/HYLMUhAT4gjhWSxDSswn8+Khc8M
utWlJW6fOsn2g8YmxHAkOWoXr1R341a3Ki0NANunAlc56LIk3OOgrdAiATsKfWPFsmYNLU+YutpZ
Q2f8jXBY35a40r673uON0ld9BXl+sD5X00JaAGTFpAcuoLDikCLxR2+ChOKjmNZnj/GMnUEI4v71
EH8lPUBsbGahWVP4gzPjsmVzlwm3u2O/irQkQff1QJky1VO371VUwSWfXx28y8VhSEARd4otjgip
cJM8Pw+85yWeaLV0l3nGnv/Qk9HLraSvcC2yo4g6ynqRGQz0uF4rGtlrbMXS2EHpb6GTF2guODUb
hJ7TRl1tPxcpyRhMidYBqebKUtDU4QO9ZH6DGjF0sm2we0g5dQxLPrA4x7W734DjfETe7jCjwvK2
sueBxJezFmUEIiJHAOF/v9KFjofadvR7wvBoMVsV0KMpzmQM7qBCiw9V27U91wmITGj2/QhPt/6G
5V17Tw1j+G7cLexop+DYX0zkVa++ME9Nc1E6wQppb1E11sodULU4Hu6aGBVmJlAv/kocPsRik9Tg
dgasltebyjOWMDFyUvHOxfZgpwSC2+4KfhVF1gIE7OjJl/w4HUBX4eraZgjjcc8Dte6tp4JhqWXU
eNX85690jY+25e2b9LhAzBgrLYVGFrgAel1kFBZ1XHMtEXOTEMDEue7aO60u0hXxD7SlE8Tx/89H
qWa1Wh7hQjCkJOygksZMfCr57xVyc/zv2AFy80rL5IJgQZtkjvVVb/FwwheE+Emk4Ahk7Jp7jRgQ
Rtgu8GxvNiAiwfSXmuSzxQgqhJqGRV/vvpGZKKKMRZZGRcjllmcIBrQJiG7bfvNNJfQ9Ynk6pyu1
99+Bw2EgZE0Aysjz1dJ+kAkyLP1t4tOLjJ0twBGvEuY3vNLh1joGZblr1iTeh0U+5ZwHnDEGKrb+
zK55k38WuqCNVjNWXnI9rk5rA25yg2LLwPoql4Jjwcbplshj2+SvegBaa2NaVDDpIVE+pTFTB/TS
BME1EA+8zEw3gKyODulB6ygcTPBfjXhDfSe86HsGIAmvslZ86kzmSX5+sHPrc+OrqAeDGiU52Bo3
XhdzhV+FQk6G0TTbUYS3OUlAuy0mtLZuGrYkkDmg22rOJi2RS+Iw/W8mqtlNsNbKZ/bhECyeMxit
YfpuNIsU5akf2nzr6QGs+zeFaeJY572hIkQ7f6OTuo5X474KXVN1wotNjUsuGdIbohKfH9Y+8lQD
XqwP8ZEcYhZY0nnTGziwDymkaI7uk9KDk+6TG8LTBInDkP3eaVr2aFGsHTMCoywoy6vumeec57Ku
jMt9K1akTfLAo3vh37W2wtqVpBhSNeyylGW79acMFdixV8Em3YbUkIzqGdIXD4DVHL/bvU10XCFD
cDkL94su+EslsFPdv0YSIfAkD2OicZMDdrQq+pw4JR5Qim5meAM/U8bBOWv+6pLFAq0XLMkV3zDV
yKuHfCn5dkw7wZK6aoiq3qlokQMUYw0CfUeDWT/Ykp4iZew+5GIgdf9c2Q7GEhhKmT9PTLmG7E1P
+JjFj2pCYT5aPcPf9wbmJTqp1DrCa6mCLJHGTXsy+e482Owk5KFzb5UB3gbr/Io6GtjoI6gKdpgj
owuvmYDN19AB/g6mXVf8VU/rWd2vECd46DeEwmaJUfc78ihGk3q9P96tw4m8RACa5uYUREhjQ50y
SXFnjDQM3C5dcHtBz7/kZ8YfelwksfF1C3vcffLks0yPPhrTvapNGtWAu4lNW2fEQ2QfFuhRt4oG
LS7y0092OSveqwF8uH6J4yDde+AqDZ0jvP1bM61+WNTuRsTHvjM3NauKKmrbBQAIXrbwEjSecyxM
g9lVGe6nF5l6EGaIaH7CRdnPbHU7QMOswSrLn6PlrHZ2qUsgJXA1h3bncSfX4docReYF4+YJD+Qn
SajmQ5b3aY5aLraZLUHYcSlIQh1T6PoiVovOfIcRfsGNQ72QveB8UlEghWJFF2kh6XbIDuQYKFPG
eEZkSzlK+P8t8H3cyYC6r2Z/hXLkqwnNx9qQDNHGSm1NTVdKEvAc0ahpcffgCFbr+wal0hFSHlxf
8OunJLV/4wjruZwdEwD4ki/tEAcIo/AZEhA2uLSa9lb7wCBEYUt56tQOSsrJn57tenkcxLqmqIjx
aoD9O/jplsCr4JsXJDPqeZnjixXgsKg7vEVOOrwKFYCZZ+Hf0CUXPHNeUUiCzvQcZ1xGtWAjCm5Q
yvnHWRMg6iqrLFQoJ5iZMA9+RMC4MO3SuQ4dJ8ZDsxAsBnMsvTrGn8VDJSuuVVlynC0FdhGMMnvR
FXPAy/NJtTsXXj4sIJj4uXlHKyqGd72kKeJCwVKepSd5RHXMJFuXN1tnFmj+byWQellhq0/GF4q/
vQmOd3NG8wZmsFK9uKoIvkXeBB+ibRCeZ3OTglXjU8uolEx6dsXtaGf5yvODuxI63zZJmkNK2V2q
DyNJuyVTAHMQF0IIf3m8CaT8slQRg+oAJGgQA6mAsFmON/fLar5IP54NBxzP96uH+F17Y5DaRvDK
hfelzO/oQa+A6RsFYj6ozDIhzgrcKkmxUgo0TekPgeqLMZSGHNK7romJcvhxcCTWUzKSA6Xh+gkb
lJXguaKwNrgUZVUDNFHgHjTUzPWZml1Tx9DueTvPf4plz75Ymavrj2JTpgnC2azBV1IKG6inebCy
CYfqy/8SA0D5lHKQTBotNIRu/SQCKDkGwaAAGos0OyWBXHzMvockUpR/4wfPZi3YqeHoIrm7or4e
HXVGysuQkUj3VXBHwROROOytTz9qAxQUr420cX6dxJURwTAN7dTSYZnYgykVvaLwfcgxwA1IwRpP
vYkl3GsEqRsaWK+MS67wm7Q/3RsHlcvQWOOJk8WkFJiI01QkEZ/a/jkapeq4gVq4upYUN01BXJx9
+vTpGhpAEQl/+RiDyac69XfbTRLTOT5VxbOO4/5jomZhgqTnnFwbNnWWOtd0I0lgkWSjNUrOKHnZ
WNT8rvMBcXMN4v3T8H56XBpCwsmigQDAiM2p1M5XKAQ8O3XotB0TzMcjqnDADLQIzJj+EtEeHT6K
vBD/0VaEuWmXYLmOJT+JJ4MU0HCHbEaDRW/c1nXqr6GJkU4Kkiu5k7Un9h2idVzd60fRG3KzFYpP
LCSVi4kKznrj+OwyEdsjr02WSNkRrEcbwTlCgRinUcT8PSrsToSKcCNGfW62idZGq/3WxagOECM4
YjppDMIWLy9XkQsNd7W+CORz9BxHjzHzHPEEGL0pjw6s0MNueeQNDOviezLj3KE+tzW5mI1cSMM6
hZR1ADRuW9U+GzZ7bLXMVDd6+nRPxsn+LjxSr7sdTp//+XpAIm5kIna5gsrZUtyytLSPr4q52713
A2s3uQR0yAH9Lf+RAwCbbcJuNhw304wu4VPWpxOP54QNrFHgBH65NWH/1jo0mdPV/Ga+V6+b7Rqu
s2tGPfWbpa278RAS0tXmnU6jRCqA9eVj1nfuco5PXg3hjPKoo/0J9kMLnNkA0HKFtxutYvOIsCeM
LD913yyzk0AZcm2mfOwmmlW0LH9cdD/0aS6TFZGFRAYnlrsgunJ8wZEKfhoLJhUckkwSqVWwEDMx
OLzPljrZx9YGgcEAtPpKAjqqNUiyp8Y43lPc11TpF9ALGCcDNCjYz5OaQdTspAIYmhOsO3Vl9ZmJ
iMdILa3u4KacyPtXiVYY7wYqrpedLJVjdB3WFebon7nojqlPl0UWwWgZK+iBsoZNYtAo8H6Q5gvz
IcQsLpqdQSBoTBolVjqYd3Et0pEnPluWdc20hkn2dyTTfe22McOcseIsdkh9mVpG1Jxq4CP9d7/M
l96QdbfMQhaYfUmY65JHiakWLyNW5SdoYlwoygWlmC0cl0gdDePEXywE/VVwdztMoazlVs7MSdgb
72WBBUo+tOMuFbnRVEzjjfCfx7ZBV2eSzpTKvnKJL1V6lY3cMzRcrJ13r/kOrmxvdsRauwDGNzOo
z3QWxF6bInTv746LR/pcNWwx0p+QmNydha48RuWoNdD0m1jdlq6YRA7tpxpDci+DyeEbjsLL3Z9X
hsdO+c7u1MluEljhXx8TSYp4O9I2EcakwCl+z73CCEAOY4fo1m6G6vAs8JfOQ6QZOy8fVnQ2/WmG
q9ke387jXQRFZrvr/BYpufAMYvZXeCLocnwBrElLey+04SF01bAXdyjKvpPWc8pl4X7cj7Pgrn6k
c8+M8fIYLeBKjP6wlGH7eW5IkYgm8WfEPLeWHpcecw2ZRt7i1WZAJklPcmba/diFijDPinKYXojE
seBaU4H7gk2sY4RPzxQdlqwgxu7XAmv0bCC1ZZtdKQzjiAhyRxtxEy1azTJGe21U/y6iPeC6OeOm
N21Sa9PCSaxb/uZ5YhIFwC6Hx9/JqwD+QF9OzyZSWqE0NUlz+cCDXjni9yZwV6l2Bx1WXiuZsmbZ
D/NAE/ttvKGyK5DbrPEOW93wvqF3eh8iUOUMsCMVhda06YyOmhrXv5tHIxvQnoZPiuLT9fd0huA9
pKY4MoEkcEnQS9cjm9/ZIkwIs4qmiYcQ6GPmfEYm+jjlZUQZq/oyiKGy75h3TfLfqDxP9t6wOyOI
DbOD5XuR/tQiPcdC2a4lEuSt59+UiQ5Rsqg/w1AxRSmyLNQBPAFteW7nkPyxiPi1FIPMMgsXNr2y
f6eHI1m2ZPie/LOAxIf/Mwe2dNV5jXo9zpR96v5YSFj7geYz6TOCuI0JLDx8QIR/uqGQwh+RJTlI
cZUTMHj9U2Iv8cXZz/Gv63VvwEz4VmhxCaPMuup04WQZvWatXoGytJ3IgbxGbC1FbCS0IAFgBK+O
KlMgJSt+vLk+wAfRQGRLxkklmlrRuY3H4pWnqxiqMquem5vRRfuVGQCrrPnie8XEpuwOBo+jd9H2
LHx/ksByCUTHFyISSyIsue3Uf2Y1KSDY76ctQbhtbT06F9Sj618WikDswI4iVOY0jemK9YD87aJL
9VRuPG7QeAXur0yuVroejGZCBfVCBGlKTf1u0jdqmduA48DMTXsVchj3nw1fC213iATIZkCoV82m
om0QqIBPk56Ww9i5LfxpYrL2JUVLqpVXM5zWYACVAUg/h923Boo+28yQqZT4UMilkL6uNkQE3mRN
vF5dfktVDXVKNwtczZnDQwIb9MEL9lEjdxfokPAhECPhtpkcUJRy8/uc0qdNNEWzfaTLuOdHg17H
spMtGZ60QjN2dLQCFai5y1IiBr61w2OrhPOCbngSHE7f+obYdo2AMhakGjIXIE7WFKrAl2u3YULR
Gm01S7qmGyCUHvMbK2QbqYW2/7VGAPK8GOggJYe0IkAEPFSdOe/R3p60/tgWErGxbn6sFPPJ/9H5
8C6YhLvsSHm15JV5d3ZPHPpgTjAwU396LtN9BL2gHfkHgNLe7E3DGqKI4uEwpJNGkuGmTknibLOf
WoXpIZvetW6w+3sARDshScuS3SifWacLRyaQF8w23xG/yXwBiwv1TuhavVb7dVN99dbCTpTyPAHp
3lFpZQ67GDyCwAqEC9xpUyKdcoVk2EN86dssCTHHBFZmPVZoJSrPdxm1kZecKR4pqYFhRTYtIZzn
5qBX40mbL8SaZl8r26rfpuGy543ffkMp5GuE9ilIoCe0pC6DUefhxFqII6ISJRQRuGbz8UFB9Laa
ZncQ4SyQbQlrEu5R7SD9Ve6PjZjaP9Dsw/5FKVNBBJNl3s99hNnB+Uc0MfKkWD7SDiauH7VsKujR
4+6ObaW0G7/Qk1UgfOZjZtj3KrtShbiZMHxekoBF1k7PI/ZYLyR8u/Nzp0mTz4jHWh9g0CaUrmSq
6Ag+dWoFI79TxxYhZLoLK1KBjUnHpDTsL9cmEwpOzMy0v0d1t/MxzrVWn5vEKgbhb4IIZMFbSjCa
1B8ri0lo+MKip4LznRiHUdDi0peKlMV0HSogVVOtuf1XvnC3Bh76sNK0x/jTn2Xa3/uzHqG4HKOw
qdt7jlnIM5o1PX3Xz2YXe8mSTOKvOOVp6/LK+FVT352m+IH4fdhZnZ52Kh/vbVDbwNfgbNMFpKlB
Z8ZMlN96bOCYNOW295djQHWmdQMIYni41cnydcxeL+q/wTdRFPB/p8dghG6Lns5BUNUgVHoA57ju
4uPRZl0h+fFYFT/eQAepOqlHbg1vPJDegUMy8ebqbvmuy/1caTNES1IzL9UgkHdxcEPIvMQFtcH2
nK+5VBI6+q2k3ao/0kmBlWPkQiGnYi72jx4At5/SCVfCB9r8g7q7F4F/HPWwE/VoygV61Fdzwrgx
JiLj3PT3tJxN6TrWwN4olfkc543dF/8RzY6PVH2sSilgZSMSDybYS1cc1CHfuXr2zeRWu76/ta7g
fZrYRimxB+Xt6esoToa0Zkaq4RwWJN96uypj1buWmyh5w21EpbsjJ+nIdV8hU9HTPb6Cnux/OpL6
AS9/YlpcHNxvrmAc7qXRdaB65nkAVTmp1qHFlm+tXsrPDdwQmD9FllexfSqCi/OX7vQTCoM3JQ6T
PNkVYQPRgI0oeff14spajHGULLkQ2KI/hWn6XCd5o4+51/d5i+4ySJs5DkQqhkUFMXHJ0vu2n8Me
4nW14qcIT7tA1sP85VqZKqL0XPNtzeflHHbSFyxllYmppOrhfjYgfH4uVm2vi46/cJ0AYs8JIw1k
1W3tN8mqu/VYbp2QtaPNMSEhzA0qLM7398HHpt6JzFej4vE+HvEvf0wAmNC+yUkOrQ8ZhgvYgp/1
ae6v55URUFoGjibhZPViuZhGxFxrJP0YHQ/Uz5CfiaiBChHbx7BGYHtXp+GF4e6CRazDp5uQfWIT
Fk/gkNYWJGyC5IL+1jPJD1BlCR17zUviUgsSmhqQ47VSNVmgT/fnqF7x76y8sQ19X7uVWTBLiVrO
NI4dDzY/ZImgiiS+JtNd1AX2DrnrpRE68Jlo/PH2h1R5Okf/AMk6wbX/YUiLKRsA9U8/cfFbRuTj
DWdczAW/KYiSgsyqaOvDD0Q2qf9FO5ZDALjixkhyuobisxVn7uwUB9y6e7jI0VaV22FJuavjl2tc
fG1TCQEzA0v4RRB+l5i2pf2HfBH3lzoBSg4pSCDIT91hUNmiCsslsceHsmAUoY5yGnrczLWcItVR
5K4sno1YTvhbpEgK79pDjC0fKNFbx/bthgZLT2GRbSkYJ6PO85Qco9liEYibskuHr3QoLeSj1GoP
9vg4OYp0hawjVquJhr0Dbvl1oYdSTyZxYbGCgjErZuyWB+qaY29aS3LaA0qDXgQkHjRly544A5FX
0JoWB81OP5kFHPsuDsKSOgK+orjJ4BVQ/2ckjb9LI4JMvC8PkxsaVDNTQkrxAuJ84OfcemNUtxwl
95DadkvFNSz/lYGxTyYE/s6q/WO0yCWte1Az9YQz0HL4xWp38PivhHTSDYByhO9DgDlmEuQTYdI2
nlGByih36/X8roC5SxHaz4s0P9RyPk1EaSf7hx2t1bFUZd2d+G7nsnkmxjZSxMwAXvNviYGCVfYl
rJK3mnIWvS18PsnV5iqGtyPoAFh0i4TH0YRpfw5lkFuN2Iozu2PJNSUZzk5hfvrOWLrc9Lxe/wan
8WCPBvTsPgx7UoeGeHE1Ww8OeG6bFovM0SQaUbK8kK2jfC6CB0Q/oZEaW6ibhuUqQgYpFinzgZdH
icScq447VAcOzLh5fk9YuqIODwHm7znNSwPZ5rfU0JLcUoMbEx/XcX6cif4QE26qLwT+4z70dgil
d3mKxdzDk6STzxxJyY0g69S4ZCYdmamgA4GjtViFY+dt9ZVF2TYcaXlnVUWvpTinra/bvVGvB08G
T68mrmOxjWCi6r9DscT64UvCjm2SxR2OQ2eMeqvirg12om32++4mKtkF7m9vOgxVIMWM5M1kfmZV
327GRhZM6wNXWyhD/Uw7TeAhWaE4BiQhsOw3rEUKmNH2SZs0vhJDOLO6fiwpdWd9lwbLfc5SsZTf
XizMdiyTd4bK01CXMeCJzcNO6r+pt9GvaDmyHfnQVtFMGhRlQ6Gu0ZGXyF5PLVQkjJ90BvIT/EbV
6lYtkiLHPv/UbvoA1kCD45RhQr2a7bfubKjbtNzfZE98jGLc5ntlW9xQvtSsfGrKFyq5X8R54lQI
JD/9BUp34MgBeUi57Mt7PXGfJycD3mq6tUXgEh0xL35GIR00EaUTRtS87SG0VIoDf3xr7w0H2kAV
UmuE6l+WpgnnOHFg31gO7FIIg292SL5Ed62VOEDl93WeZfM/nyutGtzQC0U9RD8AeWa8GAOp8h/E
vgBw0WQqqOmwC51fvWalDKLqwyQLzJYH2S7YmjzliHUmb/Yzw3HFkBeQlDSEkLubEzahP4KAXJRJ
+E5rNF91KwBYP/6OCR3bfqQ8DClRSUrsOcJChPhh39uwcaImQIMYONIhz4ywvwd+VdDGs7/dlHKx
LRYLkZ2JSM8RNmj5rCdQ+RfyyrgFALWO3VSfJawYNHgdEfBtFLofjpewP+tScBHPtfCBS7ICGfho
+zsYDbie/T7fuzcoW2/iFSpWvNPG9114jpHffCSF2UjZfMgvgsrqwKMTmoDGreALT086YE3KxPA2
nVDM07xS7rxLXCsQYVKXEgJ264m92344+mQ66/koGttZF2z6xE9iMaKS7BOhY3Iga7E0KkqUJmCy
ZOvYnpjpSxC50iPGgp4+ZU/flxXcwD8Ix1NMbrkJ0S/etS6grI9BfnrfPoT1x5vFY8bWbZ5h8QIb
lUqur47vUQf95bDipZpz6KYKr1UcCd4lsvFUHb8XHZmE267ldTXcEB2Er8p/LsUVw8Ru7+JK0zxf
zr3MuO/caELqKUP6kWVee11xENQQu77V4aZGMMU0Dc20XrZRv87HPY6/ewVowj+kfhNC+3fPXMb/
pVQcnxpeioVGoKU7NJD/kEuUkV35fV00/vPEu8y0KwAamy9Q6Qlowcmcde7chQVGaZBY5HdIKLu1
4XzVQtzpwf/DSeeD/PnJhLX2PgztTJlcw34qOezZ7bFu0urlrWSDYmXE3y6RtxLHt6/peomSV/0n
bfZZh0tjyRp3YQf6aCewsoZzXJrUP8mUTL1VNVMB1V23wkZHpR0Ak2KxClj5pAOABnWL6nyjkarH
ArEn/r8JkR0B6Saqa5u4hH0lIP7Es/uQIBqCo89PLLwDU91uJEzMlr8YSMe1CpwhmwK7QMPewnVX
D0Cliqe6BOaWxrkPZjHucMpjibzNK9g15pM28gDCdXZ+GIbVeZQb0+oztgTsIkBbG9C9qsCWI1oD
ja6nODchVAftgM+66UeTtKh8RFybRmGYe4SCN+jfFLGZWeZQ+PnOQkzuddfw6yT9T6ipRLq2epqt
Fnj/IW6iK9e4cRe3FfnZc19R85xR5czsflyPyIJKWXygKeF5zBZlAL3Od35E+v1S+1U+vsB5IvjJ
+AWS/GQfbBJ8qTsaSPq5JiSCyl9tx/pv80CUq2T5Pvk6Zg4FPX88sNeXMGqMWTx8XB/zDiywVclr
zoFrVM5SKqiXzAGvPrEtRVqYZIpQR93nJXZeOciIuWkHnwdVF6Rt6ZI1Vf3NFdgpA79LN3Juk3WB
l5Z1gpQt/k1uqdUZunhgoLXjseBCNtZzZDGNPbMKrV05EPrkI2NljiMKrtL7fgFXc5sUUPFw8WBM
28uEsrLrBKeX30ikEHNaXq32txSROYE4r0uK241DaBH9jPuqY/mvjKpgRM0jZWkU1sqAEFdgGxkW
3FptjdZ/9u4GBh2VplixC/P+28lZrX0dyHNEWbcufNAPqP73yVdXeXm+TvjEatNIOzx2hM17XKS0
ouG1xlmn7QfecwCu3M1o8QC56m71EJtuILa3ZcifPtpvjnNVE2RPLYoF/ax2jCLJXdVRdSM71QqW
BbW5QQ/6oIjkRNDOuZoPs/rl+62xfM6OVXc1Y0NzyitwOGpPha2aVeYMiWpegP+tXTFbojRFVFA3
hI2412Qp36KpecmYhDm5ZTTWVuDUgEI+un31jomBKPMJE/1Wwi9ySFOzLkbnlfMx45Y5eGeYzUrZ
HtQb/FRCSMpPhQrCaZ/7kPJhKUWPIDgHT4sqmT8iS855GbKjolIjClYRkgwVEziTYg+9UqNNLLuA
6wdINp0UL2s5kuvw/SEn7pLMZX3iY6ZssjPzxlXreiuts/M3gmq/HIEpQP95xu7AeFEbfZnDxeMz
1ojGTsZbLN3ZtK3ZkDWOJ3ODcB7vmgaSb/8GsmM7Ssathv9Bk2ihJY6kV7MG70RQY8g2SycxQz5c
pY3MAxRTnGvrCmNkD3hpFUwCmqWDYfMeTLez3ALuYdZjBbCPlCygcn82OurQa1PUxFPd1PptqBpE
36yxs60ArP4Wr0Kujs5VgI4y5Lq8dwYMNRkYtSaEeI9l3Fsj1fo/rMZZrsXHGq3pcTKfKsz3/xih
Z5kNkS3sgK+bccD7VRHGkYMx+iFSZfHzxX09NbgiSNROoXshGljlLnLqBIn5FM14dAZGovR/J8Lq
PGGRZLoTnqV+3q7HE8MUmBN7QI5A7uW4WmW6pNdv/noeDc32l7wNzm0NU5krzB13cO3HG5TOsfrF
Dj7KDRHPExC2uPuYTTdwmm8XPtjNaRHrQmcuUZ0Fr2iSlVWaeG962jl+cszD3Gh6B8P6LjpmuRpX
RMUuo5d8IT4qCPgfq+gc3sUbuMknY05bcZGxuKMUbqwZ/rfCk+0N7g/xYZ1HpY871MmLNxOUl2e8
b/ZBjL73f5IEVheb9N0Q1bqwUCF8tmYaxYhdPtWSOGxQ+XF0h7giMOLuefa+IUmnKK2wOjDy3Tjs
LVlhBNAyJWXwjSCF0QAuNQ06KBTA2j7QvCxIS/wRbBf4/J+ttKLdrZs2bCCwnKyNV9bqtcUcgI5b
gazXxZpGPRqdDjU4VEjXllgBex5Vv5W3RCwNfX40/i4MJRHCunXEA03/XNdeK97hWLoSCnib2/ja
e7qfoMP9U2PaVuPeGArkZ15Np5FMlXlQBB6o45dgOl/vMmRFW6zyEds+dgcz1TsRi4W8ok/pBL/B
7NW4/1tpwO8Y4Ib0F8QUi0B4vWhLra5xEVzIsIcEvHaQIel7xddfZcxlBEpG50piNgl5s4mpHUXI
H4PLEdI4Mw6WwVJmbBwx1678eboh+eTJXwR3Y5T6zfC5nXdAqPVqFiNXfs2E1EEKOd8EUNaEDyWS
s2aUloM5dtIqv6rMoOQhfw0zdS2k9Qzp0a2MpF/scnpXZf5TfvpSwxhBXMCaa0eeupLraGWn1BXH
JslbLRxO3InRkv0OWp2d8lWWhm0JlWY/f7kHwFSqsrcPGNoi/aqH3G43raAusLNhfQJ934qsTZ5q
BOBEIUEdQdZl2ASN1RhaUbZSiApPySM9EBkDhXn87GUO3MvLsL+TL+cHGmy/T8Qf+BG8CAimUQzv
JneuIjQXz0lSSBq7FaqhHd/xEXtslGe1zAtSie7TEGFaWIVkuNGZZnV3DcwN48n1y2DLgDE8GVsk
eC1APKZgH+nRY+rzwem+Dv2Fce/z04BzE6gdOLZvXKNlCz0Zo20mO3GGm8kXyr5YTokYJBT2nmJS
tgAVwQom8hqxgDJl4cEuwHHRxZ9aExgt6C02aez6xeJwhFgHQG7V05Nfa6p+pDTg10WtMDlzXf++
KOMH+hJEHcodHwPafQouSezgN9BcM/1GZEaDWrDWnuSmkfq4EwRe3Ksq69Zu5xS97cuKHhcxcbWi
bbuckVyxwnLt72XdMFWdpwAKDZzUnLuEaoiBHTJJ8sd9VyZCnNThioEyrQLthcBIZWHRRcEWD5Je
ieLvFf8Cw4SotF15V/UwmOU9Qud1Z3tr9IyQFSLa2OgNVpKB+UvkZM9WQUc+2E1CdP9y9CLxBM5F
xqECibVen7WTvnyYp9bybpt+uHiSBDpuyg/RtjVua1K21aINxyT1VAnxyjkuKkURbA1K2doMMzCy
0CCN2dRC+TGBMEPAqz2t1F1yoP8lqfbb79RsVGMMcNMXsG56h9Pyt4QQJeqz3T16fG25UE6h00JV
wVCejpyxWPiURgbQ5fsXDxj4UxZ/7rPgY+b765D5pMgH/mGTpLSkG7tMFr6zkKBZGovkBKG0g4ZD
2jEVRLbNB7rJwlfc17j37Kf+hz92jdMFyuS5rWzzjx40M1adhQ5GfrarQ5oZooL3trZtnQJ7YoWP
t0xJutzVfhn4DAaxiMJC6hrZA81nGb26oyEyAgVFz/thtynUz1v5UNFAo1TWQXM3HczX7cPUOQlr
dNgbz18WrjYAEEPmNiRfRhCx10Cypyj6Z7TklF5t6ixcaN6UGNpUI+JFLJAZvBIPaz1WLi0Ab3vr
jjgQ4uWuuMiLkhNzFfjCflna0fJWVe0WLyotwrad2tHQvWmH5R0y8ZfHOiFLG3Qx0eUdIEikzVdK
+6t3GAfnGgVj3SZad/zIebTmd1LreMmAPdV6B5LPbFf4tCfKwTQNvUH6E1H6N2huD3omfUcG4hr7
esOI3W2Y+i39Fde1f1VuRENslVZYXLt979pM/4Q2i26zRmcfi91J36aNpGxEWhSwzFs+HQMA1XiA
uf07Bqio0straicLxjrLxroggWAPG659Vs6UPf6ZXdS3ZZenPO7VrZ8Q8R3kzklbRm8HxQebmEqB
XR5aZdIEl+0eelSP6LNaNQZMgjop40xOWk/Qkqaek3mVeZgD1BKD0AcOQ5ADhg4bE/rRp0cIBLof
6RllM8jwOwPbzeS0hWUUsqMGnxyNxO8j3SveBcJqEHCIUYUGIaukiPgLAoI2Ik2Jl8oNyDUifhf4
wN5N8Co/bxm9VKMgHUU9pt2IqiLelXuYFWkhuEMd74geaL7H3OFaSXnv9qPZgHSiQ/pEpzYlmDko
SdmnK7h30fHhwYLrB8A75Cj/2hK24207zHZipE7IBaxj8AaWN8PoWJzsjpL57tDmPnVr1MGfCBtt
Ev9wMRcEkwh6o3F+5C/wySrpKtyOJklYxCYm4sqMRDFUSwZ2wJZPP9OaqqkXecMa+cui8DJViYEh
u4a7WAFsZIrUNW+FgCNa9tXiQYE0qVmixRzfCaLbGumRibcPemdndlby2UnXq7g8//xXF9NWu+pS
Qch0bHLV8iGQiQhEB295C7T15LnLv+T7b//Wt8nmfpXMFgNeIaqW9bgb4ZOQk9T8BHaPDG/Zkkam
UOkmHSzNFQOBpkQwKHEIk3BEi/kc5P9yITenRXewRZXAy3EVGywsu+tZA1KTGKekBpfB7N5sO8uO
bSvgRRFg4BghafxNmINGMk4Rm/3fmqduko3lP9ObMzq3K5irrSjqw7/zAcpp0rrWQgXffIZxv2Sl
f3GNxndMVjRBTnDJ1OJ5pg4sn5Ql/KbZmZx3fGIuPO/p1ZCkpsNnIOK/6eNfHySUtrldi39ccxfx
IilVri3g7x0aAW3E4+tQEwo+4SKNtvpGIZx1jBVYdSgz9HKPiRuYxEgbYEllraA9qMdt2/jjNtSp
jYh9F1x/4GeMbMbjzbLtEhL2Bope7FqZMGY62PYOFihi38FeaDKAb1VJOfKgj3FxnLcChnn/pN7O
pZmujPons/IqTsbUmm5f4cgQT/dbC/Wm46wmtr+b+jfBvz2+LKNfnmhKOQnDrJ3j/8thqRw62Qi3
1z2QtMu96+ypCOprfBq5TxyXkVmVbNfSuaAfo6jRUuFSUxJ/e0VhyYU5QbsL/0n1mNQu7HmUTlbm
HClbuqm2H0S1+vJ0meDLRjK9xPoAhfMrp5K9GSD5/ONDTunNSymMssYV9hsvXFYv7EBwawUf9Dmj
0ht2puPlKSShhHfLORG3z1ZJYVHZ14HKMRSJlnYNYWtc6ht6q5KXvMecchLMH/XQYyy3kEV3zSIO
tfcB7F9Sv75SAIboX0UxNT05AdPRjJh2zrmXRYBjXSXR1XsE6B3Ekt/D1jFfS8kCC6//wUhf/bGs
ePpg2pigtIf30+c0S0jsZic+uWzp2aJ5uo1AQaCjt6imXC7lRbqNbTD6UivKfzwXBzbKdDvx1UVU
6n51rVKSx65gDbZo9hpw1/eirNe87YdXFLMTEO71YRZP3JgdI0AuqaOzKQm+nNBk9iybaCcKcgIm
wWQITyWnXr1I/2MUi4Q7qY/HKQlBfDSoVbJ7a4x3AK96yz+mLDd+RQDF9Ud4lF2foaqLIEYfcFHK
8sJQBJKJCoZeLLfHUvcQ9YnWdoSdQZoWw1aVPf87jvVLOieH8Md4VBopflq5k3dQN26dE3FHmqpD
tkMwYhdotuthgZwBya7Q4qaKGdLCcuFMFtPMdJeoSrl196XZZ4mq3YXuzQL1x1iAVpfkrDdC8gy8
v1O5jCS7H8wEZ189gR7fJ3izhXlvc8+/v0PKYIKk0mwmk3+KgLNxJ/13MgGHq8FKIFGp3L9RLF+X
HEx0DLei14Ik7ZglqbiAXeXWDNgzAbvd54LnReO8/rV+H5oBtab1oxG/Z3AQstzPlHSjjj0h5ZtO
ON02tu1GiWGAG0t1HHu9ejLPfk2BYTJlxOXbtqZ2ctvHqIXStlR6iEfo3hoDJ9UxoT0B6aDst4jm
aOL1ev8ekXlnz4THWyy2R09jecL2/pSHii2uQ7WxAw4BHCd+jyANnXrgeNeNOkHJPLTVNvuNfH+/
WW7F6w0GwkMeogZbCLF2Ld/ZAo/kgjUybvfzKxFqL440yoT4ftXZ37wQE6bx0A6GzreyAO9408h+
bVYfbr4p4FKWHXw13qR/siBKGQv66ihpPLo8+hPlnDZsQ0OytAMO/h290VgxEqvCli5XWAsjqR3S
oY2ed4LCOP+AFH/+xHsNdSpDWYtVISl7kLoezzwUbXp7C3rg8AZipzbWHDD1quL5TDi2dCixc+rG
GzAeNV6DMa8bdgmltOL1RtN9dgsx00W7yVa9F96EXUDVwrKry9brqxk3WxB/OVXPj3rT8EeQUH5Q
l2WxRRbybn4ODTDu9hr14SI/mN6R7R7If6+7/QxQUvuJAZ2Oo/4iLWCnNi70iwCAV1w7p3Xj2ypV
dA0TuRuvDQacHysUrefdEAGXsbNRjU2s/mseefZE/OdgaiaLUf4O+kO6OdTRRpeADwBhZ9oqTCeq
02sIzBiXTpd/WiH7TYiE6JqjBt+CTBl4tsFfCiTbSJCgR9mF77/K7gq/5MiL/H9jeDIjcX91pOSM
KGD/qbHkw/p2nPCN8mXsghvAfHM6B2c7We1uP2ig58iMHycLJqd8vHEoR+qAmfAwbBFIp0bukBdD
pdW9VA0ptpzFwRBXD2XEFMkMouMLmRG0cY33ZATW7f8TGcT1KqEQrgGhIvfa3Ddw2qiDfk+HiE8c
GTBkZuE7NRKh4nK6Ad4Xp0tcyy2KRrSQRuz5QAlTXduemGlV+sR6UTqE0wtrrVu1SJbGPj4bBBYp
09VdDf5PQjEcvBw8GARiT6PyvRxvVlOaeCcpSac/K1Qy+XD04WZTd4kAfFrB7seceJSHyRWaWpXv
o6zgyaL5sAaVDK3jwNf8lRqR/FKCXXxuBmHOl756A3xbCSPOxg9LSOg1Xj4aLTc2CsDgkn7q/5VP
LZ970fp2faJxqVcf6gljrEAc/T0o0pAdH8LBrn5lclTiCV8zjLm/qRbFm8mczgfvp6T0DTvkG4kd
/8BXK0TxAKR02pMsLYPHdlg66m18U9tPh9kuWxwQmIigEDN88H3BIUqEq0vj8Q7uvS6gcuCY1kpl
YjaE/8IpnUGa05/pT4TJfKcGa8hBO0iLoUZ/pi6Ryco0Qyir+v3hd+/mYDCrSRfw65AFb13WV0OJ
C0XXbbqH9HmzjOPzA9BnNY4gYiGw5JBpDFwhMqJ0sxJ5uQpKHiQ1ryPz5dJaYK0+VGSCii9WuIGm
M0IJMsfAvCYezP/N+CfshckuVAaS5sYGcY76Wn3guOdCCav03Qur38DXBNmQH7lGrBVHefWZl50+
JAoooFjLR0yCSJKUNAszQwzwdADUzWolnzwfFP4ag64j6+2l9QzNXI8NwgXv4NwjoWamKdWfR2wz
1/bNBaBUOA0UbkAUK3+esekPsj8u5jlnnSK+QbskZnmR/eb/t4p00jvWPdvvBkgjy3nnJc1sLj39
KxW/h8/dOvm8sAxRr1lIDjPg1uLuVawxm44Ow1yajNPEaiJHpuPA7W9pOHIsEGWleJpBCotfGsi1
NmghLZhAtH7XOWRG1y+zzBCP0hYamom1tj2aE35YhkiBGlI60dVwUWnc+B9MRJqhHdpqbdED5e6Z
PqiyAadGgl5nAOUHrpYp2BwO3kZ0Syy+UCnV8xku7SfYV2POrCAuASilkcgY8QcQ3fOxyE8LeIEA
KNGHMZSNJHyr8n83+ARTMBV9ey+dm46dxF3mzNKRJsvegUe6qU5o54Hrjv8qOl5uCp4RXrizZJyE
2bIRj3mFXOZwTQM0zcV3Li2rtHhdDl8zmER+usFU/ZkOJsFX1sFDNglC+90SFAJRGqXRs1mA91kI
B/qqqhKNuDSfCpwd3p0DTBORGcxwvMut6hzJcdts22mOfvy/SXu9XJudMPXsAngZ2CZgtao4H/VI
Pr6oU/gTEM3zLjO6e49zoyHqmolYuhavqw8rDzqJqCIdNrDzh+N+l4niPNdi7P/6d8HALNPCWSza
fGBLBJqskvelTuTfKkPxumGYnAxh8eMemwuVqzTDK6dMD3BO3qDDAKglQQWgr+q2a7UjQu6FS5cD
tM/X5o6BHDiCex5voHA37Jmxm49BS3wIrRLFgOJpkcUw1XeDmk2WgkVfgj1h4CuoI0xOoU8RX3GR
vBIKxdpnCnybplFwylg25We4F3KSKdus0vV/eUuEehiaWXHbnJEysFM1QpqoBJYul4r5LJmdJ2eG
kUpEL5zRYQRqb5SBlFe4Uq1ShETQYXTFE4M33CoN/F5TLwYWCU/Tp2dNoP7/+E7q6Uql6OYXCdAL
/85lBvZbtcGdfl8RFh2ah8lcqCpsYdSLcSjrJBrIw9d35ZMuQmtdKpsS1pNsbYJ28SA8DHizaXqy
CGdSK+7/0DYJ5IuDFmY3ZhNRbVLJxTIFLG1kFsmjgWAUY/xcHWbgLvsPaKAWxMhIMoG7iRaNVU8b
CWLAM6eYJqw55Kyxb+ugIj56leg5hdcXBdVq3cWy8NqXdiKuoXZi7AMSg+jPdMxCJpqDyTmKirhz
Gd0fYdQKpcJYvQQ1ao9BbkalpGEPIiq5KMwiiHxm/UvdQ3XQX+3Xmz1f1B/8MhlhruQlA495QiaO
AczHfT1ekn9zb6GA8AGcsyq7z0hXibWLcy8u7OZOBYgm1Ij4nui7MS9j8rzxkSmEa2CpiSbjdcSe
7qbTFJu4yIgEz+ZT7srDlVip8bvUWbCjUHxpO8FRffIzkxOpn3+xhJbId7G3+r90kt1OMObYTRGx
ge1HyX51Mrj6sfPdB58zNMfDjSZiyZ7u9tCpI4cBrAFLRyTUhmc/PbsRZ4xTiV0e/oUJQkBoaNxn
bU10YYjzvEQTQRAnjWm3SFTNaXmL3yCZRoLvWKiVvrykv4XbFrjkhN05J6HUlvTFhQV+bwtB7xJT
K6mI/cbdruvitkyXaMdiQ3Ce6m838QyYrT+FZl4NCH/5RZQFvuWS7Xe6F7ImYh8FU5cwiONAjBq5
vEruGc566asFSXgfNa0bN6AWFFKeDMryWFUFrgOb+07EjXqcyKRSKiBDS7mVZadIk8Rt0JIquRdv
Urnk4N95REQImWT9zIgVy407qeo8XwGLGyhRQLGJwXJUl29iFu3zVflXfeosMPYwv5flpJCRDHNX
hgvWZPdwPEfOxQewr0ccqOv8B3EOo+UewmKJL25bWlR56NJENY/fGbWPrPrD5yyf+3gSiSzToPCm
qaktNGWD7mK9I/YFfeZT2FvdvSD0MKEKTYSlWLqneZwD2C3L5gCIqgKfRTekGKEaRmmCDbE8n/ea
xVXrgzgPKhyuIWTomj8nfYYXzP9Blz8WuVuEMfBgjG7wTO1Zgopd2Kn+x9A9ueNQj9XHw+iK3/ke
pHChSd5IwWpQ8YAxbdSGIxC0Fdrc9MD03WtTyrCyZ+sUJ7w7Y90qtt/47yLC0lCQvLJL/1v3sc7C
N0eXq6pxj51UZW39PVNeLaRZz+sBSHDjgoql1O+GmpJEmZJSAwh6Hu2p55oufh32HMVb5kxfKbB+
yT4cHuT8kWueDxYSzJX/c3EtX6eU9yeMzMy4KQESX4AJk0W/hNuHpLEF0OyTKl0BsrbnJQ0ol1Mp
HAmRbkFHdlQme9/radbVQZc6IRkpfgws+0LkM0YYohCH8uKuSi0yfE2rcIj4Xwk/lUa06eJw3Dwe
1FTEk4z0awOJeBywTqXkjHKpFSIOSsjoBDvRuPODUP5u7LveXdrNgD0L48UJxJ6RDsWXQtLI0HaQ
m3ZfLqINb0qzUMx/iHIEYBtQRz7KSGwMwioyDjy1OE4NU+IQA0DngvkpVqZPH2wJNUem6GqtF2xv
2vhynR0U5OLTdXGFbv8HGtFXpDi9ygSdfAlfMfemKoVLOa1c44R3l+tqoEotGi7fKqCvqLYph974
YyyIQyvmmKmwLc47ff+RthDXsUEaNNCJhHkG450bLieuZOaBSoBTzYxKyZZLvpYbfxc7jlOZbXSX
/0EQxu5w05wDN/eDnQASjpUdPdPm9ZiouJdArG+43mqsTUjxSKS/P5EaPszdpUvZvkFg/eC8ZwAW
hWgvqjRo4IqALXvTURmBu+AHkLI3+orIoRyzZEjjvqg/5Ex4Drb7g9Elq7PB9rWw5I1qN1xvVb3X
9IKdzHJHhSXF26VBTZrOpqg7n8NVYwvfapIiT+RbzqSRAFEXyru9R4kYOjFSlKXv8f4/FE3EiNYC
FqnkyFMnpiSLaptRZIkybNbKlpAgqkXmOOpTsYldGS117yP4kt/JWmT22VrhVmZGjMuF5twilz7i
AMxoY7k9xVFXElCB5VOtaXOK5Sv4iAknhcGiy4wfDFHhzSbeb5TbttQTduYKqepeDPD7gEXitqxb
l1wmqHa1dU/jY5w1bQqTzVPJjw7ltziAklFyeMIa18olFbNd8fQ5AGM9tHDv7u2S0O9WahbFe+FD
a04ScfcU+ewkIelahCsnSxxh32RGjIcIpbaYBg0urVdd2PzAGeHj+tYL++/gqb7EyYISnM/tX1+q
S6TXA9uiLi/Vzr+nOIhSUEaFm76bdfbej5Ov7wXrd7vlPDXzdwpRp/uix2McYciytSlfKEE5kCla
aDHPJCEPh8tW/G6CP4k8KDm1xZPksmy63jTxkAM+0vFtFAAGx3ZqmVWHQP508Kfo2b32qygNJA7Z
b4khsXBIM2ACr1g/2Q+pKxwlyoMZUvL55EU0Fs6DL+a/w8fNypd/Mgi9cvQHLfghuh5VxT4hkZuK
Io6O5u+G28hOlP4H1frBq9QkIL+2/cge/1PUjyBIi9NNe/UqWcsR9oEifi6pEVdAvmZnNAonI+e8
snryXouC1UYUNIGGTKoKPQXCr2vr1E7FGVfr89L1IW4JxRXM1DRVGdAghsQYSDKQbRVAc1l6pUrG
KYm+fCgX0mPThUJYenprzzy6YchlarcJkKr1K9yzrQckP+V+9lH28FITndDQGUICWYG1FYoWaL5q
vxZMj2cxq7ztzLfwenx4doyN6bxN+2wRRlF4TnEgysotjpn2qguXHlZIjKQt7MsOdLotjZDubPgL
Ws4Uq9AFs3DL6srRUiak22DRhgvzB9hHCJnM6cdTIk4R6JAREqd2AkOOcqKUVLkv5OJXEIA4UTxd
ylRYBZT5dyaLqVexPdeEND/VXgNo4zy0DU+022wKTDOWGpgaHj5JZqJHSC9ggkAVbKELuhvd/oxl
Ljxec88UWIlD8vpe/wLnKTBzwnZL9U1b7wXci1TkxQD2pyc3lnGT8gMWTr1oTNx/bx3GIHy9qA42
RESq/axtkHAIy5ICXXH4IcdIPLQRMkaJ1NaJWRYfXKMe+rMN9oZ7C05diVKmeKhfdo3fpk21z/Xa
2nYGdumLuSu1kNpO7F5sann/cU0hQaE7ltHLUsp6ReJfTkKnRVGpsZUSOzfsMt3QuvI6jzwHjBpT
GAq+oLeUjUqQQL759T2KojphiI0xJXJBPMG2p3EzDCaKUIVLTDE3l3hZhnC+X+ZdFs+G5KFsMiCw
THfKhRP6UCH9OmOc2YXiHpwpOP6J6xMAAtiQO3kUWc22+8423DjO87nYDQZH5B8+GUWGFJKOomBk
H/x8rU6hHaflHwDzWnibW81I72SFi2cxooqurNjwOEf0ifRBP7Rpv+hKSVsdhCp2oVaXGk1NSF6+
jBs8x1gcpdS4j398mnwDGKJw2ET4qiJhG0Fsjbme4+8T4xa4682iP0WAHfN1ZvdtIDCbm2c/u6tC
T4ORz0kyrJcHP7LECfvgTJh9eWliL6/QfdC2oIGvQzfN0a0CaobgLxgRQO1RSlPk+YdqZGZvfakQ
UzMFMz003FZ41AH5GFE0AloM38WDC+o5ft2xrc0x2FwCHBsf53ullKqVFt8t+pNj562r3A45Nwd1
qBoApZWEvhHcOKGldjeqY4WAFLgeHYz67pYl31ZcfsQWn09sc4766x/xzGe8yj1I4faMBbTGGeTD
U9FkZP6ipWQuopPvFB/Y0ZYNgDcPb46ZgF4uMs1hQm8/TI5Jga6pkgFQSV785l98VeOsUEYjbLCE
Ekl8GqWJsRlDarCAZ5RFtXQ33l6P9rMXmXQgg6Fd0iD7jaoL749rNCMtfpeRpx482gShkIlwTEBn
thmOvSD7ANODPUYCY/I+QwJ7E2YnM03bn8XM6lG3kS3bbpibCaVkLc8R4Pg9aXbxU/icI6EEk5Vm
NClH38Nf4EpBPhluunebGhqnJ4CtrLVRa8jxU6BK7nKFmuDEa71RYQfmmzamFpciTmiijj3b7epf
bwxJdrZRnX1NHJpc+MjGDrEOENe9H5ljn6Szio3PddlKps1+vBHtttiWSYqq/kccqPfMYDiIUG09
hXo2S3B+t7WVWVQPdVNMV4XlD+lL5ysQ4l5FIOzazFUioKQX/8buBvQBrdp4/bbNNCoB75HTBt0+
DArlykRT2Yh7sLVkeaBri+LtCinG6G5QLuNrSS3Q3xKBdJWjkifTAfAUeUOPWj0tUrQtudafkcj+
BB4eLSINogTCUBxvXOK5N4BbTHXC9HoO+wdE1dz/4XAOA0F+fEmIW9OikNjiBmKklrg90gWTL1Jx
nij02zQMN7keJAp2hEXgNljPaOZNEoRIlAx1OwcvWGlJr0vPO9zkPv6jOV/2W11rOl8RkYhRjGJ3
pp8V9cE4VNCeQ76vcFIHxR/Plk2Y74nVzime0i/TboFRXw7FPqC+lnFP1jcZ14qEd6cMLgaPf0ap
vb6Oo10aCu+pbsov1ae7aIqiQZe5JBe6ZtQGpP+iJhO/lXr/nUkTO9olQqxDU/zpr8kh4pdbi78r
+Ms1hE3L8nUvZKodqNletrOzXLGVNsChb6gnkivEoxBQIYUKR1JWCNxfI42nxEGwUqtRhheymx8/
BGL7xkuFGW2G4QyHpPL3A+FYMAd+Qr1Ir2o2Io+hAxWAuSZAfPRjzlZ8kM4VsuLEGhg6x5xSg3Ml
hkJiUi+HRY7Ks41N7FaaJC7Hk837nAlNEoYstLLX1oG0aoGyAlUXNtUY819o3uCE77DV+9iViMbQ
JooOPrbHcX5CahloEHb7tFk9pKX9/jPocU9PBspg9mqIebth2TyLXRw7I1QcGbHTgv1rNY1fhMxD
1EoDYfliRd0/AYk5N73jjiendY2JJu2f3maS+8GElLlFIgDEqIUBCcp2cyzUMsLaJTJdHYhIUsNB
7VGy/iU9m/hkHUS4gdu3Cxu8ns750+KbB14O1Aw/0LOWoxXgLrI/FVnLNOoDpc3mxJmYrX3c5vUB
Yg94R4LV7Rm2l0/08AFD3hbaRm02aV6XvcN0xYiOgwG6HV52zN2KtnkOZDN2bBFUYsGZFJo3jKz0
pgkrS11Kxew0BlAf5+JfvWqmCyj6mcBRAo0spe6K93ZRJPzHFtl+8x0PoXzZNNPHNKG7bCxamfpY
YQHFErhQcOF+UG0nDOqusqHRgfWGljHv1bi9h1RPB7kCRsPz7OaSi0sltpOuzx+U2VJWy1LnzEeZ
886FJytRXzvFW+u8nMOKv5IlcVsJSjtA+/BW09IRtsMWimMr0RxUjh/uc2gcQ6rMIXJQb1HMfGWI
7bsVCH7JHZ2ZhKvefhFpy+S7cOMDqj8YUFlDaCoVqvfCsoAXOTGRN1200bFwx6Qpt5VWws8GD1/l
wVbcKo27TxyWoj64ewkoInGqecPSnsa8xbVTFbKdLWs7iyPT6fafxPZUxGxa82wMRE9LU6UsFEP4
EeHW4NagPvyQO6TT+5e6kLQ35sh3H6KvvMxtD/cjWMo/LcB7pT32l8Xw9OKALjZ9RJXerzb0F9Af
IdehP+p0GFICodGVD/8cAP1pn+GaoLZueFwnWQRwNGFhz8M0numdNNs2Lo0J6lpDnbQmhHpO2U1w
YnoS1hz3knN4E/qCKZckOh00mwGiyz0jEPx29ET9V3BDFP+Bw3SY26OFXhlE7ZrQPjOV3eTFoa2g
byEBTzSsVFGgY89dFoz8rvNbFiJI1hqsRAKtcNQ/025++6fdfysflj3NEyvkThNT/G4o2wLnJTQD
+q3lxS2CkI9oGZEro4HwvtOvxq1v7TWoi6Q68gORbBEBXiWox6G7xnvrICpAECH4mIJaslujTdXl
Vw==
`protect end_protected
| bsd-2-clause | c8d0fc27cfdb62376cb32251275d38b6 | 0.94756 | 1.845681 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_mux.vhd | 27 | 91,985 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PFFltKdLY0A82yxFqahMaWdN+zxj5kThYAcsDyz3A2vhpKKQpGJvV8/AkpYYPyltKlIzJB6Md9uF
AN2ca05J0g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
obdm7XtHPDQGZMrK3kNZKnRt8ypfk4aZ9VtSDpnSwNdbgwrFg4uylDkc4YjBW8BFR32vEdXmCKFe
3L1bSMhXRkPXZ88hMJlBty0IcmSYNatn3RV9VG9yYtXM73zMkJ4NIx7KoDtvOCnGQpHNAJTknAv6
BNEUXajqHzh/vB/QNBQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nx2eU410BtrBCSzpvDl9pNpIplyp0nHGgzB9LvwnXgdhN5HNF/YNjnH8WXRfWZhIT380E9zFeNz1
cIYhUxogcuyFP2sgar0PDv645GG14wyLd7prd/d1E3Ur29iNukQkz59OjXTEIN/U9Gy3hPt+oLVA
TwpP0P8RgeQqCkJY93IlvPGfZ/yeDQHrxDZUMFMxHHI51HM/LG6Y5RjcVEJMkX5GTsC4gSd5fEHc
DWDREOSmqmG5Gmciy22xZEiB1SI044vcLqlJadcUhINRbAw0576LfZrf0pjCGq0s1+nEKeJm9MeA
baA5VHd6hhXLwLD9jRkKDvFp76mdZ8cpvFpcXw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
my8iGpxybuJuMik3+8MRqWVv3aAmCE4oY3Ij0YIUQTpme5jJv8e5DOlNoLmgXWhUlepBCUyZ1Ysj
JGlFKQ8MBs9R5aa1TLi8cCVfI579Nm4AO6VpackDfb6c5/BXCbiBb8XeC9Q6z0hKyH6xYDDC0Z7w
m1jdROr8ONcmGBJr57g=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pEGUMbCVqav8XqUNf0y2o1L56804gb2pssAnfqbrEzVo5CXZ9MmyISfyPG7HY7huXkJ9tWIeWtYt
bUG1XTbOUAj3uDqhigkZ4KnTE/68izmD5rgLlGDQ1sI7w5GLUgtjCBINeZsiQZ8IbdNK2b2sCu2x
1k1tcyPPvRv3myvuFaOhmiYYyCNc8F9T3cW6mq34yHrMb8GcN1rGLFkL16mdIcoRSSN9znhYYcLe
21llq9uuuR5MD7mOGEYx4bKUQGVdPOHLC411Ms5bCd0IbhTC0qWispRkmO0D1uXT6TguY5Z6gKTw
vMvXdJYpwStmSqzikX3kYI1zljpfWHQ7HMzzTQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 66352)
`protect data_block
a8U68t86Z3o/C3FQDJmOiqxctxRfzciGtiexeWX5/tf0YTY0s8Y3Y0I7bLXU1IZx4byo3l4tenB2
kusR0ylj1fHEU0otcwy6uhkEj1fBdDkfehty39aVpUPBuagKC3Im1ayCXGtzUoPoild7NpYA10ZW
2jGK3qYKQ69zfUu41oM6AJChIYA3g+BEc/OAgj2t+TnQHXwT2LsyuAmSYIFbCJCyTAyyPtpIr0Nn
zBrAnG9wzCjZkgFSy8ze/vycqshGS+8Y+IyIzi3+Sa91w1OZfG2CvRoPx0zArX82JxTm5TmlFU1N
Uo+UXTX5EZWlBfzrPAZfGpUtNkJslzlT3Eb3G5/98LCTJb/3TGWjL9PinvuEoEGzklGYjPZneyNc
XZNYLESXa4QUcj1iroZRElWxvh5eMXAkwSIIoNIenJJFM1Q17TMT0idV3R2tNPjGjSg+ZEUqJliG
Cbu6e82qUxu/r08gMVLhuJ4yw9opI2mndnh8faE77agfLD1UJVsp5GM90YaDngbn9CjJNTLDCtDJ
1YhNhCDlszRo5Qm1ArM3sOm6P8K2vJ0lSPW/Jpn7ZAUW4z8lUTcrLDB/X6YztwcFLpGIrBglHhIX
5NISCDR0AYL0Q0aOl2HmdBgF/hu4+Qdjx/Ya1UP0hF3t8upC4DOPdLYl8vTMGYrQeK/XBTh5dGi+
H0MJwVWdCUk0mrEGMvcl1lYvwPYr1inGd5ttzpm9OFZalPoJlNvq8MhbOuhdw9y6WCfJRD3fr1GH
pBs0Qx2pLTMxcpOuAYGLupIYrJyMl+CgIr6dN5i11acXmnlkftgCqvdiWt1ADFuQDS6vMlb8xWRP
H3/WAN3BiHEsSmTuqQEJkMhBS9SPMteSgJjYuNiKzXRFSTCO2/Db4pq1EJA4b3VnrfqXqr5rLtsj
nyMcMENcvv0ROoHS0CWpdvgUCbeOtGyfyk/0blI9ZRTpMpNirsmbMNjLRMKoMu0vjAGgTRUYKw2x
PxPhI3eT/aBuqbjxQox7A9VCCmmFJw39wYsOqjdZ4hE/UEQOoq40hJHR0tGtqwwFWtpNiG/vd+ND
YUEVOZXgHQogHIbNKNvidjC+j4WxTX8r4McBAP4tkzoGswouPXaQvnC3cNASv3HT39+RjQuHJhnJ
IbV7x3scjd7VoBupA+LPFxACxCbnPOtDPPiJUaob51ndNl4KG+A/99JxATTfmT9Iy/UtlwfKLWsE
H6gnHamAuygEvVO3Ul9bQFhLb/7Tr9qJabvhw0aItvfwex+4r5GbH/m9C/7CDr7N1AkrzZRAo6vB
LYpk+7k+zz44bzcQGxRQ+3ZCYLBAZCxWYSG0BsH7l/GfxAwYOB01t0G39XO7GpefCLk7UhZOUceV
+KyLziOEY80Z7ncER4EUFQ+GI7HenyL/9m8yiipibF0nsPBNd9i1ZYJhXTbUWPjBE6N1hKHsicv6
EgmaKgc0EY0haEi5Jkn5TZZGYF0XMIXs541sLcfDUu2NyUA+idMXBkmthwvceA7N6jw04fr67WKT
DoxRnZT5MnjTrOeltx0gh2lTaddl+pWAekkop0EQt/rPtpEstZY3vlPOla4gg4aJsYlFZqtHukKf
AoP2GG2RoYnjt4kd8pFKSuVwGXCGhHlxnlDzMynwlA3qfIWSnYxhIXFdYxSqjD/aduxgD4oB2lw8
ZfZB6D02+1kgAl4CixPB64JDd3D1BBXJaA39Vb3Cg0qB/kDQtMe2dDBAKNTyK2sjbz18YFAy1QZS
IApSGo8E+JFb5VPZMrWHOActhVutz6gKuvMfjTI0zxZ9MEM5CAh9Lec7TAj3oCB64zly2Jwz2eDu
G/OO5ag82qbd3FidjTCjGZRsIXdkWBYnKiy9cz+dYFNRkozuF1iREik9ieBtALoprO8fgJmO27S5
yJ4QQ9o1/gbCohLfzAiULwGIGUa9gmGU1gX++2GB/nrC3XehdfV1VNygWlssc/vFfiDyO3XlEmbB
sK7UsixXlAFQMTsNtzOQrVqqnXccbCaHU6OPLOcUes5jdgiEMIx4uZY5UGIm8tRuHOOwDXccvYgq
48G10taO/Rwamhq2xa3FLP7WpkZtxO9F/KRrnJMuABtKlWt8WIaQxOPlU65R3xgrxPvwBGFbch04
vX7nTp/qynBU4S2IA0J4OV6/Jdc5cmJpGC6KZKbKLRSWugJBtyOmvuYMCwWR4+kt5vfkNkKihP05
g8qaCsIRa3Na6CJ7U/OoBMWMkaTVE4YtBrFsHc5ygj5pk7ScfAoIGmFWLi2w5RDOEsY/fddBqdF5
smt05WMw4yR8wsNK6T8WcDnmCpsdih7ZBoqou0e/TcxNBaHOcUChDvf3ZHakNP1juM+rwMDMZZQ7
aNG6JX2kUSvQG3xl3MTSTLIJ1W+3Kr14AsbcQxy27BXE3BPb1EDrSrLNdo5qYdCeul2fja/GIyX3
Oia1UDpa3Y/6o2KTBPRZu391pzpM2oK24mkUmafw1pv3c5r2TbalqhJzIhCsYxCM2h1EU9fsSP7w
0PJh2tL8hqoCdNaeI5Tkxr3DSom8Anrm+w+e8AcyDomDbY+S5q/cRgP2e+nxGr8GVdTBSBjBMK24
3EpyMLNM7UzMysH4bLKlWNf0mzEzvQJOAPhgVIwkm+V1R7rn/yuYzYBoVB/PEF6vrxItLXYiWOBJ
IyDtENmti0R9VOu0dxTDgjmL4SyhOUHLTgk2YnYoNSBoH0rz2cuMh5G/F0EaowL0I++bwCBxlSNm
ycbrPxYF51AhP3Wyb5MfGlO3JbP6OEc8UgCnSS6ZnvRWOd7g0gHLk1AdEvbu5gez4gaKFl9bXhmZ
jD3p7de3dF/TYGnbeBxugL6MXghO5TnLCjDVI8L/Kg1MO4w9AAhE5rcRlbZ9MYK9tAuZ5TAl03G7
6iKgKro7CRFyjcoNAS41j234X5vWkIvBlvI6OvTRDQrQIEr4dInM8tk+oXCowQQrFIzCilDPHe75
leQ1Dt6MeyYFFnfq7oBFCoHJMisRuBC13xZCKsPMEKBzwNPMFocVz9Ud9rx59lkqWsGobkd+3H83
ABhb6bMuMRC2EoMXo9trlHlcmTyxGC0IyaQlvjSbUYqHDCRT8NB/e0QRA/kWbDHdMIER8/OLwamq
Dg7nk/+zDsocmQhl2JClBEmqdT6EVacw2rY0W4mInosQs4MHfGK6eT94JdoY4cG96N0j9LJu4uUS
IdLUSIzCrIIHDRuZCaXiB5IsrEqTG1QVkVZA8Bv3FRKnqzSybeE83iGHoPB5o/gWuVeoNlqJfjIa
F728gKbH5W/YBPryRwqiiOzMb9NZabtPWsl29n76jNwCHagGOQZO8jXvSoS9OP1im3tPgZN0vbb0
nRTnRK7VwAcPiUDaRh0wzUXw9z/uYV26wv4z76qLql7xKeuxRbFaEjVxJxQIgYCa1nq/1FJktDyF
JEP1d8yUxMTIWF7p0V+13ZKu+xBIkD0/lJ/SP4mJdU2ODTfCA2Zl2s5foXIQo8LkLSJA5tKnuju3
2gJbppH3Spv/n6fvBjs3LtB+VrDvwZnMTIkN7EIdqBYpNHPuQUbjezuWcerW0YrUdT3tw+mq4NGW
btT8PAq5NXAgJWlMVvgW4vXIaWcJdumNOhwLRi46hIico7qVbEi2C4E06KHvY6crlxI0QN+cUVZI
ACpF3FyGQp4CD2wMQwsyweBeQITuPeY3eJpxxKWIDSBB4o9TByjToBpaMsdWimzNUzh6QTMv1aaW
CyiXrwybWk7SrN1pqv9JiLdsakT+w2SLZgo3QMQXNuIJmw5zmZ/5cqlu4mzCqP7yhXdQn3EjJ7rE
UGTc8ub3te9xoH33kz7Bm1ZnG2KdrfcSTUf6YltqYwFf//1WRSSvGf4bI6hcrJodwwV4+ocbuYUF
dZe1xkhA3PqcKFSrSr1TmxS/wHq9iQtNk4C6wF+GH4RwJHPb25btqsbnnQooFI4B78AdHBC3+Y+T
2qkH2ptjh+A6a+q6v9dp7wm8MNSqAWMtVR4fUzGk2jVRtpPb3asYrnUXJU5+JvcprxZeDSYlmHS9
JBx3kq27pdu77ZHtNgmv7DevsYarW81nI9byNRA/eYm9lI2clzRqB8GFR/gIvSBu2nNj0PXCMWoO
5EExDq48Ltl0OhGxW74EhJhu3kam3pDzDdcXMOsTQF/8XhMGnzEaa7EYQdnM7R81Ji6WjSGzuyIJ
Qvn++2MPVMflQHvcdcz4wRZYi0N5cyZm9EvcGxU5stSmBjddBXsQqeefRZjX+tTcTz9EKpKqxShH
5DpdQ3Kpzye82dkri5rwf/JzHNXZB7gzEul+ekvf1yVn8WrtqWxcxQFpCnpvwvwcxZ9A9rtWVSfs
f05pEaTvrF1OCJzAUNNuGz7z29DGVSCN8lz7ACzJsLc9pLwkw7eOI0Mf5FRqAll6aFbBvSmcufNl
vjbYdK8zSOOr3v8+C18bVrFmofsp1uAzZa/EAhdo9jv51odTVgM3UubOrpdqb3jypI5gFJ+e2d+1
Cc/ckiz3KvQujgANYLgsUxxFVanreiooze+SxBKOGAcIx+7C6ysNZGdawxwMVvRd6Its2tjy/nnx
x0j3Pbexk42JYzNWxtbU4z2l++vA9xZn2rpi2Zgzi7ahK585H2Hw7GJclYJop+EYslN7Qzg9dNvw
3aYyEzm4o+lNt6IoI8G5KW48P0QJjVQ4b9e37Vs4zElpz/uxYqU1lsAgnyAHJhhUffkHRb6Knzfv
VoWkUrUdX/Zz8ceoykL45nDjTdHN28qkoGnPhUO9876ZwMC+gFBOU0J+Vt5/72Xwdf4TkedRNiYj
NTWmtPHX/SWtPEsJ3Wnsme8yo/7hwhvOj/2PCkeDDk7KfinZmKVqm7oiDBgj3RFOk5ZRAcqpNYZ/
s2WDlMd/pypkEoNCAYg1TQK3o98/vDAVZE3m3okVrPjr6gIoE41DaB7Nw7eNLBQ+L+FNKCk1Zvj/
TbP4lSpbwkftVqVwMf9FkX+4BwtnnqQuU3I7zNbfwNbJWxg+ShMOZmlsJvpXKHyw7+QzYMXpc2mo
9288treID9C1HHg2WC5FBho4+CsNunav0e94i4cS8s//GpGC2JxL+2Q9p75qunke9kUjSvkwJ7YI
6Pxkhn0dJaSh6HCDGj+Sdlx/zkhFaL85xzySdJU9EirznmAhRMS/eWzgg65FjU5j3ayYcdrYf3Eg
RpVEKULIQpiack6+JiK7oov6GX+3s34+rqyHRszklujUJ06lxy3U5/mldPOuXo0TFHD6A7nCrzkO
GRQlD/Ye1/5Qt1IEoho3tuOTvyGThmxx04Q98fu5hFLC80463B4pGmn9XjqE9iEuhIzdpmp6U/d9
tV7PK2MPHTOO6itIglDhweeYnGf3xI5cmDB3SDAgikO5N/k0M/h3SE62uNNj4H01E7GWCeWLUq13
Z1ME3QT88UYXnZl8sQt5+oR9tm9ctep5UsH7OQjb0Fy8o6m1mDuxBiRi02FwtOXShLTlQmx+WFkC
BI/cmrHFNaii5EC/JQSjIX6etewdv0s7Es3THd27PBtU9nRMQoSBXoJO+DeKXS2ivs5FTIqll2zE
LL+gfKCtVM0IG/7Y6GYh7hM/XmBilVnWdLGMlIuafB/AvNupIze5LXdecQT5+8Ds/gxaBQZwu7g2
3rT+MhdnVRp0V1JUNHhfkNZsy8IVAEReB4sbbytIO3nQAnTSjpWaixpxjMER4tzeJHoe6MU9aFlQ
Ygqi1Nx9aMWcLA02zO2CeZt77MdCo5b97kYa5rOZM5ybjOPi+xgMH9LJtf43Twb6yk5Aq8C7Nvwa
+GymQWeDFPeKTfqL4i0YxCagsmrvBH7PVtnuWkGYj+Qc8KP0F+Qg6nNR7KOUN/6eCoEjn5OA9zwt
zCcsyIl3gm0dDyFWIdpXBpEvSfX/wy5I4PY0JbPiEdwqqoUmYVhAHH8xxPQ7b/jLWGvRhfyPq+VU
taecyn27515xlyIxn5LYsXi7Gy6903argo3ihNbrMGEx9JhfyNxqPnN2ST45hPze8HGxATRqFpqL
CLFf+ja/moSPHDVtda6wZ1RZ9/EE8mj3mXrvyfe9KcZSRZgBt8orpsqQjq/D/9K7K+woxcASOAAH
xumBo6xLXQwU4xLXEFWt7R/ZEvfsYPIEXQN4Y517DUAlIY3kjdif/sL8FmoeA2xJHmQKBYb3jIS0
I5TEl2Pl2FQaaGJ4j9hi2Rhfh32CId5F9WkHNc/22a6YY7Dtg8FZaGBagEaYwNAddiGsSqxNgYW8
aoDliYCfHOlR7So7CJU7dgObrNBXyrEf58PDoBqZb4U28b0Fhj2/6k1N/o+IMHDTDrZeZTjMtv3h
siJ3m86frKbGmKEzKLx+4zs47ooTqYlkh1IA1HVxf8JbMhehjWX4wYdNzzKfJ2vow53P6nBQ1hE4
dsnfb5VrztlT4jEHDV1xFrxipdLk1xuzS3EiV7hxqot7mdlmAGvWsKfLp7PeCa8RbbqilQIWlYA/
uOAiluSsX1hBfnGDvTL2jXeBJYerNIXfM9VfsNGDocOR7yLoOvDa9P8Uhn8HJEqE8KMFLhJe4t3N
dXbZVsAdav9kykswg0U9jeSEvr2xM0DtB6lQa0dWdMOeisBpbD+0WehFDZZ2d8lqiy1ltTPqLpWU
WSG0G5T6xdANaQkcHG9uOL3UQl39Q2l56OqLIkOKqJmLctHKPg7db5VR7bM4PyyEqt6R7aZfD6k+
y2Q0TxEjG7YnwYi1wPen3/YXGvosG5Ib1tw3HdITclNeB+aUubSIJrtPhkxV0cLoya9iY/474lDN
3QIDxzlPxezJOIC6DYZiXsw2UVWCpNP07EWa+vKmvkEVxuK6qqwZB0zqEryhwrYwbX6y/VvjbX9e
3polAcqjAysoEFMQF0MyztCgCLQxhVlrtIdwKyZLHAyiSuSNgYZc/VhtcOqS+8obWEbUvZp0IaM9
NyuSr9EAltybenseduXJOFR5xYpZ8iDxuAuyVdnRFc7L+bvPUAJmdM1PYQ3tSO+o2bdFlUdv6cTU
eLmBt3FBdKXPxTA6o892JqF01n37ycz0t6sBOD5amFvWvlz8EhyIgKnxIb2T/tZhT148vtt6NAXb
Xgsm+Ma8v4fzMft7VflcvkwiXQaIZiNahl8fegHu1+AvuZNltHAtsKCKgi6fLmUvvKf3CQeUAO2X
tizJsVjTBdX3rJRWP6qNV/GVYccY00Y6U2U/RwGKLTQSHSVPo/M5dxWAOdC5oBTCbkk4Vw2ZDStT
yGIxF5SKLogxcsnNj6juX5G06B22HV0dz9w/QoYlE4Kmzik6iE//mhuGjXIPwFLyu8tn+MU2Rg/Z
oViN0ZL0bchqqGbLyb0O6bGvZTvqYCeoQQ75wllEfdsFR+2WdtulZgNt5cjDmrzTpX5lDS1nWVwZ
zAuLpn587mhMMngtxQVK1UnfWWS6TYJBLeM3NzVOvskJAV4RDSg++FLyWiV/Bl5pTOKyBppC5UpL
bDgEMHnTMGV0phn2PthJN1NU+eHCWy5rqJbSC+eiFNwEJTr6pku4h+qnFKUj2ZduIAY9OIrWJPW3
Nxmg0KySvzTj1KX2FdPdKGS5MQGd7JkIIHq7s+HsDCi3c4rYMEqI4AnnP9PscQO4VmxTLJhqMaG3
Qz20ZjiCij1nwo+DvpagX6/sJWm56bYuSm3enBPod8cqe/aczpmk/uKbUr1FvTAIGp27QwdW5TQ5
lpN9bKvRUSkT37QZeFxNUbBh09X1LY5bg982IGx+Zc5qXuIRjkgFMWAgE96waQyuTIpbkUFAfFr2
7qf+bYkdCt61C4e/lsYPagUCuM09U8zl93umfGmvGPf6j9DCM/h0Cj3kYXKsrxdeD/CViYLjodtl
9bc8KhyiBSCTVVhdqs9UX0Pm7if8VKMHUee6Y+5e9pBgosjGewh/xtv5Fzn5e2kZW39ZdQhkBI9E
R0txJKz7WjK/2l6lqySBA0ZB/NI0pzVNk5dV8xM3EO8vNYjT1CDwJjcjmzI0eoQ5PSiWqH3o0QGw
1XbJg0SxncI6grHfIDreDwvY75BLmseMNwvR2CTusI8jOgWViPEgWL1KfCOt3qHBujT9SinKDzKQ
KNVNf1WeidRhQbRp6rkvv/gpsZjfJQEph0Nkoaeq/BUnCghI/PMrAXkwLTW96p4aAMPM/JxN9jmA
W78mmThytHPRezau8ZHh2qn4sWgvqQtipjIB9T3kJEBObkHJqgUCndojtKk+cjBewn+FY9tKmk3P
OC+94l0WMJRZcdN2kX6nhaoCUzbZ48LHJB/eEIWoPHr76DtoEVHC0yVS6mFDOJgEmkOoWhi9bHWM
jwpZJ7dUaZ7HeYcT55geb3QHDojuVG0seiiJ3A2LZdVgJ5M0XjzeyCyRBDMCEkr2IZp/L8HaEcnE
UEya28qvVWQifgmCp9GZeYHle2p93RQ6d3YueX6eE7iE6RvSxEkP0VzOorEjAY1n3uZVlTqqXm9S
izBjguPio0U89VBzBqzqRaXyn7mA/o24UzoysWemPSEooa9SlC1bbKrUgY9l7RR+RGNsMy3hZTKU
YCLi4SZ7Ssy+oFf3YO9nMRFPshOJr3EQvyvhLAe0KXPK/eun52EsvfYSA+0ofw4g3TPOHw0SAudB
KH82G4GvD9YOuNsZ9SxCdKmVFPtgsF01UhV6lIiQ39MqPkRuZ+tLXdspLI+dvGl+3O4zyYaUREb1
EA4wo1wpr80jwP6AvPL7S7DubWjgHb4nt0bmVJ2YgRGtiTBvaNoalZhNJNa5msmUDsyoTVb4yMwv
3U6MpxBbX7Slc8ot8rEnOPYQ93V1n2/byVXYhcEX+KJ4swM10p9BguT2avf5T22851SXQ2xvl/mB
SiE4iJdruCGAs6oqv+rkOv1TuLfvFnlE6NR5e8hK9D6TTVhZPeUQ6OheAxHI3JlCML9W5N1qoCqM
ay8Dr6PV/42zUeqMC3hE2bC4WIbLhIrmbp0cVBXC6JAdegO0TfHYIhjTE+CucdtmuSySdg1I4vxx
5qT3SySRqhjTcUOqmzVbQU3Xujp5XcsXKo7XsbK23/sCMcM40Y2vcW4aU3im6cInQRDHlShpPCNt
ttCG+TPBx0CbbCpgNx1a8bzJKBlO9eSt5iujSH0aiiN+j3gCNi/1gDnkpcM7Bfd8NYdJG2Ga7Kzw
3XdjnrC20XsjArtovR86qa0dFEW/w9vZOAFyOwlGIz6CPBxQisd2c01nyJH93bIf5SHYYmFbARTI
kPhtb3yFMAdMsNFqOiW1p/w85Ie7e5R6VHQiU/LcKtbwn+sinq6NSEfbak882ovcy9WF0zviPAwH
nno1qhsy+nWw4HkTPfxIpA4W79+05H8k1yZ4GRTpLhruknCf2JoU77mIUfe1XKhZHiY0tE5Uug5B
R+QZw+5P5S2HNinECESTbRB6zG+wfB16tP3k4u6Wt829o6dTAVzEJH+sgrMDwkLcN6s07KVSoneA
gdMH3QoIyCkyxcTUMZJ9TDyNLKZNqgPT/TbZGKPPQYkKQrLmbaz8hhXX+RcnBuJhLpXtuFpJk2SO
Qs8SLfn65HiYK8SaDDA06rsji4lIJQImgR80VIOlU9ZghvDlYApFsVefGTmCu7C+rvbbdJf/UDg5
oKisvlD3S1B+LnJdauMXcC6qXk4iIwt9oSGaw+xz4aKxKB/fmcxiLFb/fyhb3pXwhoMTxyZfI/gJ
gNWFYTC2ZbW8a66K6JtMCAMDYDbuy5PrZI85svkxgmo232cu6mLxiWViwEe/PquKpUtwEdmnkDfF
DmuqGG6rDpTy8UqCDtMf2dogJqUvB3o6zaQndMJiizbNaCS1rPPdinlTulFpL/qnGhY4VJDLNMRm
2tVh+VWR7J7msjI1HM4n66mR+rQ6SuDnd+61WhWMkr8+xY82T7d9j97+uWB4zGcaWMzwiJZsnK4k
sAGMecXvGMDiWEtiMuchFTlA/WV/y5beWDUdPgdVEUP7pkQYKo/hLXSK2QZptTz1FUeJTi89zsT4
N2sZlD07f4M3V+zd0JdVPWusmbq2OeKzLn0rkZYAvBSskARlV3ShgpcXEJpkCrVPCKVu2VwsO8To
vcyn5dHPAuO+0c1tmxHAcsQtFHX6ZMLniyU8CvKErsjGyUp1AUcDuU4ElOC4zvzHKuGwMV0sn3qW
A/iwAjEI3JL9VlVIhznWdPuSZq2hD6qGX8GTxacadP26xEuzsbU1jg1sshV0AKN95kMFbTK+O3Fu
EmgjjrhABhJWsEbqZKY65kk+hxTa0OMJKzrLFcFlnNo3lU+4zi9ZoKenj+AWBERaBGAvKkzye2nZ
EG61OY2T8vK8UBBeD1Wt6klQ9b14lKXU3U3wGf1+QsE20UHxWrseFrX1pCnC5vRvjrdXuCtRH+bU
QYI63AM5hFH2gsCvool4W+oqiGVNNqURvNgPBAVGPARwmQijAuSURvj3I4YHXpLPuNzsD+BZT7Sf
Tf2H4PnsGQ48mzyxGzMvGYVOE0ZxFJYrHFxiQL29s8j39i5Ms7WkONeL8s84UzEqLqdSZbbzJz8x
bToCOpcJXbJaa1tq6H0JA5RujEUl4aMbDWlU9pHzKhPxXR+RjYO912dYriflhDpzpliE6w/Lc/EB
mq6BSZFD9oaThXhyuKNVJ0yVBwNWKvLqGauzluAWAS9wWfN9FbiWy+FEICeBmqbR/Bb5nvAewjdA
1KPEvq6ruHTAx2HBoOO/DEi7iTLF3P3ZEwiSM/MFtMBA1caZA+WI688wEEJbrVS8jqu7LZiJdHh1
GcKJ1MSXtao/nohxTyAQIXQ7rBRPeg+kts75jqRlXcGZTJTm0qRWkfSEJcToFltRq7Ls9ulR33zA
zRgNPChaMVnrQkqj7bsocAaL0yiwAyfqV7mdAoQK1oh5AkVLnFbD154E+ArDVxImSS9/Xb3/Y2K1
Zi2N2gbKB26bDOdjbtoS5ryMch+rIdHDALQf6JVMXWz2YgOeM3g2yCTjHBIgc78OR3o8hk8xIIYF
Tb4PCRfe53Bhk5nfIJ95acS9ss1DmEWaO3U9qwg1f6Gi8CBIjke5SZ/rOUxGXVS/TGSwYlgZEqey
POpQf87N3L/iKPu1CieNvii51lwis3Scs6Rz+yEYtYqtJlGQT5c8HzAjC3bzz4q92nIL+nbtzVh6
VAFX9ZQzvsGD1IubYa71BDmpwNV9Do7DS73cN7dj5OFe1rp5tTlO3XNZyzF/eRei7Rl9rZyXrIsV
Fy+2nalneGilFCJ4Oji5QrgiTZpMofqfNKtSxy/kLQZ5nLdM5yNjNVFoZ3cIkOcknUd7nplibMEl
xUCqohCjQajRrvsKq2WnqGhcmDo/+datBrBRAMbXKDMAaQ6X61f4eyf2RXs53Yra/GwLlvgl+BjQ
514wZ0YZU9lU9Stip3XvAHynACEn8aM4eLYkv2xp0UcoX4O8imM7WK/pgn+OCQK+ZktX5Y6TmQXO
43l463k6tduVZbhrAl1DnmcgcpoLGR4mSA1iAdZd01BCKfV4aHsBkWK17fkSkON0/dQ7vbzIh9QG
BHWS5lNjvfLWIgLUm9IzrpQXlVqshbt4WbU75rp4CCTlq+/gAyiZ+qPExevx2S8e4OjRjIiS2idV
K2zjwSAoXSb6hC22mK9Ue0jRL5iu1VOXpDj5zofsTx+veix8wEDmE7ewVa8IUB13ujINXuaaa5TY
QMXMzx1oPRO4CLoalYjZ1wpII2+dUzuUQl3qyLtCebiRvWitWoku+Ua/X8kyoLCWE+7W8m+7e86H
rSD0cTR4gMVWcQgJAwwRHTH9/cIUtgc5dJpFOhnrEvylMW3UbkOsjH1bERMJFB+TyWrgvOLJJr/x
7yjnnKhWPjFQiz+MLA+P1fcv2Uz9a1rGtxUYHO09BswScjzEfL68kuQsmRgR8RNCK8WEn4ws4MAa
OINBWve67KtEqRRkJnbscSiws8RLvDyK1W/MyDRkLUSpik8AJN9+USszYSnNNsAlk99TfGiizT32
pI7vhIW0SjcNGYOb+tgVm+A1teQbq3UBMi+v5uGAORQRa7BKwYhZGQvEac4kVMpHqUlJokAZODHX
h5HquymAb26PDXkz+xkQ0kEo7N7qMwxg2he4zdI0BEti4+l+Be0mVLxD0S7nlWXJk9xJwKV5F0TO
fw9WoQR6SfY6rFYdXDEMInV6WoKUx+mnY9avQ8o7M1BO5ut9Dnr41vyQMylbokfQWkaJdbFRBWhk
HIalnRpwkVTsQ5EFUAxl8QFIH0FJhvLdH3CPErD2maoqCIGIxRGyXbASPi+YpRvsclK8+f2YXgjt
IFhFpXs2dskBetdeMoGII9IhPiPKtF/r7r1Yd8XwD+HxusNUZnHBYa2datc9nVnwooMW9jPmzewj
8GgDRUoO7et9Hgjzo0/vxu9/jk5utFJApbqaj6K/1Zsr4jA/+OvN8HjVb6FwD9rADe9J4x3AoCQ4
K6mWCxfjJUAk/XnOLyIMolpz+r6HmsF0Og+ccT+ztXGK7A66ZfgAPGlQrdPO/SThfhhpB/IQjqnv
Jb/ZXtocYaPIoqEM4SK4t1p0AvXgX5V8v8MueIlfqzhCe5yP6vYC0qHdAxx7lhYNp9QVHlruCgw/
GCy9hwN56TUPbsWIQoCG6eWJFVZ/zYSmqu579Ig95/oCPOhFqI67MOKBPo/2FHyoaPEKYpAtptzk
GVY/yw5+J+DZlsivXZlBzzo/SqwA+8BPAMaHlx8EM94ZK3KJn0yQcUkg/NjWOvhKihB3fh4O402a
dxJ0KwYv15b9JK/fhOvxgUWfdj2dGs8B3RQtVOYl/SMuC6TAdvjAAla58QW2ZlzJut3q4pR9Irq5
EUpxS6Lr/IxS2OqUcSW7j7WFrzeetqXmMMU8pp6wWdNkL+0ce5hfVXPzzFKtDVeA+0UZ82DtO1Df
ZqtbTUDZyzk/hEvQFo53bDOIGkHxQKL2c+oabY/I6L98eq99lvSn/YmE7tSNaW7L5En8/nD4bMgz
uhyfNbFW34gYuOuxa5VzvABcllGQltZ9IHwpl8fzgMhmH5IXhov1cyrrzazwCoJpaaXSup7Mqcxp
AUnwAcL5f3lqgVNP5/maDuh8d3DIAgx/WhJNaiEgQh2uBiEtkXaBSDLmt0R2kxEZvWOHBJvBzB3G
yWCaWEmFlHy9n6srTIxAGgY5KjOnrrUEKvFeXYvnGIKyc4lgLanXStyACvEZf1jr50A5990WuH+n
EZwpFzOd1thCh7Wy74tZ8SPO4DRfefZUjd70B3lQ6UwJ52ewmp5QtV4xzglsvAW4m7sZWnyh0cWy
R8kxpVH8PYVGvtolTS+92KWLnNG1bG+ko+KTMnnJfx692oUNY1Ok6adVX95ptgaua9nBo9xjoZwK
yHdKroyFV7CPOMeLMlACkksQOIpGjeSKphvwR454vDI/t3oyGlS+Ec0n31bjs45apWW2Au6/By8K
f95m75yq4gPj2q+wYlkdqAtqdamst/WkVXK13qrBLqVoRZ+8HxFskskN969QmAsrJ31FnBkf6CbM
8DSTzFbXFPv/ll1lQI1CqYWuboppCJeDUqXwhQpcH9GAxQFe43yEqC3HhPnBcYzXlQfKp/1yr+gR
nwLbV1LQNd0HK3+exPj0roMvMfcxe9iOY038kIlCGJ1VcJ4UeVIjFiY/F4u2q0iV7UqwgXG0H3Qv
T5lqQKNcWiI20+Sc989Dfaj6KhRrq8VGK8gAqnyW0gbTocXDVfigMwbyxc6mPL+ka1gavVLcISi3
TFk64qUYhqUyNjSnnVUs9f7KmZuMrixshuNEZRbHRpLwpnIbYRD2kSjWOQKk9HOi9z2c4BIttExQ
jq6jgLj1pcagDL25JrZF/8a6NLUl0CLnwwBwLXflCE7TGIZY5TKzmufnhhBvQ1yYeyI+nRWjEo7X
i7W3qvMQ3QgwETWRi1KbmWMTM9pIEkLz6EMDnD7ruDy5aZYoncnre8fdSXBYB2zSy8fJBWIJEcMr
f3BORpeHqQlkI7RQNaBnZJJnZkPgyaU3wpLS0ofOXLWA811rGF3ygJYAo2DNfwf2gbCpsy7gHcfE
R9Jid3XkH4lQVfBJJnwF0MGmFV6FO5s50g9031OKhNescODHG68328qV3S3/FeL7CL8TCAtvNVaE
h9ByglsfxCXxAmTJZDWtpcVFsMHUqJNstWZMaNxmZCwr6o7RgyvIdHu6fd5KzR82+i7xiCmjavLQ
b1tgjb7qQcSp2q6NwUHlJWg+geSXugVVOXSc4E0miiwuhRNpz8WVAR4wzoptyKQFAdYtJIHY0iPK
tkSX1gDF4mqUdv5RaCDe9zHdxqHrw+qDazuKczddF8q9aGC/l2qrL4ttJmfeef4JSx4kwgQeIix5
Kd/lzaAZPctvEZc4Dy8x5emeTGh9mJNSduU5YcLa7OU+TDbjmJt71hZTIGhNhoRdhEApXvLSdsBV
pF50cyfUV4tbRpli8Z2++hFgUn0Y/ViaMbc/QtMmuaC88Fr6RMb/9SuPS/xGAbV1ZYmG/3fzqkLY
0He+SfyFstMC1mabQB8rdcSUJvsaKO2/46uT2emikFQe6/m4Tb+224dh4uw7pW/kUcRa8I8KIHVA
HNUba/F4fVCKBItVB91BBUxYN9wUX9QV0arbSPwbdH+Ioa79v6It7YMA9IrIklq8yUKyNuyg8PFy
anNM9W5oVL89Ag5IJjGxF1tUn36ZudKMP83zZvgJp/TkSoqahHptBDfeQwFJ+bglkUasEYRU7oqM
rbLjOWGcam5mYqHpbmrIzjbskV745peCo9eR+r21Y64La9OKuSm5fEngo9egyDut7qs0o1PlOvsH
cxEW62pAhqP6QjK2oH+MguV0BE5sv2Q1UvGyM0aG654lNIIuEiaCFyaqi96ruONITHfLHyc4VNBH
CZRG8jq5eN4B5e8PYG7cxvxnNyAm98KUPZ0vmDsDaJn2GhVSw6l2ijQms6N9Ig4yAIJjD2bN6QD6
asMtRrsgzomfYbgGFXmCkEw4tXQBrdjKTogiCFG2SzFWV8fZ8T47jUHDpOfweMAIZOYyTQnlCAsY
Rsu+DVUeFva1T92pSsl6PqnbcEZbttPBxQpFLsUQsf/O1j1lSXasV3k5he+hY5WYAO25/TjHU20x
MkU1kZL8lU0i6cnl36Wqp9BQ6lUl0GvsArDcm4uMvTNzjT4T2agIcQs9XqogEnd1d/zuHuF29rtT
vhxXALWkL7cDfCLCzkBFPQ5PlIeNj4MHsbNbAwHTqd1pz1nkVjfrcTq8STWgceA74QOFliQd7tuU
F2kHgOMi1RKuK+qlDFe+Z5gKd/sRf2oS5/Wx+v27k+SDQrLM21VHl0Zplet9C3A+FZ0kofJ6JKE2
uKhmgvixTznd0gul2gbvpoCbS66CPma09D9xZi1D1GUW5RcAevVccJO8xEM4kYtJV+gdF0ncKzwj
7uZ+PLyeWFe4IUMLAhZHkjS7apAl7QuIz7IenoYlTf8htq2W1qA6bi5T/A1Wj/66nXkx2I7F6iiO
JqMFXCF1oPfCsNKpdEFsWm237RCS7ErN+70AiG8L3EVNq0EEZ2yEqXr2PAPIKOfm8l3G/m6XLheR
g9AQDuHpYY896ZvWrXtFS/XY2YXssUlYy3YnPO6PdytACm6kLudPHAN4wNHc+Ok2L/xoH6fR+jjh
lBZX33iBV7f+HWO5CIqJ0mZH7D3i1LSJvuvaUHlPsoBKv67fJyR3ClClq2CAtxeCxc9szaEXgq7K
58CFj6mpUaZpiQERNZiQ2rZuq8amzt35spAp9EnylzkvBoADZ9xtjqV/bUBuq6G4E5hHYYEAjfnF
HV4dGg/K6/m3LB0YenBHoLhWsyxr2kQhO6atWMDlB8Vdg4YtSiQ1EpUDw2J4VZ3YUnpmQQ7dI59a
IVcEeqA8nYRLfuVZk+WT+45PMw1nCZVEJRe7c2vHwW3dY8RFrmVqARuI8a8qyn5hEKUfoL5gxNmA
6IRS/mfqUTKLhJxskAWim/Ozaha8/UcS2KByOG3HBSP7mayPENLHgkFQBkF0/vDLrJmYd49T+jP4
SkMujI6FjDrRrmuLvlLX6otJqg1pI+tIRThx/vtIUy3ZCLXWpy2vxK7owykjZ1pGi/hmy7dlZfFw
gYzsPkkLt/DwrTazfyzcdX1ijOLbetaekkcmaArjBHa0D/vzN/+d8YXB7tXqN63YddI3MbD0oPuf
uWIL4y8snvxtaA5/YStw8dKROa5nT1+3hVOCFXO7V/ra+j5OniY44mPvwmUjGp+vN+caqGz8FGpS
63uJp24I5a7Z2oCu92taP9hwv6EFCS6kkzy8IcdcuJr/h0xAVYD1lsfsZx+AsuN9GsD8YjEx+KDu
EnuPraTxiOCyipBCfF/inpffFwzmaNMo6bCNNPwkjw5CqkOKnhIed9SWYs0+tbReyk3RZHFHLIfq
GIcueO+7cs80FocgtGDjuxlokYddHGkpYlMryzl/E8mLiS1ZNlhwLvuFigEKTGoakOT9dBmgVyHa
E8vKKWzcEWhpKceSCCPzdrwBgxGSvZjCigINoBp2yil+DtY67iMBJPPyd/5pod8XdMNx8PFYgQpz
p3tWUhAz+kvidSvoaL98jmsWai2zoSxBEigTSL3DzUqW3fnB4Wb/vke861koXHZ+j5496CFUX72k
4DeMSa8D4l6DEWKxRRbRcE7fup6lBPl/7tmniK66AYy4kESW2IY3ZFhFcrC2EEV57KdRe/Omp0Iy
mlvxoiklQlpSBaVgQcRvCFyVcXpEOyMYcQUBSQrU2AfxFC9NtUvj/ExrVJY/Qhg18TlEvdu09BJ3
FUyjBNkzO5HWNvuGt9OSPhZvg0hsAulhOkm142iRfPZN0a8PsPUvqt2ON0D/aANroZjIfJwJkRkQ
BiWDjWCK316oOHObgqibzv4Bpwekkfm19jJBqpP3YJFcHOJnCd81F7Jp0sJOfELHo9tIJkvb6niN
rP3hyWvUlGZUWm9/urhQJgf/hcBXgqFsC6oUfEdGl7WRcs7BH7ekY0vOnSlfU8EfSFco6lwW1wQm
VmLmpRcd/5LARtA0rVZj88kReLlJUVxI+7lTWldb55M1CJDBZcZvxWGzqmWTB0g87/QrdK9W5sZJ
z09jJmYYBhmsSl8N2rkQ1qs5v56/yq/rkZ76aoG4u0VGZ30Yi6xSi1drlGu9YQSbvrXtpW1CLIaz
kgbnlIEaBXYNvWf2ohuTD2/7OpNu+MGptxJpA6nNfp4sEn11Dg6VFQ8M1OD0pvVircHtC7pikKGV
lpEPzRT4HBQWfyDRvDt2pidz6w2SK+X9wTWbVCAl+d9LJoYdHDq4d6M4ubNHDnhTkeJlcSfXYM7V
UptBC1td2cSqBmIo6SqNp1r80xtd9nOUZPpKauN80OhFg4S0Bwf0czapQSPrfFwkejuXvuIWN04U
i7nhYoLMYXhzej/+cdiKSNe9xYhuhSApnJrTAVmJfxARo2vSJjWi2nEiMJSt0ZjOR2nxrPfVeS7A
T5Xwev4h1R8aQYuDJhXoRrfWN/PxevTL0egeWMNndWpFLa6r0bb1QQuqD4Qsx9rc71+EHLlgxw82
q9MIMIBIC9KItWzHq1AQfQIDJd5h3p5FlB6IvibI8CZXHE5kHQwkyUBGUs5RtYO5BV2ZRvXTs0kv
dAbZmruU2Tdr0FEWqDNTT2jiI97w3IwAWw9fWe2UscptFvkL3AN8VVZ2TGNiO2L9CLTCrA4Dm129
w52wLy1Sw+LYlOTqZKqyKASXUEWry3OWcf+SbOc60opPjyqFtSM+IT74nvF22AfFdHDFn8FGix9T
WzOkEf2BlAYzlw7DlK8KEBlUd8jWoY0S/EfFdrVtFd5/LMqpblc3IrUMCPwxeOVbiPdp2Q1kQA1l
V8A4cblabnj+GeSfju65M+IJHnif+BL7JmtSk+jy0B8ctFR828Y1g1fWyhp/7WdaNlDUsG0ITjkw
lS2VLP9i0eGtcYZEdeJW5GlfALtcMslmxPHAdoi7boQKY+PAobNlynXYAhQCBv6Fq6kJf/usMT/P
3b8AucNK1DH5IqwlAHY6IORsHIuUDAkJ/n9tTN6K3QZSb26wOEZu6KNCm9ia5ve5OaDAWFg2+FgX
t2z9uWOgJDPHdNY3BZpdzqoiOZYyrDhHv2fHPZ2vLxv2iOAWPVzLQVhMExuAp4aq29jg2D3LlYbU
Khmnys+gbbJTa/Al9wSFmWS/WC5atimyMnZ0itdzYYp3lBQBjBabM1S7sRpzGHpd494C+9U1iDg6
kAqxU809ushTBx7prxiAK0osWgU3wIIJm8TcGld81byOXTYCB5A7EyxqgVXUHVjqpTExpQ3CxExG
NqDJnJfCq/PMOm9xsdVJ5w4x3IOxnPzjPoGzXMUNcOJqlk9ZuyJ5EcjcK71VsUDeiykWcqXEhLDq
9iSoY13zNZURK5LYlcCIeyEzlIcILzHTNWvs+nfvTDUDIEcqDVLMA/wMzZcsbMWubUsU04Csb1JD
qQ9qdXuCKchgUP3EyPOcNa3aP8ez2m7I+v7mtcaCzer928pWHHvJZJn//O7QTEc7oBh+4d+V3NEB
+iHTi25Gb9ZVJYeVB7+DekbTofB7qI3gB2aOz+UUWQfxtw2gEvq4D8XCl5MnYJMONntTV4bUoLIw
/HmXsSQUdVI9JAk6YC07rLcl56UKHO1lRqEhoLbvVff79GC6L06PjrJlbOn3UcN6rFWlSxWlMjcE
DDN1JLbTNplMhlJsO5mSGciSL3xbh78/srk2tZii26Fdk5tqD7rm+WJVSONTHIREQGNTz841agWF
vFcIjXLkn3vY74Klo/pEPb7gmW1EkgL1dqhrsH/WeTO0N3AetcTTK+yQieqHT3rDJByk4LGlPe/F
3dKSuhEZk4sxhXWMgDpZJy3s/Q9f6p6FRNyrkF19fdj+OHmkxxwEOG8nC7Rc9/+4gkW4U6bdAiLI
ESgjikbxiViw9087bGPKzzG76u+2h2hVtQjUc1jqdJdURdTJXrw95X/+pnkB593uoW17vMx2mRgL
jrRojpsdNJ79fwn5df8lMZzis72tzo1w4HipPEwTDeHZkp16spocnQDuVwZjN4Fvcrj7hfW6MtNE
xLHUOJi3fQM61aLrSz/84F8/Rcyl3TiLJ829TNIHroerXf4uKbuqUJAG8puOJFshsqTNO+hS98bV
vQXqCwd2FdLG77Xl01CTjr5FTK1WynKsaCtJVoADPOV9y9v5bGvvAJFGQ4Xq717oD3ICM9E6uNv9
cY4j/KHEYzlBg5XD1iDJxizylyGh1eETAQdpZ8vidkXvLqsXxEbNufffh5kIXzsqtQa8FOEAo/p5
2shxNq/1jRQuB0xf6Iaql2SeAvwnF16O9sO1LP2kXleMTKl5IAOs4j2L2xRbUm6gSmac38ah3Dze
M81bri/ux4Vfsoeq6FsNo9cQjq89vnpkKfqWEdRBTOGRbWk7DKp5utG0gVc4Zv92eHrvXJzqdbA6
dNusjGlhIvVXGpEjq5QLsvRjjIrs7sPvL7+fb7SozNb+e2X71hQRe/VMJaGhfn5S8iwi7PKzVIHR
SdfDu5jIJHOsNwylG6h6LpfDTfbTFKH9WOwwYJ7Cl2Q1PZPsmO6csBCKQzPmCJMC0clxmvui4dXT
3C2PjdAqYH1ZM5TaImw4v8N+ln7Hda+XIBuiQW49crr19sN5ZnENOzyOjHVvl4Bu9+7wTPZ1Sbhh
jKkqKXOmxGew9X5B4eV9bEMCclRqfNEI6RD0W4w15gKJ8/ViVSa82suVoI/AWdcHHsplPb7LVPV7
c8u+xySKF8pk2X2To3oULDXin+KEpSxGoBS2dhzGCBVPBJbEOGJZInozj3F7oSH2vu5Yaf7mC7+y
ve1zCdvPhmFQSr3hHDmup9FgjpuEFJhNzNpwKJBBIBj7gRquXqa/hmIy18TzErx67QapUlwVtK8j
jMOIZJCXcDoTzIZxUcAEGzyXLYfmQ3PQXz5UjNDjdL/EzsEz3tC8MGPi+1tGToeu7+N6dpEHw2/r
GVyeI0jhfdZED2zce+OquXbFBDsN7sfwhqdZeUZZBdr8a9CDmt/dLMsP+f5qenrUlrX2oOb+cSEO
LuhFxcdGSioDuU1+7v/JznT9h/Xsnft8W97TUzaUfJ8kXau7utAXl8qpyPuqXklij6dGZFYgNbjb
GlpQ14CsPBEa6hHpIJLn+sCXyjrTu7k/w+zw/rZfTCTYj7yyKiuFAVghkZbAY/lOlxd7bSMYIWu2
kToWzNsun6cIyI3N1JGdZQCtWM5qFZYIJdLIzJ2tvx/QWK4BglIEHnEzIUrsiKYth2Djf968jyN2
PmnYKj/PjcpJBoLiWjI6f2qoXhZoM6yFPRJjvpXpgjEXEbL7RSrL2f1wxhEgizoum+JBmhuyZ8Cv
ECKDpdyevAd12Igke3JRxcgwNwbSMH/aMqgixBWl9qlojZBu0y7Pl+6kr2ta4kXhgwVLplo2XfS3
oyFgzPuxBA6hCot65PUQ5pALgdmkaGXZGkJ30H/PCPJRBdVyzHHfJEfuV0Aa5TlcSjMoqbKSdJBG
+5KwH6cAwRgDMuERqzVqiXwJvhGnp+1zFyxC2Mso9ybzCRyqzP7IvMzUY8Ugm+CjVrmDzeFJEpEn
e9fG7twrv8pibikjK6SC6BavXJyKqx5eKB7cPIl993M9SATQ/uk4zdlxDNKVXSw7epzOT5ml+hXh
Sv7wXzimsFwGNJFd/MPUorj3+kc1lGSe2yeiunfT2zI0o9CcpVI1gzQANoc1dPPbe8i1/qUR4chf
6VNxiULC2uliypGTo7elO1MnwT/7j62BCrloDB1piOlGiOyid06HwdSnHVZtzysmdhmDZtwVqiDZ
gIuiWt83mL5C4e8Zs6KUMeYjkMm3Hifm6aX3Fo9Q2hl1sdPWUF+DnHRN0/ta+/TSnqrTp9hvohWq
MTQNGsRjGP5QmzslXg/5jtcxq/viU3KGw/nkR4JsdVqmecxTfYO73mFA4ubAZJh/HibHhZLFMxo5
KysRYFyGhcVDQYyg+mXCNosIOxBDpN5TSmvtUclFfIFeAv3n2NeKQ5jxXc0vFADLE74E7znlL+96
hBO5fpS1D4JZFQOlRCy+Zl+Eioubjg6/RUrY9sxyyU4HbQ6EcziSn/ECKQUPphMrYo+Bdwvm9/22
D+UhU7YES3vL734sx9pDh49+x4S8HYUAWzu7a1MbFi5Grt4st7mvbp6mRnG46De36jhMxb1K3m+s
BODg9ron9B+OdLCCC1j+pf+aecAc3PuZndysSBp+n4sjm2L/QXQVDJFcTs605uaDixG1llRukkB7
RX8Bxks4wGg0gYlfTI9T1FTXJA4KYCX7rAR59nVI7RAfzmnSYjG40FSFcQvkRscvRf1uGzRyGLTq
huRLhmKmHERklteB/32lENajYc//yKkmSlYYmn0Un0c3sPAck88cBuj7wM1NGiwaCeISYGGmOEqQ
MYFWbZu3Q+nSoThyQUoBFIwfS7vgFcWYIpIFalxB5brrgE2V9HG6HyNTXeqtLotNoxOB5KjHGVpR
FEcpgXj7j9/sf3TRUsRbI7X/KsqiMOV3HRzi23u5AGozgHXKktj/pn0kQ105wE1OTyLnM/n6AHeQ
hVcaklGIYcaVl0tgLNWY0bWc5LiqlwSJo6G16XH5FByixCs5Wab/oZh2N/RH6EtZu59/A1rXE1xc
I4UQKECNZc+lZXVRp2QNm7EF3Dd7xqZgRLgXyWFPmqnGoKqmVuzxhEWTt+qf7K17KdgZaxTaOovj
hm6puVZs4YbR91x5xO6ztzQh19llR9LzzqlCI9hTpXqZa10IBvTbbtTNFnUkmXKW6/EKifxOC6Jo
4lDveI12VRN5PotHPUmLumApNDlc1F6T3E/R3780NPLl3yxJTIqsxQh298SFhDz7p3LiUTVte2Us
m+Pe8egKezHJ43y7wlkPWcvXlUEEb5r+5TVwsoAL6TebTm/n39JFImPF4nOv6sKxd3SfwSd+EPXn
MQ7arb0aoIN9f1NPmZuxS0Ai5NNy7OIiX4dVQRMY41XFhKlzCCGFdl920ztLAIn1CWh5tRYqu4nv
mSpHykhsk7JMMcU83Zg2aCIcIt76lvGofyxgQ6SsK6ks+VqULodCUwFnow0AOfFAKFd69KOQq9wf
MIqHS35d/VsU1wZmSYuxJde8c5ls9iyYtQ0L+5GQ3J3AdmjunrIHh48J14DhsBA65PfIVRTuZZLE
4bNHDSEmX02PwVB/rYvNLNKU3mxUzjn10Dw/Girbt3g/01ysT3pJlbznxp0t6xXPzXBZNP9SM7nU
HdyHObEbmx4/W+0p2R04m9+jsFg8gkhdFVkKIHEqx8VSdBVqs8TVZzRQbega1lpuMQKiuZD8TdI9
ebVhvzYz39wiNN6T/Ni6h6nsJBq5W+w5BulfrqTimW9nGMHbHjYrNnyREp36gpjwBqe0yLt8Jbqr
B9sy9m970vjMOGDhJBBVncpLs+BvSJip0UPUV5qisNruE5qpk/tlBMqNMBq9/C3JtJHNi9aqEi8U
sPLro6rDMDfrLsyG4/KBy8SdUdrgHSutcUXp9AETMD9AWXe9u8I/djb0dDCLLYc5mJ6t0Rd2dxqh
ORWc/+cgJQq9L7XybQN/9lHeRyAetuu0f8nLwfCQneiCWQApGytKzPtbveAy+aczbjolySZ1hUqk
GCNIsAPKthOfzQstCVTmd487afx9iDyFYexg08nzLGGD9bAiyf6wFcZKh7ksvefnKfR4RlC7kH4s
xclP/iCiM8FBQ0ho549BA2QH75ga/UtXuBcYMkOjFwvZ90ovchiBCuX8dehboaF5w+7B4D6nqbzc
8Ia3CdJ4SsoPbFRyYjX9+CUcFezHsgOjXNpnRjWJ+mp1haQEDdAC7+nFQk31snRBRQ6GRcWw4Nfb
sjCoQMQQWKEXsDO4MV4NFCN8O7/qX0t7uBn9X3AIPJOZM9ZQw8mtaYuts64HdWBDqRZcJnfmDPbb
6W0ooJHBcTW5P6bqLYBDeTFfl2giucqtpr/e7Y1z2cYk6IQux2UVumecywK7JzSq+c6wfpjTAX7k
fzGsp8Usp2q3kIz3ZOKcAh6bLkMdDExs64rzpO0dQFtlFab98O5tt/2AO6bfxgWLn5GoHKslBYIo
a6zkUCwhazFfFq+wXTMqMZjD2quevckCnJptzqwJCUJip0MKFXzNMTR92tYZBbOUHoSbKkjctC/s
1/5qWG42WO8uKrZTD6b546Bp1Fscv3gTVR44BUC7KDkCTk2esF5fLNajNBVqgSotDTKA0Z4iIjl7
5GN1d68FjtAMTMnxiaqaXWwoQbC0zOUrMxTFeL08h5m+HnLBciNl6Qiu2b4UuXQTOTzQl5I6mhHF
jtiuLaNddNOXdShhTzjNqSBK/DwaMP6Syf+o1AINiiMk4B3xVXyrIWx4WeNBDzcvntFWpjDm8ShY
B7FFKNVn2Sxwd2SjNB4HQXwFrUn+LUH7oabr3rT95Hip2n/24UVfyhydXjW7twvRFET6j7fFwfgN
F221nSZ5CEHjc5AyX8QZMk0Tz7JOd4+jEhVDULgJfc+8x/7G3vRIeO85Xtf1qaJoPd8qy3frfmYh
pEvT4B+iaJQqa/lf6VnBhD5znp6hcRwW49ha9Vi+NStO5zX/HnlXfxiOWgwbS8SiM84MmPB9P19l
N7N7q5O1OEvtaSyNHah91/0ntdzv/WFrBHxDq/8A7qSczRGBURqmnflwv7AY8PvYd2SfcsgliGjc
Msa01pcKESGQ0mrUDTfBPne7VxdwP0vxhbC44jwh5X0b8jvaJtPBawXF5/FfPcpPEA4qSmdt6zip
oKxfQKr9WkcpGdbCXNXeMXt6dGs+BmJAG5VPCiTKxK4CXPOMBESdfYFUpDhJBNHrK+MD7UTdT8z1
s3AsZXFC/hWyx3HRUykwXSG1TdD8J0fSxREnkHZ9Dh8S+jf415+fGSq/WAyUIF/k7w/PV9g5KBb0
RRZ3YFwcubfxwZNiFuO7tSD+Po3T02lFhQ7zpJk4A1rH2klnbhK7Sm+AtXp/JrEMmtG05ue/yw4I
P0s+7ttr22tqa+pyUlye932RJMBBvyDhx9x3CPDHI9PAnRgZ+f+n8SwmdY4q4bmIxNIj/mXV+A+X
0kXnEIiCOH+Uw2MKJgUcbJi921lgnOdkQiQOfrqzPMjAbwy8ixGvd8TT56YS/4evdguo7BBsX61T
KvJmUVz7/8uKZ/gHgcXng78WuQdcTM7W+mCj74f6FI+iUbmCsnupTpyPJNcl/w2Rn+fNkWcnsKqI
93/S5xhR2IyYH1yIDIXBf/GNcCt4Fi9x7lAsZd7y6ZCXk4GrMqEi9Ll2uK8v2wd6RO332hmin7Y5
OIllPM6hnweWvRvMJEGp2SAY7klK9HpLmx49r8Khmxg5pl8kFLU9/aamTCTrdKePZFUnRgZ+c5Pu
qDiWSe2tennDKJsLwP2vLf881e/BLC/nWv1aMOW9ful3Xa2j5W7UP2kaYLprSi7CbeSe2onnj4Ff
DLQXefbBKOI1WD+2yMMyQnsE7zGHsWq7Ue5Ede2ZKIhiuObW8YrOOOw+vzXPbXweSlY6Q+qWdsAK
0T8RbKqIrP+m9+KiOoVW379WzzdAEjmMuy5gKb0IxVMC5A0p8+5nhmXiplMJAXYuWH25I3PGLTpJ
FVPrMAQQfeOFZz9ZnY4mupoK9Ymh/v+4y+QYVYH6zJC7/O2lWdxqK9agv4NdmrnUdMyFKm+oRbnl
SYlhQ6GntVLo0SmVqhWPL6I7ryvbt8XSpvoBxuYq6o+jxwehtc+0G67K62UTfDdYSK68kAf6GCFi
ilW8qbsEUoD+vjmrfCG1I6+oqyY1WatHHKhHXTcb65yPIOYJX5rrKpPqR0u5KGjzaW6lAe/DsrpO
6oPXdd3SMwpwkRwJbZa30DqPDh+S8wgG/8JrL9G0ucRER3tqfW3+Ax1JYERgM8jZi6W/QM6Dy8ck
grd6ehamLtlN9cECJCNDrevK7GHTNyao1Aes8tTC5u9DYxm+Xvh8HQlRAJDq9RW2iq4YmrVJgO/F
eyBKrp6zYPTMvvp8nJIHFx88WqAuNPiigDpwoHUkQWeUdC0bJ0pC2ooql7w0e/+IrjI0jpRAXwVE
cNghFKYKhGzr43b4ic5e9eDkc7hVO2LZs/FlF9W0r+ESj5DXAd5sWTxPVGPE5IyZincrhU702OLU
CN5LII1I9NKVpcneTB1Jkl6c5vcMLhn1Anqu25gizDNo4XVgNySbo1+W7NMYE9HqUy+I6xwpTvgL
zt/BTTPykoopNWaLY2C1kA8O+FyHbyOHKZFrh1WKUVX6DBpIgFdGDZMwmbLKmFmp6dB6McCmJa3+
14rsX//2WwfUbsI0jJqdVKIcLRefGz/Xbiin1y6DT9gJEhsZ/BbeaY2nGih39LEWt2v20ZoYhCJ0
hv+j8LNRpQRSS49qCfUg/4ElUZFOdU03DV5FpHG0zYcq+oeem63jD7aPTQaQbkEANH6C3ErRYKC2
ad+tia8nAmB9/1tOGXpzXShXreLcXRux8G2j7KoPpqsEqX48AMg6MiwtgdNgmqmcPyVYqR2oqraY
eMVOAIuw2ts9fS3J/PeDDKy67+EkwwfkQ2ri4O2mBIJnNczd/Xq/3PFc8BKnhQzCmAAndus7t4yL
VpFKxZKo7btWscHYQe1hYIMYoLMVRz8I5k7EzeMutiIxwKbHNUvuDyULt8edLn4C2g3/KU4GAa0G
d/u3vwhyEH/0UTl+KoKzM4jkZ4xlV5nuXSQ8V4xf4n+kq88giCfSN7l56gF4PruVgN0HvpNYpTeL
iy+AJ0oKbvS5mFH4OvDO841q04nwytKUuXXVFTHBOR1YoY0JwmV8Olkrq02iX5hWv681rhikzSdP
Wog8AnzCbZVPMVwoV+zxcHbauLtplz3+PTTbQxOFnZB/a0dbUP4BNBEq2CkaeC1CpVbWUia/y6wE
c5g0k+scJgGjIQjMNd4dQxFi7TPentRGQo/+IBFqMnrIOHPuEc+riEdnT3qtjBI0RbTv6woEdOVM
gGN2gMTKKBUmSiH/wqQqJA/6S4/1t0GMlgR+RypzLtov67mdNd6zvSldRzjMTI7SPKRCx9jfGA3c
rycory50WUaMwTNZMiiez1lkWIOZzJDB796C0W2jz31h/GJsMQvRBuex0hTly9PC5gqFfxfcngPp
VMZ8G+p1Qtn1YOCG8fbL3ABwWyWDROTs+JNdQLkDTo6q0kZJVZm4Lm+c4YVzD60EJLnH2TQCk0bx
c4QPGsm1BIwywi20xGKfscAtB5BjhB2L0OL/ww9LJhfP8ts8vm0WxI9Cg+zqWM39DISX0/CNyUS8
IMwFO0Mxb5OwkBoYnqHf4iVajsoni5k02fmE/I7gRG3lq0E/uiiCXfAeFRbc3FXZaNguu23StMm6
Y4wyqrGHM1V7n4g4TLecoGCjnqNAUAhOKGe4mmwKzh11HjWFRi/YkoSlTLsVrevfepcdxjwlFF7K
8yUUsNsYjXFYog+OOQ4TB5EhNQ5/1sZROE2LIx0I64tLjOVFyqW6V/eEdcv0R+QtHrSBJkyWLpTj
+SePO19maJJGD4W9qIpKCf2UNsL6+dZD3aB1uQCxUuS9CqiSmyT9Wunv8tRBj/eONbCwqybEfKk2
n1Lc/+56w8p9sD15PslKJ9h6UKc8nxOvyOJBukqoAW2U3+hlbr7JRT2ipNP7okwL5zJcSk2RJFfd
Re64+BaazveD6pbPLNxjPFxueUdHfpUHwW/1ODaWma2uZQntHiNi+cWiRMjwMvUM1eZFKwGwdVrD
3aOJRcPuDBejnY9J4pLvQLOCxBk3002gxv64sZ/nTvhrgkCNqJv4pgzSzCisZwTJa8+B6wZV/6Qw
t71aHaiheUqBXeK1Q/rseCJRxjoJTsMrzeoldLFjUjwOINyfnODz5PtYPIGm1WaV0e/mEkwKvGz9
S1hb2K6V/Tt9HF40H1KifgmtECv1rb1yIn/Tk3B2DfI9AUG3Ab9rwEIqNkySZ4UuKqcGMfTQ31cE
sawZftEVNZ5S953pk4xceUJ8KMEmcDysPa2mS5DGBSt2Ws9k/nVvb1sry5mxJnrKFgutGj8/RwB7
/vSau+LLKfqzIMrPYAbg4o98eEnQNUjTsQ0eJDBZFkvWa3ALAltRVMNQnlTKfA+gR5dPA8+WbuRj
pr5Tzge07AF4HVoVVT1HFVy1OEkOXAAMn4gS/bnAdREL48JCmL1XGwMRwYq82AcBuLgY8Bil9kh1
H1vGmqJzKjvwdeu31H1yhwmZEV9gyd8WObSYP1/uklDO016QY3kxbl45TXmQR9j/mEEbc7ppgsWr
jn8ymXppbcm8vM2eKN/g1wAj5VGwSsbdyhqpSDtW/Og4nQS/IKNkF9W4nKgfy51YS3iYUiubszD/
9JtoaITHUZ+QK2ALjQFUjegmymJEYNp8H2A+Yf8OAL9cLACH1WxqZgX80DI+CBNiOTNPuo5X4U2Q
od9Jchsvm9Q6YfuLXdgke4llorN+JU0ykXAboxsw9DaI/QGZ0fQrCXAqYs/D78PmLJdY69kir13b
pAuel5ZIw0ySbHlt/Iegf809xShr+6J/jdzteyZJCYXN/zZG8wmTdn2pfVni6dJ1nF3QezOCSPQb
K3HYA2OyExJsI81wzrgAZ9VhsZ4BTkAku7BMahZP6JDcABuRM+Vpz75eSbjs1zqbcHfmLax8sTF0
2o4C7T4kUl5QrS9YZZVkJ9wcbYfYwD15f/jDppzvBAf5G31jnT6G45sFPbcvsz747jCu5gOYmmjI
EMpUhTmZJg48xT17SRkH/iWx7bt6BmScpG7SN4TTCA7UtPyeTvVL3itr9C6I7spcyJIJc56K5wEe
PsMtWIWfmdgZ0vGKhq1yGoz0Ga6ZYS6aIthZdx54nEsMGR0nyr24Ky4zrSe/JjTI9avUpUOtlMOQ
VCv3wfYAtjD33Bjhhdw6he4fD2vDKDfnQ8D1efkPJg4EpAMaf/ZswlIkKVaT8PmbMgkpEKUkO9ny
czM3G6pQSuyDYDMpkSMwt+r6KiYevHLasSl2WZt/E2T4NZQ95efmXVEXpnH0Aer4PJ+adbkGkryg
vuoMGiwQ0FZ5yWxEgPhdH/TNaDJXHZ02SVJpXJ5lfpwgFUVXSno4NiKYwgtEzXRgh8AQaBHpFi9z
MwTT0qhTe9illHau13yBhN93ejNYgBtcMxUkThqAwSYle4WthzC1WhXSWS0972Rw1orNzhM5ROsv
UWwHJuJ0u39kk3feDboQKh4TWTChrhxd+KXU2bHjE8SjPcJTriOkDck7YsVY7+U46YwPiGuheAKy
kXeXwYjndRr5o5Di7rc2jceoBxrdOxbzYKGwouHpMp1vQVG71wvdbJTHt2WMOPdSVdj5L2W04+uR
4h33pGK2sg9mBK7FAaZfLL3iede8ql8MhbnSjZAZYfrITyDNYfuk0AzoUpzY4xaEtxOmdQrWMLVR
NfmK41OlG5N5PWtVEuVp8QWw2VkeEQESEH+138wtNesFoGLCyfHnq39gEc/6toI7jvO/X2UgRrRc
tsbb6hzVDov2U18c7MHtB2N6Olb45w5VUaxULhyz8I+rhOcOjd7ik0GGl2aW7eQ/6nWpPr2AcCb9
UJpriSxLpo5k7Fb1hNXDRhS//W7fiGvf587V2RX8zl7WyxSfYitF/74qDZRs8KKWhU7z2JbYWWVO
NZNAQm9RTHA6KqtnCjSpi8s5ouBxLB/D+Z6feOI9xRSZLY5A4iKxhT7hvUwjBWEMx7sFwXQa2iwA
456VZcYPdMngmBNncIjXrxmu/jHh621knaSjoBW9gBqzeXafRd4pAtKW6j2khuJ86Xv60zSviLR2
OSTVYm8jd9iaCD2pFgqqqzEp9b5VW/XD+REQPYDOHCWoZqu/c4Ls+OFuqfCuiRz3KhzyH7DsATLL
UHnyYihIz+axTCznM1X5kMcDnL8TWfSbwQCfUSuBu5BoYi/pOjIC7sx4YMCuJp5Dn34N7VEwinLS
FgjJVPaMpt3VVSn16DeTJU3QyxfynrkQHmGRID5Vt6BVjfY8ZbnimV2uYu3pvwx5H+dVZAdBqF9j
I0yhI2YBbDIhPVdm7tgpgyQwHjlOUJEdEdBZFiClpszKPjQjkh7LGVrr5GZtKiVrqWD7PNNFXVqu
qwua7WrHWeM4NTRdCUX/WDKppTmy2z5A/WPKpqwqSAOroLhNMfiVH+0WTZQpnWW4tRdLK3egohgw
/2MQ+kSBJ24gUNIrEkuw+QKiCLe94Z5UfG3I1bHqfvPRzAY6U9b1A3WyAqYbdzGb2upZ3vSDNbYY
2/fTIw3Y63mxKJcaOTOGhvoxw4eQ6mC9/3PdvHScZWjPQ4B+JUSkGg6WBhi3eBsvVXQ7KPFbpeZ1
DjEyudvH0eU6JOP06stYUH1bbd3Vv+0HA1X5MgJJWMngKDAw43TD9lp4krUdCYEh8RcoMiLdvJxn
DWi1Tk0SZ6whdrPRY3AwvB2POYo/T/whZSeELgL+JExtksowpOrLX5wbqF1N0jvUjvbIA92Qzczi
9xHiF0Q/9mK5NYXAtFSjphEdFgN6DLYyT+S13DICiWPnhDuVuNOQw2LK7N5iHwzzapWAp37s0Xs4
Hr2WtBbFO5R0Ov7oEa3F+/BMc7Am3IDlP9UsvN7GZ9+gn65KK9jfIxkpw+gtaAthpWx1GFr/hcQT
xwmmEJvLqDddC4Ua/PRVUWJioLv1SDLK2Q3V1MAizkOWJrXJdwsgMm6AG8zq/7XPBq0RD8/UcXy3
n7DDjGQk73+jfN4KzKit/yLQxwu5nEuu/REGMi2Gj/uo1S93tVEsKHH4L4xc0CioYCBo7tnVfYS8
xq7BcHKrC5pGjs1jIYoxcKK9ettRnp/AqnheqaXz2XIThA26GWigFfe2tKkZIC+SC3EjiMNVWFEG
mGQgq4YgWreh6JQUHsL/kbiwSEEwZIBoqa6VW2XqsCoe6wJipWuIWFKvZvH1Znhqv3Cs5P9gorjz
TTXizK8L+xSI+qq5Ez/IVajkreJxmbxWYlxRNDyZcJIvqV4rgKlmTZnlfTIaS09bIwVJf2FtJ3df
xgiihrnFdm76vSEQX6xoQR++d4fFvdqqYkg1gnYKvFs+0bioPHHsOUcQzCVxlTe39Bn2pkB5UJQN
Mw3/cOlTsQrMU7F7pWz8Rpnm/e1iqjp+6yERT717QrYV31FPQYnr0fZa6S6mRq6djsxBqrW7+jX/
nN3Kzme4tiiX84lDbXlwJSkarvhJiPj36e/7/nFSQP3RyrRty8a0LGrK2SJh64I2CiBI5oh2uju+
drKKi6phjrghaQqSC2A43oNtifkvlz6cCsZ29pnSCbKlRHwIzy3NV1wHYYlnVNxsukOXV87CoATj
PEZ00U1DooefsBxepniGh/+SdpiFvv//iDRRdollRLBJ1zb8QFJyPm2J99SmreYF6f7tAmcW23W/
NoFRglU7wJrt0aVFu1NX3OO8fGOvd1A6qthBnC2G6RMovpoAkzSw2w6g9Wcy/LcAb0MDLVg6k6xD
uDdM8LP4dEifl/0o/qhxSEO+vNofZLHZBPAt7bfEVtfIrvn4Nj8JFxCiIoQSaeiEuChH/p+hKcuS
3eZQRkRPbXnZ19YB3tZX9t20v2/t6idwgp1MZ9j0XTUFTYtv7iXLf3KXxd7KsEZJuqH3rYM9BQyI
Uk3VNJCTIrCfDA0VVHNumzbUTE+NMS8HoogzuTYJl1OiwBtfaUMl2OUpNf/G57Xna2QGvAXbbTAE
SwuVDCkqd/2JhEywu4n8Hvb/lzM/+rOMnBpfu+Yfk0tXxfkgVg9gN8DJH2BtS1B9bmeAJjC0KBba
p5aHeqfUwMQy3nb5h4SYb318jUAc009O+pRbCq0BwhOxr/jVYbtz8gffch89igLduWdITlmxd/JF
P7OwSg1kxnaFjuC6XKBGtPiSgFCcqBVQPUOHpvlODP3E8T8EAmzTvAsR75v0qzrlvyUTcunzRZch
C4TukASvL22OnFeYY22hCsPOuchO1jAOKf38eycafH5itxvHb7fVj9ipU7LdDfh6dJ7FVlJLkSCU
UDUkUECz/tMIq01JomcNhaQZ6uL7DyAIqB0TaCeYxZeUW0Fbe75tXx8SpUS4idrh89oLsLjyFxsc
S1FM9R0AQ4JaBRfuraV8aie5NiV+YSL9OvJ/deIQaRsNZnqVKOJ/c2mzbWGPRoN91tjK/wLRqaki
mvcmjH7O6Bl/UEtQJ1x550bGP/W5HvjrOQRZWD+ThZs1NdfdTtwmeK+MvtO6sfco9jBmIbamZ0jg
5yXjyZpRXzf+cB9XytS0JlXco3b6JrFgOP3wwK5C7QImT3L7FsbbJ9VlASjwDLxduX6u3WcuYrpU
8m1/uZAC7B8/uFBcCSRiYlEUS/I85wRVk/ychhgpLMD8FsD5g+wKDS97nPEOaIwA4wJ+iZ2e1aew
ovoKeiHv74Vr21jQhe+n8KrMsG35SQXmTA+FNekRjMQ1tBPziW86rBU8LpSzdjgiSawF7WuB3Pcb
+kxwjYNYwKQp2w0kjnFAVm9AkKXqb7O8AOBzQwmZaDo4kYsTcBCSgkbUf+2zd4Dk3rpyT9V7+m0b
s9hQ4t1LXb677Mmcdana+U7MTOgTIFQAZOaVrsJMEizGtbhSHaic4T/8VNlSxS/gCiR2QpXpts8E
weSLlU5W1ke8asbWkhLIuagN4jfiaAtsqdke0RBuAqLq6IhgVo227R7ZGCudQD7XBCdNaNryUPbS
7lWqgeasU1q9tSuYSHfCNKu7kYFZP08PYgDLqwVJrfuRGFkbfRL6P4N4xbc4hYnOcy/TuSDajUEc
WxPXcHwFnO3MvDuDtns9B+vDzGQjMu/HgdV53YwqVcmcLNDa8SyUmiYwZlONQ+xMPH5qNXfuVpvh
sUnZwUxBisyH9dtfwypxLFcq308DDCmrUgv8OWboBUiptoJ/BAftD/qvoShWGmmxoLjlwBEqojLy
LWCc0skVng0zB7B4ngj4IjBwdmi09tIqpdRbDlhymX85tzIBo8wW1ffdr5Hktv7wQ9l9ftKKc4dv
/4AkYG9A3G+RRRsEcbH3emDl1jYvPuug3ow9YCPQ34ukmLKRihwZYbVjlzWr6ZVuKXHP1WbfQztU
aoUwARqYU9ElCcOUDO6YKeFTPfvWFxa2jK2m1RPaHxNkpcVY4S5GuZmQ2dNEhCwXpq5EB8JLQpGx
sPMbxA0lBYiuCxCVHFTel/pgMw0afH1OAJCMjDt4+OzucyR6AAG8UrZ4aBKxXIzgsXMjrKPDm9b+
mqp9panvZVWefW9vfKcJYDuS/JAdfkoo8n76qTnkplCIwaSvBDGO/igQHkHNeFK10Nso+2AF1J2R
TT18FDc5+PiZpPy0aNtjLZ1hKmnZOwJ1WcZ3uQQJDEx0WMY37sfKhuqwHPFh2/t7vGH0g1cwCIgi
xoyLQjzqODu2onlDWkpuU0Lcl1NM52aJo7TllyGfBLBGjf1Z0/u8oRbC0u/MYkpZ7ZmcqG4d1PZS
DLSJIvzMpvmzDVacQOso+VxW+E3kxeF/0bln7R4MTfAjVQzwwY/rs0ciawR9MHh76a1QDgQGLOyN
X1Rfp5ZFvu+fBGDzVS1bnhMOxUu5RyOhqzgeDrSDONA7Wf3nYHdiW4hNSAr8JbuuhOJQiICT4KX3
BfK0ytrLqE6fPsQFztoNvGjh/vY4c6fqGFXZK+j7VAgvpN7YSpNFM/eJC7Lq9/FYLet9Cpo4Bh3c
2M3S+Fr9G2I0khHdhvQLgwtvyoDQW7VNNydom2DiwPjXqFLa+hHnX+XQPwFeqvgI0MadaJfkixzN
7KZxUQULsKMjxjD7UnRnvrexY/3qiBPT6flSoLOo78dBqIp/Ef1k/vk6DWYgysY12rfsJ0pW52z6
SzJP8NCxRa1f69KtVVIblOqHEgH9vRPu/kePm7VmTcRcsBhfoZoOHE7d4U3N7riLRMiu67bE4dxi
ST1s7OfvGT2iWBcELon5f1THzqa6mwNMMMryCNEHnpYfBF4errBHfP5ccU0Snme9BFIpeyvAnWcB
wEaDj4dHiI1s/0ufgkykMcgD6WDkri5w+3gKJ8DFoOFrTxGTgbv8D2KSMeNN4KkUUzjBLb+kjUna
CmZC6f594QOO9umiuadru+FdIOcNcp3Yp9hD1f5YLFOTOs827o1ghsLaL+z8ZCbdlmOLj+KWHppT
MyMMpKwxCYOtgpwYK2zl3PEh/8eXvsCzaXEBhNk2egxeOQZS7rZgsAQJyN7IqRzuq8eYg6v17UoW
iYk7IpJrAqxAFH36tMWKbIVHH/NDwAWDrhPDnrHj9Bdn//c59zAbU+cNuyyuivzjTPea7d4dCav+
fRssOQudwJU/DlFrBRXZ/Q1dhZZb3tKVh0l5MIkInqyb48AFAREYvYnYIrtBxXxCYeUShuVdfEMY
px8bDhdpvvh8dO1zubxNAfWn3wJG163SKppAEjbPndpJcHvaGjcOBszTNY8XxgXlXS8PCKo/GObn
DWva6buRrkTcrCrxpLqfE5sFIkAhQAt/zrRYFtvRsd0gDYWt+rWspv90ExCV3jhOjdSc3ZCPAR5B
t4R7LVDb7e/T1A5bK+37sUlKIYe0XBKb2jCZBPIY9FvsxAGZIAgMM/UozDS8Mt1qpn1qfODDrsdt
WvNBmvh/HkiPpMnFEsuf+5vE0LBrdJ6ZoqscidUObTIQ3gIh2YTsB9hKjikO6+rc8Tv9rY5CDmlE
s2y4yLsKO3OLbyNagvGTo4hujky9ZwxVGn2WOm8Ty97cbvxAZdgP+dkwUrasXrfKV/7XsTSc/R+F
WGXhizxY7nOk4xpjgksr4+5dqHTxccH/ta9A/xbfUVSIK1C6KYSUX5Jqk5m2QfRx5KS2GIEu6MS7
qjANh0xmvMJ6a1KGt2Y7QNJT78a5AX2q86CmUi4moX7opIkcE+4f0fCJtNCRfsQevO/bZMJOSvkZ
hq2AB5ju9J08lEsKV3vguWGj60ZVh8v3GPj8xc9+tmYwXsRQ6gSFmMQ4u7V7U6SvJcQs+nlkgtmp
MDlKN2vbLXM6R+Xbvudv0woZD0yUXohoHDY7sbF2/blppueK2C+/INCLUuIxMuRukXC+CTLjoSIR
rhnaLYDD+baipCT3vUU3kZgtkHOWpvIfTjDj6OMUO+1Dxk7f25OUTrdfflq8Z9wP7o8A1tAXWWXq
7XhmXRvOTp2WFA207rHkJ8ldIABAef+KHIUd7TaeSuS5mrhChmE6nlcP3CSjFdRHe0NhwyTAjyAr
uRZZYn3UU8XH0dlmvfiV7j8RkfoPYK93lD3UepVOYXbJcSAVDtw0RCQ61XWV4YR5f+QqdKpsBWvq
PISEsnySTnnXi7hccUjDAigG7dHgyf0mqjcO0+oZAoAJt6F4JVyWaPivEQDT4rhQRPpQL95SF7sy
Xh+pVthMK1wx/5sCNxrZ4jFA1VDX+Ti2oISD9ruy02P9ASj2Z6LWG2q0yjOhs6i4kJUieF99E8VB
+OCrBxi5dUx5i7ah/xHMYPDzMGTm7/lVBiGncFAx6a92lK8FVQbvTMaNbelAeXdyAFAbZ0Wi37hv
Aeef0jOiE5DoYFHJKttaU3vocx9Xn3foXDUnCZiLYVC5H3Fkc41MurABwEi+9NqyCI7Ev+OzhHh2
oMiUJTsHEDMCFC1rOko7VsNgUN/uFpxjXyS+7KUe0xZs0WPFbmu89sZvS3hjrjxHlODfkp+J+hFk
DLtu7fq5NDwaTd+Yv3jrkpdl5Oe8+9svIdPiwTE5I66XNL028eadoVP1kl4v2Wl5E8fc0w+mPFBP
yTZiHE4oXkVhOcUq7tY0pznzNvhDFVIyWIJPebxDt7Kw7crFGuUW8rZ50pTW0tF6w7IcMHcFnbXW
Qc+gCt2n42diWzJnygoEB2Wou5/p2eFu/VBljrNhbmQIwhsic+nsP3nCOJPbyW+TquzMsR78z0y/
oyFGMzQtDN9Mq+thkh2RXIo4qI4b2P/eXntCDts29gP8SjtBgPapZNlGoVl3zt+GKd5sKUitliHB
UdvEYOBYIkfWSqJFYBkhu+0eudxP2k9QJ1drjQ6Gz54n+Q7U/J2hijgcTw0Hk+W6RG8n/t8DfhUm
6LgnzuGyYR36R3Ti8kY//i3/4XsPrnwt2tDFiI57izM05KjttQ/AoDZQcYQ4LIOyyj9Udob/wmtg
a5FOhapKHBbcianwE8IYAgncKoK2Aws5XVdaa1U80ohNlErZZV6BtQoQ/w1Q3uLK0/MaG3dSSX68
heb8NkNtbtMcwu73dCtvAsqQUT/HcEwxYg8nxibyWgSW6SVYc5uecHH4mZXEl05uuOv2iOsR0IdA
izlKBe4S69zZIEZQo1XlTUvhpaud5L+cRgZ4bik1kiwzq413I/2VDRgnxuPKXfA3Fiv1piJkCrZ5
rzsQfGKpYQFWIVER0zQHsUwt1H3dIGWtNm5sfT9bEEcxBdITn6cwAIDUCSg3RojaukOKtrqiAe7C
Bo3yUWrJyrHgjFDtTzHl0Tpi7fYqMllVcRcILkmZaNxzws1YopqDa9HvdwKWZ3oV4pHEu1LKXr4f
slLZSPJ9u5+dmcLRvlSVUDe52HfY1yglDTV3c05eV9U/EaYJ5zGrHkA4r2Kl1es43Vf/XEGuunZZ
49iLQ0hjTncLcsyea8VJPgnF8AfKdhXkTZfmpvwLhoCvw2CqQiaxBNd8CQr4Q6+xIKRklu3z5YB7
3qyVV67Np3rV6CUtxgTHxF6CI/Spckr4k7iwid8NuoWKBkVr30YSKkGcrpmR5WOc0PfkU+QsTjX/
ou4U9mraTKmkuQQEzDIJHjmm55a9QqS/7Os99GSeIpQHtHntvVz1BKUAddmJ2DoXcHlWbGpyOp0G
/jNCrb1XLZovjQ5+90J+B95k1bjodHoQVKCuSarDIOAiA9fDdW2IXspdkEjDlFcpeKQlZcTQDLMy
AucbBpOIv4/wNtP3WDjBcTJ/7d+x3CQ6DaEGznLTZ+OnKzFev894McJBPNmzAxjPAaGkM8VTN0Wi
w4ueSzL/cJIP4iCQtCLaKqbK7BWQF2pxi7JW8m1BQBQHJYvP2lqcyydu2P8TM6x+1O74+D20yaos
10z0drmgzZz5t7Jw9wAldoF+FS/2YPzgAFifTG9WppomldZZW3dbgMvVGp6P4Wp9Y693UQbp53My
sBQv81XhZGXDrl4Bg8mHjrJmwFMAAz5YdiazDgOGUOhC5RQgOUetYBd4cjlQ+PjYaVDXFU9NQdvy
Crb1rUJZ/eHzkNgLuZczYsPO+ex/C/O+6UJaf0nBKd2KaVK1iEzXw3OZeho2gpjq+H+iGiwr+12L
5oWgkM9Ze+p4zJ+TaBT7Cq7T5Tvq/sAfWi0ex5aeZt7+9/pHim9hn+9gLVql1b43gp4I9T49JcPE
/js/L++0n2TYpNvaCPwVa1yeMrH4eCSwJRwZqenB8EfbV7jO8t3/Og0hocGATxJ+XzkhTEwplpuq
lmLRR5MbUb+FVnPFifFSXNMsa6Cj6WjCrK+Hby+uBOFlrVmDKYNJELaocOYzAfQlBJDY0l6YAigx
jrHWtm05xLyCN1SHJbQw9z4xIv2GfwTh/8lVXKOKgmnWVO6OGsIGaISB/gblhmo4OvV6/RY5fPTr
KTgAqvvp50ESmzfF/WTl/RNjPrC3SWhSzRaTBmb23Hf0PR5hX6PEebC4A9HqxwE0qFmbp2RXLeT0
Y/FgmjJBIbYl5KqRU/uqSAXl7kfwkaZy+FP5CmHKOwxmrn+FetBIhU6shsiT1KTpNSHgERbjpVgV
Mt2dUU4v0m0YdOGgnJ6QcoEOV6R3V6KoA5qsY0B6zTt5DrWdbl17mzBY9kZHbyzrp2j+N2VXxEEA
VTSx1OZuITrIjT8eI0G0mj2zgsoSN3IRgPeHANzcq8x8HD64VLItDw/l+Lv506zwY2BMsPnZNPBK
s6gL958BR/K0AC89wnF7hE1BfP0uSIMaKDAXfRoOf2vOFZ/yBiRq++y3lE9JIK1tksyLFlHS6Ixc
4ObGxPtT05Q6s3fAgrUYgfG+ROyn5ZTS+grfcbA6Nrpo6hrS7T2VvWmJqIbOY1POG4Jda1ZAEW9x
Vli40b5YMr5M7Fo74iIcn3zrrhNUIQT0//QGi22ybr4t70tDWEVCNRKgBwD6BRbO776yOxuQC9tu
srB5mfRg4g+D5zOMKPmOLs3IiB3JAIQaQnau2YZPIGMyYL4Vhki//KM8e785H1zxLdljHZKnC/3w
LKdIeAMG3VLhM2hv/D/mY5OlvqEGtGqFuyvVowbykLrDKueL3IkuNu1SSx9O0GcTV85S5Mbxewfb
ta4uFLseI1lAQuC8uLKX5f3UNkamEBNLqiu5g/XoyOPrnflAmQNBccuM0hMdampeGeNxKhkeEgES
uX80pFNpwvWwiGN3KpRilePcjP5xtRq1CUPiKoHH6R16ZFZP6ncAsLbsWBwOIvuegQ8stGV7dL/D
xgR2I6sE3oDchPBlNC377PR2d2otgs24PgSD8hkWgjM6o5rmRAtFZJ6SuTxOH9CeYTWw9zfZfLXU
UpuyOE/FyupfkVaUrqDer3AeE8PMKtI7KQ+qck2N7ISP8h7Bmlhk1pqYbFK9G97m5/RcKVH6BplE
sbNHzfAx+Q4f9n7Cs0DNm4J0OopX4O1RpkdGKMOIVQg+njBAoHvcRFVLG2cLb3ND3msLTwn5A4oP
tTP3sEiQeiA5MIfNxhPbI/TFzTfV+qJztejQeAWRWPov++xYpPo6lwZI4Qhrms4d1BfB8WVi3Lze
mxcAkxxILBJx3fJLNdRMtB59JxrFiqOuH4j8khWZcKOVT0WFeVzMjBFz8IkdMSLaa29WJyPJfrXM
tB9dD0Q13Jq1PV+M2x2dG5X4QFAlY0r9EJ/FZeZx76Wu0GmAOQJWJWVgif/roMNdI4+x0Pewbziv
w6WmdIntXTSodtww8HJHlGhiHkOKGLDjZ0l+WhfkIFLtjkc6MFUVfjRYPFq4YObFemLM9i2+u1vw
um4aouZmdxJ6Eq3PdBlOStZwO0+vvk0dfn934RI61i3XPIyFm45faQG5q26VGZ+cGknZzx3SKqaI
WJNp1EH1ObJrnTKTHC48VaJ5wqu/MfRh+40rgzjA0PLYGWovILsPPpZfusklaAvDO0brUSgQZXcd
HT+TMRv2hwjtGgsMS6NyrnCp+RLihIWOXfAavs4rFvBisEJEPjmqsTqb1UUPLrIwgZO4FUcBlDG0
6F1DbCCvabb4BdIUiX5wrTnBRrqu7bt47ghlhgmkulZk34YDgvTNPhnooOMdtqVSTPx6lXWzpX8X
TLkakbwck8gap4tbyFmvOidWVz+s6R2Vf2w2K782VTUDtmBC3Wj7mARsgo2PvHWEn6+X4FDxXuyv
biiJSYu+mkUu6rZ+iPFaTWnVzC+LP1zkIecpm0B1jfoNN1ZTtxuvRZizv62t1Ma6zjEzSF1iQe25
yAEMARsvSk/IP6FS/cw8z4lPIwzk8AEZ5vZqJUO/seqCMrLag5C5nGNVuJlLUfQDS0v3372BwSdg
+MRcdV9I+r1IK8QWbU2uhXAYhK5kTXylFu00V8vuIvwUQtJTBK6n0vOKDg+jJvpIZjZqNrIKKcnj
fOpuRaG5NlNraakPipB3TF2eFW6Qz7ZPf4OeXt93PMkRQHWT7xo5ukz5/3+KNirCt2wAjoDxKRm1
0xVAfK/hfYMe4GOWKzxwQYTnb5IR6NEyFs3LG/8n2LHCTUoKAv7V3MnDgq/rSWkaAewMNfT5lg3i
5WFlhP9MdMNq2l78SY5SatpqzdWZBfF9O+ly8n9gfMKrZpNP16/vy0pzP+xHze/iQpyP9onwkFEK
1s90oUYnh3atUq4tEhnT/dvBEusP3fZ+RM73Upp93/C0nFPJsB4gI2R6el0oBCmBuXaz1oMf5C5X
tAtJSiGIvhI7LrMDSDuSO3GHPlD4e9cqkiqb8BFjeN1yQGfAgkHTua9Rlf1+AGTl6PAgTwAwjask
7v0IzCDnGmNcue5U1bKFiXBBNRotU7QjAImd7ff2g6rk/z/juz6H1CMAEUii0dOlZ0h71F8WS6Qe
WAXp8ILzBnTquB6HBRPCiAyPXwT6S9IMVPjPyQC9tsJNtKnDfDLD4S493ODHy0G8cTAdztv9vUoS
p018ZjVi1E9SdyR6ewTwwhvDUUaRGVLljwulDOddzj/o1S1B7cKoTSZusRBPDmJldZbzJ7/CCQKC
K2a9w6GeB/eQWQLnV5BKHWbzwf1nxPexg7EMmwZc7er7LBE7M+75RNmDvJqtHvvqjoN5OEk2QgXS
mkL8kLoKmtwIxnrz5tvC/V+UXq0UZJcZLZlDyhI+0UQcUae69HQzzUcVn1MkjZAZ4K/nj5Li/n7v
NnEIdiiUA/DHWygN/wOopl7cc8CxxcKt0WeVH5LWOD4yMOFb4D77aMbZMUVEnzA1pGsHmb/7UZFU
0taofj9/AHasu7JrfxH1LjcbGXvFk0IHpYuOjk8Oo+y3bbrLNcGt26BMrzHNF24AdDgOnAfTf649
6x3ySQYbF5Zf+xxpKw70tCqGC5f6Q3R9sEezWuR8ducwoUrmsHdDOIlX9ItzkPUjSjmPG+dKmcBe
HtIrG6lu7h/Yq4rkVTakxHvz/O8A6dIL1EGFnU9XoFgamAV9iXENkTfyjgO8J25LPfwuMIxHY5c0
wpeNNfOTyhyM/tP7pHj5swNXrhg4GckGqBB46BWPEljGRa9Xo6H0Vo61LfLYZj6eQAEpLc4laNDB
SOZbQjzDGQaVGfJUtCZw3oDW6avnWcRABqpw9rt7PxX44f0MIHOMwNdAgK5yh0r5nhmLBe7w4rtb
pN3s0HH7DIVOx32GXPKLcFyiYVosdlmOXl0YwkXm9KsFaK1BbvBdchCfbpu672tZxyUHDEe/m+Y9
6TU/qVkFVkLxfJ/VzOjXmb0Buv4FGcPACET1PSq3RBB1giCmggFYylyGNMQ286fCfk2Qcb7Cwz7W
H4gz8ZsC8+kQPz/t6XDp6IEaeJEqdrTyg2aNAXZbB4Gsz1EAoCfzRSD2cw9+MfK17TxQZEwVkzOo
S//BO5++bP0Ar7doHm1VpOc71GsWDpOY4T52y+NaZf69sToYLbnPsqg6dn6BUQaWeJjqSf5VYFF9
Qom649DipQiH2bYRdVgjEsd2hxzuIRx8+dGCvrcjpOWSvtRjLcHKlHNP7DU5YKj5aD4GERf3B9Vw
CeT21ir831D/7CNt21teqox/FPQOElyTVpMzDgD/vKUeLnwxK4MVwGO/Fr3zK7R0K8z2P3gW9SEs
Q1riE1lls10XxOHTG5WxDBT2pHlhzLvwxKJIocMd5Cwi5RPVYROZIh2ken7aKWQA19/VJmvu25Oa
B/h/Dp33gYHNxrPed5qHU77LmO3pSXsiilTxOtqYXIyWz96hqBQI5P38DjVfi8hiDPV3tZry0JI1
JYGtfOTh8xCD2wrLjFnu3vJ070Om1WgtQzpth9/OxBe/4acxrkevLA39NLPyX4/R9S1MW2uE9c80
MDnQ/X0+5RF9eCvisE6F3cAGqevdUtVFvoGZoEgrceCLpFUx2smG6SOHaFlMPI11yC16iUVL9RMw
SZ3cJ2Dj2x39TTUCg4s6x20zTLdNGJzF1cQ58LiTgDCn/4XApPIMBAHJz1ug1Z7TBe5LhBdHqPWX
Y5XjWbuid4+EYandFnOlLindR+BePf052nu8ZJd5K/d9zRYqYWQIMmTfubpF7Ad6WMS0fH8n5tgn
iqGxJBBEVJA7DQ6pR1/ERHr8GHSoueDeLXQ2AvRe/K6sd2OhoPO2VVxuk3MR2g5vKeT3d2b8Bzn0
KVhuNslFB84VfeMe+VsVg+/H9+rCB9B707MesHh6WWRvF3tJ94ym1JzduOYVdrJanH5sZv3Nd0BZ
xfcHwbLh3wKqT8EzY4XXNwph2YfhTFUmSEh62+o2S2O6fsh57MbbZXX5ObZH7lXGaB4VG59qL48x
DrbZsX5sjHv1ZlN5clFf1InYPmrjHlNm75FJM/SrZqAwvTZVhS5Ep1G80zI6+ry0Shp9BtkY+Gxz
lBlERgxmGBm1lsc+XE8TYmIClfJw4Hmvhindi42/8ylkBn69e+DVUmlbnsDVA6B3hosknQ/4qFU3
YmtvGUlKG4hvsWR0+vWwkHl32GqEYD9OpHGqbmTQaKJHlO+0LdmEEBpNRHeNIpFjvbd+ZTQz/scz
+g0gmvxagFqsFCYrlpQo+pMxYUqDJtGGMBwzQTL/U8wWj0VXiu4EdnOCqmEOFvomqoVrd0InuTkQ
GFh3qBELSXshwOlTfsWDW10NIq7tLIt6pdIVccy/Rh+nEgqx49hwkGUplTKgYgF6mZCSyjKRG+vj
wD/vsm7FgCkavj7wz1hJ+Wp4JVV5ZBxqPC5PNMIXrCjTR7XQCOVdhvXM2Gdb3xGWk5lHdQhDn/2B
kaDYs3nBWay4UULg47Vmt92X9qKVQWR9RYMp5SDeJUKfS98LTVqrSGZe50sWhcW36xQ3kisASnmY
sP87f+LlmtdK9NdKCtmqjgVtlo1qULQHQf9Xywvf2DTCp9Xz3mqSAOT9cnLs5a470QgFKi24r5KS
0KyhMZwxaod7Y9+AT9GcpEucRnYZOlZWEMUkjOlsUlP/WsfCbVOo48h9iokiKS/m66sGcNsbHTqe
qxxEW+UAQLxzzaW5umuiMdKFrkg63O3qo4uyEs8/z64JZJyt5XBzoO8zvbXc1sxOiGeeTa8RPsLP
H0WEmvJCxTmQnYaY3dT0kDfOpZKqBC90IiW+/ZYJ0iCTqOxIRXOIGGHuJ7ZEl14Gu52dY8X+5lHn
q9vmNOVOWwwOe5jfcb/1LCeB3HfTzd9ChcIJVAM5Mv5wfUPnpKyxeDnlxuuXXmHMoPsja7MUCxSR
obomk+aMeH9Y37o+YgfcXuIlmqvjnGuVE6jJWWYwufFv19LzfXVQInuN/qgCDlt9acLhXKbnjMbx
BIi/VUxIXUgg05Q4LGv2fUAUGCAmzzh6hF8m0S+rrRSPg80N5D/pWXI+FFzvZffbiYlg9FX7JTBU
GSZ3RqHWt8icdhFij2fsyb5p1UZKuTQM07h62O8vX29IWZwpeXVmK322gORxnjxpGmHNQYhLw6fH
9Jvr/iZLINgnaWIL9NkvfPv8OTjlnc5vrmISnrb5+/+aeJTpEYgYyfrhqjKfaNDgxJcN+aVEieAK
uiaVsUg9imyIcCr/qio+agzmj43ItlhVhncORBoiHEZb4rSFVoi724Z+tjl9QgrXemJ0JlvINbUV
VYJVKmL/ihI8Vzv8x1ltzdrXAnyFDLuTcaC8f+P2SO7ZCkW+kFRKCcsC/HTGjfC6QWQ+MgQAXts5
4Alr8wUOIG5HF9vNJaNSXun+ZlMJYsbkt4CLJXi4ONgdmV0UMxSfYUM2UxnXoE+SnRWFa1qWcx3U
bzzB4liKdDo0+mxTQoYgAfFR+S0sWPDlnWezmU+xU4jICsi3UrApxJIel1bkv1ZYGmvskUA7G9eG
1/Sj3APyyFdP1yhne9fFQXlrls1+xfzfYdSKbBiemsI2iBI82McoAWAEF68v/bfKnGkpmN3tNwjo
J5doyd+qPu4WBQXv+VVob3um/Itq6fi8Bkcb79NAVvpJ6jB53c8a0e6hR8nAJO4IupkPucVsqpOq
rIOcdP5216Q8PajR+SL+J2bAabyPAw54wLcyl0vsXk6zQVtbt3MWMGOBIfoy5uYedRS/X3yBcpHy
IZuMandNFYpYxseJrbPt8+Qf4XB3UoviSw+vZmr2/vLDswL+Fw2rx7/tAuffWOSlQTG1XaCgf3wO
C08Tk7ahhSsDrDVzovBWZNO816Z24aGsskGm3QxROYtWTKzy4kqcseW/m6wlRq7s36LqWklC+SYt
NHxOi2DIHfmDiD6vdaAI1jwe5uCmYWMClBDE8fdiVXmTifqIRHo5kjTwvRjpywj+3YxkZVUyoUMG
LtKPSdTp1Fni4/EvGn1NnaKQpbqU0N31xJGHbI3PCAEXqKGRip1gpvFObhDTNP9OOIO0mEWupZHY
7bPwmtew9VyFF5fawMGxR497wt4KrgI57Fop0YaODZA2JkTxHRtY1+buc6GywUI4e97gLoq65l6D
ifE44ybwDhGGDpbI0Vj6DwrWgHgiChRqIMwagYqWDVgsawg78EHBoUNFHOHbOSkb+rYjPZ3QWkpB
ccE6gdbUGu4G44UFWoc8ZFoEzJMhCWJd+Ax28NeXTdBa96lgDVin0LTPfZD9ZA/698WeBjCJEgSy
vyhrtALJL4rlkWxoKztrPVdFcXwUbG/tpdGZAzKNp6rr7U21HXW2DdEY39JkVC25xFL+tILLPFB+
RdeU/ywkOymxfH51yOKMfqacXtZlHT7n/q++MQZyJV56X0wWSCSVmDYU8sT1EtDhZuiKQ3aM5yHl
68To7PBGwwWN4+YhpvtRITXRemgYCbveZhmQaGjxIQ/a5RcdviY26x+7he+ss1uBf+JjQA39MeaA
4AOdYOaKrZSoYj+eR5MmSP55ls+/ECt108sN41xPRcneSJW6+7F6X9y/oSBmrNo7pR3Wmc26A0Y8
DupvDcKIt8sQ77e7GOKyXmeqqzri4o1wwbWtguIbrOSW3Wi490yAE+hVz0OeV213HCMLY/SYT7hl
dbW2Iayq9bgJBPytK0BBSoT9jiFYGIGRzxiyti42QmjguRuTZwW37fnHQ09lBXbPeod1wExj5TC/
4Kk0RZUnIkNOzkQFgNR0MMdzm55568s1HRFQYoCck+NgD6YLjP44yDr9EArYio1H/JmEn6lSMQb6
QkJmHww0fOxB8QBA2s1Z8h3/WbEEMogoKgGtLq8MQIsz96Cgv8aeQP8trMA/ioyXt9taOKseW+9/
tBWqPSUojpuoUXutI7tgCH/z1qZHuMxg7NCtmI70HTP4lpTXSIxfPD+pwU3mV9mrxQoxMefB/hCf
M2Kq+POzvl2LGlgFy7SkkX6/oKr1jPbhoH9RIIuBLJzo5H3vvSsAq13jroX2+QocMwStefKNzqnu
rkX85U/afyFUtdpFGRN+/xwGTNnwgiDYUHMBIkw5kOZNebs/sJ5rkX7CjRAvxE3GVJIXkCpV3QC6
EeLI6GzTNbk2htImhv7rd6gQp7cruedTmpUKd5IxSe3dTGZ4jop1jZj5HctR213S5XEo3msNp0UX
21+GWyJjL68K0F0sZxQx7F2jp7gAAit8BQESxxswZgP3N/Db6+bLGiDOL7KtwZ7eiPulbrwws9Xu
BeB3hbdnXtc7pzlTUf4Yqmr35YOFe1K+GjwCFLpYw8JIujzE2t3E1CgLDrocTTvm+Pv26omie9rv
RM8hSKHFsEtFvBHDGvkZqERRbVdh5YYEIA3hmSrzNE5Eb6heYd4jOgxv/q+ss85inRZ3BPcwS2sQ
dRkBVg+nTnM9r+Vb1YNGyvRDPfSVMWcvLaiwyy0h7ZVD8eD3SuylVz3m9Jt0rMK0LMoIXzyWILFw
5YutqgZygqr1SWvEMjFabW/3xTrBPc6YpUzslQcUG2MthYeXKLsdUkpglODUhk0tUZR46ATZTy1P
7YREoLzmEYMBM6saAgFPXl/MNQFhOdAscrdTRZq78WnIdTLpQa3b/ykLvFyYXbfGjTIFnZAc/huO
YEoNV4aJlKkUJb5ZQbzx8Czi30Bg0Qb03A9ULjVZaGaSJ0a2V89itb3jekPziUA3J3Cvbk3dkgZd
9kcXPJfAGlgwFCakh2Vw8tZBKQX2tOEA9oKfBT9BDVr1OtZu1bPhCyaUgOv+qkaVDu8MRv2DYwD+
kL3E2UypkZBI+9pnKMo2Rv+JUxWpR5P4xa3rw/1lQoz3ICxGxSds/Mj/h/iQWQHfW4M+LieVcT4r
mO7YR6HgHnBKaFiQabU8BtRz5vU+ULyYye2ERaHODVnVD5mZwTM1lTRb1c3zH0y0c1IbTZ/vWjYA
pYX9z1opi9ysWyLdE8yHc9nlaUmCLXGro0Bw8ArGK8UER+oy3HIApGJazRQuulx3YQ5Z1ug628Ew
LlPSg0Jr2tWnl70My7TWEP/ENxaFUyzhtY5RIZZ2TFujWc2l+s5U36V0tKSE0lACaOgA7qt4fAg4
3fOVM4ELDKpAJzaK6guDwgbV1BkoK5vIfxUDgC6Reqjbq+RLs7NmbmTVaAeaDbdWVBr/JlebZe/h
yO9Rvk7FB5nubdMyrdOT65aOHkfFoJIOUBIslVjajQZIlVPmmX+8ieXOEhmagXB/lnKlkFA5vmDw
MdcStdHCuBaApdAwWAT4GPcYfNitIE1SKs26ozJjvE382Nj8CIDrCOhcTAYc8sm2YobTdM6lg82o
qOrDLMOafh6DRF8v7AOUBi9odt7LaoHRg/Hfu75f5pF+/OJt1Yg3gXx/UzGc7WcnxlPBndinSUej
ntHsR+Boxr9ffqDf2ISwyf26hRelQEdHbInZFJH3/rBuP74dUn0dJo+SHXzezkIo0tT5E3tU2BzL
Bi10NnMHLFydOmuGE9VgqZs5UO9RmjCaORo9dMwF4YrSXM26e4oRxy07UwDxBhoLpqIUEDzVbfsO
BFoT6aVcbRjVnPYKYf3U64vhLrmQbvfzKvDGCwe6KLkLcdEsnQ+HBHDafW+VQbFqzGiQWzz9B7+B
bZbVZ1fJyzNmO2q5+d5uF6N5GvgSQRXhe2cgVEdXumMQlFNrxlYI7rEc20BYuJcO+6eIo+tDYZe0
6Zsfs54ZuveUm2vvIIIDz29qQ6GUDSCL+icDg+mIK33VOkStjF4TrhUZ6uyj7vnWgaIYDtwKq8z1
TCDL+P0qnlhrnJtsl6NpCY2EkLOkJGExgHsR1U7LO9JJtoOqcWrO2icwVM9SMTmRmVFs8ak49gsc
Zcb0j+KJ+ShwECKZSiGr8v+mx571Ny+gkm2LqJi10UJ5+sV+U+ozZfgCdRtwXEK3kmaOg11PeehG
ZRCSRBSe0nrVsrlUWUATZjxv22RU1+VAfmlcdH+djSGHiqXrYmz7MKBzPAK1kqnVpFdNRHJ1RODF
q5a5IyiBus7zfyEl0NuG73Si/IdPnkcnaXY6nmA5m9+7lqEfUTfttQhQ87tmX7hSEKsKB3VdKqrk
Qj/k6ASxz0fHBuXHTFlP0qMPumeLflYqL5TQQUPdyNt33HAe5tOu4ci5rK4xDZ8dr1bdjAXWsSOD
7k2mQ1yvT0gMcz6K5GX4nH6MAR5jtBo77DefVldknNMmuS5F+roO8iE0GGgmOP+dkP6uAI2dQAkp
rPlb2Rq2Ha8lEQ4EHrX1Sqh6g89idxvgfDMCPsG5L/DuhQZ66HCtVS6DOGI5OtHT6cTE73yQkP2m
Uo0xH2i1oRl5pLWE8ydjtwwuxNnVeXL9nnAuSmiiqOrXzBWO0+b9GCA5tlLe4aAWtmgiRQK5co6R
rNtk70PNm2yDasBNgXWW4cMkDeCjU030ywViNTm3Qak4FXLeeB9WTHOEPCeMjWngVPc3f6qizQiE
lVfLIy+3Zh2+Bf5x1hWHeFlA6Z6va1gISETrfIP6L56xH3lClkejoFcOdZiBBWKhlvmtNmos9872
fo223AWKIqvowEjygRVWahpyCts8yQKUv3K9gHlVG674s+6N9iyN/z32xFTgMfTqePknYxf8bWMk
4Ul0wOcegIp4nKR+7XOhsSlcjOIQ2vPIp9vx2UIVTjRf8QFVSAmg2hrGr/iUVQKDhsi2J5b6Pfnj
4/fxd/f12oMzzFeQAdPiCzXg7F1tmKgyGpYcDm7bIUT4/16k6Au57dSDmUxvFko4LBx+X5+g+3zF
R+IXvn13ZvBMCQsWTdvTQE2XuCwUH4l4F3A1nDTMM5lYDBxaLaLAKa9wCgYz7PvvmW4OEIFGqxAI
JL8Dd9p9SfN89juSwfj2KH876i2y9n3m3eU19QW5pDymPlfQYeAn+2vf/kGU/8DP2D0bNDPbZj4i
q2u1ZyfTIUzvOCl92/1AqcXgGVgnBTgo2bmrHL5nRas/W3gYurvHXyeKDfLPwISUnzqjlZn7rAlM
eb/qXRTGn3lr3s6CwUpR+eGQjhVw2YLYfEn1ePST39JY4z/2IN4vCAyPNpSCee3ZHv/3QaaaSRM6
VFrmxfq0YlfHvxMR9KHpgFLKpk7ObmE0glh0Nnmnw7qU5aAOL9nfjyRKgyoVagS99DxGaKDRyhCY
tTVRIfwlllW5sHVHMbwGrbvX0z2/eAfTHYpcS8rpAs3pWHQjW7qrKPn/l0F1AczSGIqXcIzwGp3E
n2+a7a3CPiz+vifbKZ0g3w/u2+Y4ZBLUoA1+lMG3G0SnNfg3PhdCyMypwfh1F13Z9bve0FrdL+Dy
h6Z28dLpUUr8m1f1VM/DYfreLUp4QMPOl0vaJwZHfdFHp2laDWbQRX6Hkaz8y8Iti6xzNz3tYVwk
IJY2StAYudGo5gqUgrzMHrKQYLzCEFpjzQDo53+7Nwap7njZVWeGEBFSLhCu75N6Hf/FUDk6ugjs
UOJ1zmPJXPFY3Ifn31369VrPsF5Wbl36p3rSbpGxsoko7QIIS9xWpHsyB6eIdnoxdi9U0vMUZqA4
3RZqWYclUKglV5BnB+6DsdZxQTFpMrYU2JTZ0v6Ub6fCuSTYfZZllIhge1IcUNCDxGmJ0YiOkyHw
xKM+tJ5qButPdSBJ8VTGErFSIi+oOTQNerBKyLGm3MGjv4g6x7Ya5uCjjzaw1HJc7b3xtBgoVQzz
ebNEVzusA80kUg2qfK++dYHfsF/RvHsELLJ7kKJYiU7kRvFqEe6g08pcZ1MXVBuxfdrQ6JshvYNP
7bTZAP4CvVZbkJDsW19a4di0LPgSOnj+ZafS00jY1eL3xikxsSsvz4PEgVW/qRwKYkKeHNc7QCPH
Ve3yJYWkFiRnd1HYzz2l33acURuoBLcp3iZg000dSwB3lz5lrjEv3JOoa6If7xvTbsZK7MLR8VeB
z5A6tWC7oVYjfJMVLoGSFhSUcc2lmV3SqEXem0P5zHHMU66DryQeQKKLhS03mEGbkIQaQ5XRqPw6
Rjmdvb172IcAo6ysmeHHFRJQL+vg+HblIuWYnW/p7hr8ViyujXo42UGRcVz8GdL6phZ6Zx5iKVQp
vHTw8oPzVYGS5tb+yKwjPGf44b/SBzOQqou6uAZTdIKXDD3mOTf1X/scZ7NWVda+Kj63dzGRhJ4S
WvRD38y2GZGnn2Y2mV8Nh6LdeqARieGMdnlciIIubO+vdICnS35Gw30MPzg4rqrJbTJrLu4/eBrE
BHSoKvHE4mLy+yeyhblMEF4vF1TGd7agyaheWAF9gzzkdlPj38FnoG0g0uMANN1a+jI9f3xRTe1m
khFlR1ubt/P3kfokiAO8qNvhAwfI5jh6gKf906P0aWKw3V0pH4lUzgflnhX4WiDhZoYFzFgioe4n
QonnYjsxcNmTMxMO/D3LTMXyxpttqAQpgEkJo+GGyyHTUBNikEpGyGAhXZkr/ahReYtA/amBXRJQ
SOjGXH+q/w7PqNlVf5f6xyKq+HwjbPeWfpohP4WHQzFQbDTz5evr8U15TKNfHtAgO2AR4wUJTzk3
fjpRMd1k8Oy+Fi1loEsy/DDZS2aUH+Jmm/fasYiqcxcKGjMj+VQzeM/41cOjgzuKBG/LRp4BBN9x
cwyHLkaqcJ8+wdBBy1hJyu63gIGuRphJz3JrzvU7Ls+aoMXXDhU9Ua4c+q3I4C9oByF/EM2C8IlQ
wFJE9AveDFnJgESZO5+60MD3v+geH3DJr6DiN1t38CwOr+WYoMs/9n9fDp8bHnsdb6tdvSpNzyIM
0cvpIIgKpeguoVbih5IYtjBcumC1g0Gcl0av6mhZOc7v12QWFLzP5wMmRrRv7iNTdmr4LL79NSe5
WfPiUrrJSoMGgkN2qIzK5F2qKjnunlCVwgHVkz2jzrVV+nr/d9AZVlzEHnO9fqbxoDGz6Tf2/yhP
EoNLzaVN6W8TJiet8YIzrr81BIVdkgN5bydq+w/owrWe7S7EksDfpP2vobw8JII9J7ceW0+aM2Xv
ob/7lHYfTbEt1sJ83kG9oMCTBLyJMNn/1AvXBdqPG7IIOvfHzlbhDelmmPMpZJw1cXGqEbDJY48+
NuRU9e01niceAfScsbJpVU5oa5YoyR1i/f2ZEtmaSlVEXuxYWl+Wu6WFZR8LN22NaKkxcaJaNuIk
rTBaVZaA4NUEe8cC2egfz99dhMs8NM+dyaYSDvvTcy40LtiV5q5ZzZjz3M7jrywxk2LRvbcDfQ7z
nw7Bo/Yb4+gyhlGXc1AZUuxENcm5XDv2CIAgw2YWK0iCc8bKMpPerTQ4VDdskSmFamYudcjs5aON
F+4aR1YwM7GRbzxaUkn1gRQsNQiFcG5K57syWetUwo/hdcXhgzwLZq6qO2yQyf/OrQDpIvqRuEQ8
HvuX1glKQEK1l1LnLmza+CgCKmkNTgJaP7b1E+JsB2xgzpKqUHpw4565MFva57mb/EuRnYEXISqO
tA8wn2o9zwBFNLu0KdKblHBsPX8MR4ZFDd09GmRUWUa6apIXAW863ixkyGIYn/ciEN26taCGz1pm
dQTjA+i+J1Hv/7Rv3jf3glpXROiP7AFeo5xeGNYphOUkgPtFfp0dHtTPzu9+d6NJSW25t/iTeHwX
WSly0uttJ5DQcmGZvqf1Rd82gPWGRwljYAyaQTR/UqGnSDjVu16y5/akL//GIxgENhg6Jn2kRpHB
e1B4+xyohvs8JWFIHPrmFf587pxJfUJbYZjH3A1etEbF2SAyZH21D0MALl0NAAix2UGOuLzhtZdq
KKD00Szj8tUri6ZaunQoG97gDW+9rvB/U7ps9oe6Y70xNLNu2eD2Wu6rHQslx0kig9mDz5hNQnMv
nXzxmzcRVbxltnBRYwPojaGEcYCg0E4szD8OmkP87KCwfJfO3cmpGe/XIftnQvT/m9m8d5423+9i
efsR16oMt1+14eZ3V2UjYfz+qMmENMk/MLzCP8OW+oFT3jWZ0yWjjDMMe0h6k/PXGTnQoDoKRvyl
3r4QJUAui36GzagjRpHPtM7kBjp3wQeQ4rvDquDF0YF8pVErvdGnm3JnZ7TF4cmNeiRcmlAhxjbi
xfNzM1hvHne+PMeS+QGcGec0YIgWEhhBoSyG5mzKvrF9ZUX0H86NWvzfUJhmwjOEmtgkLn35ehg7
pZiVrlO08433Xd4p13ZiiaHsC2iRT6EGKCvWDWkx0Ppzt8SIkOauieCcCtLMN3dhKiZPKVYfjLgu
iM1n3JWhIaRk2dB04bj4R7LzPkFcFntK7mgA6ZJGGfwuPR4IBknkr4/j3IK2khIVaU3tLQkbDoEw
BGqY/eQOyRt/cm63JLZxcs76f8Hs6qeoHmHyWZbKqGg3an/qMLXjrGSk7S1+zkANKsfMI5IUEMFt
aEzAszxQu+Wp/9C7lIoQKlOKhJf3zS5EvAOzguDaDJEypZpu1s/VArLVSiA8riHFalVhqnKNSTEc
L6S21EhdE91twRFMegpruCeyK/l8MpuoHM8ihIPZGSQsfEiL3SWfNiubFqQPwAg7og+bcRUKsZc8
QX49DForIRspsMg24qTZmim1nfbtI++DlXy3I1X1NAGdbEcF1SAwHq+qHsylmSpsLIFnihlKDFsm
Vx+2gtRf74vw8n+oDKLgaKOr3daAZm5pZNKtNRCLQnTrlBGlhMCS1c0XIxcYG32+8coksbmkjxtn
8CC/AT/R1e/+WjBb3Z1tyNQ6CIlKewvEsYVTkwMwz7eVQvrYoAqAQyl/8gDKIL/qsAp8OlS5tMj2
76d/A/49naTCccURv+6Ksv/O66CSkkQXFqencipGRFF7eYZgCaCV0Z8vEydsgcr2vOmJf0Lr8wON
1joqRGUWdqRZIJjnPP8BiE8eP95NbEyhLxF01HCk7hpPjxNjU2VJjL5VMwy+iReN+Bh3JX7lQcx+
+sLT3p7tibdNO1GFbUcWV33/Z8+GIeBeEv+wrQAl+5OYP7fmWRbS6xiAiEsVAn4zVt6urlB2vIP8
kbcEyxztv5+cDaBWDs/ip59fhIVaqEPHI7WbwmevWoI4N3Sh9FNUs3LCtHxY/98R3WLhgQQBiVmS
6C72YQ7gUXI/dxmtYqdVA1VVVPFibqQKwp0dzux0x1mL0qzpHxHAt3RqT1/zrRGaI0CYBS5S+gxn
1nz0DPKOO93BUKC8xIUOVVgjpIB73EbufdBK8F6PsFo/euZJydwn5cIu8v3v/bn9Pot/pqsfcA0g
b5H72kTzynMnVK+1xw0n82SJt+S9Rw8UcEzVj9wWFlFiNTs1tpjDtryohF5i/lH0XzvmdJFrtwRf
umB1YJtVz3lFI9UREfU3yt3Ri019m+f6tAA92djo8k8Xtdu+f687qduZUNnzDNaHvk90R6KWICVU
3NK26FQRB8LVPFkxSrWzDUpwNnaDjhfFfBbFhQnO8Ovlmcb8MYzNheMIPi6lMkhFRVKeKyqhtBGN
GnE5z2m6sbt7NelW+2vfrJRspll5KeyKzKafGGcPg5xrmBVgdv08XQWKCvf6zTYzRRCBseHHvMmA
TV7RJYcW3vjW5MIE4GUjj9Ge2zldsJLW5gCD0A4ZkKZN1W9jsi5yPU5OxXbImta5z5AG6IHHwdG8
a7PsMjEZx1LjTfUxzgLgb3DJTE2Sfc/3LPTqgIC6w02G+oYE4C56zS0K7FwUwhvyInYou4gHffd/
1weg0dM4pbEBcJP+hkCl8VnU8894b1YBegxxfRhDE7DNd8Lyj7criEz6AlUlUGf7EiVEFt5bc0SF
km5jHX9nGvXxC0zlCftNaieWMpsmc4WnV2IIAFCCL5NjIFfiRoX/2E7Z5Nzbq1NXcBy7RR0bZ+3W
mPAxFdYgtJ4/I4fspH1a5wsBDLyDwvb3e2jCPl69NgqaJ2+FQ1fDd7Kw0BnRo0tpqWBUq85DwJlU
a571QT8nKLnYoW8DDzsGvgBHkaguwqumwQFyTWXWkow/tnEA4c//3fOc8uSUhk3t+3zixIy8xZPc
g9RWpk6LhVOcnIRV/4d/jigba5nQry3595pRHWt1dVCL9EjQPgjDuqmRD+wNHoHR31qNhVmaK4Kn
j+QIHAl+sAjZISRJBM56G9oxm5Mi3HT7fP4FnJjvUpsfRLIRp7JudvERomzV7Oka9L5E5XgdeoH7
qFE6aGQoyO0GGFHzd0rlIrntxROcY+ICthYvG1hYkfvyjKcpHGhYS5R1GoQ24cHRn/rOonQOsu5q
vtXcDgYQw/DAnSXRzgwDKvhVlFL5Uge9FCEZ8Ur6SJvXcVJb4mvq4yaY+ncZZeiCYIN3RfVZ1/Am
lUlorqM19wGlE0awycv8aV6v+Nqs5hPHw9eBHWQHQa//Flwrmog742Iz6VWtOEhpKjjTOIkour/g
5wj9qbjge7+NESwvwE5rOjs2gDufi4mSna1Ms+gAtkxp6fgtx3uPICfiNQ0cjq2r6sXjS500uA4M
1W/NvavKyZu6YaFgbF4eoOXj5KyEmRo5qRurlOc1H9Y2qr1vVU7gAqZCQleOqfxIXOX4PoHEkjQi
edJn0Dhhy4j/QmiC0Wj1My/duL9S3dNhvAsKv9u5V87b/BkYF5+OVVJKy3RZoUQy+/c1ApVkXz6G
ilpsqnrD5gWA46QfIgH3eUE4MF6NRZ39472rYD3RyhAlVvbpmE50tyW7LmE1wLE/XlSr5xZGVHHR
tJIBR2Wp+tE4DnGeFbf4hCbcqJEqbhKYsNESnhsck3XNQmgJkcpn1Mg5UoAnoQjEXwIeMi2Vf4Oh
lprl/Fe9zhgu0tiaOR+GqDdfk4T6jqNjKjkdU8o3ZFUDV4ybg2FE2rFXoRSclhfhNWlEbDA2MDPO
iDEKUbzo6GLQ5MJZK6azfbb0IHErIg1iuxOVdcApoxwyT2bar7h7WHLlq2qacokDd/cBmpFamo+C
tSgoSciIocsiadycx2mPD3dXr+Dr7PR68JEfdUVyCXO9qWU5dyBcGE/Vd60vZ4bbHWxNUwlhdp0g
Zo2PRu92i+oe/rfc/977uktKuo8duADVmS9J0DpticUt8eZbHt3Q9bMeE/mG0gFIKyIuKzWREt8s
yJBXg54NDXjdpMAKO1ttk7aUqnWFffGArv4fD59qCHrRTHJCYxyPSn1orEgeIq61UkYJaWN4pds2
Afsn7dXo+VOecrKdohDF8vJYGv6S4HlErcdbu1TZP6yOqQ80gWTmSQA9GyVzQqcspxN5H0HxnbHd
jyEQyV35o11iWW+lyQv5SFyXZm3q9jBoTRmK5m4o5f9Vu3cTy+FMv5iG+kLKQkHJgS7w0CRwqU57
N9OfYJc8saH2Hi5GvylZp0K21JEYCzcUrAgQBxV48e+KRsTzqPpGAKW1aNdux0CGffKiNe6G0wdr
KGfMDYlTBCfEOoG2FWcQtsudCSMJG5vQOfhj1JZ0EJ+T2x0OOCJYJBwxyapMbuUuivqGJNwopf4b
Qtj6nOA2R6gE1eeCrZx53SKezF7nboXyfs0PlwFkcwnk7C3w0ZmeT8WcTYFIZJ4/s7nCORGVXwpW
tK2sVtOyBANFrRPq0wH38Qbm+GUtIGqbBYpmvQ0KWkq91BFk6sogjLy8CKUeqIkwx37NdcNSgLVp
avFiesoFTfqKVSObGHJ8dJIq/WX+p357H+eni9SncUZ6BayGwROMlGrlIFYh0Ny6Ubq8Zunu5dFC
ojjdSmb96hinXpaDviZwkq0U/RAxSHiDSKo7lBTiROvrsR0TZPmX4EEmEknvuNbPaE7VW+7K64R2
NU6hhSutDh0v2Fc6xI5B/3ydkNwXjc9gQDRt9ki44m3ySKg/0ywTg9Lj4E9Yt9kW3mclAd2SCx46
v2GvDztycQlW27TJJZDseGUGlfYwFVkil9RDeZjNKJ8Qwtcs0KWgd4St6y9lOpPIroH4gC/vI3gq
/oZOGn2VwNWkWFaoT8ulQ9zZ5pzF5OhFco1aXuAMmzP0ItHxhLr2jKW1XH4YbBI6SNLiiVdpcDZu
PpbPphXhm9Oi1gJPlDEnmAcGWQUmK9KHuD2HftyMokJUrV9cyUD6oI6rLMhPfkiYvbFn+kk2nw5e
MzzkMUy5Ml/wKVo5xSvzk+9OGVDsPt0wq8j2g7PLVLWWGEI6mh6jB+o0+FQw3ePvLPWFUnD/BAET
dJBgDS8qt/yGPoZbC9yYuYz4gEqoWi7V42ZtRXsXggIlrEIZBVtjj2GWrqpqmDlBgH202Nq/fz2P
9UQeGVmw80GSy9k3CFQgsrxU5djcs2sgpFBu06gJtAGvFGdYRRxUs7l2shlg9t3FcYC6wYcz7CS7
mp+wUM8ic0xwYqNLAY8lYllYBE9iHghDAp/tMNFCM3Kq2fyxsJQkJEq7uQZQ5Yj/9O78NtICkHoS
nNznKX9hOP5K9C4q8P8rsgCnHZ/JthcgG1XsOYnc7G3nUaXsUMVnnCcznRtDUnSoxXauUAlPptCv
jG0VqwflTcJ453+/4m4MczMNjGUedtDVXH8ITUjqzb2RO/VruxfHYtFZjdRP6BFC/c2WhVVIo8/7
+8NBr6KWtzhUPISnJXb0DlVM2wzjnsRWWfyTevlui0qecEpEyrBTu8RcCgoCm69Ij8vqHWO7og0S
/l7yG5bGvU2HHXTXV7uqBg8/hIOuihtEBT+WjBrDrd42JmWmNWvRnpOt/wJLSI/OIZc3bt4GGyGC
NnwsqoRCHycn8fiEd0W7wT9QdsKQWahd37KcAlrhZAuTc0q9jhxviHIgWqMyVDBDEeM3iZqPqZQo
VpDliqNgrwpSG8m/Z18k2brtl+qbk1MN/7dbB+WOhSkqIT4a5fPogewhqwF6wGUmlTJdRXbim2rS
mHOhqpOICplaNSx0wLSCZbtVPiCz08NIYFAa2BetFglLM7OovYL4B9hJ0XOBhPpfXAzI7kMz3zyw
t1Pfz6LXWrdDeZrq/zs+hoRmyLIWQiPdNmmNtu++t84IAFILIlo34CPbrcHHHMLTcjGZe8fl+xBb
1aTnr3ZJlhRowN5G7k3tW8rrzKoKH/SjQNNgkzc41OyfoLeskidKcQ6GhYF2EByX6A5ZbyOJgviu
lK3AOlfSGyJQZxhjmRPXJLDLSQKfESuu62BFtklnTeAyYWMzjOx3zrN9Pp11QL6S6sv69lOzggaY
2BRd9dzUj3jJv8l+/qa3Hk9dRmKYDRKCggoqpbj0rOEq6pN2LED1EMSw3KuQIWrUTD9QyZ9Bk3aW
8VoTLwQK17HpvmEFWELTr5R5Dbdp3emI53a3D0DAZfyB5g0TvJBUczZRlqW8HjYKMoXovog6ZUu9
0LmCdUc/sVCBn2fvudtxAEdsdwP8uwx+VkL9y2J93F4aNxa4SD61HF0SmQoCWqIcjGRfkpaveVkf
WkCokVMn4YuMPKNMWzbyT5Ks59hzG2zTfC3uMltgGd/ztOXUTOKx6m6WHTjaK093/BR4fSbeYSXX
npKsEzT84Bd8073hF8dRKixgpBq/4nnYeAF5kCHRulDD8uLSbm5YwKA/Hho0i/OyiEUMWLMgUymb
zPAADiaBg5AlWIbIUiQCyQMQPydVp85fxpJktTeZoNZkaOVB6U7qnidEe5M03W2CsX+uAlCw0V5D
Cj4QKxzkKkOUS6L564ojax108LzkA8kk/ldJVcZQ6pX98pyaYp81jt41Y0RmYwSnT03BO6yQRoem
gnTIvH8W6Oc6zNhpWML6HnUlipPO1G3BavwUx4mZ246s/5GYObyAaCJuqCTk0jeChK+cP41qW0mb
6lyN5M7FgOUZJVwdLS7k9AiPZGnyk9HZbqgJhuWQUVDzhW0pZdjRKd267v0GyJNmpoqe/BYrO8Qm
7+a7Fr3b4kKoBzPU7LTK40+HXPQLzorzYEZCN25eCr+hbldxsbAOf+CArUej9mexx/IYL7oI8uLl
iAoyTzSziCtemBcWmBxJCXA1PIdCVvVS4b5nyyojYj6Y9RHL+EJqU+uhln2e8meGnFLo8PmkItEU
VioNXOI2o68s//Fp63TzgcXiFHIXDAQyBZqoEAIvjgT9sKl8HP8ojfSMPz2te9+hhpAnQ9oaLctb
mXcCZIgwff9w9g2AW3r3b9d4ReP2AESv9sy+/o/5pHEMsF1P8UCxR2y2CVd42Ytr76/AMN4RPhw5
JSx/62ZAo0URqjoxOKEJ+eVYHKQSJ/f8HQ7Dj7k0QlstSTFarzZea95y8/A7YQ8NiUxjlpSf6cQp
yLIGImkfrj2bFTNna8tGhS4b3n+9scKOv5tRMYijxq8cQVoflXmRSu0RZtlFxuR5loajHckIJKG4
HPi7oGha1RjlOOGAFEGVvw8nmqMOlqE46ElR4G1VGrDjd+323JcP6EnWSx6y0tXeiO7gMVi9YFCW
BMv9XvDkwGMqhT3BE1rpuK37ECKJOnnAKkuBFM1p10Z5JFXPt3cJhQpOqeQ+BG3V2jKqWiX1/MdO
EIOl0memcIPWJ5gqcnYf2XmonI9zrcgwzynfjwKoEbi+vMGq6U8DZyDHfhXL02/FuQM1B2sFODQc
rwstT5+eyHt23o7ef/Bfk/g7M9xTLJNFDfO0wLbXXXqDD4kGz1WEUPyEyyoPvDDdeGpuEHkR1p7e
VeB1VuxFisY14ObIPCxTEG5EUW20c3DUaFdI1Tr9CnsO3RElkbY1wHtzh9UhyFF2qSt37EXkcXUD
4w+RtMjNmzRR0q1JwzNwTD3c6ED9FDCOjVl8Nqx3RK+cT4M4HYhgeKJjLk+LFQDFkv6DAQB35pTp
PNpG0p6+Qkj/uq5AhuuLCVW2/kohVs41BE+XNaK+/dAqnG6eE1MTrG016xc/jjJXMw3yfyA86/bP
XkQMY4VuJI4oUwaJvNzSso3llWiBrvhZ8A3+Oop5lg+OnjJ1QBVW8cGHxXMUifcGVRknkt9Zf6Dd
kb1i0SL519svUlwiZmepOgqkknZIYEzjXP6B1rVoWq43vRQlMs43lA2VUrnT9GJQNKPG505327BB
pJ7oFGbvUioOaHkByHhcgFdiAd8hmzplSg6BNlhR1AP7tNyFyJMERfcTyGzS/5E1ULjADJDofgX2
kF4byi9iX8av2EtcmaSCKuI/b9QtbWSLdh0QzZdhNnOR8QuY3y7fqeQHu+3CF1Y1p7iLeewJb15S
iiB+vCr1h2XvPD3Sy7/6nz4PsUFXzAbu/MUvzchmM+Qzud1cGk8CYTetYo0+3J21YAO2mw5vgSqH
Tsyu1wb48Ffbh2BNyNvB5dMOF/PxnuwWrX5K8WqR0T7yJq6fGDJcueg9n7NNZywbb3dmxC3MzGJ6
+Ut8ggfYRfkrH9df4t2YrrSHEXSROzvwXw3Gxl3KcIQV0FK2jU76WzUvgk3vtz3+GqOaTjK6D6lS
SC3G4bA+do/5HQDfK1vgTfVLC5LHiFxaQyBChZPvO2LeTksGmb5X/xr5XlC/QkfZgf0wpE1WdIao
7mivGNj1yVO1r+AH1hjclWGN9kv0gzQOaKSbJAZy83GG57yS3xwPAMw149Tnb11yyUhr+mUC/MeL
9wpksTHTkz+8MeGJDsLNq1o7LiD5KU3aR1NdGvSYLFkF2c0o9m1kPyvXG2Inc+/FquU27d8ydPLp
prA4r9Clnvr5afYFj6MeDmMJiLeUzqy7M6qWN/SGfMrujlRd7BIYJw0C+MxIUdc2jONWL4p2/fdG
dB0s4PmItcbu401DHjMAmXZW6CTk+cz8E5965RXcI41/Ek3ad6W98J26K1QeRakYhGlpQlKCIm0M
e3BfZ0vpCClaOBRuNv+FPxIiWJ+B5dJReMqGTTwj/nGqnu4lXsZeJs9uiWZDOSF2mJgFVxZqfVRh
pHVhGEAtSuAnqcLGdBOLTsDmtbnYnS9lerhFchQMgw+Jm9w5nWSp3tZLjvgC3Lg6y8f3aKCo6k5D
m400yaQgeHgtF/0RHtLREBromd1xbvzlESWi8F0GET+CGr+aGbqBhBkUK4i4+r0JzhD8od6Uq9ar
wLQWDofm8Z0ZC+vGcV8/zIifm/L68E2gpIGs1DCh6lBt4tI0hdN+6TUD++pwV7zoDvBg6yaQCDC7
i0ox6mjPC9VvM91h5u0tBw7soBxUDspboPLP2tfMoAPWT7WoAVlKSUj9bke/h7J+M5dl4+pPs+AJ
QjD5PBE2wlOvdUROGNHDOz6/K7G1wyfWfk5O+TsLWII4P9Eb++zIRfv0+fiEr6lFa0R2CBEmEp8e
QYGegm48jD7mzZ77OJt2sZHvnUGKGTcGBWKkc/1fsImhAv4EU3gR28He/jjT7ARN6CbaJ67zbzTH
cmP0Hv6JAC3wf1EVXh6CJbasoQPkn7iXApyHJMvKaRHB3/B7IzLs2oSnlYlev01mk0FSqkpRZRrB
WEDlA+qLONnrAyoX7bdbk2ZdJyBG49t8Hiio71URA/+MxEOwPjABxXQdTLDkhAEm9ohJw/7QVrkE
jKWQhBRvr996dbwwkP4ym6zy17FAApjXuVLL9/GUIqCA4QtTIg4F/HH3Un0mKFmF0eU2ZMQ/RYBf
rn+pVFceghRSmB8m7Ncp5nbL3CCOmlHKD3gp68nvY0JHzotFZTsERyukVEWbCravUt9bIb3Jt0XW
ul10oojAZk7lO+rQpeo4XfBbDem50C5ke8I5IJN/3AEkYcaqbvayRZzx16WIOR1uNukF8hO+m1AC
jjWOdqyjYD4YGtAo9+BMhgeVkj/TWPLr6uhDYzPVoUWbuRLInml9YOutKmEN40DR9US68HDVyzWY
BMJunPVhbGgeDX3td/53tl7IekPs7bgspZDZF7irJWNWM6EMMeq8TjONohfIIB13RKSQ2bLWQgfU
ypCs26R8Ltg/dpVTgpvW35yIBqQ5+hyXmens1e6+3jBc32lpSxFumOwMjsvWDVAJdOfCL5NUyI52
Y7bJAUhA0tHgfsfqZ3TA+OAK+I6vJBg8smChfVTVv/o08ZMoC0QSPTcJL3bBSJayHNkC2IjSC1Zg
C0Juol1BtPgIuBr7dYTlARhMHva3N/qrtbcGUCg14ZAtoePqBzfT5ssp4tYtTf3VBtVMhpla067J
47h6bKktjlxyOJwIm9JxxtQhax5gQq/loZjmA9gw3/VSan8w5nV/MzmIIzlDYFIj6wE3tcriE1wW
i53QvCx/UW0UCYo/NQXse921fgu0qLeSmz5zIJ1aX5n7JMXGQ+6j1L3yJmc9arIMUS6+6G2Sezps
FAYCY9z1+Omo4tOM81W3VGXoaQK4HyDyl6qcmDcNfEanzxAZd+ejgJNU+cpP1Z6Ob+j3QnOGeuYh
qCL7IWVNbTXlBqKyitjUtUZI12VZK8ZnAS1eB2zi0q8Ig/rSGpj+rTZz3enaiMLAbODBIXp3uUSo
YcY9A3OFLNmkYzQ83hL129gHRMZ7sJHrO6YXscEHVckPw6SudOva8k4wx/hlmlsSECt5HnYqVitK
ED3RbOKwtTolCYHgOKqDSDopOvkjVdLaTl+ckJlU17fcyN7RdZQpMincf5TE1X/aSGQG0EMR6dMG
L0Mo6yudtct2cZ6sshqnlXd96DprgqJj1gB7mCE+wQgrbfncXxlsa5gkmPlFvrp31n76Cc5eLEX1
5u1/LDUxPceSp0uTKrE7AGDxrsLx4x6Wgebmg3Rvwp35Nr+m7r1d+MoW8L85OZpJQsBu97csGsyP
OJd5eknkUbx1w+fW2nl/EyDAlqDSoIOXm5lupjvbncj9UoH+RFlg2WxHnaJY5pa26oMwRwrpNWn1
XqRgZQ2lxrdyhIJhezXOPD1VONs/t/r0hEUjHXxFnKrkiRwDv+ti8v73YiL74joWR/CVQk3Ok3v5
tiFCCZhAFMZjk1cCF3Pp57RmvHUvccr+0142eecEC4pS47vxTlyDw65o7ydjL/utQ4Q1Yej/m17P
qfcp8u4euQCX/atNiCphgAo6143XokkBshS5me/1LohOF9ajo4Lr+lgdgpgULkbEFBG9zJNscZG6
dGjyE4xwaWeJA7GwvwBTpDdkPzth7/gUYc7Cn/sJ6hUAsmMae2a1bwW+8J3vSZHbYdodNAUT/GT+
/bvIAxnGcAIe0NgGMpr9LDhfdYzxkGeNp+ADV8p3TlM28/FEFYY3pipT+VbHJDjA+3ENHSOqXSVs
MDmRLJHYbMeOne8sADvPlQhCIjqh0KtQRBWX7JWt+hSPEc6u5lU09ZUBoNHwlWVvU0HbVkgBEvHk
lyHq6XtHbUhlgBKbcuRFHALoQoi0T4bu73wD9BWoMVzgtJrknmaQirL2D61yLz2ARilpb1UBV4z5
BOs/fg0QvO9aHlpmbRM2baYeEudSFjGSk6ajW2UBYCvZYbwKSuAd+JfWV7/SafV9pOPk6OZW+ph0
tJWzL9u7AoDshUmqONBNn3ECm3Tn59TNB7wPrXi/elyzXDlebqD3SqTMczU7oHo3OyB7KmCoCXEN
g+mx1n0nJiabGz1nORecr8n95xj2zVRSS3e9/R8wQxQRbyQEvGLUC55NZ6CqlpUm8gYmuZ1NfT28
yWZcGW50fIqwP5yX0qDEHjTvLrafuKiD40wBJ/5t9738TT/UukIkT9IOyzTqIyODA8zVFZ1Q/NhI
CqhOn8UBCBI1M3leUAJHNdGthAgeyfXuofhiDelfA55VLEIsQTozfg5X3qUrwAZ6UvnHmNYQgsUa
xkiAWDiD7bVyebCuR5pXdMJPkXIyA8t1x6ulI/Dt0O8gS/kh2gPc+3RGbs/YFRPEfZLEF9ZQP8JW
SKEl7JrTRPtrhVfU8PDhGlMH+wYIeITyFNwUR0vgPdgh0uOkaSMPwdvcy8jrRZ0HHfeiZBvG4/N9
ZsRqJ7tnZlWwrh8hLxqOG03LPyCw+CSrjuOwGRlCHc8RoiS5Ml4REwtZNrseVEWq0cqlTdjOajC5
Ymj3rYpCm8+3ApXfOmFu76D/LZgFlOZFdL4Zdi+rG7LQF1rh4dyYF375BV06hQ69Oczh/IZWeSdm
OdGn8Zw5SXdvjQe18w1ic6bIUBQBp5R8febtU1Ju9j9Om/V8KEps1xRBClcmFzswntfY+dBToJ87
0Nt7aoiQAG/DGBHVsoZ2Ll/mYUqDI1RYC3gPAkIWbH3YV0Fcg8stW+JvvWRtevPfZtshHQ+/I1KX
DexxxEivB/24I4qSwSMgq3jYJeAaHI65ONSEASUjvWoTnoWoa2KneTsUVqM9k3naJw7qLZuJdmqZ
uvLJv+pEFrRIM2sNVgzcXHffzJmEPZsTOT6ktR+Mbq2uy9rGBp4lx5GmKq7flS8JMhgSC1Q6xQ7T
q7np7gwpCVawaswIUJSAtGl1RDL3pm/kIqBwaC7NMPYqUk8Zo+4UBeIcJBt19mJuJioM4xL2u+SF
VYImE3YZhjIGq19OqTZIaTVzBWCc0qdu+IVGSi77b8MTg/nahtEouV/VGzAtnsBBZBcq7roA9xSZ
xyn+dwRDrYcJL2rC3m2+e1Z087egR/aJXny1gpGjRo8m+oRkDYUr81PRtpPe9Q6CEZ6Kq3LyzAJ9
3QKRemEvqNXBRfGFVtZEr5yhpBdRh3lFgnOFbkGyIpRjEMh0p563R/Fa8xEvHNwIa2RNN0daUKPS
8LwpXOe4dBCrEiWp+8VvvJREbQL80M5OEIX7CbzwF7nwVOnXEI92JNkmCQG/FO0oHF9SquKQM/Vj
gJHzwp5sglQ8RwdJ2HcHPQn+BJcxTgDhHh7qmtQiafS5QVoo1hyUXhTAcOikYbOcOTuPLC9MLmlN
ZZMAZ6uVD11WIEuW8xcTmApZ6rn09FSmwRmJSL/5xHXHC2mbnMEMTK29/Q73oeBr37gI6QDS+5k0
Re25U2vpvA8fKmkJCiJazCe+GFxhjmmZAQn0OCr5vRNozDyq7cO0lXh6l2Uljn++JiURX4dixc9D
w8L8fcdmRrjv+R9E/VPYbuZuGfXiA9nhcLfvuBicHsZFtw8tsDH7tUCrFJ3IHRjavGUYT4BwP46/
JkMVMwqOA+bcWOZ4gDDCRYnQu4bTcGTUozmWlf+TsHzjv5TUmpy5mQJ4iH6MaEJFqwXxSzKxxaWh
Qz030CuV0aTDecpg1m1uVv/WaL8fjfIdvHKjqHbMHud3JZAU7ZxqTTuKs9j4x6Z2F3XNkT+G3pZJ
eHvfwnEOJX4xc5X0uZe2bJCFWJanDoODG3vv+B6MAH8JQiBPkW42MSuRBQQG5pyL4oPbH/jAzERw
yZZIOceVHi0/98cWkCuASR96R6VkFJz1944p2ruf0OEUIKZ/R+9S2QTNlVh3+odIili0YqofB39h
azIkl7icqSYFXrm2vqIQzru6fqyWaQ49HvPp/6DiG3i13/HcvxiP0RPr7sRhRaDmOr63ZWLEqk3u
rqJ4B5U/HY4D3wTHt5ODsOjoO+lVYqzMqnh93GE2N+7NC7Wk4M+1x0xXDlwlRNZ89UHmwLlxXHE+
VBRCuUQlilbulG9YWx4FAIbBA6TkpADyCEH83exhdweVe4PqZ7jAWfJ3hjQNM1/V5JF+BEAvUu1U
l2Q/CJwbzzb98/WwyjL2swqdX2ymOBSZAi1VC+OOvr06J3v1sYkA942Z8/s7A0tT6/qZoNoM6SJp
4fPEJCAbD8yfNchN5Zvn/gjJ1E6CSXEzjZzSXpc3MyrvUJTWocrCNTxG9HZ+Paj2U/0D052DdIq9
+j+k0mAechp/tsjGvKqPEJ4F1VHM5ELZjbQicqHXRuxzbt2zGTyZdRgK2Sg638gIqnRqyPFmZeWs
ZxHLOMoqN97jKc5tMtkyBUwsl3cRrXtf5rHGpIKBmrdaxpqCwxQlKkAmW076nMeP0QgKCI7KJ9a0
CcKAHsfegd83IMDrED9ulGGueV4H4cvjj3yIaqcltRLIZKVd/RSGiBBLAlxRXIObrA4deDTYStix
IjAoULVQkTiH6CuSBC+f/35MdEJ17pLFGRXhDE9OjcgyDDjnDMgXRJI8KOKdQ0d1SlxCIowzDpi6
/ljM7wpyC7zZFPxYqgD/XhUuMpnDIQ4LQ9wnsxQnmNnfl2kTBcRUvo2w2IdjgPKM9fJJYKHsqi0s
tWjvK8tPovI8S/ego5sj8dE/WSboOLERG0KV/igD8Yf41wBkNQkem9lQDKAyFl+W8HyIOIKl1PC6
Oh26qTS9GdCrwimML8v7EBajhmRneLamRgI4L3WSJNUxL5v2nUD7pf+A6nb0dvS2lSsP9qs7Abk8
BSAkGr0hYe+0m37v0Ev8bRTA5sTGcB3rO9mALWLUGn6AUYofiD8gYLgKFtrXKrDpJILobIXod4oU
T9QtqxIB3NgBFx0DRpEchJNgMuv7riWBYMWIGlHd1T+nYL6mArxZQ7TS9K7NpVmtQ+ZtqFp/r23v
poJObLnOUZhUWQxDovSrc2aN+m/C0WPPSZuje9onOss2xuTIn7BzppCa/Br+g9/s8kbAWdBttBIU
Oo9Sf9KVAzLbBpnmBwcEzwQCk6aSz+CA0jx2dsFOB0DyH/M/ucuz6Y5otxAsCmNRIvU8DMN7wPjx
8bRSeGoZ7GocGJs2iZ9Tgt6rePgNrYYr8TGgHpOXgdcvqlPnug+VhtrqEC30VPPOSkJhC5ZkJq9Y
P7rzapBvUUDQ0Me7hZRuYY4tmUWG1uuVMCpRk0oNdzCNbUsapn7GVL0CSv4F89wmo4DvujeBSaaI
lpEQToojQjRwFVONfpXtG4G5iGAMH1mdlKnpUXaquulLYOTdpgLNb7j7mWaVrZaG5Elkn9zBHfgh
3EMctBrOaGrqq/P85LZfORE5kOFBuLSeXjM/qAAMmTVl2poTP9EzAe0mGBVhvNGM7w55DdSvewVt
COzJ/VaNz2mUK++mmjED47etGF3gsfURtI1m8Mj/DDK0X7i0Nj6VeXld93hwJ8GX/HybopgyE94k
v0IuGDCK4GFxTQ93MbmxLou0853EdA9ylSi74eUMPf5xPH0GBNz5nCYGW34jKzI6RR1Ps/YsOOc9
lK3c5tvrDB4dvwsIRsW4ngZwsqP7ON9MxOdjcQNZ1DQwGKg6yN0wlD/Rsz7Z7Zzd7sgHBHCa3zdV
9AHRDI/Em4GIBcsqdf9wy3qe4WJaror4zqJ8CRm828pak4TDlttprIhM3uMrwsWmLAupg98arA49
LKaGjJS01ukirTKz1Xpxu2PD0+Bcem/JkstriI04HQAA1D7LRRJBKmRtH+MJQASCgKX2cMk86X6S
2KJxjs5aaddboWhBHG4YNqpM9uzhcjE0Ol8MnFk/Rd0nCjvAMJEao+XJYWtQdWuZX1I8bHXH7QpJ
pi7b1J4QP31eDQQzP5R3q3h6z9p5ynWjLrpM45MJAXIVe6VWH9CrpsQyI42p1QTiSL6pXgG7YXsh
1wbcCjzkD6x9rzzZsiT1BYv9hAftoxgaeHYmBzmAeoXVW4ctBT62o92/Ph+/sXJn9cJnbSOWzh8F
1B9GyLwgUXsASu2XtOtPHvYCoXalnOd1kpI9w3nZe7rXI7JwavPrpEigPwU3iR3ij92cPzAWT2YI
zjb/WNQ+zZLKhUQz2OJl4X37ui2K4tobUN5RUKFfAxk0FjKXTysH2x3mbnbr/z8EIdPMP3L7lAQI
sDrgteAkmN5UPFZxjBW3pLF/FdRotS9fa7bRcUcdMmlDfxvLMyEoh65nzegL45RqfWLZeUTSJLoY
0XTIX+e3ozb9rBHUnnzfgpZJXOhUM6/WsbR1AvqwgAj1e72mxELfqzG1PV8o2fyszHtLAMyPKU3V
M1NAn20AJAGYfw8PP9mvQobN8IwaWunA1dLsA8iSKaopJT0fImGg4WjQrCsE6ZYys00w4gvwUcjQ
Ra3POUeQntruTc+L3axvDvqLf2IJAB5PT1Ce+lt5/+vOpMjsqWlVHPhLB9BeUukxRI2uCJTs3Wut
d+GlKyfuOKmyWu0UtFXvejuBwUZhgONeLmtX9clalQwSL0PaXrXkVnD5omJXYvyE3EyWxx2hq+aU
WBy/RF/Uy63ZKky8MUcVCBEdiHXkN4cmZxxgVTha/W2z4XABvXsUTlTEqjW6X8ccbhEHTVKBDAeI
/1U1K5nj4aaurQ+JzErMvo7qEnytfmlM7uqtza0hA2S7J9+nKy1cccX2b9j97X6DEl279orxA6v4
zwigHyjLORevwuQu8qm9/9gkXZRWJkTEzBuGzOLsy6dklkzLfiIEioyv/DOJAHYjlhI+XHVPE6k5
ftIPbV0hi+I/htJLc2LHSaQQYwkD5Q07mXqIZ+Ny6QcHOjw4L7WHtpAVsVT+/r4ZbjhLfU3OLcDU
Knty20wVG6w93LXtxWvY3ouBE89DqcGtQstNQd3XdRa+mejVfgNdXbkIeZidFr6fxwTsnj+2No4k
R5cng8c5Y0fYpf3t5VG4u/nK2CB/pq60XHBN9rupxG78RG508KApnu+qgdSDGus2L+zBsNIPI4Gs
6VgSu3fUZtAJwu1z37A5Y1ED8ypI248pL3iwzPfra+YGFfpfQNI3jZNjX1HbPl5iVg6XcMnD7KTd
+BWgb0z9+MCyLtsySnixeS2syUAEx2M7pIRBIi1bO/ySwnbLRbmUosvGqxzJqDmL+jeZSNibUnPq
WDnjMy4zfO/mzLqI5b6fYFdP06DMvDHeT4llBtGU99t38MfwIb/Quz7pU3XO8iICxcIna2JJcICU
kNPPY0Zn+WMzs+a9djTNqYM/p+TYvNyOHgOaU1qULmCPDwLJt0wvzQKaunXKdeZmDnCJ7WItNNE4
4pJfYaixhdK35uJcS58FWhCK4nVm1vwBW1ZPtYGokH8UOZ14rF5gub+g041rx4+5zyRgZlbq7UgE
xc6at+HJr7A8WqQmqFfx0418Z2wxL2iDsqdaWUOv4VWwkccQ7CvTMo8gFPmwFhUk2LVg70xIexDJ
OekzpClYfadjgWd/SQZUmkX5nZ4VwG+Puk3Mtd+1s1Ui0kVcMyFYGgoD2UnX9eMCGhJwzdBh4zuf
tUdcbteobDMSJeFXQSa21aIyxQ6R/Yl71S4S+uZDC72hAhf8gnkMjebPXzQ/SjqqkFjkWxgkVpZ8
EHPLrV7kd4AY+zUEd7T3JXp3aR8ihGih+JS6j6nVV+2rfYN+Hl94jEkDSyztV11XXHdJUfdoolY8
YmjUfdIYQlAN2DqIvLcs5M9vL1tbTSkykpDTX+76BIPY2b83OSekZpJp2LmEBKW321qNXhX1b460
jTGT/8WScLVVNfXaI322KgnSXDvWkiqgKpbC193mrAP3LHYW7QE0BxDOC+nvPhmUxqdo+89wJmgx
exTaESj2QdVSEjqYIw6S0gT9g2M7Pmm8m0Aq553Wt0shXHsndcDJbUenX1EJ75eplNg+9RMdhsiT
CjdggAjXyCjvPJ2torHM4HcjhhlEUEgfK8mD+y1H21/R6Dx34E0VaEExy1UFtdENtdNhk38vd+rq
sni13NAuxvrkhzwtJhIoOwKsnOk/jN2iLSgnEYwMvo2s9zeC0yGjqRtsNtIW3gAv+75hEN72woen
UkpSyuYY82ImpreGOYcoK9bFvqKPsaIR5H7dE7IdQbpocuQwogw/Gz4GaRTvdGaF6VqEpDyL0q9B
sCGr6TIHeXVxbLw2EmFHsHmagp6KK9F9ETW95kJrZU07jvKrkcp+RnU8h9btFGZF58yyyKb0U/V9
c0ugiNlK/bEmCirdwVEABgsMxAn2AM+0L+3fYgZwMUjXkp5rcgVaq1EelDJUx/Ftnr6ZBfiK3Zis
jQCtiNpZExz5Bu/UpmECkk/QRU5+Qk98tpNxPlvZ798TrxBJKse5evnbuVvh+1yXeU2VxcUtRowe
y5uQ+wVCRnLtxokBx1OMKNnUnm2dFgwc3qLFU4L13vPucAXFI/JC9LIlqDDJgicR9pE7Sx+xyJvw
X/Itj7TAI/l4jWHQ76FMmI2Jglc3UW/6eTSgXnRkURH41AdlesRkprYGZ051RXlcei6M5CGevMiS
ZWi6/pP4qYDVoo32mV+ACvFlpvQpqn5VOHALFUCFW0jSvtnUw/Nb4FQX/gJ/iixZBeVcCWkMaGl7
CQCzLx4GJ3ZRzJYOaRmZoqKmzt+0iGTxWFaEc+XONyu381hnYBsDYZNPkuMBlC84McdAz7OdXp8T
I74//VlPbtn92PTPwD2biE5A2sqDMrQO4DR8eqzxVFiTRFVaK2UtIcS4Xjj8kPsU2GBNWJtsqUVW
QfVyOwRQ8q2mPclU8PNsjEnsRh3FZlY4rIUexvQ/U2ApKUN2pwOm3ujYZCuweg17N/7lS7x8Cbps
a6wZ03lkfV9vGyZrL/zKSf6wfAsDvFwOp3iqYLExiFzwLyxIq3qrhGFvS6jdrmiPscxj6vr4/mjH
WVRwDvCd3NwRPE27y2Kc0XwYm5ZaFv0H/hcsSLBPR2jHK44+wdcBX/aC8uLNAWo0ER+uCCufz8YU
CuTNAxuhS9PoJDwgRI4FQIZvQwKPpd0TX0jhXObAIM1I3KJdcvfuJNbl4Mva6kjc1b60PyGElfLK
00kJV7TeDFLlgtpMYhF0goLPj4WJqQ+exJerHy3rYUU5u9+4IJoxqnH+uaXG1aptOQmOBnhDWThF
GNbI9HCI4j02v54MseSx2BiPYnRJusVbkgHhVFLExxyfxkoixwxAbykDUm/sGgsaVzSvSIr3fpeb
LRyQBb17T7MbLNE5M6VJX9cg0jTa9gbcM3D/zyr5ylarL1z4TwdusqENGhIgHPMz0ltEnVYf5Kie
3uQjlX/yaRZgYXGbep0wVnFG21ren11khc+gVNeuNhwL1/J0FpZqGb2cE3lkk1C/hOnrzdGzQIUp
xUTvcNWPWkULyaadMwRX7gEh97uEg1XKdJRUc1YJtueDouWDMNpaFLxcnP688drrPbSNhmlzzLfK
06J42jNuXFmpCrg7QMnoq6lB4rNJIanzKCae/zBAARt9w7B3dQHSa5Q1Xofj7JAx39VOE9ZxGxd0
tVdbAQa3Ic5u26JqW6b8AHjoNcKuPdKi91wEuTzJysgen/6u/KO4MnlHdM/XaDPiNDmBZ62aWtyy
Ci4NJ6HT56lEOhPui1yuQgd9c8N2ccKaMMYzSYEBmSEEItXbUhxCYY4x2azrQ2o1ECFsYqzLndqM
R13huYfHUV85Ov+VlWPWODUYVmcgPi/TJxly0UZkbI2dCPwQHxOgkSPZAEvZaepDT4Rm7Wsh9TJc
nO8Hnh0YSnZX7fu8NZ5wRl1Jj2A7hwsZIKIRwT7UrKTmj7eaZ42AvdUnfKns5SOa2Vef05sPhSnd
s3Ws0v91QkVrWv4fH2tJSamihm4cyqanKnNQSign/9D96yFeWzhXkW7YwlhU5KBgOyzu7zkiEsbc
9M7elOtyiUHDDSmpueiITEr9Ok79qBAMaV9IfXFrf6u7yM8l8h4IYnrplEH21+Kl2A/qMnsiT4Qk
VBDp9mcGKyYZeozTqNz6d1FQI4sFPrf5dhrhMl7j0RcyXcELA9k0mPkkpNic19ReY6lyPfs+rQaD
YfVfND5xVmbcRomZIoydIqlzsIS7KjzC5azBLYwbg/JNyt1WkjdNqfj35AjVjUFVj1NBfnH4ZTpQ
VWrbcqfgGvPbA2/UsSJyVWXcqBfL7rWzZQV6mlHmH2MhsotlgbRnBtZ+5VWdXj6V5Gjdm7ESXJ39
57se9OeTFtmq8ZMnfVxGV9PYlH8ksfU/FxXQmk96lRLp8TjKl/4mlYskLKFVr2uod3NRamqMlspP
Qu5lTS/HbnaOY2rwYyQKAstOzsIDr/X6W766wQfS0bwl5gKOzUJYrwLYV4goqA04MY2BsBY/4mtA
+peDfIvoLxZTnfQI03Qscw7FCduFHq/P524XnRScmalvKo5bQvCEpQmFoCVIZOKMGeuTX+qM35mh
DqDnFPLHH18FrN2VIzEF1wNudzz9gVldkEOvXSBbv0qv3b+fb2lr31gAapyM1e/x2NIAVDtuPr5i
DKAHX3iDj16He0b3ntYs3m1/i9mDrnlk2g1gg/6OWQDewZqeIKflYPi0KgkJsnMiec3tiliSDnO1
j20FkjcESfsIRm+hnpO3XdHeU93GucWS8GsKBdNYMZUWt8bK344yRpAcYtyuDzJdU9XP5AIR4Vcl
yjHuKiNSAAvEWSDRiiUcY+/t9hnGDG2RWchl4xVdixJPHl20wpndvbz6vg1j/5MzeWue54VrQ93L
WYZ9RJAt6EWMpvhpxw1qAZIosn0SiXGBkNfWEy43XlzxuK4XFCKs9HsQSJm9eBlQ2FCVJ4pnjP+8
lXrcMRZ2KGzh/bmZdiXg9xH6Nu0VIGuBBTmAm04wznDmmAWuUZIOrRlWbGdcPmzn8lYnUVAijYL4
MUAOTeRz9fGZAFAA0Bbz4GkgnFfVe/MiB2vhYFkg4vu/QsZfCBKpVpFYf/wRP1K6m7C8aJMfZu60
p12oU6h6t405NffcUozHTtRGPtUw/TRgu92B3yMF4AletASINbF6W5UDKO0GXtbIa1ZSmAm6d12E
S6lEO3FjV5osFA37LpVV/u0ds3euLr6inVYfih5L6zLSFp1GqoYZsvCxX6R0WG52RdEVLeuL4M+0
3akeC6PQQmWc8yDux2knI3uup3UTEqgWuz2aDcoeg5Q+tcW2YT5e57SKbOFNYP2HGF3XBqx9ZrQn
mmDZZ58Sa53BLdKvPfbBkrBKgGK0YjZBI8aVTtE+2vTNRzNg+HCYN9S6+4ztcb/h20ojRdJkHXya
WeBDr3xKxWp0cIsj95LviDLpLeVxgkusEdKTkuwJtx8sNZr3KgqFZ2wPBNdEqBniIx33Kuskavx+
Zp2KEOTJhldfANlpMLKVmtxJPjAyDa0wSLSt06qJS2/h5ZtY7vuGDpxV/j7xQ+gWJjk65UZRlQ9M
w7maw7o4+YBFyiFOebvOn8dFgq30xFbq8kvbxQBAkZnHqJHCJFZL5k3ITa9PQt4u9D8U8hCUDzJj
YyggJ62AU4tnTK2NIdoIMF6V738a8G8MSc4hLlaaSi8lHXgNCrlynhZFVaLL/j8a12fvLTxFY8p/
NxUOFicjaT3VycxdLOwz5tMlJG/fOBqvcQ/zjOqJthcOTeRrU4/CD0OQfI6hG/Zh8M0ZknJwSTza
yqHPKhfDk0zcOSdAC+TXivWIu2O8nhbefZySwVEpUagvHv2hK/cPQ0ti5glUrlD3mNQ4a8kobkUt
fCAm5mTif/9eYTPk3Kx/scx6Fviz2FF3DPhhcdl5vptqVdnyL/1dgI3LNQmE25a51c+mNg4VZxKj
x66zIOWlIwh9FTRxG/NAbESbBq4vIahdkNcGZlxPIOY+1c2CIND639azu97JJutyPyLnbSggB8Sa
Ix4xKzItcVn3GS/e7fiLutmA9ExggqZbFUIMyASy2cfJ/Fi2vY1FNaMCvF8s5afBoTzd0/Tdymzo
JtJDyElFOkjaRo+npGoRzy2XPOm6a08V/9o638v9shVpM38oedq1+Ff15mfZ2ekzRiJFXJlfk8XO
MPv3W9l6BzvX4ixuwzRNnUtCHrJV4X5pz4V2+Jb8lCNH/2+Q6FItUHDx+/zLFE+tFRTsP/7+wqUM
DZCA2lVrXmstA01Y9NeUme3TmgoVGassuliVi7Mkl5AJjoeAyLWACwuWDHjkehUex2ChcaWKM5gS
rtW0wF0lHT1h//1hqz3+zBOqcFErzSoA15VMQcaRCptjKAyeGleP3YgbJLmfbHQ79IpQKOER0TQB
Pu68znJF8zSXUKy7U2yLtVVZOju2dMsI8zvnNwoztE12e56E8S+ksKW2f+7/FKEnbZ7DRklibrYP
yPjuXruEoZ8mu+O7P92M+Mj7qh5ZJ3YjtcnwpqvDZ+lfVVfyJUJq0tDXZ/y/RDHFbbXatKMSMy84
22d+684MYMrSFTJl9qXnqw57c1nHJYqF6SYOrSy9wrrIaeCSfoL+EVh5EPg+/FLqdME6xl/uJSZA
rp1vQikH3pZcnhRQL4JqjlmMIF1lzD/hfUS88L3vMY68wLJZW/2QVnKRmqc1SiCT+mfsaZ+STBFa
ZPVFGHf/HL40O+hGorLFHlxNd5s76eUUxoOpJyS4yfAc98kpdfFbOOadt6Z2UWFvAFaOU5qoBOnl
rx+BnUUZefyZuzHZpUgqtHsxu78x1PLMQKKp9cbX8qcz/CPir1YFlbfj/1xh0M3Ykn1Kd6+xHViX
DwyJGiycMDTUS/ApTtcFtShf8INYLFotvV9omjpKhWbSpmX3MgkjiR406IsZORVEEj5ed0siY4UL
/2Pg+QrS55nVsz99iM9TyKX8K8EKlRCW7W3Bj5LQv8xd2kATkhLL50fMxFYxuDnbXQvunRiqelAY
4g43tTRxcHih90OwAXugl2PC/ANXPWP66iM/DBaX2MGBkt/v1g5bCSfC0yRpnNdSMLHWQsyPq7Lf
HucU3v5RnY0hinmEev9zxfDkJ1rB6y3uSTVAFYHmCb7QtRjE4AUZ9xDWL+du/9ovXafgQXE1dLgc
G3BXdr4PeRt75HH6xRLupcXX4+31uCF+Gjn8qr87G3x5Zp23qtaGEK3+id5RvQ1vQGZNUleeV7bU
Jpq0Ty1CcNjMvRiM9jDJ7xaQwXlg0cmlqZl//S4n4HAhNicF9herC6ZlwGuLCtnLe7p9BznqYPvJ
ZLHwyY/vRUvVGN7GzHrkt7StS2u+ypP7bOT1jy6sqvcUMjQiWb4LAVMnmDQ/TrDinPfRBoEMrw/v
cmkOUf7PyGbNNA7rEhMEMuog8YGmc7NvuWbEFTbBkHEAP7KZiW1s76th69pkZe9MUoHI6rq4sC1L
bdpkFaFiACAMuPby0xEkhhzijsJ3JctlsOeAr19rg6p6uviJPr7PhCicd3f2sbSbthRQ25FkIU4r
W+4PbiNDm1Ke+QYL0iGrXb5b8vmn3sGC5FlWTFo4qkAE//adxfWdDx1tIXwE5el+rWqSQU/uLaaU
0CENgt8mFSSbpla98P87Nha+8jQX4p2SdvqZNs3rB9GOoEoBAdt5W+Iy+uCHKtctHuExbGGVWr0A
sjRvJJ8I1mcpDgontF1cWcRPXmIZ6xBMm9VeezRHCA1aeG/UFSi0qtzGt4O4QnB4lqVfzF2Y4GWW
HZ0fVkHxYU2YhRS+w5yKwbxsnotoo9woeBXHHjJr4B1PeCCPez4KiaLqekhbfFSB/HCWmqGVw//L
sOnT6pokKJHiVom0WiWc2opucWd9JUA9qzDqhUUiyFCwLRgcMeVBwjzG/1xBuO7rD+yAU5B1u0v3
K/5cVDaJliq0qrx9wkfHeUgesaS24TFqyBi44HSthJrYHTxsOLNgVLnQqw6l2IlmcURD0qYHQyQw
eB8vXydWCRHoJcrYCZWLrJ35snxsXb8cr4Vp7Qfqnud7mlsf6beEpZ6MRz3vlLtLhEUKcCcFh5dr
R/0LxcNWPjKShOlq4HoEz5bPWu9enjE9XQPKy0T+BKXmuhxwCyYSXbDuCxNezlPv1O+3kpMHhkYB
tRzdgGefbmLnmi3/AOqbPYbOQl4CPwS3ZAFydxdPKDa3c2xjNRyz+S+ltdVkN/zvOWF823scbBQp
4C5b4mBKP0jpyk9fCeekkqbsQTfGsGid6otDHJfGyubtELiOp30i19G9RVF78UfI7+uJh9Xx+XOU
PD5c6wl+jYoLQ/zFGKp5IPU1kOy9ebmBKOtHrQDNAQbiNNOo+GUpY6FFImO4LrZ3vSdUJ7oJT4JT
qku33bJMRdGv0a63byr2WyBHjGgXYk0BfXS1DtGKf6ZtSIx1Yccit+SM+xMSQ4n2gofwX6qex7eb
LScUlFcINDrVoLwp1htGN4rdbR15i3HHapaVe8zFL+qTWiE+bHILsgdKxz8vNxKHnJGD/CpLhdIO
I7o1apSjyZoG2zCRm1IZ1xXq4reQtZXBcVI9FmxRmalS36bChfNvH9jDMUsQYkhU+bXgOXzvBinG
x0pEw5wwT86XESkh6b/iwScWpUIrVpMnSdIi4d4OOC6eyV92IUrCnuFAsmuSlj0koRdWLqTAc7RG
RTo0U/ZCsLErYurYSK3B0u8IKwYoeYYzIh7d53t17cpKle5ArFHRmTOH2kMCGfEkXgHxmyxBzvSW
d4JrLh3YNEs+/3dJ9+VSDSJhBOapD83AxYwzs1ud7r8E1KrXZ9hPYn3pMFAjJ8/XA2wZ6peJnUuo
teaXKLUiigC8XKNhsdFiZyfZ91jT0i5jotna6sfdSrgqY7xP6rBQ03fOKVfEfk20b4kw7m7hPZvS
libt/fHjtKluF0Sv5PJJ6EZA+J1JvRiBK7nuBXwzl0hSIl06ADJOWjBFOhCrVVbxZmVWSpNGYLVH
8keqiosvQbg7shYK9HoUCW+6lqFUwF1KCdqnTYIlW11ACooJCwu9Apq6GimtM4cXUgbth/WMR8qk
rFxVqu/Q+Y1PCk+WXFNB8lZfn+sIyWqhJE+sP23B8tTklA2isWWbHxhJYVRZgTYEhBE5pVAIMlAq
bDAaHxP0TEb35kT47s1oYfZTMzk9Txq39DkvCwB3j4gj87mUGJQMN+OpbdsyB1cuHWMRYawW98tb
78Sm/n5OhlyBjUx01nWRE1nXZttp7Jl/tAcCB+JhG/O9E3BiXa3P9+QN1iATgBC+B4sVG/M+4TBi
mki5LiwqLp4ci2dR0i3XivTpYOj7DCla0OqxItZqWdJ0e/hPPcfm8aO3jgN7iBThuubTGnJpi9J1
CCIyXaNd7ayBITGV+85E8dF/xhUzwX75KNLpi9z2thYzTb/T68B8L9H1tDYU1AXbWs2RzDM8l9Jx
VAMetoZYb4SOGhuGS/+5b7aOVzlae6gxnNIv5tet6U6hUGJ+ieyO4rDcTMvnfdJ+ZfUR3uIbbO0Q
CNIMWbA6WXfdc5w3yMt70RNqT+Ga8nrLNhaRW/KgdEDMw25esEl0Bna/NSa4oIywNVyC7PTt3mOC
KXkGxNDvTy7ILbTULzO6Ckd65j+onirO+/YJ7//3zZOK7So/Lx2dc59sPwvtslKXVQ5H5XZqBvSM
QuijqXqv1gZ4uODsqc0ZZTeNuv/n5Mu0mMfrOrH0zVWGR1NhptPHX0Zr3EUJTt2n6UTzugoFTBNj
UEHDWsjLw3gdPjTEMNNQgBpLmoKJeQChkSI7bcXqTSrJQDF88z4mkmiEv/djRIRXdlAz4fINzjU5
UvLBTmFHXbyFMQx24OSTiUPx1T8I0q7HL50jKtOLc4jUDbg+GQMr/hJCp15HN9NluVN7y6CnLEEB
hGlydDSVY1vhHBQfLndRx+27nxfiozs2rGdXu87YDyBEMWY+GpyU0VG+9+g9/o3VYmuIZdXTPvPv
K6BxPfMoM4irBMNLWcLdtZNB9+a7s9RdcTXvhkbEFcCL58qnBLlUyi3/VMROLRQ4PLgEE0iRMC/v
WYNBgrgfHJM3S38IMmpXEallPhGLiPev+1rbx6dc9tNFTvt3mLLGZiH5J6TrbVu+gC0BVs+sl1Iq
wo6+2ZDSCoJeR6SpbJsWDhqCb7aaLllA/UEXgJNjTHdpMdYVS/lSB5W6MQX2GNDpY94adS6ZRDrV
5BB0v2hq3tuzPVO0U+hx9qp9tq8kUw7g4ZK9mMM6FHMrdGnBBbyOG2m5tl67dwQB3QWE2AvRZEnp
XlrzYDnhrKfV5gCHU8sVvA2cSBctaLwfQq5mTpT3+0s7r1HXJqANQS1TAiDlf4psbfABpmxfMUHe
gqHnsbNshyEOY6J6lZGVQr5d0nO8FA8Xu9VwuUHduEcDCPNkv3hDCP2lLGZBpj1dJ9TibSt4mF2l
B1VlxoqvlJ1TRcv5ZHjDf5Wvrc5awx91tylOcvVit5xELf+lO+ncBmYGg16+z7HOIw1918arONhC
4iIR/1GiKF4YnADDvecSv9hWBGY2uBqtSC+I0U0zA/dMpZj4qlzcsqrN7Y9UK6PYen9LHQsChomL
vbKhkSgyQmH+VpPtPaH7HEvHYEpRkR+UsA50O9VYJ0gF0wCyVRES1G7onVhsolPVa9guB8c7hTQz
/BOL36VTbn7Y/yeCb1Sk1UfmKj6m4DFq/kgokWFsDSHSOE9G7kGNVOyP9c5YMK/6ht0R6s6X9bHh
8Mk0HWvm+sS7qOquUQ3rdmlCURAZH2udO2u/bre1GpQ0pUqMpxpEWdOo+eNnABOeodVttiGmd4nx
mAUCX9nknLMUswvGNmvXNhTy6VpqpGi5zJLxfSk53hHqoSgtuFz0rBd+5D+g4RMeReWp17UgFKV5
q+YydYvgl4evVNgnefJaQFk5Ca6ZtIIlH6W9b+q66zLgVTZIxomWl+hvrHrlmVcUgILGVx2MLxTw
FwCsheI6OxNjCXGjfv0qExirR8nvysZfPxr8jFtA1GEvK+WPwB8nWNYK/OJAjJDt2bSGsUgpwsfa
ta17L5hbHNJjOj3cl3lt3TRv8XtvXmIC+zGXbDmqvKFQ1Gn8Eo38FuX2pbEoJ1lBzzodX5uk90Mg
f4Clk0Ye5UXRqJ0quqeuTx4t6usHck96PQoCYB3WeHo3hiiQON0gNMC/vYWv85OHPCihsqcpbHwN
yy6A1WwAFWjGvKt50iwmvc40ZdrNJoxXwymdraF6TAWJ02zGvC8qjHvQFvpyHRCjctf31efoD81n
J2kGpGUBCrm0WiM+kkqgopAow9CVaxNA3FA1wo9TA4Tl3C4X0J3IPn1I/VYpVWWuQ4gV5Y+ZM9e4
vyhESZLDRq8lC8pSTMrup3vtI0O3VLWWhocW9bCrcqOXi8X7iYEd7G2QGTmmur83O141B6UMFq79
A2daY08sWf2SOZBzNThw9Vc3anYHTQdDDvOKiGX9Q/aPeGmJK1QAzIvwW5A5Gtsusf77l6D1rPVd
4pWatcpi9vY8CBvZChH04vUpv+yF1Gfp/3nOjUWJ8nW7fU/g0AcXvIagbxP5VDOq6KHouv/oEG63
9yW+jbIdIo/ioJ2u0H5lh7P46KyQWSNDCyh6gVQM8j3uM74cowa1RD455eFOUqVWBgjsaoYGsAap
qCjMceFsns8mQoure6WiXEBs2Efndu4fCVXoDcVXf/UJTNyoiA4RQtrD4WEal+7Fd7PHCxUPWOUM
sLDGvAtWObE5kCgwJWLi3zSXazaN0vUApKLuQ09iVNj/mU9i7oWfPItHCxRu5FvvJI4immTklvHR
FTtIwgJ2xy8BGVYRrGWar1r02jBOOhZO71XsFku2hgN7zG5WeqV2uP55WNNZGeBok5tcJMYW3VHE
Ky0GMVzKN3cDJKuQDsGKN36vQqsHT6y7RoMQXM4ORfRj3Hph641+Rc9NZV4CebppEcCYSY+Lv8nU
K8wJBjrYw51ll9DPSmxyeTsQ2Yg4il7bN24rWcIWIa25w1O+2dglheQfZPz2TIB0jsmoSvx9mnZe
BaIRbE43SPQnPbKUTPwfjQAHmN8xiyIfk8Ym7LQfNRJoIr4egWvs5vUXdndw1T0FiP2T83L/a/V6
ldRXtqj9KLyF243ITZ35z5uwIVzEhQ58ijA2eNAG53R9mO2N5SyUPGsBjwiUx2zS1BmAYqh7rQtR
zNGDnc7r2SQGbSNjkZOYwX8QOGcP2CzLZ+qivyUY9aDKv5cyZOPuzzQyeUPjfL3ViSM7fUPbxJWi
S+468IMGImFSzfq7y0KT0IfZh3Xq6LCcswYryHOENSx5JewBBCFyEqSXjZ4ecEQDcz6ck4Bov6uS
apjSSoXVZRX5C+fdYrC7M0/BAjMHIx1mu5SI6/UelIZwNfzZYnFak/h0G3egT7WzMzJo4T8+m7Qh
PC2gMH2hgRkH6q8P/NCrsbNeCVOemBb6e+PahWljMurcVX5BAyQokgvW9q3NKEN5PCCoOGye7/tV
ytEDPKwviVCWS7kc1b5Mcprd6fVa6SnD/sLnKYx/wuxGE8ou46p30kGHuZzXdLNhW8VyJzuwrNUy
DrEKH9TqqdwAvLetcwLMrnP18Ez3N0gkuWYQdXmZA2KcW0CjWAQQfLUF4g9Dny6m/gVR0nnaUegL
fLRc9pMrO1wlyVOZQl/h30ISvARbgqUpmdpFhhJ2C6jutpT7ARzroz/jIsEnhLMiv/Vq8YjEeYiK
i79/wPeOXsf/B9ToCiQd3TnAe+IuCXUdz2szqiSTwSymNtc+b2sL65lUVUuZq0wpFRdDyODKpy1D
uNhTTkVj1Gl9OpMBp9Wu/sNAQ5ViuqUOET1TCISzXy+lYKAOgLUsLL5klVwgkDI97gcA2ZZrkOUT
bZOOGVtIsecHFfS9lQ40WHTHqLOU/8Gq8tmKmgNOyXOZIse176cJ54r6JYxyK3TrzvZtlfoeidjE
TLB9MqUZyVc6KwrueV3oqjTiqXU6RH7nbPCJdfdQLY7MnfUAa3I7uJ3vHIE92d/u0isxjDDvVtTQ
gFsxtj1P3iA99Vnh3QkugbGDDA3ZZs2TXhUi1u7kT3ugCuOST5Sz6tSz93hW59Y5KeOvLupVkdcF
LnLWBMG6zCAyhxAsgYwuc0tQIwu5AxUgAmuKaioN+DY2/GBgelCScSbS8zxM/WvTnls68zCl8+t+
fdeG2oKzxz9l29kGnZZE27uD53lQlpBxf0IJ8iRhVqY9OiuNGwmNTyU3HBFnVlGnvDHTMYZ43Qn8
0jegY5j2V13dWT8rXdCJgeSh6q5CsgB9expO7mGHDBrSbc5k0+2zzFQ9GH+9ngp1B/Xiwjh71JZm
X64xsCauvZJSDvjvgdHtA/C9zVyzvCy+D7ptfzISrP94zEWNvvNVN9O3Hc4z8JI3Jto/81Yt0CXT
8oqs0yIiN5Gzz1cf9KtX0amioRP2t1rvrrfgT4SzYD/tG/+URcw9arTJ2c3iXzabZkF71/sABnX/
UninCuImmBeetYVyVNMPyPyX2yiMtNUzSWBtKadZwR4UDyyfimbCqm8qHWZYLTikubxP7hOBzj3v
P8LJD4qT6PtQodTyLSunzgq3rr3X0s8xM+4YvTCjlB8H071hNvWBpg69fBoNRivjWuhYg5NF2WRf
Ix/n3jriQttSH2FDTr7Mxx+dmEu7GhFVpmAly+627gcajJkDhcTUBIQIU9JAGB2zI0z9qtSDsllp
7LmVHdoub+TSdxCWOVLzY6H3VsqUGfRMz8qoGS/5wqXsd0wHISAe2LcAUSrB3/NXh+FffoGwzDe7
lzc30CpzXCpyoANeMLdBl3j7m3yWGP+F5kxpkRnfP07mG8dh+mtmDyUDFhTBIBdsqBR3qjX0YfK6
8TiODmFjcPIc1fli/AdpkLWLC4kvuvNcgxlgTrCpV6tIscdJV5UBSP6PdL7a3hUtO1g5Lg4xCX81
9sj4dig3B/1+9ZltrIGiFjU7eJUvTdwWS7Sp9+NXoT1HATp0DD8Q3I7aMSCJQWdtDK8ZWiel3Xel
FYPS3BB1fbqbV6fbE38YQoSHpai07mq82q99KN5TkPxiuuebR//nwuPX5tby74y978sUar/7WLCb
iwK3qGu+4nFT/Y0DEw2/2VUUratQrX5kVdr84zG3JYyYDJ1P4rFQde1kCnGbq3R3ZJMKkbmkWiZa
rohwyGuhmVvQX2hf8gVABHQyjODzJ6mYy0crXJKX7obV0KK+B41U6o/HGYQkEbqxL9yPT5dZVv7r
IOIfr+keEddShFP2uw3op/OZtfpyGlkPTOk25abYMSl8QPofAxV5c2YS3MHm+pP+ofz7hI+VEgc1
C6H8ek2oK/3MLOqPljhH2xSSpk2Qoo6FzUAqygqgB3UL5k3XJe3orEL/R3wELqBtsrYM2utiSba6
tmSirTcj2FJ3HvCbnAmrsRcPXECVv7LxHTGcguLaO+bHzA63aIZ3YeSEn5aBGA8JyFNVOUp+sqDH
JBliIByYL5TONbXpo1eANkAnro8WGM8Q6ceyeoVXJmj7rQ9U9e9oGvwEqdpNG/cniEYSu8o4NqjP
8ans0SgMpWMC1VePg3mFqLU3F1tclkPCTugwtH9r/S5+D5oRz3BovuWXXISpxAscuS4rfzc4Dssl
yTK0LNldX2lHtzV0iQO11mGpoz3W3KhKQ7q1xk5Xc9ZfMG8yJsfiKQe66Oi3X1wIBuNv5W1VqMhN
mDKtuW1HvWz2fli+TXDiPV4PTiSgkQnX0c2YMWCUccpAGbPX+4Jzb/hNohRjZE+Rg6oW+PMgwn2A
+PATx5tFrPwy6DsjV5q7RnCNRZSMgXd85rtl+9XxAtajD1LDfcqeQ1yAoY718bYPxKk2lEoH6KzR
mLHq43OFWDc5xg8WP2iNjdJq7mNhQdykFiFQaTR7Jr1LzVszCF5Xh5bFLT6Potpe8j74eK9UFlrJ
7Ii3bayv6UzwK7X0Jh0i2htSUcCHERLIEIj+riee75X75MTHc2hQK2NwYKq4nOyIfd67z8lbUsqm
FIR3FkIjzfKV/FxoD1Ov0OirNrB2nmDlaRgbHzUUVkIKlC48cp6qjfujlTlXyEjrdTLbVksOW9WM
YLc9rROAWdee0gmzuOM5BWh2Aq/jbx/tekUGfFzA0RAbML49wpSn2KDMb5zhl1MjH3X7ialNVii6
KSUWaJ5oHPh5jatjhfl1GgFAjin/HARzoG1pmT04YhgY3dbvwHH5ed0/7K0nguS/pgtkhLHBM78t
/tkSRigmdNsZlsPYbKw5vpfYuZ/xdWH5mxE0B75+6fJGzSFfnEs4M4FoYzwQPl/R/zw+gjrADrbZ
sFFKUmN7Hj+dVjsAIxFLyowlQccePXR0HMmg7WwBRSluuajQaYJDW1ccpZn29A0aa++J9eCNeSod
mtcn1IxXLwsTbuLDXve9vuX+35wYNwgGunthiWnUX7EMIPbHJF/0ytP4H36+d+cFcQVAWWSIXEls
ETB1BwNIIa+mVecRcSYyYeza6URlQdyPICYxd8CRTsK/x7gh2FieQorGNXJ0O1I5Vqu8mIz/ltyq
x3Ec1mgFIaS4HZGisbLK1FVCi/jcoDt90ysrMaX4ENADLuLGohHUCARpH8DNj/y0PNro7VsekHkS
P4y2mpksof858R+fbEa+Rf0LERSLYHbzH2mi314ImsOSpYya0TM1wsxHOxkFytSeWdqLtf3zClTU
eDbT3FAyHhIbhKSkdaSp2IxduH26SuCcmS7hlUMFYKKqv+Ls7BXAyY5Qw87O+BEXe9DFeEZMpEVR
5mqjCenRiY6L2nU5FlgsV9twTd5TF786NBI6+rH9d376TzJyfJTiCjGUFn2SfhwAnUfEX31Sj+pB
dUBVmmhAXLY3SmLjxMcmIzrY5lxxvdHxfFYGRbStfSw6rfqvuptc3n8ADDusd25fp5yzv3WrIxMu
zXDMAp8VqV8F3VWLWFRHheEurg9RyqxjqxoJr1sozKUUxlETyfPCospRQ5I43djaA0DwyBLI29Xw
GbYBIXg3zPieus3Q8G7LS9rSPsqvJDqEg0oUL0lctXqCOO2Gr8v4YjOgMwalLFcF3UoLcToq6NLK
nrycIOQ4M2culb1Ueszvy9e/9A8Za1bMvkhZDgTj6jqRsXG5858O8fuYLOmmDI24gIEUaZ8DgRA9
cPACbhVHIiI4Ok51Tr+rZAp5Goo+FL6da+RkSf2ii5AC8+zt2X6MhJNdfXuXeteugyg+3hNl7WdQ
pDl8XzEP3dkD/g8GgI36KC99bp/NrYo+BRyVbm+X7RwkIdcOBQ/ohriVzBu/2YyYbDsopu3eEliM
z3MKLJEQ8HwEKU0FpSvL5R7lK4/uMtxeyMEmjRMYjj/PFyixfOaQGQST4CQlfFgxz66YA5VQLMlK
l0n+Ei2z61I8Ymw7BjxGNKH1l3V3qT7jZHjGNScveIip4oggi4lRNPSdpPKzEZFO74MnQWMVhpqq
MBvhDcyhM2Hi6hNQRmiykst6Oeeoa21M5A2ra6VXgDiDPDbE+gtujT7IteQrxk/BUVuyf/cOebeP
cnSuajpk+CwOHB73c57gpO/0k12VD8Q/DAZUYFZg+pvS1T5ruO8p+fypbNFQtuK5AlUUNGKLrQtH
oyXpjjlCTPPkD7Zl5DMjvAvby+HzG5UnXIMnIXIlhB+RfqwAGMDdzEboKNv2fyFfjPneONlyU9YC
hnbpiM/JeewPQkkCt8/PVCkkb6io/ITfG4QKAUQSZFxsmF2te64C5s1lj+k10M4xz8urcvDtZvcq
laJmeC8oi/stfUYw54oAyNb2Q7LsNwOtbwYVQkk7Oks3Iowi2u5keZLOOeG4rkfyf3RNHntT2cyr
iYVby3eVQpf3hPPK9Fwf5A7lgsqcANDj+1uHFf4Rb02cSpCzj1l8OeROMA0M7G2Jm7Y62HUwPbfi
A3ITseZQEnJlWDTbNjdVH6C771pwkVLU5m73eKvGQD90hi+ROmUI8bVS5aRBWbGbCgXlle3sFOe/
0SHByRm5HmksgXDQr8CNQL3rUqS3a7WCQDMspIXDIfRjqudVdJcRYBrMl4GxUUbUMSOjcnNAfQGP
p3YDQR+00wg75HWgygKfijUeh1QFGDKRNyAaLNC+eH9xc/RBC8TUmteoClcqmvquH/b5XgFMaqXp
MVy+AxdmMsbR+gVi5VBbGOGFH9rmHf7gAf3S0stm3ivlTxiKy+S0J9iTD1MSkaspwE8rgZMZliIJ
pM5DpfG3myIlmxYeA6P29qrqvmZvBuZJWqRMrCPQY2Slr3m0pNS6KNiemER9HwxE/u89Mc5BSTmW
2lmlb72mQ5ETi+mfT6Q8xnxDisoNJqOuGBubis8vTSz2KR/uylQZkAx9VIccLjUZFxdatzo/Q4X8
tqWkAAD/7tBjpoHe+R3OTCFPT3tB8s9zEUCF+JFIKqkHhtq+nmDHU9b90a4middaDEoaU+NQwXfQ
dKutMhyLK0sEFKt9BYnxXNokIpoKUHLUPCkXeUPNY0sh9I5kmpNPH1JjEMyO6QgNITFPsuqzg3eL
A1M3P4MCzaZcSRTgcEulgPp5xHvVPF4WgvTSNM5XPqENCbj4uJ64quiPLVPlf7vfpeEqEBOSPPPt
JmOhMetGHGc+qBn/TLBckG2ycPYPRNpg63ZFfDiUp+vHkiIsRaKkSV5xb8ecd2ZiLS2D2LUFMvv/
G7hrg6odd7zvQLm85oiIt8AIrEVe4e9r+GBUIw9vb0tnc4+LcmKd1rOZeEnmH0x7bMLPCuwzZsHj
ACs9dIFkpl2D3QsbYKU27PV5Tcrb5cBVJPYi24S0yDZM6OGsnYScqgmju2tPTBqXylAsLzJLZ4Mo
b9adY/yC42XZdrwwAS7t+glINwHSOVbR6+V4e1Hb+u+BbSDWQSEgeLss4BGp5gLqA/cO6Ftl+y7o
/G2AK/kduH2ymCoSddfSrLLs5hSJP7XxX1CAaldP16pU3IOxks+rWWawgvshBcGSHNp+k4IPF9fO
V10QSUhcoJYHiuuZE42QFoCeSzEwC+mPFhESk4tmUC0KSYbLCNn7KDHvkEq09PAgTFMJSKfhrvn1
KipG9XlBzSnoT+8qU7NDvN+tYXFYqNdmm+l8aZAFY4XPJyTNSKNRLmXxUIyxf6dayeqrtztNm58D
yv1fMcoObzYFhgcBXefC4Qn83BIritRk+hilm4Hn9SZG4IdTF7I16B/G2pVtP4tcyG/fQG5ThAkM
dSo1xp3ofreVeljjKjQ7JSQtLxl2NE0kqjo8dZmNb+HPqX1dr5gmxRiaPw/1Zqi8FHjf+48xAjmu
BGsVGR2axUbkLiW+tXQxbLwWt3yxtEIcYrTAGP0X2etb67QESmBZn4FeULFHfggp2o0pOfI2dNfa
0x4klj5nJCIvsXOaxPmdCF7EHcM8V5BRXlBfwczD+mdhYyRMAzsI0jzuKpOudY5sD2JDiAcxk7gJ
VUidUMT9TWpSTwQvnbX+z4Jyu/9Mmu8qvAOtz1Bg/Z6LmCmJ8jvMgZBva8+07t58nDRQHRyiEbMZ
OkgzsRQitYfB1+SRUonhzgV9f6wUYLIqkci5PtsUkfgjn1+Jnt2R12kiLGh+WbOjBWOHENwiTMHj
Gm6yNNXrSaRFzPe1t32bSDuazVD7l0kAZ+8C2y0y/GQOHnUsZR6gPGkAdKRF4807TyyKDyoihL5J
SG9wpgijVtv9Mx3BO9+5Hh6nUwnFrVNZ0kMOmmQEfIWRmKhJMikrXm0JzWFSIx5SmFqFFmURXqsX
OM1HkgJOvz+B+vvOEeH166osBvdaVKiDbFaxQyCLMDJHJ5X85Lhnps21s9HlziKBnpgxlvxVEfQH
xkIq5fVA1thbxf4vkmIyCjYVgzeYWwKpu2ulmInSNrIjWjTh0PKwJbtwq/Bfi7958GIqNxNwhIzo
i64wy2uIiQKGrneujoWB3/UyEb2iD5lYlxgwQiPXhsBhYJp3G3KiXKTJy8XqnAMeaonVodo7H8WZ
EUbUrJjXMfACm2zsDcGHF/gYFcZQrE2UwOWd7gPdD3njGgZ932u3QWvP47yKXlLoNBFIK+PdPeU+
kSFZp9uhQBsiG0XY8A8vos1eXIALAJ43lLmOAg5pzdqYdDg7HxpXmoOtHDQ9RgfT+EfBfIaKxRBd
/p6KWtgYmRTwqngrALm9b5hBiujFSXqDHs2vG6puwoLq6ZEmqXrIEu97uWYtsA/9tvnZlsh3in/V
xXmJ8UpL1AwfV1zA9sf/4T/0mR12G8umxpvSamOY5VvBSXRQ05gh3xDs6mybrbzAMKhoobC5JSLr
vjdOLaXvIGQW4iOWlTV+AFyRErpFHGppcWqU7C21FLqFEnnMeNd9/azwsqk9x5hvS3vlN9vMw1hp
tZ2yOeymckn7jO7x95ohNdinBKJ/Ji/gnd6AgeEyimjJjqFidmWbIFKrtXVjBJoQJ8TE763tVMoV
/zuUM9ofure3i+o4r38PYBBV9IVxTKe+1Em8Fo8EP7HGEYpm9L1UOWN8z7n6KDc1I3A3u9NGDb8/
sdbz3xxbUNhWxOBknDIdC+RoAZRExniGXwB6yHExq3iHGMSj9PqWgS8y7C1IYs7AAfsFvIMT16y/
BwFYWi3MD/odV/Heg4SGJX9cc+Ge5VxqCLR+1uiF68E/OL65gASQNQn9BKj4GenPiKE8HP3ZTfbR
HXO+BmK/8rSK0pP/rVdtNMR6PstlfR+Spz2s3dLuyUNN4qVQEWUXuYKEhJb8uypKwnoB16sQwMps
s1c3ssL15MZ9vLHvBrW/W0rVdRjxWJ4DaVVw07Mtl9qIBR35XZ1+9WT7HX9dV755ThKrfh5Yw60s
W2xAbJCqRo0UnNMLOGSTd8sfHcLHQQ7X2hwvwFxTSIMm6fnbGvhsKnRuvJUri/iN/uBvTfxoSUTM
z6pY2f1aoqiQMb9ExXVNdI3L8eXDGv3Zrrn8CHBeBEQQnMKrHtpahBgMVqrTHQ1jUenlXcKsaaux
L9CGu64yJkJy4KTLU2RlubB6nxM6lo1bW3HQGNoNGPqmkeyI+6PxwsOzPAQhZKdiLEKrLP5AL4l0
ihszfmwVk4SMhDlghRrNr7MzRIRlwL2ot7sziVbJQllrJKRp8CImxEYHMxDK2r/zQBACv+bAmOGw
RO7xwT7BePSmPNjqH62Y2IZ2xwV8Mo0i4LrpCeteLGAN3VZGqHU9vg4WUXChBetX3fpNcBs8EpMm
9Lm2sZiL1mTQGhB/a1KGCP7VinHUQfdNXurZ2Lt5r8UuIzHj4CRPBJiyAD6Ryzwmx87jNh2g/+i6
jPGt9bJiOcgfx+o4FZLYFcn4j1uADLOsrasRoXAR8pNTWOdHSowgp9QeTfQ9eb5+q+BrjhIS/Pds
dxIT9B/1t+o/oIlj4X4YGYTxFwR81+xkYsS4kI/lJrK8VBVPoykx1VslBgBXHKlBUVP5By28pPN4
XXczn8Yx0Zzjj4/klZoRnkq5BRCQaW9g/IXOKPIdHzSn0+jd9gTzb4MCSx6bWaRAbY9buTZQ6dma
jdr5F0s7opYz417AIhUNdYrrA3fyzzNxMIjWLlKePr6wf3olvZ5GGNUXsOIFn8SmoWhEuqXkH41v
JrPWTNSZw/cteLZmlWJrI9k5KKXr2y7kjaxs0i//rH4eCFPz5nWMF/hlhGaicRiPXGheXytRCPiP
Xux7DwQlQNPIhHOlDr4omb9IPG9loMFWFnsyD/k4XeWVf9aWT0Gdu6xwvo/UlRl0EyYxPmf+FNJJ
q5ivmn2xAF+IsxMtx0liMY8fUpgJytJSkGnCfCxlM5aISLXzZj3JtT8a7n64nyjEmq1wgjR96aPj
kEGxKgkipkse6sTrsA8we35eATcTrmTc9OZitAEmr2/rrgyI7Cmvko4K9lwfl3hiKcYj74zQ4/UX
4zuzB00UAJ3sp/Z8RdfzeQFlWbrsc6ZF0HX47wA6wrLD8b9e26a0olBRTqHhc4ErLJjjh7m44jQ1
6f6RP58yiPcW9Q3dAISKPjEaJ4MqE2nL4xq4PwcqA6On9mbdJsnuG0tfbLp3JnMwhqfs8DQFMNte
BE7+9m1T1dG8rKxoPhMr/sQ1ZXqaEfgFxUgHFsaiORkwwe4DuMV4qECUlDQwMrPxcdxjT4LynY/E
YdYL6LQXGdq+XrTN+BZ/3q9fKos98ltv1qk5PdtfEMVV38z6DGSmMYvmHoWi8ycB8w/Xh8hJv3dz
AWnYF12PdGZk8o8t1e0W6xfAyJyKy0LABFfk7SsYj4SmbfDw1yEiPO/jKqNRHk+OhRSczr7vAPW3
SNBk9p/eE5E7MDEHowxHs1H1YNeds2/QyLvLakDOw6Snfu22SFvnAYcsEPkHAay3HWH7hpEhYUbV
jCepL9FfZlixiaXm6jgqO9pfpX2odauPzLbgL8W6/5/0SJIjHFYX6HzlDNNYnkijGKfvuP7kDqec
bIP9XS+3GYgclHFIcLkimQvIDJkvIZUu0LAClZw0zHqOochiBH+WaUdsT0TojC1jZDX48R0LYI3J
sQNDKIBpAsJbw0NLOVQMhGkWbbkfxbkLULGcfgjK3dK34U0l7jMKJLg1mP8/HINU+Qvdc7YaZpmK
/2KvOFMNUEt986tt5VTlQSRELra+43VStT0BXm2A3FsHyoJzG/dEiybvnrvLJX+4q0jK5woEAEap
7CaNncW7f6EkXcjiY0J5GbHrXBneeCkKbr7To9yOpFSCyaB1QqmqBnZXatcV4rG0wId5HwXrTndG
e+cIQblSIsxCSi1QN7Wyc98p3btUWJWsj2N9SGifxrIsGVeXCd6eoh1JKPEI49QsFFLAWweRHHYi
q5aLNIGEUY1MOMnAw4jeGSjqSci5p2hsKKlJzwEMaaIsMQ7qTfG+iLK/jBu/UUl/RA4cO3TSU9+C
mskIxsTAhbbvC8LVjhq+NqihXJE9SLYXWrjiB5uiNxI1BCkgtkc87jO4zq/YVwz1gEwBMIcMbajt
iimDqeYFHoL6MnuqTQH67tzYuNHw3iET2oF7fC5NsXFDyOUFzItC37cag5GX484e+9JuZubi2V6r
pu2HWbnNjRPFoYQPBP1zTe+SUikMVpgzlswU0xtA+c/3U3jdehmR9j+bS1dytjA+wrn74tC7nK/U
tQRabO8qYcUXI3V0v7tqYN7QzP51R/VpZdg+eVBL50mxWlIpPdmAhVSLG02sNjAksewTNwPbgqGc
Hpdm5x1unrhn50YthdcoYQPY2hcUIpdfxUvsNYJ/+at2BzKeSKwR4AGDzmKOI/jaBCD0ZMl+y+MC
/a5VOrGmuWiRqioL1Za+D2LYb8QMKS7h/dUo2v0zQkVCPIORvuqrvDX7uHzrCxFvO7UlzVXHHKnI
gsyqV2rclRvAd1A09+bHfU2lFD28Z8qj9fXFMHsr3BdfvMfbuGECFhkY/vNcSvGeR1WDi7/E4B06
P68AV+ogMdsEBw2Lulf0dhyMmJCSSGvmEcKs/syCocXAmpLA59vnCffKKMMzWDletRGSTRVpUHoo
xenDGKra4uE6i/jAPl5doxGravOfefxbd8u3RwwUVdcTL+EQq1rfrHMN29dFIVnigccsqLW/l2Kv
bkmY9WS4rMEXoHQ5dvKXs2n++o04uhyaILiGO+5jybUBIpP/E4zMycKWY4g394+lo9XyxUDCT3Ph
Izl+crpa1WhkaRNjUuyT6h16CClBc3MSoAvp7O5sOcnGMSSYeeOrXALmxiRo6YEzeDkrDaK94xYT
RIywnfXq2OXlJ1YyjpThU9WRotCV0nLTHTEqoSyxmnrZ1TPEO2k3okL4LmEB2JqgnS3534LPRpYe
ufdyVkAe1bEoz+oYlL7eZhewYhhnlKNCXh3B6IkeIiScIbVXaTrC+bVjjSKfH5aN6tbbkDY7qK7N
yT2cwzR+i7hHvMfm8fEOl6WggdUiPKBANzNiMNuaYCZ52I054Qy2fhlKNpCcrUP4MSZ+qEkAGP4j
so4WqnGK/XDjlBQ3IedYMTlrCf3bQrO0NLidcuQN05VNJeBF1bh4OCREH47Y7PbaR5PD1X9SZGZq
08Srqoo2896O+8jUIUIcfj8y2LDN/Aip7CZbV3NBBeMWLYoh5rqTMz9gJKLiOYt4wdM4uI4f5zkJ
iOW/FdwcNlSeJxZUXBY8G/XRSk5jVD6FkHHK94b4LqbaHwISecfS7tF2Gc2S6YQotc+cs4ImTYSQ
qnZ0lNx67FWmGsitZXoxnV9l+wJTue8HxLf+Sy39vbVuN0ODBrDB3xpTizU51l5gxnQZdle1XHut
drZmuXZICh4E1BeTnkwmvG1jHYPzXLqxjsh6PflyDqgu0cxnW2zA5BMGXZzdM5ND5heniVYBUYwF
mdbNPQDJD1ZavAMp8daVnVsf2rRJzevvMiPC0wMC5TsM2nM6/cwbg1PNS//cXgBGEx1Dzgtetyb0
OcyLrYquEvZDhPjHuA5Drw2RSDcI7Ci7DFiZThrrcqC6Q2jIkB4ny4Kcjs34VRUsS2CJrRuF+O0G
CPqCihOtK4ggyArFlXTQoTzKgzanPbxBDCzT+kH04t5iUuZeguxI3s7WHZ43sq+f3w9NOxZbndIY
nV82FMl3F+s4HRxu49TuWalM++W75TxXeDnxNebQ6ApBSlIbKFn15yje6CbW/TOZ2fOrUy8RXulH
iEdfLemh1vg9srz/I1r57Sn9q400wka8ZAqEvtcMRKacDNmcZVXlAKa6+3ZIn42WetOT03XpRuSR
5qj4XsIa0jXnqHrmOIsIQLyz3nPxUJC+xBxBs5KvvKzT3q94Rzd9ro9J8Xq+qqgcJljfPM4PgAtZ
FYwyCctfu4yyXQ7WpiV0Uy8cyVkQruQrSZ9oyvHOrKspmzH8r3nS5lWoW6YOoFnhJANMKrgUzu8x
JBzFlzZJ1V5I8leV6pe4oquoh8anGxzjFU/oRqVkzWfXmvxQLQmlukBdvynmYMv4RIOiytM3eHFh
ZqJciQS6kHQsAUGbKhxE/Hi4Otm7xP9ewjI72nDQ6vYKT1ndq1JqCKluBiyMiJw5t5E6rkHA91cy
i50JHQMg1y3i9L/rH14njXPfOFqK0HnMPdZdJzUF1DtgsiWnIc0KrcyCBaEJ/N+Hv3hoLI5roZEs
k2eLeN4fox/TVLF5sMDNbyjmMQV4siwpr/fLBOD38dE/UjyVveT1A06LnWHQB2OU5OUkKjUW9pI3
iETmZ9pjpNyEk+rET9FnCzeifn71aCX/7ONggCkz4ZZeX2/kCXYmw5t7hhiCRkpounEjbnkTDQRR
s2P0po6tiIHZK8hc0wxBXybcAMqNaAfx3AIsIbafPCrYMiDwpaPV6DxgIjCE0EAqWzj2jB/LJ84y
p49YU8hwT5twwNgFqvWRlilkps0P1woadydyAJfS4Vktx/9r+Ana5+fGfmi+aebgXKLV3FbNha6s
4jSQuA+mnB0ETQAJGGOd9lPakbMemWfi0X/czPJCl5TjxeoG+aOYOPBr3p1uqwPlF/0bJX0ocMLt
/4x+mrWBuOVeTVsHFm4OGyYy2QeLcx9eDrr5ZPWQmt/WfqCHaIa5JR7Fbnq2tWS0tJOrn4LvWYKo
09wUhBHZAwgIZlU2dR3CYZm1oDb/EUbNYCXSgJEd7aaon1RDFTrfw1imsUWrP4RB994DIpjeiN3O
y3WZOw==
`protect end_protected
| bsd-2-clause | 3a4686eb0c370d610b310f046ec321f9 | 0.953123 | 1.810764 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_dc_as.vhd | 19 | 10,777 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EHhlU67zSXzve/de+KpY85nXXvMNuZL7tYgf9fn2xs2MMX6KZ+NkxxVYV7RC95SlNzgUt4DfQ4/9
3ul1mLnDjQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UlAZFSxNoqgvPPKliBxVt5c0coSpd2sh9B8mE9L64FOLOsIE10QbDZBGLO1c2gEWIwuQ23M7QvQA
5NLCK/AU93Cer6u3Y5Kw85Zu7Q3cTJ6gtsPScNo+F/wtG37D/TBvZy9QIxLBvCRLOZx77GL+Y61M
X3HQ3kaL5tpBN9LRA7Y=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BhywTGDm5IJZmP+63CSoL/TDCpGJVG3VkCIbV3f5gGTJ6iLDPwvtFhhY8681GBR+EoOyUSMbP3AZ
DMFHBgscpLa8vafzBYp5kDkIAp6zpVke5p8WT0T374mfT86d/rJV4lUvVArJtTXZ7Qb2BRu+oMwW
4NXsxCdhgqbldJw6uUCqk28aEPgcbivrgwKY8foWfBnTw+EKHyn/oWDvwghTokcxfEnmhIMsR0T3
yD/98FKNKviERlHfn1BhQ/aqkW51Vp/q5U9qrKs/+lZwoRMsy8lRZRggDQnNmQrFO+0t1Oq/DlpL
Pzgpskdyam5KjVkaaUDiD9LunE1mnunv1fkvkQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
M0G+I4o5qs/wY3cBNkJHuC5SdvD7yJrXn6vr03zDaDrjCzuSM2xSWnhAroxnc+rs8YiB5XG+kxRS
nfrpZghhDmt8SYAMsT5eb/ToWHwFcmxPkOwf0TCRf7UHox/rcVr0f6gppZYuBp8i/HMdTy7/9hVi
Jazk/jJ0qiENaXH3lhU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
II8O6ksX/NQP2v4t19inJMyzBruYXofFp7EnZduWuRh3lmwU4/uZj2tsoMzEFI9GURJGr6OGMrIR
LHPoTtEBaHFBnPNcL2m+mOF2hh90g7CmgF4J8nr08oNvCPZORB5fd/Cj4ujbrC4saBHdapCX/nOt
W3mratI2AGAl+T3t7Q0k1PLokEpC1hOrn+eLqLqV9hKaNBlW7DfM0Swj9M60AbHp0kL8sQjj6PfO
zKNcq6Xvq1JnJLzZ115Py+hhtw8g3az1/vAI3s/sf20/ggZ0t1s4m7+wPif6Tf6IZJCySXPmKW47
LjAxEb+MGgXZe5eFDZ4nbVPt5Q03mtQWzOAzTQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240)
`protect data_block
KjU9w7W+EMycYBwWubdK4cdo2TVOg7IXnsAenMl8Ozs+YPsIVEz9JLFHnXtP+EnrqLSP6JpsfCDv
c5EY5IiZohLLsnigtGQoAbw3xJrNfW7odSYx5OD4rGw1worABRCGX65sm+Dz/Wupvrnmbf1sWTzb
I1Yb+4MVfrIKHdMbYrS9PLjZ7K2J3YbboHo5MI6h5AlOz/+wGnMsAEaQbMYvqJbaN2FCbAce2hhV
fy/iMb+u44tGRUobF7EBOM25t3AN6z0qAN8B8tt70gHhP7G2dr/q/u0VygxQRtQ4Qwop7a1Y+Y/Y
vKnqlKUJJW1lNtGrDOjKvANBtviInxNmIJJuTt9TX6ORbWBArIhf4J6Swg7TRMm+PSivJewPvN7T
YlACXXW8PSBf7kQxUv1GmNucJA2TdwxipfmPsgFE9jFxlJzGdnUSgScm1bb+uhyB4SFKWJtjiUfk
ChVZ1dA71YVoQibyJENp2WllpAlhr57uOo5B3OboE31a8NK0MnpKkDvAFfCKtRNWChM61a50DzPs
x1ya5DsBYVEJE0yQqZaMTKjONm1Q2quPFAsNFlIParq8YIf+YJI1h2iCp3VNOolk3dXcZ5+dFf9A
5lFIch83dsv7U9xkziK3ZOXOGSAKe7ZuKMduaZS/faR4T7ZaQ8Dnr6BOjylOmEwycfepVvnpgQkU
P2jdhLwiosu6YGAjUzolNsxAZE+sMJ80VQSxu+dfjyT7buiY0oLLoZrCeLdIHrJAIBSBkt9PUppT
rEvWd3qEWeh+cRk0qVqy8k41MvEg2jAtAcZwP06/lVrGvtQRiB44kWdpJUC73xqVc5F2sDuWVYfX
ItM4rOxLGOjc+JhvqhFPqYLepDQFcz23kjWAaIp5z4Wa6AAYrhw0t+0FrnsRp/vvhdQb9wVWj5SR
9IPA+3c2CP2uDvkHbm4qfXQpOUplq7T5+r17VfKonq8y3TepvMT2CJyp1Et2UGI5paOFkMGQfb6j
KgH+9hqhTaCeKynmIF/WVAwvmw4MK5K3mIyBgTu67u1VlOIiT7jyCVc6UM+8YKnMW0bGA5Owy4o4
bH0qDAUvCp25DSbPUfVvg6qUSpHuepCIxnVO4fcrknYmhLSPF1oeNQCJsVkX8OqLwTa6Y66Nn12C
yJ06vsMa4TLKWHzIp5FhBIFCTVHFV6DqNVBBEty81GRMwHIQKnJsziUfTQunlfoTTe09MT4VYem1
JR9qHh8Xq9h2Mmd6kAoNyP10G34oyVKq5WUkaTmHuDZEzONtfQ9eYbyiCvLbx/rwenhiGuaIjFA8
qUpm7XmYDatnG5yhquyKCEYoNpe8yJBUaShg9Gldmnxo9vwa0Q2JtqA741aspVRtIx+ebh9d8me5
o6VAeWToXdA3tEzz7lT/7u4OTR6OzjIDVlOMDGJty45RUN9219if9lcBbxEvwDXV6YgAG+wZebE3
wuE83MwN7As9EDPxC3boQMqzDvVgKZSr70o/08jjb9dB/p3vjw+nwuYd4xzPLI+ZB9s6k6xNf4HB
Ck1RrL5Qo+56iyJC2smH4sKP6Y+W2QcYA9ZCvCnzsSJZqgwKuGNbtMwAi9TYd3KlyRcSZ+kXdLcu
J++NMX2z6jAn73e+iRBQ1HnxRp3OV5Ow8LnVLUD9kkfGuRMmxREgNHdH/Q4JJRQL/Kbn+JKttwzj
3NnV/Q3Rvv25dflq+WytAtxKz6x8J/iShR+b/PFS3nLI0as7Wc08d0XcTgivltF8gXAFME38kEhz
LWd3xy7WO9pp9kVQ2mBQcFM0IFS1fIFdlia+lz2ahyZ2GlMA5hx0CoVNEgX/Y0zndSpyVUb5W4zW
hLWph1aw3YTJQ5ae2ZI+BkzaapyF9d1cn4iId6yN4jotmC6btlrlvNCCXIkmQIUswF3mrXc5rEbW
PSV9t0/hho6lE3+B17Cu/NOIQq5gaUinTfCC89mKYwaVN+0/q3JJvOIeHc9LrOJcBpxKx7hfMZSk
a5KPoDp2JWpXxFGDnteZ5sCm9Z1/n/BB6v7WirmQrzd3VckoX6bh1+OVF8eq0SQ4ewiJDcYQRvl5
vGRTaQnEUxQ3dY+CD8d5vfU1ttwQZyV/t8kuUn3wtmN6q5O6qeEDCc69Vs01v/K20/2qRkpemzi4
vHzYf0UWqtCkZBmNZhuAe6T2uSP8aD4swtzxVlIgjenx618ljrBfxMBUNu5zlkkO//eppVOZZ3eQ
3ZQ+gKF61Yb485fHH5K0N0+69hMjt+c8mHTgxq1r9lIstt4GVIOk7t6hYEIj5zAB9Cr7jB9dhZJH
W6+bNSs2ND5fs34wXhV7QfCSw/lqkqAoWRjMXI/QaDHltstQR1SWTkGmIi51DZhWyVamFnXXVDTn
HGjS7OfRJ2uOreyQhYkTgF/6wt0/pz26j3JWShhGauXx4QPBAKbmFNlNG4BUMWBJqT6PQzqPrJ/F
zkC1JHRwlJzPanaZKUkNwSQbb9jSQFo88u8qOMRwLACi0QaMyEDzjDhUKBTFhtkNv+PE473gNVTu
dsh00VAJs9qI3Hn71rRiHCOVBTlsmSgR93k3nWX1XnVUEFd2w8RYacOI4FzVNmfVdB8CFXW8x1MI
XNkWyeCIfPtZXI9nIHQjU8O+SMIFQxNCDVv3OK/hDvTlABDMnorSePsakt7H+S29pO27i7tlBluH
IibyZMBi4ZCOVtbw0gJAQTqBunz6xI3f+jYU8LWkw5JUUv3qa1MPzBi9dGDkx8cCsUyPeNfMzvZq
qXu+q54Ph4x4N4TYy9kUR+faW99xbXYMtwCT1rIegoAFsH17fj0chu8s2IpZBzVLPrtOYbWFCLys
D4v5twypLkZUMfyO0o/QuQkHJVLms6Tmue2s8fKAM9CRturZt21W2rMkVPQk93mlcE9esvJvzYp6
0zl9OMmTiX+14q0pVSiTgMk0n387MXfY+lNk3w6ufLZ5bVEthiktsRZfI2m3YpVy+Bb+JJi0ZrTN
3qPzechDhnxe08dNumoKP8C0N9qCUSwwAjAgVxWsePL51iNn8W2ny1vslQBVKss4X6VNV93bzN7Y
pTzexLphfNpq5ylQ8m23Gn1cFhII5SzJvxdtrZ/aw5GefPFKHq8DUlkDi/o13opwW1Rudh1/7e6i
QGThg51wgrH3lhgGKsRV2ZPRowf303ZguR2y9Cb6g7WXWuT4hfzHnreW2MCTy2v5vTN9s3RH8rw6
T0SNO53iN3FLiTX08m+lHto2cZiRbsfJtC7q4ueY7rMofv5Qtcl5/IyuoC/3cQ903bEId59UKzMY
umv695NMs84zzX8csSPDhWT+7Tgsvb6w0OK4tsUipFScSUYXO2qWUZAyURWFHNUpI6MyCPUVtyxR
6w6QLfIsISkvQ1Qgsr60Eu/tFlvu5y8Gw3YwVZe5gsekdIqIKo+StixkAg7sFZDu+DKh8CqjpUzG
FSbT4O66nnBTo+FV9PM1oHTKb+mbC20KpeH59wqWOA6P80vAwi30okV0T+GfgTCrXmDN9A6inzbj
tXkhBd81pgRkHSH6NG+2iSgpl4ArLZDP/SgiIFfopv3GGevpKW6mBOGTj7L1ay8ecl441bPadA4w
ly1qyjVk13dRWAF/Q6r5foqht1VxP99OY+WyYuK39t+cyUbbPaHXJoV7p+EzpLyDlWi4f7o7XJ95
G/vCQ9WDlBLg9ySIyVPRyEs9UBE4770bLaLEQ8LPmRzOEvKU01Z2njPkITN4qi5Y7hwuCea95Hz6
nfVMlN9nvZea5nlaVYU7OcWlTcGqfnqF1jUmel7Vzu5t43tqS/SY3fhJlOveToOUwG5ZvUEGZ8Vl
yvsIZPgTpQNpsjd3G/+XdjlqFH4Bn1E7rpNJ3Do3vGcA0n4BGpbyy1XVBMJWm4ISLKC2T7v1mQgk
YXf1goSB2GgWsn7zo120p1WfzA5uqIfRVPdYDNkt1tvuxseRPyI2G7sRaI+U4b4Mr8vnAK/xQ/ZQ
bhKCmy7hHe+5b+TAs7cN+PFwFfTjboS8ob0gRtlwDRhuNx9vARvnyTKf/v2FlhqYnmLO7OygE6NM
MvWQjcHRlQ7U1mbmMJLupQM0xU2z8x0EYh9ZwLvfPe2+s5y7+ZJIiUT1ZJfte99H/UUfcjvRcMxu
K5WNcSVFY4Wwbyoc6c33aoyPL1hKB7MuaXjdpwXPnoytM0Bmefl5y6zJVDhn9f6EgVm9vwldGzpJ
Rcv1MZ5o+Xz6ewQZPnfqW/IFdVa4hKIYiGsJa88rqTpnRWVlxw9wh3aKL0CNpR3YgNpJITrqN0NY
LNor1+ITn95qrsU1f56R5P7pjpyIQU2+oHFSewnCsdOu3BMbGh20EFIGyzUIbDnFnjAr9BAvtrJi
ECSswhcR5GcntzjfbdkiZdF1VlhVXPvTcuzmlu0s5NaHBxa5UL7dCOEjD31YFJumOz0HZOBuprDV
zwYpzI1Rn6DXuVWncio9rog6qk+gSTTLsYhXgJt179BcqMMfy6iwia46hioq58+WgIHx85l8PNIc
J8Wqqvtqrz51OpeHn9RL6CDT9WM0kBq/S8ZqtCaZRlhMLR2uSWc3+Ajsv2lNh82Ft3xGf17pCFdc
v4dMZD1kHYdyLsyh5wZZIqwniillJDKGt2SHfkZEs357oP/58CiGR7HqqxlIMuX/FPdjMvtUnY3k
9GtabkoYXsw6yyuYj3vW0wcaGlpRmJPy7Cwfcu+NrioQB45ZRgJ+QKBrKcXMWyMDq7u3St+cikUz
sLavLUyILtCX/g1/Vi0eUg6L+Ucae0AIHJfDyGQLeM/7LKEE7HDoSRCTOpRvskTmATZ6HRiDqDVi
i5ajpg9IC27m/mzhvhaUcqae1sZY6RjDCKoV9ZYJFlHl2Pj++Na2wBBBhSN8Zyd4N5vwn/dcK22A
9RlOhqY6eLE1RKF4/L3UK/Xo03TxT1H+qX4uZ/sjvadrip22KLIFkazxHxoNW4OFEaGfagi98BSZ
HfFyv4+i3R6ElzL4pJotn/RY6nQ/RRqmiRKMqBpqR/zmisLHCYIwsVOaI7UjJoadoSkPrwRP3/s4
FMJGHD/xgZOOzDHySq/rwoVLOEDg2wsLxZLBF+MeXlDrf5ErQ6e8Df5FpcHX96E9VlvWoWHIyLZf
PjmMwsqSilfSSDdjyN3+HjPVBWdH3NOG8ftg/VCat/kLbVNILhjbRXlMbnYv0hXMELTYqDME0agq
MQR3/V+OD8ayhGnvwgnjaR0KSVolk16J3xYG6WWPjxyK5ZfesItCG5J7h70/lr+6mhz35z9B+Oe7
gH+b3q88UfE5i2fJgimvv+k4qxy5PuPnQnS/wSibTI1CMOHB/RVEptCmrmbmtehzkgJYfLJ/HV2K
fq0FfBRHgfchpZczvxl6kwo/IBmkorYvHAT6UyCH/S9lx+ZVlhHT9RhTGC8schH2WK/3NGBk3YN0
hqXu2lPsYmnuylISAeZINjVZBMOcdYOPojd+qwJ8lMmdszi4y/Rd5T4fcNL8RPlC4Zis81kYrOrq
1bXONdnD2Zkdpt69NklwEDjEBTpvChAlShyoDes1EnRCS5g/PbIe0Sr1EoahHzhgBR8nR8xpfoQa
A2ELvnuj44fZEVKNdmrXdk76Rx7CnkqnLZcw5CLT8e2/1d4n9Le18lAjOBhVjSNPqYxqVGdOv+90
z/EeVaHTMpZopWqO+urdTiOgFYkUdW4cycOsPIGqc25QtlPaHbl+kkI+8Ja43ohgHSulzqD7rg19
e441QqOh8cVzOXKQ7KR1NUbTWKxbWXPzrPe8pcXQNO+ZM0aTjAgmO1pg0wvzzrzE3zHiDzzDiLw7
LcPnZrLgxl4uRF/Amvgc57aQsKX+xZ1DoeopcoBkTFFtRIXRxbebWJBJXvHETQYBrK/PPQK1/0dj
2LgyOvwScij1T6S+AXwZ/E/96/PjsbFtRzB1RYhI2USIxTFC9VzNzy4QweJJccLVX1ngrWJZwNG4
0s5BVlvSDhXvcUxLPs5JgGrrDNeZkBUHC6qChGSLZ4iy5SUAq851+llkJjtGNh7aQe5yfNUvZGXi
Poq4aupTbfQ2VZe3L4c3ZHX+hM349R2pUr7mFiosmG/k5QUF8KvDCUVQeWRw9zZ71cLjYF24+cDS
hcdR2p48A6uJtHrx25jxiYvlULgN3wsJl4VxsacJ6iLYE2JsEVZH5HsIm9lCRRweYJGA1rkXrX9V
W966Fh+8QPzTh+OJcjIOwK55ziN1OewT5udp/kseHK1upjRH63mw1C6+NTFVTW0zddpmnm4MsfXN
xCiOUbE/u8woN0L3f/bUoLoBb+JLo97+Qi7TCEXgiQScFGMkl90SaoOe4f5r+1hyze8bF+pwSMoE
t5vH3k+xIYqH+EMyt6Tv031CZEcuyJsWA/BTBCcWie2M1s5VkzV1vVKh+JLd/PgHM6prq+PgdVpa
KP9Y3Xj2ThNzOb9wdU4EHKiLooW+qSv0Ucyb9sn9PXFQKhWd9CuaOevHurHShyHGPfLTCwM8JzzA
Q5WHHtD6RRo0dH2NC6YKbemtXRyUWY5chnNgGKy/tbC/GPQV1XH22nBt8dmq5+Kr/A6nj+rPmoLp
+28uOLkhmiWed1Fa5x3okuUeRTZDDcVozRmeHXAE6aRWnKe+Xp/kELYNT58781JmyF6QMsE9+f8e
fPebURfrIFGdHW1EHd+sq1dArvUf3MNP2l7OacdRXuN3CwWj981u3cC7l/WgP7qEzJgAmr6IebEq
XGxWldGXS1AhBU8dIEWsLRRQH0X6FaKTMQKyGnQkX9nIXKTMkIWoqtgJLEoUHXDqDl9+CaB0pqBj
5PmpneFM+t4DxlnWwLPKEMakAugbg2XJXFSIzDR/U+C7Y2YCXAoZiL1AcKXMyRHp9xB8Nya/9QRe
4VoLms5Bq3GSp1zU1sCofg3x6grhWXFdVj4ISfTztjWNfQ31zEFx1/Lqsn8utwHkDLzzYvaqSBv5
v0R+WdwAFrd5IXXmWewka4CscS7Weq61tW1/Ueg5MMCqQJ+SZPLtCQQNiGS9msr6vTcX0m2Nc8Kq
+WRd41/K09XWVV5vG7GDRcgDeABBbZT/5lRZne9OJhWEJh2Pd4jKXyRtj3XefzpY4RHpENgchHBI
CZq1eUU64j1zMI2MWlK8tvJeQOCJ/zgvuS9H4VjyOttYO/88EOpUrJH1MYp0JHbxZoNX9y/BqREw
vAX9U7E+1K3EF0oyFS4z8TdxLt0Osr/8TB0lhKt907mqp4vDKO2Amz8dU0S7DLa256p2KtFxP84g
yTEWYJHzw5QVbhC85j5zbmsMyTiME5+pu1SnJjflcwMnq1krNk8Y1JWBmlBe2uSsmkZjIRrysIs1
DW1whU2fBSdiMRESHY33H8wPHGA81hQ17pF4wCGFSG6mNtNwUb+NA6bXZorDmEMmLf6BfgGQfx6q
2xT9YXuw/KEC0Qb4/8TXIYtMeObaFAPMwPM1ueH/q2GRBJuBLDQYHOOvOyCGXxgYxj9LZ+9U64rr
yaqrYtCQy/AtPyGW1xaMiLw5FeEoEQrt66kwqIkuUXZftATG4TDIVO239uMumZFgHWUksN3bLoCq
QcmAM7+Zb9SlUc7QWkD2p179PcRjDBRxvi66jJiWtm9EGGZ/i3R+JNQEZKfzppHwsACRetKhmFAa
4IpYOATGHTlPWaRfAmZyFCEe7Zp27x7FLOK1pnoEmfuBCuTtX+03L/QsLKEjELAccXBDD++PWcJ4
yR+Xzcw19BqvUsEOSduJk1aDRUxHKVAIrmB1XEPsQW0oaBVp0ju2+IcfQ30Nc9JqM4MW+VsJy9JL
4Ib2mfkizlZyb86Jv43u1NYdCnx9uioKSPNJoabHF4DFdax9d0uISC5KDT+JHQOZjWtIq1YMBOiw
hY9W4iZ3SPFboYzsOMjkZPmBtfuMpfGjVc3h0pWQk03S2vx6FTVTnZaKUrB2LUh7qrHt2OUA/9Ew
y7qbQDe59drGmedYTvjYiSFJewzHBN8C6jEd1GDMN7B1hPGK1r+0gAQsTDbKnNmqcB6h4rQZqVHl
pPB5v+ZDRLUPYqY8dHofgZCXjeJUbAdd1ZQ8xMJP0Uamm0jChwad3bcNGiihLvwrhB+72V3jnhcg
BcDmVPfM2+vgzpiBEE2LfWEgA9OuA15/hI1VbSN44ga+R6Gp6Ss8F5PLAgvx1DNkjrnjvDOlrzea
tV47ZAFdv2JD81L9UxFeXHN/+NBrqHj04HxCX0Mo6QiFUWBivOjzuJMo6y+VyEC+4L9EllJARzLQ
DE911LdeTdqyTWxBrTlQ8wrGcPiZgVsTmedJidbagT19F8bs/+xgDmVOo2ewxfV9syoGjlMwVmmg
Ul4iJv6lX4gQUMP6uU2Hcb5Rv7AZL4lkOzek
`protect end_protected
| bsd-2-clause | 9bebaa5c17e2da4d2e5c3cd7dfb9fb65 | 0.924933 | 1.888383 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reset.vhd | 1 | 39,339 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
signal halt_cmplt_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
halt_cmplt_reg <= halt_cmplt;
end if;
end process;
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
| mit | 121a67ad7e7e7b5d20f90ac2ca960cbf | 0.461603 | 4.131814 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/kc705/top_kc705.vhd | 1 | 10,847 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity top_kc705 is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
end top_kc705;
architecture arch_top_kc705 of top_kc705 is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
o_pwm => open,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => '0',
o_flash_so => open,
o_flash_sck => open,
o_flash_csn => open,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => X"0000",
o_otp_d => open,
o_otp_a => open,
o_otp_we => open,
o_otp_re => open,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => '0',
i_gps_I => "00",
i_gps_Q => "00",
i_glo_I => "00",
i_glo_Q => "00",
o_pps => open,
i_gps_ld => '0',
i_glo_ld => '0',
o_max_sclk => open,
o_max_sdata => open,
o_max_ncs => open,
i_antext_stat => '0',
i_antext_detect => '0',
o_antext_ena => open,
o_antint_contr => open
);
end arch_top_kc705;
| apache-2.0 | f5240e0790a2dea45ea0375ca5b563ce | 0.609293 | 2.810104 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/rocketlib/tilelink/axibridge.vhd | 1 | 8,225 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief TileLink-to-AXI4 bridge implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity AxiBridge is
port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_in_type
);
end;
architecture arch_AxiBridge of AxiBridge is
type tile_rstatetype is (rwait_acq, reading);
type tile_wstatetype is (wwait_acq, writting);
type registers is record
rstate : tile_rstatetype;
rd_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
rd_addr_incr : integer;
rd_beat_cnt : integer;
rd_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
rd_xact_id : std_logic_vector(2 downto 0);
rd_g_type : std_logic_vector(3 downto 0);
wstate : tile_wstatetype;
wr_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
wr_addr_incr : integer;
wr_beat_cnt : integer;
wr_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
wr_xact_id : std_logic_vector(2 downto 0);
wr_g_type : std_logic_vector(3 downto 0);
wmask : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
end record;
signal r, rin : registers;
function functionAxi4MetaData(
a : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
len : integer;
sz : std_logic_vector(2 downto 0)
) return nasti_metadata_type is
variable ret : nasti_metadata_type;
begin
ret.addr := a;
ret.len := conv_std_logic_vector(len,8);
ret.size := sz;
ret.burst := NASTI_BURST_INCR;
ret.lock := '0';
ret.cache := (others => '0');
ret.prot := (others => '0');
ret.qos := (others => '0');
ret.region := (others => '0');
return (ret);
end function;
begin
comblogic : process(tloi, msti, r)
variable v : registers;
variable vmsto : nasti_master_out_type;
variable vtlio : tile_in_type;
variable addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
variable write : std_logic;
variable next_ena : std_logic;
variable wWrite : std_logic;
variable wb_xsize : std_logic_vector(2 downto 0);
variable wbByteAddr : std_logic_vector(2 downto 0);
begin
v := r;
addr := (others => '0');
write := '0';
vmsto.aw_valid := '0';
vmsto.aw_bits := META_NONE;
vmsto.aw_id := (others => '0');
vmsto.w_valid := '0';
vmsto.w_data := (others => '0');
vmsto.w_last := '0';
vmsto.w_strb := (others => '0');
vmsto.ar_valid := '0';
vmsto.ar_bits := META_NONE;
vmsto.ar_id := (others => '0');
vmsto.r_ready := '0';
vmsto.ar_user := '0';
vmsto.aw_user := '0';
vmsto.w_user := '0';
vmsto.b_ready := '1';
vtlio.a_ready := '0';
vtlio.b_valid := '0';
vtlio.b_opcode := "000";
vtlio.b_param := "00";
vtlio.b_size := "0000";
vtlio.b_source := "000";
vtlio.b_address := (others => '0');
vtlio.b_mask := (others => '0');
vtlio.b_data := (others => '0');
vtlio.c_ready := '0';
vtlio.d_valid := '0';
vtlio.d_opcode := "001";
vtlio.d_param := "00";
vtlio.d_size := "0000";
vtlio.d_source := "000";
vtlio.d_sink := "0000";
vtlio.d_addr_lo := "000";
vtlio.d_data := (others => '0');
vtlio.d_error := '0';
vtlio.e_ready := '1';
wWrite := not tloi.a_opcode(2);
if tloi.a_size(3 downto 2) /= "00" then
wb_xsize := "011";
else
wb_xsize := '0' & tloi.a_size(1 downto 0);
end if;
vmsto.aw_valid := tloi.a_valid and wWrite;
vmsto.ar_valid := tloi.a_valid and not wWrite;
case r.wstate is
when wwait_acq =>
if vmsto.aw_valid = '1' and r.rstate = rwait_acq then
v.wr_xsize := wb_xsize;
v.wr_addr := tloi.a_address;
v.wr_addr_incr := XSizeToBytes(conv_integer(wb_xsize));
v.wr_beat_cnt := conv_integer(tloi.a_size(3 downto 2));
v.wr_xact_id := tloi.a_source;
v.wmask := tloi.a_mask;
if msti.aw_ready = '1' then
v.wstate := writting;
v.wdata := tloi.a_data;
end if;
vmsto.aw_bits := functionAxi4MetaData(tloi.a_address, v.wr_beat_cnt, wb_xsize);
vmsto.aw_id(2 downto 0) := tloi.a_source;
vmsto.aw_id(CFG_ROCKET_ID_BITS-1 downto 3) := (others => '0');
vtlio.a_ready := tloi.a_valid and msti.aw_ready;
end if;
when writting =>
if r.wr_beat_cnt = 0 and msti.w_ready = '1' then
vmsto.w_last := '1';
v.wstate := wwait_acq;
elsif msti.w_ready = '1' and tloi.a_valid = '1' then
v.wr_beat_cnt := r.wr_beat_cnt - 1;
v.wr_addr := r.wr_addr + r.wr_addr_incr;
v.wdata := tloi.a_data;
end if;
vmsto.w_valid := '1';
vmsto.w_data := r.wdata;
vmsto.w_strb := r.wmask;
when others =>
end case;
case r.rstate is
when rwait_acq =>
if vmsto.ar_valid = '1' and r.wstate = wwait_acq then
v.rd_addr := tloi.a_address;
v.rd_addr_incr := XSizeToBytes(conv_integer(wb_xsize));
v.rd_beat_cnt := conv_integer(tloi.a_size(3 downto 2));
v.rd_xsize := wb_xsize;
v.rd_xact_id := tloi.a_source;
if msti.ar_ready = '1' then
v.rstate := reading;
end if;
vmsto.ar_bits := functionAxi4MetaData(tloi.a_address, v.rd_beat_cnt, wb_xsize);
vmsto.ar_id(2 downto 0) := tloi.a_source;
vmsto.ar_id(CFG_ROCKET_ID_BITS-1 downto 3) := (others => '0');
vtlio.a_ready := tloi.a_valid and msti.ar_ready;
end if;
when reading =>
next_ena := tloi.d_ready and msti.r_valid;
if next_ena = '1' and r.rd_xact_id = msti.r_id(2 downto 0) then
v.rd_beat_cnt := r.rd_beat_cnt - 1;
v.rd_addr := r.rd_addr + r.rd_addr_incr;
if r.rd_beat_cnt = 0 then
v.rstate := rwait_acq;
end if;
end if;
vmsto.r_ready := tloi.d_ready;
when others =>
end case;
if r.rstate = reading then
if r.rd_xact_id = msti.r_id(2 downto 0) then
vtlio.d_valid := msti.r_valid;
else
vtlio.d_valid := '0';
end if;
vtlio.d_size := "0110";
vtlio.d_addr_lo := r.rd_addr(5 downto 3);--!! depends on AXI_DATA_WIDTH
vtlio.d_source := r.rd_xact_id;
--vtlio.grant_bits_g_type := r.rd_g_type;
vtlio.d_data := msti.r_data;
elsif r.wstate = writting then
vtlio.d_valid := msti.w_ready;
vtlio.d_addr_lo := r.wr_addr(5 downto 3);--!! depends on AXI_DATA_WIDTH
vtlio.d_source := r.wr_xact_id;
--vtlio.grant_bits_g_type := r.wr_g_type;
--vtlio.grant_bits_data := (others => '0');
end if;
rin <= v;
tlio <= vtlio;
msto <= vmsto;
end process;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.rstate <= rwait_acq;
r.wstate <= wwait_acq;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | a1685ae6413510448c1c63e919b0d62e | 0.517447 | 3.275587 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/work/tb/ethphy_sim.vhd | 1 | 13,437 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
use commonlib.types_util.all;
entity ethphy_sim is
generic (
OUTPUT_ENA : std_logic := '1'
);
port (
rst : in std_logic;
clk : in std_logic;
o_rxd : out std_logic_vector(3 downto 0);
o_rxdv : out std_logic
);
end;
architecture ethphy_sim_rtl of ethphy_sim is
type crc32type is array (0 to 255)
of std_logic_vector(31 downto 0);
constant crc32_table : crc32type := (
X"00000000", X"77073096", X"ee0e612c", X"990951ba", X"076dc419", X"706af48f", X"e963a535", X"9e6495a3",
X"0edb8832", X"79dcb8a4", X"e0d5e91e", X"97d2d988", X"09b64c2b", X"7eb17cbd", X"e7b82d07", X"90bf1d91",
X"1db71064", X"6ab020f2", X"f3b97148", X"84be41de", X"1adad47d", X"6ddde4eb", X"f4d4b551", X"83d385c7",
X"136c9856", X"646ba8c0", X"fd62f97a", X"8a65c9ec", X"14015c4f", X"63066cd9", X"fa0f3d63", X"8d080df5",
X"3b6e20c8", X"4c69105e", X"d56041e4", X"a2677172", X"3c03e4d1", X"4b04d447", X"d20d85fd", X"a50ab56b",
X"35b5a8fa", X"42b2986c", X"dbbbc9d6", X"acbcf940", X"32d86ce3", X"45df5c75", X"dcd60dcf", X"abd13d59",
X"26d930ac", X"51de003a", X"c8d75180", X"bfd06116", X"21b4f4b5", X"56b3c423", X"cfba9599", X"b8bda50f",
X"2802b89e", X"5f058808", X"c60cd9b2", X"b10be924", X"2f6f7c87", X"58684c11", X"c1611dab", X"b6662d3d",
X"76dc4190", X"01db7106", X"98d220bc", X"efd5102a", X"71b18589", X"06b6b51f", X"9fbfe4a5", X"e8b8d433",
X"7807c9a2", X"0f00f934", X"9609a88e", X"e10e9818", X"7f6a0dbb", X"086d3d2d", X"91646c97", X"e6635c01",
X"6b6b51f4", X"1c6c6162", X"856530d8", X"f262004e", X"6c0695ed", X"1b01a57b", X"8208f4c1", X"f50fc457",
X"65b0d9c6", X"12b7e950", X"8bbeb8ea", X"fcb9887c", X"62dd1ddf", X"15da2d49", X"8cd37cf3", X"fbd44c65",
X"4db26158", X"3ab551ce", X"a3bc0074", X"d4bb30e2", X"4adfa541", X"3dd895d7", X"a4d1c46d", X"d3d6f4fb",
X"4369e96a", X"346ed9fc", X"ad678846", X"da60b8d0", X"44042d73", X"33031de5", X"aa0a4c5f", X"dd0d7cc9",
X"5005713c", X"270241aa", X"be0b1010", X"c90c2086", X"5768b525", X"206f85b3", X"b966d409", X"ce61e49f",
X"5edef90e", X"29d9c998", X"b0d09822", X"c7d7a8b4", X"59b33d17", X"2eb40d81", X"b7bd5c3b", X"c0ba6cad",
X"edb88320", X"9abfb3b6", X"03b6e20c", X"74b1d29a", X"ead54739", X"9dd277af", X"04db2615", X"73dc1683",
X"e3630b12", X"94643b84", X"0d6d6a3e", X"7a6a5aa8", X"e40ecf0b", X"9309ff9d", X"0a00ae27", X"7d079eb1",
X"f00f9344", X"8708a3d2", X"1e01f268", X"6906c2fe", X"f762575d", X"806567cb", X"196c3671", X"6e6b06e7",
X"fed41b76", X"89d32be0", X"10da7a5a", X"67dd4acc", X"f9b9df6f", X"8ebeeff9", X"17b7be43", X"60b08ed5",
X"d6d6a3e8", X"a1d1937e", X"38d8c2c4", X"4fdff252", X"d1bb67f1", X"a6bc5767", X"3fb506dd", X"48b2364b",
X"d80d2bda", X"af0a1b4c", X"36034af6", X"41047a60", X"df60efc3", X"a867df55", X"316e8eef", X"4669be79",
X"cb61b38c", X"bc66831a", X"256fd2a0", X"5268e236", X"cc0c7795", X"bb0b4703", X"220216b9", X"5505262f",
X"c5ba3bbe", X"b2bd0b28", X"2bb45a92", X"5cb36a04", X"c2d7ffa7", X"b5d0cf31", X"2cd99e8b", X"5bdeae1d",
X"9b64c2b0", X"ec63f226", X"756aa39c", X"026d930a", X"9c0906a9", X"eb0e363f", X"72076785", X"05005713",
X"95bf4a82", X"e2b87a14", X"7bb12bae", X"0cb61b38", X"92d28e9b", X"e5d5be0d", X"7cdcefb7", X"0bdbdf21",
X"86d3d2d4", X"f1d4e242", X"68ddb3f8", X"1fda836e", X"81be16cd", X"f6b9265b", X"6fb077e1", X"18b74777",
X"88085ae6", X"ff0f6a70", X"66063bca", X"11010b5c", X"8f659eff", X"f862ae69", X"616bffd3", X"166ccf45",
X"a00ae278", X"d70dd2ee", X"4e048354", X"3903b3c2", X"a7672661", X"d06016f7", X"4969474d", X"3e6e77db",
X"aed16a4a", X"d9d65adc", X"40df0b66", X"37d83bf0", X"a9bcae53", X"debb9ec5", X"47b2cf7f", X"30b5ffe9",
X"bdbdf21c", X"cabac28a", X"53b39330", X"24b4a3a6", X"bad03605", X"cdd70693", X"54de5729", X"23d967bf",
X"b3667a2e", X"c4614ab8", X"5d681b02", X"2a6f2b94", X"b40bbe37", X"c30c8ea1", X"5a05df1b", X"2d02ef8d");
--constant EDCL0 : std_logic_vector(455 downto 0) :=
--X"5d207098001032badcacefebeb800000e100450000000029bd11000c8a00a00c8a00f07788556600a02266000000002300010020009ac7c2dc";
-- edcl_idx=6, read 0x80090000, 1 word (4 bytes)
constant EDCL0 : std_logic_vector(455 downto 0) :=
X"5d207098001032badcacefebeb800000e100450000000029bd11000c8a00a00c8a00f07788556600a04e44000000812000089000002ea59ac7";
function gen_msg(edcl_idx : in integer) return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable idx : integer;
variable wb_edcl_idx : std_logic_vector(15 downto 0);
variable checksum : std_logic_vector(31 downto 0);
variable byte : std_logic_vector(7 downto 0);
variable ret : std_logic_vector(455 downto 0);
begin
ret := EDCL0;
wb_edcl_idx := conv_std_logic_vector(edcl_idx, 14) & "00";
ret(95 downto 80) := wb_edcl_idx(11 downto 8) & wb_edcl_idx(15 downto 12)
& wb_edcl_idx(3 downto 0) & wb_edcl_idx(7 downto 4);
checksum(31 downto 16) := (others => '0');
checksum(15 downto 0) := EDCL0(123 downto 120) & EDCL0(127 downto 124)
& EDCL0(115 downto 112) & EDCL0(119 downto 116);
-- [6] checksum 0x2266 => 0x224e
-- crc = 0xa542c092
-- 5d207098001032badcacefebeb800000e100450000000029bd11000c8a00a00c8a00f07788556600a022e400000081230001002000290c245a
checksum := checksum - (conv_std_logic_vector(edcl_idx, 30) & "00");
if checksum(31) = '1' then
checksum(15 downto 0) := checksum(15 downto 0) + checksum(31 downto 16);
end if;
ret(127 downto 112) := checksum(11 downto 8) & checksum(15 downto 12)
& checksum(3 downto 0) & checksum(7 downto 4);
crc := (others => '1');
for i in 0 to 51 loop
byte := ret(443-8*i downto 440-8*i) & ret(447-8*i downto 444-8*i);
idx := conv_integer(crc(7 downto 0) xor byte);
crc := (X"00" & crc(31 downto 8)) xor crc32_table(idx);
end loop;
crc := not crc;
ret(7 downto 0) := crc(27 downto 24) & crc(31 downto 28);
ret(15 downto 8) := crc(19 downto 16) & crc(23 downto 20);
ret(23 downto 16) := crc(11 downto 8) & crc(15 downto 12);
ret(31 downto 24) := crc(3 downto 0) & crc(7 downto 4);
return ret;
end function;
-- Use '20150601_riscv' project to generate network nibbles in string format:
-- Open grethaxi.cpp (line 855)
-- Use methods sendEdclRead/sendEdclWrite and generate_tb_string.
-- Message 1: Read npc register from debug port of RIVER CPU:
-- edcl index = 0
-- address = 0x80088000 | (33 << 3) = 0x80088108
-- size = 2 x word32 = 8 bytes
constant EDCL_MSG1_START : integer := 1000;
constant EDCL_MSG1_LEN : integer := 114;
constant EDCL_MSG1 : std_logic_vector(EDCL_MSG1_LEN*4-1 downto 0) :=
X"5d207098001032badcacefebeb800000e100450000000029bd11000c8a00a00c8a00f07788556600a01655000000004000088018802a32c544";
-- Message 2: Write CSR register mtimecmp to debug port of RIVER CPU:
-- edcl index = 1
-- address = 0x8008000 | (321 << 3)
-- size = 8 bytes
-- wdata = 0x8877665544332211
constant EDCL_MSG2_START : integer := 2000;
constant EDCL_MSG2_LEN : integer := 130;
constant EDCL_MSG2 : std_logic_vector(EDCL_MSG2_LEN*4-1 downto 0) :=
X"5d207098001032badcacefebeb80000062004500000000293e11000c8a00a00c8a00f07788556600217baf000000604000088091801122334455667788ec10d362";
-- Message 3: Read 32 x words32 from ROM (romimage):
-- edcl index = 2
-- address = 0x00100000
-- size = 32 x word32 = 256 bytes
constant EDCL_MSG3_START : integer := 3000;
constant EDCL_MSG3_LEN : integer := 114;
constant EDCL_MSG3 : std_logic_vector(EDCL_MSG3_LEN*4-1 downto 0) :=
X"5d207098001032badcacefebeb800000e100450000000029bd11000c8a00a00c8a00f07788556600a062e40000008004000001000048d5979f";
-- Message 4: Read 20 x words32 from SRAM:
-- edcl index = 3
-- address = 0x10001450
-- size = 20 x word32 = 80 bytes
constant EDCL_MSG4_START : integer := 4000;
constant EDCL_MSG4_LEN : integer := 114;
constant EDCL_MSG4 : std_logic_vector(EDCL_MSG4_LEN*4-1 downto 0) :=
X"5d207098001032badcacefebeb800000e100450000000029bd11000c8a00a00c8a00f07788556600a0a1a0000000c082000100410560799d79";
-- Message 5: Read 10 x words32 from SRAM:
-- edcl index = 4
-- address = 0x10001D60
-- size = 10 x word32 = 40 bytes
constant EDCL_MSG5_START : integer := 5000-22;
constant EDCL_MSG5_LEN : integer := 114;
constant EDCL_MSG5 : std_logic_vector(EDCL_MSG5_LEN*4-1 downto 0) :=
X"5d207098001032badcacefebeb800000e100450000000029bd11000c8a00a00c8a00f07788556600a0426f0000000141000100d106e3d35cdc";
-- Message 6: Write 8 x 64-bits (64 bytes) into SRAM:
-- edcl index = 5
-- address = 0x10030d40
-- uint64_t wdata6[8] = {0x2222222211111111ull", 0x4444444433333333ull", 0x6666666655555555ull", 0x8888888877777777ull,
-- 0xaaaaaaaa99999999ull", 0xccccccccbbbbbbbbull", 0xffffffffeeeeeeeeull", 0xcafecafebeefbeefull};
-- size = 64 bytes
constant EDCL_MSG6_START : integer := 6000;
constant EDCL_MSG6_LEN : integer := 242;
constant EDCL_MSG6 : std_logic_vector(EDCL_MSG6_LEN*4-1 downto 0) :=
X"5d207098001032badcacefebeb800000e500450000000039b111000c8a00a00c8a00f07788556600a4705b0000006102000130d004111111112222222233333333444444445555555566666666777777778888888899999999aaaaaaaabbbbbbbbcccccccceeeeeeeefffffffffeebfeebefacefacc3875a17";
type registers is record
clk_cnt : integer;
edcl_idx : integer;
msg_len : integer;
msg_cnt : integer;
msg : std_logic_vector(455 downto 0);
end record;
signal r, rin : registers;
begin
comblogic : process(rst, r)
variable v : registers;
variable rxd : std_logic_vector(3 downto 0);
variable rxdv : std_logic;
variable ibit : integer;
variable wb_clk_cnt : std_logic_vector(31 downto 0);
begin
v := r;
rxd := "0000";
rxdv := '0';
v.clk_cnt := r.clk_cnt + 1;
if r.clk_cnt >= 10000 then
wb_clk_cnt := conv_std_logic_vector(r.clk_cnt, 32);
if wb_clk_cnt(9 downto 0) = "0000000000" then
v.msg := gen_msg(r.edcl_idx);
v.edcl_idx := r.edcl_idx + 1;
v.msg_len := 114;
v.msg_cnt := 0;
end if;
end if;
if r.clk_cnt >= EDCL_MSG1_START and r.clk_cnt < (EDCL_MSG1_START + EDCL_MSG1_LEN) then
ibit := r.clk_cnt - EDCL_MSG1_START;
rxd := EDCL_MSG1(4*(EDCL_MSG1_LEN - ibit)-1 downto 4*(EDCL_MSG1_LEN - ibit)-4);
rxdv := OUTPUT_ENA;
elsif r.clk_cnt >= EDCL_MSG2_START and r.clk_cnt < (EDCL_MSG2_START + EDCL_MSG2_LEN) then
ibit := r.clk_cnt - EDCL_MSG2_START;
rxd := EDCL_MSG2(4*(EDCL_MSG2_LEN - ibit)-1 downto 4*(EDCL_MSG2_LEN - ibit)-4);
rxdv := OUTPUT_ENA;
elsif r.clk_cnt >= EDCL_MSG3_START and r.clk_cnt < (EDCL_MSG3_START + EDCL_MSG3_LEN) then
ibit := r.clk_cnt - EDCL_MSG3_START;
rxd := EDCL_MSG3(4*(EDCL_MSG3_LEN - ibit)-1 downto 4*(EDCL_MSG3_LEN - ibit)-4);
rxdv := OUTPUT_ENA;
elsif r.clk_cnt >= EDCL_MSG4_START and r.clk_cnt < (EDCL_MSG4_START + EDCL_MSG4_LEN) then
ibit := r.clk_cnt - EDCL_MSG4_START;
rxd := EDCL_MSG4(4*(EDCL_MSG4_LEN - ibit)-1 downto 4*(EDCL_MSG4_LEN - ibit)-4);
rxdv := OUTPUT_ENA;
elsif r.clk_cnt >= EDCL_MSG5_START and r.clk_cnt < (EDCL_MSG5_START + EDCL_MSG5_LEN) then
ibit := r.clk_cnt - EDCL_MSG5_START;
rxd := EDCL_MSG5(4*(EDCL_MSG5_LEN - ibit)-1 downto 4*(EDCL_MSG5_LEN - ibit)-4);
rxdv := OUTPUT_ENA;
elsif r.clk_cnt >= EDCL_MSG6_START and r.clk_cnt < (EDCL_MSG6_START + EDCL_MSG6_LEN) then
ibit := r.clk_cnt - EDCL_MSG6_START;
rxd := EDCL_MSG6(4*(EDCL_MSG6_LEN - ibit)-1 downto 4*(EDCL_MSG6_LEN - ibit)-4);
rxdv := OUTPUT_ENA;
elsif r.msg_cnt /= r.msg_len then
v.msg_cnt := r.msg_cnt + 1;
rxd := r.msg(4*(r.msg_len - r.msg_cnt)-1 downto 4*(r.msg_len - r.msg_cnt)-4);
rxdv := OUTPUT_ENA;
end if;
-- Reset
if rst = '1' then
v.clk_cnt := 0;
v.edcl_idx := 6;
v.msg_len := 0;
v.msg_cnt := 0;
v.msg := (others => '0');
end if;
rin <= v;
o_rxd <= rxd;
o_rxdv <= rxdv;
end process;
procCheck : process (clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | bfcfc8361d1049017d99df20952997c2 | 0.64047 | 2.594516 | false | false | false | false |
szanni/aeshw | aes-core/decryption_module.vhd | 1 | 2,274 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:21:40 07/20/2014
-- Design Name:
-- Module Name: decryption_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decryption_module is
port(
clk : in std_logic;
reset : in std_logic;
dec_start : in std_logic;
dec_end : out std_logic;
din : in state;
dout : out state;
addr_rkey : out std_logic_vector (3 downto 0);
rkey_in : in state
);
end decryption_module;
architecture Behavioral of decryption_module is
signal x_last_round : std_logic;
signal y_1_2, y_3_4 : std_logic_vector (1 downto 0);
signal addr_rkey_tmp : byte;
begin
control_unit : entity work.inv_cipher_cu port map (clk => clk,
reset => reset,
x_start => dec_start,
x_comp => x_last_round,
y_1_2 => y_1_2,
y_3_4 => y_3_4,
y_end => dec_end
);
cipher_unit : entity work.inv_cipher port map (clk => clk,
reset => reset,
y => y_1_2,
din => din,
rkey_in => rkey_in,
dout => dout
);
counter : entity work.decrementor port map (clk => clk,
reset => reset,
y => y_3_4,
d_out => addr_rkey_tmp,
x => x_last_round
);
addr_rkey <= addr_rkey_tmp(3 downto 0);
end Behavioral;
| bsd-2-clause | 5b7d033148137543498436f51ba8db69 | 0.476253 | 3.709625 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/river_cfg.vhd | 1 | 75,446 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! @brief Library global parameters.
package river_cfg is
constant CFG_VENDOR_ID : std_logic_vector(31 downto 0) := X"000000F1";
constant CFG_IMPLEMENTATION_ID : std_logic_vector(31 downto 0) := X"20200906";
constant CFG_HW_FPU_ENABLE : boolean := true;
--! Architecture size difinition.
constant RISCV_ARCH : integer := 64;
constant CFG_CPU_ADDR_BITS : integer := 32;
constant CFG_CPU_ID_BITS : integer := 1;
constant CFG_CPU_USER_BITS : integer := 1;
--
-- ICacheLru config (16 KB by default)
--
constant CFG_ILOG2_BYTES_PER_LINE : integer := 5; -- [4:0] 32 Bytes = 4x8 B log2(Bytes per line)
constant CFG_ILOG2_LINES_PER_WAY : integer := 7;
constant CFG_ILOG2_NWAYS : integer := 2;
-- Derivatives I$ constants:
constant ICACHE_BYTES_PER_LINE : integer := 2**CFG_ILOG2_BYTES_PER_LINE;
constant ICACHE_LINES_PER_WAY : integer := 2**CFG_ILOG2_LINES_PER_WAY;
constant ICACHE_WAYS : integer := 2**CFG_ILOG2_NWAYS;
constant ICACHE_LINE_BITS : integer := 8*ICACHE_BYTES_PER_LINE;
-- Information: To define the CACHE SIZE in Bytes use the following:
constant ICACHE_SIZE_BYTES : integer :=
ICACHE_WAYS * ICACHE_LINES_PER_WAY * ICACHE_BYTES_PER_LINE;
constant ITAG_FL_TOTAL : integer := 1;
--
-- DCacheLru config (16 KB by default)
--
constant CFG_DLOG2_BYTES_PER_LINE : integer := 5; -- [4:0] 32 Bytes = 4x8 B log2(Bytes per line)
constant CFG_DLOG2_LINES_PER_WAY : integer := 7;
constant CFG_DLOG2_NWAYS : integer := 2;
-- Derivatives D$ constants:
constant DCACHE_BYTES_PER_LINE : integer := 2**CFG_DLOG2_BYTES_PER_LINE;
constant DCACHE_LINES_PER_WAY : integer := 2**CFG_DLOG2_LINES_PER_WAY;
constant DCACHE_WAYS : integer := 2**CFG_DLOG2_NWAYS;
constant DCACHE_LINE_BITS : integer := 8*DCACHE_BYTES_PER_LINE;
-- Information: To define the CACHE SIZE in Bytes use the following:
constant DCACHE_SIZE_BYTES : integer :=
DCACHE_WAYS * DCACHE_LINES_PER_WAY * DCACHE_BYTES_PER_LINE;
constant TAG_FL_VALID : integer := 0; -- always 0
constant DTAG_FL_DIRTY : integer := 1;
constant DTAG_FL_SHARED : integer := 2;
constant DTAG_FL_TOTAL : integer := 3;
-- L1 cache common parameters (suppose I$ and D$ have the same size)
constant L1CACHE_BYTES_PER_LINE : integer := DCACHE_BYTES_PER_LINE;
constant L1CACHE_LINE_BITS : integer := 8*DCACHE_BYTES_PER_LINE;
constant REQ_MEM_TYPE_WRITE : integer := 0;
constant REQ_MEM_TYPE_CACHED : integer := 1;
constant REQ_MEM_TYPE_UNIQUE : integer := 2;
constant REQ_MEM_TYPE_BITS : integer := 3;
constant SNOOP_REQ_TYPE_READDATA : integer := 0; -- 0=check flags; 1=data transfer
constant SNOOP_REQ_TYPE_READCLEAN : integer := 1; -- 0=do nothing; 1=read and invalidate line
constant SNOOP_REQ_TYPE_BITS : integer := 2;
function ReadNoSnoop return std_logic_vector;
function ReadShared return std_logic_vector;
function ReadMakeUnique return std_logic_vector;
function WriteNoSnoop return std_logic_vector;
function WriteLineUnique return std_logic_vector;
function WriteBack return std_logic_vector;
-- MPU config:
constant CFG_MPU_TBL_WIDTH : integer := 2; -- [1:0] log2(MPU_TBL_SIZE)
constant CFG_MPU_TBL_SIZE : integer := 2**CFG_MPU_TBL_WIDTH;
constant CFG_MPU_FL_WR : integer := 0;
constant CFG_MPU_FL_RD : integer := 1;
constant CFG_MPU_FL_EXEC : integer := 2;
constant CFG_MPU_FL_CACHABLE : integer := 3;
constant CFG_MPU_FL_ENA : integer := 4;
constant CFG_MPU_FL_TOTAL : integer := 5;
--! @name Encoded Memory operation size values
--! @{
constant MEMOP_8B : std_logic_vector(1 downto 0) := "11";
constant MEMOP_4B : std_logic_vector(1 downto 0) := "10";
constant MEMOP_2B : std_logic_vector(1 downto 0) := "01";
constant MEMOP_1B : std_logic_vector(1 downto 0) := "00";
--! @}
--! Non-maskable interrupts (exceptions) table.
--! It can be freely changed to optimize memory consumption/performance
--!
constant CFG_NMI_RESET_VECTOR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000000";
constant CFG_NMI_INSTR_UNALIGNED_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000008";
constant CFG_NMI_INSTR_FAULT_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000010";
constant CFG_NMI_INSTR_ILLEGAL_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000018";
constant CFG_NMI_BREAKPOINT_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000020";
constant CFG_NMI_LOAD_UNALIGNED_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000028";
constant CFG_NMI_LOAD_FAULT_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000030";
constant CFG_NMI_STORE_UNALIGNED_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000038";
constant CFG_NMI_STORE_FAULT_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000040";
constant CFG_NMI_CALL_FROM_UMODE_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000048";
constant CFG_NMI_CALL_FROM_SMODE_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000050";
constant CFG_NMI_CALL_FROM_HMODE_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000058";
constant CFG_NMI_CALL_FROM_MMODE_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000060";
constant CFG_NMI_INSTR_PAGE_FAULT_ADDR: std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000068";
constant CFG_NMI_LOAD_PAGE_FAULT_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000070";
constant CFG_NMI_STORE_PAGE_FAULT_ADDR: std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000078";
constant CFG_NMI_STACK_OVERFLOW_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000080";
constant CFG_NMI_STACK_UNDERFLOW_ADDR : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0) := X"00000088";
--! Debug interface configuration:
constant CFG_DPORT_ADDR_BITS : integer := 16;
-- Valid size 0..16
constant CFG_PROGBUF_REG_TOTAL : integer := 16;
-- Must be at least 2 to support RV64I
constant CFG_DATA_REG_TOTAL : integer := 2;
--! Number of elements each 2*CFG_ADDR_WIDTH in stack trace buffer, 0 = disabled
constant CFG_LOG2_STACK_TRACE_ADDR : integer := 5;
constant STACK_TRACE_BUF_SIZE : integer := 2**CFG_LOG2_STACK_TRACE_ADDR;
--! @name Integer Registers specified by ISA
--! @{
constant Reg_Zero : integer := 0;
constant Reg_ra : integer := 1; -- [1] Return address
constant Reg_sp : integer := 2; -- [2] Stack pointer
constant Reg_gp : integer := 3; -- [3] Global pointer
constant Reg_tp : integer := 4; -- [4] Thread pointer
constant Reg_t0 : integer := 5; -- [5] Temporaries 0 s3
constant Reg_t1 : integer := 6; -- [6] Temporaries 1 s4
constant Reg_t2 : integer := 7; -- [7] Temporaries 2 s5
constant Reg_s0 : integer := 8; -- [8] s0/fp Saved register/frame pointer
constant Reg_s1 : integer := 9; -- [9] Saved register 1
constant Reg_a0 : integer := 10; -- [10] Function argumentes 0
constant Reg_a1 : integer := 11; -- [11] Function argumentes 1
constant Reg_a2 : integer := 12; -- [12] Function argumentes 2
constant Reg_a3 : integer := 13; -- [13] Function argumentes 3
constant Reg_a4 : integer := 14; -- [14] Function argumentes 4
constant Reg_a5 : integer := 15; -- [15] Function argumentes 5
constant Reg_a6 : integer := 16; -- [16] Function argumentes 6
constant Reg_a7 : integer := 17; -- [17] Function argumentes 7
constant Reg_s2 : integer := 18; -- [18] Saved register 2
constant Reg_s3 : integer := 19; -- [19] Saved register 3
constant Reg_s4 : integer := 20; -- [20] Saved register 4
constant Reg_s5 : integer := 21; -- [21] Saved register 5
constant Reg_s6 : integer := 22; -- [22] Saved register 6
constant Reg_s7 : integer := 23; -- [23] Saved register 7
constant Reg_s8 : integer := 24; -- [24] Saved register 8
constant Reg_s9 : integer := 25; -- [25] Saved register 9
constant Reg_s10 : integer := 26; -- [26] Saved register 10
constant Reg_s11 : integer := 27; -- [27] Saved register 11
constant Reg_t3 : integer := 28; -- [28]
constant Reg_t4 : integer := 29; -- [29]
constant Reg_t5 : integer := 30; -- [30]
constant Reg_t6 : integer := 31; -- [31]
constant Reg_Total : integer := 32;
--! @}
--! @name Floating Point Unit Registers specified by ISA
--! @{
constant Reg_f0 : integer := 0; -- ft0 temporary register
constant Reg_f1 : integer := 1; -- ft1
constant Reg_f2 : integer := 2; -- ft2
constant Reg_f3 : integer := 3; -- ft3
constant Reg_f4 : integer := 4; -- ft4
constant Reg_f5 : integer := 5; -- ft5
constant Reg_f6 : integer := 6; -- ft6
constant Reg_f7 : integer := 7; -- ft7
constant Reg_f8 : integer := 8; -- fs0 saved register
constant Reg_f9 : integer := 9; -- fs1
constant Reg_f10 : integer := 10; -- fa0 argument/return value
constant Reg_f11 : integer := 11; -- fa1 argument/return value
constant Reg_f12 : integer := 12; -- fa2 argument register
constant Reg_f13 : integer := 13; -- fa3
constant Reg_f14 : integer := 14; -- fa4
constant Reg_f15 : integer := 15; -- fa5
constant Reg_f16 : integer := 16; -- fa6
constant Reg_f17 : integer := 17; -- fa7
constant Reg_f18 : integer := 18; -- fs2 saved register
constant Reg_f19 : integer := 19; -- fs3
constant Reg_f20 : integer := 20; -- fs4
constant Reg_f21 : integer := 21; -- fs5
constant Reg_f22 : integer := 22; -- fs6
constant Reg_f23 : integer := 23; -- fs7
constant Reg_f24 : integer := 24; -- fs8
constant Reg_f25 : integer := 25; -- fs9
constant Reg_f26 : integer := 26; -- fs10
constant Reg_f27 : integer := 27; -- fs11
constant Reg_f28 : integer := 28; -- ft8 temporary register
constant Reg_f29 : integer := 29; -- ft9
constant Reg_f30 : integer := 30; -- ft10
constant Reg_f31 : integer := 31; -- ft11
constant RegFpu_Total : integer := 32;
--! @}
--! @name Instruction formats specified by ISA specification
--! @{
constant ISA_R_type : integer := 0;
constant ISA_I_type : integer := 1;
constant ISA_S_type : integer := 2;
constant ISA_SB_type : integer := 3;
constant ISA_U_type : integer := 4;
constant ISA_UJ_type : integer := 5;
constant ISA_Total : integer := 6;
--! @}
--! @name Implemented instruction list and its indexes
--! @{
constant Instr_ADD : integer := 0;
constant Instr_ADDI : integer := 1;
constant Instr_ADDIW : integer := 2;
constant Instr_ADDW : integer := 3;
constant Instr_AND : integer := 4;
constant Instr_ANDI : integer := 5;
constant Instr_AUIPC : integer := 6;
constant Instr_BEQ : integer := 7;
constant Instr_BGE : integer := 8;
constant Instr_BGEU : integer := 9;
constant Instr_BLT : integer := 10;
constant Instr_BLTU : integer := 11;
constant Instr_BNE : integer := 12;
constant Instr_JAL : integer := 13;
constant Instr_JALR : integer := 14;
constant Instr_LB : integer := 15;
constant Instr_LH : integer := 16;
constant Instr_LW : integer := 17;
constant Instr_LD : integer := 18;
constant Instr_LBU : integer := 19;
constant Instr_LHU : integer := 20;
constant Instr_LWU : integer := 21;
constant Instr_LUI : integer := 22;
constant Instr_OR : integer := 23;
constant Instr_ORI : integer := 24;
constant Instr_SLLI : integer := 25;
constant Instr_SLT : integer := 26;
constant Instr_SLTI : integer := 27;
constant Instr_SLTU : integer := 28;
constant Instr_SLTIU : integer := 29;
constant Instr_SLL : integer := 30;
constant Instr_SLLW : integer := 31;
constant Instr_SLLIW : integer := 32;
constant Instr_SRA : integer := 33;
constant Instr_SRAW : integer := 34;
constant Instr_SRAI : integer := 35;
constant Instr_SRAIW : integer := 36;
constant Instr_SRL : integer := 37;
constant Instr_SRLI : integer := 38;
constant Instr_SRLIW : integer := 39;
constant Instr_SRLW : integer := 40;
constant Instr_SB : integer := 41;
constant Instr_SH : integer := 42;
constant Instr_SW : integer := 43;
constant Instr_SD : integer := 44;
constant Instr_SUB : integer := 45;
constant Instr_SUBW : integer := 46;
constant Instr_XOR : integer := 47;
constant Instr_XORI : integer := 48;
constant Instr_CSRRW : integer := 49;
constant Instr_CSRRS : integer := 50;
constant Instr_CSRRC : integer := 51;
constant Instr_CSRRWI : integer := 52;
constant Instr_CSRRCI : integer := 53;
constant Instr_CSRRSI : integer := 54;
constant Instr_URET : integer := 55;
constant Instr_SRET : integer := 56;
constant Instr_HRET : integer := 57;
constant Instr_MRET : integer := 58;
constant Instr_FENCE : integer := 59;
constant Instr_FENCE_I : integer := 60;
constant Instr_DIV : integer := 61;
constant Instr_DIVU : integer := 62;
constant Instr_DIVW : integer := 63;
constant Instr_DIVUW : integer := 64;
constant Instr_MUL : integer := 65;
constant Instr_MULW : integer := 66;
constant Instr_MULH : integer := 67;
constant Instr_MULHSU : integer := 68;
constant Instr_MULHU : integer := 69;
constant Instr_REM : integer := 70;
constant Instr_REMU : integer := 71;
constant Instr_REMW : integer := 72;
constant Instr_REMUW : integer := 73;
constant Instr_ECALL : integer := 74;
constant Instr_EBREAK : integer := 75;
constant Instr_FADD_D : integer := 76;
constant Instr_FCVT_D_W : integer := 77;
constant Instr_FCVT_D_WU : integer := 78;
constant Instr_FCVT_D_L : integer := 79;
constant Instr_FCVT_D_LU : integer := 80;
constant Instr_FCVT_W_D : integer := 81;
constant Instr_FCVT_WU_D : integer := 82;
constant Instr_FCVT_L_D : integer := 83;
constant Instr_FCVT_LU_D : integer := 84;
constant Instr_FDIV_D : integer := 85;
constant Instr_FEQ_D : integer := 86;
constant Instr_FLD : integer := 87;
constant Instr_FLE_D : integer := 88;
constant Instr_FLT_D : integer := 89;
constant Instr_FMAX_D : integer := 90;
constant Instr_FMIN_D : integer := 91;
constant Instr_FMOV_D_X : integer := 92;
constant Instr_FMOV_X_D : integer := 93;
constant Instr_FMUL_D : integer := 94;
constant Instr_FSD : integer := 95;
constant Instr_FSUB_D : integer := 96;
constant Instr_Total : integer := 97;
constant Instr_FPU_Total : integer := Instr_FSUB_D - Instr_FADD_D + 1;
--! @}
--! @name PRV bits possible values:
--!
--! @{
--! User-mode
constant PRV_U : std_logic_vector(1 downto 0) := "00";
--! super-visor mode
constant PRV_S : std_logic_vector(1 downto 0) := "01";
--! hyper-visor mode
constant PRV_H : std_logic_vector(1 downto 0) := "10";
--! machine mode
constant PRV_M : std_logic_vector(1 downto 0) := "11";
--! @}
--! @name CSR registers.
--!
--! @{
-- FPU Accrued Exceptions fields from FCSR
constant CSR_fflags : std_logic_vector(11 downto 0) := X"001";
-- FPU dynamic Rounding Mode fields from FCSR
constant CSR_frm : std_logic_vector(11 downto 0) := X"002";
-- FPU Control and Status register (frm + fflags)
constant CSR_fcsr : std_logic_vector(11 downto 0) := X"003";
-- machine mode status read/write register.
constant CSR_mstatus : std_logic_vector(11 downto 0) := X"300";
-- ISA and extensions supported.
constant CSR_misa : std_logic_vector(11 downto 0) := X"301";
-- Machine exception delegation
constant CSR_medeleg : std_logic_vector(11 downto 0) := X"302";
-- Machine interrupt delegation
constant CSR_mideleg : std_logic_vector(11 downto 0) := X"303";
-- Machine interrupt enable
constant CSR_mie : std_logic_vector(11 downto 0) := X"304";
-- The base address of the M-mode trap vector.
constant CSR_mtvec : std_logic_vector(11 downto 0) := X"305";
-- Scratch register for machine trap handlers.
constant CSR_mscratch : std_logic_vector(11 downto 0) := X"340";
-- Exception program counters.
constant CSR_uepc : std_logic_vector(11 downto 0) := X"041";
constant CSR_sepc : std_logic_vector(11 downto 0) := X"141";
constant CSR_hepc : std_logic_vector(11 downto 0) := X"241";
constant CSR_mepc : std_logic_vector(11 downto 0) := X"341";
-- Machine trap cause
constant CSR_mcause : std_logic_vector(11 downto 0) := X"342";
-- Machine bad address.
constant CSR_mbadaddr : std_logic_vector(11 downto 0) := X"343";
-- Machine interrupt pending
constant CSR_mip : std_logic_vector(11 downto 0) := X"344";
-- Machine stack overflow
constant CSR_mstackovr : std_logic_vector(11 downto 0) := X"350";
-- Machine stack underflow
constant CSR_mstackund : std_logic_vector(11 downto 0) := X"351";
-- MPU region address (non-standard CSR).
constant CSR_mpu_addr : std_logic_vector(11 downto 0) := X"352";
-- MPU region mask (non-standard CSR).
constant CSR_mpu_mask : std_logic_vector(11 downto 0) := X"353";
-- MPU region control (non-standard CSR).
constant CSR_mpu_ctrl : std_logic_vector(11 downto 0) := X"354";
-- Halt/resume requests handling
constant CSR_runcontrol : std_logic_vector(11 downto 0) := X"355";
-- Instruction per single step
constant CSR_insperstep : std_logic_vector(11 downto 0) := X"356";
-- Write value into progbuf
constant CSR_progbuf : std_logic_vector(11 downto 0) := X"357";
-- Abstract commmand control status (ABSTRACTCS)
constant CSR_abstractcs : std_logic_vector(11 downto 0) := X"358";
-- Flush specified address in I-cache module without execution of fence.i
constant CSR_flushi : std_logic_vector(11 downto 0) := X"359";
-- Software reset.
constant CSR_mreset : std_logic_vector(11 downto 0) := X"782";
-- Debug Control and status
constant CSR_dcsr : std_logic_vector(11 downto 0) := X"7b0";
-- Debug PC
constant CSR_dpc : std_logic_vector(11 downto 0) := X"7b1";
-- Debug Scratch Register 0
constant CSR_dscratch0 : std_logic_vector(11 downto 0) := X"7b2";
-- Debug Scratch Register 1
constant CSR_dscratch1 : std_logic_vector(11 downto 0) := X"7b3";
-- Machine Cycle counter
constant CSR_mcycle : std_logic_vector(11 downto 0) := X"B00";
-- Machine Instructions-retired counter
constant CSR_minsret : std_logic_vector(11 downto 0) := X"B02";
-- User Cycle counter for RDCYCLE pseudo-instruction
constant CSR_cycle : std_logic_vector(11 downto 0) := X"C00";
-- User Timer for RDTIME pseudo-instruction
constant CSR_time : std_logic_vector(11 downto 0) := X"C01";
-- User Instructions-retired counter for RDINSTRET pseudo-instruction
constant CSR_insret : std_logic_vector(11 downto 0) := X"C02";
-- 0xC00 to 0xC1F reserved for counters
-- Vendor ID.
constant CSR_mvendorid : std_logic_vector(11 downto 0) := X"f11";
-- Architecture ID.
constant CSR_marchid : std_logic_vector(11 downto 0) := X"f12";
-- Vendor ID.
constant CSR_mimplementationid : std_logic_vector(11 downto 0) := X"f13";
-- Thread id (the same as core).
constant CSR_mhartid : std_logic_vector(11 downto 0) := X"f14";
--! @}
--! @name Exceptions
--! @{
-- Instruction address misaligned
constant EXCEPTION_InstrMisalign : std_logic_vector(4 downto 0) := "00000";
-- Instruction access fault
constant EXCEPTION_InstrFault : std_logic_vector(4 downto 0) := "00001";
-- Illegal instruction
constant EXCEPTION_InstrIllegal : std_logic_vector(4 downto 0) := "00010";
-- Breakpoint
constant EXCEPTION_Breakpoint : std_logic_vector(4 downto 0) := "00011";
-- Load address misaligned
constant EXCEPTION_LoadMisalign : std_logic_vector(4 downto 0) := "00100";
-- Load access fault
constant EXCEPTION_LoadFault : std_logic_vector(4 downto 0) := "00101";
-- Store/AMO address misaligned
constant EXCEPTION_StoreMisalign : std_logic_vector(4 downto 0) := "00110";
-- Store/AMO access fault
constant EXCEPTION_StoreFault : std_logic_vector(4 downto 0) := "00111";
-- Environment call from U-mode
constant EXCEPTION_CallFromUmode : std_logic_vector(4 downto 0) := "01000";
-- Environment call from S-mode
constant EXCEPTION_CallFromSmode : std_logic_vector(4 downto 0) := "01001";
-- Environment call from H-mode
constant EXCEPTION_CallFromHmode : std_logic_vector(4 downto 0) := "01010";
-- Environment call from M-mode
constant EXCEPTION_CallFromMmode : std_logic_vector(4 downto 0) := "01011";
-- Instruction page fault
constant EXCEPTION_InstrPageFault : std_logic_vector(4 downto 0) := "01100";
-- Load page fault
constant EXCEPTION_LoadPageFault : std_logic_vector(4 downto 0) := "01101";
-- reserved
constant EXCEPTION_rsrv14 : std_logic_vector(4 downto 0) := "01110";
-- Store/AMO page fault
constant EXCEPTION_StorePageFault : std_logic_vector(4 downto 0) := "01111";
-- Stack overflow
constant EXCEPTION_StackOverflow : std_logic_vector(4 downto 0) := "10000";
-- Stack underflow
constant EXCEPTION_StackUnderflow : std_logic_vector(4 downto 0) := "10001";
--! @}
--! @name Interrupts
--! @{
-- User software interrupt
constant INTERRUPT_USoftware : std_logic_vector(4 downto 0) := "00000";
-- Superuser software interrupt
constant INTERRUPT_SSoftware : std_logic_vector(4 downto 0) := "00001";
-- Hypervisor software itnerrupt
constant INTERRUPT_HSoftware : std_logic_vector(4 downto 0) := "00010";
-- Machine software interrupt
constant INTERRUPT_MSoftware : std_logic_vector(4 downto 0) := "00011";
-- User timer interrupt
constant INTERRUPT_UTimer : std_logic_vector(4 downto 0) := "00100";
-- Superuser timer interrupt
constant INTERRUPT_STimer : std_logic_vector(4 downto 0) := "00101";
-- Hypervisor timer interrupt
constant INTERRUPT_HTimer : std_logic_vector(4 downto 0) := "00110";
-- Machine timer interrupt
constant INTERRUPT_MTimer : std_logic_vector(4 downto 0) := "00111";
-- User external interrupt
constant INTERRUPT_UExternal : std_logic_vector(4 downto 0) := "01000";
-- Superuser external interrupt
constant INTERRUPT_SExternal : std_logic_vector(4 downto 0) := "01001";
-- Hypervisor external interrupt
constant INTERRUPT_HExternal : std_logic_vector(4 downto 0) := "01010";
-- Machine external interrupt (from PLIC)
constant INTERRUPT_MExternal : std_logic_vector(4 downto 0) := "01011";
--! @}
-- DCSR register halt causes:
constant HALT_CAUSE_EBREAK : std_logic_vector(2 downto 0) := "001"; -- software breakpoint
constant HALT_CAUSE_TRIGGER : std_logic_vector(2 downto 0) := "010"; -- hardware breakpoint
constant HALT_CAUSE_HALTREQ : std_logic_vector(2 downto 0) := "011"; -- halt request via debug interface
constant HALT_CAUSE_STEP : std_logic_vector(2 downto 0) := "100"; -- step done
constant HALT_CAUSE_RESETHALTREQ : std_logic_vector(2 downto 0) := "101"; -- not implemented
constant PROGBUF_ERR_NONE : std_logic_vector(2 downto 0) := "000"; -- no error
constant PROGBUF_ERR_BUSY : std_logic_vector(2 downto 0) := "001"; -- abstract command in progress
constant PROGBUF_ERR_NOT_SUPPORTED : std_logic_vector(2 downto 0) := "010";-- Request command not supported
constant PROGBUF_ERR_EXCEPTION : std_logic_vector(2 downto 0) := "011"; -- Exception occurs while executing progbuf
constant PROGBUF_ERR_HALT_RESUME : std_logic_vector(2 downto 0) := "100"; -- Command cannot be executed because of wrong CPU state
constant PROGBUF_ERR_BUS : std_logic_vector(2 downto 0) := "101"; -- Bus error occurs
constant PROGBUF_ERR_OTHER : std_logic_vector(2 downto 0) := "111"; -- Other reason
--! @param[in] i_clk CPU clock
--! @param[in] i_nrst Reset. Active LOW.
--! @param[in] i_req_mem_fire Memory request was accepted
--! @param[in] i_resp_mem_valid Memory response from ICache is valid
--! @param[in] i_resp_mem_addr Memory response address
--! @param[in] i_resp_mem_data Memory response value
--! @param[in] i_e_npc Valid instruction value awaited by 'Executor'
--! @param[in] i_ra Return address register value
--! @param[out] o_npc_predic Predicted next instruction address
--! @param[out] o_predict Mark requested address as predicted
component BranchPredictor is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_req_mem_fire : in std_logic;
i_resp_mem_valid : in std_logic;
i_resp_mem_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_resp_mem_data : in std_logic_vector(31 downto 0);
i_e_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ra : in std_logic_vector(RISCV_ARCH-1 downto 0);
o_npc_predict : out std_logic_vector(31 downto 0)
);
end component;
--! @param[in] i_clk CPU clock
--! @param[in] i_nrst Reset. Active LOW.
--! @param[in] i_xret XRet instruction signals mode switching
--! @param[in] i_addr CSR address, if xret=1 switch mode accordingly
--! @param[in] i_wena Write enable
--! @param[in] i_wdata CSR writing value
--! @param[out] o_rdata CSR read value
--! @param[out] o_mepc Instruction pointer on mret
--! @param[out] o_uepc Instruction pointer on uret
--! @param[in] i_trap_ready Trap branch request was accepted
--! @param[in] i_ex_data_addr Data path: address must be equal to the latest request address
--! @param[in] i_ex_data_load_fault Data path: Bus response with SLVERR or DECERR on read
--! @param[in] i_ex_data_store_fault Data path: Bus response with SLVERR or DECERR on write
--! @param[in] i_break_mode Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
--! @param[out] o_break_event ebreak detected1 clock event
--! @param[in] i_dport_ena Debug port request is enabled
--! @param[in] i_dport_write Debug port Write enable
--! @param[in] i_dport_addr Debug port CSR address
--! @param[in] i_dport_wdata Debug port CSR writing value
--! @param[out] o_dport_rdata Debug port CSR read value
component CsrRegs is
generic (
hartid : integer;
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_mret : in std_logic;
i_uret : in std_logic;
i_sp : in std_logic_vector(RISCV_ARCH-1 downto 0);
i_addr : in std_logic_vector(11 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);
o_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);
o_mepc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_uepc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_trap_ready : in std_logic;
i_e_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_e_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ex_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ex_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ex_data_load_fault : in std_logic;
i_ex_data_store_fault : in std_logic;
i_ex_data_store_fault_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_ex_instr_load_fault : in std_logic;
i_ex_illegal_instr : in std_logic;
i_ex_unalign_store : in std_logic;
i_ex_unalign_load : in std_logic;
i_ex_mpu_store : in std_logic;
i_ex_mpu_load : in std_logic;
i_ex_breakpoint : in std_logic;
i_ex_ecall : in std_logic;
i_ex_fpu_invalidop : in std_logic;
i_ex_fpu_divbyzero : in std_logic;
i_ex_fpu_overflow : in std_logic;
i_ex_fpu_underflow : in std_logic;
i_ex_fpu_inexact : in std_logic;
i_fpu_valid : in std_logic;
i_irq_external : in std_logic;
i_e_next_ready: in std_logic;
i_e_valid : in std_logic;
o_executed_cnt : out std_logic_vector(63 downto 0);
o_trap_valid : out std_logic;
o_trap_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_dbg_pc_write : out std_logic; -- Modify pc via debug interface
o_dbg_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Writing value into pc register
o_progbuf_ena : out std_logic;
o_progbuf_pc : out std_logic_vector(31 downto 0);
o_progbuf_data : out std_logic_vector(31 downto 0);
o_flushi_ena : out std_logic; -- clear specified addr in ICache without execution of fence.i
o_flushi_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- ICache address to flush
o_mpu_region_we : out std_logic;
o_mpu_region_idx : out std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
o_mpu_region_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_mpu_region_mask : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_mpu_region_flags : out std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
i_dport_ena : in std_logic;
i_dport_write : in std_logic;
i_dport_addr : in std_logic_vector(11 downto 0);
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);
o_dport_valid : out std_logic;
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);
o_halt : out std_logic
);
end component;
--! @param[in] i_clk CPU clock
--! @param[in] i_nrst Reset. Active LOW.
--! @param[in] i_any_hold Hold pipeline by any reason
--! @param[in] i_f_valid Fetch input valid
--! @param[in] i_f_pc Fetched pc
--! @param[in] i_f_instr Fetched instruction value
--! @param[in] i_instr_load_fault Instruction fetched from fault address
--! @param[out] o_valid Current output values are valid
--! @param[out] o_pc Current instruction pointer value
--! @param[out] o_instr Current instruction value
--! @param[out] o_memop_store Store to memory operation
--! @param[out] o_memop_load Load from memoru operation
--! @param[out] o_memop_sign_ext Load memory value with sign extending
--! @param[out] o_memop_size Memory transaction size
--! @param[out] o_rv32 32-bits instruction
--! @param[out] o_f64 64-bits FPU (D-extension)
--! @param[out] o_compressed 16-bits instruction (C-extension)
--! @param[out] o_insigned_op Unsigned operands
--! @param[out] o_isa_type Instruction format accordingly with ISA
--! @param[out] o_instr_vec One bit per decoded instruction bus
--! @param[out] o_exception Unimplemented instruction
--! @param[out] o_instr_load_fault Instruction fetched from fault address
component InstrDecoder is generic (
async_reset : boolean;
fpu_ena : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_any_hold : in std_logic; -- Hold pipeline by any reason
i_f_valid : in std_logic; -- Fetch input valid
i_f_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Fetched pc
i_f_instr : in std_logic_vector(31 downto 0); -- Fetched instruction value
i_instr_load_fault : in std_logic; -- Instruction fetched from fault address
i_instr_executable : in std_logic; -- MPU flag
o_radr1 : out std_logic_vector(5 downto 0);
o_radr2 : out std_logic_vector(5 downto 0);
o_waddr : out std_logic_vector(5 downto 0);
o_csr_addr : out std_logic_vector(11 downto 0);
o_imm : out std_logic_vector(RISCV_ARCH-1 downto 0);
i_e_ready : in std_logic;
i_flush_pipeline : in std_logic; -- reset pipeline and cache
i_progbuf_ena : in std_logic; -- executing from progbuf
o_valid : out std_logic; -- Current output values are valid
o_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Current instruction pointer value
o_instr : out std_logic_vector(31 downto 0); -- Current instruction value
o_memop_store : out std_logic; -- Store to memory operation
o_memop_load : out std_logic; -- Load from memoru operation
o_memop_sign_ext : out std_logic; -- Load memory value with sign extending
o_memop_size : out std_logic_vector(1 downto 0); -- Memory transaction size
o_rv32 : out std_logic; -- 32-bits instruction
o_compressed : out std_logic; -- 16-bits opcode (C-extension)
o_f64 : out std_logic; -- 64-bits FPU (D-extension)
o_unsigned_op : out std_logic; -- Unsigned operands
o_isa_type : out std_logic_vector(ISA_Total-1 downto 0); -- Instruction format accordingly with ISA
o_instr_vec : out std_logic_vector(Instr_Total-1 downto 0); -- One bit per decoded instruction bus
o_exception : out std_logic; -- Unimplemented instruction
o_instr_load_fault : out std_logic; -- Instruction fetched from fault address
o_instr_executable : out std_logic; -- MPU flag
o_progbuf_ena : out std_logic
);
end component;
--! @param[in] i_clk
--! @param[in] i_nrst Reset active LOW
--! @param[in] i_pipeline_hold Hold execution by any reason
--! @param[in] i_d_valid Decoded instruction is valid
--! @param[in] i_d_pc Instruction pointer on decoded instruction
--! @param[in] i_d_instr Decoded instruction value
--! @param[in] i_wb_done write back done (Used to clear hazardness)
--! @param[in] i_memop_store Store to memory operation
--! @param[in] i_memop_load Load from memoru operation
--! @param[in] i_memop_sign_ext Load memory value with sign extending
--! @param[in] i_memop_size Memory transaction size
--! @param[in] i_unsigned_op Unsigned operands
--! @param[in] i_rv32 32-bits instruction
--! @param[in] i_compressed 16-bits instruction (C-extension)
--! @param[in] i_f64 D-extension (FPU)
--! @param[in] i_isa_type Type of the instruction's structure (ISA spec.)
--! @param[in] i_break_mode Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
--! @param[in] i_unsup_exception Unsupported instruction exception
--! @param[in] i_instr_load_fault Instruction fetched from fault address
--! @param[in] i_ext_irq External interrupt from PLIC (todo: timer & software interrupts)
--! @param[in] i_dport_npc_write Write npc value from debug port
--! @param[in] i_dport_npc Debug port npc value to write
--! @param[out] o_radr1 Integer/float register index 1
--! @param[in] i_rdata1 Integer register value 1
--! @param[out] o_radr2 Integer/float register index 2
--! @param[in] i_rdata2 Integer register value 2
--! @param[out] o_res_addr Address to store result of the instruction (0=do not store)
--! @param[out] o_res_data Value to store
--! @param[out] o_pipeline_hold Hold pipeline while 'writeback' not done or multi-clock instruction.
--! @param[out] o_csr_wena Write new CSR value
--! @param[in] i_csr_rdata CSR current value
--! @param[out] o_csr_wdata CSR new value
--! @param[out] o_ex_npc exception npc
--! @param[out] o_ex_instr_load_fault Instruction fetched from fault address
--! @param[out] o_ex_illegal_instr Exception: illegal instruction
--! @param[out] o_ex_unalign_store Exception: Unaligned store
--! @param[out] o_ex_unalign_load Exception: Unaligned load
--! @param[out] o_ex_breakpoint Exception: BREAK
--! @param[out] o_ex_ecall Exception: ECALL
--! @param[out] o_ex_fpu_invalidop FPU Exception: invalid operation
--! @param[out] o_ex_fpu_divbyzero FPU Exception: divide by zero
--! @param[out] o_ex_fpu_overflow FPU Exception: overflow
--! @param[out] o_ex_fpu_underflow FPU Exception: underflow
--! @param[out] o_ex_fpu_inexact FPU Exception: inexact
--! @param[out] o_fpu_valid FPU output is valid
--! @param[out] o_memop_sign_ext Load data with sign extending
--! @param[out] o_memop_load Load data instruction
--! @param[out] o_memop_store Store data instruction
--! @param[out] o_memop_size 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
--! @param[out] o_memop_addr Memory access address
--! @param[out] o_trap_ready Trap branch request was accepted
--! @param[out] o_valid Output is valid
--! @param[out] o_pc Valid instruction pointer
--! @param[out] o_npc Next instruction pointer. Next decoded pc must match to this value or will be ignored.
--! @param[out] o_instr Valid instruction value
--! @param[out] o_call CALL pseudo instruction detected
--! @param[out] o_ret RET pseudoinstruction detected
--! @param[out] o_mret MRET detected
--! @param[out] o_uret URET detected
component InstrExecute is generic (
async_reset : boolean;
fpu_ena : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic; -- Reset active LOW
i_d_valid : in std_logic; -- Decoded instruction is valid
i_d_radr1 : in std_logic_vector(5 downto 0);
i_d_radr2 : in std_logic_vector(5 downto 0);
i_d_waddr : in std_logic_vector(5 downto 0);
i_d_imm : in std_logic_vector(RISCV_ARCH-1 downto 0);
i_d_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Instruction pointer on decoded instruction
i_d_instr : in std_logic_vector(31 downto 0); -- Decoded instruction value
i_d_progbuf_ena : in std_logic; -- instruction from progbuf passed decoder
i_dbg_progbuf_ena : in std_logic; -- progbuf mode enabled
i_wb_waddr : in std_logic_vector(5 downto 0); -- Write back address
i_memop_store : in std_logic; -- Store to memory operation
i_memop_load : in std_logic; -- Load from memoru operation
i_memop_sign_ext : in std_logic; -- Load memory value with sign extending
i_memop_size : in std_logic_vector(1 downto 0); -- Memory transaction size
i_unsigned_op : in std_logic; -- Unsigned operands
i_rv32 : in std_logic; -- 32-bits instruction
i_compressed : in std_logic; -- C-extension (2-bytes length)
i_f64 : in std_logic; -- D-extension (FPU)
i_isa_type : in std_logic_vector(ISA_Total-1 downto 0); -- Type of the instruction's structure (ISA spec.)
i_ivec : in std_logic_vector(Instr_Total-1 downto 0); -- One pulse per supported instruction.
i_unsup_exception : in std_logic; -- Unsupported instruction exception
i_instr_load_fault : in std_logic; -- Instruction fetched from fault address
i_instr_executable : in std_logic; -- MPU flag
i_dport_npc_write : in std_logic; -- Write npc value from debug port
i_dport_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Debug port npc value to write
i_rdata1 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Integer/FPU registers value 1
i_rhazard1 : in std_logic;
i_rdata2 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Integer/FPU registers value 2
i_rhazard2 : in std_logic;
i_wtag : in std_logic_vector(3 downto 0);
o_wena : out std_logic;
o_waddr : out std_logic_vector(5 downto 0); -- Address to store result of the instruction (0=do not store)
o_whazard : out std_logic;
o_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Value to store
o_wtag : out std_logic_vector(3 downto 0);
o_d_ready : out std_logic; -- Hold pipeline while 'writeback' not done or multi-clock instruction.
o_csr_wena : out std_logic; -- Write new CSR value
i_csr_rdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- CSR current value
o_csr_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0); -- CSR new value
i_mepc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- next instruction in a case of MRET
i_uepc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); --
i_trap_valid : in std_logic;
i_trap_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
-- exceptions:
o_ex_npc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_ex_instr_load_fault : out std_logic; -- Instruction fetched from fault address
o_ex_instr_not_executable : out std_logic; -- MPU prohibit this instruction
o_ex_illegal_instr : out std_logic;
o_ex_unalign_store : out std_logic;
o_ex_unalign_load : out std_logic;
o_ex_breakpoint : out std_logic;
o_ex_ecall : out std_logic;
o_ex_fpu_invalidop : out std_logic; -- FPU Exception: invalid operation
o_ex_fpu_divbyzero : out std_logic; -- FPU Exception: divide by zero
o_ex_fpu_overflow : out std_logic; -- FPU Exception: overflow
o_ex_fpu_underflow : out std_logic; -- FPU Exception: underflow
o_ex_fpu_inexact : out std_logic; -- FPU Exception: inexact
o_fpu_valid : out std_logic; -- FPU output is valid
o_memop_sign_ext : out std_logic; -- Load data with sign extending
o_memop_load : out std_logic; -- Load data instruction
o_memop_store : out std_logic; -- Store data instruction
o_memop_size : out std_logic_vector(1 downto 0); -- 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
o_memop_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Memory access address
o_memop_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0);
o_memop_waddr : out std_logic_vector(5 downto 0);
o_memop_wtag : out std_logic_vector(3 downto 0);
i_memop_ready : in std_logic;
o_trap_ready : out std_logic; -- Trap branch request was accepted
o_valid : out std_logic; -- Output is valid
o_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Valid instruction pointer
o_npc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Next instruction pointer. Next decoded pc must match to this value or will be ignored.
o_instr : out std_logic_vector(31 downto 0); -- Valid instruction value
i_flushd_end : in std_logic;
o_flushd : out std_logic;
o_flushi : out std_logic;
o_call : out std_logic; -- CALL pseudo instruction detected
o_ret : out std_logic; -- RET pseudoinstruction detected
o_mret : out std_logic; -- MRET instruction
o_uret : out std_logic; -- URET instruction
o_multi_ready : out std_logic
);
end component;
--! @param[in] i_clk
--! @param[in] i_nrst
--! @param[in] i_pipeline_hold
--! @param[in] i_mem_ready
--! @param[out] o_mem_addr_valid
--! @param[out] o_mem_addr
--! @param[in] i_mem_data_valid
--! @param[in] i_mem_data_addr
--! @param[in] i_mem_data
--! @param[out] o_mem_ready
--! @param[in] i_predict_npc
--! @param[out] o_mem_req_fire Used by branch predictor to form new npc value
--! @param[out] o_valid
--! @param[out] o_pc
--! @param[out] o_instr
--! @param[out] o_hold Hold due no response from icache yet
component InstrFetch is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_pipeline_hold : in std_logic;
i_mem_req_ready : in std_logic;
o_mem_addr_valid : out std_logic;
o_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_mem_data_valid : in std_logic;
i_mem_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_mem_data : in std_logic_vector(31 downto 0);
i_mem_load_fault : in std_logic;
i_mem_executable : in std_logic;
o_mem_resp_ready : out std_logic;
i_flush_pipeline : in std_logic; -- reset pipeline and cache
i_progbuf_ena : in std_logic; -- executing from prog buffer
i_progbuf_pc : in std_logic_vector(31 downto 0); -- progbuf counter
i_progbuf_data : in std_logic_vector(31 downto 0); -- progbuf instruction
i_predict_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_mem_req_fire : out std_logic; -- used by branch predictor to form new npc value
o_instr_load_fault : out std_logic; -- fault instruction's address
o_instr_executable : out std_logic;
o_valid : out std_logic;
o_pc : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_instr : out std_logic_vector(31 downto 0);
o_hold : out std_logic -- Hold due no response from icache yet
);
end component;
--! @param[in] i_clk
--! @param[in] i_nrst
--! @param[in] i_e_valid Execution stage outputs are valid
--! @param[in] i_e_pc Execution stage instruction pointer
--! @param[in] i_e_instr Execution stage instruction value
--! @param[in] i_res_addr Register address to be written (0=no writing)
--! @param[in] i_res_data Register value to be written
--! @param[in] i_memop_sign_ext Load data with sign extending (if less than 8 Bytes)
--! @param[in] i_memop_load Load data from memory and write to i_res_addr
--! @param[in] i_memop_store Store i_res_data value into memory
--! @param[in] i_memop_size Encoded memory transaction size in bytes:
--! 0=1B; 1=2B; 2=4B; 3=8B
--! @param[in] i_memop_addr Memory access address
--! @param[out] o_wena Write enable signal
--! @param[out] o_waddr Output register address (0 = x0 = no write)
--! @param[out] o_wdata Register value
--! @param[in] i_mem_req_read Memory request is acceptable
--! @param[out] o_mem_valid Memory request is valid
--! @param[out] o_mem_write Memory write request
--! @param[out] o_mem_sz Encoded data size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
--! @param[out] o_mem_addr Data path requested address
--! @param[out] o_mem_data Data path requested data (write transaction)
--! @param[in] i_mem_data_valid Data path memory response is valid
--! @param[in] i_mem_data_addr Data path memory response address
--! @param[in] i_mem_data Data path memory response value
--! @param[out] o_mem_resp_ready Data from DCache was accepted
--! @param[out] o_hold Hold-on pipeline while memory operation not finished
--! @param[out] o_valid Output is valid
--! @param[out] o_pc Valid instruction pointer
--! @param[out] o_instr Valid instruction value
component MemAccess is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_e_valid : in std_logic; -- Execution stage outputs are valid
i_e_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Execution stage instruction pointer
i_e_instr : in std_logic_vector(31 downto 0); -- Execution stage instruction value
i_e_flushd : in std_logic;
o_flushd : out std_logic;
i_memop_waddr : in std_logic_vector(5 downto 0); -- Register address to be written (0=no writing)
i_memop_wtag : in std_logic_vector(3 downto 0);
i_memop_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Register value to be written
i_memop_sign_ext : in std_logic; -- Load data with sign extending (if less than 8 Bytes)
i_memop_load : in std_logic; -- Load data from memory and write to i_res_addr
i_memop_store : in std_logic; -- Store i_res_data value into memory
i_memop_size : in std_logic_vector(1 downto 0); -- Encoded memory transaction size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
i_memop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Memory access address
o_memop_ready : out std_logic; -- Ready to accept memop request
o_wb_wena : out std_logic; -- Write enable signal
o_wb_waddr : out std_logic_vector(5 downto 0); -- Output register address (0 = x0 = no write)
o_wb_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Register value
o_wb_wtag : out std_logic_vector(3 downto 0);
i_wb_ready : in std_logic;
-- Memory interface:
i_mem_req_ready : in std_logic;
o_mem_valid : out std_logic; -- Memory request is valid
o_mem_write : out std_logic; -- Memory write request
o_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Data path requested address
o_mem_wdata : out std_logic_vector(63 downto 0); -- Data path requested data (write transaction)
o_mem_wstrb : out std_logic_vector(7 downto 0); -- 8-bytes aligned strobs
i_mem_data_valid : in std_logic; -- Data path memory response is valid
i_mem_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Data path memory response address
i_mem_data : in std_logic_vector(63 downto 0); -- Data path memory response value
o_mem_resp_ready : out std_logic
);
end component;
--! @param[in] i_clk CPU clock
--! @param[in] i_nrst Reset. Active LOW.
--! @param[in] i_radr1 Port 1 read address
--! @param[out] o_rdata1 Port 1 read value
--! @param[in] i_radr2 Port 2 read address
--! @param[out] o_rdata2 Port 2 read value
--! @param[in] i_waddr Writing value
--! @param[in] i_wena Writing is enabled
--! @param[in] i_wdata Writing value
--! @param[in] i_dport_addr Debug port address
--! @param[in] i_dport_ena Debug port is enabled
--! @param[in] i_dport_write Debug port write is enabled
--! @param[in] i_dport_wdata Debug port write value
--! @param[out] o_dport_rdata Debug port read value
--! @param[out] o_ra Return address for branch predictor
--! @param[out] o_sp Stack Pointer for the borders control
component RegBank is generic (
async_reset : boolean;
fpu_ena : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
i_radr1 : in std_logic_vector(5 downto 0); -- Port 1 read address
o_rdata1 : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Port 1 read value
o_rhazard1 : out std_logic;
i_radr2 : in std_logic_vector(5 downto 0); -- Port 2 read address
o_rdata2 : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Port 2 read value
o_rhazard2 : out std_logic;
i_waddr : in std_logic_vector(5 downto 0); -- Writing value
i_wena : in std_logic; -- Writing is enabled
i_whazard : in std_logic;
i_wtag : in std_logic_vector(3 downto 0);
i_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Writing value
o_wtag : out std_logic_vector(3 downto 0);
i_dport_addr : in std_logic_vector(5 downto 0); -- Debug port address
i_dport_ena : in std_logic; -- Debug port is enabled
i_dport_write : in std_logic; -- Debug port write is enabled
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Debug port write value
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Debug port read value
o_ra : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Return address for branch predictor
o_sp : out std_logic_vector(RISCV_ARCH-1 downto 0) -- Stack Pointer for the borders control
);
end component;
--! @param[in] i_clk CPU clock
--! @param[in] i_nrst Reset. Active LOW.
--! @param[in] i_dport_valid Debug access from DSU is valid
--! @param[in] i_dport_write Write command flag
--! @param[in] i_dport_addr Register idx
--! @param[in] i_dport_wdata Write value
--! @param[out] o_dport_ready Response is ready
--! @param[out] o_dport_rdata Response value
--! @param[out] o_core_addr Address of the sub-region register
--! @param[out] o_core_wdata Write data
--! @param[out] o_csr_ena Region 0: Access to CSR bank is enabled.
--! @param[out] o_csr_write Region 0: CSR write enable
--! @param[in] i_csr_valid Region 0: CSR value is valid
--! @param[in] i_csr_rdata Region 0: CSR read value
--! @param[out] o_ireg_ena Region 1: Access to integer register bank is enabled
--! @param[out] o_ireg_write Region 1: Integer registers bank write pulse
--! @param[in] i_ireg_rdata Region 1: Integer register read value
--! @param[in] i_pc Region 1: Instruction pointer
--! @param[in] i_npc Region 1: Next Instruction pointer
--! @param[in] i_e_call Pseudo-instruction CALL
--! @param[in] i_e_ret Pseudo-instruction RET
component DbgPort is generic (
async_reset : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
i_dport_req_valid : in std_logic; -- Debug access from DSU is valid
i_dport_write : in std_logic; -- Write command flag
i_dport_addr : in std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0); -- Debug Port address
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Write value
o_dport_req_ready : out std_logic; -- Ready to accept dbg request
i_dport_resp_ready : in std_logic; -- Read to accept response
o_dport_resp_valid : out std_logic; -- Response is valid
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Response value
o_csr_addr : out std_logic_vector(11 downto 0); -- Address of the sub-region register
o_reg_addr : out std_logic_vector(5 downto 0);
o_core_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Write data
o_csr_ena : out std_logic; -- Region 0: Access to CSR bank is enabled.
o_csr_write : out std_logic; -- Region 0: CSR write enable
i_csr_valid : in std_logic;
i_csr_rdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Region 0: CSR read value
o_ireg_ena : out std_logic; -- Region 1: Access to integer register bank is enabled
o_ireg_write : out std_logic; -- Region 1: Integer registers bank write pulse
i_ireg_rdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Region 1: Integer register read value
i_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Region 1: Instruction pointer
i_npc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Region 1: Next Instruction pointer
i_e_call : in std_logic; -- pseudo-instruction CALL
i_e_ret : in std_logic -- pseudo-instruction RET
);
end component;
--! @brief CPU 5-stages pipeline top-level
--! @param[in] i_clk CPU clock
--! @param[in] i_nrst Reset. Active LOW.
--! @param[in] i_req_ctrl_ready ICache is ready to accept request
--! @param[out] o_req_ctrl_valid Request to ICache is valid
--! @param[out] o_req_ctrl_addr Requesting address to ICache
--! @param[in] i_resp_ctrl_valid ICache response is valid
--! @param[in] i_resp_ctrl_addr Response address must be equal to the latest request address
--! @param[in] i_resp_ctrl_data Read value
--! @param[out] o_resp_ctrl_ready Response from ICache is accepted
--! @param[in] i_req_data_ready DCache is ready to accept request
--! @param[out] o_req_data_valid Request to DCache is valid
--! @param[out] o_req_data_write Read/Write transaction
--! @param[out] o_req_data_size Size [Bytes]: 0=1B; 1=2B; 2=4B; 3=8B
--! @param[out] o_req_data_addr Requesting address to DCache
--! @param[out] o_req_data_data Writing value
--! @param[in] i_resp_data_valid DCache response is valid
--! @param[in] i_resp_data_addr DCache response address must be equal to the latest request address
--! @param[in] i_resp_data_data Read value
--! @param[in] i_resp_data_load_fault Bus response SLVERR or DECERR on read
--! @param[in] i_resp_data_store_fault Bus response SLVERR or DECERR on write
--! @param[out] o_resp_data_ready Response drom DCache is accepted
--! @param[in] i_ext_irq PLIC interrupt accordingly with spec
--! @param[out] o_time Timer in clock except halt state
--! @param[in] i_dport_valid Debug access from DSU is valid
--! @param[in] i_dport_write Write command flag
--! @param[in] i_dport_region Registers region ID: 0=CSR; 1=IREGS; 2=Control
--! @param[in] i_dport_addr Register idx
--! @param[in] i_dport_wdata Write value
--! @param[out] o_dport_ready Response is ready
--! @param[out] o_dport_rdata Response value
--! @param[out] o_flush_address Address of instruction to remove from ICache
--! @param[out] o_flush_valid Remove address from ICache is valid
component Processor is
generic (
hartid : integer;
async_reset : boolean;
fpu_ena : boolean;
tracer_ena : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
-- Control path:
i_req_ctrl_ready : in std_logic; -- ICache is ready to accept request
o_req_ctrl_valid : out std_logic; -- Request to ICache is valid
o_req_ctrl_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Requesting address to ICache
i_resp_ctrl_valid : in std_logic; -- ICache response is valid
i_resp_ctrl_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Response address must be equal to the latest request address
i_resp_ctrl_data : in std_logic_vector(31 downto 0); -- Read value
i_resp_ctrl_load_fault : in std_logic; -- bus response with error
i_resp_ctrl_executable : in std_logic;
o_resp_ctrl_ready : out std_logic;
-- Data path:
i_req_data_ready : in std_logic; -- DCache is ready to accept request
o_req_data_valid : out std_logic; -- Request to DCache is valid
o_req_data_write : out std_logic; -- Read/Write transaction
o_req_data_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Requesting address to DCache
o_req_data_wdata : out std_logic_vector(63 downto 0); -- Writing value
o_req_data_wstrb : out std_logic_vector(7 downto 0); -- 8-bytes aligned strobs
i_resp_data_valid : in std_logic; -- DCache response is valid
i_resp_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- DCache response address must be equal to the latest request address
i_resp_data_data : in std_logic_vector(63 downto 0); -- Read value
i_resp_data_store_fault_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_resp_data_load_fault : in std_logic; -- Bus response with SLVERR or DECERR on read
i_resp_data_store_fault : in std_logic; -- Bus response with SLVERR or DECERR on write
i_resp_data_er_mpu_load : in std_logic;
i_resp_data_er_mpu_store : in std_logic;
o_resp_data_ready : out std_logic;
-- External interrupt pin
i_ext_irq : in std_logic; -- PLIC interrupt accordingly with spec
-- MPU interface
o_mpu_region_we : out std_logic;
o_mpu_region_idx : out std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
o_mpu_region_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_mpu_region_mask : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_mpu_region_flags : out std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0); -- {ena, cachable, r, w, x}
-- Debug interface:
i_dport_req_valid : in std_logic; -- Debug access from DSU is valid
i_dport_write : in std_logic; -- Write command flag
i_dport_addr : in std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0); -- Debug Port address
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Write value
o_dport_req_ready : out std_logic; -- Ready to accept dbg request
i_dport_resp_ready : in std_logic; -- Read to accept response
o_dport_resp_valid : out std_logic; -- Response is valid
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Response value
o_halted : out std_logic;
-- Debug signals:
o_flush_address : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);-- Address of instruction to remove from ICache
o_flush_valid : out std_logic; -- Remove address from ICache is valid
o_data_flush_address : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Address of instruction to remove from D$
o_data_flush_valid : out std_logic; -- Remove address from D$ is valid
i_data_flush_end : in std_logic
);
end component;
--! @brief CPU cache top level
--! @param[in] i_clk
--! @param[in] i_nrst
--! @param[in] i_req_ctrl_valid
--! @param[in] i_req_ctrl_addr
--! @param[out] o_req_ctrl_ready
--! @param[out] o_resp_ctrl_valid
--! @param[out] o_resp_ctrl_addr
--! @param[out] o_resp_ctrl_data
--! @param[in] i_resp_ctrl_ready
--! @param[out] o_req_data_ready
--! @param[in] i_req_data_valid
--! @param[in] i_req_data_write
--! @param[in] i_req_data_sz
--! @param[in] i_req_data_addr
--! @param[in] i_req_data_data
--! @param[out] o_resp_data_valid
--! @param[out] o_resp_data_addr
--! @param[out] o_resp_data_data
--! @param[out] o_resp_data_load_fault
--! @param[out] o_resp_data_store_fault
--! @param[in] i_resp_data_ready
--! @param[in] i_req_mem_ready AXI request was accepted
--! @param[out] o_req_mem_valid
--! @param[out] o_req_mem_write
--! @param[out] o_req_mem_addr
--! @param[out] o_req_mem_strob
--! @param[out] o_req_mem_data
--! @param[out] o_req_mem_len burst length
--! @param[out] o_req_mem_burst burst type: "00" FIX; "01" INCR; "10" WRAP
--! @param[in] i_resp_mem_data_valid
--! @param[in] i_resp_mem_data
--! @param[in] i_resp_mem_load_store
--! @param[in] i_resp_mem_store_store
--! @param[in] i_flush_address clear ICache address from debug interface
--! @param[in] i_flush_valid address to clear icache is valid
--! @param[out] o_istate ICache state machine value
--! @param[out] o_dstate DCache state machine value
--! @param[out] o_cstate cachetop state machine value
component CacheTop is generic (
memtech : integer;
async_reset : boolean;
coherence_ena : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
-- Control path:
i_req_ctrl_valid : in std_logic;
i_req_ctrl_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_req_ctrl_ready : out std_logic;
o_resp_ctrl_valid : out std_logic;
o_resp_ctrl_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_resp_ctrl_data : out std_logic_vector(31 downto 0);
o_resp_ctrl_load_fault : out std_logic;
o_resp_ctrl_executable : out std_logic;
i_resp_ctrl_ready : in std_logic;
-- Data path:
i_req_data_valid : in std_logic;
i_req_data_write : in std_logic;
i_req_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_req_data_wdata : in std_logic_vector(63 downto 0);
i_req_data_wstrb : in std_logic_vector(7 downto 0);
o_req_data_ready : out std_logic;
o_resp_data_valid : out std_logic;
o_resp_data_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_resp_data_data : out std_logic_vector(63 downto 0);
o_resp_data_store_fault_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_resp_data_load_fault : out std_logic;
o_resp_data_store_fault : out std_logic;
o_resp_data_er_mpu_load : out std_logic;
o_resp_data_er_mpu_store : out std_logic;
i_resp_data_ready : in std_logic;
-- Memory interface:
i_req_mem_ready : in std_logic; -- AXI request was accepted
o_req_mem_path : out std_logic;
o_req_mem_valid : out std_logic;
o_req_mem_type : out std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
o_req_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_req_mem_strob : out std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);
o_req_mem_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0); -- burst transaction length
i_resp_mem_valid : in std_logic;
i_resp_mem_path : in std_logic;
i_resp_mem_data : in std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
i_resp_mem_load_fault : in std_logic; -- Bus response with SLVERR or DECERR on read
i_resp_mem_store_fault : in std_logic; -- Bus response with SLVERR or DECERR on write
-- MPU interface:
i_mpu_region_we : in std_logic;
i_mpu_region_idx : in std_logic_vector(CFG_MPU_TBL_WIDTH-1 downto 0);
i_mpu_region_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_mpu_region_mask : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_mpu_region_flags : in std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
-- D$ Snoop interface
i_req_snoop_valid : in std_logic;
i_req_snoop_type : in std_logic_vector(SNOOP_REQ_TYPE_BITS-1 downto 0);
o_req_snoop_ready : out std_logic;
i_req_snoop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_resp_snoop_ready : in std_logic;
o_resp_snoop_valid : out std_logic;
o_resp_snoop_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
o_resp_snoop_flags : out std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
-- Debug signals:
i_flush_address : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- clear ICache address from debug interface
i_flush_valid : in std_logic; -- address to clear icache is valid
i_data_flush_address : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- clear D$ address
i_data_flush_valid : in std_logic; -- address to clear D$ is valid
o_data_flush_end : out std_logic
);
end component;
--! @brief "River" CPU Top level.
--! @param[in] i_clk CPU clock
--! @param[in] i_nrst Reset. Active LOW.
--! @param[in] i_req_mem_ready AXI request was accepted
--! @param[out] o_req_mem_valid AXI memory request is valid
--! @param[out] o_req_mem_write AXI memory request is write type
--! @param[out] o_req_mem_addr AXI memory request address
--! @param[out] o_req_mem_strob Writing strob. 1 bit per Byte
--! @param[out] o_req_mem_data Writing data
--! @param[out] o_req_mem_len burst length
--! @param[out] o_req_mem_burst burst type: "00" FIX; "01" INCR; "10" WRAP
--! @param[in] i_resp_mem_data_valid AXI response is valid
--! @param[in] i_resp_mem_data Read data
--! @param[in] i_resp_mem_load_fault Bus response with SLVERR or DECERR on read
--! @param[in] i_resp_mem_store_fault Bus response with SLVERR or DECERR on write
--! @param[in] i_ext_irq Interrupt line from external interrupts controller (PLIC).
--! @param[out] o_time Timer. Clock counter except halt state.
--! @param[in] i_dport_valid Debug access from DSU is valid
--! @param[in] i_dport_write Write command flag
--! @param[in] i_dport_region Registers region ID: 0=CSR; 1=IREGS; 2=Control
--! @param[in] i_dport_addr Register idx
--! @param[in] i_dport_wdata Write value
--! @param[out] o_dport_ready Response is ready
--! @param[out] o_dport_rdata Response value
component RiverTop is
generic (
memtech : integer := 0;
hartid : integer := 0;
async_reset : boolean := false;
fpu_ena : boolean := true;
coherence_ena : boolean := false;
tracer_ena : boolean := false
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
-- Memory interface:
i_req_mem_ready : in std_logic; -- AXI request was accepted
o_req_mem_path : out std_logic; -- 0=ctrl; 1=data path
o_req_mem_valid : out std_logic; -- AXI memory request is valid
o_req_mem_type : out std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);-- AXI memory request is write type
o_req_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- AXI memory request address
o_req_mem_strob : out std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);-- Writing strob. 1 bit per Byte
o_req_mem_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0); -- Writing data
i_resp_mem_valid : in std_logic; -- AXI response is valid
i_resp_mem_path : in std_logic; -- 0=ctrl; 1=data path
i_resp_mem_data : in std_logic_vector(L1CACHE_LINE_BITS-1 downto 0); -- Read data
i_resp_mem_load_fault : in std_logic; -- Bus response with SLVERR or DECERR on read
i_resp_mem_store_fault : in std_logic; -- Bus response with SLVERR or DECERR on write
-- D$ Snoop interface
i_req_snoop_valid : in std_logic;
i_req_snoop_type : in std_logic_vector(SNOOP_REQ_TYPE_BITS-1 downto 0);
o_req_snoop_ready : out std_logic;
i_req_snoop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_resp_snoop_ready : in std_logic;
o_resp_snoop_valid : out std_logic;
o_resp_snoop_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
o_resp_snoop_flags : out std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
-- Interrupt line from external interrupts controller (PLIC).
i_ext_irq : in std_logic;
-- Debug interface:
i_dport_req_valid : in std_logic; -- Debug access from DSU is valid
i_dport_write : in std_logic; -- Write command flag
i_dport_addr : in std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0); -- Debug Port address
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Write value
o_dport_req_ready : out std_logic; -- Ready to accept dbg request
i_dport_resp_ready : in std_logic; -- Read to accept response
o_dport_resp_valid : out std_logic; -- Response is valid
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Response value
o_halted : out std_logic
);
end component;
component queue is generic (
async_reset : boolean := false;
szbits : integer := 2;
dbits : integer := 32
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_re : in std_logic;
i_we : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
o_full : out std_logic;
o_nempty : out std_logic
);
end component;
end;
package body river_cfg is
function ReadNoSnoop return std_logic_vector is
variable ret : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
begin
ret := (others => '0');
return ret;
end function;
function ReadShared return std_logic_vector is
variable ret : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
begin
ret := (others => '0');
ret(REQ_MEM_TYPE_CACHED) := '1';
return ret;
end function;
function ReadMakeUnique return std_logic_vector is
variable ret : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
begin
ret := (others => '0');
ret(REQ_MEM_TYPE_CACHED) := '1';
ret(REQ_MEM_TYPE_UNIQUE) := '1';
return ret;
end function;
function WriteNoSnoop return std_logic_vector is
variable ret : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
begin
ret := (others => '0');
ret(REQ_MEM_TYPE_WRITE) := '1';
return ret;
end function;
function WriteLineUnique return std_logic_vector is
variable ret : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
begin
ret := (others => '0');
ret(REQ_MEM_TYPE_WRITE) := '1';
ret(REQ_MEM_TYPE_CACHED) := '1';
ret(REQ_MEM_TYPE_UNIQUE) := '1';
return ret;
end function;
function WriteBack return std_logic_vector is
variable ret : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
begin
ret := (others => '0');
ret(REQ_MEM_TYPE_WRITE) := '1';
ret(REQ_MEM_TYPE_CACHED) := '1';
return ret;
end function;
end; -- package body
| apache-2.0 | 10dabf87dff90f84e2708b693f2b800c | 0.62104 | 3.42516 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.