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hamsternz/FPGA_DisplayPort | src/colour_bars_3480.vhd | 1 | 12,155 | ----------------------------------------------------------------------------------
-- Module Name: test_source_3840_2160_YCC_422_ch2 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case a 3840x2160 @ 30p grey screen.
-- Timings:
-- YCC 422, 8 bits per component
-- H Vis 3840 V Vis 2160
-- H Front 48 V Front 3
-- H Sync 32 V Sync 5
-- H Back 112 V Back 23
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity colour_bars_3840 is
port (
clk : in std_logic;
new_frame : in std_logic;
next_pixels : in std_logic;
y0 : out std_logic(7 downto 0);
y1 : out std_logic(7 downto 0);
cb : out std_logic(7 downto 0);
cr : out std_logic(7 downto 0));
);
end test_source_3840_2160_YCC_422_ch2;
architecture arch of colour_bars_3840 is
constant BAR0_Y : std_logic_vector(8 downto 0) := "11110000";
constant BAR0_Cb : std_logic_vector(8 downto 0) := "10000000";
constant BAR0_Cr : std_logic_vector(8 downto 0) := "10000000";
constant BAR1_Y0 : std_logic_vector(8 downto 0) := "111000000"; -- 0xC0
constant BAR1_Y1 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR1_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR1_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR2_Y0 : std_logic_vector(8 downto 0) := "110100000"; -- 0xC0
constant BAR2_Y1 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR2_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR2_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR3_Y0 : std_logic_vector(8 downto 0) := "110000000"; -- 0xC0
constant BAR3_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR3_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR4_Y0 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR4_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR4_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR5_Y0 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR5_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR5_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR6_Y0 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR6_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR6_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
signal col_count : unsigned(10 downto 0) := (others => '0');
constant max_col_count : unsigned(10 downto 0) := to_unsigned(1919,12); -- (3840+32+48+112)*270/265-1
begin
------------------------------------------------------------------
-- The M number here is almost magic. Here's how to calculate it.
--
-- The pixel clock is 265MHz, or 53/54 of the DisplayPort's 270MHz
-- symbol rate. As I am using YCC 422 53 pixels are being sent
-- every 54 cycles, allowing a constant TU size of 54 symbols with
-- one FE symbol for padding.
--
-- So you should expect M to be 53/54 * 0x80000 = 0x07DA12.
--
-- And you will be wrong. Bash your head against the wall for a
-- week wrong.
--
-- Here's the right way. A line is sent every 2054 cycles of the
-- 135 MHz clock, or 4108 link symbols. Each line is 4032 pixel
-- clocks (at 265 MHz). So the M value should be 4032/4108*0x80000
-- = 514588.4 = 0x07DA1C.
--
-- That small difference is enough to make things not work.
--
-- So why the difference? It's because line length (4032) doesn't
-- divide evenly by 53. To get this bang-on you would need to add
-- an extra 13 symbols every 52 lines, and as it needs to transmit
-- two symbols per cycle this would be awkward.
--
-- However the second way gives actual pixel clock is 4032/4108*270
-- 265.004,868 MHz.
--
--
-- The upside of this scheme is that an accurate Mvid[7:0] value
-- followingthe BS and VB_ID be constant for all raster lines. So
-- you can use any legal value you like.
--
-- The downside is that you have to drive your pixel generator from
-- the transceiver's reference clock.
--------------------------------------------------------------------
M_value <= x"07DA1C"; -- For 265MHz/270Mhz
N_value <= x"080000";
H_visible <= x"F00"; -- 3840
H_total <= x"FC0"; -- 4032
H_sync_width <= x"030"; -- 128
H_start <= x"0A0"; -- 160
V_visible <= x"870"; -- 2160
V_total <= x"88F"; -- 2191
V_sync_width <= x"003"; -- 3
V_start <= x"01A"; -- 26
H_vsync_active_high <= '1';
V_vsync_active_high <= '1';
flag_sync_clock <= '1';
flag_YCCnRGB <= '1';
flag_422n444 <= '1';
flag_range_reduced <= '1';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "010";
ready <= '1';
data(72) <= switch_point;
data(71 downto 36) <= (others => '0');
process(clk)
begin
if rising_edge(clk) then
switch_point <= '0';
block_count <= block_count+1;
if col_count = 0 then
if active_line = '1' then
data(35 downto 0) <= BE & DUMMY & BE & DUMMY;
else
data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
end if;
phase <= '0';
block_count <= (others => '0');
-- we do this here to get the VB_ID field correct
elsif col_count < 1957 then
------------------------------------
-- Pixel data goes here
------------------------------------
if active_line = '1' then
if block_count = 26 then
if phase = '0' then
data(35 downto 0) <= FE & PIX_Cr & FE & PIX_Cb;
else
data(35 downto 0) <= FE & PIX_Y1 & FE & PIX_Y0;
end if;
block_count <= (others => '0');
phase <= not phase;
else
if phase = '0' then
data(35 downto 0) <= PIX_Y1 & PIX_Cr & PIX_Y0 & PIX_Cb;
else
data(35 downto 0) <= PIX_Cr & PIX_Y1 & PIX_Cb & PIX_Y0;
end if;
block_count <= block_count + 1;
end if;
else
data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
switch_point <= '1';
end if;
elsif col_count = 1957 then
if active_line = '1' then
data(35 downto 0) <= VB_NVS & BS & VB_NVS & BS;
else
data(35 downto 0) <= VB_VS & BS & VB_VS & BS;
end if;
elsif col_count = 1958 then
data(35 downto 0) <= Maud & Mvid & Maud & Mvid;
elsif col_count = 1959 then
if active_line = '1' then
data(35 downto 0) <= Mvid & VB_NVS & Mvid & VB_NVS;
else
data(35 downto 0) <= Mvid & VB_VS & Mvid & VB_VS;
end if;
elsif col_count = 1960 then data(35 downto 0) <= DUMMY & Maud & DUMMY & Maud;
else data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
end if;
----------------------------------
-- When to update the active_line,
-- use to set VB-ID field after
-- te BS symbols and control
-- emitting pixels
----------------------------------
if col_count = 1956 then
if line_count = max_active_line then
active_line <= '0';
end if;
end if;
if col_count = max_col_count then
if line_count = max_line_count then
active_line <= '1';
end if;
end if;
----------------------------------
-- Update the counters
----------------------------------
if col_count = max_col_count then
col_count <= (others => '0');
if line_count = max_line_count then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
col_count <= col_count + 1;
end if;
end if;
end process;
end architecture; | mit | 6b3b13443d321e707b45a465abbc88b4 | 0.477664 | 4.099494 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpDsp/unitWhiteNoise/hdl/WhiteNoise-ea.vhd | 1 | 2,707 | -------------------------------------------------------------------------------
-- Title : White Noise Generator
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : White Noise Generation with an maximum tap LFSR
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use work.lfsr.all;
entity WhiteNoise is
generic (
-- number of bits for the streaming interface
data_width_g : natural := 24;
-- number of bits for the lfsr
lfsr_length_g : natural := 24);
port (
csi_clk : in std_logic;
rsi_reset_n : in std_logic;
-- sample strobe
coe_sample_strobe : in std_logic;
-- Avalon MM Slave Port s0 - used for enable
-- writedata[0] = 0 => disabled
-- writedata[1] = 1 => enabled
avs_s0_write : in std_logic;
avs_s0_writedata : in std_logic_vector(31 downto 0);
-- Avalon ST source
aso_data : out std_logic_vector(data_width_g-1 downto 0);
aso_valid : out std_logic
);
begin
-- plausibility checks
assert lfsr_length_g >= data_width_g
report "lfsr length must be equal or greater than data width"
severity failure;
end entity WhiteNoise;
architecture Rtl of WhiteNoise is
-- enable lfsr and output
signal enable : std_ulogic;
-- lfsr
signal lfsr_state : std_ulogic_vector(lfsr_length_g downto 1);
-- noise
signal white_noise : u_sfixed(0 downto -(data_width_g-1));
begin -- architecture Rtl
-- MM slave for enable
s0_config : process (csi_clk, rsi_reset_n) is
begin -- process
if rsi_reset_n = '0' then -- asynchronous reset (active low)
enable <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s0_write = '1' then
enable <= avs_s0_writedata(0);
end if;
end if;
end process;
-- lfsr white noise generation
lfsr_gen : process (csi_clk, rsi_reset_n) is
begin -- process lfsr_gen
if rsi_reset_n = '0' then -- asynchronous reset (active low)
lfsr_state <= (others => '0');
elsif rising_edge(csi_clk) then -- rising clock edge
if coe_sample_strobe = '1' and enable = '1' then
lfsr_state <= lfsr_nx_state(lfsr_state);
elsif enable = '0' then
lfsr_state <= (others => '0');
end if;
end if;
end process lfsr_gen;
white_noise <= to_sfixed(lfsr_state(data_width_g downto 1), white_noise);
-- avalon stream
aso_valid <= coe_sample_strobe;
aso_data <= to_slv(white_noise);
end architecture Rtl;
| gpl-3.0 | 146bb54a5b6a3060a2af43bd7d9b00ed | 0.575545 | 3.688011 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_row.vhd | 1 | 5,096 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity tb_Row is
end tb_Row;
architecture arch of tb_Row is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, cell0_sll, cell1_sll, cell2_sll,
cell3_sll);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxAB : std_logic := '1';
signal CExE : std_logic := '1';
signal Cfg : rowConfigArray;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0) := (others => '0');
signal Input : rowInputArray;
signal Output : rowOutputArray;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Row
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxABI => ClrxAB,
CExEI => CExE,
ConfigxI => Cfg,
ContextxSI => ContextxS,
InpxI => Input,
OutxO => Output);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
-- cell0: shift (SSL) by constant operator (=3)
tbStatus <= cell0_sll;
Cfg(0).procConf.AluOpxS <= alu_sll;
Cfg(0).procConf.Op1MuxS <= "10";
Cfg(0).procConf.ConstOpxD <= std_logic_vector(to_unsigned(3, DATAWIDTH));
Cfg(0).routConf.Tri0OExE <= '1';
Cfg(0).routConf.Tri1OExE <= '1';
Cfg(0).routConf.Tri2OExE <= '1';
Input(0).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD;
-- cell1: shift (SSL) by constant operator (=4)
tbStatus <= cell1_sll;
Cfg(1).procConf.AluOpxS <= alu_sll;
Cfg(1).procConf.Op1MuxS <= "10";
Cfg(1).procConf.ConstOpxD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
Cfg(1).routConf.Tri0OExE <= '1';
Cfg(1).routConf.Tri1OExE <= '1';
Cfg(1).routConf.Tri2OExE <= '1';
Input(1).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD;
-- cell2: shift (SSL) by constant operator (=5)
tbStatus <= cell2_sll;
Cfg(2).procConf.AluOpxS <= alu_sll;
Cfg(2).procConf.Op1MuxS <= "10";
Cfg(2).procConf.ConstOpxD <= std_logic_vector(to_unsigned(5, DATAWIDTH));
Cfg(2).routConf.Tri0OExE <= '1';
Cfg(2).routConf.Tri1OExE <= '1';
Cfg(2).routConf.Tri2OExE <= '1';
Input(2).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD;
-- cell3: shift (SSL) by constant operator (=6)
tbStatus <= cell3_sll;
Cfg(3).procConf.AluOpxS <= alu_sll;
Cfg(3).procConf.Op1MuxS <= "10";
Cfg(3).procConf.ConstOpxD <= std_logic_vector(to_unsigned(6, DATAWIDTH));
Cfg(3).routConf.Tri0OExE <= '1';
Cfg(3).routConf.Tri1OExE <= '1';
Cfg(3).routConf.Tri2OExE <= '1';
Input(3).In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_rowConfig;
Input <= init_rowInput;
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 193b73a76d0f5d46decb5901c9a38872 | 0.507849 | 3.59887 | false | true | false | false |
quicky2000/top_test_sharp_screen | top_test_sharp_screen.vhd | 1 | 3,231 | --
-- This file is part of top_test_sharp_screen
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_test_sharp_screen is
Port ( clk : in STD_LOGIC;
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0) ;
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
rx : in STD_LOGIC;
tx : inout STD_LOGIC
);
end top_test_sharp_screen;
architecture Behavioral of top_test_sharp_screen is
COMPONENT clock_25mhz
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
signal clk_screen_driver : std_logic;
signal clk_screen : std_logic;
signal reset : std_logic;
signal vsync : std_logic;
signal hsync : std_logic;
signal enable : std_logic;
signal screen_right_left : std_logic;
signal screen_up_down : std_logic;
signal r : std_logic_vector ( 5 downto 0);
signal g : std_logic_vector ( 5 downto 0);
signal b : std_logic_vector ( 5 downto 0);
signal audio_right : std_logic;
signal audio_left : std_logic;
begin
Inst_clock_screen: clock_25mhz PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => clk_screen_driver,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
Inst_mire_screen : entity work.mire_screen PORT MAP(
clk => clk_screen_driver,
rst => reset,
clk_out => clk_screen,
vsync => vsync,
hsync => hsync,
enable => enable,
r => r,
g => g,
b => b
);
Inst_giovanni_card : entity work.giovanni_card PORT MAP(
w1a => W1A,
w1b => W1B,
scr_red => r,
scr_green => g,
scr_blue => b,
scr_clk => clk_screen,
scr_hsync => hsync,
scr_vsync => vsync,
scr_enable => enable,
scr_right_left => screen_right_left,
scr_up_down => screen_up_down,
audio_right => audio_right,
audio_left => audio_left,
audio_stereo_ok => open,
audio_plugged => open,
io => open
);
reset <= '0';
screen_right_left <= '1';
screen_up_down <= '1';
audio_right <= '0';
audio_left <= '0';
end Behavioral;
| gpl-3.0 | a684f79112470e40c92eeeda40c841ff | 0.64005 | 3.34472 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/scrambler.vhd | 1 | 8,164 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: scrambler - Behavioral
-- Description: A x^16+x^5+x^4+x^3+1 LFSR scxrambler for DisplayPort
--
-- Scrambler LFSR is reset when a K.28.0 passes through it,
-- as per the DisplayPort spec.
--
-- Verified against the table in Apprndix C of the "PCI Express Base
-- Specification 2.1" which uses the same polynomial.
--
-- Here are the first 32 output words when data values of "00" are scrambled:
--
-- | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
-- ---+------------------------------------------------
-- 00 | FF 17 C0 14 B2 E7 02 82 72 6E 28 A6 BE 6D BF 8D
-- 10 | BE 40 A7 E6 2C D3 E2 B2 07 02 77 2A CD 34 BE E0
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scrambler is
Port ( clk : in STD_LOGIC;
bypass0 : in STD_LOGIC;
bypass1 : in STD_LOGIC;
in_data : in STD_LOGIC_VECTOR (71 downto 0);
out_data : out STD_LOGIC_VECTOR (71 downto 0) := (others => '0'));
end scrambler;
architecture Behavioral of scrambler is
signal lfsr_state : STD_LOGIC_VECTOR (15 downto 0) := (others => '1');
constant SR : STD_LOGIC_VECTOR ( 8 downto 0) := "100011100"; -- K28.0 ia used to reset the scrambler
begin
process(clk)
variable s0 : STD_LOGIC_VECTOR (15 downto 0);
variable s1 : STD_LOGIC_VECTOR (15 downto 0);
begin
if rising_edge(clk) then
s0 := lfsr_state;
--------------------------------------------
-- Process symbol 0
--------------------------------------------
if in_data(8) = '1' or bypass0 = '1' then
-- Bypass the scrambler for 'K' symbols (but still update LFSR state!)
out_data(8 downto 0) <= in_data(8 downto 0);
else
out_data(0) <= in_data(0) xor s0(15);
out_data(1) <= in_data(1) xor s0(14);
out_data(2) <= in_data(2) xor s0(13);
out_data(3) <= in_data(3) xor s0(12);
out_data(4) <= in_data(4) xor s0(11);
out_data(5) <= in_data(5) xor s0(10);
out_data(6) <= in_data(6) xor s0( 9);
out_data(7) <= in_data(7) xor s0( 8);
out_data(8) <= '0';
end if;
-- generate intermediate scrambler state
if in_data(8 downto 0) = SR then
s1 := x"FFFF";
else
s1(0) := s0(8);
s1(1) := s0(9);
s1(2) := s0(10);
s1(3) := s0(11) xor s0(8);
s1(4) := s0(12) xor s0(8) xor s0(9);
s1(5) := s0(13) xor s0(8) xor s0(9) xor s0(10);
s1(6) := s0(14) xor s0(9) xor s0(10) xor s0(11);
s1(7) := s0(15) xor s0(10) xor s0(11) xor s0(12);
s1(8) := s0(0) xor s0(11) xor s0(12) xor s0(13);
s1(9) := s0(1) xor s0(12) xor s0(13) xor s0(14);
s1(10) := s0(2) xor s0(13) xor s0(14) xor s0(15);
s1(11) := s0(3) xor s0(14) xor s0(15);
s1(12) := s0(4) xor s0(15);
s1(13) := s0(5);
s1(14) := s0(6);
s1(15) := s0(7);
end if;
--------------------------------------------
-- Process symbol 1
--------------------------------------------
if in_data(17) = '1' or bypass1 = '1' then
-- Bypass the scrambler for 'K' symbols (but still update LFSR state!)
out_data(17 downto 9) <= in_data(17 downto 9);
else
-- Scramble symbol 1
out_data( 9) <= in_data( 9) xor s1(15);
out_data(10) <= in_data(10) xor s1(14);
out_data(11) <= in_data(11) xor s1(13);
out_data(12) <= in_data(12) xor s1(12);
out_data(13) <= in_data(13) xor s1(11);
out_data(14) <= in_data(14) xor s1(10);
out_data(15) <= in_data(15) xor s1( 9);
out_data(16) <= in_data(16) xor s1( 8);
out_data(17) <= '0';
end if;
-- Update scrambler state
if in_data(17 downto 9) = SR then
lfsr_state <= x"FFFF";
else
lfsr_state(0) <= s1(8);
lfsr_state(1) <= s1(9);
lfsr_state(2) <= s1(10);
lfsr_state(3) <= s1(11) xor s1(8);
lfsr_state(4) <= s1(12) xor s1(8) xor s1(9);
lfsr_state(5) <= s1(13) xor s1(8) xor s1(9) xor s1(10);
lfsr_state(6) <= s1(14) xor s1(9) xor s1(10) xor s1(11);
lfsr_state(7) <= s1(15) xor s1(10) xor s1(11) xor s1(12);
lfsr_state(8) <= s1(0) xor s1(11) xor s1(12) xor s1(13);
lfsr_state(9) <= s1(1) xor s1(12) xor s1(13) xor s1(14);
lfsr_state(10) <= s1(2) xor s1(13) xor s1(14) xor s1(15);
lfsr_state(11) <= s1(3) xor s1(14) xor s1(15);
lfsr_state(12) <= s1(4) xor s1(15);
lfsr_state(13) <= s1(5);
lfsr_state(14) <= s1(6);
lfsr_state(15) <= s1(7);
end if;
end if;
end process;
end Behavioral;
| mit | 45e6a36f838e17d1798893e259bbbbca | 0.457741 | 3.620399 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_reg_en.vhd | 1 | 3,607 | ------------------------------------------------------------------------------
-- Testbench for reg_en.vhd
--
-- Project :
-- File : tb_reg_en.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Reg_en is
end tb_Reg_en;
architecture arch of tb_Reg_en is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, en, dis);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data signals
signal DinxD, DoutxD : std_logic_vector(WIDTH-1 downto 0);
-- control/status signals
signal EnxE : std_logic;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Reg_en
generic map (
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
EnxEI => EnxE,
DinxDI => DinxD,
DoutxDO => DoutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(0, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= en;
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(1, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(2, WIDTH));
wait for CLK_PERIOD;
tbStatus <= en;
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(3, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(4, WIDTH));
wait for CLK_PERIOD;
tbStatus <= en;
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(5, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(6, WIDTH));
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 59bd4a097492fac7d2e1da0feb8037b4 | 0.46687 | 3.990044 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_reg_clr_en.vhd | 1 | 4,263 | ------------------------------------------------------------------------------
-- Testbench for reg_clr_en.vhd
--
-- Project :
-- File : tb_reg_clr_en.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/02/12
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Reg_clr_en is
end tb_Reg_clr_en;
architecture arch of tb_Reg_clr_en is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, en, dis, clr, clr_en);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxE : std_logic;
signal EnxE : std_logic;
signal DinxD : std_logic_vector(WIDTH-1 downto 0);
signal DoutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Reg_Clr_En
generic map (
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxEI => ClrxE,
EnxEI => EnxE,
DinxDI => DinxD,
DoutxDO => DoutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(0, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= en;
ClrxE <= '0';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(1, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(2, WIDTH));
wait for CLK_PERIOD;
tbStatus <= en;
ClrxE <= '0';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(3, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(4, WIDTH));
wait for CLK_PERIOD;
tbStatus <= clr;
ClrxE <= '1';
EnxE <= '0';
DinxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= en;
ClrxE <= '0';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(5, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxE <= '0';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(6, WIDTH));
wait for CLK_PERIOD;
tbStatus <= clr_en;
ClrxE <= '1';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(7, WIDTH));
wait for CLK_PERIOD;
tbStatus <= done;
ClrxE <= '0';
EnxE <= '0';
DinxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 3431d08d249e00a316fef323d46624ff | 0.463054 | 3.694107 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt/vtest/adpcm_p2.vhd | 1 | 5,692 | -- c_0_0 opt232
cfg.gridConf(0)(0).procConf.AluOpxS := alu_pass0;
-- o.0
cfg.gridConf(0)(0).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(0)(0).procConf.OutCtxRegSelxS := i2ctx(1);
-- c_0_1 op22
cfg.gridConf(0)(1).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(1).HBusNxE(0) := '1';
-- i.2
cfg.gridConf(0)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(2).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(1).routConf.o.HBusNxE(0) := '1';
-- c_0_2 op25b
cfg.gridConf(0)(2).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(0)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(0)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(2).procConf.ConstOpxD := i2cfgconst(32768);
-- i.2
cfg.gridConf(0)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(2).LocalxE(LOCAL_SE) := '1';
-- o.0
cfg.gridConf(0)(2).procConf.OutMuxS := O_NOREG;
-- c_0_3 obuf
cfg.gridConf(0)(3).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(0)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(0)(3).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(0)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(3).routConf.o.HBusNxE(1) := '1';
-- c_1_0 opt230
cfg.gridConf(1)(0).procConf.AluOpxS := alu_pass0;
-- o.0
cfg.gridConf(1)(0).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(1)(0).procConf.OutCtxRegSelxS := i2ctx(1);
cfg.gridConf(1)(0).routConf.o.VBusExE(1) := '1';
-- c_1_1 op24
cfg.gridConf(1)(1).procConf.AluOpxS := alu_lt;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(1).procConf.ConstOpxD := i2cfgconst(-32768);
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
-- c_1_2 op25c
cfg.gridConf(1)(2).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_SE) := '1';
-- i.2
cfg.gridConf(1)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(2).LocalxE(LOCAL_W) := '1';
-- o.0
cfg.gridConf(1)(2).procConf.OutMuxS := O_NOREG;
-- c_1_3 op23
cfg.gridConf(1)(3).procConf.AluOpxS := alu_gt;
-- i.0
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(3).procConf.ConstOpxD := i2cfgconst(32767);
-- o.0
cfg.gridConf(1)(3).procConf.OutMuxS := O_NOREG;
-- c_2_0 opt231
cfg.gridConf(2)(0).procConf.AluOpxS := alu_pass0;
-- o.0
cfg.gridConf(2)(0).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(2)(0).procConf.OutCtxRegSelxS := i2ctx(1);
-- c_2_1 op20
cfg.gridConf(2)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op21
cfg.gridConf(2)(2).procConf.AluOpxS := alu_sub;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(2).routConf.i(1).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op25a
cfg.gridConf(2)(3).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_CONST;
cfg.gridConf(2)(3).procConf.ConstOpxD := i2cfgconst(-32767);
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(3).procConf.ConstOpxD := i2cfgconst(-32767);
-- i.2
cfg.gridConf(2)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(2).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
-- c_3_0 op5
cfg.gridConf(3)(0).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(0).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(3)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(0).procConf.ConstOpxD := i2cfgconst(8);
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 op18
cfg.gridConf(3)(1).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(3)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- i.1
cfg.gridConf(3)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(1).VBusExE(1) := '1';
-- i.2
cfg.gridConf(3)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(2).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(3)(1).procConf.OutMuxS := O_NOREG;
-- c_3_2 feedthrough_c_3_2
cfg.gridConf(3)(2).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- c_3_3 feedthrough_c_3_3
cfg.gridConf(3)(3).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(3)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(3).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(3)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(3).routConf.o.HBusNxE(0) := '1';
-- input drivers
cfg.inputDriverConf(0)(3)(1) := '1';
-- output drivers
cfg.outputDriverConf(1)(1)(1) := '1';
| bsd-3-clause | e071a521254123973009acd0d1a628a4 | 0.650914 | 2.08651 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpTemplate/tbdTemplate/hdl/PlatformHps-e.vhd | 2 | 1,826 | library ieee;
use ieee.std_logic_1164.all;
entity PlatformHps is
port(
-- Clock
CLOCK_50 : in std_logic;
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- KEY
KEY : in std_logic_vector(3 downto 0);
-- Switches
SW : in std_logic_vector(9 downto 0);
--7SEG
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : in std_logic;
AUD_XCK : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- HPS
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0) := (others => 'X');
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0) := (others => 'X');
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0) := (others => 'X');
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_RZQ : in std_logic := 'X';
HPS_KEY : inout std_logic;
HPS_LED : inout std_logic
);
end entity PlatformHps;
| gpl-3.0 | d496034dc14ee4e2832aab1273696a5c | 0.576123 | 2.884676 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_fifo.vhd | 1 | 9,163 | ------------------------------------------------------------------------------
-- Testbench for fifo.vhd
--
-- Project :
-- File : tb_fifo.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/25
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Fifo is
end tb_Fifo;
architecture arch of tb_Fifo is
constant WIDTH : integer := 8; -- Data width
constant DEPTH : integer := 4; -- FIFO depth
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, wr, wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr0,
rd, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd0, r_w, done);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- FIFO data and control/status signals
signal FifoWExEI : std_logic;
signal FifoRExEI : std_logic;
signal FifoDinxDI : std_logic_vector(WIDTH-1 downto 0);
signal FifoDoutxDO : std_logic_vector(WIDTH-1 downto 0);
signal FifoEmptyxSO : std_logic;
signal FifoFullxSO : std_logic;
signal FifoFillLevelxDO : std_logic_vector(log2(DEPTH) downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Fifo
generic map (
WIDTH => WIDTH,
DEPTH => DEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => FifoWExEI,
RExEI => FifoRExEI,
DinxDI => FifoDinxDI,
DoutxDO => FifoDoutxDO,
EmptyxSO => FifoEmptyxSO,
FullxSO => FifoFullxSO,
FillLevelxDO => FifoFillLevelxDO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= wr1; -- write #1
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(10, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr2; -- write #2
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(20, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr3; -- write #3
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(30, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd1; -- read #1
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= wr4; -- write #4
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(40, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd2; -- read #2
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= wr5; -- write #5
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(50, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr6; -- write #6
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(60, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr0; -- write #0 (fifo is full...)
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(61, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd3; -- read #3
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd4; -- read #4
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= wr7; -- write #7
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(70, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd5; -- read #5
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd6; -- read #6
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd7; -- read #7
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd0; -- read #0 (fifo is empty...)
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 3*CLK_PERIOD;
-------------------------------------------------------------------------
-- now test what happens if read and write are both set at the same time
-------------------------------------------------------------------------
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(11, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(22, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
tbStatus <= r_w; -- read AND write
FifoWExEI <= '1';
FifoRExEI <= '1';
FifoDinxDI <= std_logic_vector(to_unsigned(33, WIDTH));
wait for CLK_PERIOD;
FifoDinxDI <= std_logic_vector(to_unsigned(44, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(55, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(66, WIDTH));
wait for CLK_PERIOD;
-- now FIFO is full ----------------------------------------------------
tbStatus <= r_w; -- read AND write
FifoWExEI <= '1';
FifoRExEI <= '1';
FifoDinxDI <= std_logic_vector(to_unsigned(67, WIDTH)); -- => no write
wait for CLK_PERIOD;
FifoDinxDI <= std_logic_vector(to_unsigned(77, WIDTH)); -- => write
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
-- now FIFO is empty ---------------------------------------------------
tbStatus <= r_w; -- read AND write
FifoWExEI <= '1';
FifoRExEI <= '1';
FifoDinxDI <= std_logic_vector(to_unsigned(88, WIDTH));
wait for CLK_PERIOD;
FifoDinxDI <= std_logic_vector(to_unsigned(99, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= done; -- done
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 7040dc80dc41627dfaa7974b0bd46a41 | 0.473098 | 3.700727 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/pixel_x4_generator.vhd | 1 | 7,969 | ----------------------------------------------------------------------------------
-- Module Name: pixel_x4_generator - Behavioral
--
-- Description: A module to generate a group of pixels at a time.
-- Not yet in use in the main project.
--
----------------------------------------------------------------------------------
-- NOTE FOR THIS TO WORK CORRECTLY h_visible_en, h_blank_len, h_front_len & h_sync_len
-- MUST BE DIVISIBLE BY 4!!!!!
------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pixel_x4_generator is
port (
clk_135 : in std_logic;
pixel_rate_div_10k : in std_logic(15 downto 0); -- 0 to 643.5 MHz rates
h_visible_len : in std_logic(11 downto 0);
h_blank_len : in std_logic(11 downto 0);
h_front_len : in std_logic(11 downto 0);
h_sync_len : in std_logic(11 downto 0);
v_visible_len : in std_logic(11 downto 0);
v_blank_len : in std_logic(11 downto 0);
v_front_len : in std_logic(11 downto 0);
v_sync_len : in std_logic(11 downto 0);
-----------------------------------------------
px_de : out std_logic;
px_blank : out std_logic;
px_vsync : out std_logic;
px_hsync : out std_logic;
p0_Cb : out std_logic(7 downto 0);
p0_Y : out std_logic(7 downto 0);
p1_Cr : out std_logic(7 downto 0);
p1_Y : out std_logic(7 downto 0);
p2_Cb : out std_logic(7 downto 0);
p2_Y : out std_logic(7 downto 0);
p2_blue : out std_logic(7 downto 0);
p2_Cr : out std_logic(7 downto 0);
p2_Y : out std_logic(7 downto 0));
end entity;
architecture arch of pixel_x4_generator is
signal h_count_0 : unsigned(11 downto 0) := (others => '0');
signal h_counter : unsigned(11 downto 0) := (others => '0');
signal v_counter : unsigned(11 downto 0) := (others => '0');
signal v_sync : std_logic := '0';
signal v_blank : std_logic := '0';
signal new_pixels : std_logic := '0';
signal phase_accumulator : unsigned(18 downto 0) := (others => '0');
begin
clk_proc: process(clk_135)
begin
if rising_edge(clk_135) then
h_total <= h_visible_len - h_blank_len;
-------------------------------------
-- Generate new pixels
-------------------------------------
px_de <= '0';
if new_pixels = '1' then
px_de <= '1';
-----------------
-- For all pixels
-----------------
-- Are we in the horizontal sync?
if h_count_0 >= h_front_len and h_count_0 < h_front_len+h_sync_len then
px_hsync <= '1';
else
px_hsync <= '0';
end if;
-- Are we in the horizontal blank?
px_blank <= '0';
if h_count_0 < h_blank_len then
px_blank <= '1';
end if;
-- Are we in the vertical blank?
if v_count_0 < v_blank_len then
px_blank <= '1';
end if;
-- Are we in the vertical sync?
if v_count_0 > v_front_len or v_counter < v_front_len+v_sync_len then
px_vsync <= '1';
else
px_vsync <= '0';
end if;
-------------------
-- Per pixel levels
-------------------
if h_count_0 < h_blank_len then
p0_cb <= x"80";
p1_cb <= x"80";
p2_cb <= x"80";
p3_cb <= x"80";
p0_y <= x"10";
p1_y <= x"10";
p2_y <= x"10";
p3_y <= x"10";
else
p0_cb <= x"80";
p1_cb <= x"80";
p2_cb <= x"80";
p3_cb <= x"80";
p0_y <= std_logic_vector(h_count_0(7 downto 0));
p1_y <= std_logic_vector(h_count_0(7 downto 0));
p2_y <= std_logic_vector(h_count_0(7 downto 0));
p3_y <= std_logic_vector(h_count_0(7 downto 0));
end if;
end if;
---------------------------------------------
-- Advance the counters and trigger the
-- generation of four new pixels
---------------------------------------------
if generate_pixels = '1' then
new_pixels <= '1';
h_count_0 <= h_counter;
v_count_0 <= v_counter;
if h_counter >= h_blank_len+h_visible_len-4 then
h_counter <= (others => '0');
if v_counter = v_blank_len + v_visible_len then
v_counter <= (others => '0');
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter+4;
end if;
else
new_pixels <= '0';
end if;
--------------------------------------------------
-- Generate a pulse at 1/4th the pixel clock rate
-- but in the clk_135 domain.
--------------------------------------------------
if phase_accumulator < pixel_rate_div_10k then
phase_accumulator <= phase_accumulator + (13500*4) - pixel_rate_div_10k;
generate_pixels <= '1';
else
phase_accumulator <= phase_accumulator - pixel_rate_div_10k;
generate_pixels <= '0';
end if;
end if;
end process;
end architecture; | mit | 6e038126eb84ca8f353f871ac3897aca | 0.470699 | 3.980519 | false | false | false | false |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_tb.vhd | 5 | 4,403 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: blk_mem_gen_v7_3_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY blk_mem_gen_v7_3_tb IS
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_tb_ARCH OF blk_mem_gen_v7_3_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
blk_mem_gen_v7_3_synth_inst:ENTITY work.blk_mem_gen_v7_3_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 | 52343a5eb20ad187084b8546855fe0d6 | 0.619123 | 4.474593 | false | false | false | false |
tmeissner/raspberrypi | raspiFpga/src/RaspiFpgaE.vhd | 1 | 8,892 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.components.all;
entity RaspiFpgaE is
port (
--+ SPI slave if
SpiSclk_i : inout std_logic;
SpiSte_i : in std_logic;
SpiMosi_i : inout std_logic;
SpiMiso_o : inout std_logic;
--* interrupt line to raspi
RaspiIrq_o : out std_logic
);
end entity RaspiFpgaE;
architecture rtl of RaspiFpgaE is
--+ Wishbone master component
component WishBoneMasterE is
generic (
G_ADR_WIDTH : positive := 8; --* address bus width
G_DATA_WIDTH : positive := 8 --* data bus width
);
port (
--+ wishbone system if
WbRst_i : in std_logic;
WbClk_i : in std_logic;
--+ wishbone outputs
WbCyc_o : out std_logic;
WbStb_o : out std_logic;
WbWe_o : out std_logic;
WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
--+ wishbone inputs
WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
WbAck_i : in std_logic;
WbErr_i : in std_logic;
--+ local register if
LocalWen_i : in std_logic;
LocalRen_i : in std_logic;
LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
LocalAck_o : out std_logic;
LocalError_o : out std_logic
);
end component WishBoneMasterE;
component RaspiFpgaCtrlE is
port (
--+ System if
Rst_n_i : in std_logic;
Clk_i : in std_logic;
--+ local register if
LocalWen_o : out std_logic;
LocalRen_o : out std_logic;
LocalAdress_o : out std_logic_vector(7 downto 0);
LocalData_i : in std_logic_vector(7 downto 0);
LocalData_o : out std_logic_vector(7 downto 0);
LocalAck_i : in std_logic;
LocalError_i : in std_logic;
--+ EFB if
EfbSpiIrq_i : in std_logic;
--+ RNG if
RngStart_o : out std_logic;
RngWait_o : out std_logic_vector(7 downto 0);
RngRun_o : out std_logic_vector(7 downto 0);
RngDataValid_i : in std_logic;
RngData_i : in std_logic_vector(7 downto 0)
);
end component RaspiFpgaCtrlE;
component FiRoCtrlE is
generic (
EXTRACT : boolean := true
);
port (
--+ system if
Clk_i : in std_logic;
Reset_i : in std_logic;
--+ ctrl/status
Start_i : in std_logic;
Wait_i : in std_logic_vector(7 downto 0);
Run_i : in std_logic_vector(7 downto 0);
--+ rnd data
DataValid_o : out std_logic;
Data_o : out std_logic_vector(7 downto 0);
-- firo
Run_o : out std_logic;
Data_i : in std_logic
);
end component FiRoCtrlE;
component FiRoE is
generic (
IMP : string := "HDL",
TOGGLE : boolean := true
);
port (
FiRo_o : out std_logic;
Run_i : in std_logic
);
end component FiRoE;
--+ EFB SPI slave component
component EfbSpiSlave is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_ack_o : out std_logic;
spi_clk : inout std_logic;
spi_miso : inout std_logic;
spi_mosi : inout std_logic;
spi_scsn : in std_logic;
spi_irq : out std_logic
);
end component EfbSpiSlave;
--+ oscillator component
component OSCH is
generic (
NOM_FREQ : string := "26.60"
);
port (
STDBY : in std_logic;
OSC : out std_logic;
SEDSTDBY : out std_logic
);
end component OSCH;
attribute NOM_FREQ : string;
attribute NOM_FREQ of i_OSC : label is "26.60";
--+ system signals
signal s_sys_clk : std_logic;
signal s_sys_rst : std_logic := '1';
signal s_spi_sclk : std_logic;
signal s_spi_miso : std_logic;
signal s_spi_mosi : std_logic;
--+ Wishbone bus signals
signal s_wb_clk : std_logic;
signal s_wb_rst : std_logic;
signal s_wb_cyc : std_logic;
signal s_wb_stb : std_logic;
signal s_wb_we : std_logic;
signal s_wb_adr : std_logic_vector(7 downto 0);
signal s_wb_master_dat : std_logic_vector(7 downto 0);
signal s_wb_slave_dat : std_logic_vector(7 downto 0);
signal s_wb_ack : std_logic;
--+ EFB signals
signal s_efb_irq : std_logic;
--+ Wishbone master signals
signal s_local_wen : std_logic;
signal s_local_ren : std_logic;
signal s_local_adr : std_logic_vector(7 downto 0);
signal s_local_read_data : std_logic_vector(7 downto 0);
signal s_local_write_data : std_logic_vector(7 downto 0);
signal s_local_ack : std_logic;
--+ RNG signals
signal s_rng_start : std_logic;
signal s_rng_wait : std_logic_vector(7 downto 0);
signal s_rng_run : std_logic_vector(7 downto 0);
signal s_rng_data_valid : std_logic;
signal s_rng_data : std_logic_vector(7 downto 0);
signal s_firo_run : std_logic;
signal s_firo_data : std_logic;
begin
--+ Oscillator instance
--+ It's generating our 26.6 MHz system lock
i_OSC : OSCH
generic map (
NOM_FREQ => "26.60"
)
port map (
STDBY => '0',
OSC => s_sys_clk,
SEDSTDBY => open
);
s_wb_clk <= s_sys_clk;
s_wb_rst <= not(s_sys_rst);
ResetP : process (s_sys_clk) is
variable v_clk_count : natural range 0 to 15 := 15;
begin
if(rising_edge(s_sys_clk)) then
if(v_clk_count = 0) then
s_sys_rst <= '1';
else
s_sys_rst <= '0';
v_clk_count := v_clk_count - 1;
end if;
end if;
end process ResetP;
--+ EFB SPI slave instance
i_EfbSpiSlave : EfbSpiSlave
port map (
wb_clk_i => s_wb_clk,
wb_rst_i => s_wb_rst,
wb_cyc_i => s_wb_cyc,
wb_stb_i => s_wb_stb,
wb_we_i => s_wb_we,
wb_adr_i => s_wb_adr,
wb_dat_i => s_wb_master_dat,
wb_dat_o => s_wb_slave_dat,
wb_ack_o => s_wb_ack,
spi_clk => SpiSclk_i,
spi_miso => SpiMiso_o,
spi_mosi => SpiMosi_i,
spi_scsn => SpiSte_i,
spi_irq => s_efb_irq
);
i_WishBoneMasterE : WishBoneMasterE
generic map (
G_ADR_WIDTH => 8,
G_DATA_WIDTH => 8
)
port map (
--+ wishbone system if
WbRst_i => s_wb_rst,
WbClk_i => s_wb_clk,
--+ wishbone outputs
WbCyc_o => s_wb_cyc,
WbStb_o => s_wb_stb,
WbWe_o => s_wb_we,
WbAdr_o => s_wb_adr,
WbDat_o => s_wb_master_dat,
--+ wishbone inputs
WbDat_i => s_wb_slave_dat,
WbAck_i => s_wb_ack,
WbErr_i => '0',
--+ local register if
LocalWen_i => s_local_wen,
LocalRen_i => s_local_ren,
LocalAdress_i => s_local_adr,
LocalData_i => s_local_write_data,
LocalData_o => s_local_read_data,
LocalAck_o => s_local_ack,
LocalError_o => open
);
i_RaspiFpgaCtrlE : RaspiFpgaCtrlE
port map (
--+ System if
Rst_n_i => s_sys_rst,
Clk_i => s_sys_clk,
--+ local register if
LocalWen_o => s_local_wen,
LocalRen_o => s_local_ren,
LocalAdress_o => s_local_adr,
LocalData_i => s_local_read_data,
LocalData_o => s_local_write_data,
LocalAck_i => s_local_ack,
LocalError_i => '0',
--+ EFB if
EfbSpiIrq_i => s_efb_irq,
--+ RNG if
RngStart_o => s_rng_start,
RngWait_o => s_rng_wait,
RngRun_o => s_rng_run,
RngDataValid_i => s_rng_data_valid,
RngData_i => s_rng_data
);
i_FiRoCtrlE : FiRoCtrlE
generic map (
EXTRACT => true
)
port map (
--+ system if
Clk_i => s_sys_clk,
Reset_i => s_sys_rst,
--+ ctrl/status
Start_i => s_rng_start,
Wait_i => s_rng_wait,
Run_i => s_rng_run,
--+ rnd data
DataValid_o => s_rng_data_valid,
Data_o => s_rng_data,
-- firo
Run_o => s_firo_run,
Data_i => s_firo_data
);
i_FiRoE : FiRoE
generic map (
IMP => "LUT",
TOGGLE => true
)
port map (
FiRo_o => s_firo_data,
Run_i => s_firo_run
);
RaspiIrq_o <= '0';
end architecture rtl;
| gpl-2.0 | d9d24ac53f1d37dad80be715294760d1 | 0.532389 | 3.02861 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_updowncounter.vhd | 1 | 5,656 | ------------------------------------------------------------------------------
-- Testbench for updowncounter.vhd
--
-- Project :
-- File : updowncounter.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/21
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_UpDownCounter is
end tb_UpDownCounter;
architecture arch of tb_UpDownCounter is
constant WIDTH : integer := 4;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, load, cnt_up, cnt_down);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT I/O signals
signal LoadxEI : std_logic;
signal CExEI : std_logic;
signal ModexSI : std_logic;
signal CinxDI : std_logic_vector(WIDTH-1 downto 0);
signal CoutxDO : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : UpDownCounter
generic map (
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
LoadxEI => LoadxEI,
CExEI => CExEI,
ModexSI => ModexSI,
CinxDI => CinxDI,
CoutxDO => CoutxDO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal LoadxEI : out std_logic;
signal CExEI : out std_logic;
signal ModexSI : out std_logic;
signal CinxDI : out std_logic_vector(WIDTH-1 downto 0)) is
begin
LoadxEI <= '0';
CExEI <= '0';
ModexSI <= '0';
CinxDI <= (others => '0');
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(LoadxEI, CExEI, ModexSI, CinxDI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= load; -- load start value
LoadxEI <= '1';
CinxDI <= std_logic_vector(to_unsigned(7, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(LoadxEI, CExEI, ModexSI, CinxDI);
wait for CLK_PERIOD;
tbStatus <= cnt_up; -- count up
CExEI <= '1';
ModexSI <= '0';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= load; -- load new start value
LoadxEI <= '1';
CinxDI <= std_logic_vector(to_unsigned(5, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(LoadxEI, CExEI, ModexSI, CinxDI);
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= cnt_up; -- count up
CExEI <= '1';
ModexSI <= '0';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= load; -- load new start value
LoadxEI <= '1';
CinxDI <= std_logic_vector(to_unsigned(13, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(LoadxEI, CExEI, ModexSI, CinxDI);
wait for CLK_PERIOD;
tbStatus <= cnt_up; -- count up
CExEI <= '1';
ModexSI <= '0';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(LoadxEI, CExEI, ModexSI, CinxDI);
wait for CLK_PERIOD;
tbStatus <= load; -- load new start value
LoadxEI <= '1';
CinxDI <= std_logic_vector(to_unsigned(4, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(LoadxEI, CExEI, ModexSI, CinxDI);
wait for CLK_PERIOD;
tbStatus <= cnt_down; -- count down
CExEI <= '1';
ModexSI <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= done; -- done
init_stimuli(LoadxEI, CExEI, ModexSI, CinxDI);
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 9b68b4b96d8a3b94647102e290a3b6a0 | 0.499823 | 3.866029 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/insert_training_pattern.vhd | 1 | 8,250 | ---------------------------------------------------
-- Module: training_and_channel_delay
--
-- Description: Allow the insertion of the training patterns into the symbol
-- stream, and ensure a clean switch-over to the input channel,
--
-- Also adds the 8b10b encoder's "force negative parity" flag
--
-- Also delay the symbols by the inter-channel skew (2 symbols per channel)
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-18 | Resolve clock domain crossing issues
------------------------------------------------------------------------------------
---------------------------------------------------
--
-- This is set up so the change over from test patters
-- to data happens seamlessly - e.g. the value for
-- on data_in when send_patter_1 and send_pattern_2
-- are both become zero is guarranteed to be sent
--
-- +----+--------------------+--------------------+
-- |Word| Training pattern 1 | Training pattern 2 |
-- | | Code MSB LSB | Code MSB LSB |
-- +----+--------------------+-------------------+
-- | 0 | D10.2 1010101010 | K28.5- 0101111100 |
-- | 1 | D10.2 1010101010 | D11.6 0110001011 |
-- | 2 | D10.2 1010101010 | K28.5+ 1010000011 |
-- | 3 | D10.2 1010101010 | D11.6 0110001011 |
-- | 4 | D10.2 1010101010 | D10.2 1010101010 |
-- | 5 | D10.2 1010101010 | D10.2 1010101010 |
-- | 6 | D10.2 1010101010 | D10.2 1010101010 |
-- | 7 | D10.2 1010101010 | D10.2 1010101010 |
-- | 8 | D10.2 1010101010 | D10.2 1010101010 |
-- | 9 | D10.2 1010101010 | D10.2 1010101010 |
-- +----+--------------------+--------------------+
-- Patterns are transmitted LSB first.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity insert_training_pattern is
port (
clk : in std_logic;
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(79 downto 0) := (others => '0')
);
end insert_training_pattern;
architecture arch of insert_training_pattern is
signal state : std_logic_vector(3 downto 0) := "0000";
signal clock_train_meta : std_logic := '0';
signal clock_train_i : std_logic := '0';
signal align_train_meta : std_logic := '0';
signal align_train_i : std_logic := '0';
signal hold_at_state_one : std_logic_vector(9 downto 0) := "1111111111";
constant CODE_K28_5 : std_logic_vector(8 downto 0) := "110111100";
constant CODE_D11_6 : std_logic_vector(8 downto 0) := "011001011";
constant CODE_D10_2 : std_logic_vector(8 downto 0) := "001001010";
constant p0 : std_logic_vector(19 downto 0) := '0' & CODE_D11_6 & '1' & CODE_K28_5;
constant p1 : std_logic_vector(19 downto 0) := '0' & CODE_D11_6 & '0' & CODE_K28_5;
constant p2 : std_logic_vector(19 downto 0) := '0' & CODE_D10_2 & '0' & CODE_D10_2;
constant p3 : std_logic_vector(19 downto 0) := '0' & CODE_D10_2 & '0' & CODE_D10_2;
constant p4 : std_logic_vector(19 downto 0) := '0' & CODE_D10_2 & '0' & CODE_D10_2;
type a_delay_line is array (0 to 5) of std_logic_vector(79 downto 0);
signal delay_line : a_delay_line := (others => (others => '0'));
begin
out_data <= delay_line(5);
process(clk)
begin
if rising_edge(clk) then
-- Move the dalay line along
delay_line(1 to 5) <= delay_line(0 to 4);
delay_line(0) <= '0' & in_data(71 downto 63) & '0' & in_data(62 downto 54)
& '0' & in_data(53 downto 45) & '0' & in_data(44 downto 36)
& '0' & in_data(35 downto 27) & '0' & in_data(26 downto 18)
& '0' & in_data(17 downto 9) & '0' & in_data(8 downto 0);
-- Do we ened to hold at state 1 until valid data has filtered down the delay line?
if align_train_i = '1' or clock_train_i = '1' then
hold_at_state_one <= (others => '1');
else
hold_at_state_one <= '0' & hold_at_state_one(hold_at_state_one'high downto 1);
end if;
-- Do we need to overwrite the data in slot 5 with the sync patterns?
case state is
when x"5" => state <= x"4"; delay_line(5) <= p0 & p0 & p0 & p0;
when x"4" => state <= x"3"; delay_line(5) <= p1 & p1 & p1 & p1;
when x"3" => state <= x"2"; delay_line(5) <= p2 & p2 & p2 & p2;
when x"2" => state <= x"1"; delay_line(5) <= p3 & p3 & p3 & p3;
when x"1" => state <= x"0"; delay_line(5) <= p4 & p4 & p4 & p4;
if align_train_i = '1' then
state <= x"5";
elsif hold_at_state_one(0) = '1' then
state <= x"1";
end if;
when others => state <= x"0";
if align_train_i = '1' then
state <= x"5";
elsif hold_at_state_one(0) = '1' then
state <= x"1";
end if;
end case;
clock_train_meta <= clock_train;
clock_train_i <= clock_train_meta;
align_train_meta <= align_train;
align_train_i <= align_train_meta;
end if;
end process;
end architecture; | mit | 605832ac35a112b5f2e30f05fe8a6b94 | 0.491515 | 3.721245 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_routel.vhd | 1 | 7,442 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity tb_RoutEl is
end tb_RoutEl;
architecture arch of tb_RoutEl is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, inmux0, inmux1, outdirect,
outtri0, outtri1, outtri2);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data signals
signal Cfg : routConfigRec;
signal In0xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In1xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In2xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In3xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In4xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In5xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In6xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In7xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal OutxD : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out0xZ : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out1xZ : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out2xZ : std_logic_vector(DATAWIDTH-1 downto 0);
signal ProcElIn0xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal ProcElIn1xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal ProcElOutxD : std_logic_vector(DATAWIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : RoutEl
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ConfigxI => Cfg,
In0xDI => In0xD,
In1xDI => In1xD,
In2xDI => In2xD,
In3xDI => In3xD,
In4xDI => In4xD,
In5xDI => In5xD,
In6xDI => In6xD,
In7xDI => In7xD,
OutxDO => OutxD,
Out0xZO => Out0xZ,
Out1xZO => Out1xZ,
Out2xZO => Out2xZ,
ProcElIn0xDO => ProcElIn0xD,
ProcElIn1xDO => ProcElIn1xD,
ProcElOutxDI => ProcElOutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(10, DATAWIDTH));
In2xD <= std_logic_vector(to_unsigned(20, DATAWIDTH));
In3xD <= std_logic_vector(to_unsigned(30, DATAWIDTH));
In4xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
In5xD <= std_logic_vector(to_unsigned(50, DATAWIDTH));
In6xD <= std_logic_vector(to_unsigned(60, DATAWIDTH));
In7xD <= std_logic_vector(to_unsigned(70, DATAWIDTH));
ProcElOutxD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
tbStatus <= rst;
Cfg <= init_routConfig;
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= inmux0; -- test in mux 0
Cfg.Route0MuxS <= "000";
wait for CLK_PERIOD;
Cfg.Route0MuxS <= "001";
wait for CLK_PERIOD;
Cfg.Route0MuxS <= "010";
wait for CLK_PERIOD;
Cfg.Route0MuxS <= "011";
wait for CLK_PERIOD;
Cfg.Route0MuxS <= "100";
wait for CLK_PERIOD;
Cfg.Route0MuxS <= "101";
wait for CLK_PERIOD;
Cfg.Route0MuxS <= "110";
wait for CLK_PERIOD;
Cfg.Route0MuxS <= "111";
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_routConfig;
wait for CLK_PERIOD;
tbStatus <= inmux1; -- test in mux 1
Cfg.Route1MuxS <= "000";
wait for CLK_PERIOD;
Cfg.Route1MuxS <= "001";
wait for CLK_PERIOD;
Cfg.Route1MuxS <= "010";
wait for CLK_PERIOD;
Cfg.Route1MuxS <= "011";
wait for CLK_PERIOD;
Cfg.Route1MuxS <= "100";
wait for CLK_PERIOD;
Cfg.Route1MuxS <= "101";
wait for CLK_PERIOD;
Cfg.Route1MuxS <= "110";
wait for CLK_PERIOD;
Cfg.Route1MuxS <= "111";
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_routConfig;
wait for CLK_PERIOD;
tbStatus <= outdirect; -- test out
ProcElOutxD <= std_logic_vector(to_unsigned(11, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(22, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(33, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(44, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_routConfig;
ProcElOutxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= outtri0; -- test out tristate 0
Cfg.Tri0OExE <= '1';
ProcElOutxD <= std_logic_vector(to_unsigned(11, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(22, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(33, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_routConfig;
ProcElOutxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= outtri1; -- test out tristate 1
Cfg.Tri1OExE <= '1';
ProcElOutxD <= std_logic_vector(to_unsigned(11, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(22, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(33, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_routConfig;
ProcElOutxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= outtri2; -- test out tristate 2
Cfg.Tri2OExE <= '1';
ProcElOutxD <= std_logic_vector(to_unsigned(11, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(22, DATAWIDTH));
wait for CLK_PERIOD;
ProcElOutxD <= std_logic_vector(to_unsigned(33, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_routConfig;
ProcElOutxD <= (others => '0');
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | a50a9bfc33fbdb92a79a08d12d5327f8 | 0.55563 | 3.577885 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpDsp/unitDds/hdl/Dds-e.vhd | 1 | 2,145 | -------------------------------------------------------------------------------
-- Title : Direct Digital Synthesis
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : DDS with RAM Table, Table can be defined over MM Interface
-- The Phase Increment and Enable can also be set over an extra MM Interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use work.sin_4096.all;
entity Dds is
generic (
-- number of bits for the streaming interface
data_width_g : natural := 24;
-- amount of bits for the phase register
phase_bits_g : natural := 20;
-- phase register dither bist
phase_dither_g : natural := 8;
-- number of bits for the waveform rom entries
wave_table_width_g : natural := 14;
-- number of wave table entries
wave_table_len_g : natural := 4096;
-- number of bits to address the wave table
-- shoud be log dualis of wave_table_len_g
wave_table_addr_bits_g : natural := 12
);
port (
csi_clk : in std_logic;
rsi_reset_n : in std_logic;
-- sample strobe
coe_sample_strobe : in std_logic;
-- Avalon MM Slave Port s0 - used for dds table
avs_s0_write : in std_logic;
avs_s0_address : in std_logic_vector(wave_table_addr_bits_g-1 downto 0);
avs_s0_writedata : in std_logic_vector(31 downto 0);
-- Avalon MM Slave Port s1 - used for phase increment and enable
-- not enable also clear the phase register
-- address + 0 => enable register (1 bit) : '1' => enable, '0' => not enable
-- address + 1 => phase increment (phase_bits_g bits) => 0 no phase increment
avs_s1_write : in std_logic;
avs_s1_address : in std_logic;
avs_s1_writedata : in std_logic_vector(31 downto 0);
-- Avalon ST source
aso_data : out std_logic_vector(data_width_g-1 downto 0);
aso_valid : out std_logic
);
end entity Dds;
| gpl-3.0 | 46f4343b09b2554c5dfbedfcfdaba201 | 0.567366 | 3.871841 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/ipcore_dir/dualBRAM/example_design/dualBRAM_prod.vhd | 1 | 10,503 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: dualBRAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : dualBRAM.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 00
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY dualBRAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END dualBRAM_prod;
ARCHITECTURE xilinx OF dualBRAM_prod IS
COMPONENT dualBRAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : dualBRAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| mit | e192146912e98f74b9794568dd0f1703 | 0.489765 | 3.840219 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpDsp/unitWhiteNoise/hdl/WhiteNoise_tb.vhd | 1 | 3,337 | -------------------------------------------------------------------------------
-- Title : Testbench for design "WhiteNoise"
-- Project :
-------------------------------------------------------------------------------
-- File : WhiteNoise_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- Created : 2017-12-12
-- Last update: 2017-12-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-12-12 1.0 fxst Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Global.all;
-------------------------------------------------------------------------------
entity WhiteNoise_tb is
end entity WhiteNoise_tb;
-------------------------------------------------------------------------------
architecture bhv of WhiteNoise_tb is
constant strobe_time : time := 1 sec/real(44117);
-- component generics
constant data_width_g : natural := 24;
constant lfsr_length_g : natural := 24;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal coe_sample_strobe : std_logic;
signal avs_s0_write : std_logic;
signal avs_s0_writedata : std_logic_vector(31 downto 0);
signal aso_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_valid : std_logic;
begin -- architecture bhv
-- component instantiation
DUT: entity work.WhiteNoise
generic map (
data_width_g => data_width_g,
lfsr_length_g => lfsr_length_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
coe_sample_strobe => coe_sample_strobe,
avs_s0_write => avs_s0_write,
avs_s0_writedata => avs_s0_writedata,
aso_data => aso_data,
aso_valid => aso_valid);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
-- sample strobe generation
sample_strobe : process is
begin -- process
wait for strobe_time;
wait until rising_edge(csi_clk);
coe_sample_strobe <= '1';
wait until rising_edge(csi_clk);
coe_sample_strobe <= '0';
end process;
-- waveform generation
WaveGen_Proc: process
begin
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
avs_s0_write <= '0';
avs_s0_writedata <= (others => '-');
wait for 100 ns;
-- enable
avs_s0_write <= '1';
avs_s0_writedata(0) <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(0) <= '-';
wait for 50000 ns;
-- disable
avs_s0_write <= '1';
avs_s0_writedata(0) <= '0';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(0) <= '-';
wait for 50000 ns;
-- enable
avs_s0_write <= '1';
avs_s0_writedata(0) <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(0) <= '-';
wait;
end process WaveGen_Proc;
end architecture bhv;
| gpl-3.0 | d9d8ee6e0e7d35f0939e780e1422f565 | 0.471082 | 3.813714 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/unitFIR/hdl/tbFIR-Bhv-ea.vhd | 1 | 3,705 | -------------------------------------------------------------------------------
-- Title : Finite Impulse Response Filter
-- Author : Steiger Martin <[email protected]>
-------------------------------------------------------------------------------
-- Description : Simple FIR filter structure for damping, amplifying and
-- compounding audio signals -> TESTING UNIT
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; --try to use this library as much as possible.
use IEEE.fixed_pkg.all;
use work.pkgFIR.all;
use work.Global.all;
entity tbFIR is
end entity;
architecture Bhv of tbFIR is
constant cNumberOfAddressLines : natural := 4;
constant cDataWidth : natural := 24;
signal DataClk : std_ulogic := '0';
signal FIRClk : std_ulogic := '0';
signal DataIn : sfixed(-1 downto -24):= to_sfixed(0.0, -1, -24);
signal DataOut : real;
signal address : std_logic_vector(cNumberOfAddressLines-1 downto 0) := (others => '0');
signal avs_write : std_logic := cInactivated;
signal avs_writedata : std_logic_vector(31 downto 0) := (others => cInactivated);
signal avs_read : std_logic;
signal avs_readdata : std_logic_vector(31 downto 0);
signal asi_valid : std_logic := cInactivated;
signal asi_data : std_logic_vector(cDataWidth - 1 downto 0);
signal aso_valid : std_logic;
signal aso_data : std_logic_vector(cDataWidth - 1 downto 0);
signal reset : std_logic := cnInactivated;
subtype res_type is std_logic_vector (0 to asi_data'length-1);
begin
SineGen : entity work.sinewave(Behavioral)
port map(
clk => DataClk,
dataout => DataOut
);
DataIn <= to_sfixed(DataOut, 0, -23);
asi_data <= res_type(DataIn);
FIR : entity work.FIR(Rtl)
port map
(
csi_clk => FIRClk,
rsi_reset_n => reset,
avs_s0_address => address,
avs_s0_write => avs_write,
avs_s0_writedata => avs_writedata,
--avs_s0_read => avs_read,
avs_s0_readdata => avs_readdata,
-- AudioSignals: streaming interface
asi_valid => asi_valid,
asi_data => asi_data,
aso_valid => aso_valid,
aso_data => aso_data
);
VALIDSTROBE: entity work.StrobeGen(Rtl)
generic map (gClkFrequency => 50E6,
gStrobeCycleTime => 21 us)
port map(
iClk => FIRClk,
inResetAsync => reset,
oStrobe => asi_valid
);
--**********************************************
-- clock of the FIR => has to be way higher
-- than input data clock
--**********************************************
FIRCLOCK : process(FIRClk)
begin
FIRClk <= not(FIRClk) after 20 ns; --Abtastfrequenz des Filters => verwendeter FPGA-Takt
end process;
--**********************************************
-- clock of the input signal
--**********************************************
CLOCK : process(DataClk)
begin
DataClk <= not(DataClk) after 30 us; --Sinus-Gen: 30 Samples werden für volle Periode ausgegeben => clk/30 ergibt die Frequenz
end process;
Stimul : process is
begin
reset <= cnActivated after 1 us, cnInactivated after 10 us;
address <= "0000" after 100 us, "0001" after 200 us, "0010" after 300 us, "0011" after 400 us, "0100" after 500 us,
"0101" after 600 us, "0110" after 700 us, "0111" after 800 us, "1000" after 900 us, "1001" after 1000 us,
"1010" after 1100 us, "1011" after 1200 us, "1100" after 1300 us, "1101" after 1400 us, "1110" after 1500 us,
"1111" after 1600 us, "0000" after 2000 us;
avs_writedata <= "00000000000000000000000000000000" after 2100 us, "00000000001100000010000000100001" after 2300 us; -- 000000000,01000000000000000000000 0,3759804964
avs_write <= cActivated after 90 us, cInactivated after 2500 us;
wait;
end process;
end architecture;
| gpl-3.0 | 87f4cbcef957fbc18af11b37f2e6dc14 | 0.62041 | 3.564966 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/synlayQuartus/AudioCodecSubSytem/Platform_inst.vhd | 1 | 18,225 | component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
hex0_2_export : out std_logic_vector(20 downto 0); -- export
hex3_5_export : out std_logic_vector(20 downto 0); -- export
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic; -- SCLK
keys_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
xck_clk : out std_logic -- clk
);
end component Platform;
u0 : component Platform
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hex0_2_export => CONNECTED_TO_hex0_2_export, -- hex0_2.export
hex3_5_export => CONNECTED_TO_hex3_5_export, -- hex3_5.export
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO0, -- .hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO1, -- .hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO2, -- .hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO3, -- .hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_SS0, -- .hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK => CONNECTED_TO_hps_io_hps_io_qspi_inst_CLK, -- .hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO48, -- .hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
i2c_SDAT => CONNECTED_TO_i2c_SDAT, -- i2c.SDAT
i2c_SCLK => CONNECTED_TO_i2c_SCLK, -- .SCLK
keys_export => CONNECTED_TO_keys_export, -- keys.export
leds_export => CONNECTED_TO_leds_export, -- leds.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
switches_export => CONNECTED_TO_switches_export, -- switches.export
xck_clk => CONNECTED_TO_xck_clk -- xck.clk
);
| gpl-3.0 | ea1766c98aab3899a60a3af9b51e1cf2 | 0.475501 | 2.877329 | false | false | false | false |
plessl/zippy | vhdl/engine.vhd | 1 | 11,876 | ------------------------------------------------------------------------------
-- ZIPPY engine: - 2 input ports, 2 output ports (with enables)
-- - interconnect: some neighbours + busses
--
-- Project :
-- File : $Id: engine.vhd 241 2005-04-07 08:50:55Z plessl $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/02
-- $Id: engine.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- The engine is the core of the zippy architecture. It combines the cells
-- that form a grid, the local and bus interconnect between the cells, the io
-- ports and the corresponding io port controllers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.txt_util.all;
entity Engine is
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in engineConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
InPortxDI : in engineInoutDataType;
OutPortxDO : out engineInoutDataType;
InPortxEO : out std_logic_vector(N_IOP-1 downto 0);
OutPortxEO : out std_logic_vector(N_IOP-1 downto 0));
end Engine;
architecture simple of Engine is
signal GridInp : gridInputArray; -- GridInp(#row)(#cell).Inp*xD
signal GridOut : gridOutputArray; -- GridOut(#row)(#cell).Out*x{D,Z}
signal HBusNxZ : engineHBusNorthArray; -- all horiz north buses
signal HBusSxZ : engineHBusSouthArray; -- all horiz south buses
signal VBusExZ : engineVBusEastArray; -- all vertical east buses
type gridRomIOArray is array (N_ROWS-1 downto 0) of
data_vector(N_COLS-1 downto 0);
signal cellMemDataxDI : gridRomIOArray;
signal cellMemDataxDO : gridRomIOArray;
signal cellMemAddrxDO : gridRomIOArray;
signal cellMemCtrlxSO : gridRomIOArray;
-- IO signals to attach the ROM blocks, a ROM block is shared betweed all
-- cells in a row
signal RowRomRdAddrxZ : data_vector(N_ROWS-1 downto 0);
--signal RowRomWrDataxZ : data_vector(N_ROWS-1 downto 0);
--signal RowRomCtrlxZ : data_vector(N_ROWS-1 downto 0);
signal RowRomRdDataxZ : data_vector(N_ROWS-1 downto 0);
begin -- simple
-----------------------------------------------------------------------------
-- connect an ioport controller to every input and output of the
-- engine
-----------------------------------------------------------------------------
IOPortCtrlPort_gen : for prt in N_IOP-1 downto 0 generate
InPortCtrl : IOPortCtrl
generic map (
CCNTWIDTH => CCNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ConfigxI => ConfigxI.inportConf(prt),
CycleDnCntxDI => CycleDnCntxDI,
CycleUpCntxDI => CycleUpCntxDI,
PortxEO => InPortxEO(prt));
OutPortCtrl : IOPortCtrl
generic map (
CCNTWIDTH => CCNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ConfigxI => ConfigxI.outportConf(prt),
CycleDnCntxDI => CycleDnCntxDI,
CycleUpCntxDI => CycleUpCntxDI,
PortxEO => OutPortxEO(prt));
end generate IOPortCtrlPort_gen;
Gen_Rows : for i in N_ROWS-1 downto 0 generate
row_i : Row
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
CExEI => CExEI,
ConfigxI => ConfigxI.gridConf(i),
ClrContextxSI => ClrContextxSI,
ClrContextxEI => ClrContextxEI,
ContextxSI => ContextxSI,
InpxI => GridInp(i),
OutxO => GridOut(i),
MemDataxDI => cellMemDataxDI(i), -- input from MEM
MemAddrxDO => cellMemAddrxDO(i), -- addr output to MEM
MemDataxDO => cellMemDataxDO(i), -- data output to MEM
MemCtrlxSO => cellMemCtrlxSO(i) -- ctrl output to MEM
);
end generate Gen_Rows;
Gen_Roms : for r in N_ROWS-1 downto 0 generate
rom_i : Rom
generic map (
DEPTH => N_MEMDEPTH)
port map (
ConfigxI => ConfigxI.memoryConf(r),
RdAddrxDI => RowRomRdAddrxZ(r),
RdDataxDO => RowRomRdDataxZ(r));
end generate Gen_Roms;
-----------------------------------------------------------------------------
-- create tristate buffers for driving the HBusN buses from the input ports,
-- and add tristate buffers for driving the results from the HBusN buses to
-- the output ports
-----------------------------------------------------------------------------
TBufPort_gen : for prt in N_IOP-1 downto 0 generate
TBufrow_gen : for row in N_ROWS-1 downto 0 generate
TBufHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
-- connect input ports to HBusN
InpTBuf : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InPortxDI(prt),
OExEI => ConfigxI.inputDriverConf(prt)(row)(hbusn),
OutxZO => HBusNxZ(row)(hbusn));
-- connect HBusN to output ports
OutpTristateBuf : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => HBusNxZ(row)(hbusn),
OExEI => ConfigxI.outputDriverConf(prt)(row)(hbusn),
OutxZO => OutPortxDO(prt));
end generate TBufHBusN_gen;
end generate TBufrow_gen;
end generate TBufPort_gen;
-------------------------------------------------------------------------------
-- CELL OUTPUTS
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- create bus drivers the allow to write data from the cells to HBusN, HBusS
-- and VBusE buses.
-----------------------------------------------------------------------------
TBufConHBusRow_gen : for r in N_ROWS-1 downto 0 generate
TBufConHBusCol_gen : for c in N_COLS-1 downto 0 generate
-- output to HBusN
-- cells in row r drive the HBusN of row r+1
TBufConHBusHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
HBusNxZ((r+1) mod N_ROWS)(hbusn) <= GridOut(r)(c).HBusNxDZ(hbusn);
end generate TBufConHBusHBusN_gen;
-- output to HBusS
-- cell in row r drive the HBusS of the same row r
TBufConHBusHBusS_gen : for hbuss in N_HBUSS-1 downto 0 generate
HBusSxZ(r)(hbuss) <= GridOut(r)(c).HBusSxDZ(hbuss);
end generate TBufConHBusHBusS_gen;
-- output to VBusE
-- cells in column c drive the VBusE of column the same column c
TBufConHBusVBusE_gen : for vbuse in N_VBUSE-1 downto 0 generate
VBusExZ(c)(vbuse) <= GridOut(r)(c).VBusExDZ(vbuse);
end generate TBufConHBusVBusE_gen;
-- output to memory elements: all cells in a row drive the same bus,
-- since there is just a single shared memory block per ROW
-- arbitration of bus is handled with configuration. If a cell is
-- configured as alu_rom, it drives address data to this bus. Only one
-- cell per row is allowed to be configured as memory cell
RowRomRdAddrxZ(r) <= cellMemAddrxDO(r)(c);
-- for RAM, add other output signals here
end generate TBufConHBusCol_gen;
end generate TBufConHBusRow_gen;
-----------------------------------------------------------------------------
-- CELL INPUTS
-----------------------------------------------------------------------------
CellInpRow_gen : for r in N_ROWS-1 downto 0 generate
CellInpCol_gen : for c in N_COLS-1 downto 0 generate
-- local interconnect
GridInp(r)(c).LocalxDI(LOCAL_NW) <=
GridOut((r-1) mod N_ROWS)((c-1) mod N_COLS).LocalxDO; -- NW
GridInp(r)(c).LocalxDI(LOCAL_N) <=
GridOut((r-1) mod N_ROWS)((c+0) mod N_COLS).LocalxDO; -- N
GridInp(r)(c).LocalxDI(LOCAL_NE) <=
GridOut((r-1) mod N_ROWS)((c+1) mod N_COLS).LocalxDO; -- NE
GridInp(r)(c).LocalxDI(LOCAL_W) <=
GridOut((r+0) mod N_ROWS)((c-1) mod N_COLS).LocalxDO; -- W
GridInp(r)(c).LocalxDI(LOCAL_E) <=
GridOut((r+0) mod N_ROWS)((c+1) mod N_COLS).LocalxDO; -- E
GridInp(r)(c).LocalxDI(LOCAL_SW) <=
GridOut((r+1) mod N_ROWS)((c-1) mod N_COLS).LocalxDO; -- SW
GridInp(r)(c).LocalxDI(LOCAL_S) <=
GridOut((r+1) mod N_ROWS)((c+0) mod N_COLS).LocalxDO; -- S
GridInp(r)(c).LocalxDI(LOCAL_SE) <=
GridOut((r+1) mod N_ROWS)((c+1) mod N_COLS).LocalxDO; -- SE
-- FIXME FIXME FIXME: check feeding of singals to cells. Our testbenches
-- do not test the south and VBusE buses yet. create test for these buses.
-- bus interconnect
-- input from HBusN
CellInpHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
GridInp(r)(c).HBusNxDI(hbusn) <= HBusNxZ(r)(hbusn); -- HBusN inputs
end generate CellInpHBusN_gen;
-- input from HBusS
CellInpHBusS_gen : for hbuss in N_HBUSS-1 downto 0 generate
GridInp(r)(c).HBusSxDI(hbuss) <= HBusSxZ(r)(hbuss); -- HBusS inputs
end generate CellInpHBusS_gen;
-- input from VBusE
-- cells in column c read from VBusE of column c-1 (west)
-- VBusE inputs
CellInpVBusE_gen : for vbuse in N_VBUSE-1 downto 0 generate
GridInp(r)(c).VBusExDI(vbuse) <= VBusExZ((c-1) mod N_COLS)(vbuse);
end generate CellInpVBusE_gen;
-- cell input from MEM, drive all cell memory inputs in a row with the
-- same data, since there is a shared memory block per row
cellMemDataxDI(r)(c) <= RowRomRdDataxZ(r);
end generate CellInpCol_gen;
end generate CellInpRow_gen;
-----------------------------------------------------------------------------
-- add pulldowns to all buses (horizontal,vertical, memory);
-----------------------------------------------------------------------------
PullDownRows_gen : for r in N_ROWS-1 downto 0 generate
PullDownHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
begin
PullDownHBusN : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => HBusNxZ(r)(hbusn));
end generate PullDownHBusN_gen;
PullDownHBusS_gen : for hbuss in N_HBUSS-1 downto 0 generate
begin
PullDownHBusS : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => HBusSxZ(r)(hbuss));
end generate PullDownHBusS_gen;
end generate PullDownRows_gen;
PullDownCols_gen : for c in N_COLS-1 downto 0 generate
PullDownVBusE_gen : for vbuse in N_VBUSE-1 downto 0 generate
begin
PullDownVBusE : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => VBusExZ(c)(vbuse));
end generate PullDownVBusE_gen;
end generate PullDownCols_gen;
PullDownRowRomIn_gen : for r in N_ROWS-1 downto 0 generate
begin
PullDownRowRomAddrxDI : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => RowRomRdAddrxZ(r));
end generate PullDownRowRomIn_gen;
end simple;
| bsd-3-clause | 5c5daf5a6c7bb756804366b8198bea40 | 0.562647 | 3.668829 | false | false | false | false |
plessl/zippy | vhdl/mux.vhd | 1 | 5,662 | ------------------------------------------------------------------------------
-- Various multiplexers for the usage in the Zippy architecture
--
-- Project :
-- File : $Id: $
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
entity GMux is
generic (
NINP : integer; -- no. of inputs
WIDTH : integer); -- input width
port (
SelxSI : in std_logic_vector(log2(NINP)-1 downto 0);
InxDI : in std_logic_vector(NINP*WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end GMux;
architecture behav of GMux is
type inpArray is array (NINP-1 downto 0) of
std_logic_vector(WIDTH-1 downto 0);
signal Inp : inpArray;
begin -- behav
InputArray: for i in Inp'range generate
Inp(i) <= InxDI((i+1)*WIDTH-1 downto i*WIDTH);
end generate InputArray;
OutxDO <= Inp(to_integer(unsigned(SelxSI)));
end behav;
------------------------------------------------------------------------------
-- 2:1 Multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Mux2to1 is
generic (
WIDTH : integer);
port (
SelxSI : in std_logic;
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end Mux2to1;
architecture simple of Mux2to1 is
begin
with SelxSI select
OutxDO <=
In0xDI when '0',
In1xDI when '1',
In0xDI when others;
end simple;
------------------------------------------------------------------------------
-- 4:1 Multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Mux4to1 is
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(1 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end Mux4to1;
architecture simple of Mux4to1 is
begin -- simple
with SelxSI select
OutxDO <=
In0xDI when "00",
In1xDI when "01",
In2xDI when "10",
In3xDI when "11",
In0xDI when others;
end simple;
------------------------------------------------------------------------------
-- 8:1 Multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8to1 is
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(2 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
In4xDI : in std_logic_vector(WIDTH-1 downto 0);
In5xDI : in std_logic_vector(WIDTH-1 downto 0);
In6xDI : in std_logic_vector(WIDTH-1 downto 0);
In7xDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end Mux8to1;
architecture simple of Mux8to1 is
begin -- simple
with SelxSI select
OutxDO <=
In0xDI when O"0",
In1xDI when O"1",
In2xDI when O"2",
In3xDI when O"3",
In4xDI when O"4",
In5xDI when O"5",
In6xDI when O"6",
In7xDI when O"7",
In0xDI when others;
end simple;
------------------------------------------------------------------------------
-- 16:1 Multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux16to1 is
generic (
WIDTH : integer);
port (
SelxSI : in std_logic_vector(3 downto 0);
In0xDI : in std_logic_vector(WIDTH-1 downto 0);
In1xDI : in std_logic_vector(WIDTH-1 downto 0);
In2xDI : in std_logic_vector(WIDTH-1 downto 0);
In3xDI : in std_logic_vector(WIDTH-1 downto 0);
In4xDI : in std_logic_vector(WIDTH-1 downto 0);
In5xDI : in std_logic_vector(WIDTH-1 downto 0);
In6xDI : in std_logic_vector(WIDTH-1 downto 0);
In7xDI : in std_logic_vector(WIDTH-1 downto 0);
In8xDI : in std_logic_vector(WIDTH-1 downto 0);
In9xDI : in std_logic_vector(WIDTH-1 downto 0);
InAxDI : in std_logic_vector(WIDTH-1 downto 0);
InBxDI : in std_logic_vector(WIDTH-1 downto 0);
InCxDI : in std_logic_vector(WIDTH-1 downto 0);
InDxDI : in std_logic_vector(WIDTH-1 downto 0);
InExDI : in std_logic_vector(WIDTH-1 downto 0);
InFxDI : in std_logic_vector(WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end Mux16to1;
architecture simple of Mux16to1 is
begin -- simple
with SelxSI select
OutxDO <=
In0xDI when "0000",
In1xDI when "0001",
In2xDI when "0010",
In3xDI when "0011",
In4xDI when "0100",
In5xDI when "0101",
In6xDI when "0110",
In7xDI when "0111",
In8xDI when "1000",
In9xDI when "1001",
InAxDI when "1010",
InBxDI when "1011",
InCxDI when "1100",
InDxDI when "1101",
InExDI when "1110",
InFxDI when "1111",
In0xDI when others;
end simple;
| bsd-3-clause | 477ed583c0bb2171cb8402131663bf41 | 0.555104 | 3.380299 | false | false | false | false |
bver/GERET | sample/vhdl_design/adder_tb.vhdl | 1 | 2,434 | -- Adapted from the original source:
-- http://ghdl.free.fr/ghdl/A-full-adder.html
use std.textio.all; -- Imports the standard textio package.
-- A testbench has no ports.
entity adder_tb is
end adder_tb;
architecture behav of adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end component;
-- Specifies which entity is bound with the component.
for adder_0: adder use entity work.adder;
signal i0, i1, ci, s, co : bit;
begin
-- Component instantiation.
adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
s => s, co => co);
-- This process does the real job.
process
type pattern_type is record
-- The inputs of the adder.
i0, i1, ci : bit;
-- The expected outputs of the adder.
s, co : bit;
end record;
variable cnt : integer range 0 to 256 :=0;
variable my_line : line;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '0', '0'),
('0', '0', '1', '1', '0'),
('0', '1', '0', '1', '0'),
('0', '1', '1', '0', '1'),
('1', '0', '0', '1', '0'),
('1', '0', '1', '0', '1'),
('1', '1', '0', '0', '1'),
('1', '1', '1', '1', '1'));
begin
-- Check each pattern.
for i in patterns'range loop
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
wait for 1 ns;
if s = patterns(i).s then
cnt := cnt + 1;
end if;
if co = patterns(i).co then
cnt := cnt + 1;
end if;
end loop;
-- Write the fitness value to stdout:
write(my_line, cnt);
writeline (output, my_line);
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
| mit | 240abe20b9a95fb5703e9091630ca4e0 | 0.43673 | 3.996716 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt_tpsched/tstadpcm_virt_tpsched_cfg.vhd | 2 | 23,508 | ------------------------------------------------------------------------------
-- Configuration for ADPCM application with virtualized execution on a
-- 4x4 zippy array
--
-- File : $URL: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/27
-- $Id: $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTADPCM_VIRT is
function tstadpcmcfg_p0 return engineConfigRec;
function tstadpcmcfg_p1 return engineConfigRec;
function tstadpcmcfg_p2 return engineConfigRec;
end CfgLib_TSTADPCM_VIRT;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTADPCM_VIRT is
---------------------------------------------------------------------------
-- ROM DATA
---------------------------------------------------------------------------
type indextable_arr is array (0 to 15) of integer;
constant INDEXTABLE : indextable_arr := (
-1, -1, -1, -1, 2, 4, 6, 8,
-1, -1, -1, -1, 2, 4, 6, 8
);
type stepsizetable_arr is array (0 to 88) of integer;
constant STEPSIZETABLE : stepsizetable_arr := (
7, 8, 9, 10, 11, 12, 13, 14, 16, 17,
19, 21, 23, 25, 28, 31, 34, 37, 41, 45,
50, 55, 60, 66, 73, 80, 88, 97, 107, 118,
130, 143, 157, 173, 190, 209, 230, 253, 279, 307,
337, 371, 408, 449, 494, 544, 598, 658, 724, 796,
876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066,
2272, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358,
5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899,
15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767
);
----------------------------------------------------------------------------
-- tstadpcm partition p0 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p0 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 0 ###################
-- c_0_1 op4a
cfg.gridConf(0)(1).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_CONST;
cfg.gridConf(0)(1).procConf.ConstOpxD := i2cfgconst(88);
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(1).procConf.ConstOpxD := i2cfgconst(88);
-- i.2
cfg.gridConf(0)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(2).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
-- c_1_0 op4b
cfg.gridConf(1)(0).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(1)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(1)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(0).procConf.ConstOpxD := i2cfgconst(0);
-- i.2
cfg.gridConf(1)(0).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(2).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(1)(0).procConf.OutMuxS := O_NOREG;
-- c_1_1 op4c
cfg.gridConf(1)(1).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(1).LocalxE(LOCAL_N) := '1';
-- i.2
cfg.gridConf(1)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(2).LocalxE(LOCAL_SE) := '1';
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
-- c_2_0 op1
cfg.gridConf(2)(0).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(2)(0).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(2)(0).routConf.i(1).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(2)(0).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(0).routConf.o.HBusSxE(1) := '1';
-- c_2_1 op19
cfg.gridConf(2)(1).procConf.AluOpxS := ALU_OP_ROM;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op2
cfg.gridConf(2)(2).procConf.AluOpxS := ALU_OP_GT;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(2).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(2).procConf.ConstOpxD := i2cfgconst(88);
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op3
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_LT;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(3).procConf.ConstOpxD := i2cfgconst(0);
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
-- c_3_0 op0
cfg.gridConf(3)(0).procConf.AluOpxS := ALU_OP_ROM;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(0).routConf.i(0).HBusNxE(1) := '1';
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 opt120
cfg.gridConf(3)(1).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(3)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- c_3_2 feedthrough_c_3_2
cfg.gridConf(3)(2).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- input drivers
cfg.inputDriverConf(0)(3)(1) := '1';
-- output drivers
-- ############# end configuration of partition 0 ###################
-- initialize ROM
-- ROM index table (op0) is mapped to cell c_3_0
for i in INDEXTABLE'range loop
cfg.memoryConf(3)(i) :=
std_logic_vector(to_signed(INDEXTABLE(i), DATAWIDTH));
end loop; -- i
-- ROM stepsize table (op19) is mapped to cell c_2_1
for i in STEPSIZETABLE'range loop
cfg.memoryConf(2)(i) :=
std_logic_vector(to_signed(STEPSIZETABLE(i), DATAWIDTH));
end loop; -- i
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstadpcmcfg_p0;
----------------------------------------------------------------------------
-- tstadpcm partition p1 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p1 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 1 ###################
-- c_0_0 opt232
cfg.gridConf(0)(0).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(0)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- c_0_1 op13
cfg.gridConf(0)(1).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(0)(1).routConf.i(1).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
-- c_0_2 op14
cfg.gridConf(0)(2).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(0)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(0)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(1).LocalxE(LOCAL_W) := '1';
-- i.2
cfg.gridConf(0)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(2).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(2).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(2).routConf.o.VBusExE(1) := '1';
-- c_0_3 op6
cfg.gridConf(0)(3).procConf.AluOpxS := ALU_OP_AND;
-- i.0
cfg.gridConf(0)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(3).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(0)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(3).procConf.ConstOpxD := i2cfgconst(7);
-- o.0
cfg.gridConf(0)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(3).routConf.o.HBusNxE(0) := '1';
-- c_1_0 opt230
cfg.gridConf(1)(0).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(1)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- c_1_1 op8
cfg.gridConf(1)(1).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(1).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
cfg.gridConf(1)(1).routConf.o.HBusNxE(0) := '1';
-- c_1_2 op15
cfg.gridConf(1)(2).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_S) := '1';
-- o.0
cfg.gridConf(1)(2).procConf.OutMuxS := O_NOREG;
-- c_1_3 op9
cfg.gridConf(1)(3).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(3).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(1)(3).procConf.OutMuxS := O_NOREG;
-- c_2_0 opt231
cfg.gridConf(2)(0).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- c_2_1 op17
cfg.gridConf(2)(1).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).HBusSxE(0) := '1';
-- i.1
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op11
cfg.gridConf(2)(2).procConf.AluOpxS := ALU_OP_SRL;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(2).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op16
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(0).VBusExE(1) := '1';
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(1).LocalxE(LOCAL_NW) := '1';
-- i.2
cfg.gridConf(2)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(2).HBusNxE(0) := '1';
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(3).routConf.o.HBusSxE(0) := '1';
-- c_3_0 op10
cfg.gridConf(3)(0).procConf.AluOpxS := ALU_OP_SRL;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(0).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(3)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(0).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 opt120
cfg.gridConf(3)(1).procConf.AluOpxS := ALU_OP_PASS0;
-- o.0
cfg.gridConf(3)(1).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(3)(1).procConf.OutCtxRegSelxS := i2ctx(0);
cfg.gridConf(3)(1).routConf.o.HBusSxE(1) := '1';
-- c_3_2 op7
cfg.gridConf(3)(2).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- i.1
cfg.gridConf(3)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(2).procConf.ConstOpxD := i2cfgconst(4);
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- c_3_3 op12
cfg.gridConf(3)(3).procConf.AluOpxS := ALU_OP_SRL;
-- i.0
cfg.gridConf(3)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(3).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(3)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(3).procConf.ConstOpxD := i2cfgconst(3);
-- o.0
cfg.gridConf(3)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(3).routConf.o.HBusNxE(0) := '1';
-- input drivers
cfg.inputDriverConf(0)(0)(1) := '1';
-- output drivers
-- ############# end configuration of partition 1 ###################
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstadpcmcfg_p1;
----------------------------------------------------------------------------
-- tstadpcm partition p2 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p2 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 2 ###################
-- c_0_0 opt232
cfg.gridConf(0)(0).procConf.AluOpxS := ALU_OP_PASS0;
-- o.0
cfg.gridConf(0)(0).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(0)(0).procConf.OutCtxRegSelxS := i2ctx(1);
-- c_0_1 op22
cfg.gridConf(0)(1).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(1).HBusNxE(0) := '1';
-- i.2
cfg.gridConf(0)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(2).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(1).routConf.o.HBusNxE(0) := '1';
-- c_0_2 op25b
cfg.gridConf(0)(2).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(0)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(0)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(2).procConf.ConstOpxD := i2cfgconst(32768);
-- i.2
cfg.gridConf(0)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(2).LocalxE(LOCAL_SE) := '1';
-- o.0
cfg.gridConf(0)(2).procConf.OutMuxS := O_NOREG;
-- c_0_3 obuf
cfg.gridConf(0)(3).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(0)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(0)(3).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(0)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(3).routConf.o.HBusNxE(1) := '1';
-- c_1_0 opt230
cfg.gridConf(1)(0).procConf.AluOpxS := ALU_OP_PASS0;
-- o.0
cfg.gridConf(1)(0).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(1)(0).procConf.OutCtxRegSelxS := i2ctx(1);
cfg.gridConf(1)(0).routConf.o.VBusExE(1) := '1';
-- c_1_1 op24
cfg.gridConf(1)(1).procConf.AluOpxS := ALU_OP_LT;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(1).procConf.ConstOpxD := i2cfgconst(-32768);
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
-- c_1_2 op25c
cfg.gridConf(1)(2).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_SE) := '1';
-- i.2
cfg.gridConf(1)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(2).LocalxE(LOCAL_W) := '1';
-- o.0
cfg.gridConf(1)(2).procConf.OutMuxS := O_NOREG;
-- c_1_3 op23
cfg.gridConf(1)(3).procConf.AluOpxS := ALU_OP_GT;
-- i.0
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(3).procConf.ConstOpxD := i2cfgconst(32767);
-- o.0
cfg.gridConf(1)(3).procConf.OutMuxS := O_NOREG;
-- c_2_0 opt231
cfg.gridConf(2)(0).procConf.AluOpxS := ALU_OP_PASS0;
-- o.0
cfg.gridConf(2)(0).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(2)(0).procConf.OutCtxRegSelxS := i2ctx(1);
-- c_2_1 op20
cfg.gridConf(2)(1).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op21
cfg.gridConf(2)(2).procConf.AluOpxS := ALU_OP_SUB;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(2).routConf.i(1).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op25a
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_CONST;
cfg.gridConf(2)(3).procConf.ConstOpxD := i2cfgconst(-32767);
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(3).procConf.ConstOpxD := i2cfgconst(-32767);
-- i.2
cfg.gridConf(2)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(2).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
-- c_3_0 op5
cfg.gridConf(3)(0).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(0).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(3)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(0).procConf.ConstOpxD := i2cfgconst(8);
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 op18
cfg.gridConf(3)(1).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(3)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- i.1
cfg.gridConf(3)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(1).VBusExE(1) := '1';
-- i.2
cfg.gridConf(3)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(2).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(3)(1).procConf.OutMuxS := O_NOREG;
-- c_3_2 feedthrough_c_3_2
cfg.gridConf(3)(2).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- c_3_3 feedthrough_c_3_3
cfg.gridConf(3)(3).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(3)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(3).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(3)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(3).routConf.o.HBusNxE(0) := '1';
-- input drivers
cfg.inputDriverConf(0)(3)(1) := '1';
-- output drivers
cfg.outputDriverConf(1)(1)(1) := '1';
-- ############# end configuration of partition 2 ###################
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_ON;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_ON;
return cfg;
end tstadpcmcfg_p2;
end CfgLib_TSTADPCM_VIRT;
| bsd-3-clause | 23b3f2428936f7fa5306c829865210a9 | 0.510082 | 2.754306 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/data_scheduler.vhd | 1 | 3,132 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:23:55 10/11/2015
-- Design Name:
-- Module Name: data_scheduler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity data_scheduler is
Port ( clk : in STD_LOGIC;
toggle_on_end_of_hblank : in STD_LOGIC;
pixel_count : in STD_LOGIC_VECTOR (11 downto 0);
lanes_in_use : in STD_LOGIC_VECTOR (2 downto 0);
RGB_nYCC : in STD_LOGIC;
hblank_or_vblank : in STD_LOGIC;
pix_per_ms : in STD_LOGIC_VECTOR (19 downto 0);
------
out0_BE : out STD_LOGIC;
out0_PixData : out STD_LOGIC;
out0_FS : out STD_LOGIC;
out0_FE : out STD_LOGIC;
out0_BS : out STD_LOGIC;
----
out1_BE : out STD_LOGIC;
out1_PixData : out STD_LOGIC;
out1_FS : out STD_LOGIC;
out1_FE : out STD_LOGIC;
out1_BS : out STD_LOGIC);
end data_scheduler;
architecture Behavioral of data_scheduler is
-- How many 135MHz cycles have been seen this line
signal counter : unsigned(12 downto 0);
constant cZo : std_logic_vector(2 downto 0) := "000";
constant cBE : std_logic_vector(2 downto 0) := "001";
constant cPD : std_logic_vector(2 downto 0) := "010";
constant cFS : std_logic_vector(2 downto 0) := "011";
constant cFE : std_logic_vector(2 downto 0) := "100";
constant cBS : std_logic_vector(2 downto 0) := "101";
-- schedule :=
-- -- 1 & 0, 3 & 2, 5 & 4, 7 & 6, 9 & 8, 11 & 10, 13 & 12, 15 & 14, 17 & 16, 19 & 18, 21 & 20, 23 & 22, 25 & 24, 27 & 26, 29 & 28, 31 & 30, 33 & 32, 35 & 34, 37 & 36, 39 & 38, 41 & 40, 43 & 42, 45 & 44, 47 & 46, 49 & 48, 51 & 10, 53 & 52, 55 & 54, 57 & 56, 59 & 58, 61 & 60, 63 & 62,
-- cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cZo&cZo, cBE&cZo,
begin
process(clk)
begin
if rising_edge(clk) then
if toggle_on_end_of_hblank_synced /= toggle_on_end_of_hblank_synced_last then
counter <= 0;
active_period <= '1';
else
counter <= counter + 1;
end if;
end if;
end process;
end Behavioral;
| mit | 9a2fb0d3064e0110092af0a83829701c | 0.504789 | 3.205732 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/insert_main_stream_attrbutes_one_channel.vhd | 1 | 13,069 | ----------------------------------------------------------------------------------
-- Module Name: insert_main_stream_attrbutes - Behavioral
--
-- Description: Add the Main Stream Attributes into a DisplayPort stream.
--
-- Places the MSA after the first VIB-ID which has the vblank
-- bit set (after allowing for repeated VB-ID/Mvid/Maud sequences
--
-- The MSA requires up to 39 cycles (for signal channel) or
-- Only 12 cycles (for four channels).
--
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity insert_main_stream_attrbutes_one_channel is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flag_YCC_colour_709 : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0) := (others => '0'));
end entity;
architecture arch of insert_main_stream_attrbutes_one_channel is
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
type t_msa is array(0 to 39) of std_logic_vector(8 downto 0);
signal msa : t_msa := (others => (others => '0'));
signal Misc0 : std_logic_vector(7 downto 0);
signal Misc1 : std_logic_vector(7 downto 0);
signal count : signed(4 downto 0) := (others => '0');
signal last_was_bs : std_logic := '0';
signal armed : std_logic := '0';
begin
with bits_per_colour select misc0(7 downto 5)<= "000" when "00110", -- 6 bpc
"001" when "01000", -- 8 bpp
"010" when "01010", -- 10 bpp
"011" when "01100", -- 12 bpp
"100" when "10000", -- 16 bpp
"001" when others; -- default to 8
misc0(4) <= flag_YCC_colour_709;
misc0(3) <= flag_range_reduced;
misc0(2 downto 1) <= "00" when flag_YCCnRGB = '0' else -- RGB444
"01" when flag_422n444 = '1' else -- YCC422
"10"; -- YCC444
misc0(0) <= flag_sync_clock;
misc1 <= "00000" & flags_3d_Indicators & flag_interlaced_even;
--------------------------------------------
-- Build data fields for 4 lane case.
-- SS and SE symbols are set in declaration.
--------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- default to copying the input data across
out_data <= in_data;
case count is
when "00000" => NULL; -- while waiting for BS symbol
when "00001" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00010" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00011" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00100" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00101" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00110" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00111" => out_data(17 downto 0) <= SS & SS;
when "01000" => out_data(17 downto 0) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "01001" => out_data(17 downto 0) <= "0" & "0000" & H_total(11 downto 8) & "0" & M_value( 7 downto 0);
when "01010" => out_data(17 downto 0) <= "0" & "0000" & V_total(11 downto 8) & "0" & H_total( 7 downto 0);
when "01011" => out_data(17 downto 0) <= "0" & H_vsync_active_high & "000" & H_sync_width(11 downto 8) & "0" & V_total( 7 downto 0);
when "01100" => out_data(17 downto 0) <= "0" & M_value(23 downto 16) & "0" & H_sync_width(7 downto 0);
when "01101" => out_data(17 downto 0) <= "0" & M_value( 7 downto 0) & "0" & M_value(15 downto 8);
when "01110" => out_data(17 downto 0) <= "0" & H_start( 7 downto 0) & "0" & "0000" & H_start(11 downto 8);
when "01111" => out_data(17 downto 0) <= "0" & V_start( 7 downto 0) & "0" & "0000" & V_start(11 downto 8);
when "10000" => out_data(17 downto 0) <= "0" & V_sync_width(7 downto 0) & "0" & V_vsync_active_high & "000" & V_sync_width(11 downto 8);
when "10001" => out_data(17 downto 0) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "10010" => out_data(17 downto 0) <= "0" & "0000" & H_visible(11 downto 8) & "0" & M_value( 7 downto 0);
when "10011" => out_data(17 downto 0) <= "0" & "0000" & V_visible(11 downto 8) & "0" & H_visible( 7 downto 0);
when "10100" => out_data(17 downto 0) <= "0" & "00000000" & "0" & V_visible( 7 downto 0);
when "10101" => out_data(17 downto 0) <= "0" & M_value(23 downto 16) & "0" & "00000000";
when "10110" => out_data(17 downto 0) <= "0" & M_value( 7 downto 0) & "0" & M_value(15 downto 8);
when "10111" => out_data(17 downto 0) <= "0" & N_value(15 downto 8) & "0" & N_value(23 downto 16);
when "11000" => out_data(17 downto 0) <= "0" & Misc0 & "0" & N_value( 7 downto 0);
when "11001" => out_data(17 downto 0) <= "0" & "00000000" & "0" & Misc1;
when "11010" => out_data(17 downto 0) <= "0" & "00000000" & SE;
when others => NULL;
end case;
-----------------------------------------------------------
-- Update the counter
------------------------------------------------------------
if count = "11011" then
count <= (others => '0');
elsif count /= "00000" then
count <= count + 1;
end if;
---------------------------------------------
-- Was the BS in the channel 0's data1 symbol
-- during the last cycle?
---------------------------------------------
if last_was_bs = '1' then
---------------------------------
-- This time in_ch0_data0 = VB-ID
-- First, see if this is a line in
-- the VSYNC
---------------------------------
if in_data(0) = '1' then
if armed = '1' then
count <= "00001";
armed <= '0';
end if;
else
-- Not in the Vblank. so arm the trigger to send the MSA
-- when the next BS with Vblank asserted occurs
armed <= active;
end if;
end if;
---------------------------------------------
-- Is the BS in the channel 0's data0 symbol?
---------------------------------------------
if in_data(8 downto 0) = BS then
---------------------------------
-- This time in_data(17 downto 9) = VB-ID
-- First, see if this is a line in
-- the VSYNC
---------------------------------
if in_data(9) = '1' then
if armed = '1' then
count <= "00001";
armed <= '0';
end if;
else
-- Not in the Vblank. so arm the trigger to send the MSA
-- when the next BS with Vblank asserted occurs
armed <= '1';
end if;
end if;
---------------------------------------------
-- Is the BS in the channel 0's data1 symbol?
---------------------------------------------
if in_data(17 downto 9) = BS then
last_was_bs <= '1';
else
last_was_bs <= '0';
end if;
end if;
end process;
end architecture;
| mit | efcdec566c6643160ae590473e491b74 | 0.427271 | 4.338977 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/edid_decode.vhd | 1 | 6,768 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: edid_decode - Behavioral
--
-- Description: Extract the default video timing and
-- modes from a stream of EDID data.
--
-- The Stream must end with EDID_addr of 0xFF so that the
-- checksum can be verified and valid asserted
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity edid_decode is
port ( clk : in std_logic;
edid_de : in std_logic;
edid_data : in std_logic_vector(7 downto 0);
edid_addr : in std_logic_vector(7 downto 0);
invalidate : in std_logic;
valid : out std_logic := '0';
support_RGB444 : out std_logic := '0';
support_YCC444 : out std_logic := '0';
support_YCC422 : out std_logic := '0';
pixel_clock_x10k : out std_logic_vector(15 downto 0) := (others => '0');
h_visible_len : out std_logic_vector(11 downto 0) := (others => '0');
h_blank_len : out std_logic_vector(11 downto 0) := (others => '0');
h_front_len : out std_logic_vector(11 downto 0) := (others => '0');
h_sync_len : out std_logic_vector(11 downto 0) := (others => '0');
v_visible_len : out std_logic_vector(11 downto 0) := (others => '0');
v_blank_len : out std_logic_vector(11 downto 0) := (others => '0');
v_front_len : out std_logic_vector(11 downto 0) := (others => '0');
v_sync_len : out std_logic_vector(11 downto 0) := (others => '0');
interlaced : out std_logic := '0');
end edid_decode;
architecture arch of edid_decode is
signal checksum : unsigned(7 downto 0);
signal checksum_next : unsigned(7 downto 0);
begin
checksum_next <= checksum + unsigned(edid_data);
clk_proc: process(clk)
begin
if rising_edge(clk) then
if edid_de = '1' then
checksum <= checksum_next;
valid <= '0';
case edid_addr is
when x"00" => -- reset the checksum
checksum <= unsigned(edid_data);
when x"18" => -- Colour modes supported
support_rgb444 <= '1';
support_ycc444 <= edid_data(3);
support_ycc422 <= edid_data(4);
-- Timing 0 - 1
when x"36" => pixel_clock_x10k( 7 downto 0) <= edid_data;
when x"37" => pixel_clock_x10k(15 downto 8) <= edid_data;
-- Timing 2 - 4
when x"38" => h_visible_len( 7 downto 0) <= edid_data;
when x"39" => h_blank_len(7 downto 0) <= edid_data;
when x"3A" => h_visible_len(11 downto 8) <= edid_data(7 downto 4);
h_blank_len(11 downto 8) <= edid_data(3 downto 0);
-- Timing 5 - 7
when x"3B" => v_visible_len( 7 downto 0) <= edid_data;
when x"3C" => v_blank_len(7 downto 0) <= edid_data;
when x"3D" => v_visible_len(11 downto 8) <= edid_data(7 downto 4);
v_blank_len(11 downto 8) <= edid_data(3 downto 0);
-- Timing 8 - 11
when x"3E" => h_front_len( 7 downto 0) <= edid_data;
when x"3F" => h_sync_len( 7 downto 0) <= edid_data;
when x"40" => v_front_len( 3 downto 0) <= edid_data(7 downto 4);
v_sync_len( 3 downto 0) <= edid_data(3 downto 0);
when x"41" => h_front_len( 9 downto 8) <= edid_data(7 downto 6);
h_sync_len( 9 downto 8) <= edid_data(5 downto 4);
v_front_len( 5 downto 4) <= edid_data(3 downto 2);
v_sync_len( 5 downto 4) <= edid_data(1 downto 0);
-- Timing 11-16 not used - that is the physical
-- size and boarder.
when x"7F" => if checksum_next = x"00" then
valid <= '1';
end if;
when others => NULL;
end case;
------------------------------------------------
-- Allow for an external event to invalidate the
-- outputs (e.g. hot plug)
------------------------------------------------
if invalidate = '1' then
valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
| mit | b262f7918480dca50f2faf90f9554024 | 0.523936 | 3.815107 | false | false | false | false |
plessl/zippy | vhdl/txt_util.vhd | 1 | 13,747 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text : string);
-- prints the message when active
-- useful for debug switches
procedure print(active : boolean; text : string);
-- converts std_logic into a character
function chr(sl : std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv : std_logic_vector) return string;
-- converts boolean into a string
function str(b : boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int : integer) return character;
-- converts integer into string using specified base
function str(int : integer; base : integer) return string;
-- converts integer to string, using base 10
function str(int : integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv : std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c : character) return character;
-- convert a character to lower case
function to_lower(c : character) return character;
-- convert a string to upper case
function to_upper(s : string) return string;
-- convert a string to lower case
function to_lower(s : string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c : character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string);
-- print string to a file and start new line
procedure print(file out_file : text;
new_string : in string);
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text : string) is
variable msg_line : line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active : boolean; text : string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl : std_logic) return character is
variable c : character;
begin
case sl is
when 'U' => c := 'U';
when 'X' => c := 'X';
when '0' => c := '0';
when '1' => c := '1';
when 'Z' => c := 'Z';
when 'W' => c := 'W';
when 'L' => c := 'L';
when 'H' => c := 'H';
when '-' => c := '-';
when others => c := '?';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string is
variable s : string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv : std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b : boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int : integer) return character is
variable c : character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int : integer; base : integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer := 1;
variable power : integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int : integer) return string is
begin
return str(int, 10);
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c : character) return character is
variable u : character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c : character) return character is
variable l : character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s : string) return string is
variable uppercase : string (s'range);
begin
for i in s'range loop
uppercase(i) := to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s : string) return string is
variable lowercase : string (s'range);
begin
for i in s'range loop
lowercase(i) := to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c : character) return std_logic is
variable sl : std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector is
variable slv : std_logic_vector(s'high-s'low downto 0);
variable k : integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string) is
variable l : line;
variable c : character;
variable is_string : boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file : text;
new_string : in string) is
variable l : line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character) is
variable l : line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file : text;
new_string : in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| bsd-3-clause | 579cc93898a20c50add734db8c7a3ddd | 0.500109 | 3.529397 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/spartan6/gtp_refclock_only.vhd | 1 | 33,588 | ----------------------------------------------------------------------------------
-- Module Name: gtp_refclock_only - Behavioral
--
-- Description: Receive the reference clock and pass it over to the other bank
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity gtp_refclock_only is
Port ( clk : in STD_LOGIC;
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
testlock0 : out STD_LOGIC;
testlock1 : out STD_LOGIC;
out_ref_clk0 : out STD_LOGIC;
out_ref_clk1 : out STD_LOGIC);
end gtp_refclock_only;
architecture Behavioral of gtp_refclock_only is
signal refclk0 : std_logic;
signal refclk1 : std_logic;
begin
------------- GT txdata_i Assignments for 20 bit datapath -------
I_IBUFDS_0 : IBUFDS
port map
(
O => refclk0,
I => refclk0_p,
IB => refclk0_n
);
I_IBUFDS_1 : IBUFDS
port map
(
O => refclk1,
I => refclk1_p,
IB => refclk1_n
);
--------------------------------------------------------------------
-- From here down this is all crap that is just to get the refclock1
-- out of the GTPA1_DUAL and across to the other transceiver block
---------------------------------------------------------------------
gtpa1_dual_i:GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_TX_ELEC_IDLE_LEVEL => ("Z"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("100"),
SIM_REFCLK1_SOURCE => ("100"),
SIM_GTPRESET_SPEEDUP => (1),
CLK25_DIVIDER_0 => (5),
CLK25_DIVIDER_1 => (5),
PLL_DIVSEL_FB_0 => (2),
PLL_DIVSEL_FB_1 => (2),
PLL_DIVSEL_REF_0 => (1),
PLL_DIVSEL_REF_1 => (1),
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
--PLL Attributes
CLKINDC_B_0 => (TRUE),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (1),
PLL_SATA_0 => (FALSE),
PLL_SOURCE_0 => ("PLL0"), -- Source from PLL 0
PLL_TXDIVSEL_OUT_0 => (1),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (TRUE),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (1),
PLL_SATA_1 => (FALSE),
PLL_SOURCE_1 => ("PLL1"), -- Source from PLL1
PLL_TXDIVSEL_OUT_1 => (1),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"00000a000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
TX_TDCC_CFG_0 => ("11"),
TX_TDCC_CFG_1 => ("11"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"),
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"00082"),
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (TRUE),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce089"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (FALSE),
RCV_TERM_VTTRX_0 => (TRUE),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (TRUE),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce089"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (FALSE),
RCV_TERM_VTTRX_1 => (TRUE),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (TRUE),
DEC_PCOMMA_DETECT_0 => (TRUE),
DEC_VALID_COMMA_ONLY_0 => (TRUE),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (TRUE),
DEC_PCOMMA_DETECT_1 => (TRUE),
DEC_VALID_COMMA_ONLY_1 => (TRUE),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (TRUE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (TRUE),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (5),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0100000000"),
CLK_COR_SEQ_1_3_0 => ("0100000000"),
CLK_COR_SEQ_1_4_0 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0100000000"),
CLK_COR_SEQ_2_3_0 => ("0100000000"),
CLK_COR_SEQ_2_4_0 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (FALSE),
CLK_CORRECT_USE_0 => (FALSE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (5),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0100000000"),
CLK_COR_SEQ_1_3_1 => ("0100000000"),
CLK_COR_SEQ_1_4_1 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0100000000"),
CLK_COR_SEQ_2_3_1 => ("0100000000"),
CLK_COR_SEQ_2_4_1 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (FALSE),
CLK_CORRECT_USE_1 => (FALSE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => ("0110111100"),
CHAN_BOND_SEQ_1_2_0 => ("0011001011"),
CHAN_BOND_SEQ_1_3_0 => ("0110111100"),
CHAN_BOND_SEQ_1_4_0 => ("0011001011"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (FALSE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => ("0110111100"),
CHAN_BOND_SEQ_1_2_1 => ("0011001011"),
CHAN_BOND_SEQ_1_3_1 => ("0110111100"),
CHAN_BOND_SEQ_1_4_1 => ("0011001011"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (FALSE),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (FALSE),
RX_EN_IDLE_HOLD_CDR_0 => (FALSE),
RX_EN_IDLE_RESET_FR_0 => (TRUE),
RX_EN_IDLE_RESET_PH_0 => (TRUE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (FALSE),
RX_EN_IDLE_HOLD_CDR_1 => (FALSE),
RX_EN_IDLE_RESET_FR_1 => (TRUE),
RX_EN_IDLE_RESET_PH_1 => (TRUE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (10),
SATA_MAX_INIT_0 => (29),
SATA_MAX_WAKE_0 => (10),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (16),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (10),
SATA_MAX_INIT_1 => (29),
SATA_MAX_WAKE_1 => (10),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (16),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => (others => '0'),
LOOPBACK1 => (others => '0'),
RXPOWERDOWN0 => "11",
RXPOWERDOWN1 => "11",
TXPOWERDOWN0 => "11",
TXPOWERDOWN1 => "11",
--------------------------------- PLL Ports --------------------------------
CLK00 => refclk0,
CLK01 => refclk0,
CLK10 => refclk1,
CLK11 => refclk1,
CLKINEAST0 => '0',
CLKINEAST1 => '0',
CLKINWEST0 => '0',
CLKINWEST1 => '0',
GCLK00 => '0',
GCLK01 => '0',
GCLK10 => '0',
GCLK11 => '0',
GTPRESET0 => '0',
GTPRESET1 => '0',
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => '1',
INTDATAWIDTH1 => '1',
PLLCLK00 => '0',
PLLCLK01 => '0',
PLLCLK10 => '0',
PLLCLK11 => '0',
PLLLKDET0 => testlock0,
PLLLKDET1 => testlock1,
PLLLKDETEN0 => '1',
PLLLKDETEN1 => '1',
PLLPOWERDOWN0 => '0',
PLLPOWERDOWN1 => '0',
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => out_ref_clk0,
REFCLKPLL1 => out_ref_clk1,
REFCLKPWRDNB0 => '0', -- Used- must be powered up
REFCLKPWRDNB1 => '0', -- Not used - should power down
REFSELDYPLL0 => "100", -- CLK10
REFSELDYPLL1 => "100", -- CLK11
RESETDONE0 => open,
RESETDONE1 => open,
TSTCLK0 => '0',
TSTCLK1 => '0',
TSTIN0 => (others => '0'),
TSTIN1 => (others => '0'),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => open,
RXCHARISK1 => open,
RXDEC8B10BUSE0 => '1',
RXDEC8B10BUSE1 => '1',
RXDISPERR0 => open,
RXDISPERR1 => open,
RXNOTINTABLE0 => open,
RXNOTINTABLE1 => open,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => '0',
USRCODEERR1 => '0',
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => (others => '0'),
RXCHBONDMASTER0 => '0',
RXCHBONDMASTER1 => '0',
RXCHBONDO => open,
RXCHBONDSLAVE0 => '0',
RXCHBONDSLAVE1 => '0',
RXENCHANSYNC0 => '0',
RXENCHANSYNC1 => '0',
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => '1',
RXCOMMADETUSE1 => '1',
RXENMCOMMAALIGN0 => '0',
RXENMCOMMAALIGN1 => '0',
RXENPCOMMAALIGN0 => '0',
RXENPCOMMAALIGN1 => '0',
RXSLIDE0 => '0',
RXSLIDE1 => '0',
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => '1',
PRBSCNTRESET1 => '1',
RXENPRBSTST0 => "000",
RXENPRBSTST1 => "000",
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => open,
RXDATA1 => open,
RXDATAWIDTH0 => "01",
RXDATAWIDTH1 => "01",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => '1',
RXRESET1 => '1',
RXUSRCLK0 => '0',
RXUSRCLK1 => '0',
RXUSRCLK20 => '0',
RXUSRCLK21 => '0',
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => '0',
GATERXELECIDLE1 => '0',
IGNORESIGDET0 => '1',
IGNORESIGDET1 => '1',
RCALINEAST => (others =>'0'),
RCALINWEST => (others =>'0'),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => '0',
RXCDRRESET1 => '0',
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXN0 => '0',
RXN1 => '0',
RXP0 => '1',
RXP1 => '1',
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => '1',
RXBUFRESET1 => '1',
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => '0',
RXENPMAPHASEALIGN1 => '0',
RXPMASETPHASE0 => '0',
RXPMASETPHASE1 => '0',
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => '0',
RXPOLARITY1 => '0',
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => (others=>'0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DRDY => open,
DRPDO => open,
DWE => '0',
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => open,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => open,
GTPCLKOUT0 => open,
GTPCLKOUT1 => open,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => "0000",
TXBYPASS8B10B1 => "0000",
TXCHARDISPMODE0 => (others => '0'),
TXCHARDISPMODE1 => (others => '0'),
TXCHARDISPVAL0 => (others => '0'),
TXCHARDISPVAL1 => (others => '0'),
TXCHARISK0 => "0000",
TXCHARISK1 => "0000",
TXENC8B10BUSE0 => '0',
TXENC8B10BUSE1 => '0',
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => '0',
TXENPMAPHASEALIGN1 => '0',
TXPMASETPHASE0 => '0',
TXPMASETPHASE1 => '0',
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => (others => '0'),
TXDATA1 => (others => '0'),
TXDATAWIDTH0 => "01",
TXDATAWIDTH1 => "01",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => '1',
TXRESET1 => '1',
TXUSRCLK0 => '0',
TXUSRCLK1 => '0',
TXUSRCLK20 => '0',
TXUSRCLK21 => '0',
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0000",
TXDIFFCTRL1 => "0000",
TXINHIBIT0 => '0',
TXINHIBIT1 => '0',
TXP0 => open,
TXN0 => open,
TXP1 => open,
TXN1 => open,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => "000",
TXENPRBSTST1 => "000",
TXPRBSFORCEERR0 => '0',
TXPRBSFORCEERR1 => '0',
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => '0',
TXPOLARITY1 => '0',
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => '0',
TXDETECTRX1 => '0',
TXELECIDLE0 => '0',
TXELECIDLE1 => '0',
TXPDOWNASYNCH0 => '0',
TXPDOWNASYNCH1 => '0',
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => '0',
TXCOMSTART1 => '0',
TXCOMTYPE0 => '0',
TXCOMTYPE1 => '0'
);
end Behavioral;
| mit | 187954a6ce61c7bfb33bc2221505f185 | 0.312373 | 4.803776 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_mux16to1.vhd | 1 | 7,192 | ------------------------------------------------------------------------------
-- Testbench for mux16to1.vhd
--
-- Project :
-- File : tb_mux16to1.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/02
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Mux16to1 is
end tb_Mux16to1;
architecture arch of tb_Mux16to1 is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, sel8,
sel9, selA, selB, selC, selD, selE, selF);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal SelxS : std_logic_vector(3 downto 0);
signal In0xD : std_logic_vector(WIDTH-1 downto 0);
signal In1xD : std_logic_vector(WIDTH-1 downto 0);
signal In2xD : std_logic_vector(WIDTH-1 downto 0);
signal In3xD : std_logic_vector(WIDTH-1 downto 0);
signal In4xD : std_logic_vector(WIDTH-1 downto 0);
signal In5xD : std_logic_vector(WIDTH-1 downto 0);
signal In6xD : std_logic_vector(WIDTH-1 downto 0);
signal In7xD : std_logic_vector(WIDTH-1 downto 0);
signal In8xD : std_logic_vector(WIDTH-1 downto 0);
signal In9xD : std_logic_vector(WIDTH-1 downto 0);
signal InAxD : std_logic_vector(WIDTH-1 downto 0);
signal InBxD : std_logic_vector(WIDTH-1 downto 0);
signal InCxD : std_logic_vector(WIDTH-1 downto 0);
signal InDxD : std_logic_vector(WIDTH-1 downto 0);
signal InExD : std_logic_vector(WIDTH-1 downto 0);
signal InFxD : std_logic_vector(WIDTH-1 downto 0);
signal OutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Mux16to1
generic map (
WIDTH => WIDTH)
port map (
SelxSI => SelxS,
In0xDI => In0xD,
In1xDI => In1xD,
In2xDI => In2xD,
In3xDI => In3xD,
In4xDI => In4xD,
In5xDI => In5xD,
In6xDI => In6xD,
In7xDI => In7xD,
In8xDI => In8xD,
In9xDI => In9xD,
InAxDI => InAxD,
InBxDI => InBxD,
InCxDI => InCxD,
InDxDI => InDxD,
InExDI => InExD,
InFxDI => InFxD,
OutxDO => OutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
SelxS <= "0000";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
In1xD <= std_logic_vector(to_unsigned(1, WIDTH));
In2xD <= std_logic_vector(to_unsigned(2, WIDTH));
In3xD <= std_logic_vector(to_unsigned(3, WIDTH));
In4xD <= std_logic_vector(to_unsigned(4, WIDTH));
In5xD <= std_logic_vector(to_unsigned(5, WIDTH));
In6xD <= std_logic_vector(to_unsigned(6, WIDTH));
In7xD <= std_logic_vector(to_unsigned(7, WIDTH));
In8xD <= std_logic_vector(to_unsigned(8, WIDTH));
In9xD <= std_logic_vector(to_unsigned(9, WIDTH));
InAxD <= std_logic_vector(to_unsigned(10, WIDTH));
InBxD <= std_logic_vector(to_unsigned(11, WIDTH));
InCxD <= std_logic_vector(to_unsigned(12, WIDTH));
InDxD <= std_logic_vector(to_unsigned(13, WIDTH));
InExD <= std_logic_vector(to_unsigned(14, WIDTH));
InFxD <= std_logic_vector(to_unsigned(15, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= sel0; -- sel0
SelxS <= "0000";
wait for CLK_PERIOD;
tbStatus <= sel1; -- sel1
SelxS <= "0001";
wait for CLK_PERIOD;
tbStatus <= sel2; -- sel2
SelxS <= "0010";
wait for CLK_PERIOD;
tbStatus <= sel3; -- sel3
SelxS <= "0011";
wait for CLK_PERIOD;
tbStatus <= sel4; -- sel4
SelxS <= "0100";
wait for CLK_PERIOD;
tbStatus <= sel5; -- sel5
SelxS <= "0101";
wait for CLK_PERIOD;
tbStatus <= sel6; -- sel6
SelxS <= "0110";
wait for CLK_PERIOD;
tbStatus <= sel7; -- sel7
SelxS <= "0111";
wait for CLK_PERIOD;
tbStatus <= sel8; -- sel8
SelxS <= "1000";
wait for CLK_PERIOD;
tbStatus <= sel9; -- sel9
SelxS <= "1001";
wait for CLK_PERIOD;
tbStatus <= selA; -- selA
SelxS <= "1010";
wait for CLK_PERIOD;
tbStatus <= selB; -- selB
SelxS <= "1011";
wait for CLK_PERIOD;
tbStatus <= selC; -- selC
SelxS <= "1100";
wait for CLK_PERIOD;
tbStatus <= selD; -- selD
SelxS <= "1101";
wait for CLK_PERIOD;
tbStatus <= selE; -- selE
SelxS <= "1110";
wait for CLK_PERIOD;
tbStatus <= selF; -- selF
SelxS <= "1111";
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= "0000";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
tbStatus <= sel0; -- sel0
SelxS <= "0000";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(30, WIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(31, WIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(32, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= "0000";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | f872dbbb24fe2b5e976a2dbce81b58d6 | 0.510011 | 3.578109 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_SchedulerTemporalPartitioning.vhd | 1 | 3,644 | -------------------------------------------------------------------------------
-- Title : Testbench for design "SchedulerTemporalPartitioning"
-- Project :
-------------------------------------------------------------------------------
-- File : SchedulerTemporalPartitioning_tb.vhd
-- Author : Christian Plessl <[email protected]>
-- Company : Computer Engineering Lab, ETH Zurich
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
-------------------------------------------------------------------------------
entity SchedulerTemporalPartitioning_tb is
end SchedulerTemporalPartitioning_tb;
-------------------------------------------------------------------------------
architecture arch of SchedulerTemporalPartitioning_tb is
component SchedulerTemporalPartitioning
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ScheduleStartxEI : in std_logic;
ScheduleDonexSO : out std_logic;
NoTpContextsxSI : in unsigned(CNTXTWIDTH-1 downto 0);
NoTpUserCyclesxSI : in unsigned(CCNTWIDTH-1 downto 0);
CExEO : out std_logic;
ClrContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEO : out std_logic;
ContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0));
end component;
-- component ports
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
signal ScheduleStartxE : std_logic;
signal ScheduleDonexS : std_logic;
signal NoTpContextsxS : unsigned(CNTXTWIDTH-1 downto 0);
signal NoTpUserCyclesxS : unsigned(CCNTWIDTH-1 downto 0);
signal CExE : std_logic;
signal ClrContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal ClrContextxE : std_logic;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal CycleDnCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal CycleUpCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
begin -- arch
-- component instantiation
DUT : SchedulerTemporalPartitioning
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ScheduleStartxEI => ScheduleStartxE,
ScheduleDonexSO => ScheduleDonexS,
NoTpContextsxSI => NoTpContextsxS,
NoTpUserCyclesxSI => NoTpUserCyclesxS,
CExEO => CExE,
ClrContextxSO => ClrContextxS,
ClrContextxEO => ClrContextxE,
ContextxSO => ContextxS,
CycleDnCntxDO => CycleDnCntxD,
CycleUpCntxDO => CycleUpCntxD);
-- clock generation
ClkxC <= not ClkxC after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until ClkxC = '1';
NoTpUserCyclesxS <= to_unsigned(20, NoTpUserCyclesxS'length);
NoTpContextsxS <= to_unsigned(3, NoTpContextsxS'length);
RstxRB <= '0';
wait for 20 ns;
RstxRB <= '1';
ScheduleStartxE <= '1';
wait for 20 ns;
ScheduleStartxE <= '0';
wait for 1300 ns;
assert false report "simulation terminated" severity failure;
end process WaveGen_Proc;
end arch;
| bsd-3-clause | 28d640e239c499efeaeddcc7046208a7 | 0.55708 | 4.122172 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/transceivers_test.vhd | 1 | 13,304 | ----------------------------------------------------------------------------------
-- Module Name: transceiver_test - Behavioral
--
-- Description: A partial implementation allowing simulation of the main stream
-- components without the compications of the AUX channel. Not made
-- to be implemented in hardware!
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity transceiver_test is
port (
clk : in std_logic;
debug_pmod : out std_logic_vector(7 downto 0) := (others => '0');
switches : in std_logic_vector(7 downto 0) := (others => '0');
leds : out std_logic_vector(7 downto 0) := (others => '0');
------------------------------
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
gtptxp : out std_logic;
gtptxn : out std_logic;
------------------------------
dp_tx_hp_detect : in std_logic;
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic
);
end transceiver_test;
architecture Behavioral of transceiver_test is
component test_source is
port (
clk : in std_logic;
data0 : out std_logic_vector(7 downto 0);
data0k : out std_logic;
data1 : out std_logic_vector(7 downto 0);
data1k : out std_logic
);
end component;
component idle_pattern is
port (
clk : in std_logic;
data0 : out std_logic_vector(7 downto 0);
data0k : out std_logic;
data1 : out std_logic_vector(7 downto 0);
data1k : out std_logic
);
end component;
component scrambler is
port (
clk : in std_logic;
bypass0 : in std_logic;
in_data0 : in std_logic_vector(7 downto 0);
in_data0k : in std_logic;
bypass1 : in std_logic;
in_data1 : in std_logic_vector(7 downto 0);
in_data1k : in std_logic;
out_data0 : out std_logic_vector(7 downto 0);
out_data0k : out std_logic;
out_data1 : out std_logic_vector(7 downto 0);
out_data1k : out std_logic
);
end component;
component data_to_8b10b is
port (
clk : in std_logic;
data0 : in std_logic_vector(7 downto 0);
data0k : in std_logic;
data0forceneg : in std_logic;
data1 : in std_logic_vector(7 downto 0);
data1k : in std_logic;
data1forceneg : in std_logic;
symbol0 : out std_logic_vector(9 downto 0);
symbol1 : out std_logic_vector(9 downto 0)
);
end component;
component Transceiver is
Port ( mgmt_clk : in STD_LOGIC;
powerup_channel : in STD_LOGIC;
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
swing_0p4 : in STD_LOGIC;
swing_0p6 : in STD_LOGIC;
swing_0p8 : in STD_LOGIC;
tx_running : out STD_LOGIC;
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
txsymbol0 : in std_logic_vector(9 downto 0);
txsymbol1 : in std_logic_vector(9 downto 0);
symbolclk : out STD_LOGIC;
gtptxp : out std_logic;
gtptxn : out std_logic);
end component;
component training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
clock_train : in std_logic;
align_train : in std_logic;
in_data0 : in std_logic_vector(7 downto 0);
in_data0k : in std_logic;
in_data1 : in std_logic_vector(7 downto 0);
in_data1k : in std_logic;
out_data0 : out std_logic_vector(7 downto 0);
out_data0k : out std_logic;
out_data0forceneg : out std_logic;
out_data1 : out std_logic_vector(7 downto 0);
out_data1k : out std_logic;
out_data1forceneg : out std_logic
);
end component;
--------------------------------------------------------------------------
signal tx_powerup : std_logic := '0';
signal tx_clock_train : std_logic := '0';
signal tx_align_train : std_logic := '0';
signal data_channel_0 : std_logic_vector(19 downto 0):= (others => '0');
---------------------------------------------
-- Transceiver signals
---------------------------------------------
signal txresetdone : std_logic := '0';
signal symbolclk : std_logic := '0';
signal tx_running : std_logic := '0';
signal powerup_channel : std_logic_vector(3 downto 0) := (others => '0');
signal clock_locked : std_logic := '0';
signal equ_locked : std_logic := '0';
signal symbol_locked : std_logic := '0';
signal align_locked : std_logic := '0';
signal preemp_0p0 : std_logic := '1';
signal preemp_3p5 : STD_LOGIC := '0';
signal preemp_6p0 : STD_LOGIC := '0';
signal swing_0p4 : STD_LOGIC := '1';
signal swing_0p6 : STD_LOGIC := '0';
signal swing_0p8 : STD_LOGIC := '0';
------------------------------------------------
signal tx_link_established : std_logic := '0';
------------------------------------------------
signal interface_debug : std_logic_vector(7 downto 0);
signal sink_channel_count : std_logic_vector(2 downto 0) := "100";
signal source_channel_count : std_logic_vector(2 downto 0) := "001";
signal active_channel_count : std_logic_vector(2 downto 0) := "000";
signal debug : std_logic_vector(7 downto 0);
signal test_signal : std_logic_vector(8 downto 0);
signal test_signal_data0 : std_logic_vector(7 downto 0);
signal test_signal_data0k : std_logic;
signal test_signal_data1 : std_logic_vector(7 downto 0);
signal test_signal_data1k : std_logic;
signal test_signal_symbol0 : std_logic_vector(9 downto 0);
signal test_signal_symbol1 : std_logic_vector(9 downto 0);
--
signal scrambled_data0 : std_logic_vector(7 downto 0);
signal scrambled_data0k : std_logic;
signal scrambled_data1 : std_logic_vector(7 downto 0);
signal scrambled_data1k : std_logic;
signal scrambled_symbol0 : std_logic_vector(9 downto 0);
signal scrambled_symbol1 : std_logic_vector(9 downto 0);
--
signal ch0_data0 : std_logic_vector(7 downto 0);
signal ch0_data0k : std_logic;
signal ch0_data0forceneg : std_logic;
signal ch0_symbol0 : std_logic_vector(9 downto 0);
--
signal ch0_data1 : std_logic_vector(7 downto 0);
signal ch0_data1k : std_logic;
signal ch0_data1forceneg : std_logic;
signal ch0_symbol1 : std_logic_vector(9 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
powerup_channel <= (others => '1');
end if;
end process;
i_test_source : idle_pattern port map (
clk => symbolclk,
data0 => test_signal_data0,
data0k => test_signal_data0k,
data1 => test_signal_data1,
data1k => test_signal_data1k
);
i_scrambler : scrambler
port map (
clk => symbolclk,
bypass0 => '1',
bypass1 => '1',
in_data0 => test_signal_data0,
in_data0k => test_signal_data0k,
in_data1 => test_signal_data1,
in_data1k => test_signal_data1k,
out_data0 => scrambled_data0,
out_data0k => scrambled_data0k,
out_data1 => scrambled_data1,
out_data1k => scrambled_data1k
);
i_train_channel0: training_and_channel_delay port map (
clk => symbolclk,
channel_delay => "00",
clock_train => tx_clock_train,
align_train => tx_align_train,
in_data0 => test_signal_data0,
in_data0k => test_signal_data0k,
in_data1 => test_signal_data1,
in_data1k => test_signal_data1k,
out_data0 => ch0_data0,
out_data0k => ch0_data0k,
out_data0forceneg => ch0_data0forceneg,
out_data1 => ch0_data1,
out_data1k => ch0_data1k,
out_data1forceneg => ch0_data1forceneg
);
i_data_to_8b10b: data_to_8b10b port map (
clk => symbolclk,
data0 => ch0_data0,
data0k => ch0_data0k,
data0forceneg => ch0_data0forceneg,
data1 => ch0_data1,
data1k => ch0_data1k,
data1forceneg => ch0_data1forceneg,
symbol0 => ch0_symbol0,
symbol1 => ch0_symbol1
);
i_tx0: Transceiver Port map (
mgmt_clk => clk,
symbolclk => symbolclk,
powerup_channel => powerup_channel(0),
tx_running => tx_running,
preemp_0p0 => preemp_0p0,
preemp_3p5 => preemp_3p5,
preemp_6p0 => preemp_6p0,
swing_0p4 => swing_0p4,
swing_0p6 => swing_0p6,
swing_0p8 => swing_0p8,
refclk0_p => refclk0_p,
refclk0_n => refclk0_n,
refclk1_p => refclk1_p,
refclk1_n => refclk1_n,
txsymbol0 => ch0_symbol0,
txsymbol1 => ch0_symbol1,
gtptxp => gtptxp,
gtptxn => gtptxn);
end Behavioral;
| mit | 707e8a0eeb2ad1cd7ebbdb7be22c792c | 0.486621 | 3.861829 | false | true | false | false |
hamsternz/FPGA_DisplayPort | src/vga_to_dp_stream/capture_test.vhd | 1 | 5,639 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:39:08 10/12/2015
-- Design Name:
-- Module Name: capture_test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity capture_test is
Port ( clk40 : in STD_LOGIC;
dp_clk : in STD_LOGIC;
dp_ch0_data_0 : out STD_LOGIC_VECTOR (8 downto 0);
dp_ch0_data_1 : out STD_LOGIC_VECTOR (8 downto 0));
end capture_test;
architecture Behavioral of capture_test is
component test_800_600_source is
Port ( clk40 : in STD_LOGIC;
hblank : out STD_LOGIC;
hsync : out STD_LOGIC;
vblank : out STD_LOGIC;
vsync : out STD_LOGIC;
data : out STD_LOGIC_VECTOR (23 downto 0));
end component;
component extract_timings is
Port ( pixel_clk : in STD_LOGIC;
pixel_hblank : in STD_LOGIC;
pixel_hsync : in STD_LOGIC;
pixel_vblank : in STD_LOGIC;
pixel_vsync : in STD_LOGIC;
--------------------------------------------------
-- These should be stable when 'ready' is asserted
--------------------------------------------------
ready : out std_logic;
h_visible : out STD_LOGIC_VECTOR (12 downto 0);
v_visible : out STD_LOGIC_VECTOR (12 downto 0);
h_total : out STD_LOGIC_VECTOR (12 downto 0);
v_total : out STD_LOGIC_VECTOR (12 downto 0);
h_sync_width : out STD_LOGIC_VECTOR (12 downto 0);
v_sync_width : out STD_LOGIC_VECTOR (12 downto 0);
h_start : out STD_LOGIC_VECTOR (12 downto 0);
v_start : out STD_LOGIC_VECTOR (12 downto 0);
h_sync_active_high : out std_logic;
v_sync_active_high : out std_logic);
end component ;
component pixel_receiver is
Port ( pixel_clk : in STD_LOGIC;
pixel_data : in STD_LOGIC_VECTOR (23 downto 0);
pixel_hblank : in STD_LOGIC;
pixel_hsync : in STD_LOGIC;
pixel_vblank : in STD_LOGIC;
pixel_vsync : in STD_LOGIC;
h_visible : in STD_LOGIC_VECTOR (12 downto 0);
dp_clk : in STD_LOGIC;
ch0_data_0 : out STD_LOGIC_VECTOR (8 downto 0);
ch0_data_1 : out STD_LOGIC_VECTOR (8 downto 0));
end component ;
signal pixel_data : STD_LOGIC_VECTOR (23 downto 0);
signal pixel_hblank : STD_LOGIC;
signal pixel_hsync : STD_LOGIC;
signal pixel_vblank : STD_LOGIC;
signal pixel_vsync : STD_LOGIC;
signal ready : std_logic;
signal h_visible : STD_LOGIC_VECTOR (12 downto 0);
signal v_visible : STD_LOGIC_VECTOR (12 downto 0);
signal h_total : STD_LOGIC_VECTOR (12 downto 0);
signal v_total : STD_LOGIC_VECTOR (12 downto 0);
signal h_sync_width : STD_LOGIC_VECTOR (12 downto 0);
signal v_sync_width : STD_LOGIC_VECTOR (12 downto 0);
signal h_start : STD_LOGIC_VECTOR (12 downto 0);
signal v_start : STD_LOGIC_VECTOR (12 downto 0);
signal h_sync_active_high : std_logic;
signal v_sync_active_high : std_logic;
begin
source: test_800_600_source
Port map (
clk40 => clk40,
hblank => pixel_hblank,
hsync => pixel_hsync,
vblank => pixel_vblank,
vsync => pixel_vsync,
data => pixel_data);
timings: extract_timings
Port map (
pixel_clk => clk40,
pixel_hblank => pixel_hblank,
pixel_hsync => pixel_hsync,
pixel_vblank => pixel_vblank,
pixel_vsync => pixel_vsync,
--------------------------------------------------
-- These should be stable when ready is asserted
--------------------------------------------------
ready => ready,
h_visible => h_visible,
v_visible => v_visible,
h_total => h_total,
v_total => v_total,
h_sync_width => h_sync_width,
v_sync_width => v_sync_width,
h_start => h_start,
v_start => v_start,
h_sync_active_high => h_sync_active_high,
v_sync_active_high => v_sync_active_high);
capture: pixel_receiver
Port map (
pixel_clk => clk40,
pixel_data => pixel_data,
pixel_hblank => pixel_hblank,
pixel_hsync => pixel_hsync,
pixel_vblank => pixel_vblank,
pixel_vsync => pixel_vsync,
h_visible => h_visible,
dp_clk => dp_clk,
ch0_data_0 => dp_ch0_data_0,
ch0_data_1 => dp_ch0_data_1);
end Behavioral;
| mit | 8f6025c5e0f98423abd57d919c7c02b4 | 0.492463 | 3.937849 | false | false | false | false |
huljar/present-vhdl | src/axi_stream_wrapper.vhd | 1 | 5,271 | library ieee;
use ieee.std_logic_1164.all;
use work.util.all;
entity axi_stream_wrapper is
generic(k: key_enum);
port(ACLK: in std_logic; -- positive edge clock
ARESETN: in std_logic; -- active-low synchronous reset
S_AXIS_TREADY: out std_logic;
S_AXIS_TDATA: in std_logic_vector(31 downto 0);
S_AXIS_TLAST: in std_logic;
S_AXIS_TVALID: in std_logic;
M_AXIS_TVALID: out std_logic;
M_AXIS_TDATA: out std_logic_vector(31 downto 0);
M_AXIS_TLAST: out std_logic;
M_AXIS_TREADY: in std_logic
);
end axi_stream_wrapper;
architecture behavioral of axi_stream_wrapper is
type state_type is (idle, read_plaintext, read_key, stabilize, active, write_ciphertext);
type axis_buffer is array(integer range <>) of std_logic_vector(31 downto 0);
constant plaintext_reads: natural := 2;
constant key_reads: natural := 4;
constant active_cycles: natural := 33;
constant ciphertext_writes: natural := 2;
signal state: state_type;
signal counter: natural range 0 to 32;
signal ip_plaintext: std_logic_vector(63 downto 0);
signal ip_key: std_logic_vector(key_bits(k)-1 downto 0);
signal ip_reset: std_logic;
signal ip_ciphertext: std_logic_vector(63 downto 0);
signal ip_plaintext_buf: axis_buffer(0 to 1);
signal ip_key_buf: axis_buffer(0 to 3);
signal ip_ciphertext_buf: axis_buffer(0 to 1);
component present_top
generic(k: key_enum);
port(plaintext: in std_logic_vector(63 downto 0);
key: in std_logic_vector(key_bits(k)-1 downto 0);
clk: in std_logic;
reset: in std_logic;
ciphertext: out std_logic_vector(63 downto 0)
);
end component;
begin
IP: present_top generic map(
k => k
) port map(
plaintext => ip_plaintext,
key => ip_key,
clk => ACLK,
reset => ip_reset,
ciphertext => ip_ciphertext
);
ip_plaintext <= ip_plaintext_buf(0) & ip_plaintext_buf(1);
KEY_80: if k = K_80 generate
ip_key <= ip_key_buf(0) & ip_key_buf(1) & ip_key_buf(2)(31 downto 16);
end generate;
KEY_128: if k = K_128 generate
ip_key <= ip_key_buf(0) & ip_key_buf(1) & ip_key_buf(2) & ip_key_buf(3);
end generate;
ip_reset <= '0' when state = active else '1';
S_AXIS_TREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
M_AXIS_TVALID <= '1' when state = write_ciphertext else '0';
M_AXIS_TLAST <= '1' when (state = write_ciphertext and counter = ciphertext_writes-1) else '0';
state_machine: process(ACLK)
begin
if rising_edge(ACLK) then
if ARESETN = '0' then
state <= idle;
counter <= 0;
else
case state is
when idle =>
ip_ciphertext_buf(0) <= (others => '0');
ip_ciphertext_buf(1) <= (others => '0');
M_AXIS_TDATA <= (others => '0');
if S_AXIS_TVALID = '1' then
state <= read_plaintext;
counter <= 0;
end if;
when read_plaintext =>
if S_AXIS_TVALID = '1' then
ip_plaintext_buf(counter) <= S_AXIS_TDATA;
if counter = plaintext_reads-1 then
state <= read_key;
counter <= 0;
else
counter <= counter+1;
end if;
end if;
when read_key =>
if S_AXIS_TVALID = '1' then
ip_key_buf(counter) <= S_AXIS_TDATA;
if counter = key_reads-1 then
state <= stabilize;
counter <= 0;
else
counter <= counter+1;
end if;
end if;
when stabilize =>
state <= active;
when active =>
if counter = active_cycles-1 then
ip_ciphertext_buf(0) <= ip_ciphertext(63 downto 32);
ip_ciphertext_buf(1) <= ip_ciphertext(31 downto 0);
state <= write_ciphertext;
counter <= 0;
else
counter <= counter+1;
end if;
when write_ciphertext =>
M_AXIS_TDATA <= ip_ciphertext_buf(counter);
if M_AXIS_TREADY = '1' then
if counter = ciphertext_writes-1 then
state <= idle;
counter <= 0;
else
counter <= counter+1;
end if;
end if;
end case;
end if;
end if;
end process;
end architecture;
| mit | 4b5678ae0a2e047e8876f47776aed487 | 0.46955 | 4.313421 | false | false | false | false |
plessl/zippy | vhdl/counter.vhd | 1 | 4,130 | ------------------------------------------------------------------------------
-- Up/down counters
--
-- Project :
-- File : $Id: counter.vhd 173 2004-11-17 15:57:19Z plessl $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/17
-- Changed : $LastChangedDate: 2004-11-17 16:57:19 +0100 (Wed, 17 Nov 2004) $
------------------------------------------------------------------------------
-- Loadable up counter with enable and reset
-- RstxRB resets the counter to low
-- On assertion of LoadxEI the counter is synchrounously loaded with
-- with CinxDI
-- Counting is enabled when CExEI is asserted
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UpCounter is
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CExEI : in std_logic;
CinxDI : in std_logic_vector(WIDTH-1 downto 0);
CoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end UpCounter;
architecture simple of UpCounter is
signal CountxD : unsigned(WIDTH-1 downto 0);
begin -- simple
Count : process (ClkxC, RstxRB)
begin -- process Count
if RstxRB = '0' then -- asynchronous reset (active low)
CountxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if LoadxEI = '1' then
CountxD <= unsigned(CinxDI);
elsif CExEI = '1' then
CountxD <= CountxD + 1;
end if;
end if;
end process Count;
CoutxDO <= std_logic_vector(CountxD);
end simple;
------------------------------------------------------------------------------
-- Up/down counter
--
-- Project :
-- File : updowncounter.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/21
-- Last changed: $LastChangedDate: 2004-11-17 16:57:19 +0100 (Wed, 17 Nov 2004) $
------------------------------------------------------------------------------
-- Loadable up/down counter with enable and reset
-- RstxRB resets the counter to low
-- On assertion of LoadxEI the counter is synchrounously loaded with
-- with CinxDI
-- Counting is enabled when CExEI is asserted
-- ModexSI = 0 enables counting up, ModexSI=1 enables counting down
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UpDownCounter is
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CExEI : in std_logic;
ModexSI : in std_logic;
CinxDI : in std_logic_vector(WIDTH-1 downto 0);
CoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end UpDownCounter;
architecture simple of UpDownCounter is
signal CountxD : signed(WIDTH-1 downto 0);
begin -- simple
Count : process (ClkxC, RstxRB)
begin -- process Count
if RstxRB = '0' then -- asynchronous reset (active low)
CountxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if (LoadxEI = '1') then -- load counter
CountxD <= signed(CinxDI);
elsif (CExEI = '1') then -- enable counter
if (ModexSI = '0') then
CountxD <= CountxD + 1; -- count up
else
CountxD <= CountxD - 1; -- count down
end if;
end if;
end if;
end process Count;
CoutxDO <= std_logic_vector(CountxD);
end simple;
| bsd-3-clause | deeb2d258a30bcc2a0fca89654ed311d | 0.528814 | 3.834726 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt/tstadpcm_virt_cfg.template.vhd | 1 | 4,934 | ------------------------------------------------------------------------------
-- Configuration for ADPCM application with virtualized execution on a
-- 4x4 zippy array
--
-- Id : $Id: $
-- File : $Url: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/27
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTADPCM_VIRT is
function tstadpcmcfg_p0 return engineConfigRec;
function tstadpcmcfg_p1 return engineConfigRec;
function tstadpcmcfg_p2 return engineConfigRec;
end CfgLib_TSTADPCM_VIRT;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTADPCM_VIRT is
---------------------------------------------------------------------------
-- ROM DATA
---------------------------------------------------------------------------
type indextable_arr is array (0 to 15) of integer;
constant INDEXTABLE : indextable_arr := (
-1, -1, -1, -1, 2, 4, 6, 8,
-1, -1, -1, -1, 2, 4, 6, 8
);
type stepsizetable_arr is array (0 to 88) of integer;
constant STEPSIZETABLE : stepsizetable_arr := (
7, 8, 9, 10, 11, 12, 13, 14, 16, 17,
19, 21, 23, 25, 28, 31, 34, 37, 41, 45,
50, 55, 60, 66, 73, 80, 88, 97, 107, 118,
130, 143, 157, 173, 190, 209, 230, 253, 279, 307,
337, 371, 408, 449, 494, 544, 598, 658, 724, 796,
876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066,
2272, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358,
5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899,
15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767
);
----------------------------------------------------------------------------
-- tstadpcm partition p0 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p0 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 0 ###################
-- ############# end configuration of partition 0 ###################
-- initialize ROM
-- ROM index table (op0) is mapped to cell c_3_0
for i in INDEXTABLE'range loop
cfg.memoryConf(3)(i) :=
std_logic_vector(to_signed(INDEXTABLE(i), DATAWIDTH));
end loop; -- i
-- ROM stepsize table (op19) is mapped to cell c_2_1
for i in STEPSIZETABLE'range loop
cfg.memoryConf(2)(i) :=
std_logic_vector(to_signed(STEPSIZETABLE(i), DATAWIDTH));
end loop; -- i
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstadpcmcfg_p0;
----------------------------------------------------------------------------
-- tstadpcm partition p1 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p1 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 1 ###################
-- ############# end configuration of partition 1 ###################
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstadpcmcfg_p1;
----------------------------------------------------------------------------
-- tstadpcm partition p2 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p2 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 2 ###################
-- ############# end configuration of partition 2 ###################
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_ON;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_ON;
return cfg;
end tstadpcmcfg_p2;
end CfgLib_TSTADPCM_VIRT;
| bsd-3-clause | 3587423d1da0e015f1a95b027d8eb44e | 0.492501 | 3.959872 | false | true | false | false |
plessl/zippy | vhdl/testbenches/tb_mux4to1.vhd | 1 | 4,039 | ------------------------------------------------------------------------------
-- Testbench for mux4to1.vhd
--
-- Project :
-- File : tb_mux4to1.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/25
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Mux4to1 is
end tb_Mux4to1;
architecture arch of tb_Mux4to1 is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, sel0, sel1, sel2, sel3);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal SelxS : std_logic_vector(1 downto 0);
signal In0xD : std_logic_vector(WIDTH-1 downto 0);
signal In1xD : std_logic_vector(WIDTH-1 downto 0);
signal In2xD : std_logic_vector(WIDTH-1 downto 0);
signal In3xD : std_logic_vector(WIDTH-1 downto 0);
signal OutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut: Mux4to1
generic map (
WIDTH => WIDTH)
port map (
SelxSI => SelxS,
In0xDI => In0xD,
In1xDI => In1xD,
In2xDI => In2xD,
In3xDI => In3xD,
OutxDO => OutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
SelxS <= "00";
In0xD <= std_logic_vector(to_unsigned(01, WIDTH));
In1xD <= std_logic_vector(to_unsigned(10, WIDTH));
In2xD <= std_logic_vector(to_unsigned(20, WIDTH));
In3xD <= std_logic_vector(to_unsigned(30, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= sel0; -- sel0
SelxS <= "00";
wait for CLK_PERIOD;
tbStatus <= sel1; -- sel1
SelxS <= "01";
wait for CLK_PERIOD;
tbStatus <= sel2; -- sel2
SelxS <= "10";
wait for CLK_PERIOD;
tbStatus <= sel3; -- sel3
SelxS <= "11";
wait for CLK_PERIOD;
tbStatus <= sel0; -- sel0
SelxS <= "00";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(1, WIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(2, WIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(3, WIDTH));
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 9d2e5d89731e1132524dadcd399eabfe | 0.48304 | 3.917556 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_contextregfile.vhd | 1 | 6,610 | ------------------------------------------------------------------------------
-- Testbench for contextregfile.vhd
--
-- Project :
-- File : tb_contextregfile.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/06
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_ContextRegFile is
end tb_ContextRegFile;
architecture arch of tb_ContextRegFile is
constant NCONTEXTS : integer := 8;
constant WIDTH : integer := 16;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, reg1, clr3, wrall, rdall, clrall);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrContextxSI : std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal ClrContextxEI : std_logic;
signal ContextxSI : std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal EnxEI : std_logic;
signal DinxDI : std_logic_vector(WIDTH-1 downto 0);
signal DoutxDO : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ContextRegFile
generic map (
NCONTEXTS => NCONTEXTS,
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrContextxSI => ClrContextxSI,
ClrContextxEI => ClrContextxEI,
ContextxSI => ContextxSI,
EnxEI => EnxEI,
DinxDI => DinxDI,
DoutxDO => DoutxDO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal ClrContextxSI : out std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal ClrContextxEI : out std_logic;
signal ContextxSI : out std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal EnxEI : out std_logic;
signal DinxDI : out std_logic_vector(WIDTH-1 downto 0)) is
begin
ClrContextxSI <= (others => '0');
ClrContextxEI <= '0';
ContextxSI <= (others => '0');
EnxEI <= '0';
DinxDI <= (others => '0');
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
-- enable and disable register 1
tbStatus <= reg1;
ContextxSI <= std_logic_vector(to_unsigned(1, log2(NCONTEXTS)));
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(11, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '0';
DinxDI <= std_logic_vector(to_unsigned(12, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(13, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '0';
DinxDI <= std_logic_vector(to_unsigned(14, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(15, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- write all
tbStatus <= wrall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(c+10, WIDTH));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- read all
tbStatus <= rdall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- clear register 3
tbstatus <= clr3;
ContextxSI <= std_logic_vector(to_unsigned(3, log2(NCONTEXTS)));
ClrContextxSI <= std_logic_vector(to_unsigned(3, log2(NCONTEXTS)));
ClrContextxEI <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- clear all
tbstatus <= clrall;
for c in 0 to NCONTEXTS-1 loop
ClrContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
ClrContextxEI <= '1';
wait for CLK_PERIOD;
end loop; -- c
-- read all
tbStatus <= rdall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
tbStatus <= done;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 71af41a266e42eb1ed63289b9f0c2d5d | 0.546293 | 3.698937 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_decoder.vhd | 1 | 17,356 | ------------------------------------------------------------------------------
-- Testbench for decoder.vhd
--
-- Project :
-- File : tb_decoder.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- see ZArchPkg:
--
-- ZUnit Register Mapping and Functions:
-- 0 Reset W
-- 1 FIFO0 R/W
-- 2 FIFO0 Level R
-- 3 FIFO1 R/W
-- 4 FIFO1 Level R
-- 5 Run Cycle Counter R/W
-- 6 CfgMemory0 W
-- 7 CfgMemory0 Pointer W
-- 8 CfgMemory1 W
-- 9 CfgMemory1 Pointer W
-- 10 CfgMemory2 W
-- 11 CfgMemory2 Pointer W
-- 12 CfgMemory3 W
-- 13 CfgMemory3 Pointer W
-- 14 CfgMemory4 W
-- 15 CfgMemory4 Pointer W
-- 16 CfgMemory5 W
-- 17 CfgMemory5 Pointer W
-- 18 CfgMemory6 W
-- 19 CfgMemory6 Pointer W
-- 20 CfgMemory7 W
-- 21 CfgMemory7 Pointer W
-- 22 Context Sel. Reg. W
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComponentsPkg.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
entity tb_Decoder is
end tb_Decoder;
architecture arch of tb_Decoder is
constant REGWDT : integer := 8; -- Register Width
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (init, idle, done, w_rst, w_fifo0, r_fifo0,
r_fifo0lev, w_fifo1, r_fifo1, r_fifo1lev,
w_ccnt, r_ccnt,
w_cfgmem0, w_cfgmem0ptr, w_cfgmem1, w_cfgmem1ptr,
w_cfgmem2, w_cfgmem2ptr, w_cfgmem3, w_cfgmem3ptr,
w_cfgmem4, w_cfgmem4ptr, w_cfgmem5, w_cfgmem5ptr,
w_cfgmem6, w_cfgmem6ptr, w_cfgmem7, w_cfgmem7ptr,
w_cntxt);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal WrReqxE : std_logic;
signal RdReqxE : std_logic;
signal RegNrxD : std_logic_vector(REGWDT-1 downto 0);
signal SystRstxRB : std_logic;
signal CCloadxE : std_logic;
signal Fifo0WExE : std_logic;
signal Fifo0RExE : std_logic;
signal Fifo1WExE : std_logic;
signal Fifo1RExE : std_logic;
signal CMWExE : std_logic_vector(N_CONTEXTS-1 downto 0);
signal CMLoadPtrxE : std_logic_vector(N_CONTEXTS-1 downto 0);
signal CSRxE : std_logic;
signal DoutMuxS : std_logic_vector(2 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut: Decoder
generic map (
REGWIDTH => REGWDT)
port map (
RstxRB => RstxRB,
WrReqxEI => WrReqxE,
RdReqxEI => RdReqxE,
RegNrxDI => RegNrxD,
SystRstxRBO => SystRstxRB,
CCloadxEO => CCloadxE,
Fifo0WExEO => Fifo0WExE,
Fifo0RExEO => Fifo0RExE,
Fifo1WExEO => Fifo1WExE,
Fifo1RExEO => Fifo1RExE,
CMWExEO => CMWExE,
CMLoadPtrxEO => CMLoadPtrxE,
CSRxEO => CSRxE,
DoutMuxSO => DoutMuxS);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= init;
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD*0.25;
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*1.25;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- reset (ZREG_RST:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_rst;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_RST, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- push data into FIFO0 (ZREG_FIFO0:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_fifo0;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- pop data from FIFO0 (ZREG_FIFO0:R)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= r_fifo0;
WrReqxE <= '0';
RdReqxE <= '1';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- read FIFO0 fill level (ZREG_FIFO0LEV:R)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= r_fifo0lev;
WrReqxE <= '0';
RdReqxE <= '1';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0LEV, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- push data into FIFO1 (ZREG_FIFO1:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_fifo1;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- pop data from FIFO1 (ZREG_FIFO1:R)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= r_fifo1;
WrReqxE <= '0';
RdReqxE <= '1';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- read FIFO1 fill level (ZREG_FIFO1LEV:R)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= r_fifo1lev;
WrReqxE <= '0';
RdReqxE <= '1';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1LEV, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write cycle count register (ZREG_CYCLECNT:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_ccnt;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- read cycle count register (ZREG_CYCLECNT:R)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= r_ccnt;
WrReqxE <= '0';
RdReqxE <= '1';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 0 (ZREG_CFGMEM0:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem0;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 0 pointer (ZREG_CFGMEM0PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem0ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 1 (ZREG_CFGMEM1:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem1;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM1, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 1 pointer (ZREG_CFGMEM1PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem1ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM1PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 2 (ZREG_CFGMEM2:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem2;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM2, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 2 pointer (ZREG_CFGMEM2PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem2ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM2PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 3 (ZREG_CFGMEM3:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem3;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM3, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 3 pointer (ZREG_CFGMEM3PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem3ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM3PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 4 (ZREG_CFGMEM4:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem4;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM4, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 4 pointer (ZREG_CFGMEM4PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem4ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM4PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 5 (ZREG_CFGMEM5:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem5;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM5, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 5 pointer (ZREG_CFGMEM5PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem5ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM5PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 6 (ZREG_CFGMEM6:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem6;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM6, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 6 pointer (ZREG_CFGMEM6PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem6ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM6PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write config. memory 7 (ZREG_CFGMEM7:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem7;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM7, REGWDT));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- set config. memory 7 pointer (ZREG_CFGMEM7PTR:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cfgmem7ptr;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM7PTR, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
-- - - - - - - - - - - - - - - - - - - - - - - -
-- write context sel. register (ZREG_CONTEXTSEL:W)
-- - - - - - - - - - - - - - - - - - - - - - - -
tbStatus <= w_cntxt;
WrReqxE <= '1';
RdReqxE <= '0';
RegNrxD <= std_logic_vector(to_unsigned(ZREG_CONTEXTSEL, REGWDT));
wait for CLK_PERIOD;
tbStatus <= done; -- done
WrReqxE <= '0';
RdReqxE <= '0';
RegNrxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | dea4e543205d980a5168848e43763aea | 0.426654 | 3.032145 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/skew_channels.vhd | 1 | 4,876 | ---------------------------------------------------
-- Module: skew_channels
--
-- Description: Delay the symbols by the inter-channel skew (2 symbols per channel)
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-17 | Initial Version
------------------------------------------------------------------------------------
---------------------------------------------------
--
-- This is set up so the change over from test patters
-- to data happens seamlessly - e.g. the value for
-- on data_in when send_patter_1 and send_pattern_2
-- are both become zero is guarranteed to be sent
--
-- +----+--------------------+--------------------+
-- |Word| Training pattern 1 | Training pattern 2 |
-- | | Code MSB LSB | Code MSB LSB |
-- +----+--------------------+-------------------+
-- | 0 | D10.2 1010101010 | K28.5- 0101111100 |
-- | 1 | D10.2 1010101010 | D11.6 0110001011 |
-- | 2 | D10.2 1010101010 | K28.5+ 1010000011 |
-- | 3 | D10.2 1010101010 | D11.6 0110001011 |
-- | 4 | D10.2 1010101010 | D10.2 1010101010 |
-- | 5 | D10.2 1010101010 | D10.2 1010101010 |
-- | 6 | D10.2 1010101010 | D10.2 1010101010 |
-- | 7 | D10.2 1010101010 | D10.2 1010101010 |
-- | 8 | D10.2 1010101010 | D10.2 1010101010 |
-- | 9 | D10.2 1010101010 | D10.2 1010101010 |
-- +----+--------------------+--------------------+
-- Patterns are transmitted LSB first.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity skew_channels is
port (
clk : in std_logic;
in_data : in std_logic_vector(79 downto 0);
out_data : out std_logic_vector(79 downto 0) := (others => '0')
);
end skew_channels;
architecture arch of skew_channels is
type a_delay_line is array (0 to 2) of std_logic_vector(79 downto 0);
signal delay_line : a_delay_line := (others => (others => '0'));
begin
out_data <= delay_line(2)(79 downto 60) &
delay_line(1)(59 downto 40) &
delay_line(0)(39 downto 20) &
in_data(19 downto 0);
process(clk)
begin
if rising_edge(clk) then
-- Move the dalay line along
delay_line(1 to 2) <= delay_line(0 to 1);
delay_line(0) <= in_data;
end if;
end process;
end architecture; | mit | 3ee07058172f5774212648e2f33ff289 | 0.509639 | 3.957792 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_tristatebuf.vhd | 1 | 2,871 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ComponentsPkg.all;
entity tb_TristateBuf is
end tb_TristateBuf;
architecture arch of tb_TristateBuf is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, enable, disable);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data signals
signal InxD : std_logic_vector(WIDTH-1 downto 0);
signal OExE : std_logic;
signal OutxZ : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : TristateBuf
generic map (
WIDTH => WIDTH)
port map (
InxDI => InxD,
OExEI => OExE,
OutxZO => OutxZ);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
InxD <= (others => '0');
OExE <= '0';
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
InxD <= std_logic_vector(to_unsigned(111, WIDTH));
tbStatus <= enable;
OExE <= '1';
wait for CLK_PERIOD;
tbStatus <= disable;
OExE <= '0';
wait for CLK_PERIOD;
InxD <= std_logic_vector(to_unsigned(33, WIDTH));
tbStatus <= enable;
OExE <= '1';
wait for CLK_PERIOD;
tbStatus <= disable;
OExE <= '0';
wait for CLK_PERIOD;
tbStatus <= idle;
InxD <= (others => '0');
OExE <= '0';
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 2402e521c80939ea8071ff106cd2b34a | 0.468826 | 4.142857 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm/tstadpcm_cfg.vhd | 1 | 17,296 | ------------------------------------------------------------------------------
-- Configuration for ADPCM application
--
-- Id : $Id: $
-- File : $Url: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/27
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
-------------------------------------------------------------------------------
-- Array Size requiremetns
-- N_ROWS = 7
-- N_COLS = 7
-- N_HBUSN >= 2
-- N_HBUSS >= 2
-- N_VBUSE >= 1
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTADPCM is
function tstadpcmcfg return engineConfigRec;
end CfgLib_TSTADPCM;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTADPCM is
---------------------------------------------------------------------------
-- ROM DATA
---------------------------------------------------------------------------
type indextable_arr is array (0 to 15) of integer;
constant INDEXTABLE : indextable_arr := (
-1, -1, -1, -1, 2, 4, 6, 8,
-1, -1, -1, -1, 2, 4, 6, 8
);
type stepsizetable_arr is array (0 to 88) of integer;
constant STEPSIZETABLE : stepsizetable_arr := (
7, 8, 9, 10, 11, 12, 13, 14, 16, 17,
19, 21, 23, 25, 28, 31, 34, 37, 41, 45,
50, 55, 60, 66, 73, 80, 88, 97, 107, 118,
130, 143, 157, 173, 190, 209, 230, 253, 279, 307,
337, 371, 408, 449, 494, 544, 598, 658, 724, 796,
876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066,
2272, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358,
5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899,
15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767
);
----------------------------------------------------------------------------
-- tstadpcm configuration
----------------------------------------------------------------------------
function tstadpcmcfg return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- c_0_0 op0
cfg.gridConf(0)(0).procConf.AluOpxS := ALU_OP_ROM;
-- i.0
cfg.gridConf(0)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(0).HBusNxE(1) := '1';
-- o.0
cfg.gridConf(0)(0).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(0).routConf.o.HBusSxE(1) := '1';
-- c_0_1 op2
cfg.gridConf(0)(1).procConf.AluOpxS := ALU_OP_GT;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(1).procConf.ConstOpxD := i2cfgconst(88);
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(1).routConf.o.HBusNxE(0) := '1';
-- c_0_2 op1
cfg.gridConf(0)(2).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(0)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(0)(2).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(0)(2).routConf.i(1).LocalxE(LOCAL_SE) := '1';
-- o.0
cfg.gridConf(0)(2).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(2).routConf.o.HBusSxE(0) := '1';
-- c_0_3 op3
cfg.gridConf(0)(3).procConf.AluOpxS := ALU_OP_LT;
-- i.0
cfg.gridConf(0)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(3).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(0)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(3).procConf.ConstOpxD := i2cfgconst(0);
-- o.0
cfg.gridConf(0)(3).procConf.OutMuxS := O_NOREG;
-- c_0_4 op4b
cfg.gridConf(0)(4).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(0)(4).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(4).routConf.i(0).HBusSxE(0) := '1';
-- i.1
cfg.gridConf(0)(4).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(4).procConf.ConstOpxD := i2cfgconst(0);
-- i.2
cfg.gridConf(0)(4).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(4).routConf.i(2).LocalxE(LOCAL_W) := '1';
-- o.0
cfg.gridConf(0)(4).procConf.OutMuxS := O_NOREG;
-- c_1_1 op12
cfg.gridConf(1)(1).procConf.AluOpxS := ALU_OP_SRL;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(1).procConf.ConstOpxD := i2cfgconst(3);
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
-- c_1_2 op19
cfg.gridConf(1)(2).procConf.AluOpxS := ALU_OP_ROM;
-- i.0
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- o.0
cfg.gridConf(1)(2).procConf.OutMuxS := O_NOREG;
-- c_1_3 op4c
cfg.gridConf(1)(3).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(1).LocalxE(LOCAL_E) := '1';
-- i.2
cfg.gridConf(1)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(2).HBusNxE(0) := '1';
-- o.0
cfg.gridConf(1)(3).procConf.OutMuxS := O_NOREG;
-- c_1_4 op4a
cfg.gridConf(1)(4).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(1)(4).procConf.OpMuxS(0) := I_CONST;
cfg.gridConf(1)(4).procConf.ConstOpxD := i2cfgconst(88);
-- i.1
cfg.gridConf(1)(4).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(4).procConf.ConstOpxD := i2cfgconst(88);
-- i.2
cfg.gridConf(1)(4).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(4).routConf.i(2).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(1)(4).procConf.OutMuxS := O_NOREG;
-- c_2_0 op14
cfg.gridConf(2)(0).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(2)(0).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(1).LocalxE(LOCAL_E) := '1';
-- i.2
cfg.gridConf(2)(0).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(2).LocalxE(LOCAL_S) := '1';
-- o.0
cfg.gridConf(2)(0).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(0).routConf.o.HBusNxE(0) := '1';
-- c_2_1 op13
cfg.gridConf(2)(1).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op11
cfg.gridConf(2)(2).procConf.AluOpxS := ALU_OP_SRL;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(2).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op10
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_SRL;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(3).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(3).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
-- c_3_0 op7
cfg.gridConf(3)(0).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(0).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(3)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(0).procConf.ConstOpxD := i2cfgconst(4);
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 op15
cfg.gridConf(3)(1).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(3)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- i.1
cfg.gridConf(3)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(1).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(3)(1).procConf.OutMuxS := O_NOREG;
-- c_3_2 op17
cfg.gridConf(3)(2).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(3)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(1).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- c_3_3 feedthrough_c_3_3
cfg.gridConf(3)(3).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(3)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(3).routConf.i(0).HBusNxE(0) := '1';
-- o.0
cfg.gridConf(3)(3).procConf.OutMuxS := O_NOREG;
-- c_3_4 op25a
cfg.gridConf(3)(4).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(3)(4).procConf.OpMuxS(0) := I_CONST;
cfg.gridConf(3)(4).procConf.ConstOpxD := i2cfgconst(-32767);
-- i.1
cfg.gridConf(3)(4).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(4).procConf.ConstOpxD := i2cfgconst(-32767);
-- i.2
cfg.gridConf(3)(4).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(3)(4).routConf.i(2).HBusSxE(0) := '1';
-- o.0
cfg.gridConf(3)(4).procConf.OutMuxS := O_NOREG;
-- c_3_5 op25b
cfg.gridConf(3)(5).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(3)(5).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(5).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- i.1
cfg.gridConf(3)(5).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(5).procConf.ConstOpxD := i2cfgconst(32768);
-- i.2
cfg.gridConf(3)(5).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(3)(5).routConf.i(2).LocalxE(LOCAL_E) := '1';
-- o.0
cfg.gridConf(3)(5).procConf.OutMuxS := O_NOREG;
-- c_3_6 op23
cfg.gridConf(3)(6).procConf.AluOpxS := ALU_OP_GT;
-- i.0
cfg.gridConf(3)(6).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(6).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(3)(6).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(6).procConf.ConstOpxD := i2cfgconst(32767);
-- o.0
cfg.gridConf(3)(6).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(6).routConf.o.HBusSxE(0) := '1';
-- c_4_0 op6
cfg.gridConf(4)(0).procConf.AluOpxS := ALU_OP_AND;
-- i.0
cfg.gridConf(4)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(4)(0).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(4)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(4)(0).procConf.ConstOpxD := i2cfgconst(7);
-- o.0
cfg.gridConf(4)(0).procConf.OutMuxS := O_NOREG;
cfg.gridConf(4)(0).routConf.o.HBusNxE(0) := '1';
-- c_4_1 op8
cfg.gridConf(4)(1).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(4)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(4)(1).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(4)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(4)(1).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(4)(1).procConf.OutMuxS := O_NOREG;
-- c_4_2 op16
cfg.gridConf(4)(2).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(4)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(4)(2).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(4)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(4)(2).routConf.i(1).LocalxE(LOCAL_NW) := '1';
-- i.2
cfg.gridConf(4)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(4)(2).routConf.i(2).LocalxE(LOCAL_W) := '1';
-- o.0
cfg.gridConf(4)(2).procConf.OutMuxS := O_NOREG;
-- c_4_3 op18
cfg.gridConf(4)(3).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(4)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(4)(3).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(4)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(4)(3).routConf.i(1).LocalxE(LOCAL_NW) := '1';
-- i.2
cfg.gridConf(4)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(4)(3).routConf.i(2).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(4)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(4)(3).routConf.o.HBusSxE(1) := '1';
-- c_4_4 op25c
cfg.gridConf(4)(4).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(4)(4).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(4)(4).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(4)(4).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(4)(4).routConf.i(1).LocalxE(LOCAL_N) := '1';
-- i.2
cfg.gridConf(4)(4).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(4)(4).routConf.i(2).LocalxE(LOCAL_SE) := '1';
-- o.0
cfg.gridConf(4)(4).procConf.OutMuxS := O_NOREG;
-- c_4_5 op20
cfg.gridConf(4)(5).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(4)(5).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(4)(5).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(4)(5).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(4)(5).routConf.i(1).LocalxE(LOCAL_W) := '1';
-- o.0
cfg.gridConf(4)(5).procConf.OutMuxS := O_NOREG;
-- c_4_6 op22
cfg.gridConf(4)(6).procConf.AluOpxS := ALU_OP_MUX;
-- i.0
cfg.gridConf(4)(6).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(4)(6).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(4)(6).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(4)(6).routConf.i(1).VBusExE(0) := '1';
-- i.2
cfg.gridConf(4)(6).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(4)(6).routConf.i(2).LocalxE(LOCAL_S) := '1';
-- o.0
cfg.gridConf(4)(6).procConf.OutMuxS := O_NOREG;
-- c_5_2 op9
cfg.gridConf(5)(2).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(5)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(5)(2).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(5)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(5)(2).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(5)(2).procConf.OutMuxS := O_NOREG;
-- c_5_3 obuf
cfg.gridConf(5)(3).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(5)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(5)(3).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(5)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(5)(3).routConf.o.HBusNxE(1) := '1';
-- c_5_4 op21
cfg.gridConf(5)(4).procConf.AluOpxS := ALU_OP_SUB;
-- i.0
cfg.gridConf(5)(4).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(5)(4).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(5)(4).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(5)(4).routConf.i(1).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(5)(4).procConf.OutMuxS := O_NOREG;
-- c_5_5 op24
cfg.gridConf(5)(5).procConf.AluOpxS := ALU_OP_LT;
-- i.0
cfg.gridConf(5)(5).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(5)(5).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(5)(5).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(5)(5).procConf.ConstOpxD := i2cfgconst(-32768);
-- o.0
cfg.gridConf(5)(5).procConf.OutMuxS := O_NOREG;
-- c_5_6 op5
cfg.gridConf(5)(6).procConf.AluOpxS := ALU_OP_TSTBITAT1;
-- i.0
cfg.gridConf(5)(6).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(5)(6).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(5)(6).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(5)(6).procConf.ConstOpxD := i2cfgconst(8);
-- o.0
cfg.gridConf(5)(6).procConf.OutMuxS := O_NOREG;
-- c_6_5 feedthrough_c_6_5
cfg.gridConf(6)(5).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(6)(5).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(6)(5).routConf.i(0).LocalxE(LOCAL_NW) := '1';
-- o.0
cfg.gridConf(6)(5).procConf.OutMuxS := O_NOREG;
cfg.gridConf(6)(5).routConf.o.VBusExE(0) := '1';
-- input drivers
cfg.inputDriverConf(0)(0)(1) := '1';
cfg.inputDriverConf(0)(4)(1) := '1';
cfg.inputDriverConf(0)(5)(1) := '1';
-- output drivers
cfg.outputDriverConf(1)(6)(1) := '1';
for i in INDEXTABLE'range loop
cfg.memoryConf(0)(i) :=
std_logic_vector(to_signed(INDEXTABLE(i), DATAWIDTH));
end loop; -- i
for i in STEPSIZETABLE'range loop
cfg.memoryConf(1)(i) :=
std_logic_vector(to_signed(STEPSIZETABLE(i), DATAWIDTH));
end loop; -- i
---------------------------------------------------------------------------
-- FIXME Naming of inport and outport is consistent but a little
-- confusing. Inport is the inport of the array, i.e. die outport
-- of the FIFO.
---------------------------------------------------------------------------
-- i/o port controller
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_ON;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_ON;
-- -- activate write to output FIFO0 after 2 cycles
-- cfg.outportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEUP;
-- cfg.outportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
-- cfg.outportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(1, CCNTWIDTH));
-- cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
--
-- -- deactivate read from input FIFO0 2 cycles before end
-- cfg.inportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
-- cfg.inportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
-- cfg.inportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
-- cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
--
-- cfg.inportConf(1).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
-- cfg.inportConf(1).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
-- cfg.inportConf(1).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
-- cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_CMP0;
--
-- cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstadpcmcfg;
end CfgLib_TSTADPCM;
| bsd-3-clause | 4961014a9e469f093ab52ad7ce54652c | 0.606441 | 2.30429 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/netgen/par/neander_timesim.vhd | 1 | 370,079 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: neander_timesim.vhd
-- /___/ /\ Timestamp: Sun May 15 14:37:41 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -s 4 -pcf neander.pcf -rpw 100 -tpw 0 -ar Structure -tm neander -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim neander.ncd neander_timesim.vhd
-- Device : 3s100ecp132-4 (PRODUCTION 1.27 2013-10-13)
-- Input file : neander.ncd
-- Output file : C:\Users\franc\Documents\neander\neanderImplementation\netgen\par\neander_timesim.vhd
-- # of Entities : 1
-- Design Name : neander
-- Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity neander is
port (
clk : in STD_LOGIC := 'X';
debug_out : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
enable : in STD_LOGIC := 'X'
);
end neander;
architecture Structure of neander is
signal clk_BUFGP : STD_LOGIC;
signal rst_IBUF_1438 : STD_LOGIC;
signal exec_HLT : STD_LOGIC;
signal CU_N9_0 : STD_LOGIC;
signal CU_next_state_mux0012_0_8_0 : STD_LOGIC;
signal exec_STA : STD_LOGIC;
signal CU_N7 : STD_LOGIC;
signal CU_loadRDM_1452 : STD_LOGIC;
signal CU_sel_mux_RDM_1453 : STD_LOGIC;
signal CU_loadRDM_mux00004_0 : STD_LOGIC;
signal CU_loadRDM_mux000015_0 : STD_LOGIC;
signal CU_sel_ula_and0000_0 : STD_LOGIC;
signal exec_NOP_0 : STD_LOGIC;
signal NZ_data_N_1484 : STD_LOGIC;
signal CU_current_state_not0001_inv_0 : STD_LOGIC;
signal N32 : STD_LOGIC;
signal CU_N18_0 : STD_LOGIC;
signal NZ_data_Z_1506 : STD_LOGIC;
signal N30_0 : STD_LOGIC;
signal alu_MULTIPLICATION_cmp_eq0000_0 : STD_LOGIC;
signal CU_stop_s_1511 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal CU_loadRI_1515 : STD_LOGIC;
signal alu_Z_cmp_eq00007_0 : STD_LOGIC;
signal enable_IBUF_1520 : STD_LOGIC;
signal N24 : STD_LOGIC;
signal CU_next_state_mux0012_12_13_0 : STD_LOGIC;
signal CU_state_timer_not0001_inv : STD_LOGIC;
signal CU_loadPC_1524 : STD_LOGIC;
signal CU_PC_inc_1525 : STD_LOGIC;
signal PC_data_not0001_0 : STD_LOGIC;
signal CU_next_state_mux0012_13_14_0 : STD_LOGIC;
signal alu_Madd_result_addsub0000_cy_1_Q : STD_LOGIC;
signal alu_Madd_result_addsub0000_cy_3_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_1_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_3_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_5_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_7_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_9_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_11_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_13_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_15_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_17_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_19_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_21_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_23_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_25_Q : STD_LOGIC;
signal CU_Mcount_state_timer_cy_27_Q : STD_LOGIC;
signal PC_Mcount_data_cy_1_Q : STD_LOGIC;
signal PC_Mcount_data_cy_3_Q : STD_LOGIC;
signal CU_loadAC_1652 : STD_LOGIC;
signal alu_Mmux_result_3_f5 : STD_LOGIC;
signal alu_Mmux_result_4_f5 : STD_LOGIC;
signal alu_Mmux_result_3_f51 : STD_LOGIC;
signal alu_Mmux_result_4_f51 : STD_LOGIC;
signal alu_Mmux_result_3_f52 : STD_LOGIC;
signal alu_Mmux_result_4_f52 : STD_LOGIC;
signal alu_Mmux_result_3_f53 : STD_LOGIC;
signal alu_Mmux_result_4_f53 : STD_LOGIC;
signal alu_Mmux_result_3_f54 : STD_LOGIC;
signal alu_Mmux_result_4_f54 : STD_LOGIC;
signal alu_Mmux_result_3_f55 : STD_LOGIC;
signal alu_Mmux_result_4_f55 : STD_LOGIC;
signal alu_Mmux_result_3_f56 : STD_LOGIC;
signal alu_Mmux_result_4_f56 : STD_LOGIC;
signal alu_Mmux_result_3_f57 : STD_LOGIC;
signal alu_Mmux_result_4_f57 : STD_LOGIC;
signal ULA_N : STD_LOGIC;
signal CU_N10 : STD_LOGIC;
signal CU_loadREM_1685 : STD_LOGIC;
signal CU_next_state_mux0012_13_38 : STD_LOGIC;
signal exec_NOT : STD_LOGIC;
signal exec_JN : STD_LOGIC;
signal exec_JZ : STD_LOGIC;
signal CU_next_state_mux0012_4_11_0 : STD_LOGIC;
signal alu_Z_cmp_eq000028_SW0_O : STD_LOGIC;
signal CU_next_state_or0001 : STD_LOGIC;
signal N14_0 : STD_LOGIC;
signal CU_next_state_mux0012_12_22_O : STD_LOGIC;
signal CU_next_state_mux0012_7_11_0 : STD_LOGIC;
signal CU_next_state_mux0012_4_23_0 : STD_LOGIC;
signal CU_next_state_mux0012_13_56_O : STD_LOGIC;
signal CU_sel_1698 : STD_LOGIC;
signal CU_next_state_11_DXMUX_1734 : STD_LOGIC;
signal CU_next_state_11_DYMUX_1720 : STD_LOGIC;
signal CU_next_state_11_SRINV_1711 : STD_LOGIC;
signal CU_next_state_11_CLKINV_1710 : STD_LOGIC;
signal CU_next_state_13_DXMUX_1776 : STD_LOGIC;
signal CU_next_state_13_DYMUX_1762 : STD_LOGIC;
signal CU_next_state_13_SRINV_1754 : STD_LOGIC;
signal CU_next_state_13_CLKINV_1753 : STD_LOGIC;
signal R_D_M_reg_1_DXMUX_1821 : STD_LOGIC;
signal R_D_M_reg_1_DYMUX_1805 : STD_LOGIC;
signal R_D_M_reg_1_SRINV_1796 : STD_LOGIC;
signal R_D_M_reg_1_CLKINV_1795 : STD_LOGIC;
signal R_D_M_reg_1_CEINV_1794 : STD_LOGIC;
signal CU_loadRDM_DYMUX_1845 : STD_LOGIC;
signal CU_loadRDM_mux0000 : STD_LOGIC;
signal CU_loadRDM_CLKINV_1834 : STD_LOGIC;
signal R_D_M_reg_3_DXMUX_1890 : STD_LOGIC;
signal R_D_M_reg_3_DYMUX_1874 : STD_LOGIC;
signal R_D_M_reg_3_SRINV_1865 : STD_LOGIC;
signal R_D_M_reg_3_CLKINV_1864 : STD_LOGIC;
signal R_D_M_reg_3_CEINV_1863 : STD_LOGIC;
signal CU_sel_ula_1_DXMUX_1931 : STD_LOGIC;
signal CU_sel_ula_1_DYMUX_1919 : STD_LOGIC;
signal CU_sel_ula_1_CLKINV_1911 : STD_LOGIC;
signal CU_sel_ula_1_CEINV_1910 : STD_LOGIC;
signal R_D_M_reg_5_DXMUX_1974 : STD_LOGIC;
signal R_D_M_reg_5_DYMUX_1958 : STD_LOGIC;
signal R_D_M_reg_5_SRINV_1949 : STD_LOGIC;
signal R_D_M_reg_5_CLKINV_1948 : STD_LOGIC;
signal R_D_M_reg_5_CEINV_1947 : STD_LOGIC;
signal exec_NOP : STD_LOGIC;
signal CU_sel_ula_2_DYMUX_2003 : STD_LOGIC;
signal CU_sel_ula_2_CLKINV_1995 : STD_LOGIC;
signal CU_sel_ula_2_CEINV_1994 : STD_LOGIC;
signal R_D_M_reg_7_DXMUX_2053 : STD_LOGIC;
signal R_D_M_reg_7_DYMUX_2037 : STD_LOGIC;
signal R_D_M_reg_7_SRINV_2028 : STD_LOGIC;
signal R_D_M_reg_7_CLKINV_2027 : STD_LOGIC;
signal R_D_M_reg_7_CEINV_2026 : STD_LOGIC;
signal CU_current_state_3_DXMUX_2076 : STD_LOGIC;
signal CU_current_state_3_DYMUX_2070 : STD_LOGIC;
signal CU_current_state_3_CLKINV_2068 : STD_LOGIC;
signal CU_current_state_3_CEINV_2067 : STD_LOGIC;
signal CU_next_state_7_DXMUX_2109 : STD_LOGIC;
signal N32_pack_2 : STD_LOGIC;
signal CU_next_state_7_CLKINV_2093 : STD_LOGIC;
signal CU_next_state_7_FFX_RSTAND_2114 : STD_LOGIC;
signal CU_current_state_5_DXMUX_2131 : STD_LOGIC;
signal CU_current_state_5_DYMUX_2125 : STD_LOGIC;
signal CU_current_state_5_CLKINV_2123 : STD_LOGIC;
signal CU_current_state_5_CEINV_2122 : STD_LOGIC;
signal CU_current_state_7_DXMUX_2151 : STD_LOGIC;
signal CU_current_state_7_DYMUX_2145 : STD_LOGIC;
signal CU_current_state_7_CLKINV_2143 : STD_LOGIC;
signal CU_current_state_7_CEINV_2142 : STD_LOGIC;
signal CU_current_state_9_DXMUX_2171 : STD_LOGIC;
signal CU_current_state_9_DYMUX_2165 : STD_LOGIC;
signal CU_current_state_9_CLKINV_2163 : STD_LOGIC;
signal CU_current_state_9_CEINV_2162 : STD_LOGIC;
signal CU_N18 : STD_LOGIC;
signal CU_loadRDM_mux00004_2190 : STD_LOGIC;
signal N30 : STD_LOGIC;
signal alu_MULTIPLICATION_cmp_eq0000 : STD_LOGIC;
signal CU_stop_s_DYMUX_2233 : STD_LOGIC;
signal CU_stop_s_BYINV_2232 : STD_LOGIC;
signal CU_stop_s_CLKINV_2230 : STD_LOGIC;
signal CU_stop_s_CEINV_2229 : STD_LOGIC;
signal CU_loadRI_DXMUX_2269 : STD_LOGIC;
signal CU_loadRI_mux0000_2266 : STD_LOGIC;
signal N10_pack_2 : STD_LOGIC;
signal CU_loadRI_CLKINV_2253 : STD_LOGIC;
signal CU_current_state_11_DXMUX_2291 : STD_LOGIC;
signal CU_current_state_11_DYMUX_2285 : STD_LOGIC;
signal CU_current_state_11_CLKINV_2283 : STD_LOGIC;
signal CU_current_state_11_CEINV_2282 : STD_LOGIC;
signal CU_current_state_13_DXMUX_2311 : STD_LOGIC;
signal CU_current_state_13_DYMUX_2305 : STD_LOGIC;
signal CU_current_state_13_CLKINV_2303 : STD_LOGIC;
signal CU_current_state_13_CEINV_2302 : STD_LOGIC;
signal alu_Z_cmp_eq00007_2325 : STD_LOGIC;
signal CU_next_state_mux0012_12_13_2349 : STD_LOGIC;
signal N24_pack_1 : STD_LOGIC;
signal RI_reg_5_DXMUX_2372 : STD_LOGIC;
signal RI_reg_5_DYMUX_2363 : STD_LOGIC;
signal RI_reg_5_SRINV_2361 : STD_LOGIC;
signal RI_reg_5_CLKINV_2360 : STD_LOGIC;
signal RI_reg_5_CEINV_2359 : STD_LOGIC;
signal RI_reg_7_DXMUX_2400 : STD_LOGIC;
signal RI_reg_7_DYMUX_2391 : STD_LOGIC;
signal RI_reg_7_SRINV_2389 : STD_LOGIC;
signal RI_reg_7_CLKINV_2388 : STD_LOGIC;
signal RI_reg_7_CEINV_2387 : STD_LOGIC;
signal CU_current_state_not0001_inv : STD_LOGIC;
signal CU_loadPC_DXMUX_2448 : STD_LOGIC;
signal CU_loadPC_mux0000 : STD_LOGIC;
signal PC_data_not0001 : STD_LOGIC;
signal CU_loadPC_CLKINV_2429 : STD_LOGIC;
signal CU_wr_enable_mem_0_DXMUX_2483 : STD_LOGIC;
signal CU_wr_enable_mem_0_mux0000 : STD_LOGIC;
signal CU_next_state_mux0012_13_14_2472 : STD_LOGIC;
signal CU_wr_enable_mem_0_CLKINV_2465 : STD_LOGIC;
signal alu_MULTIPLICATION_1_DXMUX_2502 : STD_LOGIC;
signal alu_MULTIPLICATION_1_DYMUX_2497 : STD_LOGIC;
signal alu_MULTIPLICATION_1_CLKINVNOT : STD_LOGIC;
signal alu_MULTIPLICATION_3_DXMUX_2518 : STD_LOGIC;
signal alu_MULTIPLICATION_3_DYMUX_2513 : STD_LOGIC;
signal alu_MULTIPLICATION_3_CLKINVNOT : STD_LOGIC;
signal alu_MULTIPLICATION_5_DXMUX_2534 : STD_LOGIC;
signal alu_MULTIPLICATION_5_DYMUX_2529 : STD_LOGIC;
signal alu_MULTIPLICATION_5_CLKINVNOT : STD_LOGIC;
signal alu_MULTIPLICATION_7_DXMUX_2550 : STD_LOGIC;
signal alu_MULTIPLICATION_7_DYMUX_2545 : STD_LOGIC;
signal alu_MULTIPLICATION_7_CLKINVNOT : STD_LOGIC;
signal CU_current_state_1_DXMUX_2569 : STD_LOGIC;
signal CU_current_state_1_DYMUX_2563 : STD_LOGIC;
signal CU_current_state_1_CLKINV_2561 : STD_LOGIC;
signal CU_current_state_1_CEINV_2560 : STD_LOGIC;
signal alu_result_addsub0000_0_XORF_2608 : STD_LOGIC;
signal alu_result_addsub0000_0_CYINIT_2607 : STD_LOGIC;
signal alu_result_addsub0000_0_CY0F_2606 : STD_LOGIC;
signal alu_result_addsub0000_0_CYSELF_2598 : STD_LOGIC;
signal alu_result_addsub0000_0_BXINV_2596 : STD_LOGIC;
signal alu_result_addsub0000_0_XORG_2594 : STD_LOGIC;
signal alu_result_addsub0000_0_CYMUXG_2593 : STD_LOGIC;
signal alu_Madd_result_addsub0000_cy_0_Q : STD_LOGIC;
signal alu_result_addsub0000_0_CY0G_2591 : STD_LOGIC;
signal alu_result_addsub0000_0_CYSELG_2583 : STD_LOGIC;
signal alu_result_addsub0000_2_XORF_2647 : STD_LOGIC;
signal alu_result_addsub0000_2_CYINIT_2646 : STD_LOGIC;
signal alu_result_addsub0000_2_CY0F_2645 : STD_LOGIC;
signal alu_result_addsub0000_2_XORG_2635 : STD_LOGIC;
signal alu_Madd_result_addsub0000_cy_2_Q : STD_LOGIC;
signal alu_result_addsub0000_2_CYSELF_2633 : STD_LOGIC;
signal alu_result_addsub0000_2_CYMUXFAST_2632 : STD_LOGIC;
signal alu_result_addsub0000_2_CYAND_2631 : STD_LOGIC;
signal alu_result_addsub0000_2_FASTCARRY_2630 : STD_LOGIC;
signal alu_result_addsub0000_2_CYMUXG2_2629 : STD_LOGIC;
signal alu_result_addsub0000_2_CYMUXF2_2628 : STD_LOGIC;
signal alu_result_addsub0000_2_CY0G_2627 : STD_LOGIC;
signal alu_result_addsub0000_2_CYSELG_2619 : STD_LOGIC;
signal alu_result_addsub0000_4_XORF_2686 : STD_LOGIC;
signal alu_result_addsub0000_4_CYINIT_2685 : STD_LOGIC;
signal alu_result_addsub0000_4_CY0F_2684 : STD_LOGIC;
signal alu_result_addsub0000_4_XORG_2674 : STD_LOGIC;
signal alu_Madd_result_addsub0000_cy_4_Q : STD_LOGIC;
signal alu_result_addsub0000_4_CYSELF_2672 : STD_LOGIC;
signal alu_result_addsub0000_4_CYMUXFAST_2671 : STD_LOGIC;
signal alu_result_addsub0000_4_CYAND_2670 : STD_LOGIC;
signal alu_result_addsub0000_4_FASTCARRY_2669 : STD_LOGIC;
signal alu_result_addsub0000_4_CYMUXG2_2668 : STD_LOGIC;
signal alu_result_addsub0000_4_CYMUXF2_2667 : STD_LOGIC;
signal alu_result_addsub0000_4_CY0G_2666 : STD_LOGIC;
signal alu_result_addsub0000_4_CYSELG_2658 : STD_LOGIC;
signal alu_result_addsub0000_6_XORF_2717 : STD_LOGIC;
signal alu_result_addsub0000_6_CYINIT_2716 : STD_LOGIC;
signal alu_result_addsub0000_6_CY0F_2715 : STD_LOGIC;
signal alu_result_addsub0000_6_CYSELF_2707 : STD_LOGIC;
signal alu_result_addsub0000_6_XORG_2704 : STD_LOGIC;
signal alu_Madd_result_addsub0000_cy_6_Q : STD_LOGIC;
signal CU_Result_0_XORF_2753 : STD_LOGIC;
signal CU_Result_0_LOGIC_ZERO_2752 : STD_LOGIC;
signal CU_Result_0_CYINIT_2751 : STD_LOGIC;
signal CU_Result_0_CYSELF_2742 : STD_LOGIC;
signal CU_Result_0_F : STD_LOGIC;
signal CU_Result_0_BXINV_2740 : STD_LOGIC;
signal CU_Result_0_XORG_2738 : STD_LOGIC;
signal CU_Result_0_CYMUXG_2737 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_0_Q : STD_LOGIC;
signal CU_Result_0_LOGIC_ONE_2735 : STD_LOGIC;
signal CU_Result_0_CYSELG_2726 : STD_LOGIC;
signal CU_Result_2_XORF_2791 : STD_LOGIC;
signal CU_Result_2_CYINIT_2790 : STD_LOGIC;
signal CU_Result_2_XORG_2779 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_2_Q : STD_LOGIC;
signal CU_Result_2_CYSELF_2777 : STD_LOGIC;
signal CU_Result_2_CYMUXFAST_2776 : STD_LOGIC;
signal CU_Result_2_CYAND_2775 : STD_LOGIC;
signal CU_Result_2_FASTCARRY_2774 : STD_LOGIC;
signal CU_Result_2_CYMUXG2_2773 : STD_LOGIC;
signal CU_Result_2_CYMUXF2_2772 : STD_LOGIC;
signal CU_Result_2_LOGIC_ONE_2771 : STD_LOGIC;
signal CU_Result_2_CYSELG_2762 : STD_LOGIC;
signal CU_Result_4_XORF_2829 : STD_LOGIC;
signal CU_Result_4_CYINIT_2828 : STD_LOGIC;
signal CU_Result_4_XORG_2817 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_4_Q : STD_LOGIC;
signal CU_Result_4_CYSELF_2815 : STD_LOGIC;
signal CU_Result_4_CYMUXFAST_2814 : STD_LOGIC;
signal CU_Result_4_CYAND_2813 : STD_LOGIC;
signal CU_Result_4_FASTCARRY_2812 : STD_LOGIC;
signal CU_Result_4_CYMUXG2_2811 : STD_LOGIC;
signal CU_Result_4_CYMUXF2_2810 : STD_LOGIC;
signal CU_Result_4_LOGIC_ONE_2809 : STD_LOGIC;
signal CU_Result_4_CYSELG_2800 : STD_LOGIC;
signal CU_Result_6_XORF_2867 : STD_LOGIC;
signal CU_Result_6_CYINIT_2866 : STD_LOGIC;
signal CU_Result_6_XORG_2855 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_6_Q : STD_LOGIC;
signal CU_Result_6_CYSELF_2853 : STD_LOGIC;
signal CU_Result_6_CYMUXFAST_2852 : STD_LOGIC;
signal CU_Result_6_CYAND_2851 : STD_LOGIC;
signal CU_Result_6_FASTCARRY_2850 : STD_LOGIC;
signal CU_Result_6_CYMUXG2_2849 : STD_LOGIC;
signal CU_Result_6_CYMUXF2_2848 : STD_LOGIC;
signal CU_Result_6_LOGIC_ONE_2847 : STD_LOGIC;
signal CU_Result_6_CYSELG_2838 : STD_LOGIC;
signal CU_Result_8_XORF_2905 : STD_LOGIC;
signal CU_Result_8_CYINIT_2904 : STD_LOGIC;
signal CU_Result_8_XORG_2893 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_8_Q : STD_LOGIC;
signal CU_Result_8_CYSELF_2891 : STD_LOGIC;
signal CU_Result_8_CYMUXFAST_2890 : STD_LOGIC;
signal CU_Result_8_CYAND_2889 : STD_LOGIC;
signal CU_Result_8_FASTCARRY_2888 : STD_LOGIC;
signal CU_Result_8_CYMUXG2_2887 : STD_LOGIC;
signal CU_Result_8_CYMUXF2_2886 : STD_LOGIC;
signal CU_Result_8_LOGIC_ONE_2885 : STD_LOGIC;
signal CU_Result_8_CYSELG_2876 : STD_LOGIC;
signal CU_Result_10_XORF_2943 : STD_LOGIC;
signal CU_Result_10_CYINIT_2942 : STD_LOGIC;
signal CU_Result_10_XORG_2931 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_10_Q : STD_LOGIC;
signal CU_Result_10_CYSELF_2929 : STD_LOGIC;
signal CU_Result_10_CYMUXFAST_2928 : STD_LOGIC;
signal CU_Result_10_CYAND_2927 : STD_LOGIC;
signal CU_Result_10_FASTCARRY_2926 : STD_LOGIC;
signal CU_Result_10_CYMUXG2_2925 : STD_LOGIC;
signal CU_Result_10_CYMUXF2_2924 : STD_LOGIC;
signal CU_Result_10_LOGIC_ONE_2923 : STD_LOGIC;
signal CU_Result_10_CYSELG_2914 : STD_LOGIC;
signal CU_Result_12_XORF_2981 : STD_LOGIC;
signal CU_Result_12_CYINIT_2980 : STD_LOGIC;
signal CU_Result_12_XORG_2969 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_12_Q : STD_LOGIC;
signal CU_Result_12_CYSELF_2967 : STD_LOGIC;
signal CU_Result_12_CYMUXFAST_2966 : STD_LOGIC;
signal CU_Result_12_CYAND_2965 : STD_LOGIC;
signal CU_Result_12_FASTCARRY_2964 : STD_LOGIC;
signal CU_Result_12_CYMUXG2_2963 : STD_LOGIC;
signal CU_Result_12_CYMUXF2_2962 : STD_LOGIC;
signal CU_Result_12_LOGIC_ONE_2961 : STD_LOGIC;
signal CU_Result_12_CYSELG_2952 : STD_LOGIC;
signal CU_Result_14_XORF_3019 : STD_LOGIC;
signal CU_Result_14_CYINIT_3018 : STD_LOGIC;
signal CU_Result_14_XORG_3007 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_14_Q : STD_LOGIC;
signal CU_Result_14_CYSELF_3005 : STD_LOGIC;
signal CU_Result_14_CYMUXFAST_3004 : STD_LOGIC;
signal CU_Result_14_CYAND_3003 : STD_LOGIC;
signal CU_Result_14_FASTCARRY_3002 : STD_LOGIC;
signal CU_Result_14_CYMUXG2_3001 : STD_LOGIC;
signal CU_Result_14_CYMUXF2_3000 : STD_LOGIC;
signal CU_Result_14_LOGIC_ONE_2999 : STD_LOGIC;
signal CU_Result_14_CYSELG_2990 : STD_LOGIC;
signal CU_Result_16_XORF_3057 : STD_LOGIC;
signal CU_Result_16_CYINIT_3056 : STD_LOGIC;
signal CU_Result_16_XORG_3045 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_16_Q : STD_LOGIC;
signal CU_Result_16_CYSELF_3043 : STD_LOGIC;
signal CU_Result_16_CYMUXFAST_3042 : STD_LOGIC;
signal CU_Result_16_CYAND_3041 : STD_LOGIC;
signal CU_Result_16_FASTCARRY_3040 : STD_LOGIC;
signal CU_Result_16_CYMUXG2_3039 : STD_LOGIC;
signal CU_Result_16_CYMUXF2_3038 : STD_LOGIC;
signal CU_Result_16_LOGIC_ONE_3037 : STD_LOGIC;
signal CU_Result_16_CYSELG_3028 : STD_LOGIC;
signal CU_Result_18_XORF_3095 : STD_LOGIC;
signal CU_Result_18_CYINIT_3094 : STD_LOGIC;
signal CU_Result_18_XORG_3083 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_18_Q : STD_LOGIC;
signal CU_Result_18_CYSELF_3081 : STD_LOGIC;
signal CU_Result_18_CYMUXFAST_3080 : STD_LOGIC;
signal CU_Result_18_CYAND_3079 : STD_LOGIC;
signal CU_Result_18_FASTCARRY_3078 : STD_LOGIC;
signal CU_Result_18_CYMUXG2_3077 : STD_LOGIC;
signal CU_Result_18_CYMUXF2_3076 : STD_LOGIC;
signal CU_Result_18_LOGIC_ONE_3075 : STD_LOGIC;
signal CU_Result_18_CYSELG_3066 : STD_LOGIC;
signal CU_Result_20_XORF_3133 : STD_LOGIC;
signal CU_Result_20_CYINIT_3132 : STD_LOGIC;
signal CU_Result_20_XORG_3121 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_20_Q : STD_LOGIC;
signal CU_Result_20_CYSELF_3119 : STD_LOGIC;
signal CU_Result_20_CYMUXFAST_3118 : STD_LOGIC;
signal CU_Result_20_CYAND_3117 : STD_LOGIC;
signal CU_Result_20_FASTCARRY_3116 : STD_LOGIC;
signal CU_Result_20_CYMUXG2_3115 : STD_LOGIC;
signal CU_Result_20_CYMUXF2_3114 : STD_LOGIC;
signal CU_Result_20_LOGIC_ONE_3113 : STD_LOGIC;
signal CU_Result_20_CYSELG_3104 : STD_LOGIC;
signal CU_Result_22_XORF_3171 : STD_LOGIC;
signal CU_Result_22_CYINIT_3170 : STD_LOGIC;
signal CU_Result_22_XORG_3159 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_22_Q : STD_LOGIC;
signal CU_Result_22_CYSELF_3157 : STD_LOGIC;
signal CU_Result_22_CYMUXFAST_3156 : STD_LOGIC;
signal CU_Result_22_CYAND_3155 : STD_LOGIC;
signal CU_Result_22_FASTCARRY_3154 : STD_LOGIC;
signal CU_Result_22_CYMUXG2_3153 : STD_LOGIC;
signal CU_Result_22_CYMUXF2_3152 : STD_LOGIC;
signal CU_Result_22_LOGIC_ONE_3151 : STD_LOGIC;
signal CU_Result_22_CYSELG_3142 : STD_LOGIC;
signal CU_Result_24_XORF_3209 : STD_LOGIC;
signal CU_Result_24_CYINIT_3208 : STD_LOGIC;
signal CU_Result_24_XORG_3197 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_24_Q : STD_LOGIC;
signal CU_Result_24_CYSELF_3195 : STD_LOGIC;
signal CU_Result_24_CYMUXFAST_3194 : STD_LOGIC;
signal CU_Result_24_CYAND_3193 : STD_LOGIC;
signal CU_Result_24_FASTCARRY_3192 : STD_LOGIC;
signal CU_Result_24_CYMUXG2_3191 : STD_LOGIC;
signal CU_Result_24_CYMUXF2_3190 : STD_LOGIC;
signal CU_Result_24_LOGIC_ONE_3189 : STD_LOGIC;
signal CU_Result_24_CYSELG_3180 : STD_LOGIC;
signal CU_Result_26_XORF_3247 : STD_LOGIC;
signal CU_Result_26_CYINIT_3246 : STD_LOGIC;
signal CU_Result_26_XORG_3235 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_26_Q : STD_LOGIC;
signal CU_Result_26_CYSELF_3233 : STD_LOGIC;
signal CU_Result_26_CYMUXFAST_3232 : STD_LOGIC;
signal CU_Result_26_CYAND_3231 : STD_LOGIC;
signal CU_Result_26_FASTCARRY_3230 : STD_LOGIC;
signal CU_Result_26_CYMUXG2_3229 : STD_LOGIC;
signal CU_Result_26_CYMUXF2_3228 : STD_LOGIC;
signal CU_Result_26_LOGIC_ONE_3227 : STD_LOGIC;
signal CU_Result_26_CYSELG_3218 : STD_LOGIC;
signal CU_Result_28_XORF_3285 : STD_LOGIC;
signal CU_Result_28_CYINIT_3284 : STD_LOGIC;
signal CU_Result_28_XORG_3273 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_28_Q : STD_LOGIC;
signal CU_Result_28_CYSELF_3271 : STD_LOGIC;
signal CU_Result_28_CYMUXFAST_3270 : STD_LOGIC;
signal CU_Result_28_CYAND_3269 : STD_LOGIC;
signal CU_Result_28_FASTCARRY_3268 : STD_LOGIC;
signal CU_Result_28_CYMUXG2_3267 : STD_LOGIC;
signal CU_Result_28_CYMUXF2_3266 : STD_LOGIC;
signal CU_Result_28_LOGIC_ONE_3265 : STD_LOGIC;
signal CU_Result_28_CYSELG_3256 : STD_LOGIC;
signal CU_Result_30_XORF_3316 : STD_LOGIC;
signal CU_Result_30_LOGIC_ONE_3315 : STD_LOGIC;
signal CU_Result_30_CYINIT_3314 : STD_LOGIC;
signal CU_Result_30_CYSELF_3305 : STD_LOGIC;
signal CU_Result_30_XORG_3302 : STD_LOGIC;
signal CU_Mcount_state_timer_cy_30_Q : STD_LOGIC;
signal PC_data_0_FFY_RST : STD_LOGIC;
signal PC_data_0_FFX_RST : STD_LOGIC;
signal PC_data_0_DXMUX_3367 : STD_LOGIC;
signal PC_data_0_XORF_3365 : STD_LOGIC;
signal PC_data_0_CYINIT_3364 : STD_LOGIC;
signal PC_data_0_CYSELF_3357 : STD_LOGIC;
signal PC_data_0_DYMUX_3347 : STD_LOGIC;
signal PC_data_0_XORG_3345 : STD_LOGIC;
signal PC_data_0_CYMUXG_3344 : STD_LOGIC;
signal PC_Mcount_data_cy_0_Q : STD_LOGIC;
signal PC_data_0_LOGIC_ZERO_3342 : STD_LOGIC;
signal PC_data_0_CYSELG_3335 : STD_LOGIC;
signal PC_data_0_SRINV_3333 : STD_LOGIC;
signal PC_data_0_CLKINV_3332 : STD_LOGIC;
signal PC_data_0_CEINV_3331 : STD_LOGIC;
signal PC_data_2_DXMUX_3427 : STD_LOGIC;
signal PC_data_2_XORF_3425 : STD_LOGIC;
signal PC_data_2_CYINIT_3424 : STD_LOGIC;
signal PC_data_2_DYMUX_3409 : STD_LOGIC;
signal PC_data_2_XORG_3407 : STD_LOGIC;
signal PC_Mcount_data_cy_2_Q : STD_LOGIC;
signal PC_data_2_CYSELF_3405 : STD_LOGIC;
signal PC_data_2_CYMUXFAST_3404 : STD_LOGIC;
signal PC_data_2_CYAND_3403 : STD_LOGIC;
signal PC_data_2_FASTCARRY_3402 : STD_LOGIC;
signal PC_data_2_CYMUXG2_3401 : STD_LOGIC;
signal PC_data_2_CYMUXF2_3400 : STD_LOGIC;
signal PC_data_2_LOGIC_ZERO_3399 : STD_LOGIC;
signal PC_data_2_CYSELG_3392 : STD_LOGIC;
signal PC_data_2_SRINV_3390 : STD_LOGIC;
signal PC_data_2_CLKINV_3389 : STD_LOGIC;
signal PC_data_2_CEINV_3388 : STD_LOGIC;
signal PC_data_4_DXMUX_3487 : STD_LOGIC;
signal PC_data_4_XORF_3485 : STD_LOGIC;
signal PC_data_4_CYINIT_3484 : STD_LOGIC;
signal PC_data_4_DYMUX_3469 : STD_LOGIC;
signal PC_data_4_XORG_3467 : STD_LOGIC;
signal PC_Mcount_data_cy_4_Q : STD_LOGIC;
signal PC_data_4_CYSELF_3465 : STD_LOGIC;
signal PC_data_4_CYMUXFAST_3464 : STD_LOGIC;
signal PC_data_4_CYAND_3463 : STD_LOGIC;
signal PC_data_4_FASTCARRY_3462 : STD_LOGIC;
signal PC_data_4_CYMUXG2_3461 : STD_LOGIC;
signal PC_data_4_CYMUXF2_3460 : STD_LOGIC;
signal PC_data_4_LOGIC_ZERO_3459 : STD_LOGIC;
signal PC_data_4_CYSELG_3452 : STD_LOGIC;
signal PC_data_4_SRINV_3450 : STD_LOGIC;
signal PC_data_4_CLKINV_3449 : STD_LOGIC;
signal PC_data_4_CEINV_3448 : STD_LOGIC;
signal PC_data_6_DXMUX_3540 : STD_LOGIC;
signal PC_data_6_XORF_3538 : STD_LOGIC;
signal PC_data_6_LOGIC_ZERO_3537 : STD_LOGIC;
signal PC_data_6_CYINIT_3536 : STD_LOGIC;
signal PC_data_6_CYSELF_3529 : STD_LOGIC;
signal PC_data_6_DYMUX_3520 : STD_LOGIC;
signal PC_data_6_XORG_3518 : STD_LOGIC;
signal PC_Mcount_data_cy_6_Q : STD_LOGIC;
signal PC_data_6_SRINV_3509 : STD_LOGIC;
signal PC_data_6_CLKINV_3508 : STD_LOGIC;
signal PC_data_6_CEINV_3507 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_1_CYINIT_3576 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_1_CYSELF_3570 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_1_BXINV_3568 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_1_CYMUXG_3567 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_1_LOGIC_ZERO_3565 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_1_CYSELG_3559 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_CYSELF_3600 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_CYMUXFAST_3599 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_CYAND_3598 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_FASTCARRY_3597 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_CYMUXG2_3596 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_CYMUXF2_3595 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_LOGIC_ZERO_3594 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_3_CYSELG_3588 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_CYSELF_3630 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_CYMUXFAST_3629 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_CYAND_3628 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_FASTCARRY_3627 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_CYMUXG2_3626 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_CYMUXF2_3625 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_LOGIC_ZERO_3624 : STD_LOGIC;
signal CU_current_state_cmp_eq0000_wg_cy_5_CYSELG_3618 : STD_LOGIC;
signal CU_state_timer_not0001_inv_CYSELF_3660 : STD_LOGIC;
signal CU_state_timer_not0001_inv_CYMUXFAST_3659 : STD_LOGIC;
signal CU_state_timer_not0001_inv_CYAND_3658 : STD_LOGIC;
signal CU_state_timer_not0001_inv_FASTCARRY_3657 : STD_LOGIC;
signal CU_state_timer_not0001_inv_CYMUXG2_3656 : STD_LOGIC;
signal CU_state_timer_not0001_inv_CYMUXF2_3655 : STD_LOGIC;
signal CU_state_timer_not0001_inv_LOGIC_ZERO_3654 : STD_LOGIC;
signal CU_state_timer_not0001_inv_CYSELG_3648 : STD_LOGIC;
signal AC_reg_0_F5MUX_3712 : STD_LOGIC;
signal alu_Mmux_result_4_3710 : STD_LOGIC;
signal AC_reg_0_BXINV_3703 : STD_LOGIC;
signal AC_reg_0_DYMUX_3695 : STD_LOGIC;
signal AC_reg_0_GYMUX_3694 : STD_LOGIC;
signal AC_reg_0_F6MUX_3693 : STD_LOGIC;
signal alu_Mmux_result_5_3691 : STD_LOGIC;
signal AC_reg_0_BYINV_3685 : STD_LOGIC;
signal AC_reg_0_CLKINV_3683 : STD_LOGIC;
signal AC_reg_0_CEINV_3682 : STD_LOGIC;
signal alu_Mmux_result_4_f5_F5MUX_3736 : STD_LOGIC;
signal alu_Mmux_result_51_3734 : STD_LOGIC;
signal alu_Mmux_result_4_f5_BXINV_3728 : STD_LOGIC;
signal alu_Mmux_result_6_3726 : STD_LOGIC;
signal AC_reg_1_F5MUX_3782 : STD_LOGIC;
signal alu_Mmux_result_41_3780 : STD_LOGIC;
signal AC_reg_1_BXINV_3774 : STD_LOGIC;
signal AC_reg_1_DYMUX_3766 : STD_LOGIC;
signal AC_reg_1_GYMUX_3765 : STD_LOGIC;
signal AC_reg_1_F6MUX_3764 : STD_LOGIC;
signal alu_Mmux_result_52_3762 : STD_LOGIC;
signal AC_reg_1_BYINV_3756 : STD_LOGIC;
signal AC_reg_1_CLKINV_3754 : STD_LOGIC;
signal AC_reg_1_CEINV_3753 : STD_LOGIC;
signal alu_Mmux_result_4_f51_F5MUX_3806 : STD_LOGIC;
signal alu_Mmux_result_53_3804 : STD_LOGIC;
signal alu_Mmux_result_4_f51_BXINV_3798 : STD_LOGIC;
signal alu_Mmux_result_61_3796 : STD_LOGIC;
signal AC_reg_2_F5MUX_3852 : STD_LOGIC;
signal alu_Mmux_result_42_3850 : STD_LOGIC;
signal AC_reg_2_BXINV_3844 : STD_LOGIC;
signal AC_reg_2_DYMUX_3836 : STD_LOGIC;
signal AC_reg_2_GYMUX_3835 : STD_LOGIC;
signal AC_reg_2_F6MUX_3834 : STD_LOGIC;
signal alu_Mmux_result_54_3832 : STD_LOGIC;
signal AC_reg_2_BYINV_3826 : STD_LOGIC;
signal AC_reg_2_CLKINV_3824 : STD_LOGIC;
signal AC_reg_2_CEINV_3823 : STD_LOGIC;
signal alu_Mmux_result_4_f52_F5MUX_3876 : STD_LOGIC;
signal alu_Mmux_result_55_3874 : STD_LOGIC;
signal alu_Mmux_result_4_f52_BXINV_3868 : STD_LOGIC;
signal alu_Mmux_result_62_3866 : STD_LOGIC;
signal AC_reg_3_F5MUX_3922 : STD_LOGIC;
signal alu_Mmux_result_43_3920 : STD_LOGIC;
signal AC_reg_3_BXINV_3914 : STD_LOGIC;
signal AC_reg_3_DYMUX_3906 : STD_LOGIC;
signal AC_reg_3_GYMUX_3905 : STD_LOGIC;
signal AC_reg_3_F6MUX_3904 : STD_LOGIC;
signal alu_Mmux_result_56_3902 : STD_LOGIC;
signal AC_reg_3_BYINV_3896 : STD_LOGIC;
signal AC_reg_3_CLKINV_3894 : STD_LOGIC;
signal AC_reg_3_CEINV_3893 : STD_LOGIC;
signal alu_Mmux_result_4_f53_F5MUX_3946 : STD_LOGIC;
signal alu_Mmux_result_57_3944 : STD_LOGIC;
signal alu_Mmux_result_4_f53_BXINV_3938 : STD_LOGIC;
signal alu_Mmux_result_63_3936 : STD_LOGIC;
signal AC_reg_4_F5MUX_3992 : STD_LOGIC;
signal alu_Mmux_result_44_3990 : STD_LOGIC;
signal AC_reg_4_BXINV_3984 : STD_LOGIC;
signal AC_reg_4_DYMUX_3976 : STD_LOGIC;
signal AC_reg_4_GYMUX_3975 : STD_LOGIC;
signal AC_reg_4_F6MUX_3974 : STD_LOGIC;
signal alu_Mmux_result_58_3972 : STD_LOGIC;
signal AC_reg_4_BYINV_3966 : STD_LOGIC;
signal AC_reg_4_CLKINV_3964 : STD_LOGIC;
signal AC_reg_4_CEINV_3963 : STD_LOGIC;
signal alu_Mmux_result_4_f54_F5MUX_4016 : STD_LOGIC;
signal alu_Mmux_result_59_4014 : STD_LOGIC;
signal alu_Mmux_result_4_f54_BXINV_4008 : STD_LOGIC;
signal alu_Mmux_result_64_4006 : STD_LOGIC;
signal AC_reg_5_F5MUX_4062 : STD_LOGIC;
signal alu_Mmux_result_45_4060 : STD_LOGIC;
signal AC_reg_5_BXINV_4054 : STD_LOGIC;
signal AC_reg_5_DYMUX_4046 : STD_LOGIC;
signal AC_reg_5_GYMUX_4045 : STD_LOGIC;
signal AC_reg_5_F6MUX_4044 : STD_LOGIC;
signal alu_Mmux_result_510_4042 : STD_LOGIC;
signal AC_reg_5_BYINV_4036 : STD_LOGIC;
signal AC_reg_5_CLKINV_4034 : STD_LOGIC;
signal AC_reg_5_CEINV_4033 : STD_LOGIC;
signal alu_Mmux_result_4_f55_F5MUX_4086 : STD_LOGIC;
signal alu_Mmux_result_511_4084 : STD_LOGIC;
signal alu_Mmux_result_4_f55_BXINV_4078 : STD_LOGIC;
signal alu_Mmux_result_65_4076 : STD_LOGIC;
signal AC_reg_6_F5MUX_4132 : STD_LOGIC;
signal alu_Mmux_result_46_4130 : STD_LOGIC;
signal AC_reg_6_BXINV_4124 : STD_LOGIC;
signal AC_reg_6_DYMUX_4116 : STD_LOGIC;
signal AC_reg_6_GYMUX_4115 : STD_LOGIC;
signal AC_reg_6_F6MUX_4114 : STD_LOGIC;
signal alu_Mmux_result_512_4112 : STD_LOGIC;
signal AC_reg_6_BYINV_4106 : STD_LOGIC;
signal AC_reg_6_CLKINV_4104 : STD_LOGIC;
signal AC_reg_6_CEINV_4103 : STD_LOGIC;
signal alu_Mmux_result_4_f56_F5MUX_4156 : STD_LOGIC;
signal alu_Mmux_result_513_4154 : STD_LOGIC;
signal alu_Mmux_result_4_f56_BXINV_4148 : STD_LOGIC;
signal alu_Mmux_result_66_4146 : STD_LOGIC;
signal NZ_data_N_F5MUX_4202 : STD_LOGIC;
signal alu_Mmux_result_47_4200 : STD_LOGIC;
signal NZ_data_N_BXINV_4194 : STD_LOGIC;
signal NZ_data_N_DYMUX_4186 : STD_LOGIC;
signal NZ_data_N_GYMUX_4185 : STD_LOGIC;
signal NZ_data_N_F6MUX_4184 : STD_LOGIC;
signal alu_Mmux_result_514_4182 : STD_LOGIC;
signal NZ_data_N_BYINV_4175 : STD_LOGIC;
signal NZ_data_N_CLKINV_4173 : STD_LOGIC;
signal NZ_data_N_CEINV_4172 : STD_LOGIC;
signal NZ_data_N_FFY_RSTAND_4192 : STD_LOGIC;
signal alu_Mmux_result_4_f57_F5MUX_4226 : STD_LOGIC;
signal alu_Mmux_result_515_4224 : STD_LOGIC;
signal alu_Mmux_result_4_f57_BXINV_4218 : STD_LOGIC;
signal alu_Mmux_result_67_4216 : STD_LOGIC;
signal clk_INBUF : STD_LOGIC;
signal enable_INBUF : STD_LOGIC;
signal debug_out_O : STD_LOGIC;
signal rst_INBUF : STD_LOGIC;
signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal clk_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT0 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT1 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT2 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT3 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT4 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT5 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT6 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT7 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT8 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT9 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT10 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT11 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT12 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT13 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT14 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT15 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT16 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCOUT17 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P8 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P9 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P10 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P11 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P12 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P13 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P14 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P15 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P16 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P17 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P18 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P19 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P20 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P21 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P22 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P23 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P24 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P25 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P26 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P27 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P28 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P29 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P30 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P31 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P32 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P33 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P34 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_P35 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN0 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN1 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN2 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN3 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN4 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN5 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN6 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN7 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN8 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN9 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN10 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN11 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN12 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN13 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN14 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN15 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN16 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_BCIN17 : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_RSTP_INT : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_RSTB_INT : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_RSTA_INT : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_CLK_INT : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_CEP_INT : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_CEB_INT : STD_LOGIC;
signal alu_Mmult_MULTIPLICATION_mult0000_CEA_INT : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB3 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB2 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB1 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB0 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB31 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB30 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB29 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB28 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB27 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB26 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB25 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB24 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB23 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB22 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB21 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB20 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB19 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB18 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB17 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB16 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB15 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB14 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB13 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB12 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB11 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB10 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB9 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB8 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB7 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB6 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB5 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB4 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB3 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB2 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB1 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB0 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA3 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA2 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA1 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA0 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA31 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA30 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA29 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA28 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA27 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA26 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA23 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA22 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA21 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA20 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA19 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA18 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA15 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA14 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA13 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA12 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA11 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA10 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA7 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA6 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA5 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA4 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA3 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA2 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB3 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB2 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB1 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB0 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB31 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB30 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB29 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB28 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB27 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB26 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB25 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB24 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB23 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB22 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB21 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB20 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB19 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB18 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB17 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB16 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB15 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB14 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB13 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB12 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB11 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB10 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB9 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB8 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB7 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB6 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB5 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB4 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB3 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB2 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB1 : STD_LOGIC;
signal MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB0 : STD_LOGIC;
signal CU_PC_inc_DXMUX_4579 : STD_LOGIC;
signal CU_PC_inc_F5MUX_4577 : STD_LOGIC;
signal CU_PC_inc_mux00001_4575 : STD_LOGIC;
signal CU_PC_inc_BXINV_4570 : STD_LOGIC;
signal CU_PC_inc_mux00002_4568 : STD_LOGIC;
signal CU_PC_inc_CLKINV_4562 : STD_LOGIC;
signal CU_PC_inc_CEINVNOT : STD_LOGIC;
signal CU_loadREM_DXMUX_4613 : STD_LOGIC;
signal CU_loadREM_F5MUX_4611 : STD_LOGIC;
signal CU_loadREM_mux00001_4609 : STD_LOGIC;
signal CU_loadREM_BXINV_4604 : STD_LOGIC;
signal CU_loadREM_mux00002_4602 : STD_LOGIC;
signal CU_loadREM_CLKINV_4595 : STD_LOGIC;
signal CU_next_state_mux0012_13_38_F5MUX_4643 : STD_LOGIC;
signal CU_next_state_mux0012_13_381_4641 : STD_LOGIC;
signal CU_next_state_mux0012_13_38_BXINV_4634 : STD_LOGIC;
signal CU_next_state_mux0012_13_382_4632 : STD_LOGIC;
signal CU_sel_ula_and0000 : STD_LOGIC;
signal CU_N7_pack_1 : STD_LOGIC;
signal CU_next_state_mux0012_0_8_4690 : STD_LOGIC;
signal exec_NOT_pack_1 : STD_LOGIC;
signal CU_N9 : STD_LOGIC;
signal exec_STA_pack_1 : STD_LOGIC;
signal CU_next_state_mux0012_4_11_4738 : STD_LOGIC;
signal exec_JN_pack_1 : STD_LOGIC;
signal NZ_data_Z_DXMUX_4771 : STD_LOGIC;
signal ULA_Z : STD_LOGIC;
signal alu_Z_cmp_eq000028_SW0_O_pack_1 : STD_LOGIC;
signal NZ_data_Z_CLKINV_4755 : STD_LOGIC;
signal NZ_data_Z_CEINV_4754 : STD_LOGIC;
signal N14 : STD_LOGIC;
signal CU_next_state_or0001_pack_1 : STD_LOGIC;
signal CU_next_state_1_DXMUX_4831 : STD_LOGIC;
signal CU_next_state_mux0012_12_22_O_pack_2 : STD_LOGIC;
signal CU_next_state_1_CLKINV_4814 : STD_LOGIC;
signal CU_next_state_mux0012_7_11_4859 : STD_LOGIC;
signal exec_JZ_pack_1 : STD_LOGIC;
signal CU_loadRDM_mux000015_4883 : STD_LOGIC;
signal CU_N10_pack_1 : STD_LOGIC;
signal CU_next_state_mux0012_4_23 : STD_LOGIC;
signal exec_HLT_pack_1 : STD_LOGIC;
signal CU_next_state_0_DXMUX_4938 : STD_LOGIC;
signal CU_next_state_mux0012_13_56_O_pack_2 : STD_LOGIC;
signal CU_next_state_0_CLKINV_4922 : STD_LOGIC;
signal CU_sel_mux_RDM_DXMUX_4977 : STD_LOGIC;
signal CU_sel_mux_RDM_mux0000 : STD_LOGIC;
signal CU_sel_mux_RDM_DYMUX_4965 : STD_LOGIC;
signal CU_sel_mux0000 : STD_LOGIC;
signal CU_sel_mux_RDM_CLKINV_4957 : STD_LOGIC;
signal CU_sel_mux_RDM_CEINVNOT : STD_LOGIC;
signal R_E_M_reg_1_DXMUX_5020 : STD_LOGIC;
signal R_E_M_reg_1_DYMUX_5004 : STD_LOGIC;
signal R_E_M_reg_1_SRINV_4995 : STD_LOGIC;
signal R_E_M_reg_1_CLKINV_4994 : STD_LOGIC;
signal R_E_M_reg_1_CEINV_4993 : STD_LOGIC;
signal R_E_M_reg_3_DXMUX_5066 : STD_LOGIC;
signal R_E_M_reg_3_DYMUX_5050 : STD_LOGIC;
signal R_E_M_reg_3_SRINV_5041 : STD_LOGIC;
signal R_E_M_reg_3_CLKINV_5040 : STD_LOGIC;
signal R_E_M_reg_3_CEINV_5039 : STD_LOGIC;
signal R_E_M_reg_5_DXMUX_5112 : STD_LOGIC;
signal R_E_M_reg_5_DYMUX_5096 : STD_LOGIC;
signal R_E_M_reg_5_SRINV_5087 : STD_LOGIC;
signal R_E_M_reg_5_CLKINV_5086 : STD_LOGIC;
signal R_E_M_reg_5_CEINV_5085 : STD_LOGIC;
signal R_E_M_reg_7_DXMUX_5158 : STD_LOGIC;
signal R_E_M_reg_7_DYMUX_5142 : STD_LOGIC;
signal R_E_M_reg_7_SRINV_5133 : STD_LOGIC;
signal R_E_M_reg_7_CLKINV_5132 : STD_LOGIC;
signal R_E_M_reg_7_CEINV_5131 : STD_LOGIC;
signal CU_state_timer_1_DXMUX_5200 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_1 : STD_LOGIC;
signal CU_state_timer_1_DYMUX_5185 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_0 : STD_LOGIC;
signal CU_state_timer_1_SRINV_5175 : STD_LOGIC;
signal CU_state_timer_1_CLKINV_5174 : STD_LOGIC;
signal CU_state_timer_3_DXMUX_5242 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_3 : STD_LOGIC;
signal CU_state_timer_3_DYMUX_5226 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_2 : STD_LOGIC;
signal CU_state_timer_3_SRINV_5216 : STD_LOGIC;
signal CU_state_timer_3_CLKINV_5215 : STD_LOGIC;
signal CU_state_timer_11_DXMUX_5284 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_11 : STD_LOGIC;
signal CU_state_timer_11_DYMUX_5268 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_10 : STD_LOGIC;
signal CU_state_timer_11_SRINV_5258 : STD_LOGIC;
signal CU_state_timer_11_CLKINV_5257 : STD_LOGIC;
signal CU_state_timer_5_DXMUX_5326 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_5 : STD_LOGIC;
signal CU_state_timer_5_DYMUX_5310 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_4 : STD_LOGIC;
signal CU_state_timer_5_SRINV_5300 : STD_LOGIC;
signal CU_state_timer_5_CLKINV_5299 : STD_LOGIC;
signal CU_state_timer_13_DXMUX_5368 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_13 : STD_LOGIC;
signal CU_state_timer_13_DYMUX_5352 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_12 : STD_LOGIC;
signal CU_state_timer_13_SRINV_5342 : STD_LOGIC;
signal CU_state_timer_13_CLKINV_5341 : STD_LOGIC;
signal CU_state_timer_21_DXMUX_5410 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_21 : STD_LOGIC;
signal CU_state_timer_21_DYMUX_5394 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_20 : STD_LOGIC;
signal CU_state_timer_21_SRINV_5384 : STD_LOGIC;
signal CU_state_timer_21_CLKINV_5383 : STD_LOGIC;
signal CU_state_timer_7_DXMUX_5452 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_7 : STD_LOGIC;
signal CU_state_timer_7_DYMUX_5436 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_6 : STD_LOGIC;
signal CU_state_timer_7_SRINV_5426 : STD_LOGIC;
signal CU_state_timer_7_CLKINV_5425 : STD_LOGIC;
signal CU_state_timer_15_DXMUX_5494 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_15 : STD_LOGIC;
signal CU_state_timer_15_DYMUX_5478 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_14 : STD_LOGIC;
signal CU_state_timer_15_SRINV_5468 : STD_LOGIC;
signal CU_state_timer_15_CLKINV_5467 : STD_LOGIC;
signal CU_state_timer_23_DXMUX_5536 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_23 : STD_LOGIC;
signal CU_state_timer_23_DYMUX_5520 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_22 : STD_LOGIC;
signal CU_state_timer_23_SRINV_5510 : STD_LOGIC;
signal CU_state_timer_23_CLKINV_5509 : STD_LOGIC;
signal CU_state_timer_31_DXMUX_5578 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_31 : STD_LOGIC;
signal CU_state_timer_31_DYMUX_5562 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_30 : STD_LOGIC;
signal CU_state_timer_31_SRINV_5552 : STD_LOGIC;
signal CU_state_timer_31_CLKINV_5551 : STD_LOGIC;
signal CU_state_timer_9_DXMUX_5620 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_9 : STD_LOGIC;
signal CU_state_timer_9_DYMUX_5604 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_8 : STD_LOGIC;
signal CU_state_timer_9_SRINV_5594 : STD_LOGIC;
signal CU_state_timer_9_CLKINV_5593 : STD_LOGIC;
signal CU_state_timer_17_DXMUX_5662 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_17 : STD_LOGIC;
signal CU_state_timer_17_DYMUX_5646 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_16 : STD_LOGIC;
signal CU_state_timer_17_SRINV_5636 : STD_LOGIC;
signal CU_state_timer_17_CLKINV_5635 : STD_LOGIC;
signal CU_state_timer_25_FFX_RST : STD_LOGIC;
signal CU_state_timer_25_FFY_RST : STD_LOGIC;
signal CU_state_timer_25_DXMUX_5704 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_25 : STD_LOGIC;
signal CU_state_timer_25_DYMUX_5688 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_24 : STD_LOGIC;
signal CU_state_timer_25_SRINV_5678 : STD_LOGIC;
signal CU_state_timer_25_CLKINV_5677 : STD_LOGIC;
signal CU_state_timer_19_FFY_RST : STD_LOGIC;
signal CU_state_timer_19_FFX_RST : STD_LOGIC;
signal CU_state_timer_19_DXMUX_5746 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_19 : STD_LOGIC;
signal CU_state_timer_19_DYMUX_5730 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_18 : STD_LOGIC;
signal CU_state_timer_19_SRINV_5720 : STD_LOGIC;
signal CU_state_timer_19_CLKINV_5719 : STD_LOGIC;
signal CU_state_timer_27_DXMUX_5788 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_27 : STD_LOGIC;
signal CU_state_timer_27_DYMUX_5772 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_26 : STD_LOGIC;
signal CU_state_timer_27_SRINV_5762 : STD_LOGIC;
signal CU_state_timer_27_CLKINV_5761 : STD_LOGIC;
signal CU_state_timer_29_FFY_RST : STD_LOGIC;
signal CU_state_timer_29_FFX_RST : STD_LOGIC;
signal CU_state_timer_29_DXMUX_5830 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_29 : STD_LOGIC;
signal CU_state_timer_29_DYMUX_5814 : STD_LOGIC;
signal CU_Mcount_state_timer_eqn_28 : STD_LOGIC;
signal CU_state_timer_29_SRINV_5804 : STD_LOGIC;
signal CU_state_timer_29_CLKINV_5803 : STD_LOGIC;
signal CU_next_state_3_DXMUX_5872 : STD_LOGIC;
signal CU_next_state_3_DYMUX_5857 : STD_LOGIC;
signal CU_next_state_3_SRINV_5848 : STD_LOGIC;
signal CU_next_state_3_CLKINV_5847 : STD_LOGIC;
signal CU_next_state_5_DXMUX_5914 : STD_LOGIC;
signal CU_next_state_5_DYMUX_5900 : STD_LOGIC;
signal CU_next_state_5_SRINV_5891 : STD_LOGIC;
signal CU_next_state_5_CLKINV_5890 : STD_LOGIC;
signal CU_loadAC_DYMUX_5937 : STD_LOGIC;
signal CU_loadAC_mux0000 : STD_LOGIC;
signal CU_loadAC_CLKINV_5927 : STD_LOGIC;
signal CU_next_state_6_DYMUX_5960 : STD_LOGIC;
signal CU_next_state_6_CLKINV_5951 : STD_LOGIC;
signal CU_next_state_9_DXMUX_6002 : STD_LOGIC;
signal CU_next_state_9_DYMUX_5988 : STD_LOGIC;
signal CU_next_state_9_SRINV_5979 : STD_LOGIC;
signal CU_next_state_9_CLKINV_5978 : STD_LOGIC;
signal AC_reg_2_FFY_RSTAND_3842 : STD_LOGIC;
signal AC_reg_6_FFY_RSTAND_4122 : STD_LOGIC;
signal CU_loadRDM_FFY_RSTAND_1850 : STD_LOGIC;
signal CU_stop_s_FFY_RSTAND_2239 : STD_LOGIC;
signal CU_loadRI_FFX_RSTAND_2274 : STD_LOGIC;
signal CU_loadPC_FFX_RSTAND_2453 : STD_LOGIC;
signal CU_wr_enable_mem_0_FFX_RSTAND_2488 : STD_LOGIC;
signal AC_reg_0_FFY_RSTAND_3701 : STD_LOGIC;
signal AC_reg_1_FFY_RSTAND_3772 : STD_LOGIC;
signal AC_reg_3_FFY_RSTAND_3912 : STD_LOGIC;
signal AC_reg_4_FFY_RSTAND_3982 : STD_LOGIC;
signal AC_reg_5_FFY_RSTAND_4052 : STD_LOGIC;
signal CU_loadREM_FFX_RSTAND_4618 : STD_LOGIC;
signal NZ_data_Z_FFX_RSTAND_4777 : STD_LOGIC;
signal CU_next_state_1_FFX_RSTAND_4836 : STD_LOGIC;
signal CU_next_state_0_FFX_SET : STD_LOGIC;
signal CU_loadAC_FFY_RSTAND_5942 : STD_LOGIC;
signal CU_next_state_6_FFY_RSTAND_5965 : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_7_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_6_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_5_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_4_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_3_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_2_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_1_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_0_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_0_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_1_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_8_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_9_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_16_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_17_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_24_Q : STD_LOGIC;
signal NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_25_Q : STD_LOGIC;
signal VCC : STD_LOGIC;
signal GND : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_1_CLK : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_2_CLK : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_0_CLK : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_3_CLK : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_4_CLK : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_5_CLK : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_6_CLK : STD_LOGIC;
signal NlwInverterSignal_alu_MULTIPLICATION_7_CLK : STD_LOGIC;
signal CU_current_state : STD_LOGIC_VECTOR ( 13 downto 0 );
signal CU_next_state : STD_LOGIC_VECTOR ( 13 downto 0 );
signal MEM_output : STD_LOGIC_VECTOR ( 7 downto 0 );
signal AC_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
signal R_D_M_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal RI_reg : STD_LOGIC_VECTOR ( 7 downto 4 );
signal CU_sel_ula : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ULA_output : STD_LOGIC_VECTOR ( 6 downto 0 );
signal CU_wr_enable_mem : STD_LOGIC_VECTOR ( 0 downto 0 );
signal alu_MULTIPLICATION_mult0000 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal alu_MULTIPLICATION : STD_LOGIC_VECTOR ( 7 downto 0 );
signal alu_result_addsub0000 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CU_state_timer : STD_LOGIC_VECTOR ( 31 downto 0 );
signal CU_Result : STD_LOGIC_VECTOR ( 31 downto 0 );
signal PC_data : STD_LOGIC_VECTOR ( 7 downto 0 );
signal R_E_M_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CU_next_state_mux0012 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal muxrdm_output : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CU_sel_ula_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal alu_Madd_result_addsub0000_lut : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CU_Mcount_state_timer_lut : STD_LOGIC_VECTOR ( 31 downto 1 );
signal PC_Mcount_data_lut : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CU_current_state_cmp_eq0000_wg_lut : STD_LOGIC_VECTOR ( 7 downto 0 );
signal CU_current_state_cmp_eq0000_wg_cy : STD_LOGIC_VECTOR ( 0 downto 0 );
signal MPX_output : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B : STD_LOGIC_VECTOR ( 17 downto 0 );
begin
CU_next_state_11_DXMUX : X_BUF
generic map(
LOC => "SLICE_X25Y8",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(2),
O => CU_next_state_11_DXMUX_1734
);
CU_next_state_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y8",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(3),
O => CU_next_state_11_DYMUX_1720
);
CU_next_state_11_SRINV : X_BUF
generic map(
LOC => "SLICE_X25Y8",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_11_SRINV_1711
);
CU_next_state_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y8",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_11_CLKINV_1710
);
CU_next_state_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(0),
O => CU_next_state_13_DXMUX_1776
);
CU_next_state_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(1),
O => CU_next_state_13_DYMUX_1762
);
CU_next_state_13_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_13_SRINV_1754
);
CU_next_state_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_13_CLKINV_1753
);
R_D_M_reg_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X24Y29",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(1),
O => R_D_M_reg_1_DXMUX_1821
);
R_D_M_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X24Y29",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(0),
O => R_D_M_reg_1_DYMUX_1805
);
R_D_M_reg_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X24Y29",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_D_M_reg_1_SRINV_1796
);
R_D_M_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X24Y29",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_D_M_reg_1_CLKINV_1795
);
R_D_M_reg_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X24Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRDM_1452,
O => R_D_M_reg_1_CEINV_1794
);
mux_rdm_S_0_1 : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X24Y29"
)
port map (
ADR0 => MEM_output(0),
ADR1 => VCC,
ADR2 => AC_reg(0),
ADR3 => CU_sel_mux_RDM_1453,
O => muxrdm_output(0)
);
CU_loadRDM_DYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRDM_mux0000,
O => CU_loadRDM_DYMUX_1845
);
CU_loadRDM_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_loadRDM_CLKINV_1834
);
mux_rdm_S_3_1 : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X24Y32"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(3),
ADR2 => MEM_output(3),
ADR3 => CU_sel_mux_RDM_1453,
O => muxrdm_output(3)
);
R_D_M_reg_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X24Y32",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(3),
O => R_D_M_reg_3_DXMUX_1890
);
R_D_M_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X24Y32",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(2),
O => R_D_M_reg_3_DYMUX_1874
);
R_D_M_reg_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X24Y32",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_D_M_reg_3_SRINV_1865
);
R_D_M_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X24Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_D_M_reg_3_CLKINV_1864
);
R_D_M_reg_3_CEINV : X_BUF
generic map(
LOC => "SLICE_X24Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRDM_1452,
O => R_D_M_reg_3_CEINV_1863
);
CU_sel_ula_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X23Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula_mux0000(1),
O => CU_sel_ula_1_DXMUX_1931
);
CU_sel_ula_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula_mux0000(2),
O => CU_sel_ula_1_DYMUX_1919
);
CU_sel_ula_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_sel_ula_1_CLKINV_1911
);
CU_sel_ula_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X23Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula_and0000_0,
O => CU_sel_ula_1_CEINV_1910
);
mux_rdm_S_5_1 : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X22Y32"
)
port map (
ADR0 => AC_reg(5),
ADR1 => VCC,
ADR2 => MEM_output(5),
ADR3 => CU_sel_mux_RDM_1453,
O => muxrdm_output(5)
);
R_D_M_reg_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X22Y32",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(5),
O => R_D_M_reg_5_DXMUX_1974
);
R_D_M_reg_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X22Y32",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(4),
O => R_D_M_reg_5_DYMUX_1958
);
R_D_M_reg_5_SRINV : X_BUF
generic map(
LOC => "SLICE_X22Y32",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_D_M_reg_5_SRINV_1949
);
R_D_M_reg_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X22Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_D_M_reg_5_CLKINV_1948
);
R_D_M_reg_5_CEINV : X_BUF
generic map(
LOC => "SLICE_X22Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRDM_1452,
O => R_D_M_reg_5_CEINV_1947
);
R_D_M_reg_4 : X_FF
generic map(
LOC => "SLICE_X22Y32",
INIT => '0'
)
port map (
I => R_D_M_reg_5_DYMUX_1958,
CE => R_D_M_reg_5_CEINV_1947,
CLK => R_D_M_reg_5_CLKINV_1948,
SET => GND,
RST => R_D_M_reg_5_SRINV_1949,
O => R_D_M_reg(4)
);
CU_sel_ula_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => exec_NOP,
O => exec_NOP_0
);
CU_sel_ula_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula_mux0000(0),
O => CU_sel_ula_2_DYMUX_2003
);
CU_sel_ula_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_sel_ula_2_CLKINV_1995
);
CU_sel_ula_2_CEINV : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula_and0000_0,
O => CU_sel_ula_2_CEINV_1994
);
mux_rdm_S_7_1 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X22Y28"
)
port map (
ADR0 => MEM_output(7),
ADR1 => NZ_data_N_1484,
ADR2 => VCC,
ADR3 => CU_sel_mux_RDM_1453,
O => muxrdm_output(7)
);
R_D_M_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(7),
O => R_D_M_reg_7_DXMUX_2053
);
R_D_M_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => muxrdm_output(6),
O => R_D_M_reg_7_DYMUX_2037
);
R_D_M_reg_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_D_M_reg_7_SRINV_2028
);
R_D_M_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_D_M_reg_7_CLKINV_2027
);
R_D_M_reg_7_CEINV : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRDM_1452,
O => R_D_M_reg_7_CEINV_2026
);
R_D_M_reg_6 : X_FF
generic map(
LOC => "SLICE_X22Y28",
INIT => '0'
)
port map (
I => R_D_M_reg_7_DYMUX_2037,
CE => R_D_M_reg_7_CEINV_2026,
CLK => R_D_M_reg_7_CLKINV_2027,
SET => GND,
RST => R_D_M_reg_7_SRINV_2028,
O => R_D_M_reg(6)
);
CU_current_state_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y8",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(3),
O => CU_current_state_3_DXMUX_2076
);
CU_current_state_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y8",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(2),
O => CU_current_state_3_DYMUX_2070
);
CU_current_state_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y8",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_current_state_3_CLKINV_2068
);
CU_current_state_3_CEINV : X_BUF
generic map(
LOC => "SLICE_X18Y8",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv_0,
O => CU_current_state_3_CEINV_2067
);
CU_next_state_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X21Y9",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(6),
O => CU_next_state_7_DXMUX_2109
);
CU_next_state_7_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y9",
PATHPULSE => 638 ps
)
port map (
I => N32_pack_2,
O => N32
);
CU_next_state_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X21Y9",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_7_CLKINV_2093
);
CU_next_state_7 : X_FF
generic map(
LOC => "SLICE_X21Y9",
INIT => '0'
)
port map (
I => CU_next_state_7_DXMUX_2109,
CE => VCC,
CLK => CU_next_state_7_CLKINV_2093,
SET => GND,
RST => CU_next_state_7_FFX_RSTAND_2114,
O => CU_next_state(7)
);
CU_next_state_7_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X21Y9",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_7_FFX_RSTAND_2114
);
CU_current_state_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(5),
O => CU_current_state_5_DXMUX_2131
);
CU_current_state_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(4),
O => CU_current_state_5_DYMUX_2125
);
CU_current_state_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_current_state_5_CLKINV_2123
);
CU_current_state_5_CEINV : X_BUF
generic map(
LOC => "SLICE_X17Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv_0,
O => CU_current_state_5_CEINV_2122
);
CU_current_state_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(7),
O => CU_current_state_7_DXMUX_2151
);
CU_current_state_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(6),
O => CU_current_state_7_DYMUX_2145
);
CU_current_state_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_current_state_7_CLKINV_2143
);
CU_current_state_7_CEINV : X_BUF
generic map(
LOC => "SLICE_X17Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv_0,
O => CU_current_state_7_CEINV_2142
);
CU_current_state_9 : X_FF
generic map(
LOC => "SLICE_X21Y10",
INIT => '0'
)
port map (
I => CU_current_state_9_DXMUX_2171,
CE => CU_current_state_9_CEINV_2162,
CLK => CU_current_state_9_CLKINV_2163,
SET => GND,
RST => GND,
O => CU_current_state(9)
);
CU_current_state_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(9),
O => CU_current_state_9_DXMUX_2171
);
CU_current_state_9_DYMUX : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(8),
O => CU_current_state_9_DYMUX_2165
);
CU_current_state_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_current_state_9_CLKINV_2163
);
CU_current_state_9_CEINV : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv_0,
O => CU_current_state_9_CEINV_2162
);
CU_N18_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_N18,
O => CU_N18_0
);
CU_N18_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRDM_mux00004_2190,
O => CU_loadRDM_mux00004_0
);
N30_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y17",
PATHPULSE => 638 ps
)
port map (
I => N30,
O => N30_0
);
alu_MULTIPLICATION_cmp_eq0000_YUSED : X_BUF
generic map(
LOC => "SLICE_X28Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_cmp_eq0000,
O => alu_MULTIPLICATION_cmp_eq0000_0
);
CU_stop_s_DYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y9",
PATHPULSE => 638 ps
)
port map (
I => CU_stop_s_BYINV_2232,
O => CU_stop_s_DYMUX_2233
);
CU_stop_s_BYINV : X_BUF
generic map(
LOC => "SLICE_X25Y9",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => CU_stop_s_BYINV_2232
);
CU_stop_s_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y9",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_stop_s_CLKINV_2230
);
CU_stop_s_CEINV : X_BUF
generic map(
LOC => "SLICE_X25Y9",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state(11),
O => CU_stop_s_CEINV_2229
);
CU_loadRI_DXMUX : X_BUF
generic map(
LOC => "SLICE_X23Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRI_mux0000_2266,
O => CU_loadRI_DXMUX_2269
);
CU_loadRI_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y11",
PATHPULSE => 638 ps
)
port map (
I => N10_pack_2,
O => N10
);
CU_loadRI_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_loadRI_CLKINV_2253
);
CU_current_state_11_DXMUX : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(11),
O => CU_current_state_11_DXMUX_2291
);
CU_current_state_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(10),
O => CU_current_state_11_DYMUX_2285
);
CU_current_state_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_current_state_11_CLKINV_2283
);
CU_current_state_11_CEINV : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv_0,
O => CU_current_state_11_CEINV_2282
);
CU_current_state_12 : X_FF
generic map(
LOC => "SLICE_X13Y14",
INIT => '0'
)
port map (
I => CU_current_state_13_DYMUX_2305,
CE => CU_current_state_13_CEINV_2302,
CLK => CU_current_state_13_CLKINV_2303,
SET => GND,
RST => GND,
O => CU_current_state(12)
);
CU_current_state_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X13Y14",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(13),
O => CU_current_state_13_DXMUX_2311
);
CU_current_state_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X13Y14",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(12),
O => CU_current_state_13_DYMUX_2305
);
CU_current_state_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X13Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_current_state_13_CLKINV_2303
);
CU_current_state_13_CEINV : X_BUF
generic map(
LOC => "SLICE_X13Y14",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv_0,
O => CU_current_state_13_CEINV_2302
);
alu_Z_cmp_eq00007 : X_LUT4
generic map(
INIT => X"000F",
LOC => "SLICE_X24Y30"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => ULA_output(0),
ADR3 => ULA_output(1),
O => alu_Z_cmp_eq00007_2325
);
alu_Z_cmp_eq00007_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_Z_cmp_eq00007_2325,
O => alu_Z_cmp_eq00007_0
);
CU_next_state_mux0012_12_13_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_12_13_2349,
O => CU_next_state_mux0012_12_13_0
);
CU_next_state_mux0012_12_13_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y11",
PATHPULSE => 638 ps
)
port map (
I => N24_pack_1,
O => N24
);
RI_reg_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X23Y15",
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(5),
O => RI_reg_5_DXMUX_2372
);
RI_reg_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y15",
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(4),
O => RI_reg_5_DYMUX_2363
);
RI_reg_5_SRINV : X_BUF
generic map(
LOC => "SLICE_X23Y15",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => RI_reg_5_SRINV_2361
);
RI_reg_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => RI_reg_5_CLKINV_2360
);
RI_reg_5_CEINV : X_BUF
generic map(
LOC => "SLICE_X23Y15",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRI_1515,
O => RI_reg_5_CEINV_2359
);
RI_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X22Y17",
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => RI_reg_7_DXMUX_2400
);
RI_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X22Y17",
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(6),
O => RI_reg_7_DYMUX_2391
);
RI_reg_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X22Y17",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => RI_reg_7_SRINV_2389
);
RI_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X22Y17",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => RI_reg_7_CLKINV_2388
);
RI_reg_7_CEINV : X_BUF
generic map(
LOC => "SLICE_X22Y17",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRI_1515,
O => RI_reg_7_CEINV_2387
);
CU_current_state_not0001_inv_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv,
O => CU_current_state_not0001_inv_0
);
CU_loadPC_mux00001 : X_LUT4
generic map(
INIT => X"F2F2",
LOC => "SLICE_X25Y14"
)
port map (
ADR0 => CU_loadPC_1524,
ADR1 => CU_current_state(1),
ADR2 => CU_current_state(8),
ADR3 => VCC,
O => CU_loadPC_mux0000
);
CU_loadPC_DXMUX : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => CU_loadPC_mux0000,
O => CU_loadPC_DXMUX_2448
);
CU_loadPC_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => PC_data_not0001,
O => PC_data_not0001_0
);
CU_loadPC_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_loadPC_CLKINV_2429
);
CU_wr_enable_mem_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X23Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_wr_enable_mem_0_mux0000,
O => CU_wr_enable_mem_0_DXMUX_2483
);
CU_wr_enable_mem_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_13_14_2472,
O => CU_next_state_mux0012_13_14_0
);
CU_wr_enable_mem_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_wr_enable_mem_0_CLKINV_2465
);
alu_MULTIPLICATION_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X26Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(1),
O => alu_MULTIPLICATION_1_DXMUX_2502
);
alu_MULTIPLICATION_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X26Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(0),
O => alu_MULTIPLICATION_1_DYMUX_2497
);
alu_MULTIPLICATION_1_CLKINV : X_INV
generic map(
LOC => "SLICE_X26Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_cmp_eq0000_0,
O => alu_MULTIPLICATION_1_CLKINVNOT
);
alu_MULTIPLICATION_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X26Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(3),
O => alu_MULTIPLICATION_3_DXMUX_2518
);
alu_MULTIPLICATION_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X26Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(2),
O => alu_MULTIPLICATION_3_DYMUX_2513
);
alu_MULTIPLICATION_3_CLKINV : X_INV
generic map(
LOC => "SLICE_X26Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_cmp_eq0000_0,
O => alu_MULTIPLICATION_3_CLKINVNOT
);
alu_MULTIPLICATION_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X22Y33",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(5),
O => alu_MULTIPLICATION_5_DXMUX_2534
);
alu_MULTIPLICATION_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X22Y33",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(4),
O => alu_MULTIPLICATION_5_DYMUX_2529
);
alu_MULTIPLICATION_5_CLKINV : X_INV
generic map(
LOC => "SLICE_X22Y33",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_cmp_eq0000_0,
O => alu_MULTIPLICATION_5_CLKINVNOT
);
alu_MULTIPLICATION_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X26Y32",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(7),
O => alu_MULTIPLICATION_7_DXMUX_2550
);
alu_MULTIPLICATION_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X26Y32",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_mult0000(6),
O => alu_MULTIPLICATION_7_DYMUX_2545
);
alu_MULTIPLICATION_7_CLKINV : X_INV
generic map(
LOC => "SLICE_X26Y32",
PATHPULSE => 638 ps
)
port map (
I => alu_MULTIPLICATION_cmp_eq0000_0,
O => alu_MULTIPLICATION_7_CLKINVNOT
);
CU_current_state_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(1),
O => CU_current_state_1_DXMUX_2569
);
CU_current_state_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state(0),
O => CU_current_state_1_DYMUX_2563
);
CU_current_state_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_current_state_1_CLKINV_2561
);
CU_current_state_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X16Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_not0001_inv_0,
O => CU_current_state_1_CEINV_2560
);
alu_result_addsub0000_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_0_XORF_2608,
O => alu_result_addsub0000(0)
);
alu_result_addsub0000_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X25Y29"
)
port map (
I0 => alu_result_addsub0000_0_CYINIT_2607,
I1 => alu_Madd_result_addsub0000_lut(0),
O => alu_result_addsub0000_0_XORF_2608
);
alu_result_addsub0000_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X25Y29"
)
port map (
IA => alu_result_addsub0000_0_CY0F_2606,
IB => alu_result_addsub0000_0_CYINIT_2607,
SEL => alu_result_addsub0000_0_CYSELF_2598,
O => alu_Madd_result_addsub0000_cy_0_Q
);
alu_result_addsub0000_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_0_BXINV_2596,
O => alu_result_addsub0000_0_CYINIT_2607
);
alu_result_addsub0000_0_CY0F : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => AC_reg(0),
O => alu_result_addsub0000_0_CY0F_2606
);
alu_result_addsub0000_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_lut(0),
O => alu_result_addsub0000_0_CYSELF_2598
);
alu_result_addsub0000_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_result_addsub0000_0_BXINV_2596
);
alu_result_addsub0000_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_0_XORG_2594,
O => alu_result_addsub0000(1)
);
alu_result_addsub0000_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X25Y29"
)
port map (
I0 => alu_Madd_result_addsub0000_cy_0_Q,
I1 => alu_Madd_result_addsub0000_lut(1),
O => alu_result_addsub0000_0_XORG_2594
);
alu_result_addsub0000_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_0_CYMUXG_2593,
O => alu_Madd_result_addsub0000_cy_1_Q
);
alu_result_addsub0000_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X25Y29"
)
port map (
IA => alu_result_addsub0000_0_CY0G_2591,
IB => alu_Madd_result_addsub0000_cy_0_Q,
SEL => alu_result_addsub0000_0_CYSELG_2583,
O => alu_result_addsub0000_0_CYMUXG_2593
);
alu_result_addsub0000_0_CY0G : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => AC_reg(1),
O => alu_result_addsub0000_0_CY0G_2591
);
alu_result_addsub0000_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X25Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_lut(1),
O => alu_result_addsub0000_0_CYSELG_2583
);
alu_result_addsub0000_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_2_XORF_2647,
O => alu_result_addsub0000(2)
);
alu_result_addsub0000_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X25Y30"
)
port map (
I0 => alu_result_addsub0000_2_CYINIT_2646,
I1 => alu_Madd_result_addsub0000_lut(2),
O => alu_result_addsub0000_2_XORF_2647
);
alu_result_addsub0000_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X25Y30"
)
port map (
IA => alu_result_addsub0000_2_CY0F_2645,
IB => alu_result_addsub0000_2_CYINIT_2646,
SEL => alu_result_addsub0000_2_CYSELF_2633,
O => alu_Madd_result_addsub0000_cy_2_Q
);
alu_result_addsub0000_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X25Y30"
)
port map (
IA => alu_result_addsub0000_2_CY0F_2645,
IB => alu_result_addsub0000_2_CY0F_2645,
SEL => alu_result_addsub0000_2_CYSELF_2633,
O => alu_result_addsub0000_2_CYMUXF2_2628
);
alu_result_addsub0000_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_cy_1_Q,
O => alu_result_addsub0000_2_CYINIT_2646
);
alu_result_addsub0000_2_CY0F : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg(2),
O => alu_result_addsub0000_2_CY0F_2645
);
alu_result_addsub0000_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_lut(2),
O => alu_result_addsub0000_2_CYSELF_2633
);
alu_result_addsub0000_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_2_XORG_2635,
O => alu_result_addsub0000(3)
);
alu_result_addsub0000_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X25Y30"
)
port map (
I0 => alu_Madd_result_addsub0000_cy_2_Q,
I1 => alu_Madd_result_addsub0000_lut(3),
O => alu_result_addsub0000_2_XORG_2635
);
alu_result_addsub0000_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_2_CYMUXFAST_2632,
O => alu_Madd_result_addsub0000_cy_3_Q
);
alu_result_addsub0000_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_cy_1_Q,
O => alu_result_addsub0000_2_FASTCARRY_2630
);
alu_result_addsub0000_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X25Y30"
)
port map (
I0 => alu_result_addsub0000_2_CYSELG_2619,
I1 => alu_result_addsub0000_2_CYSELF_2633,
O => alu_result_addsub0000_2_CYAND_2631
);
alu_result_addsub0000_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X25Y30"
)
port map (
IA => alu_result_addsub0000_2_CYMUXG2_2629,
IB => alu_result_addsub0000_2_FASTCARRY_2630,
SEL => alu_result_addsub0000_2_CYAND_2631,
O => alu_result_addsub0000_2_CYMUXFAST_2632
);
alu_result_addsub0000_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X25Y30"
)
port map (
IA => alu_result_addsub0000_2_CY0G_2627,
IB => alu_result_addsub0000_2_CYMUXF2_2628,
SEL => alu_result_addsub0000_2_CYSELG_2619,
O => alu_result_addsub0000_2_CYMUXG2_2629
);
alu_result_addsub0000_2_CY0G : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg(3),
O => alu_result_addsub0000_2_CY0G_2627
);
alu_result_addsub0000_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X25Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_lut(3),
O => alu_result_addsub0000_2_CYSELG_2619
);
alu_result_addsub0000_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_4_XORF_2686,
O => alu_result_addsub0000(4)
);
alu_result_addsub0000_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X25Y31"
)
port map (
I0 => alu_result_addsub0000_4_CYINIT_2685,
I1 => alu_Madd_result_addsub0000_lut(4),
O => alu_result_addsub0000_4_XORF_2686
);
alu_result_addsub0000_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X25Y31"
)
port map (
IA => alu_result_addsub0000_4_CY0F_2684,
IB => alu_result_addsub0000_4_CYINIT_2685,
SEL => alu_result_addsub0000_4_CYSELF_2672,
O => alu_Madd_result_addsub0000_cy_4_Q
);
alu_result_addsub0000_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X25Y31"
)
port map (
IA => alu_result_addsub0000_4_CY0F_2684,
IB => alu_result_addsub0000_4_CY0F_2684,
SEL => alu_result_addsub0000_4_CYSELF_2672,
O => alu_result_addsub0000_4_CYMUXF2_2667
);
alu_result_addsub0000_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_cy_3_Q,
O => alu_result_addsub0000_4_CYINIT_2685
);
alu_result_addsub0000_4_CY0F : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => AC_reg(4),
O => alu_result_addsub0000_4_CY0F_2684
);
alu_result_addsub0000_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_lut(4),
O => alu_result_addsub0000_4_CYSELF_2672
);
alu_result_addsub0000_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_4_XORG_2674,
O => alu_result_addsub0000(5)
);
alu_result_addsub0000_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X25Y31"
)
port map (
I0 => alu_Madd_result_addsub0000_cy_4_Q,
I1 => alu_Madd_result_addsub0000_lut(5),
O => alu_result_addsub0000_4_XORG_2674
);
alu_result_addsub0000_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_cy_3_Q,
O => alu_result_addsub0000_4_FASTCARRY_2669
);
alu_result_addsub0000_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X25Y31"
)
port map (
I0 => alu_result_addsub0000_4_CYSELG_2658,
I1 => alu_result_addsub0000_4_CYSELF_2672,
O => alu_result_addsub0000_4_CYAND_2670
);
alu_result_addsub0000_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X25Y31"
)
port map (
IA => alu_result_addsub0000_4_CYMUXG2_2668,
IB => alu_result_addsub0000_4_FASTCARRY_2669,
SEL => alu_result_addsub0000_4_CYAND_2670,
O => alu_result_addsub0000_4_CYMUXFAST_2671
);
alu_result_addsub0000_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X25Y31"
)
port map (
IA => alu_result_addsub0000_4_CY0G_2666,
IB => alu_result_addsub0000_4_CYMUXF2_2667,
SEL => alu_result_addsub0000_4_CYSELG_2658,
O => alu_result_addsub0000_4_CYMUXG2_2668
);
alu_result_addsub0000_4_CY0G : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => AC_reg(5),
O => alu_result_addsub0000_4_CY0G_2666
);
alu_result_addsub0000_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X25Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_lut(5),
O => alu_result_addsub0000_4_CYSELG_2658
);
alu_result_addsub0000_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y32",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_6_XORF_2717,
O => alu_result_addsub0000(6)
);
alu_result_addsub0000_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X25Y32"
)
port map (
I0 => alu_result_addsub0000_6_CYINIT_2716,
I1 => alu_Madd_result_addsub0000_lut(6),
O => alu_result_addsub0000_6_XORF_2717
);
alu_result_addsub0000_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X25Y32"
)
port map (
IA => alu_result_addsub0000_6_CY0F_2715,
IB => alu_result_addsub0000_6_CYINIT_2716,
SEL => alu_result_addsub0000_6_CYSELF_2707,
O => alu_Madd_result_addsub0000_cy_6_Q
);
alu_result_addsub0000_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X25Y32",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_4_CYMUXFAST_2671,
O => alu_result_addsub0000_6_CYINIT_2716
);
alu_result_addsub0000_6_CY0F : X_BUF
generic map(
LOC => "SLICE_X25Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg(6),
O => alu_result_addsub0000_6_CY0F_2715
);
alu_result_addsub0000_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X25Y32",
PATHPULSE => 638 ps
)
port map (
I => alu_Madd_result_addsub0000_lut(6),
O => alu_result_addsub0000_6_CYSELF_2707
);
alu_result_addsub0000_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y32",
PATHPULSE => 638 ps
)
port map (
I => alu_result_addsub0000_6_XORG_2704,
O => alu_result_addsub0000(7)
);
alu_result_addsub0000_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X25Y32"
)
port map (
I0 => alu_Madd_result_addsub0000_cy_6_Q,
I1 => alu_Madd_result_addsub0000_lut(7),
O => alu_result_addsub0000_6_XORG_2704
);
CU_Result_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y18"
)
port map (
O => CU_Result_0_LOGIC_ONE_2735
);
CU_Result_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X1Y18"
)
port map (
O => CU_Result_0_LOGIC_ZERO_2752
);
CU_Result_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_0_XORF_2753,
O => CU_Result(0)
);
CU_Result_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y18"
)
port map (
I0 => CU_Result_0_CYINIT_2751,
I1 => CU_Result_0_F,
O => CU_Result_0_XORF_2753
);
CU_Result_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y18"
)
port map (
IA => CU_Result_0_LOGIC_ZERO_2752,
IB => CU_Result_0_CYINIT_2751,
SEL => CU_Result_0_CYSELF_2742,
O => CU_Mcount_state_timer_cy_0_Q
);
CU_Result_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_0_BXINV_2740,
O => CU_Result_0_CYINIT_2751
);
CU_Result_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_0_F,
O => CU_Result_0_CYSELF_2742
);
CU_Result_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X1Y18",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => CU_Result_0_BXINV_2740
);
CU_Result_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_0_XORG_2738,
O => CU_Result(1)
);
CU_Result_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y18"
)
port map (
I0 => CU_Mcount_state_timer_cy_0_Q,
I1 => CU_Mcount_state_timer_lut(1),
O => CU_Result_0_XORG_2738
);
CU_Result_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_0_CYMUXG_2737,
O => CU_Mcount_state_timer_cy_1_Q
);
CU_Result_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X1Y18"
)
port map (
IA => CU_Result_0_LOGIC_ONE_2735,
IB => CU_Mcount_state_timer_cy_0_Q,
SEL => CU_Result_0_CYSELG_2726,
O => CU_Result_0_CYMUXG_2737
);
CU_Result_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(1),
O => CU_Result_0_CYSELG_2726
);
CU_Result_2_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y19"
)
port map (
O => CU_Result_2_LOGIC_ONE_2771
);
CU_Result_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_2_XORF_2791,
O => CU_Result(2)
);
CU_Result_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y19"
)
port map (
I0 => CU_Result_2_CYINIT_2790,
I1 => CU_Mcount_state_timer_lut(2),
O => CU_Result_2_XORF_2791
);
CU_Result_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y19"
)
port map (
IA => CU_Result_2_LOGIC_ONE_2771,
IB => CU_Result_2_CYINIT_2790,
SEL => CU_Result_2_CYSELF_2777,
O => CU_Mcount_state_timer_cy_2_Q
);
CU_Result_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y19"
)
port map (
IA => CU_Result_2_LOGIC_ONE_2771,
IB => CU_Result_2_LOGIC_ONE_2771,
SEL => CU_Result_2_CYSELF_2777,
O => CU_Result_2_CYMUXF2_2772
);
CU_Result_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_1_Q,
O => CU_Result_2_CYINIT_2790
);
CU_Result_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(2),
O => CU_Result_2_CYSELF_2777
);
CU_Result_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_2_XORG_2779,
O => CU_Result(3)
);
CU_Result_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y19"
)
port map (
I0 => CU_Mcount_state_timer_cy_2_Q,
I1 => CU_Mcount_state_timer_lut(3),
O => CU_Result_2_XORG_2779
);
CU_Result_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_2_CYMUXFAST_2776,
O => CU_Mcount_state_timer_cy_3_Q
);
CU_Result_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_1_Q,
O => CU_Result_2_FASTCARRY_2774
);
CU_Result_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y19"
)
port map (
I0 => CU_Result_2_CYSELG_2762,
I1 => CU_Result_2_CYSELF_2777,
O => CU_Result_2_CYAND_2775
);
CU_Result_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y19"
)
port map (
IA => CU_Result_2_CYMUXG2_2773,
IB => CU_Result_2_FASTCARRY_2774,
SEL => CU_Result_2_CYAND_2775,
O => CU_Result_2_CYMUXFAST_2776
);
CU_Result_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y19"
)
port map (
IA => CU_Result_2_LOGIC_ONE_2771,
IB => CU_Result_2_CYMUXF2_2772,
SEL => CU_Result_2_CYSELG_2762,
O => CU_Result_2_CYMUXG2_2773
);
CU_Result_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(3),
O => CU_Result_2_CYSELG_2762
);
CU_Result_4_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y20"
)
port map (
O => CU_Result_4_LOGIC_ONE_2809
);
CU_Result_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_4_XORF_2829,
O => CU_Result(4)
);
CU_Result_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
I0 => CU_Result_4_CYINIT_2828,
I1 => CU_Mcount_state_timer_lut(4),
O => CU_Result_4_XORF_2829
);
CU_Result_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
IA => CU_Result_4_LOGIC_ONE_2809,
IB => CU_Result_4_CYINIT_2828,
SEL => CU_Result_4_CYSELF_2815,
O => CU_Mcount_state_timer_cy_4_Q
);
CU_Result_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
IA => CU_Result_4_LOGIC_ONE_2809,
IB => CU_Result_4_LOGIC_ONE_2809,
SEL => CU_Result_4_CYSELF_2815,
O => CU_Result_4_CYMUXF2_2810
);
CU_Result_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_3_Q,
O => CU_Result_4_CYINIT_2828
);
CU_Result_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(4),
O => CU_Result_4_CYSELF_2815
);
CU_Result_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_4_XORG_2817,
O => CU_Result(5)
);
CU_Result_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
I0 => CU_Mcount_state_timer_cy_4_Q,
I1 => CU_Mcount_state_timer_lut(5),
O => CU_Result_4_XORG_2817
);
CU_Result_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_4_CYMUXFAST_2814,
O => CU_Mcount_state_timer_cy_5_Q
);
CU_Result_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_3_Q,
O => CU_Result_4_FASTCARRY_2812
);
CU_Result_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
I0 => CU_Result_4_CYSELG_2800,
I1 => CU_Result_4_CYSELF_2815,
O => CU_Result_4_CYAND_2813
);
CU_Result_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
IA => CU_Result_4_CYMUXG2_2811,
IB => CU_Result_4_FASTCARRY_2812,
SEL => CU_Result_4_CYAND_2813,
O => CU_Result_4_CYMUXFAST_2814
);
CU_Result_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
IA => CU_Result_4_LOGIC_ONE_2809,
IB => CU_Result_4_CYMUXF2_2810,
SEL => CU_Result_4_CYSELG_2800,
O => CU_Result_4_CYMUXG2_2811
);
CU_Result_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(5),
O => CU_Result_4_CYSELG_2800
);
CU_Result_6_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y21"
)
port map (
O => CU_Result_6_LOGIC_ONE_2847
);
CU_Result_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_6_XORF_2867,
O => CU_Result(6)
);
CU_Result_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y21"
)
port map (
I0 => CU_Result_6_CYINIT_2866,
I1 => CU_Mcount_state_timer_lut(6),
O => CU_Result_6_XORF_2867
);
CU_Result_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y21"
)
port map (
IA => CU_Result_6_LOGIC_ONE_2847,
IB => CU_Result_6_CYINIT_2866,
SEL => CU_Result_6_CYSELF_2853,
O => CU_Mcount_state_timer_cy_6_Q
);
CU_Result_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y21"
)
port map (
IA => CU_Result_6_LOGIC_ONE_2847,
IB => CU_Result_6_LOGIC_ONE_2847,
SEL => CU_Result_6_CYSELF_2853,
O => CU_Result_6_CYMUXF2_2848
);
CU_Result_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_5_Q,
O => CU_Result_6_CYINIT_2866
);
CU_Result_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(6),
O => CU_Result_6_CYSELF_2853
);
CU_Result_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_6_XORG_2855,
O => CU_Result(7)
);
CU_Result_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y21"
)
port map (
I0 => CU_Mcount_state_timer_cy_6_Q,
I1 => CU_Mcount_state_timer_lut(7),
O => CU_Result_6_XORG_2855
);
CU_Result_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_6_CYMUXFAST_2852,
O => CU_Mcount_state_timer_cy_7_Q
);
CU_Result_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_5_Q,
O => CU_Result_6_FASTCARRY_2850
);
CU_Result_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y21"
)
port map (
I0 => CU_Result_6_CYSELG_2838,
I1 => CU_Result_6_CYSELF_2853,
O => CU_Result_6_CYAND_2851
);
CU_Result_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y21"
)
port map (
IA => CU_Result_6_CYMUXG2_2849,
IB => CU_Result_6_FASTCARRY_2850,
SEL => CU_Result_6_CYAND_2851,
O => CU_Result_6_CYMUXFAST_2852
);
CU_Result_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y21"
)
port map (
IA => CU_Result_6_LOGIC_ONE_2847,
IB => CU_Result_6_CYMUXF2_2848,
SEL => CU_Result_6_CYSELG_2838,
O => CU_Result_6_CYMUXG2_2849
);
CU_Result_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(7),
O => CU_Result_6_CYSELG_2838
);
CU_Result_8_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y22"
)
port map (
O => CU_Result_8_LOGIC_ONE_2885
);
CU_Result_8_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_8_XORF_2905,
O => CU_Result(8)
);
CU_Result_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y22"
)
port map (
I0 => CU_Result_8_CYINIT_2904,
I1 => CU_Mcount_state_timer_lut(8),
O => CU_Result_8_XORF_2905
);
CU_Result_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y22"
)
port map (
IA => CU_Result_8_LOGIC_ONE_2885,
IB => CU_Result_8_CYINIT_2904,
SEL => CU_Result_8_CYSELF_2891,
O => CU_Mcount_state_timer_cy_8_Q
);
CU_Result_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y22"
)
port map (
IA => CU_Result_8_LOGIC_ONE_2885,
IB => CU_Result_8_LOGIC_ONE_2885,
SEL => CU_Result_8_CYSELF_2891,
O => CU_Result_8_CYMUXF2_2886
);
CU_Result_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_7_Q,
O => CU_Result_8_CYINIT_2904
);
CU_Result_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(8),
O => CU_Result_8_CYSELF_2891
);
CU_Result_8_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_8_XORG_2893,
O => CU_Result(9)
);
CU_Result_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y22"
)
port map (
I0 => CU_Mcount_state_timer_cy_8_Q,
I1 => CU_Mcount_state_timer_lut(9),
O => CU_Result_8_XORG_2893
);
CU_Result_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_8_CYMUXFAST_2890,
O => CU_Mcount_state_timer_cy_9_Q
);
CU_Result_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_7_Q,
O => CU_Result_8_FASTCARRY_2888
);
CU_Result_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y22"
)
port map (
I0 => CU_Result_8_CYSELG_2876,
I1 => CU_Result_8_CYSELF_2891,
O => CU_Result_8_CYAND_2889
);
CU_Result_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y22"
)
port map (
IA => CU_Result_8_CYMUXG2_2887,
IB => CU_Result_8_FASTCARRY_2888,
SEL => CU_Result_8_CYAND_2889,
O => CU_Result_8_CYMUXFAST_2890
);
CU_Result_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y22"
)
port map (
IA => CU_Result_8_LOGIC_ONE_2885,
IB => CU_Result_8_CYMUXF2_2886,
SEL => CU_Result_8_CYSELG_2876,
O => CU_Result_8_CYMUXG2_2887
);
CU_Result_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(9),
O => CU_Result_8_CYSELG_2876
);
CU_Result_10_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y23"
)
port map (
O => CU_Result_10_LOGIC_ONE_2923
);
CU_Result_10_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_10_XORF_2943,
O => CU_Result(10)
);
CU_Result_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y23"
)
port map (
I0 => CU_Result_10_CYINIT_2942,
I1 => CU_Mcount_state_timer_lut(10),
O => CU_Result_10_XORF_2943
);
CU_Result_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y23"
)
port map (
IA => CU_Result_10_LOGIC_ONE_2923,
IB => CU_Result_10_CYINIT_2942,
SEL => CU_Result_10_CYSELF_2929,
O => CU_Mcount_state_timer_cy_10_Q
);
CU_Result_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y23"
)
port map (
IA => CU_Result_10_LOGIC_ONE_2923,
IB => CU_Result_10_LOGIC_ONE_2923,
SEL => CU_Result_10_CYSELF_2929,
O => CU_Result_10_CYMUXF2_2924
);
CU_Result_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_9_Q,
O => CU_Result_10_CYINIT_2942
);
CU_Result_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(10),
O => CU_Result_10_CYSELF_2929
);
CU_Result_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_10_XORG_2931,
O => CU_Result(11)
);
CU_Result_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y23"
)
port map (
I0 => CU_Mcount_state_timer_cy_10_Q,
I1 => CU_Mcount_state_timer_lut(11),
O => CU_Result_10_XORG_2931
);
CU_Result_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_10_CYMUXFAST_2928,
O => CU_Mcount_state_timer_cy_11_Q
);
CU_Result_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_9_Q,
O => CU_Result_10_FASTCARRY_2926
);
CU_Result_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y23"
)
port map (
I0 => CU_Result_10_CYSELG_2914,
I1 => CU_Result_10_CYSELF_2929,
O => CU_Result_10_CYAND_2927
);
CU_Result_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y23"
)
port map (
IA => CU_Result_10_CYMUXG2_2925,
IB => CU_Result_10_FASTCARRY_2926,
SEL => CU_Result_10_CYAND_2927,
O => CU_Result_10_CYMUXFAST_2928
);
CU_Result_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y23"
)
port map (
IA => CU_Result_10_LOGIC_ONE_2923,
IB => CU_Result_10_CYMUXF2_2924,
SEL => CU_Result_10_CYSELG_2914,
O => CU_Result_10_CYMUXG2_2925
);
CU_Result_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(11),
O => CU_Result_10_CYSELG_2914
);
CU_Result_12_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y24"
)
port map (
O => CU_Result_12_LOGIC_ONE_2961
);
CU_Result_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_12_XORF_2981,
O => CU_Result(12)
);
CU_Result_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y24"
)
port map (
I0 => CU_Result_12_CYINIT_2980,
I1 => CU_Mcount_state_timer_lut(12),
O => CU_Result_12_XORF_2981
);
CU_Result_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y24"
)
port map (
IA => CU_Result_12_LOGIC_ONE_2961,
IB => CU_Result_12_CYINIT_2980,
SEL => CU_Result_12_CYSELF_2967,
O => CU_Mcount_state_timer_cy_12_Q
);
CU_Result_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y24"
)
port map (
IA => CU_Result_12_LOGIC_ONE_2961,
IB => CU_Result_12_LOGIC_ONE_2961,
SEL => CU_Result_12_CYSELF_2967,
O => CU_Result_12_CYMUXF2_2962
);
CU_Result_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_11_Q,
O => CU_Result_12_CYINIT_2980
);
CU_Result_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(12),
O => CU_Result_12_CYSELF_2967
);
CU_Result_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_12_XORG_2969,
O => CU_Result(13)
);
CU_Result_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y24"
)
port map (
I0 => CU_Mcount_state_timer_cy_12_Q,
I1 => CU_Mcount_state_timer_lut(13),
O => CU_Result_12_XORG_2969
);
CU_Result_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_12_CYMUXFAST_2966,
O => CU_Mcount_state_timer_cy_13_Q
);
CU_Result_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_11_Q,
O => CU_Result_12_FASTCARRY_2964
);
CU_Result_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y24"
)
port map (
I0 => CU_Result_12_CYSELG_2952,
I1 => CU_Result_12_CYSELF_2967,
O => CU_Result_12_CYAND_2965
);
CU_Result_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y24"
)
port map (
IA => CU_Result_12_CYMUXG2_2963,
IB => CU_Result_12_FASTCARRY_2964,
SEL => CU_Result_12_CYAND_2965,
O => CU_Result_12_CYMUXFAST_2966
);
CU_Result_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y24"
)
port map (
IA => CU_Result_12_LOGIC_ONE_2961,
IB => CU_Result_12_CYMUXF2_2962,
SEL => CU_Result_12_CYSELG_2952,
O => CU_Result_12_CYMUXG2_2963
);
CU_Result_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(13),
O => CU_Result_12_CYSELG_2952
);
CU_Result_14_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y25"
)
port map (
O => CU_Result_14_LOGIC_ONE_2999
);
CU_Result_14_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_14_XORF_3019,
O => CU_Result(14)
);
CU_Result_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y25"
)
port map (
I0 => CU_Result_14_CYINIT_3018,
I1 => CU_Mcount_state_timer_lut(14),
O => CU_Result_14_XORF_3019
);
CU_Result_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y25"
)
port map (
IA => CU_Result_14_LOGIC_ONE_2999,
IB => CU_Result_14_CYINIT_3018,
SEL => CU_Result_14_CYSELF_3005,
O => CU_Mcount_state_timer_cy_14_Q
);
CU_Result_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y25"
)
port map (
IA => CU_Result_14_LOGIC_ONE_2999,
IB => CU_Result_14_LOGIC_ONE_2999,
SEL => CU_Result_14_CYSELF_3005,
O => CU_Result_14_CYMUXF2_3000
);
CU_Result_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_13_Q,
O => CU_Result_14_CYINIT_3018
);
CU_Result_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(14),
O => CU_Result_14_CYSELF_3005
);
CU_Result_14_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_14_XORG_3007,
O => CU_Result(15)
);
CU_Result_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y25"
)
port map (
I0 => CU_Mcount_state_timer_cy_14_Q,
I1 => CU_Mcount_state_timer_lut(15),
O => CU_Result_14_XORG_3007
);
CU_Result_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_14_CYMUXFAST_3004,
O => CU_Mcount_state_timer_cy_15_Q
);
CU_Result_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_13_Q,
O => CU_Result_14_FASTCARRY_3002
);
CU_Result_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y25"
)
port map (
I0 => CU_Result_14_CYSELG_2990,
I1 => CU_Result_14_CYSELF_3005,
O => CU_Result_14_CYAND_3003
);
CU_Result_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y25"
)
port map (
IA => CU_Result_14_CYMUXG2_3001,
IB => CU_Result_14_FASTCARRY_3002,
SEL => CU_Result_14_CYAND_3003,
O => CU_Result_14_CYMUXFAST_3004
);
CU_Result_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y25"
)
port map (
IA => CU_Result_14_LOGIC_ONE_2999,
IB => CU_Result_14_CYMUXF2_3000,
SEL => CU_Result_14_CYSELG_2990,
O => CU_Result_14_CYMUXG2_3001
);
CU_Result_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(15),
O => CU_Result_14_CYSELG_2990
);
CU_Result_16_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y26"
)
port map (
O => CU_Result_16_LOGIC_ONE_3037
);
CU_Result_16_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_16_XORF_3057,
O => CU_Result(16)
);
CU_Result_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y26"
)
port map (
I0 => CU_Result_16_CYINIT_3056,
I1 => CU_Mcount_state_timer_lut(16),
O => CU_Result_16_XORF_3057
);
CU_Result_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y26"
)
port map (
IA => CU_Result_16_LOGIC_ONE_3037,
IB => CU_Result_16_CYINIT_3056,
SEL => CU_Result_16_CYSELF_3043,
O => CU_Mcount_state_timer_cy_16_Q
);
CU_Result_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y26"
)
port map (
IA => CU_Result_16_LOGIC_ONE_3037,
IB => CU_Result_16_LOGIC_ONE_3037,
SEL => CU_Result_16_CYSELF_3043,
O => CU_Result_16_CYMUXF2_3038
);
CU_Result_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_15_Q,
O => CU_Result_16_CYINIT_3056
);
CU_Result_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(16),
O => CU_Result_16_CYSELF_3043
);
CU_Result_16_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_16_XORG_3045,
O => CU_Result(17)
);
CU_Result_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y26"
)
port map (
I0 => CU_Mcount_state_timer_cy_16_Q,
I1 => CU_Mcount_state_timer_lut(17),
O => CU_Result_16_XORG_3045
);
CU_Result_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_16_CYMUXFAST_3042,
O => CU_Mcount_state_timer_cy_17_Q
);
CU_Result_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_15_Q,
O => CU_Result_16_FASTCARRY_3040
);
CU_Result_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y26"
)
port map (
I0 => CU_Result_16_CYSELG_3028,
I1 => CU_Result_16_CYSELF_3043,
O => CU_Result_16_CYAND_3041
);
CU_Result_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y26"
)
port map (
IA => CU_Result_16_CYMUXG2_3039,
IB => CU_Result_16_FASTCARRY_3040,
SEL => CU_Result_16_CYAND_3041,
O => CU_Result_16_CYMUXFAST_3042
);
CU_Result_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y26"
)
port map (
IA => CU_Result_16_LOGIC_ONE_3037,
IB => CU_Result_16_CYMUXF2_3038,
SEL => CU_Result_16_CYSELG_3028,
O => CU_Result_16_CYMUXG2_3039
);
CU_Result_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(17),
O => CU_Result_16_CYSELG_3028
);
CU_Result_18_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y27"
)
port map (
O => CU_Result_18_LOGIC_ONE_3075
);
CU_Result_18_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_18_XORF_3095,
O => CU_Result(18)
);
CU_Result_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y27"
)
port map (
I0 => CU_Result_18_CYINIT_3094,
I1 => CU_Mcount_state_timer_lut(18),
O => CU_Result_18_XORF_3095
);
CU_Result_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y27"
)
port map (
IA => CU_Result_18_LOGIC_ONE_3075,
IB => CU_Result_18_CYINIT_3094,
SEL => CU_Result_18_CYSELF_3081,
O => CU_Mcount_state_timer_cy_18_Q
);
CU_Result_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y27"
)
port map (
IA => CU_Result_18_LOGIC_ONE_3075,
IB => CU_Result_18_LOGIC_ONE_3075,
SEL => CU_Result_18_CYSELF_3081,
O => CU_Result_18_CYMUXF2_3076
);
CU_Result_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_17_Q,
O => CU_Result_18_CYINIT_3094
);
CU_Result_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(18),
O => CU_Result_18_CYSELF_3081
);
CU_Result_18_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_18_XORG_3083,
O => CU_Result(19)
);
CU_Result_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y27"
)
port map (
I0 => CU_Mcount_state_timer_cy_18_Q,
I1 => CU_Mcount_state_timer_lut(19),
O => CU_Result_18_XORG_3083
);
CU_Result_18_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_18_CYMUXFAST_3080,
O => CU_Mcount_state_timer_cy_19_Q
);
CU_Result_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_17_Q,
O => CU_Result_18_FASTCARRY_3078
);
CU_Result_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y27"
)
port map (
I0 => CU_Result_18_CYSELG_3066,
I1 => CU_Result_18_CYSELF_3081,
O => CU_Result_18_CYAND_3079
);
CU_Result_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y27"
)
port map (
IA => CU_Result_18_CYMUXG2_3077,
IB => CU_Result_18_FASTCARRY_3078,
SEL => CU_Result_18_CYAND_3079,
O => CU_Result_18_CYMUXFAST_3080
);
CU_Result_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y27"
)
port map (
IA => CU_Result_18_LOGIC_ONE_3075,
IB => CU_Result_18_CYMUXF2_3076,
SEL => CU_Result_18_CYSELG_3066,
O => CU_Result_18_CYMUXG2_3077
);
CU_Result_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(19),
O => CU_Result_18_CYSELG_3066
);
CU_Result_20_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y28"
)
port map (
O => CU_Result_20_LOGIC_ONE_3113
);
CU_Result_20_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_20_XORF_3133,
O => CU_Result(20)
);
CU_Result_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y28"
)
port map (
I0 => CU_Result_20_CYINIT_3132,
I1 => CU_Mcount_state_timer_lut(20),
O => CU_Result_20_XORF_3133
);
CU_Result_20_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y28"
)
port map (
IA => CU_Result_20_LOGIC_ONE_3113,
IB => CU_Result_20_CYINIT_3132,
SEL => CU_Result_20_CYSELF_3119,
O => CU_Mcount_state_timer_cy_20_Q
);
CU_Result_20_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y28"
)
port map (
IA => CU_Result_20_LOGIC_ONE_3113,
IB => CU_Result_20_LOGIC_ONE_3113,
SEL => CU_Result_20_CYSELF_3119,
O => CU_Result_20_CYMUXF2_3114
);
CU_Result_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_19_Q,
O => CU_Result_20_CYINIT_3132
);
CU_Result_20_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(20),
O => CU_Result_20_CYSELF_3119
);
CU_Result_20_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_20_XORG_3121,
O => CU_Result(21)
);
CU_Result_20_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y28"
)
port map (
I0 => CU_Mcount_state_timer_cy_20_Q,
I1 => CU_Mcount_state_timer_lut(21),
O => CU_Result_20_XORG_3121
);
CU_Result_20_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_20_CYMUXFAST_3118,
O => CU_Mcount_state_timer_cy_21_Q
);
CU_Result_20_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_19_Q,
O => CU_Result_20_FASTCARRY_3116
);
CU_Result_20_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y28"
)
port map (
I0 => CU_Result_20_CYSELG_3104,
I1 => CU_Result_20_CYSELF_3119,
O => CU_Result_20_CYAND_3117
);
CU_Result_20_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y28"
)
port map (
IA => CU_Result_20_CYMUXG2_3115,
IB => CU_Result_20_FASTCARRY_3116,
SEL => CU_Result_20_CYAND_3117,
O => CU_Result_20_CYMUXFAST_3118
);
CU_Result_20_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y28"
)
port map (
IA => CU_Result_20_LOGIC_ONE_3113,
IB => CU_Result_20_CYMUXF2_3114,
SEL => CU_Result_20_CYSELG_3104,
O => CU_Result_20_CYMUXG2_3115
);
CU_Result_20_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(21),
O => CU_Result_20_CYSELG_3104
);
CU_Result_22_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y29"
)
port map (
O => CU_Result_22_LOGIC_ONE_3151
);
CU_Result_22_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_22_XORF_3171,
O => CU_Result(22)
);
CU_Result_22_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y29"
)
port map (
I0 => CU_Result_22_CYINIT_3170,
I1 => CU_Mcount_state_timer_lut(22),
O => CU_Result_22_XORF_3171
);
CU_Result_22_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y29"
)
port map (
IA => CU_Result_22_LOGIC_ONE_3151,
IB => CU_Result_22_CYINIT_3170,
SEL => CU_Result_22_CYSELF_3157,
O => CU_Mcount_state_timer_cy_22_Q
);
CU_Result_22_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y29"
)
port map (
IA => CU_Result_22_LOGIC_ONE_3151,
IB => CU_Result_22_LOGIC_ONE_3151,
SEL => CU_Result_22_CYSELF_3157,
O => CU_Result_22_CYMUXF2_3152
);
CU_Result_22_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_21_Q,
O => CU_Result_22_CYINIT_3170
);
CU_Result_22_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(22),
O => CU_Result_22_CYSELF_3157
);
CU_Result_22_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_22_XORG_3159,
O => CU_Result(23)
);
CU_Result_22_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y29"
)
port map (
I0 => CU_Mcount_state_timer_cy_22_Q,
I1 => CU_Mcount_state_timer_lut(23),
O => CU_Result_22_XORG_3159
);
CU_Result_22_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_22_CYMUXFAST_3156,
O => CU_Mcount_state_timer_cy_23_Q
);
CU_Result_22_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_21_Q,
O => CU_Result_22_FASTCARRY_3154
);
CU_Result_22_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y29"
)
port map (
I0 => CU_Result_22_CYSELG_3142,
I1 => CU_Result_22_CYSELF_3157,
O => CU_Result_22_CYAND_3155
);
CU_Result_22_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y29"
)
port map (
IA => CU_Result_22_CYMUXG2_3153,
IB => CU_Result_22_FASTCARRY_3154,
SEL => CU_Result_22_CYAND_3155,
O => CU_Result_22_CYMUXFAST_3156
);
CU_Result_22_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y29"
)
port map (
IA => CU_Result_22_LOGIC_ONE_3151,
IB => CU_Result_22_CYMUXF2_3152,
SEL => CU_Result_22_CYSELG_3142,
O => CU_Result_22_CYMUXG2_3153
);
CU_Result_22_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(23),
O => CU_Result_22_CYSELG_3142
);
CU_Result_24_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y30"
)
port map (
O => CU_Result_24_LOGIC_ONE_3189
);
CU_Result_24_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_24_XORF_3209,
O => CU_Result(24)
);
CU_Result_24_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y30"
)
port map (
I0 => CU_Result_24_CYINIT_3208,
I1 => CU_Mcount_state_timer_lut(24),
O => CU_Result_24_XORF_3209
);
CU_Result_24_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y30"
)
port map (
IA => CU_Result_24_LOGIC_ONE_3189,
IB => CU_Result_24_CYINIT_3208,
SEL => CU_Result_24_CYSELF_3195,
O => CU_Mcount_state_timer_cy_24_Q
);
CU_Result_24_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y30"
)
port map (
IA => CU_Result_24_LOGIC_ONE_3189,
IB => CU_Result_24_LOGIC_ONE_3189,
SEL => CU_Result_24_CYSELF_3195,
O => CU_Result_24_CYMUXF2_3190
);
CU_Result_24_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_23_Q,
O => CU_Result_24_CYINIT_3208
);
CU_Result_24_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(24),
O => CU_Result_24_CYSELF_3195
);
CU_Result_24_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_24_XORG_3197,
O => CU_Result(25)
);
CU_Result_24_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y30"
)
port map (
I0 => CU_Mcount_state_timer_cy_24_Q,
I1 => CU_Mcount_state_timer_lut(25),
O => CU_Result_24_XORG_3197
);
CU_Result_24_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_24_CYMUXFAST_3194,
O => CU_Mcount_state_timer_cy_25_Q
);
CU_Result_24_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_23_Q,
O => CU_Result_24_FASTCARRY_3192
);
CU_Result_24_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y30"
)
port map (
I0 => CU_Result_24_CYSELG_3180,
I1 => CU_Result_24_CYSELF_3195,
O => CU_Result_24_CYAND_3193
);
CU_Result_24_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y30"
)
port map (
IA => CU_Result_24_CYMUXG2_3191,
IB => CU_Result_24_FASTCARRY_3192,
SEL => CU_Result_24_CYAND_3193,
O => CU_Result_24_CYMUXFAST_3194
);
CU_Result_24_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y30"
)
port map (
IA => CU_Result_24_LOGIC_ONE_3189,
IB => CU_Result_24_CYMUXF2_3190,
SEL => CU_Result_24_CYSELG_3180,
O => CU_Result_24_CYMUXG2_3191
);
CU_Result_24_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(25),
O => CU_Result_24_CYSELG_3180
);
CU_Mcount_state_timer_lut_26_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y31"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(26),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(26)
);
CU_Result_26_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y31"
)
port map (
O => CU_Result_26_LOGIC_ONE_3227
);
CU_Result_26_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_26_XORF_3247,
O => CU_Result(26)
);
CU_Result_26_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y31"
)
port map (
I0 => CU_Result_26_CYINIT_3246,
I1 => CU_Mcount_state_timer_lut(26),
O => CU_Result_26_XORF_3247
);
CU_Result_26_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y31"
)
port map (
IA => CU_Result_26_LOGIC_ONE_3227,
IB => CU_Result_26_CYINIT_3246,
SEL => CU_Result_26_CYSELF_3233,
O => CU_Mcount_state_timer_cy_26_Q
);
CU_Result_26_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y31"
)
port map (
IA => CU_Result_26_LOGIC_ONE_3227,
IB => CU_Result_26_LOGIC_ONE_3227,
SEL => CU_Result_26_CYSELF_3233,
O => CU_Result_26_CYMUXF2_3228
);
CU_Result_26_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_25_Q,
O => CU_Result_26_CYINIT_3246
);
CU_Result_26_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(26),
O => CU_Result_26_CYSELF_3233
);
CU_Result_26_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_26_XORG_3235,
O => CU_Result(27)
);
CU_Result_26_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y31"
)
port map (
I0 => CU_Mcount_state_timer_cy_26_Q,
I1 => CU_Mcount_state_timer_lut(27),
O => CU_Result_26_XORG_3235
);
CU_Result_26_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X1Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_26_CYMUXFAST_3232,
O => CU_Mcount_state_timer_cy_27_Q
);
CU_Result_26_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_25_Q,
O => CU_Result_26_FASTCARRY_3230
);
CU_Result_26_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y31"
)
port map (
I0 => CU_Result_26_CYSELG_3218,
I1 => CU_Result_26_CYSELF_3233,
O => CU_Result_26_CYAND_3231
);
CU_Result_26_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y31"
)
port map (
IA => CU_Result_26_CYMUXG2_3229,
IB => CU_Result_26_FASTCARRY_3230,
SEL => CU_Result_26_CYAND_3231,
O => CU_Result_26_CYMUXFAST_3232
);
CU_Result_26_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y31"
)
port map (
IA => CU_Result_26_LOGIC_ONE_3227,
IB => CU_Result_26_CYMUXF2_3228,
SEL => CU_Result_26_CYSELG_3218,
O => CU_Result_26_CYMUXG2_3229
);
CU_Result_26_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(27),
O => CU_Result_26_CYSELG_3218
);
CU_Mcount_state_timer_lut_27_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X1Y31"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_state_timer(27),
O => CU_Mcount_state_timer_lut(27)
);
CU_Mcount_state_timer_lut_28_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y32"
)
port map (
ADR0 => CU_state_timer(28),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(28)
);
CU_Result_28_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y32"
)
port map (
O => CU_Result_28_LOGIC_ONE_3265
);
CU_Result_28_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_28_XORF_3285,
O => CU_Result(28)
);
CU_Result_28_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y32"
)
port map (
I0 => CU_Result_28_CYINIT_3284,
I1 => CU_Mcount_state_timer_lut(28),
O => CU_Result_28_XORF_3285
);
CU_Result_28_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y32"
)
port map (
IA => CU_Result_28_LOGIC_ONE_3265,
IB => CU_Result_28_CYINIT_3284,
SEL => CU_Result_28_CYSELF_3271,
O => CU_Mcount_state_timer_cy_28_Q
);
CU_Result_28_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X1Y32"
)
port map (
IA => CU_Result_28_LOGIC_ONE_3265,
IB => CU_Result_28_LOGIC_ONE_3265,
SEL => CU_Result_28_CYSELF_3271,
O => CU_Result_28_CYMUXF2_3266
);
CU_Result_28_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_27_Q,
O => CU_Result_28_CYINIT_3284
);
CU_Result_28_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(28),
O => CU_Result_28_CYSELF_3271
);
CU_Result_28_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_28_XORG_3273,
O => CU_Result(29)
);
CU_Result_28_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y32"
)
port map (
I0 => CU_Mcount_state_timer_cy_28_Q,
I1 => CU_Mcount_state_timer_lut(29),
O => CU_Result_28_XORG_3273
);
CU_Result_28_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X1Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_cy_27_Q,
O => CU_Result_28_FASTCARRY_3268
);
CU_Result_28_CYAND : X_AND2
generic map(
LOC => "SLICE_X1Y32"
)
port map (
I0 => CU_Result_28_CYSELG_3256,
I1 => CU_Result_28_CYSELF_3271,
O => CU_Result_28_CYAND_3269
);
CU_Result_28_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X1Y32"
)
port map (
IA => CU_Result_28_CYMUXG2_3267,
IB => CU_Result_28_FASTCARRY_3268,
SEL => CU_Result_28_CYAND_3269,
O => CU_Result_28_CYMUXFAST_3270
);
CU_Result_28_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X1Y32"
)
port map (
IA => CU_Result_28_LOGIC_ONE_3265,
IB => CU_Result_28_CYMUXF2_3266,
SEL => CU_Result_28_CYSELG_3256,
O => CU_Result_28_CYMUXG2_3267
);
CU_Result_28_CYSELG : X_BUF
generic map(
LOC => "SLICE_X1Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(29),
O => CU_Result_28_CYSELG_3256
);
CU_Mcount_state_timer_lut_29_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X1Y32"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_state_timer(29),
O => CU_Mcount_state_timer_lut(29)
);
CU_Mcount_state_timer_lut_30_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y33"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(30),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(30)
);
CU_Result_30_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X1Y33"
)
port map (
O => CU_Result_30_LOGIC_ONE_3315
);
CU_Result_30_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y33",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_30_XORF_3316,
O => CU_Result(30)
);
CU_Result_30_XORF : X_XOR2
generic map(
LOC => "SLICE_X1Y33"
)
port map (
I0 => CU_Result_30_CYINIT_3314,
I1 => CU_Mcount_state_timer_lut(30),
O => CU_Result_30_XORF_3316
);
CU_Result_30_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X1Y33"
)
port map (
IA => CU_Result_30_LOGIC_ONE_3315,
IB => CU_Result_30_CYINIT_3314,
SEL => CU_Result_30_CYSELF_3305,
O => CU_Mcount_state_timer_cy_30_Q
);
CU_Result_30_CYINIT : X_BUF
generic map(
LOC => "SLICE_X1Y33",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_28_CYMUXFAST_3270,
O => CU_Result_30_CYINIT_3314
);
CU_Result_30_CYSELF : X_BUF
generic map(
LOC => "SLICE_X1Y33",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_lut(30),
O => CU_Result_30_CYSELF_3305
);
CU_Result_30_YUSED : X_BUF
generic map(
LOC => "SLICE_X1Y33",
PATHPULSE => 638 ps
)
port map (
I => CU_Result_30_XORG_3302,
O => CU_Result(31)
);
CU_Result_30_XORG : X_XOR2
generic map(
LOC => "SLICE_X1Y33"
)
port map (
I0 => CU_Mcount_state_timer_cy_30_Q,
I1 => CU_Mcount_state_timer_lut(31),
O => CU_Result_30_XORG_3302
);
CU_Mcount_state_timer_lut_31_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y33"
)
port map (
ADR0 => CU_state_timer(31),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(31)
);
PC_Mcount_data_lut_1_Q : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X27Y19"
)
port map (
ADR0 => VCC,
ADR1 => PC_data(1),
ADR2 => CU_loadPC_1524,
ADR3 => R_D_M_reg(1),
O => PC_Mcount_data_lut(1)
);
PC_data_0_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_data_0_SRINV_3333,
O => PC_data_0_FFY_RST
);
PC_data_1 : X_FF
generic map(
LOC => "SLICE_X27Y19",
INIT => '0'
)
port map (
I => PC_data_0_DYMUX_3347,
CE => PC_data_0_CEINV_3331,
CLK => PC_data_0_CLKINV_3332,
SET => GND,
RST => PC_data_0_FFY_RST,
O => PC_data(1)
);
PC_Mcount_data_lut_0_Q : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X27Y19"
)
port map (
ADR0 => VCC,
ADR1 => PC_data(0),
ADR2 => CU_loadPC_1524,
ADR3 => R_D_M_reg(0),
O => PC_Mcount_data_lut(0)
);
PC_data_0_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_data_0_SRINV_3333,
O => PC_data_0_FFX_RST
);
PC_data_0 : X_FF
generic map(
LOC => "SLICE_X27Y19",
INIT => '0'
)
port map (
I => PC_data_0_DXMUX_3367,
CE => PC_data_0_CEINV_3331,
CLK => PC_data_0_CLKINV_3332,
SET => GND,
RST => PC_data_0_FFX_RST,
O => PC_data(0)
);
PC_data_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X27Y19"
)
port map (
O => PC_data_0_LOGIC_ZERO_3342
);
PC_data_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_data_0_XORF_3365,
O => PC_data_0_DXMUX_3367
);
PC_data_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X27Y19"
)
port map (
I0 => PC_data_0_CYINIT_3364,
I1 => PC_Mcount_data_lut(0),
O => PC_data_0_XORF_3365
);
PC_data_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X27Y19"
)
port map (
IA => PC_data_0_LOGIC_ZERO_3342,
IB => PC_data_0_CYINIT_3364,
SEL => PC_data_0_CYSELF_3357,
O => PC_Mcount_data_cy_0_Q
);
PC_data_0_CYINIT : X_INV
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_loadPC_1524,
O => PC_data_0_CYINIT_3364
);
PC_data_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_lut(0),
O => PC_data_0_CYSELF_3357
);
PC_data_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_data_0_XORG_3345,
O => PC_data_0_DYMUX_3347
);
PC_data_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X27Y19"
)
port map (
I0 => PC_Mcount_data_cy_0_Q,
I1 => PC_Mcount_data_lut(1),
O => PC_data_0_XORG_3345
);
PC_data_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_data_0_CYMUXG_3344,
O => PC_Mcount_data_cy_1_Q
);
PC_data_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X27Y19"
)
port map (
IA => PC_data_0_LOGIC_ZERO_3342,
IB => PC_Mcount_data_cy_0_Q,
SEL => PC_data_0_CYSELG_3335,
O => PC_data_0_CYMUXG_3344
);
PC_data_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_lut(1),
O => PC_data_0_CYSELG_3335
);
PC_data_0_SRINV : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => PC_data_0_SRINV_3333
);
PC_data_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => PC_data_0_CLKINV_3332
);
PC_data_0_CEINV : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => PC_data_not0001_0,
O => PC_data_0_CEINV_3331
);
PC_Mcount_data_lut_2_Q : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X27Y20"
)
port map (
ADR0 => PC_data(2),
ADR1 => VCC,
ADR2 => CU_loadPC_1524,
ADR3 => R_D_M_reg(2),
O => PC_Mcount_data_lut(2)
);
PC_data_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X27Y20"
)
port map (
O => PC_data_2_LOGIC_ZERO_3399
);
PC_data_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_data_2_XORF_3425,
O => PC_data_2_DXMUX_3427
);
PC_data_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
I0 => PC_data_2_CYINIT_3424,
I1 => PC_Mcount_data_lut(2),
O => PC_data_2_XORF_3425
);
PC_data_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
IA => PC_data_2_LOGIC_ZERO_3399,
IB => PC_data_2_CYINIT_3424,
SEL => PC_data_2_CYSELF_3405,
O => PC_Mcount_data_cy_2_Q
);
PC_data_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
IA => PC_data_2_LOGIC_ZERO_3399,
IB => PC_data_2_LOGIC_ZERO_3399,
SEL => PC_data_2_CYSELF_3405,
O => PC_data_2_CYMUXF2_3400
);
PC_data_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_cy_1_Q,
O => PC_data_2_CYINIT_3424
);
PC_data_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_lut(2),
O => PC_data_2_CYSELF_3405
);
PC_data_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_data_2_XORG_3407,
O => PC_data_2_DYMUX_3409
);
PC_data_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
I0 => PC_Mcount_data_cy_2_Q,
I1 => PC_Mcount_data_lut(3),
O => PC_data_2_XORG_3407
);
PC_data_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_data_2_CYMUXFAST_3404,
O => PC_Mcount_data_cy_3_Q
);
PC_data_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_cy_1_Q,
O => PC_data_2_FASTCARRY_3402
);
PC_data_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
I0 => PC_data_2_CYSELG_3392,
I1 => PC_data_2_CYSELF_3405,
O => PC_data_2_CYAND_3403
);
PC_data_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
IA => PC_data_2_CYMUXG2_3401,
IB => PC_data_2_FASTCARRY_3402,
SEL => PC_data_2_CYAND_3403,
O => PC_data_2_CYMUXFAST_3404
);
PC_data_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
IA => PC_data_2_LOGIC_ZERO_3399,
IB => PC_data_2_CYMUXF2_3400,
SEL => PC_data_2_CYSELG_3392,
O => PC_data_2_CYMUXG2_3401
);
PC_data_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_lut(3),
O => PC_data_2_CYSELG_3392
);
PC_data_2_SRINV : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => PC_data_2_SRINV_3390
);
PC_data_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => PC_data_2_CLKINV_3389
);
PC_data_2_CEINV : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => PC_data_not0001_0,
O => PC_data_2_CEINV_3388
);
PC_data_3 : X_FF
generic map(
LOC => "SLICE_X27Y20",
INIT => '0'
)
port map (
I => PC_data_2_DYMUX_3409,
CE => PC_data_2_CEINV_3388,
CLK => PC_data_2_CLKINV_3389,
SET => GND,
RST => PC_data_2_SRINV_3390,
O => PC_data(3)
);
PC_data_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X27Y21"
)
port map (
O => PC_data_4_LOGIC_ZERO_3459
);
PC_data_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => PC_data_4_XORF_3485,
O => PC_data_4_DXMUX_3487
);
PC_data_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X27Y21"
)
port map (
I0 => PC_data_4_CYINIT_3484,
I1 => PC_Mcount_data_lut(4),
O => PC_data_4_XORF_3485
);
PC_data_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X27Y21"
)
port map (
IA => PC_data_4_LOGIC_ZERO_3459,
IB => PC_data_4_CYINIT_3484,
SEL => PC_data_4_CYSELF_3465,
O => PC_Mcount_data_cy_4_Q
);
PC_data_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X27Y21"
)
port map (
IA => PC_data_4_LOGIC_ZERO_3459,
IB => PC_data_4_LOGIC_ZERO_3459,
SEL => PC_data_4_CYSELF_3465,
O => PC_data_4_CYMUXF2_3460
);
PC_data_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_cy_3_Q,
O => PC_data_4_CYINIT_3484
);
PC_data_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_lut(4),
O => PC_data_4_CYSELF_3465
);
PC_data_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => PC_data_4_XORG_3467,
O => PC_data_4_DYMUX_3469
);
PC_data_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X27Y21"
)
port map (
I0 => PC_Mcount_data_cy_4_Q,
I1 => PC_Mcount_data_lut(5),
O => PC_data_4_XORG_3467
);
PC_data_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_cy_3_Q,
O => PC_data_4_FASTCARRY_3462
);
PC_data_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X27Y21"
)
port map (
I0 => PC_data_4_CYSELG_3452,
I1 => PC_data_4_CYSELF_3465,
O => PC_data_4_CYAND_3463
);
PC_data_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X27Y21"
)
port map (
IA => PC_data_4_CYMUXG2_3461,
IB => PC_data_4_FASTCARRY_3462,
SEL => PC_data_4_CYAND_3463,
O => PC_data_4_CYMUXFAST_3464
);
PC_data_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X27Y21"
)
port map (
IA => PC_data_4_LOGIC_ZERO_3459,
IB => PC_data_4_CYMUXF2_3460,
SEL => PC_data_4_CYSELG_3452,
O => PC_data_4_CYMUXG2_3461
);
PC_data_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_lut(5),
O => PC_data_4_CYSELG_3452
);
PC_data_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => PC_data_4_SRINV_3450
);
PC_data_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => PC_data_4_CLKINV_3449
);
PC_data_4_CEINV : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => PC_data_not0001_0,
O => PC_data_4_CEINV_3448
);
PC_Mcount_data_lut_4_Q : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X27Y21"
)
port map (
ADR0 => VCC,
ADR1 => PC_data(4),
ADR2 => CU_loadPC_1524,
ADR3 => R_D_M_reg(4),
O => PC_Mcount_data_lut(4)
);
PC_data_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X27Y22"
)
port map (
O => PC_data_6_LOGIC_ZERO_3537
);
PC_data_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => PC_data_6_XORF_3538,
O => PC_data_6_DXMUX_3540
);
PC_data_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X27Y22"
)
port map (
I0 => PC_data_6_CYINIT_3536,
I1 => PC_Mcount_data_lut(6),
O => PC_data_6_XORF_3538
);
PC_data_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X27Y22"
)
port map (
IA => PC_data_6_LOGIC_ZERO_3537,
IB => PC_data_6_CYINIT_3536,
SEL => PC_data_6_CYSELF_3529,
O => PC_Mcount_data_cy_6_Q
);
PC_data_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => PC_data_4_CYMUXFAST_3464,
O => PC_data_6_CYINIT_3536
);
PC_data_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => PC_Mcount_data_lut(6),
O => PC_data_6_CYSELF_3529
);
PC_data_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => PC_data_6_XORG_3518,
O => PC_data_6_DYMUX_3520
);
PC_data_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X27Y22"
)
port map (
I0 => PC_Mcount_data_cy_6_Q,
I1 => PC_Mcount_data_lut(7),
O => PC_data_6_XORG_3518
);
PC_data_6_SRINV : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => PC_data_6_SRINV_3509
);
PC_data_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => PC_data_6_CLKINV_3508
);
PC_data_6_CEINV : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => PC_data_not0001_0,
O => PC_data_6_CEINV_3507
);
PC_data_6 : X_FF
generic map(
LOC => "SLICE_X27Y22",
INIT => '0'
)
port map (
I => PC_data_6_DXMUX_3540,
CE => PC_data_6_CEINV_3507,
CLK => PC_data_6_CLKINV_3508,
SET => GND,
RST => PC_data_6_SRINV_3509,
O => PC_data(6)
);
CU_current_state_cmp_eq0000_wg_cy_1_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X3Y20"
)
port map (
O => CU_current_state_cmp_eq0000_wg_cy_1_LOGIC_ZERO_3565
);
CU_current_state_cmp_eq0000_wg_cy_1_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X3Y20"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_1_LOGIC_ZERO_3565,
IB => CU_current_state_cmp_eq0000_wg_cy_1_CYINIT_3576,
SEL => CU_current_state_cmp_eq0000_wg_cy_1_CYSELF_3570,
O => CU_current_state_cmp_eq0000_wg_cy(0)
);
CU_current_state_cmp_eq0000_wg_cy_1_CYINIT : X_BUF
generic map(
LOC => "SLICE_X3Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_cy_1_BXINV_3568,
O => CU_current_state_cmp_eq0000_wg_cy_1_CYINIT_3576
);
CU_current_state_cmp_eq0000_wg_cy_1_CYSELF : X_BUF
generic map(
LOC => "SLICE_X3Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(0),
O => CU_current_state_cmp_eq0000_wg_cy_1_CYSELF_3570
);
CU_current_state_cmp_eq0000_wg_cy_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X3Y20",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => CU_current_state_cmp_eq0000_wg_cy_1_BXINV_3568
);
CU_current_state_cmp_eq0000_wg_cy_1_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X3Y20"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_1_LOGIC_ZERO_3565,
IB => CU_current_state_cmp_eq0000_wg_cy(0),
SEL => CU_current_state_cmp_eq0000_wg_cy_1_CYSELG_3559,
O => CU_current_state_cmp_eq0000_wg_cy_1_CYMUXG_3567
);
CU_current_state_cmp_eq0000_wg_cy_1_CYSELG : X_BUF
generic map(
LOC => "SLICE_X3Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(1),
O => CU_current_state_cmp_eq0000_wg_cy_1_CYSELG_3559
);
CU_current_state_cmp_eq0000_wg_cy_3_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X3Y21"
)
port map (
O => CU_current_state_cmp_eq0000_wg_cy_3_LOGIC_ZERO_3594
);
CU_current_state_cmp_eq0000_wg_cy_3_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X3Y21"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_3_LOGIC_ZERO_3594,
IB => CU_current_state_cmp_eq0000_wg_cy_3_LOGIC_ZERO_3594,
SEL => CU_current_state_cmp_eq0000_wg_cy_3_CYSELF_3600,
O => CU_current_state_cmp_eq0000_wg_cy_3_CYMUXF2_3595
);
CU_current_state_cmp_eq0000_wg_cy_3_CYSELF : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(2),
O => CU_current_state_cmp_eq0000_wg_cy_3_CYSELF_3600
);
CU_current_state_cmp_eq0000_wg_cy_3_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_cy_1_CYMUXG_3567,
O => CU_current_state_cmp_eq0000_wg_cy_3_FASTCARRY_3597
);
CU_current_state_cmp_eq0000_wg_cy_3_CYAND : X_AND2
generic map(
LOC => "SLICE_X3Y21"
)
port map (
I0 => CU_current_state_cmp_eq0000_wg_cy_3_CYSELG_3588,
I1 => CU_current_state_cmp_eq0000_wg_cy_3_CYSELF_3600,
O => CU_current_state_cmp_eq0000_wg_cy_3_CYAND_3598
);
CU_current_state_cmp_eq0000_wg_cy_3_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X3Y21"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_3_CYMUXG2_3596,
IB => CU_current_state_cmp_eq0000_wg_cy_3_FASTCARRY_3597,
SEL => CU_current_state_cmp_eq0000_wg_cy_3_CYAND_3598,
O => CU_current_state_cmp_eq0000_wg_cy_3_CYMUXFAST_3599
);
CU_current_state_cmp_eq0000_wg_cy_3_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X3Y21"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_3_LOGIC_ZERO_3594,
IB => CU_current_state_cmp_eq0000_wg_cy_3_CYMUXF2_3595,
SEL => CU_current_state_cmp_eq0000_wg_cy_3_CYSELG_3588,
O => CU_current_state_cmp_eq0000_wg_cy_3_CYMUXG2_3596
);
CU_current_state_cmp_eq0000_wg_cy_3_CYSELG : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(3),
O => CU_current_state_cmp_eq0000_wg_cy_3_CYSELG_3588
);
CU_current_state_cmp_eq0000_wg_cy_5_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X3Y22"
)
port map (
O => CU_current_state_cmp_eq0000_wg_cy_5_LOGIC_ZERO_3624
);
CU_current_state_cmp_eq0000_wg_cy_5_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X3Y22"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_5_LOGIC_ZERO_3624,
IB => CU_current_state_cmp_eq0000_wg_cy_5_LOGIC_ZERO_3624,
SEL => CU_current_state_cmp_eq0000_wg_cy_5_CYSELF_3630,
O => CU_current_state_cmp_eq0000_wg_cy_5_CYMUXF2_3625
);
CU_current_state_cmp_eq0000_wg_cy_5_CYSELF : X_BUF
generic map(
LOC => "SLICE_X3Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(4),
O => CU_current_state_cmp_eq0000_wg_cy_5_CYSELF_3630
);
CU_current_state_cmp_eq0000_wg_cy_5_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X3Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_cy_3_CYMUXFAST_3599,
O => CU_current_state_cmp_eq0000_wg_cy_5_FASTCARRY_3627
);
CU_current_state_cmp_eq0000_wg_cy_5_CYAND : X_AND2
generic map(
LOC => "SLICE_X3Y22"
)
port map (
I0 => CU_current_state_cmp_eq0000_wg_cy_5_CYSELG_3618,
I1 => CU_current_state_cmp_eq0000_wg_cy_5_CYSELF_3630,
O => CU_current_state_cmp_eq0000_wg_cy_5_CYAND_3628
);
CU_current_state_cmp_eq0000_wg_cy_5_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X3Y22"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_5_CYMUXG2_3626,
IB => CU_current_state_cmp_eq0000_wg_cy_5_FASTCARRY_3627,
SEL => CU_current_state_cmp_eq0000_wg_cy_5_CYAND_3628,
O => CU_current_state_cmp_eq0000_wg_cy_5_CYMUXFAST_3629
);
CU_current_state_cmp_eq0000_wg_cy_5_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X3Y22"
)
port map (
IA => CU_current_state_cmp_eq0000_wg_cy_5_LOGIC_ZERO_3624,
IB => CU_current_state_cmp_eq0000_wg_cy_5_CYMUXF2_3625,
SEL => CU_current_state_cmp_eq0000_wg_cy_5_CYSELG_3618,
O => CU_current_state_cmp_eq0000_wg_cy_5_CYMUXG2_3626
);
CU_current_state_cmp_eq0000_wg_cy_5_CYSELG : X_BUF
generic map(
LOC => "SLICE_X3Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(5),
O => CU_current_state_cmp_eq0000_wg_cy_5_CYSELG_3618
);
CU_current_state_cmp_eq0000_wg_lut_5_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y22"
)
port map (
ADR0 => CU_state_timer(2),
ADR1 => CU_state_timer(23),
ADR2 => CU_state_timer(24),
ADR3 => CU_state_timer(25),
O => CU_current_state_cmp_eq0000_wg_lut(5)
);
CU_state_timer_not0001_inv_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X3Y23"
)
port map (
O => CU_state_timer_not0001_inv_LOGIC_ZERO_3654
);
CU_state_timer_not0001_inv_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X3Y23"
)
port map (
IA => CU_state_timer_not0001_inv_LOGIC_ZERO_3654,
IB => CU_state_timer_not0001_inv_LOGIC_ZERO_3654,
SEL => CU_state_timer_not0001_inv_CYSELF_3660,
O => CU_state_timer_not0001_inv_CYMUXF2_3655
);
CU_state_timer_not0001_inv_CYSELF : X_BUF
generic map(
LOC => "SLICE_X3Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(6),
O => CU_state_timer_not0001_inv_CYSELF_3660
);
CU_state_timer_not0001_inv_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X3Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_state_timer_not0001_inv_CYMUXFAST_3659,
O => CU_state_timer_not0001_inv
);
CU_state_timer_not0001_inv_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X3Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_cy_5_CYMUXFAST_3629,
O => CU_state_timer_not0001_inv_FASTCARRY_3657
);
CU_state_timer_not0001_inv_CYAND : X_AND2
generic map(
LOC => "SLICE_X3Y23"
)
port map (
I0 => CU_state_timer_not0001_inv_CYSELG_3648,
I1 => CU_state_timer_not0001_inv_CYSELF_3660,
O => CU_state_timer_not0001_inv_CYAND_3658
);
CU_state_timer_not0001_inv_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X3Y23"
)
port map (
IA => CU_state_timer_not0001_inv_CYMUXG2_3656,
IB => CU_state_timer_not0001_inv_FASTCARRY_3657,
SEL => CU_state_timer_not0001_inv_CYAND_3658,
O => CU_state_timer_not0001_inv_CYMUXFAST_3659
);
CU_state_timer_not0001_inv_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X3Y23"
)
port map (
IA => CU_state_timer_not0001_inv_LOGIC_ZERO_3654,
IB => CU_state_timer_not0001_inv_CYMUXF2_3655,
SEL => CU_state_timer_not0001_inv_CYSELG_3648,
O => CU_state_timer_not0001_inv_CYMUXG2_3656
);
CU_state_timer_not0001_inv_CYSELG : X_BUF
generic map(
LOC => "SLICE_X3Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state_cmp_eq0000_wg_lut(7),
O => CU_state_timer_not0001_inv_CYSELG_3648
);
CU_current_state_cmp_eq0000_wg_lut_6_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y23"
)
port map (
ADR0 => CU_state_timer(28),
ADR1 => CU_state_timer(1),
ADR2 => CU_state_timer(26),
ADR3 => CU_state_timer(27),
O => CU_current_state_cmp_eq0000_wg_lut(6)
);
AC_reg_0_F5USED : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_0_F5MUX_3712,
O => alu_Mmux_result_3_f5
);
AC_reg_0_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y26"
)
port map (
IA => alu_Mmux_result_5_3691,
IB => alu_Mmux_result_4_3710,
SEL => AC_reg_0_BXINV_3703,
O => AC_reg_0_F5MUX_3712
);
AC_reg_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => AC_reg_0_BXINV_3703
);
AC_reg_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_0_GYMUX_3694,
O => AC_reg_0_DYMUX_3695
);
AC_reg_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_0_GYMUX_3694,
O => ULA_output(0)
);
AC_reg_0_GYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_0_F6MUX_3693,
O => AC_reg_0_GYMUX_3694
);
AC_reg_0_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y26"
)
port map (
IA => alu_Mmux_result_4_f5,
IB => alu_Mmux_result_3_f5,
SEL => AC_reg_0_BYINV_3685,
O => AC_reg_0_F6MUX_3693
);
AC_reg_0_BYINV : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => AC_reg_0_BYINV_3685
);
AC_reg_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => AC_reg_0_CLKINV_3683
);
AC_reg_0_CEINV : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => AC_reg_0_CEINV_3682
);
alu_Mmux_result_4_f5_F5USED : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f5_F5MUX_3736,
O => alu_Mmux_result_4_f5
);
alu_Mmux_result_4_f5_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y27"
)
port map (
IA => alu_Mmux_result_6_3726,
IB => alu_Mmux_result_51_3734,
SEL => alu_Mmux_result_4_f5_BXINV_3728,
O => alu_Mmux_result_4_f5_F5MUX_3736
);
alu_Mmux_result_4_f5_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f5_BXINV_3728
);
AC_reg_1_F5USED : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_1_F5MUX_3782,
O => alu_Mmux_result_3_f51
);
AC_reg_1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y30"
)
port map (
IA => alu_Mmux_result_52_3762,
IB => alu_Mmux_result_41_3780,
SEL => AC_reg_1_BXINV_3774,
O => AC_reg_1_F5MUX_3782
);
AC_reg_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => AC_reg_1_BXINV_3774
);
AC_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_1_GYMUX_3765,
O => AC_reg_1_DYMUX_3766
);
AC_reg_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_1_GYMUX_3765,
O => ULA_output(1)
);
AC_reg_1_GYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_1_F6MUX_3764,
O => AC_reg_1_GYMUX_3765
);
AC_reg_1_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y30"
)
port map (
IA => alu_Mmux_result_4_f51,
IB => alu_Mmux_result_3_f51,
SEL => AC_reg_1_BYINV_3756,
O => AC_reg_1_F6MUX_3764
);
AC_reg_1_BYINV : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => AC_reg_1_BYINV_3756
);
AC_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => AC_reg_1_CLKINV_3754
);
AC_reg_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => AC_reg_1_CEINV_3753
);
alu_Mmux_result_4_f51_F5USED : X_BUF
generic map(
LOC => "SLICE_X27Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f51_F5MUX_3806,
O => alu_Mmux_result_4_f51
);
alu_Mmux_result_4_f51_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y31"
)
port map (
IA => alu_Mmux_result_61_3796,
IB => alu_Mmux_result_53_3804,
SEL => alu_Mmux_result_4_f51_BXINV_3798,
O => alu_Mmux_result_4_f51_F5MUX_3806
);
alu_Mmux_result_4_f51_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f51_BXINV_3798
);
alu_Mmux_result_54 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X27Y32"
)
port map (
ADR0 => AC_reg(3),
ADR1 => R_D_M_reg(2),
ADR2 => CU_sel_ula(0),
ADR3 => VCC,
O => alu_Mmux_result_54_3832
);
AC_reg_2_F5USED : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_2_F5MUX_3852,
O => alu_Mmux_result_3_f52
);
AC_reg_2_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y32"
)
port map (
IA => alu_Mmux_result_54_3832,
IB => alu_Mmux_result_42_3850,
SEL => AC_reg_2_BXINV_3844,
O => AC_reg_2_F5MUX_3852
);
AC_reg_2_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => AC_reg_2_BXINV_3844
);
AC_reg_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_2_GYMUX_3835,
O => AC_reg_2_DYMUX_3836
);
AC_reg_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_2_GYMUX_3835,
O => ULA_output(2)
);
AC_reg_2_GYMUX : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_2_F6MUX_3834,
O => AC_reg_2_GYMUX_3835
);
AC_reg_2_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y32"
)
port map (
IA => alu_Mmux_result_4_f52,
IB => alu_Mmux_result_3_f52,
SEL => AC_reg_2_BYINV_3826,
O => AC_reg_2_F6MUX_3834
);
AC_reg_2_BYINV : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => AC_reg_2_BYINV_3826
);
AC_reg_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => AC_reg_2_CLKINV_3824
);
AC_reg_2_CEINV : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => AC_reg_2_CEINV_3823
);
alu_Mmux_result_4_f52_F5USED : X_BUF
generic map(
LOC => "SLICE_X27Y33",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f52_F5MUX_3876,
O => alu_Mmux_result_4_f52
);
alu_Mmux_result_4_f52_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y33"
)
port map (
IA => alu_Mmux_result_62_3866,
IB => alu_Mmux_result_55_3874,
SEL => alu_Mmux_result_4_f52_BXINV_3868,
O => alu_Mmux_result_4_f52_F5MUX_3876
);
alu_Mmux_result_4_f52_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y33",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f52_BXINV_3868
);
alu_Mmux_result_43 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X23Y28"
)
port map (
ADR0 => CU_sel_ula(0),
ADR1 => VCC,
ADR2 => alu_MULTIPLICATION(3),
ADR3 => AC_reg(2),
O => alu_Mmux_result_43_3920
);
AC_reg_3_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_3_F5MUX_3922,
O => alu_Mmux_result_3_f53
);
AC_reg_3_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y28"
)
port map (
IA => alu_Mmux_result_56_3902,
IB => alu_Mmux_result_43_3920,
SEL => AC_reg_3_BXINV_3914,
O => AC_reg_3_F5MUX_3922
);
AC_reg_3_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => AC_reg_3_BXINV_3914
);
AC_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_3_GYMUX_3905,
O => AC_reg_3_DYMUX_3906
);
AC_reg_3_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_3_GYMUX_3905,
O => ULA_output(3)
);
AC_reg_3_GYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_3_F6MUX_3904,
O => AC_reg_3_GYMUX_3905
);
AC_reg_3_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y28"
)
port map (
IA => alu_Mmux_result_4_f53,
IB => alu_Mmux_result_3_f53,
SEL => AC_reg_3_BYINV_3896,
O => AC_reg_3_F6MUX_3904
);
AC_reg_3_BYINV : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => AC_reg_3_BYINV_3896
);
AC_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => AC_reg_3_CLKINV_3894
);
AC_reg_3_CEINV : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => AC_reg_3_CEINV_3893
);
alu_Mmux_result_4_f53_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f53_F5MUX_3946,
O => alu_Mmux_result_4_f53
);
alu_Mmux_result_4_f53_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y29"
)
port map (
IA => alu_Mmux_result_63_3936,
IB => alu_Mmux_result_57_3944,
SEL => alu_Mmux_result_4_f53_BXINV_3938,
O => alu_Mmux_result_4_f53_F5MUX_3946
);
alu_Mmux_result_4_f53_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f53_BXINV_3938
);
AC_reg_4_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_4_F5MUX_3992,
O => alu_Mmux_result_3_f54
);
AC_reg_4_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y32"
)
port map (
IA => alu_Mmux_result_58_3972,
IB => alu_Mmux_result_44_3990,
SEL => AC_reg_4_BXINV_3984,
O => AC_reg_4_F5MUX_3992
);
AC_reg_4_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => AC_reg_4_BXINV_3984
);
AC_reg_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_4_GYMUX_3975,
O => AC_reg_4_DYMUX_3976
);
AC_reg_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_4_GYMUX_3975,
O => ULA_output(4)
);
AC_reg_4_GYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_4_F6MUX_3974,
O => AC_reg_4_GYMUX_3975
);
AC_reg_4_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y32"
)
port map (
IA => alu_Mmux_result_4_f54,
IB => alu_Mmux_result_3_f54,
SEL => AC_reg_4_BYINV_3966,
O => AC_reg_4_F6MUX_3974
);
AC_reg_4_BYINV : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => AC_reg_4_BYINV_3966
);
AC_reg_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => AC_reg_4_CLKINV_3964
);
AC_reg_4_CEINV : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => AC_reg_4_CEINV_3963
);
alu_Mmux_result_59 : X_LUT4
generic map(
INIT => X"33FC",
LOC => "SLICE_X23Y33"
)
port map (
ADR0 => VCC,
ADR1 => CU_sel_ula(0),
ADR2 => R_D_M_reg(4),
ADR3 => AC_reg(4),
O => alu_Mmux_result_59_4014
);
alu_Mmux_result_4_f54_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y33",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f54_F5MUX_4016,
O => alu_Mmux_result_4_f54
);
alu_Mmux_result_4_f54_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y33"
)
port map (
IA => alu_Mmux_result_64_4006,
IB => alu_Mmux_result_59_4014,
SEL => alu_Mmux_result_4_f54_BXINV_4008,
O => alu_Mmux_result_4_f54_F5MUX_4016
);
alu_Mmux_result_4_f54_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y33",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f54_BXINV_4008
);
alu_Mmux_result_64 : X_LUT4
generic map(
INIT => X"B830",
LOC => "SLICE_X23Y33"
)
port map (
ADR0 => R_D_M_reg(4),
ADR1 => CU_sel_ula(0),
ADR2 => alu_result_addsub0000(4),
ADR3 => AC_reg(4),
O => alu_Mmux_result_64_4006
);
AC_reg_5_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_5_F5MUX_4062,
O => alu_Mmux_result_3_f55
);
AC_reg_5_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y30"
)
port map (
IA => alu_Mmux_result_510_4042,
IB => alu_Mmux_result_45_4060,
SEL => AC_reg_5_BXINV_4054,
O => AC_reg_5_F5MUX_4062
);
AC_reg_5_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => AC_reg_5_BXINV_4054
);
AC_reg_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_5_GYMUX_4045,
O => AC_reg_5_DYMUX_4046
);
AC_reg_5_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_5_GYMUX_4045,
O => ULA_output(5)
);
AC_reg_5_GYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_5_F6MUX_4044,
O => AC_reg_5_GYMUX_4045
);
AC_reg_5_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y30"
)
port map (
IA => alu_Mmux_result_4_f55,
IB => alu_Mmux_result_3_f55,
SEL => AC_reg_5_BYINV_4036,
O => AC_reg_5_F6MUX_4044
);
AC_reg_5_BYINV : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => AC_reg_5_BYINV_4036
);
AC_reg_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => AC_reg_5_CLKINV_4034
);
AC_reg_5_CEINV : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => AC_reg_5_CEINV_4033
);
alu_Mmux_result_4_f55_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y31",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f55_F5MUX_4086,
O => alu_Mmux_result_4_f55
);
alu_Mmux_result_4_f55_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y31"
)
port map (
IA => alu_Mmux_result_65_4076,
IB => alu_Mmux_result_511_4084,
SEL => alu_Mmux_result_4_f55_BXINV_4078,
O => alu_Mmux_result_4_f55_F5MUX_4086
);
alu_Mmux_result_4_f55_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f55_BXINV_4078
);
alu_Mmux_result_512 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X25Y34"
)
port map (
ADR0 => R_D_M_reg(6),
ADR1 => NZ_data_N_1484,
ADR2 => CU_sel_ula(0),
ADR3 => VCC,
O => alu_Mmux_result_512_4112
);
AC_reg_6_F5USED : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_6_F5MUX_4132,
O => alu_Mmux_result_3_f56
);
AC_reg_6_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y34"
)
port map (
IA => alu_Mmux_result_512_4112,
IB => alu_Mmux_result_46_4130,
SEL => AC_reg_6_BXINV_4124,
O => AC_reg_6_F5MUX_4132
);
AC_reg_6_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => AC_reg_6_BXINV_4124
);
AC_reg_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_6_GYMUX_4115,
O => AC_reg_6_DYMUX_4116
);
AC_reg_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_6_GYMUX_4115,
O => ULA_output(6)
);
AC_reg_6_GYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => AC_reg_6_F6MUX_4114,
O => AC_reg_6_GYMUX_4115
);
AC_reg_6_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y34"
)
port map (
IA => alu_Mmux_result_4_f56,
IB => alu_Mmux_result_3_f56,
SEL => AC_reg_6_BYINV_4106,
O => AC_reg_6_F6MUX_4114
);
AC_reg_6_BYINV : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => AC_reg_6_BYINV_4106
);
AC_reg_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => AC_reg_6_CLKINV_4104
);
AC_reg_6_CEINV : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => AC_reg_6_CEINV_4103
);
alu_Mmux_result_4_f56_F5USED : X_BUF
generic map(
LOC => "SLICE_X25Y35",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f56_F5MUX_4156,
O => alu_Mmux_result_4_f56
);
alu_Mmux_result_4_f56_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y35"
)
port map (
IA => alu_Mmux_result_66_4146,
IB => alu_Mmux_result_513_4154,
SEL => alu_Mmux_result_4_f56_BXINV_4148,
O => alu_Mmux_result_4_f56_F5MUX_4156
);
alu_Mmux_result_4_f56_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y35",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f56_BXINV_4148
);
NZ_data_N_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_F5MUX_4202,
O => alu_Mmux_result_3_f57
);
NZ_data_N_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y34"
)
port map (
IA => alu_Mmux_result_514_4182,
IB => alu_Mmux_result_47_4200,
SEL => NZ_data_N_BXINV_4194,
O => NZ_data_N_F5MUX_4202
);
NZ_data_N_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => NZ_data_N_BXINV_4194
);
NZ_data_N_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_GYMUX_4185,
O => NZ_data_N_DYMUX_4186
);
NZ_data_N_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_GYMUX_4185,
O => ULA_N
);
NZ_data_N_GYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_F6MUX_4184,
O => NZ_data_N_GYMUX_4185
);
NZ_data_N_F6MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y34"
)
port map (
IA => alu_Mmux_result_4_f57,
IB => alu_Mmux_result_3_f57,
SEL => NZ_data_N_BYINV_4175,
O => NZ_data_N_F6MUX_4184
);
NZ_data_N_BYINV : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(2),
O => NZ_data_N_BYINV_4175
);
NZ_data_N_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => NZ_data_N_CLKINV_4173
);
NZ_data_N_CEINV : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => NZ_data_N_CEINV_4172
);
NZ_data_N : X_FF
generic map(
LOC => "SLICE_X23Y34",
INIT => '0'
)
port map (
I => NZ_data_N_DYMUX_4186,
CE => NZ_data_N_CEINV_4172,
CLK => NZ_data_N_CLKINV_4173,
SET => GND,
RST => NZ_data_N_FFY_RSTAND_4192,
O => NZ_data_N_1484
);
NZ_data_N_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X23Y34",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => NZ_data_N_FFY_RSTAND_4192
);
alu_Mmux_result_4_f57_F5USED : X_BUF
generic map(
LOC => "SLICE_X23Y35",
PATHPULSE => 638 ps
)
port map (
I => alu_Mmux_result_4_f57_F5MUX_4226,
O => alu_Mmux_result_4_f57
);
alu_Mmux_result_4_f57_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y35"
)
port map (
IA => alu_Mmux_result_67_4216,
IB => alu_Mmux_result_515_4224,
SEL => alu_Mmux_result_4_f57_BXINV_4218,
O => alu_Mmux_result_4_f57_F5MUX_4226
);
alu_Mmux_result_4_f57_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y35",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula(1),
O => alu_Mmux_result_4_f57_BXINV_4218
);
clk_BUFGP_IBUFG : X_BUF
generic map(
LOC => "IPAD12",
PATHPULSE => 638 ps
)
port map (
I => clk,
O => clk_INBUF
);
enable_IBUF : X_BUF
generic map(
LOC => "PAD47",
PATHPULSE => 638 ps
)
port map (
I => enable,
O => enable_INBUF
);
debug_out_OBUF : X_OBUF
generic map(
LOC => "PAD48"
)
port map (
I => debug_out_O,
O => debug_out
);
rst_IBUF : X_BUF
generic map(
LOC => "PAD49",
PATHPULSE => 638 ps
)
port map (
I => rst,
O => rst_INBUF
);
clk_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX_X2Y10"
)
port map (
I0 => clk_BUFGP_BUFG_I0_INV,
I1 => GND,
S => clk_BUFGP_BUFG_S_INVNOT,
O => clk_BUFGP
);
clk_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX_X2Y10",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => clk_BUFGP_BUFG_S_INVNOT
);
clk_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX_X2Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_INBUF,
O => clk_BUFGP_BUFG_I0_INV
);
alu_Mmult_MULTIPLICATION_mult0000_RSTPINV : X_BUF
generic map(
LOC => "MULT18X18_X0Y2",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_Mmult_MULTIPLICATION_mult0000_RSTP_INT
);
alu_Mmult_MULTIPLICATION_mult0000_RSTBINV : X_BUF
generic map(
LOC => "MULT18X18_X0Y2",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_Mmult_MULTIPLICATION_mult0000_RSTB_INT
);
alu_Mmult_MULTIPLICATION_mult0000_RSTAINV : X_BUF
generic map(
LOC => "MULT18X18_X0Y2",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_Mmult_MULTIPLICATION_mult0000_RSTA_INT
);
alu_Mmult_MULTIPLICATION_mult0000_CLKINV : X_BUF
generic map(
LOC => "MULT18X18_X0Y2",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_Mmult_MULTIPLICATION_mult0000_CLK_INT
);
alu_Mmult_MULTIPLICATION_mult0000_CEPINV : X_BUF
generic map(
LOC => "MULT18X18_X0Y2",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_Mmult_MULTIPLICATION_mult0000_CEP_INT
);
alu_Mmult_MULTIPLICATION_mult0000_CEBINV : X_BUF
generic map(
LOC => "MULT18X18_X0Y2",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_Mmult_MULTIPLICATION_mult0000_CEB_INT
);
alu_Mmult_MULTIPLICATION_mult0000_CEAINV : X_BUF
generic map(
LOC => "MULT18X18_X0Y2",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => alu_Mmult_MULTIPLICATION_mult0000_CEA_INT
);
alu_Mmult_MULTIPLICATION_mult0000 : X_MULT18X18SIO
generic map(
AREG => 0,
BREG => 0,
PREG => 0,
B_INPUT => "DIRECT",
LOC => "MULT18X18_X0Y2"
)
port map (
CEA => alu_Mmult_MULTIPLICATION_mult0000_CEA_INT,
CEB => alu_Mmult_MULTIPLICATION_mult0000_CEB_INT,
CEP => alu_Mmult_MULTIPLICATION_mult0000_CEP_INT,
CLK => alu_Mmult_MULTIPLICATION_mult0000_CLK_INT,
RSTA => alu_Mmult_MULTIPLICATION_mult0000_RSTA_INT,
RSTB => alu_Mmult_MULTIPLICATION_mult0000_RSTB_INT,
RSTP => alu_Mmult_MULTIPLICATION_mult0000_RSTP_INT,
A(17) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(17),
A(16) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(16),
A(15) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(15),
A(14) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(14),
A(13) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(13),
A(12) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(12),
A(11) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(11),
A(10) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(10),
A(9) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(9),
A(8) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(8),
A(7) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(7),
A(6) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(6),
A(5) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(5),
A(4) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(4),
A(3) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(3),
A(2) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(2),
A(1) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(1),
A(0) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(0),
B(17) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(17),
B(16) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(16),
B(15) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(15),
B(14) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(14),
B(13) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(13),
B(12) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(12),
B(11) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(11),
B(10) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(10),
B(9) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(9),
B(8) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(8),
B(7) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(7),
B(6) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(6),
B(5) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(5),
B(4) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(4),
B(3) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(3),
B(2) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(2),
B(1) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(1),
B(0) => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(0),
BCIN(17) => alu_Mmult_MULTIPLICATION_mult0000_BCIN17,
BCIN(16) => alu_Mmult_MULTIPLICATION_mult0000_BCIN16,
BCIN(15) => alu_Mmult_MULTIPLICATION_mult0000_BCIN15,
BCIN(14) => alu_Mmult_MULTIPLICATION_mult0000_BCIN14,
BCIN(13) => alu_Mmult_MULTIPLICATION_mult0000_BCIN13,
BCIN(12) => alu_Mmult_MULTIPLICATION_mult0000_BCIN12,
BCIN(11) => alu_Mmult_MULTIPLICATION_mult0000_BCIN11,
BCIN(10) => alu_Mmult_MULTIPLICATION_mult0000_BCIN10,
BCIN(9) => alu_Mmult_MULTIPLICATION_mult0000_BCIN9,
BCIN(8) => alu_Mmult_MULTIPLICATION_mult0000_BCIN8,
BCIN(7) => alu_Mmult_MULTIPLICATION_mult0000_BCIN7,
BCIN(6) => alu_Mmult_MULTIPLICATION_mult0000_BCIN6,
BCIN(5) => alu_Mmult_MULTIPLICATION_mult0000_BCIN5,
BCIN(4) => alu_Mmult_MULTIPLICATION_mult0000_BCIN4,
BCIN(3) => alu_Mmult_MULTIPLICATION_mult0000_BCIN3,
BCIN(2) => alu_Mmult_MULTIPLICATION_mult0000_BCIN2,
BCIN(1) => alu_Mmult_MULTIPLICATION_mult0000_BCIN1,
BCIN(0) => alu_Mmult_MULTIPLICATION_mult0000_BCIN0,
P(35) => alu_Mmult_MULTIPLICATION_mult0000_P35,
P(34) => alu_Mmult_MULTIPLICATION_mult0000_P34,
P(33) => alu_Mmult_MULTIPLICATION_mult0000_P33,
P(32) => alu_Mmult_MULTIPLICATION_mult0000_P32,
P(31) => alu_Mmult_MULTIPLICATION_mult0000_P31,
P(30) => alu_Mmult_MULTIPLICATION_mult0000_P30,
P(29) => alu_Mmult_MULTIPLICATION_mult0000_P29,
P(28) => alu_Mmult_MULTIPLICATION_mult0000_P28,
P(27) => alu_Mmult_MULTIPLICATION_mult0000_P27,
P(26) => alu_Mmult_MULTIPLICATION_mult0000_P26,
P(25) => alu_Mmult_MULTIPLICATION_mult0000_P25,
P(24) => alu_Mmult_MULTIPLICATION_mult0000_P24,
P(23) => alu_Mmult_MULTIPLICATION_mult0000_P23,
P(22) => alu_Mmult_MULTIPLICATION_mult0000_P22,
P(21) => alu_Mmult_MULTIPLICATION_mult0000_P21,
P(20) => alu_Mmult_MULTIPLICATION_mult0000_P20,
P(19) => alu_Mmult_MULTIPLICATION_mult0000_P19,
P(18) => alu_Mmult_MULTIPLICATION_mult0000_P18,
P(17) => alu_Mmult_MULTIPLICATION_mult0000_P17,
P(16) => alu_Mmult_MULTIPLICATION_mult0000_P16,
P(15) => alu_Mmult_MULTIPLICATION_mult0000_P15,
P(14) => alu_Mmult_MULTIPLICATION_mult0000_P14,
P(13) => alu_Mmult_MULTIPLICATION_mult0000_P13,
P(12) => alu_Mmult_MULTIPLICATION_mult0000_P12,
P(11) => alu_Mmult_MULTIPLICATION_mult0000_P11,
P(10) => alu_Mmult_MULTIPLICATION_mult0000_P10,
P(9) => alu_Mmult_MULTIPLICATION_mult0000_P9,
P(8) => alu_Mmult_MULTIPLICATION_mult0000_P8,
P(7) => alu_MULTIPLICATION_mult0000(7),
P(6) => alu_MULTIPLICATION_mult0000(6),
P(5) => alu_MULTIPLICATION_mult0000(5),
P(4) => alu_MULTIPLICATION_mult0000(4),
P(3) => alu_MULTIPLICATION_mult0000(3),
P(2) => alu_MULTIPLICATION_mult0000(2),
P(1) => alu_MULTIPLICATION_mult0000(1),
P(0) => alu_MULTIPLICATION_mult0000(0),
BCOUT(17) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT17,
BCOUT(16) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT16,
BCOUT(15) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT15,
BCOUT(14) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT14,
BCOUT(13) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT13,
BCOUT(12) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT12,
BCOUT(11) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT11,
BCOUT(10) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT10,
BCOUT(9) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT9,
BCOUT(8) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT8,
BCOUT(7) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT7,
BCOUT(6) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT6,
BCOUT(5) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT5,
BCOUT(4) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT4,
BCOUT(3) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT3,
BCOUT(2) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT2,
BCOUT(1) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT1,
BCOUT(0) => alu_Mmult_MULTIPLICATION_mult0000_BCOUT0
);
MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram : X_RAMB16_S36_S36
generic map(
INIT_A => X"000000000",
INIT_B => X"000000000",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
SIM_COLLISION_CHECK => "ALL",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0101000000020101010000000002010000030000000200030002000000000000",
INIT_01 => X"0303000000000303020100000303000000000300000200030102000000020100",
INIT_02 => X"0201000000020101000200000303000000010100020200000002010200030000",
INIT_03 => X"0303000000020102000300000001030202020000000201020003000000010302",
INIT_04 => X"0000000000000201010000000000020000000100000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
LOC => "RAMB16_X0Y3",
SETUP_ALL => 227 ps,
SETUP_READ_FIRST => 227 ps
)
port map (
CLKA => clk_BUFGP,
CLKB => clk_BUFGP,
ENA => '1',
ENB => '1',
SSRA => '0',
SSRB => '0',
WEA => CU_wr_enable_mem(0),
WEB => '0',
ADDRA(8) => '0',
ADDRA(7) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_7_Q,
ADDRA(6) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_6_Q,
ADDRA(5) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_5_Q,
ADDRA(4) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_4_Q,
ADDRA(3) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_3_Q,
ADDRA(2) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_2_Q,
ADDRA(1) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_1_Q,
ADDRA(0) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_0_Q,
ADDRB(8) => '0',
ADDRB(7) => '0',
ADDRB(6) => '0',
ADDRB(5) => '0',
ADDRB(4) => '0',
ADDRB(3) => '0',
ADDRB(2) => '0',
ADDRB(1) => '0',
ADDRB(0) => '0',
DIA(31) => '0',
DIA(30) => '0',
DIA(29) => '0',
DIA(28) => '0',
DIA(27) => '0',
DIA(26) => '0',
DIA(25) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_25_Q,
DIA(24) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_24_Q,
DIA(23) => '0',
DIA(22) => '0',
DIA(21) => '0',
DIA(20) => '0',
DIA(19) => '0',
DIA(18) => '0',
DIA(17) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_17_Q,
DIA(16) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_16_Q,
DIA(15) => '0',
DIA(14) => '0',
DIA(13) => '0',
DIA(12) => '0',
DIA(11) => '0',
DIA(10) => '0',
DIA(9) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_9_Q,
DIA(8) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_8_Q,
DIA(7) => '0',
DIA(6) => '0',
DIA(5) => '0',
DIA(4) => '0',
DIA(3) => '0',
DIA(2) => '0',
DIA(1) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_1_Q,
DIA(0) =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_0_Q,
DIPA(3) => '0',
DIPA(2) => '0',
DIPA(1) => '0',
DIPA(0) => '0',
DIB(31) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB31,
DIB(30) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB30,
DIB(29) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB29,
DIB(28) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB28,
DIB(27) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB27,
DIB(26) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB26,
DIB(25) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB25,
DIB(24) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB24,
DIB(23) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB23,
DIB(22) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB22,
DIB(21) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB21,
DIB(20) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB20,
DIB(19) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB19,
DIB(18) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB18,
DIB(17) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB17,
DIB(16) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB16,
DIB(15) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB15,
DIB(14) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB14,
DIB(13) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB13,
DIB(12) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB12,
DIB(11) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB11,
DIB(10) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB10,
DIB(9) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB9,
DIB(8) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB8,
DIB(7) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB7,
DIB(6) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB6,
DIB(5) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB5,
DIB(4) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB4,
DIB(3) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB3,
DIB(2) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB2,
DIB(1) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB1,
DIB(0) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIB0,
DIPB(3) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB3,
DIPB(2) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB2,
DIPB(1) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB1,
DIPB(0) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIPB0,
DOA(31) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA31,
DOA(30) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA30,
DOA(29) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA29,
DOA(28) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA28,
DOA(27) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA27,
DOA(26) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA26,
DOA(25) => MEM_output(7),
DOA(24) => MEM_output(6),
DOA(23) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA23,
DOA(22) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA22,
DOA(21) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA21,
DOA(20) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA20,
DOA(19) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA19,
DOA(18) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA18,
DOA(17) => MEM_output(5),
DOA(16) => MEM_output(4),
DOA(15) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA15,
DOA(14) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA14,
DOA(13) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA13,
DOA(12) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA12,
DOA(11) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA11,
DOA(10) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA10,
DOA(9) => MEM_output(3),
DOA(8) => MEM_output(2),
DOA(7) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA7,
DOA(6) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA6,
DOA(5) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA5,
DOA(4) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA4,
DOA(3) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA3,
DOA(2) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOA2,
DOA(1) => MEM_output(1),
DOA(0) => MEM_output(0),
DOPA(3) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA3,
DOPA(2) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA2,
DOPA(1) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA1,
DOPA(0) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPA0,
DOB(31) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB31,
DOB(30) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB30,
DOB(29) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB29,
DOB(28) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB28,
DOB(27) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB27,
DOB(26) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB26,
DOB(25) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB25,
DOB(24) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB24,
DOB(23) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB23,
DOB(22) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB22,
DOB(21) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB21,
DOB(20) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB20,
DOB(19) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB19,
DOB(18) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB18,
DOB(17) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB17,
DOB(16) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB16,
DOB(15) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB15,
DOB(14) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB14,
DOB(13) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB13,
DOB(12) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB12,
DOB(11) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB11,
DOB(10) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB10,
DOB(9) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB9,
DOB(8) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB8,
DOB(7) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB7,
DOB(6) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB6,
DOB(5) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB5,
DOB(4) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB4,
DOB(3) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB3,
DOB(2) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB2,
DOB(1) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB1,
DOB(0) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOB0,
DOPB(3) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB3,
DOPB(2) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB2,
DOPB(1) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB1,
DOPB(0) => MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DOPB0
);
CU_PC_inc_DXMUX : X_BUF
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_PC_inc_F5MUX_4577,
O => CU_PC_inc_DXMUX_4579
);
CU_PC_inc_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y12"
)
port map (
IA => CU_PC_inc_mux00002_4568,
IB => CU_PC_inc_mux00001_4575,
SEL => CU_PC_inc_BXINV_4570,
O => CU_PC_inc_F5MUX_4577
);
CU_PC_inc_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_PC_inc_1525,
O => CU_PC_inc_BXINV_4570
);
CU_PC_inc_CLKINV : X_BUF
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_PC_inc_CLKINV_4562
);
CU_PC_inc_CEINV : X_INV
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_PC_inc_CEINVNOT
);
CU_loadREM_DXMUX : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_loadREM_F5MUX_4611,
O => CU_loadREM_DXMUX_4613
);
CU_loadREM_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y12"
)
port map (
IA => CU_loadREM_mux00002_4602,
IB => CU_loadREM_mux00001_4609,
SEL => CU_loadREM_BXINV_4604,
O => CU_loadREM_F5MUX_4611
);
CU_loadREM_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_N18_0,
O => CU_loadREM_BXINV_4604
);
CU_loadREM_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_loadREM_CLKINV_4595
);
CU_next_state_mux0012_13_38_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_13_38_F5MUX_4643,
O => CU_next_state_mux0012_13_38
);
CU_next_state_mux0012_13_38_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y10"
)
port map (
IA => CU_next_state_mux0012_13_382_4632,
IB => CU_next_state_mux0012_13_381_4641,
SEL => CU_next_state_mux0012_13_38_BXINV_4634,
O => CU_next_state_mux0012_13_38_F5MUX_4643
);
CU_next_state_mux0012_13_38_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_current_state(0),
O => CU_next_state_mux0012_13_38_BXINV_4634
);
CU_sel_ula_and0000_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_ula_and0000,
O => CU_sel_ula_and0000_0
);
CU_sel_ula_and0000_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_N7_pack_1,
O => CU_N7
);
CU_next_state_mux0012_1_1122 : X_LUT4
generic map(
INIT => X"712A",
LOC => "SLICE_X22Y12"
)
port map (
ADR0 => RI_reg(6),
ADR1 => RI_reg(7),
ADR2 => RI_reg(4),
ADR3 => RI_reg(5),
O => CU_N7_pack_1
);
CU_next_state_mux0012_0_8_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_0_8_4690,
O => CU_next_state_mux0012_0_8_0
);
CU_next_state_mux0012_0_8_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y10",
PATHPULSE => 638 ps
)
port map (
I => exec_NOT_pack_1,
O => exec_NOT
);
CU_N9_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_N9,
O => CU_N9_0
);
CU_N9_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => exec_STA_pack_1,
O => exec_STA
);
CU_next_state_mux0012_4_11_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_4_11_4738,
O => CU_next_state_mux0012_4_11_0
);
CU_next_state_mux0012_4_11_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => exec_JN_pack_1,
O => exec_JN
);
alu_Z_cmp_eq000028_SW0 : X_LUT4
generic map(
INIT => X"FFFE",
LOC => "SLICE_X22Y30"
)
port map (
ADR0 => ULA_output(2),
ADR1 => ULA_output(5),
ADR2 => ULA_output(3),
ADR3 => ULA_output(4),
O => alu_Z_cmp_eq000028_SW0_O_pack_1
);
NZ_data_Z_DXMUX : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => ULA_Z,
O => NZ_data_Z_DXMUX_4771
);
NZ_data_Z_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => alu_Z_cmp_eq000028_SW0_O_pack_1,
O => alu_Z_cmp_eq000028_SW0_O
);
NZ_data_Z_CLKINV : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => NZ_data_Z_CLKINV_4755
);
NZ_data_Z_CEINV : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_1652,
O => NZ_data_Z_CEINV_4754
);
N14_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y12",
PATHPULSE => 638 ps
)
port map (
I => N14,
O => N14_0
);
N14_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y12",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_or0001_pack_1,
O => CU_next_state_or0001
);
CU_next_state_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X20Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(12),
O => CU_next_state_1_DXMUX_4831
);
CU_next_state_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_12_22_O_pack_2,
O => CU_next_state_mux0012_12_22_O
);
CU_next_state_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X20Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_1_CLKINV_4814
);
CU_next_state_mux0012_7_11_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_7_11_4859,
O => CU_next_state_mux0012_7_11_0
);
CU_next_state_mux0012_7_11_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y19",
PATHPULSE => 638 ps
)
port map (
I => exec_JZ_pack_1,
O => exec_JZ
);
CU_loadRDM_mux000015_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_loadRDM_mux000015_4883,
O => CU_loadRDM_mux000015_0
);
CU_loadRDM_mux000015_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_N10_pack_1,
O => CU_N10
);
CU_next_state_mux0012_4_23_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y11",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_4_23,
O => CU_next_state_mux0012_4_23_0
);
CU_next_state_mux0012_4_23_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y11",
PATHPULSE => 638 ps
)
port map (
I => exec_HLT_pack_1,
O => exec_HLT
);
CU_next_state_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(13),
O => CU_next_state_0_DXMUX_4938
);
CU_next_state_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012_13_56_O_pack_2,
O => CU_next_state_mux0012_13_56_O
);
CU_next_state_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_0_CLKINV_4922
);
CU_sel_mux_RDM_DXMUX : X_BUF
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_mux_RDM_mux0000,
O => CU_sel_mux_RDM_DXMUX_4977
);
CU_sel_mux_RDM_DYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_sel_mux0000,
O => CU_sel_mux_RDM_DYMUX_4965
);
CU_sel_mux_RDM_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_sel_mux_RDM_CLKINV_4957
);
CU_sel_mux_RDM_CEINV : X_INV
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_sel_mux_RDM_CEINVNOT
);
R_E_M_reg_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(1),
O => R_E_M_reg_1_DXMUX_5020
);
R_E_M_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(0),
O => R_E_M_reg_1_DYMUX_5004
);
R_E_M_reg_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_E_M_reg_1_SRINV_4995
);
R_E_M_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_E_M_reg_1_CLKINV_4994
);
R_E_M_reg_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_loadREM_1685,
O => R_E_M_reg_1_CEINV_4993
);
R_E_M_reg_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(3),
O => R_E_M_reg_3_DXMUX_5066
);
R_E_M_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(2),
O => R_E_M_reg_3_DYMUX_5050
);
R_E_M_reg_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_E_M_reg_3_SRINV_5041
);
R_E_M_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_E_M_reg_3_CLKINV_5040
);
R_E_M_reg_3_CEINV : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_loadREM_1685,
O => R_E_M_reg_3_CEINV_5039
);
R_E_M_reg_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(5),
O => R_E_M_reg_5_DXMUX_5112
);
R_E_M_reg_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(4),
O => R_E_M_reg_5_DYMUX_5096
);
R_E_M_reg_5_SRINV : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_E_M_reg_5_SRINV_5087
);
R_E_M_reg_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_E_M_reg_5_CLKINV_5086
);
R_E_M_reg_5_CEINV : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_loadREM_1685,
O => R_E_M_reg_5_CEINV_5085
);
R_E_M_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(7),
O => R_E_M_reg_7_DXMUX_5158
);
R_E_M_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => MPX_output(6),
O => R_E_M_reg_7_DYMUX_5142
);
R_E_M_reg_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => R_E_M_reg_7_SRINV_5133
);
R_E_M_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => R_E_M_reg_7_CLKINV_5132
);
R_E_M_reg_7_CEINV : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_loadREM_1685,
O => R_E_M_reg_7_CEINV_5131
);
CU_state_timer_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X0Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_1,
O => CU_state_timer_1_DXMUX_5200
);
CU_state_timer_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_0,
O => CU_state_timer_1_DYMUX_5185
);
CU_state_timer_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X0Y18",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_1_SRINV_5175
);
CU_state_timer_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_1_CLKINV_5174
);
CU_state_timer_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_3,
O => CU_state_timer_3_DXMUX_5242
);
CU_state_timer_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y19",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_2,
O => CU_state_timer_3_DYMUX_5226
);
CU_state_timer_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y19",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_3_SRINV_5216
);
CU_state_timer_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y19",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_3_CLKINV_5215
);
CU_state_timer_11_DXMUX : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_11,
O => CU_state_timer_11_DXMUX_5284
);
CU_state_timer_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_10,
O => CU_state_timer_11_DYMUX_5268
);
CU_state_timer_11_SRINV : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_11_SRINV_5258
);
CU_state_timer_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_11_CLKINV_5257
);
CU_state_timer_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_5,
O => CU_state_timer_5_DXMUX_5326
);
CU_state_timer_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_4,
O => CU_state_timer_5_DYMUX_5310
);
CU_state_timer_5_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_5_SRINV_5300
);
CU_state_timer_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_5_CLKINV_5299
);
CU_state_timer_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X0Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_13,
O => CU_state_timer_13_DXMUX_5368
);
CU_state_timer_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_12,
O => CU_state_timer_13_DYMUX_5352
);
CU_state_timer_13_SRINV : X_BUF
generic map(
LOC => "SLICE_X0Y22",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_13_SRINV_5342
);
CU_state_timer_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_13_CLKINV_5341
);
CU_state_timer_21_DXMUX : X_BUF
generic map(
LOC => "SLICE_X0Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_21,
O => CU_state_timer_21_DXMUX_5410
);
CU_state_timer_21_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y23",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_20,
O => CU_state_timer_21_DYMUX_5394
);
CU_state_timer_21_SRINV : X_BUF
generic map(
LOC => "SLICE_X0Y23",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_21_SRINV_5384
);
CU_state_timer_21_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y23",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_21_CLKINV_5383
);
CU_state_timer_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_7,
O => CU_state_timer_7_DXMUX_5452
);
CU_state_timer_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_6,
O => CU_state_timer_7_DYMUX_5436
);
CU_state_timer_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_7_SRINV_5426
);
CU_state_timer_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_7_CLKINV_5425
);
CU_state_timer_15_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_15,
O => CU_state_timer_15_DXMUX_5494
);
CU_state_timer_15_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_14,
O => CU_state_timer_15_DYMUX_5478
);
CU_state_timer_15_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_15_SRINV_5468
);
CU_state_timer_15_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_15_CLKINV_5467
);
CU_state_timer_23_DXMUX : X_BUF
generic map(
LOC => "SLICE_X0Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_23,
O => CU_state_timer_23_DXMUX_5536
);
CU_state_timer_23_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y24",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_22,
O => CU_state_timer_23_DYMUX_5520
);
CU_state_timer_23_SRINV : X_BUF
generic map(
LOC => "SLICE_X0Y24",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_23_SRINV_5510
);
CU_state_timer_23_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y24",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_23_CLKINV_5509
);
CU_state_timer_31_DXMUX : X_BUF
generic map(
LOC => "SLICE_X0Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_31,
O => CU_state_timer_31_DXMUX_5578
);
CU_state_timer_31_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_30,
O => CU_state_timer_31_DYMUX_5562
);
CU_state_timer_31_SRINV : X_BUF
generic map(
LOC => "SLICE_X0Y26",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_31_SRINV_5552
);
CU_state_timer_31_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y26",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_31_CLKINV_5551
);
CU_state_timer_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_9,
O => CU_state_timer_9_DXMUX_5620
);
CU_state_timer_9_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y18",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_8,
O => CU_state_timer_9_DYMUX_5604
);
CU_state_timer_9_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y18",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_9_SRINV_5594
);
CU_state_timer_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_9_CLKINV_5593
);
CU_state_timer_17_DXMUX : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_17,
O => CU_state_timer_17_DXMUX_5662
);
CU_state_timer_17_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_16,
O => CU_state_timer_17_DYMUX_5646
);
CU_state_timer_17_SRINV : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_17_SRINV_5636
);
CU_state_timer_17_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_17_CLKINV_5635
);
CU_state_timer_25_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X3Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_state_timer_25_SRINV_5678,
O => CU_state_timer_25_FFX_RST
);
CU_state_timer_25 : X_FF
generic map(
LOC => "SLICE_X3Y31",
INIT => '0'
)
port map (
I => CU_state_timer_25_DXMUX_5704,
CE => VCC,
CLK => CU_state_timer_25_CLKINV_5677,
SET => GND,
RST => CU_state_timer_25_FFX_RST,
O => CU_state_timer(25)
);
CU_Mcount_state_timer_eqn_241 : X_LUT4
generic map(
INIT => X"0C0C",
LOC => "SLICE_X3Y31"
)
port map (
ADR0 => VCC,
ADR1 => CU_Result(24),
ADR2 => CU_state_timer_not0001_inv,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_24
);
CU_state_timer_25_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X3Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_state_timer_25_SRINV_5678,
O => CU_state_timer_25_FFY_RST
);
CU_state_timer_24 : X_FF
generic map(
LOC => "SLICE_X3Y31",
INIT => '0'
)
port map (
I => CU_state_timer_25_DYMUX_5688,
CE => VCC,
CLK => CU_state_timer_25_CLKINV_5677,
SET => GND,
RST => CU_state_timer_25_FFY_RST,
O => CU_state_timer(24)
);
CU_state_timer_25_DXMUX : X_BUF
generic map(
LOC => "SLICE_X3Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_25,
O => CU_state_timer_25_DXMUX_5704
);
CU_state_timer_25_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y31",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_24,
O => CU_state_timer_25_DYMUX_5688
);
CU_state_timer_25_SRINV : X_BUF
generic map(
LOC => "SLICE_X3Y31",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_25_SRINV_5678
);
CU_state_timer_25_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y31",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_25_CLKINV_5677
);
CU_state_timer_19_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X2Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_state_timer_19_SRINV_5720,
O => CU_state_timer_19_FFY_RST
);
CU_state_timer_18 : X_FF
generic map(
LOC => "SLICE_X2Y22",
INIT => '0'
)
port map (
I => CU_state_timer_19_DYMUX_5730,
CE => VCC,
CLK => CU_state_timer_19_CLKINV_5719,
SET => GND,
RST => CU_state_timer_19_FFY_RST,
O => CU_state_timer(18)
);
CU_Mcount_state_timer_eqn_191 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X2Y22"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(19),
O => CU_Mcount_state_timer_eqn_19
);
CU_state_timer_19_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X2Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_state_timer_19_SRINV_5720,
O => CU_state_timer_19_FFX_RST
);
CU_state_timer_19 : X_FF
generic map(
LOC => "SLICE_X2Y22",
INIT => '0'
)
port map (
I => CU_state_timer_19_DXMUX_5746,
CE => VCC,
CLK => CU_state_timer_19_CLKINV_5719,
SET => GND,
RST => CU_state_timer_19_FFX_RST,
O => CU_state_timer(19)
);
CU_state_timer_19_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_19,
O => CU_state_timer_19_DXMUX_5746
);
CU_state_timer_19_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y22",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_18,
O => CU_state_timer_19_DYMUX_5730
);
CU_state_timer_19_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y22",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_19_SRINV_5720
);
CU_state_timer_19_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_19_CLKINV_5719
);
CU_Mcount_state_timer_eqn_181 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X2Y22"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(18),
O => CU_Mcount_state_timer_eqn_18
);
CU_Mcount_state_timer_eqn_271 : X_LUT4
generic map(
INIT => X"00F0",
LOC => "SLICE_X2Y25"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_Result(27),
ADR3 => CU_state_timer_not0001_inv,
O => CU_Mcount_state_timer_eqn_27
);
CU_state_timer_27_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_27,
O => CU_state_timer_27_DXMUX_5788
);
CU_state_timer_27_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y25",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_26,
O => CU_state_timer_27_DYMUX_5772
);
CU_state_timer_27_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y25",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_27_SRINV_5762
);
CU_state_timer_27_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y25",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_27_CLKINV_5761
);
CU_Mcount_state_timer_eqn_261 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X2Y25"
)
port map (
ADR0 => VCC,
ADR1 => CU_Result(26),
ADR2 => VCC,
ADR3 => CU_state_timer_not0001_inv,
O => CU_Mcount_state_timer_eqn_26
);
CU_state_timer_29_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X3Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_state_timer_29_SRINV_5804,
O => CU_state_timer_29_FFY_RST
);
CU_state_timer_28 : X_FF
generic map(
LOC => "SLICE_X3Y26",
INIT => '0'
)
port map (
I => CU_state_timer_29_DYMUX_5814,
CE => VCC,
CLK => CU_state_timer_29_CLKINV_5803,
SET => GND,
RST => CU_state_timer_29_FFY_RST,
O => CU_state_timer(28)
);
CU_state_timer_29_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X3Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_state_timer_29_SRINV_5804,
O => CU_state_timer_29_FFX_RST
);
CU_state_timer_29 : X_FF
generic map(
LOC => "SLICE_X3Y26",
INIT => '0'
)
port map (
I => CU_state_timer_29_DXMUX_5830,
CE => VCC,
CLK => CU_state_timer_29_CLKINV_5803,
SET => GND,
RST => CU_state_timer_29_FFX_RST,
O => CU_state_timer(29)
);
CU_state_timer_29_DXMUX : X_BUF
generic map(
LOC => "SLICE_X3Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_29,
O => CU_state_timer_29_DXMUX_5830
);
CU_state_timer_29_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y26",
PATHPULSE => 638 ps
)
port map (
I => CU_Mcount_state_timer_eqn_28,
O => CU_state_timer_29_DYMUX_5814
);
CU_state_timer_29_SRINV : X_BUF
generic map(
LOC => "SLICE_X3Y26",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_state_timer_29_SRINV_5804
);
CU_state_timer_29_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y26",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_state_timer_29_CLKINV_5803
);
CU_Mcount_state_timer_eqn_281 : X_LUT4
generic map(
INIT => X"4444",
LOC => "SLICE_X3Y26"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => CU_Result(28),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_28
);
CU_next_state_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y9",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(10),
O => CU_next_state_3_DXMUX_5872
);
CU_next_state_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y9",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(11),
O => CU_next_state_3_DYMUX_5857
);
CU_next_state_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y9",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_3_SRINV_5848
);
CU_next_state_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y9",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_3_CLKINV_5847
);
CU_next_state_2 : X_FF
generic map(
LOC => "SLICE_X18Y9",
INIT => '0'
)
port map (
I => CU_next_state_3_DYMUX_5857,
CE => VCC,
CLK => CU_next_state_3_CLKINV_5847,
SET => GND,
RST => CU_next_state_3_SRINV_5848,
O => CU_next_state(2)
);
CU_next_state_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(8),
O => CU_next_state_5_DXMUX_5914
);
CU_next_state_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y10",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(9),
O => CU_next_state_5_DYMUX_5900
);
CU_next_state_5_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y10",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_5_SRINV_5891
);
CU_next_state_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_5_CLKINV_5890
);
CU_loadAC_DYMUX : X_BUF
generic map(
LOC => "SLICE_X24Y17",
PATHPULSE => 638 ps
)
port map (
I => CU_loadAC_mux0000,
O => CU_loadAC_DYMUX_5937
);
CU_loadAC_CLKINV : X_BUF
generic map(
LOC => "SLICE_X24Y17",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_loadAC_CLKINV_5927
);
CU_next_state_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y13",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(7),
O => CU_next_state_6_DYMUX_5960
);
CU_next_state_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_6_CLKINV_5951
);
CU_next_state_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(4),
O => CU_next_state_9_DXMUX_6002
);
CU_next_state_9_DYMUX : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => CU_next_state_mux0012(5),
O => CU_next_state_9_DYMUX_5988
);
CU_next_state_9_SRINV : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_9_SRINV_5979
);
CU_next_state_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => CU_next_state_9_CLKINV_5978
);
alu_MULTIPLICATION_1 : X_LATCHE
generic map(
LOC => "SLICE_X26Y31",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_1_DXMUX_2502,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_1_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(1)
);
CU_Mcount_state_timer_lut_24_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y30"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(24),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(24)
);
CU_Mcount_state_timer_lut_22_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y29"
)
port map (
ADR0 => CU_state_timer(22),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(22)
);
CU_Mcount_state_timer_lut_25_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y30"
)
port map (
ADR0 => CU_state_timer(25),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(25)
);
PC_Mcount_data_lut_3_Q : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X27Y20"
)
port map (
ADR0 => PC_data(3),
ADR1 => R_D_M_reg(3),
ADR2 => CU_loadPC_1524,
ADR3 => VCC,
O => PC_Mcount_data_lut(3)
);
CU_current_state_cmp_eq0000_wg_lut_4_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y22"
)
port map (
ADR0 => CU_state_timer(20),
ADR1 => CU_state_timer(22),
ADR2 => CU_state_timer(21),
ADR3 => CU_state_timer(3),
O => CU_current_state_cmp_eq0000_wg_lut(4)
);
CU_current_state_cmp_eq0000_wg_lut_7_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y23"
)
port map (
ADR0 => CU_state_timer(29),
ADR1 => CU_state_timer(30),
ADR2 => CU_state_timer(0),
ADR3 => CU_state_timer(31),
O => CU_current_state_cmp_eq0000_wg_lut(7)
);
AC_reg_2 : X_FF
generic map(
LOC => "SLICE_X27Y32",
INIT => '0'
)
port map (
I => AC_reg_2_DYMUX_3836,
CE => AC_reg_2_CEINV_3823,
CLK => AC_reg_2_CLKINV_3824,
SET => GND,
RST => AC_reg_2_FFY_RSTAND_3842,
O => AC_reg(2)
);
AC_reg_2_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X27Y32",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => AC_reg_2_FFY_RSTAND_3842
);
AC_reg_6 : X_FF
generic map(
LOC => "SLICE_X25Y34",
INIT => '0'
)
port map (
I => AC_reg_6_DYMUX_4116,
CE => AC_reg_6_CEINV_4103,
CLK => AC_reg_6_CLKINV_4104,
SET => GND,
RST => AC_reg_6_FFY_RSTAND_4122,
O => AC_reg(6)
);
AC_reg_6_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X25Y34",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => AC_reg_6_FFY_RSTAND_4122
);
alu_Mmux_result_47 : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X23Y34"
)
port map (
ADR0 => CU_sel_ula(0),
ADR1 => alu_MULTIPLICATION(7),
ADR2 => AC_reg(6),
ADR3 => VCC,
O => alu_Mmux_result_47_4200
);
CU_next_state_mux0012_13_381 : X_LUT4
generic map(
INIT => X"BBBB",
LOC => "SLICE_X24Y10"
)
port map (
ADR0 => CU_stop_s_1511,
ADR1 => enable_IBUF_1520,
ADR2 => VCC,
ADR3 => VCC,
O => CU_next_state_mux0012_13_381_4641
);
CU_next_state_mux0012_13_382 : X_LUT4
generic map(
INIT => X"4000",
LOC => "SLICE_X24Y10"
)
port map (
ADR0 => CU_current_state(6),
ADR1 => CU_next_state_mux0012_13_14_0,
ADR2 => CU_N10,
ADR3 => CU_N18_0,
O => CU_next_state_mux0012_13_382_4632
);
CU_next_state_mux0012_10_1 : X_LUT4
generic map(
INIT => X"FCF0",
LOC => "SLICE_X18Y9"
)
port map (
ADR0 => VCC,
ADR1 => CU_next_state(3),
ADR2 => CU_current_state(2),
ADR3 => CU_N9_0,
O => CU_next_state_mux0012(10)
);
CU_Mcount_state_timer_eqn_291 : X_LUT4
generic map(
INIT => X"5050",
LOC => "SLICE_X3Y26"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => VCC,
ADR2 => CU_Result(29),
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_29
);
CU_state_timer_27 : X_FF
generic map(
LOC => "SLICE_X2Y25",
INIT => '0'
)
port map (
I => CU_state_timer_27_DXMUX_5788,
CE => VCC,
CLK => CU_state_timer_27_CLKINV_5761,
SET => GND,
RST => CU_state_timer_27_SRINV_5762,
O => CU_state_timer(27)
);
CU_state_timer_26 : X_FF
generic map(
LOC => "SLICE_X2Y25",
INIT => '0'
)
port map (
I => CU_state_timer_27_DYMUX_5772,
CE => VCC,
CLK => CU_state_timer_27_CLKINV_5761,
SET => GND,
RST => CU_state_timer_27_SRINV_5762,
O => CU_state_timer(26)
);
CU_Mcount_state_timer_eqn_251 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X3Y31"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_state_timer_not0001_inv,
ADR3 => CU_Result(25),
O => CU_Mcount_state_timer_eqn_25
);
CU_next_state_mux0012_3_1 : X_LUT4
generic map(
INIT => X"FAAA",
LOC => "SLICE_X25Y8"
)
port map (
ADR0 => CU_current_state(6),
ADR1 => VCC,
ADR2 => CU_N9_0,
ADR3 => CU_next_state(10),
O => CU_next_state_mux0012(3)
);
CU_next_state_10 : X_FF
generic map(
LOC => "SLICE_X25Y8",
INIT => '0'
)
port map (
I => CU_next_state_11_DYMUX_1720,
CE => VCC,
CLK => CU_next_state_11_CLKINV_1710,
SET => GND,
RST => CU_next_state_11_SRINV_1711,
O => CU_next_state(10)
);
CU_next_state_mux0012_2_1 : X_LUT4
generic map(
INIT => X"ECA0",
LOC => "SLICE_X25Y8"
)
port map (
ADR0 => CU_next_state(11),
ADR1 => exec_HLT,
ADR2 => CU_N9_0,
ADR3 => CU_current_state(3),
O => CU_next_state_mux0012(2)
);
CU_next_state_11 : X_FF
generic map(
LOC => "SLICE_X25Y8",
INIT => '0'
)
port map (
I => CU_next_state_11_DXMUX_1734,
CE => VCC,
CLK => CU_next_state_11_CLKINV_1710,
SET => GND,
RST => CU_next_state_11_SRINV_1711,
O => CU_next_state(11)
);
CU_next_state_mux0012_1_1 : X_LUT4
generic map(
INIT => X"AA08",
LOC => "SLICE_X16Y12"
)
port map (
ADR0 => CU_current_state(7),
ADR1 => CU_next_state(12),
ADR2 => exec_STA,
ADR3 => CU_N7,
O => CU_next_state_mux0012(1)
);
R_D_M_reg_0 : X_FF
generic map(
LOC => "SLICE_X24Y29",
INIT => '0'
)
port map (
I => R_D_M_reg_1_DYMUX_1805,
CE => R_D_M_reg_1_CEINV_1794,
CLK => R_D_M_reg_1_CLKINV_1795,
SET => GND,
RST => R_D_M_reg_1_SRINV_1796,
O => R_D_M_reg(0)
);
CU_next_state_12 : X_FF
generic map(
LOC => "SLICE_X16Y12",
INIT => '0'
)
port map (
I => CU_next_state_13_DYMUX_1762,
CE => VCC,
CLK => CU_next_state_13_CLKINV_1753,
SET => GND,
RST => CU_next_state_13_SRINV_1754,
O => CU_next_state(12)
);
CU_next_state_mux0012_0_17 : X_LUT4
generic map(
INIT => X"FEEE",
LOC => "SLICE_X16Y12"
)
port map (
ADR0 => CU_next_state_mux0012_0_8_0,
ADR1 => CU_current_state(12),
ADR2 => CU_N9_0,
ADR3 => CU_next_state(13),
O => CU_next_state_mux0012(0)
);
CU_next_state_13 : X_FF
generic map(
LOC => "SLICE_X16Y12",
INIT => '0'
)
port map (
I => CU_next_state_13_DXMUX_1776,
CE => VCC,
CLK => CU_next_state_13_CLKINV_1753,
SET => GND,
RST => CU_next_state_13_SRINV_1754,
O => CU_next_state(13)
);
mux_rdm_S_1_1 : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X24Y29"
)
port map (
ADR0 => AC_reg(1),
ADR1 => VCC,
ADR2 => MEM_output(1),
ADR3 => CU_sel_mux_RDM_1453,
O => muxrdm_output(1)
);
R_D_M_reg_1 : X_FF
generic map(
LOC => "SLICE_X24Y29",
INIT => '0'
)
port map (
I => R_D_M_reg_1_DXMUX_1821,
CE => R_D_M_reg_1_CEINV_1794,
CLK => R_D_M_reg_1_CLKINV_1795,
SET => GND,
RST => R_D_M_reg_1_SRINV_1796,
O => R_D_M_reg(1)
);
CU_loadRDM_mux00004 : X_LUT4
generic map(
INIT => X"FFFE",
LOC => "SLICE_X24Y13"
)
port map (
ADR0 => CU_current_state(10),
ADR1 => CU_current_state(5),
ADR2 => CU_current_state(2),
ADR3 => CU_current_state(12),
O => CU_loadRDM_mux00004_2190
);
CU_loadRDM_mux000016 : X_LUT4
generic map(
INIT => X"FFCC",
LOC => "SLICE_X27Y11"
)
port map (
ADR0 => VCC,
ADR1 => CU_loadRDM_mux00004_0,
ADR2 => VCC,
ADR3 => CU_loadRDM_mux000015_0,
O => CU_loadRDM_mux0000
);
CU_loadRDM : X_FF
generic map(
LOC => "SLICE_X27Y11",
INIT => '0'
)
port map (
I => CU_loadRDM_DYMUX_1845,
CE => VCC,
CLK => CU_loadRDM_CLKINV_1834,
SET => GND,
RST => CU_loadRDM_FFY_RSTAND_1850,
O => CU_loadRDM_1452
);
CU_loadRDM_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X27Y11",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_loadRDM_FFY_RSTAND_1850
);
mux_rdm_S_2_1 : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X24Y32"
)
port map (
ADR0 => MEM_output(2),
ADR1 => VCC,
ADR2 => AC_reg(2),
ADR3 => CU_sel_mux_RDM_1453,
O => muxrdm_output(2)
);
R_D_M_reg_2 : X_FF
generic map(
LOC => "SLICE_X24Y32",
INIT => '0'
)
port map (
I => R_D_M_reg_3_DYMUX_1874,
CE => R_D_M_reg_3_CEINV_1863,
CLK => R_D_M_reg_3_CLKINV_1864,
SET => GND,
RST => R_D_M_reg_3_SRINV_1865,
O => R_D_M_reg(2)
);
R_D_M_reg_3 : X_FF
generic map(
LOC => "SLICE_X24Y32",
INIT => '0'
)
port map (
I => R_D_M_reg_3_DXMUX_1890,
CE => R_D_M_reg_3_CEINV_1863,
CLK => R_D_M_reg_3_CLKINV_1864,
SET => GND,
RST => R_D_M_reg_3_SRINV_1865,
O => R_D_M_reg(3)
);
CU_sel_ula_0 : X_FF
generic map(
LOC => "SLICE_X23Y18",
INIT => '0'
)
port map (
I => CU_sel_ula_1_DYMUX_1919,
CE => CU_sel_ula_1_CEINV_1910,
CLK => CU_sel_ula_1_CLKINV_1911,
SET => GND,
RST => GND,
O => CU_sel_ula(0)
);
CU_sel_ula_mux0000_2_Q : X_LUT4
generic map(
INIT => X"BAFD",
LOC => "SLICE_X23Y18"
)
port map (
ADR0 => RI_reg(6),
ADR1 => RI_reg(4),
ADR2 => RI_reg(7),
ADR3 => RI_reg(5),
O => CU_sel_ula_mux0000(2)
);
CU_sel_ula_mux0000_1_Q : X_LUT4
generic map(
INIT => X"FF27",
LOC => "SLICE_X23Y18"
)
port map (
ADR0 => RI_reg(6),
ADR1 => RI_reg(4),
ADR2 => RI_reg(5),
ADR3 => RI_reg(7),
O => CU_sel_ula_mux0000(1)
);
CU_sel_ula_1 : X_FF
generic map(
LOC => "SLICE_X23Y18",
INIT => '0'
)
port map (
I => CU_sel_ula_1_DXMUX_1931,
CE => CU_sel_ula_1_CEINV_1910,
CLK => CU_sel_ula_1_CLKINV_1911,
SET => GND,
RST => GND,
O => CU_sel_ula(1)
);
mux_rdm_S_4_1 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X22Y32"
)
port map (
ADR0 => AC_reg(4),
ADR1 => VCC,
ADR2 => CU_sel_mux_RDM_1453,
ADR3 => MEM_output(4),
O => muxrdm_output(4)
);
R_D_M_reg_5 : X_FF
generic map(
LOC => "SLICE_X22Y32",
INIT => '0'
)
port map (
I => R_D_M_reg_5_DXMUX_1974,
CE => R_D_M_reg_5_CEINV_1947,
CLK => R_D_M_reg_5_CLKINV_1948,
SET => GND,
RST => R_D_M_reg_5_SRINV_1949,
O => R_D_M_reg(5)
);
CU_sel_ula_mux0000_0_1 : X_LUT4
generic map(
INIT => X"F8F7",
LOC => "SLICE_X23Y13"
)
port map (
ADR0 => RI_reg(5),
ADR1 => RI_reg(4),
ADR2 => RI_reg(7),
ADR3 => RI_reg(6),
O => CU_sel_ula_mux0000(0)
);
CU_sel_ula_2 : X_FF
generic map(
LOC => "SLICE_X23Y13",
INIT => '0'
)
port map (
I => CU_sel_ula_2_DYMUX_2003,
CE => CU_sel_ula_2_CEINV_1994,
CLK => CU_sel_ula_2_CLKINV_1995,
SET => GND,
RST => GND,
O => CU_sel_ula(2)
);
dec_s_exec_NOP_cmp_eq00001 : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X23Y13"
)
port map (
ADR0 => RI_reg(5),
ADR1 => RI_reg(4),
ADR2 => RI_reg(7),
ADR3 => RI_reg(6),
O => exec_NOP
);
mux_rdm_S_6_1 : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X22Y28"
)
port map (
ADR0 => AC_reg(6),
ADR1 => MEM_output(6),
ADR2 => VCC,
ADR3 => CU_sel_mux_RDM_1453,
O => muxrdm_output(6)
);
R_D_M_reg_7 : X_FF
generic map(
LOC => "SLICE_X22Y28",
INIT => '0'
)
port map (
I => R_D_M_reg_7_DXMUX_2053,
CE => R_D_M_reg_7_CEINV_2026,
CLK => R_D_M_reg_7_CLKINV_2027,
SET => GND,
RST => R_D_M_reg_7_SRINV_2028,
O => R_D_M_reg(7)
);
CU_current_state_2 : X_FF
generic map(
LOC => "SLICE_X18Y8",
INIT => '0'
)
port map (
I => CU_current_state_3_DYMUX_2070,
CE => CU_current_state_3_CEINV_2067,
CLK => CU_current_state_3_CLKINV_2068,
SET => GND,
RST => GND,
O => CU_current_state(2)
);
CU_current_state_3 : X_FF
generic map(
LOC => "SLICE_X18Y8",
INIT => '0'
)
port map (
I => CU_current_state_3_DXMUX_2076,
CE => CU_current_state_3_CEINV_2067,
CLK => CU_current_state_3_CLKINV_2068,
SET => GND,
RST => GND,
O => CU_current_state(3)
);
CU_next_state_mux0012_6_SW1 : X_LUT4
generic map(
INIT => X"E271",
LOC => "SLICE_X21Y9"
)
port map (
ADR0 => RI_reg(5),
ADR1 => RI_reg(4),
ADR2 => RI_reg(7),
ADR3 => RI_reg(6),
O => N32_pack_2
);
CU_next_state_mux0012_6_Q : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X21Y9"
)
port map (
ADR0 => CU_current_state(7),
ADR1 => CU_next_state(7),
ADR2 => CU_current_state(10),
ADR3 => N32,
O => CU_next_state_mux0012(6)
);
CU_current_state_4 : X_FF
generic map(
LOC => "SLICE_X17Y10",
INIT => '0'
)
port map (
I => CU_current_state_5_DYMUX_2125,
CE => CU_current_state_5_CEINV_2122,
CLK => CU_current_state_5_CLKINV_2123,
SET => GND,
RST => GND,
O => CU_current_state(4)
);
CU_current_state_5 : X_FF
generic map(
LOC => "SLICE_X17Y10",
INIT => '0'
)
port map (
I => CU_current_state_5_DXMUX_2131,
CE => CU_current_state_5_CEINV_2122,
CLK => CU_current_state_5_CLKINV_2123,
SET => GND,
RST => GND,
O => CU_current_state(5)
);
CU_current_state_6 : X_FF
generic map(
LOC => "SLICE_X17Y11",
INIT => '0'
)
port map (
I => CU_current_state_7_DYMUX_2145,
CE => CU_current_state_7_CEINV_2142,
CLK => CU_current_state_7_CLKINV_2143,
SET => GND,
RST => GND,
O => CU_current_state(6)
);
CU_current_state_7 : X_FF
generic map(
LOC => "SLICE_X17Y11",
INIT => '0'
)
port map (
I => CU_current_state_7_DXMUX_2151,
CE => CU_current_state_7_CEINV_2142,
CLK => CU_current_state_7_CLKINV_2143,
SET => GND,
RST => GND,
O => CU_current_state(7)
);
CU_current_state_8 : X_FF
generic map(
LOC => "SLICE_X21Y10",
INIT => '0'
)
port map (
I => CU_current_state_9_DYMUX_2165,
CE => CU_current_state_9_CEINV_2162,
CLK => CU_current_state_9_CLKINV_2163,
SET => GND,
RST => GND,
O => CU_current_state(8)
);
CU_next_state_mux0012_13_41 : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X24Y13"
)
port map (
ADR0 => CU_current_state(10),
ADR1 => CU_current_state(5),
ADR2 => CU_current_state(2),
ADR3 => CU_current_state(12),
O => CU_N18
);
CU_next_state_or000123_SW1 : X_LUT4
generic map(
INIT => X"BB0A",
LOC => "SLICE_X23Y17"
)
port map (
ADR0 => RI_reg(4),
ADR1 => NZ_data_Z_1506,
ADR2 => NZ_data_N_1484,
ADR3 => RI_reg(5),
O => N30
);
alu_MULTIPLICATION_cmp_eq00001 : X_LUT4
generic map(
INIT => X"8080",
LOC => "SLICE_X28Y31"
)
port map (
ADR0 => CU_sel_ula(1),
ADR1 => CU_sel_ula(0),
ADR2 => CU_sel_ula(2),
ADR3 => VCC,
O => alu_MULTIPLICATION_cmp_eq0000
);
CU_stop_s : X_FF
generic map(
LOC => "SLICE_X25Y9",
INIT => '0'
)
port map (
I => CU_stop_s_DYMUX_2233,
CE => CU_stop_s_CEINV_2229,
CLK => CU_stop_s_CLKINV_2230,
SET => GND,
RST => CU_stop_s_FFY_RSTAND_2239,
O => CU_stop_s_1511
);
CU_stop_s_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X25Y9",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_stop_s_FFY_RSTAND_2239
);
CU_loadRI_mux0000_SW0 : X_LUT4
generic map(
INIT => X"FEFF",
LOC => "SLICE_X23Y11"
)
port map (
ADR0 => CU_current_state(11),
ADR1 => CU_current_state(9),
ADR2 => CU_current_state(6),
ADR3 => CU_loadRI_1515,
O => N10_pack_2
);
CU_loadRI_mux0000 : X_LUT4
generic map(
INIT => X"F0F1",
LOC => "SLICE_X23Y11"
)
port map (
ADR0 => CU_current_state(1),
ADR1 => CU_current_state(13),
ADR2 => CU_current_state(3),
ADR3 => N10,
O => CU_loadRI_mux0000_2266
);
CU_loadRI : X_FF
generic map(
LOC => "SLICE_X23Y11",
INIT => '0'
)
port map (
I => CU_loadRI_DXMUX_2269,
CE => VCC,
CLK => CU_loadRI_CLKINV_2253,
SET => GND,
RST => CU_loadRI_FFX_RSTAND_2274,
O => CU_loadRI_1515
);
CU_loadRI_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X23Y11",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_loadRI_FFX_RSTAND_2274
);
CU_current_state_10 : X_FF
generic map(
LOC => "SLICE_X15Y12",
INIT => '0'
)
port map (
I => CU_current_state_11_DYMUX_2285,
CE => CU_current_state_11_CEINV_2282,
CLK => CU_current_state_11_CLKINV_2283,
SET => GND,
RST => GND,
O => CU_current_state(10)
);
CU_current_state_11 : X_FF
generic map(
LOC => "SLICE_X15Y12",
INIT => '0'
)
port map (
I => CU_current_state_11_DXMUX_2291,
CE => CU_current_state_11_CEINV_2282,
CLK => CU_current_state_11_CLKINV_2283,
SET => GND,
RST => GND,
O => CU_current_state(11)
);
CU_current_state_13 : X_FF
generic map(
LOC => "SLICE_X13Y14",
INIT => '0'
)
port map (
I => CU_current_state_13_DXMUX_2311,
CE => CU_current_state_13_CEINV_2302,
CLK => CU_current_state_13_CLKINV_2303,
SET => GND,
RST => GND,
O => CU_current_state(13)
);
alu_MULTIPLICATION_2 : X_LATCHE
generic map(
LOC => "SLICE_X26Y29",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_3_DYMUX_2513,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_2_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(2)
);
CU_next_state_mux0012_12_13_SW0 : X_LUT4
generic map(
INIT => X"FFFE",
LOC => "SLICE_X25Y11"
)
port map (
ADR0 => CU_current_state(9),
ADR1 => CU_current_state(13),
ADR2 => CU_current_state(4),
ADR3 => CU_current_state(8),
O => N24_pack_1
);
CU_next_state_mux0012_12_13 : X_LUT4
generic map(
INIT => X"FF40",
LOC => "SLICE_X25Y11"
)
port map (
ADR0 => CU_stop_s_1511,
ADR1 => enable_IBUF_1520,
ADR2 => CU_current_state(0),
ADR3 => N24,
O => CU_next_state_mux0012_12_13_2349
);
RI_reg_4 : X_FF
generic map(
LOC => "SLICE_X23Y15",
INIT => '0'
)
port map (
I => RI_reg_5_DYMUX_2363,
CE => RI_reg_5_CEINV_2359,
CLK => RI_reg_5_CLKINV_2360,
SET => GND,
RST => RI_reg_5_SRINV_2361,
O => RI_reg(4)
);
RI_reg_5 : X_FF
generic map(
LOC => "SLICE_X23Y15",
INIT => '0'
)
port map (
I => RI_reg_5_DXMUX_2372,
CE => RI_reg_5_CEINV_2359,
CLK => RI_reg_5_CLKINV_2360,
SET => GND,
RST => RI_reg_5_SRINV_2361,
O => RI_reg(5)
);
RI_reg_6 : X_FF
generic map(
LOC => "SLICE_X22Y17",
INIT => '0'
)
port map (
I => RI_reg_7_DYMUX_2391,
CE => RI_reg_7_CEINV_2387,
CLK => RI_reg_7_CLKINV_2388,
SET => GND,
RST => RI_reg_7_SRINV_2389,
O => RI_reg(6)
);
RI_reg_7 : X_FF
generic map(
LOC => "SLICE_X22Y17",
INIT => '0'
)
port map (
I => RI_reg_7_DXMUX_2400,
CE => RI_reg_7_CEINV_2387,
CLK => RI_reg_7_CLKINV_2388,
SET => GND,
RST => RI_reg_7_SRINV_2389,
O => RI_reg(7)
);
CU_current_state_and00001 : X_LUT4
generic map(
INIT => X"5050",
LOC => "SLICE_X16Y11"
)
port map (
ADR0 => rst_IBUF_1438,
ADR1 => VCC,
ADR2 => CU_state_timer_not0001_inv,
ADR3 => VCC,
O => CU_current_state_not0001_inv
);
PC_data_not00011 : X_LUT4
generic map(
INIT => X"FFAA",
LOC => "SLICE_X25Y14"
)
port map (
ADR0 => CU_loadPC_1524,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_PC_inc_1525,
O => PC_data_not0001
);
CU_loadPC : X_FF
generic map(
LOC => "SLICE_X25Y14",
INIT => '0'
)
port map (
I => CU_loadPC_DXMUX_2448,
CE => VCC,
CLK => CU_loadPC_CLKINV_2429,
SET => GND,
RST => CU_loadPC_FFX_RSTAND_2453,
O => CU_loadPC_1524
);
CU_loadPC_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_loadPC_FFX_RSTAND_2453
);
CU_next_state_mux0012_13_14 : X_LUT4
generic map(
INIT => X"0011",
LOC => "SLICE_X23Y10"
)
port map (
ADR0 => CU_current_state(9),
ADR1 => CU_current_state(4),
ADR2 => VCC,
ADR3 => CU_current_state(13),
O => CU_next_state_mux0012_13_14_2472
);
CU_wr_enable_mem_0_mux00001 : X_LUT4
generic map(
INIT => X"CCEE",
LOC => "SLICE_X23Y10"
)
port map (
ADR0 => CU_wr_enable_mem(0),
ADR1 => CU_current_state(4),
ADR2 => VCC,
ADR3 => CU_current_state(1),
O => CU_wr_enable_mem_0_mux0000
);
CU_wr_enable_mem_0 : X_FF
generic map(
LOC => "SLICE_X23Y10",
INIT => '0'
)
port map (
I => CU_wr_enable_mem_0_DXMUX_2483,
CE => VCC,
CLK => CU_wr_enable_mem_0_CLKINV_2465,
SET => GND,
RST => CU_wr_enable_mem_0_FFX_RSTAND_2488,
O => CU_wr_enable_mem(0)
);
CU_wr_enable_mem_0_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X23Y10",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_wr_enable_mem_0_FFX_RSTAND_2488
);
alu_MULTIPLICATION_0 : X_LATCHE
generic map(
LOC => "SLICE_X26Y31",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_1_DYMUX_2497,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_0_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(0)
);
alu_MULTIPLICATION_3 : X_LATCHE
generic map(
LOC => "SLICE_X26Y29",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_3_DXMUX_2518,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_3_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(3)
);
PC_data_2 : X_FF
generic map(
LOC => "SLICE_X27Y20",
INIT => '0'
)
port map (
I => PC_data_2_DXMUX_3427,
CE => PC_data_2_CEINV_3388,
CLK => PC_data_2_CLKINV_3389,
SET => GND,
RST => PC_data_2_SRINV_3390,
O => PC_data(2)
);
alu_MULTIPLICATION_4 : X_LATCHE
generic map(
LOC => "SLICE_X22Y33",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_5_DYMUX_2529,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_4_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(4)
);
alu_MULTIPLICATION_5 : X_LATCHE
generic map(
LOC => "SLICE_X22Y33",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_5_DXMUX_2534,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_5_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(5)
);
alu_MULTIPLICATION_6 : X_LATCHE
generic map(
LOC => "SLICE_X26Y32",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_7_DYMUX_2545,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_6_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(6)
);
alu_MULTIPLICATION_7 : X_LATCHE
generic map(
LOC => "SLICE_X26Y32",
INIT => '0'
)
port map (
I => alu_MULTIPLICATION_7_DXMUX_2550,
GE => VCC,
CLK => NlwInverterSignal_alu_MULTIPLICATION_7_CLK,
SET => GND,
RST => GND,
O => alu_MULTIPLICATION(7)
);
CU_current_state_0 : X_FF
generic map(
LOC => "SLICE_X16Y10",
INIT => '1'
)
port map (
I => CU_current_state_1_DYMUX_2563,
CE => CU_current_state_1_CEINV_2560,
CLK => CU_current_state_1_CLKINV_2561,
SET => GND,
RST => GND,
O => CU_current_state(0)
);
CU_current_state_1 : X_FF
generic map(
LOC => "SLICE_X16Y10",
INIT => '0'
)
port map (
I => CU_current_state_1_DXMUX_2569,
CE => CU_current_state_1_CEINV_2560,
CLK => CU_current_state_1_CLKINV_2561,
SET => GND,
RST => GND,
O => CU_current_state(1)
);
alu_Madd_result_addsub0000_lut_1_Q : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X25Y29"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(1),
ADR2 => R_D_M_reg(1),
ADR3 => VCC,
O => alu_Madd_result_addsub0000_lut(1)
);
alu_Madd_result_addsub0000_lut_0_Q : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X25Y29"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(0),
ADR2 => VCC,
ADR3 => R_D_M_reg(0),
O => alu_Madd_result_addsub0000_lut(0)
);
alu_Madd_result_addsub0000_lut_3_Q : X_LUT4
generic map(
INIT => X"55AA",
LOC => "SLICE_X25Y30"
)
port map (
ADR0 => AC_reg(3),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => R_D_M_reg(3),
O => alu_Madd_result_addsub0000_lut(3)
);
alu_Madd_result_addsub0000_lut_2_Q : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X25Y30"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(2),
ADR2 => R_D_M_reg(2),
ADR3 => VCC,
O => alu_Madd_result_addsub0000_lut(2)
);
alu_Madd_result_addsub0000_lut_5_Q : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X25Y31"
)
port map (
ADR0 => R_D_M_reg(5),
ADR1 => AC_reg(5),
ADR2 => VCC,
ADR3 => VCC,
O => alu_Madd_result_addsub0000_lut(5)
);
alu_Madd_result_addsub0000_lut_4_Q : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X25Y31"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(4),
ADR2 => VCC,
ADR3 => R_D_M_reg(4),
O => alu_Madd_result_addsub0000_lut(4)
);
alu_Madd_result_addsub0000_lut_7_Q : X_LUT4
generic map(
INIT => X"55AA",
LOC => "SLICE_X25Y32"
)
port map (
ADR0 => R_D_M_reg(7),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => NZ_data_N_1484,
O => alu_Madd_result_addsub0000_lut(7)
);
alu_Madd_result_addsub0000_lut_6_Q : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X25Y32"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(6),
ADR2 => R_D_M_reg(6),
ADR3 => VCC,
O => alu_Madd_result_addsub0000_lut(6)
);
CU_Mcount_state_timer_lut_1_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y18"
)
port map (
ADR0 => CU_state_timer(1),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(1)
);
CU_Mcount_state_timer_lut_3_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X1Y19"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_state_timer(3),
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(3)
);
CU_Mcount_state_timer_lut_2_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y19"
)
port map (
ADR0 => CU_state_timer(2),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(2)
);
CU_Mcount_state_timer_lut_5_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y20"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(5),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(5)
);
CU_Mcount_state_timer_lut_4_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y20"
)
port map (
ADR0 => CU_state_timer(4),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(4)
);
CU_Mcount_state_timer_lut_7_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y21"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(7),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(7)
);
CU_Mcount_state_timer_lut_6_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y21"
)
port map (
ADR0 => CU_state_timer(6),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(6)
);
CU_Mcount_state_timer_lut_9_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X1Y22"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_state_timer(9),
O => CU_Mcount_state_timer_lut(9)
);
CU_Mcount_state_timer_lut_8_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X1Y22"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_state_timer(8),
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(8)
);
CU_Mcount_state_timer_lut_11_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X1Y23"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_state_timer(11),
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(11)
);
CU_Mcount_state_timer_lut_10_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y23"
)
port map (
ADR0 => CU_state_timer(10),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(10)
);
CU_Mcount_state_timer_lut_13_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X1Y24"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_state_timer(13),
O => CU_Mcount_state_timer_lut(13)
);
CU_Mcount_state_timer_lut_12_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y24"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(12),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(12)
);
CU_Mcount_state_timer_lut_15_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y25"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(15),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(15)
);
CU_Mcount_state_timer_lut_14_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X1Y25"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_state_timer(14),
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(14)
);
CU_Mcount_state_timer_lut_17_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X1Y26"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_state_timer(17),
O => CU_Mcount_state_timer_lut(17)
);
CU_Mcount_state_timer_lut_16_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y26"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(16),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(16)
);
CU_Mcount_state_timer_lut_19_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X1Y27"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_state_timer(19),
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(19)
);
CU_Mcount_state_timer_lut_18_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X1Y27"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_state_timer(18),
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(18)
);
CU_Mcount_state_timer_lut_21_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y28"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(21),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(21)
);
CU_Mcount_state_timer_lut_20_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X1Y28"
)
port map (
ADR0 => CU_state_timer(20),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(20)
);
CU_Mcount_state_timer_lut_23_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X1Y29"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(23),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_lut(23)
);
PC_Mcount_data_lut_5_Q : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X27Y21"
)
port map (
ADR0 => VCC,
ADR1 => R_D_M_reg(5),
ADR2 => CU_loadPC_1524,
ADR3 => PC_data(5),
O => PC_Mcount_data_lut(5)
);
PC_data_5 : X_FF
generic map(
LOC => "SLICE_X27Y21",
INIT => '0'
)
port map (
I => PC_data_4_DYMUX_3469,
CE => PC_data_4_CEINV_3448,
CLK => PC_data_4_CLKINV_3449,
SET => GND,
RST => PC_data_4_SRINV_3450,
O => PC_data(5)
);
PC_data_4 : X_FF
generic map(
LOC => "SLICE_X27Y21",
INIT => '0'
)
port map (
I => PC_data_4_DXMUX_3487,
CE => PC_data_4_CEINV_3448,
CLK => PC_data_4_CLKINV_3449,
SET => GND,
RST => PC_data_4_SRINV_3450,
O => PC_data(4)
);
PC_Mcount_data_lut_7_Q : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X27Y22"
)
port map (
ADR0 => R_D_M_reg(7),
ADR1 => VCC,
ADR2 => CU_loadPC_1524,
ADR3 => PC_data(7),
O => PC_Mcount_data_lut(7)
);
PC_data_7 : X_FF
generic map(
LOC => "SLICE_X27Y22",
INIT => '0'
)
port map (
I => PC_data_6_DYMUX_3520,
CE => PC_data_6_CEINV_3507,
CLK => PC_data_6_CLKINV_3508,
SET => GND,
RST => PC_data_6_SRINV_3509,
O => PC_data(7)
);
PC_Mcount_data_lut_6_Q : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X27Y22"
)
port map (
ADR0 => PC_data(6),
ADR1 => R_D_M_reg(6),
ADR2 => CU_loadPC_1524,
ADR3 => VCC,
O => PC_Mcount_data_lut(6)
);
CU_current_state_cmp_eq0000_wg_lut_1_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y20"
)
port map (
ADR0 => CU_state_timer(6),
ADR1 => CU_state_timer(13),
ADR2 => CU_state_timer(11),
ADR3 => CU_state_timer(12),
O => CU_current_state_cmp_eq0000_wg_lut(1)
);
CU_current_state_cmp_eq0000_wg_lut_0_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y20"
)
port map (
ADR0 => CU_state_timer(10),
ADR1 => CU_state_timer(7),
ADR2 => CU_state_timer(8),
ADR3 => CU_state_timer(9),
O => CU_current_state_cmp_eq0000_wg_lut(0)
);
CU_current_state_cmp_eq0000_wg_lut_3_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y21"
)
port map (
ADR0 => CU_state_timer(19),
ADR1 => CU_state_timer(18),
ADR2 => CU_state_timer(4),
ADR3 => CU_state_timer(17),
O => CU_current_state_cmp_eq0000_wg_lut(3)
);
CU_current_state_cmp_eq0000_wg_lut_2_Q : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X3Y21"
)
port map (
ADR0 => CU_state_timer(15),
ADR1 => CU_state_timer(5),
ADR2 => CU_state_timer(16),
ADR3 => CU_state_timer(14),
O => CU_current_state_cmp_eq0000_wg_lut(2)
);
alu_Mmux_result_5 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X25Y26"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(1),
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(0),
O => alu_Mmux_result_5_3691
);
AC_reg_0 : X_FF
generic map(
LOC => "SLICE_X25Y26",
INIT => '0'
)
port map (
I => AC_reg_0_DYMUX_3695,
CE => AC_reg_0_CEINV_3682,
CLK => AC_reg_0_CLKINV_3683,
SET => GND,
RST => AC_reg_0_FFY_RSTAND_3701,
O => AC_reg(0)
);
AC_reg_0_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => AC_reg_0_FFY_RSTAND_3701
);
alu_Mmux_result_4 : X_LUT4
generic map(
INIT => X"F000",
LOC => "SLICE_X25Y26"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => alu_MULTIPLICATION(0),
ADR3 => CU_sel_ula(0),
O => alu_Mmux_result_4_3710
);
alu_Mmux_result_6 : X_LUT4
generic map(
INIT => X"CA0A",
LOC => "SLICE_X25Y27"
)
port map (
ADR0 => alu_result_addsub0000(0),
ADR1 => AC_reg(0),
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(0),
O => alu_Mmux_result_6_3726
);
alu_Mmux_result_51 : X_LUT4
generic map(
INIT => X"5F5A",
LOC => "SLICE_X25Y27"
)
port map (
ADR0 => AC_reg(0),
ADR1 => VCC,
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(0),
O => alu_Mmux_result_51_3734
);
alu_Mmux_result_52 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X27Y30"
)
port map (
ADR0 => R_D_M_reg(1),
ADR1 => AC_reg(2),
ADR2 => CU_sel_ula(0),
ADR3 => VCC,
O => alu_Mmux_result_52_3762
);
AC_reg_1 : X_FF
generic map(
LOC => "SLICE_X27Y30",
INIT => '0'
)
port map (
I => AC_reg_1_DYMUX_3766,
CE => AC_reg_1_CEINV_3753,
CLK => AC_reg_1_CLKINV_3754,
SET => GND,
RST => AC_reg_1_FFY_RSTAND_3772,
O => AC_reg(1)
);
AC_reg_1_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X27Y30",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => AC_reg_1_FFY_RSTAND_3772
);
alu_Mmux_result_41 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X27Y30"
)
port map (
ADR0 => AC_reg(0),
ADR1 => alu_MULTIPLICATION(1),
ADR2 => CU_sel_ula(0),
ADR3 => VCC,
O => alu_Mmux_result_41_3780
);
alu_Mmux_result_61 : X_LUT4
generic map(
INIT => X"D850",
LOC => "SLICE_X27Y31"
)
port map (
ADR0 => CU_sel_ula(0),
ADR1 => R_D_M_reg(1),
ADR2 => alu_result_addsub0000(1),
ADR3 => AC_reg(1),
O => alu_Mmux_result_61_3796
);
alu_Mmux_result_53 : X_LUT4
generic map(
INIT => X"0FFA",
LOC => "SLICE_X27Y31"
)
port map (
ADR0 => R_D_M_reg(1),
ADR1 => VCC,
ADR2 => CU_sel_ula(0),
ADR3 => AC_reg(1),
O => alu_Mmux_result_53_3804
);
alu_Mmux_result_42 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X27Y32"
)
port map (
ADR0 => VCC,
ADR1 => alu_MULTIPLICATION(2),
ADR2 => CU_sel_ula(0),
ADR3 => AC_reg(1),
O => alu_Mmux_result_42_3850
);
alu_Mmux_result_62 : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X27Y33"
)
port map (
ADR0 => R_D_M_reg(2),
ADR1 => AC_reg(2),
ADR2 => alu_result_addsub0000(2),
ADR3 => CU_sel_ula(0),
O => alu_Mmux_result_62_3866
);
alu_Mmux_result_55 : X_LUT4
generic map(
INIT => X"3F3C",
LOC => "SLICE_X27Y33"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(2),
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(2),
O => alu_Mmux_result_55_3874
);
alu_Mmux_result_56 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X23Y28"
)
port map (
ADR0 => VCC,
ADR1 => AC_reg(4),
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(3),
O => alu_Mmux_result_56_3902
);
AC_reg_3 : X_FF
generic map(
LOC => "SLICE_X23Y28",
INIT => '0'
)
port map (
I => AC_reg_3_DYMUX_3906,
CE => AC_reg_3_CEINV_3893,
CLK => AC_reg_3_CLKINV_3894,
SET => GND,
RST => AC_reg_3_FFY_RSTAND_3912,
O => AC_reg(3)
);
AC_reg_3_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => AC_reg_3_FFY_RSTAND_3912
);
alu_Mmux_result_63 : X_LUT4
generic map(
INIT => X"8F80",
LOC => "SLICE_X23Y29"
)
port map (
ADR0 => AC_reg(3),
ADR1 => R_D_M_reg(3),
ADR2 => CU_sel_ula(0),
ADR3 => alu_result_addsub0000(3),
O => alu_Mmux_result_63_3936
);
alu_Mmux_result_57 : X_LUT4
generic map(
INIT => X"5F5A",
LOC => "SLICE_X23Y29"
)
port map (
ADR0 => AC_reg(3),
ADR1 => VCC,
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(3),
O => alu_Mmux_result_57_3944
);
alu_Mmux_result_58 : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X23Y32"
)
port map (
ADR0 => VCC,
ADR1 => CU_sel_ula(0),
ADR2 => R_D_M_reg(4),
ADR3 => AC_reg(5),
O => alu_Mmux_result_58_3972
);
AC_reg_4 : X_FF
generic map(
LOC => "SLICE_X23Y32",
INIT => '0'
)
port map (
I => AC_reg_4_DYMUX_3976,
CE => AC_reg_4_CEINV_3963,
CLK => AC_reg_4_CLKINV_3964,
SET => GND,
RST => AC_reg_4_FFY_RSTAND_3982,
O => AC_reg(4)
);
AC_reg_4_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X23Y32",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => AC_reg_4_FFY_RSTAND_3982
);
alu_Mmux_result_44 : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X23Y32"
)
port map (
ADR0 => alu_MULTIPLICATION(4),
ADR1 => CU_sel_ula(0),
ADR2 => VCC,
ADR3 => AC_reg(3),
O => alu_Mmux_result_44_3990
);
alu_Mmux_result_510 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X23Y30"
)
port map (
ADR0 => CU_sel_ula(0),
ADR1 => VCC,
ADR2 => AC_reg(6),
ADR3 => R_D_M_reg(5),
O => alu_Mmux_result_510_4042
);
AC_reg_5 : X_FF
generic map(
LOC => "SLICE_X23Y30",
INIT => '0'
)
port map (
I => AC_reg_5_DYMUX_4046,
CE => AC_reg_5_CEINV_4033,
CLK => AC_reg_5_CLKINV_4034,
SET => GND,
RST => AC_reg_5_FFY_RSTAND_4052,
O => AC_reg(5)
);
AC_reg_5_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => AC_reg_5_FFY_RSTAND_4052
);
alu_Mmux_result_45 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X23Y30"
)
port map (
ADR0 => CU_sel_ula(0),
ADR1 => AC_reg(4),
ADR2 => alu_MULTIPLICATION(5),
ADR3 => VCC,
O => alu_Mmux_result_45_4060
);
alu_Mmux_result_65 : X_LUT4
generic map(
INIT => X"AC0C",
LOC => "SLICE_X23Y31"
)
port map (
ADR0 => AC_reg(5),
ADR1 => alu_result_addsub0000(5),
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(5),
O => alu_Mmux_result_65_4076
);
alu_Mmux_result_511 : X_LUT4
generic map(
INIT => X"7766",
LOC => "SLICE_X23Y31"
)
port map (
ADR0 => AC_reg(5),
ADR1 => CU_sel_ula(0),
ADR2 => VCC,
ADR3 => R_D_M_reg(5),
O => alu_Mmux_result_511_4084
);
alu_Mmux_result_46 : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X25Y34"
)
port map (
ADR0 => alu_MULTIPLICATION(6),
ADR1 => VCC,
ADR2 => AC_reg(5),
ADR3 => CU_sel_ula(0),
O => alu_Mmux_result_46_4130
);
alu_Mmux_result_66 : X_LUT4
generic map(
INIT => X"8F80",
LOC => "SLICE_X25Y35"
)
port map (
ADR0 => R_D_M_reg(6),
ADR1 => AC_reg(6),
ADR2 => CU_sel_ula(0),
ADR3 => alu_result_addsub0000(6),
O => alu_Mmux_result_66_4146
);
alu_Mmux_result_513 : X_LUT4
generic map(
INIT => X"0FFA",
LOC => "SLICE_X25Y35"
)
port map (
ADR0 => R_D_M_reg(6),
ADR1 => VCC,
ADR2 => CU_sel_ula(0),
ADR3 => AC_reg(6),
O => alu_Mmux_result_513_4154
);
alu_Mmux_result_514 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X23Y34"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => CU_sel_ula(0),
ADR3 => R_D_M_reg(7),
O => alu_Mmux_result_514_4182
);
alu_Mmux_result_67 : X_LUT4
generic map(
INIT => X"D850",
LOC => "SLICE_X23Y35"
)
port map (
ADR0 => CU_sel_ula(0),
ADR1 => NZ_data_N_1484,
ADR2 => alu_result_addsub0000(7),
ADR3 => R_D_M_reg(7),
O => alu_Mmux_result_67_4216
);
alu_Mmux_result_515 : X_LUT4
generic map(
INIT => X"7766",
LOC => "SLICE_X23Y35"
)
port map (
ADR0 => CU_sel_ula(0),
ADR1 => NZ_data_N_1484,
ADR2 => VCC,
ADR3 => R_D_M_reg(7),
O => alu_Mmux_result_515_4224
);
enable_IFF_IMUX : X_BUF
generic map(
LOC => "PAD47",
PATHPULSE => 638 ps
)
port map (
I => enable_INBUF,
O => enable_IBUF_1520
);
rst_IFF_IMUX : X_BUF
generic map(
LOC => "PAD49",
PATHPULSE => 638 ps
)
port map (
I => rst_INBUF,
O => rst_IBUF_1438
);
CU_PC_inc_mux00002 : X_LUT4
generic map(
INIT => X"FFFA",
LOC => "SLICE_X24Y12"
)
port map (
ADR0 => CU_current_state(10),
ADR1 => VCC,
ADR2 => CU_current_state(2),
ADR3 => CU_current_state(9),
O => CU_PC_inc_mux00002_4568
);
CU_PC_inc_mux00001 : X_LUT4
generic map(
INIT => X"FFFE",
LOC => "SLICE_X24Y12"
)
port map (
ADR0 => CU_N10,
ADR1 => CU_current_state(10),
ADR2 => CU_current_state(2),
ADR3 => CU_current_state(9),
O => CU_PC_inc_mux00001_4575
);
CU_PC_inc : X_FF
generic map(
LOC => "SLICE_X24Y12",
INIT => '0'
)
port map (
I => CU_PC_inc_DXMUX_4579,
CE => CU_PC_inc_CEINVNOT,
CLK => CU_PC_inc_CLKINV_4562,
SET => GND,
RST => GND,
O => CU_PC_inc_1525
);
CU_loadREM_mux00002 : X_LUT4
generic map(
INIT => X"FFEE",
LOC => "SLICE_X25Y12"
)
port map (
ADR0 => CU_current_state(1),
ADR1 => CU_current_state(7),
ADR2 => VCC,
ADR3 => CU_current_state(6),
O => CU_loadREM_mux00002_4602
);
CU_loadREM_mux00001 : X_LUT4
generic map(
INIT => X"FFFE",
LOC => "SLICE_X25Y12"
)
port map (
ADR0 => CU_current_state(1),
ADR1 => CU_current_state(7),
ADR2 => CU_loadREM_1685,
ADR3 => CU_current_state(6),
O => CU_loadREM_mux00001_4609
);
CU_loadREM : X_FF
generic map(
LOC => "SLICE_X25Y12",
INIT => '0'
)
port map (
I => CU_loadREM_DXMUX_4613,
CE => VCC,
CLK => CU_loadREM_CLKINV_4595,
SET => GND,
RST => CU_loadREM_FFX_RSTAND_4618,
O => CU_loadREM_1685
);
CU_loadREM_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_loadREM_FFX_RSTAND_4618
);
CU_sel_ula_and00001 : X_LUT4
generic map(
INIT => X"0C08",
LOC => "SLICE_X22Y12"
)
port map (
ADR0 => exec_NOT,
ADR1 => CU_current_state(12),
ADR2 => rst_IBUF_1438,
ADR3 => CU_N7,
O => CU_sel_ula_and0000
);
dec_s_exec_NOT1 : X_LUT4
generic map(
INIT => X"0200",
LOC => "SLICE_X22Y10"
)
port map (
ADR0 => RI_reg(6),
ADR1 => RI_reg(7),
ADR2 => RI_reg(4),
ADR3 => RI_reg(5),
O => exec_NOT_pack_1
);
CU_next_state_mux0012_0_8 : X_LUT4
generic map(
INIT => X"0200",
LOC => "SLICE_X22Y10"
)
port map (
ADR0 => CU_current_state(3),
ADR1 => exec_NOP_0,
ADR2 => exec_HLT,
ADR3 => exec_NOT,
O => CU_next_state_mux0012_0_8_4690
);
dec_s_exec_STA1 : X_LUT4
generic map(
INIT => X"0010",
LOC => "SLICE_X20Y13"
)
port map (
ADR0 => RI_reg(5),
ADR1 => RI_reg(7),
ADR2 => RI_reg(4),
ADR3 => RI_reg(6),
O => exec_STA_pack_1
);
CU_next_state_mux0012_4_11 : X_LUT4
generic map(
INIT => X"0202",
LOC => "SLICE_X20Y13"
)
port map (
ADR0 => CU_current_state(7),
ADR1 => CU_N7,
ADR2 => exec_STA,
ADR3 => VCC,
O => CU_N9
);
dec_s_exec_JN_cmp_eq00001 : X_LUT4
generic map(
INIT => X"0020",
LOC => "SLICE_X22Y18"
)
port map (
ADR0 => RI_reg(7),
ADR1 => RI_reg(5),
ADR2 => RI_reg(4),
ADR3 => RI_reg(6),
O => exec_JN_pack_1
);
CU_next_state_mux0012_4_111 : X_LUT4
generic map(
INIT => X"4F44",
LOC => "SLICE_X22Y18"
)
port map (
ADR0 => NZ_data_Z_1506,
ADR1 => exec_JZ,
ADR2 => NZ_data_N_1484,
ADR3 => exec_JN,
O => CU_next_state_mux0012_4_11_4738
);
alu_Z_cmp_eq000028 : X_LUT4
generic map(
INIT => X"0010",
LOC => "SLICE_X22Y30"
)
port map (
ADR0 => ULA_output(6),
ADR1 => ULA_N,
ADR2 => alu_Z_cmp_eq00007_0,
ADR3 => alu_Z_cmp_eq000028_SW0_O,
O => ULA_Z
);
NZ_data_Z : X_FF
generic map(
LOC => "SLICE_X22Y30",
INIT => '0'
)
port map (
I => NZ_data_Z_DXMUX_4771,
CE => NZ_data_Z_CEINV_4754,
CLK => NZ_data_Z_CLKINV_4755,
SET => GND,
RST => NZ_data_Z_FFX_RSTAND_4777,
O => NZ_data_Z_1506
);
NZ_data_Z_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => NZ_data_Z_FFX_RSTAND_4777
);
CU_next_state_mux0012_11_1 : X_LUT4
generic map(
INIT => X"EEAA",
LOC => "SLICE_X18Y9"
)
port map (
ADR0 => CU_current_state(1),
ADR1 => CU_next_state(2),
ADR2 => VCC,
ADR3 => CU_N9_0,
O => CU_next_state_mux0012(11)
);
CU_next_state_or000123 : X_LUT4
generic map(
INIT => X"0050",
LOC => "SLICE_X23Y12"
)
port map (
ADR0 => N30_0,
ADR1 => VCC,
ADR2 => RI_reg(7),
ADR3 => RI_reg(6),
O => CU_next_state_or0001_pack_1
);
CU_next_state_mux0012_5_SW0 : X_LUT4
generic map(
INIT => X"153F",
LOC => "SLICE_X23Y12"
)
port map (
ADR0 => CU_next_state(8),
ADR1 => CU_current_state(10),
ADR2 => CU_next_state_or0001,
ADR3 => CU_current_state(7),
O => N14
);
CU_next_state_mux0012_12_22 : X_LUT4
generic map(
INIT => X"3000",
LOC => "SLICE_X20Y11"
)
port map (
ADR0 => VCC,
ADR1 => exec_HLT,
ADR2 => exec_NOP_0,
ADR3 => CU_current_state(3),
O => CU_next_state_mux0012_12_22_O_pack_2
);
CU_next_state_mux0012_12_37 : X_LUT4
generic map(
INIT => X"FEFC",
LOC => "SLICE_X20Y11"
)
port map (
ADR0 => CU_next_state(1),
ADR1 => CU_next_state_mux0012_12_13_0,
ADR2 => CU_next_state_mux0012_12_22_O,
ADR3 => CU_N9_0,
O => CU_next_state_mux0012(12)
);
CU_next_state_1 : X_FF
generic map(
LOC => "SLICE_X20Y11",
INIT => '0'
)
port map (
I => CU_next_state_1_DXMUX_4831,
CE => VCC,
CLK => CU_next_state_1_CLKINV_4814,
SET => GND,
RST => CU_next_state_1_FFX_RSTAND_4836,
O => CU_next_state(1)
);
CU_next_state_1_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X20Y11",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_1_FFX_RSTAND_4836
);
dec_s_exec_JZ_cmp_eq00001 : X_LUT4
generic map(
INIT => X"1000",
LOC => "SLICE_X23Y19"
)
port map (
ADR0 => RI_reg(6),
ADR1 => RI_reg(4),
ADR2 => RI_reg(7),
ADR3 => RI_reg(5),
O => exec_JZ_pack_1
);
CU_next_state_mux0012_7_11 : X_LUT4
generic map(
INIT => X"C4F5",
LOC => "SLICE_X23Y19"
)
port map (
ADR0 => exec_JN,
ADR1 => NZ_data_Z_1506,
ADR2 => NZ_data_N_1484,
ADR3 => exec_JZ,
O => CU_next_state_mux0012_7_11_4859
);
CU_next_state_mux0012_13_21 : X_LUT4
generic map(
INIT => X"0001",
LOC => "SLICE_X25Y10"
)
port map (
ADR0 => CU_current_state(1),
ADR1 => CU_current_state(8),
ADR2 => CU_current_state(3),
ADR3 => CU_current_state(7),
O => CU_N10_pack_1
);
CU_loadRDM_mux000015 : X_LUT4
generic map(
INIT => X"0400",
LOC => "SLICE_X25Y10"
)
port map (
ADR0 => CU_current_state(13),
ADR1 => CU_N10,
ADR2 => CU_current_state(4),
ADR3 => CU_loadRDM_1452,
O => CU_loadRDM_mux000015_4883
);
dec_s_exec_HLT_cmp_eq00001 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X22Y11"
)
port map (
ADR0 => RI_reg(6),
ADR1 => RI_reg(7),
ADR2 => RI_reg(4),
ADR3 => RI_reg(5),
O => exec_HLT_pack_1
);
CU_next_state_mux0012_7_23 : X_LUT4
generic map(
INIT => X"0002",
LOC => "SLICE_X22Y11"
)
port map (
ADR0 => CU_current_state(3),
ADR1 => exec_NOP_0,
ADR2 => exec_HLT,
ADR3 => exec_NOT,
O => CU_next_state_mux0012_4_23
);
CU_next_state_mux0012_13_56 : X_LUT4
generic map(
INIT => X"BA30",
LOC => "SLICE_X22Y13"
)
port map (
ADR0 => CU_current_state(7),
ADR1 => CU_next_state_or0001,
ADR2 => CU_current_state(10),
ADR3 => CU_next_state(0),
O => CU_next_state_mux0012_13_56_O_pack_2
);
CU_next_state_mux0012_13_69 : X_LUT4
generic map(
INIT => X"FF10",
LOC => "SLICE_X22Y13"
)
port map (
ADR0 => CU_N7,
ADR1 => exec_STA,
ADR2 => CU_next_state_mux0012_13_56_O,
ADR3 => CU_next_state_mux0012_13_38,
O => CU_next_state_mux0012(13)
);
CU_next_state_0 : X_FF
generic map(
LOC => "SLICE_X22Y13",
INIT => '1'
)
port map (
I => CU_next_state_0_DXMUX_4938,
CE => VCC,
CLK => CU_next_state_0_CLKINV_4922,
SET => CU_next_state_0_FFX_SET,
RST => GND,
O => CU_next_state(0)
);
CU_next_state_0_FFX_SETOR : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_0_FFX_SET
);
CU_sel : X_FF
generic map(
LOC => "SLICE_X25Y13",
INIT => '0'
)
port map (
I => CU_sel_mux_RDM_DYMUX_4965,
CE => CU_sel_mux_RDM_CEINVNOT,
CLK => CU_sel_mux_RDM_CLKINV_4957,
SET => GND,
RST => GND,
O => CU_sel_1698
);
CU_sel_mux00001 : X_LUT4
generic map(
INIT => X"CCDC",
LOC => "SLICE_X25Y13"
)
port map (
ADR0 => CU_current_state(1),
ADR1 => CU_current_state(7),
ADR2 => CU_sel_1698,
ADR3 => CU_current_state(6),
O => CU_sel_mux0000
);
CU_sel_mux_RDM_mux00001 : X_LUT4
generic map(
INIT => X"FF04",
LOC => "SLICE_X25Y13"
)
port map (
ADR0 => CU_current_state(1),
ADR1 => CU_sel_mux_RDM_1453,
ADR2 => CU_current_state(4),
ADR3 => CU_current_state(5),
O => CU_sel_mux_RDM_mux0000
);
CU_sel_mux_RDM : X_FF
generic map(
LOC => "SLICE_X25Y13",
INIT => '0'
)
port map (
I => CU_sel_mux_RDM_DXMUX_4977,
CE => CU_sel_mux_RDM_CEINVNOT,
CLK => CU_sel_mux_RDM_CLKINV_4957,
SET => GND,
RST => GND,
O => CU_sel_mux_RDM_1453
);
mpx_S_0_1 : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X25Y21"
)
port map (
ADR0 => VCC,
ADR1 => CU_sel_1698,
ADR2 => PC_data(0),
ADR3 => R_D_M_reg(0),
O => MPX_output(0)
);
R_E_M_reg_0 : X_FF
generic map(
LOC => "SLICE_X25Y21",
INIT => '0'
)
port map (
I => R_E_M_reg_1_DYMUX_5004,
CE => R_E_M_reg_1_CEINV_4993,
CLK => R_E_M_reg_1_CLKINV_4994,
SET => GND,
RST => R_E_M_reg_1_SRINV_4995,
O => R_E_M_reg(0)
);
mpx_S_1_1 : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X25Y21"
)
port map (
ADR0 => PC_data(1),
ADR1 => CU_sel_1698,
ADR2 => VCC,
ADR3 => R_D_M_reg(1),
O => MPX_output(1)
);
R_E_M_reg_1 : X_FF
generic map(
LOC => "SLICE_X25Y21",
INIT => '0'
)
port map (
I => R_E_M_reg_1_DXMUX_5020,
CE => R_E_M_reg_1_CEINV_4993,
CLK => R_E_M_reg_1_CLKINV_4994,
SET => GND,
RST => R_E_M_reg_1_SRINV_4995,
O => R_E_M_reg(1)
);
mpx_S_2_1 : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X25Y20"
)
port map (
ADR0 => R_D_M_reg(2),
ADR1 => CU_sel_1698,
ADR2 => VCC,
ADR3 => PC_data(2),
O => MPX_output(2)
);
R_E_M_reg_2 : X_FF
generic map(
LOC => "SLICE_X25Y20",
INIT => '0'
)
port map (
I => R_E_M_reg_3_DYMUX_5050,
CE => R_E_M_reg_3_CEINV_5039,
CLK => R_E_M_reg_3_CLKINV_5040,
SET => GND,
RST => R_E_M_reg_3_SRINV_5041,
O => R_E_M_reg(2)
);
mpx_S_3_1 : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X25Y20"
)
port map (
ADR0 => VCC,
ADR1 => CU_sel_1698,
ADR2 => PC_data(3),
ADR3 => R_D_M_reg(3),
O => MPX_output(3)
);
R_E_M_reg_3 : X_FF
generic map(
LOC => "SLICE_X25Y20",
INIT => '0'
)
port map (
I => R_E_M_reg_3_DXMUX_5066,
CE => R_E_M_reg_3_CEINV_5039,
CLK => R_E_M_reg_3_CLKINV_5040,
SET => GND,
RST => R_E_M_reg_3_SRINV_5041,
O => R_E_M_reg(3)
);
mpx_S_4_1 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X24Y21"
)
port map (
ADR0 => CU_sel_1698,
ADR1 => VCC,
ADR2 => R_D_M_reg(4),
ADR3 => PC_data(4),
O => MPX_output(4)
);
R_E_M_reg_4 : X_FF
generic map(
LOC => "SLICE_X24Y21",
INIT => '0'
)
port map (
I => R_E_M_reg_5_DYMUX_5096,
CE => R_E_M_reg_5_CEINV_5085,
CLK => R_E_M_reg_5_CLKINV_5086,
SET => GND,
RST => R_E_M_reg_5_SRINV_5087,
O => R_E_M_reg(4)
);
mpx_S_5_1 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X24Y21"
)
port map (
ADR0 => R_D_M_reg(5),
ADR1 => VCC,
ADR2 => CU_sel_1698,
ADR3 => PC_data(5),
O => MPX_output(5)
);
R_E_M_reg_5 : X_FF
generic map(
LOC => "SLICE_X24Y21",
INIT => '0'
)
port map (
I => R_E_M_reg_5_DXMUX_5112,
CE => R_E_M_reg_5_CEINV_5085,
CLK => R_E_M_reg_5_CLKINV_5086,
SET => GND,
RST => R_E_M_reg_5_SRINV_5087,
O => R_E_M_reg(5)
);
mpx_S_6_1 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X24Y22"
)
port map (
ADR0 => R_D_M_reg(6),
ADR1 => PC_data(6),
ADR2 => CU_sel_1698,
ADR3 => VCC,
O => MPX_output(6)
);
R_E_M_reg_6 : X_FF
generic map(
LOC => "SLICE_X24Y22",
INIT => '0'
)
port map (
I => R_E_M_reg_7_DYMUX_5142,
CE => R_E_M_reg_7_CEINV_5131,
CLK => R_E_M_reg_7_CLKINV_5132,
SET => GND,
RST => R_E_M_reg_7_SRINV_5133,
O => R_E_M_reg(6)
);
mpx_S_7_1 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X24Y22"
)
port map (
ADR0 => VCC,
ADR1 => R_D_M_reg(7),
ADR2 => CU_sel_1698,
ADR3 => PC_data(7),
O => MPX_output(7)
);
R_E_M_reg_7 : X_FF
generic map(
LOC => "SLICE_X24Y22",
INIT => '0'
)
port map (
I => R_E_M_reg_7_DXMUX_5158,
CE => R_E_M_reg_7_CEINV_5131,
CLK => R_E_M_reg_7_CLKINV_5132,
SET => GND,
RST => R_E_M_reg_7_SRINV_5133,
O => R_E_M_reg(7)
);
CU_Mcount_state_timer_eqn_01 : X_LUT4
generic map(
INIT => X"FAFA",
LOC => "SLICE_X0Y18"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => VCC,
ADR2 => CU_Result(0),
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_0
);
CU_state_timer_0 : X_FF
generic map(
LOC => "SLICE_X0Y18",
INIT => '1'
)
port map (
I => CU_state_timer_1_DYMUX_5185,
CE => VCC,
CLK => CU_state_timer_1_CLKINV_5174,
SET => CU_state_timer_1_SRINV_5175,
RST => GND,
O => CU_state_timer(0)
);
CU_Mcount_state_timer_eqn_110 : X_LUT4
generic map(
INIT => X"4444",
LOC => "SLICE_X0Y18"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => CU_Result(1),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_1
);
CU_state_timer_1 : X_FF
generic map(
LOC => "SLICE_X0Y18",
INIT => '0'
)
port map (
I => CU_state_timer_1_DXMUX_5200,
CE => VCC,
CLK => CU_state_timer_1_CLKINV_5174,
SET => GND,
RST => CU_state_timer_1_SRINV_5175,
O => CU_state_timer(1)
);
CU_Mcount_state_timer_eqn_210 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X2Y19"
)
port map (
ADR0 => VCC,
ADR1 => CU_Result(2),
ADR2 => VCC,
ADR3 => CU_state_timer_not0001_inv,
O => CU_Mcount_state_timer_eqn_2
);
CU_state_timer_2 : X_FF
generic map(
LOC => "SLICE_X2Y19",
INIT => '0'
)
port map (
I => CU_state_timer_3_DYMUX_5226,
CE => VCC,
CLK => CU_state_timer_3_CLKINV_5215,
SET => GND,
RST => CU_state_timer_3_SRINV_5216,
O => CU_state_timer(2)
);
CU_Mcount_state_timer_eqn_32 : X_LUT4
generic map(
INIT => X"00AA",
LOC => "SLICE_X2Y19"
)
port map (
ADR0 => CU_Result(3),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_state_timer_not0001_inv,
O => CU_Mcount_state_timer_eqn_3
);
CU_state_timer_3 : X_FF
generic map(
LOC => "SLICE_X2Y19",
INIT => '0'
)
port map (
I => CU_state_timer_3_DXMUX_5242,
CE => VCC,
CLK => CU_state_timer_3_CLKINV_5215,
SET => GND,
RST => CU_state_timer_3_SRINV_5216,
O => CU_state_timer(3)
);
CU_Mcount_state_timer_eqn_101 : X_LUT4
generic map(
INIT => X"2222",
LOC => "SLICE_X3Y18"
)
port map (
ADR0 => CU_Result(10),
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_10
);
CU_state_timer_10 : X_FF
generic map(
LOC => "SLICE_X3Y18",
INIT => '0'
)
port map (
I => CU_state_timer_11_DYMUX_5268,
CE => VCC,
CLK => CU_state_timer_11_CLKINV_5257,
SET => GND,
RST => CU_state_timer_11_SRINV_5258,
O => CU_state_timer(10)
);
CU_Mcount_state_timer_eqn_111 : X_LUT4
generic map(
INIT => X"4444",
LOC => "SLICE_X3Y18"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => CU_Result(11),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_11
);
CU_state_timer_11 : X_FF
generic map(
LOC => "SLICE_X3Y18",
INIT => '0'
)
port map (
I => CU_state_timer_11_DXMUX_5284,
CE => VCC,
CLK => CU_state_timer_11_CLKINV_5257,
SET => GND,
RST => CU_state_timer_11_SRINV_5258,
O => CU_state_timer(11)
);
CU_Mcount_state_timer_eqn_41 : X_LUT4
generic map(
INIT => X"5050",
LOC => "SLICE_X2Y21"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => VCC,
ADR2 => CU_Result(4),
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_4
);
CU_state_timer_4 : X_FF
generic map(
LOC => "SLICE_X2Y21",
INIT => '0'
)
port map (
I => CU_state_timer_5_DYMUX_5310,
CE => VCC,
CLK => CU_state_timer_5_CLKINV_5299,
SET => GND,
RST => CU_state_timer_5_SRINV_5300,
O => CU_state_timer(4)
);
CU_Mcount_state_timer_eqn_51 : X_LUT4
generic map(
INIT => X"5500",
LOC => "SLICE_X2Y21"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_Result(5),
O => CU_Mcount_state_timer_eqn_5
);
CU_state_timer_5 : X_FF
generic map(
LOC => "SLICE_X2Y21",
INIT => '0'
)
port map (
I => CU_state_timer_5_DXMUX_5326,
CE => VCC,
CLK => CU_state_timer_5_CLKINV_5299,
SET => GND,
RST => CU_state_timer_5_SRINV_5300,
O => CU_state_timer(5)
);
CU_Mcount_state_timer_eqn_121 : X_LUT4
generic map(
INIT => X"4444",
LOC => "SLICE_X0Y22"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => CU_Result(12),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_12
);
CU_state_timer_12 : X_FF
generic map(
LOC => "SLICE_X0Y22",
INIT => '0'
)
port map (
I => CU_state_timer_13_DYMUX_5352,
CE => VCC,
CLK => CU_state_timer_13_CLKINV_5341,
SET => GND,
RST => CU_state_timer_13_SRINV_5342,
O => CU_state_timer(12)
);
CU_Mcount_state_timer_eqn_131 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X0Y22"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(13),
O => CU_Mcount_state_timer_eqn_13
);
CU_state_timer_13 : X_FF
generic map(
LOC => "SLICE_X0Y22",
INIT => '0'
)
port map (
I => CU_state_timer_13_DXMUX_5368,
CE => VCC,
CLK => CU_state_timer_13_CLKINV_5341,
SET => GND,
RST => CU_state_timer_13_SRINV_5342,
O => CU_state_timer(13)
);
CU_Mcount_state_timer_eqn_201 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X0Y23"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(20),
O => CU_Mcount_state_timer_eqn_20
);
CU_state_timer_20 : X_FF
generic map(
LOC => "SLICE_X0Y23",
INIT => '0'
)
port map (
I => CU_state_timer_21_DYMUX_5394,
CE => VCC,
CLK => CU_state_timer_21_CLKINV_5383,
SET => GND,
RST => CU_state_timer_21_SRINV_5384,
O => CU_state_timer(20)
);
CU_Mcount_state_timer_eqn_211 : X_LUT4
generic map(
INIT => X"3030",
LOC => "SLICE_X0Y23"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => CU_Result(21),
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_21
);
CU_state_timer_21 : X_FF
generic map(
LOC => "SLICE_X0Y23",
INIT => '0'
)
port map (
I => CU_state_timer_21_DXMUX_5410,
CE => VCC,
CLK => CU_state_timer_21_CLKINV_5383,
SET => GND,
RST => CU_state_timer_21_SRINV_5384,
O => CU_state_timer(21)
);
CU_Mcount_state_timer_eqn_61 : X_LUT4
generic map(
INIT => X"5500",
LOC => "SLICE_X0Y21"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_Result(6),
O => CU_Mcount_state_timer_eqn_6
);
CU_state_timer_6 : X_FF
generic map(
LOC => "SLICE_X0Y21",
INIT => '0'
)
port map (
I => CU_state_timer_7_DYMUX_5436,
CE => VCC,
CLK => CU_state_timer_7_CLKINV_5425,
SET => GND,
RST => CU_state_timer_7_SRINV_5426,
O => CU_state_timer(6)
);
CU_Mcount_state_timer_eqn_71 : X_LUT4
generic map(
INIT => X"2222",
LOC => "SLICE_X0Y21"
)
port map (
ADR0 => CU_Result(7),
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_7
);
CU_state_timer_7 : X_FF
generic map(
LOC => "SLICE_X0Y21",
INIT => '0'
)
port map (
I => CU_state_timer_7_DXMUX_5452,
CE => VCC,
CLK => CU_state_timer_7_CLKINV_5425,
SET => GND,
RST => CU_state_timer_7_SRINV_5426,
O => CU_state_timer(7)
);
CU_Mcount_state_timer_eqn_141 : X_LUT4
generic map(
INIT => X"4444",
LOC => "SLICE_X2Y20"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => CU_Result(14),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_14
);
CU_state_timer_14 : X_FF
generic map(
LOC => "SLICE_X2Y20",
INIT => '0'
)
port map (
I => CU_state_timer_15_DYMUX_5478,
CE => VCC,
CLK => CU_state_timer_15_CLKINV_5467,
SET => GND,
RST => CU_state_timer_15_SRINV_5468,
O => CU_state_timer(14)
);
CU_Mcount_state_timer_eqn_151 : X_LUT4
generic map(
INIT => X"5050",
LOC => "SLICE_X2Y20"
)
port map (
ADR0 => CU_state_timer_not0001_inv,
ADR1 => VCC,
ADR2 => CU_Result(15),
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_15
);
CU_state_timer_15 : X_FF
generic map(
LOC => "SLICE_X2Y20",
INIT => '0'
)
port map (
I => CU_state_timer_15_DXMUX_5494,
CE => VCC,
CLK => CU_state_timer_15_CLKINV_5467,
SET => GND,
RST => CU_state_timer_15_SRINV_5468,
O => CU_state_timer(15)
);
CU_Mcount_state_timer_eqn_221 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X0Y24"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(22),
O => CU_Mcount_state_timer_eqn_22
);
CU_state_timer_22 : X_FF
generic map(
LOC => "SLICE_X0Y24",
INIT => '0'
)
port map (
I => CU_state_timer_23_DYMUX_5520,
CE => VCC,
CLK => CU_state_timer_23_CLKINV_5509,
SET => GND,
RST => CU_state_timer_23_SRINV_5510,
O => CU_state_timer(22)
);
CU_Mcount_state_timer_eqn_231 : X_LUT4
generic map(
INIT => X"00AA",
LOC => "SLICE_X0Y24"
)
port map (
ADR0 => CU_Result(23),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => CU_state_timer_not0001_inv,
O => CU_Mcount_state_timer_eqn_23
);
CU_state_timer_23 : X_FF
generic map(
LOC => "SLICE_X0Y24",
INIT => '0'
)
port map (
I => CU_state_timer_23_DXMUX_5536,
CE => VCC,
CLK => CU_state_timer_23_CLKINV_5509,
SET => GND,
RST => CU_state_timer_23_SRINV_5510,
O => CU_state_timer(23)
);
CU_Mcount_state_timer_eqn_301 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X0Y26"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(30),
O => CU_Mcount_state_timer_eqn_30
);
CU_state_timer_30 : X_FF
generic map(
LOC => "SLICE_X0Y26",
INIT => '0'
)
port map (
I => CU_state_timer_31_DYMUX_5562,
CE => VCC,
CLK => CU_state_timer_31_CLKINV_5551,
SET => GND,
RST => CU_state_timer_31_SRINV_5552,
O => CU_state_timer(30)
);
CU_Mcount_state_timer_eqn_311 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X0Y26"
)
port map (
ADR0 => VCC,
ADR1 => CU_Result(31),
ADR2 => VCC,
ADR3 => CU_state_timer_not0001_inv,
O => CU_Mcount_state_timer_eqn_31
);
CU_state_timer_31 : X_FF
generic map(
LOC => "SLICE_X0Y26",
INIT => '0'
)
port map (
I => CU_state_timer_31_DXMUX_5578,
CE => VCC,
CLK => CU_state_timer_31_CLKINV_5551,
SET => GND,
RST => CU_state_timer_31_SRINV_5552,
O => CU_state_timer(31)
);
CU_Mcount_state_timer_eqn_81 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X2Y18"
)
port map (
ADR0 => VCC,
ADR1 => CU_Result(8),
ADR2 => VCC,
ADR3 => CU_state_timer_not0001_inv,
O => CU_Mcount_state_timer_eqn_8
);
CU_state_timer_8 : X_FF
generic map(
LOC => "SLICE_X2Y18",
INIT => '0'
)
port map (
I => CU_state_timer_9_DYMUX_5604,
CE => VCC,
CLK => CU_state_timer_9_CLKINV_5593,
SET => GND,
RST => CU_state_timer_9_SRINV_5594,
O => CU_state_timer(8)
);
CU_Mcount_state_timer_eqn_91 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X2Y18"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(9),
O => CU_Mcount_state_timer_eqn_9
);
CU_state_timer_9 : X_FF
generic map(
LOC => "SLICE_X2Y18",
INIT => '0'
)
port map (
I => CU_state_timer_9_DXMUX_5620,
CE => VCC,
CLK => CU_state_timer_9_CLKINV_5593,
SET => GND,
RST => CU_state_timer_9_SRINV_5594,
O => CU_state_timer(9)
);
CU_Mcount_state_timer_eqn_161 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X0Y20"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => VCC,
ADR3 => CU_Result(16),
O => CU_Mcount_state_timer_eqn_16
);
CU_state_timer_16 : X_FF
generic map(
LOC => "SLICE_X0Y20",
INIT => '0'
)
port map (
I => CU_state_timer_17_DYMUX_5646,
CE => VCC,
CLK => CU_state_timer_17_CLKINV_5635,
SET => GND,
RST => CU_state_timer_17_SRINV_5636,
O => CU_state_timer(16)
);
CU_Mcount_state_timer_eqn_171 : X_LUT4
generic map(
INIT => X"3030",
LOC => "SLICE_X0Y20"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer_not0001_inv,
ADR2 => CU_Result(17),
ADR3 => VCC,
O => CU_Mcount_state_timer_eqn_17
);
CU_state_timer_17 : X_FF
generic map(
LOC => "SLICE_X0Y20",
INIT => '0'
)
port map (
I => CU_state_timer_17_DXMUX_5662,
CE => VCC,
CLK => CU_state_timer_17_CLKINV_5635,
SET => GND,
RST => CU_state_timer_17_SRINV_5636,
O => CU_state_timer(17)
);
CU_next_state_3 : X_FF
generic map(
LOC => "SLICE_X18Y9",
INIT => '0'
)
port map (
I => CU_next_state_3_DXMUX_5872,
CE => VCC,
CLK => CU_next_state_3_CLKINV_5847,
SET => GND,
RST => CU_next_state_3_SRINV_5848,
O => CU_next_state(3)
);
CU_next_state_mux0012_9_1 : X_LUT4
generic map(
INIT => X"EECC",
LOC => "SLICE_X19Y10"
)
port map (
ADR0 => CU_N9_0,
ADR1 => CU_current_state(5),
ADR2 => VCC,
ADR3 => CU_next_state(4),
O => CU_next_state_mux0012(9)
);
CU_next_state_4 : X_FF
generic map(
LOC => "SLICE_X19Y10",
INIT => '0'
)
port map (
I => CU_next_state_5_DYMUX_5900,
CE => VCC,
CLK => CU_next_state_5_CLKINV_5890,
SET => GND,
RST => CU_next_state_5_SRINV_5891,
O => CU_next_state(4)
);
CU_next_state_mux0012_8_1 : X_LUT4
generic map(
INIT => X"5400",
LOC => "SLICE_X19Y10"
)
port map (
ADR0 => CU_N7,
ADR1 => exec_STA,
ADR2 => CU_next_state(5),
ADR3 => CU_current_state(7),
O => CU_next_state_mux0012(8)
);
CU_next_state_5 : X_FF
generic map(
LOC => "SLICE_X19Y10",
INIT => '0'
)
port map (
I => CU_next_state_5_DXMUX_5914,
CE => VCC,
CLK => CU_next_state_5_CLKINV_5890,
SET => GND,
RST => CU_next_state_5_SRINV_5891,
O => CU_next_state(5)
);
CU_loadAC_mux00001 : X_LUT4
generic map(
INIT => X"BBAA",
LOC => "SLICE_X24Y17"
)
port map (
ADR0 => CU_current_state(13),
ADR1 => CU_current_state(1),
ADR2 => VCC,
ADR3 => CU_loadAC_1652,
O => CU_loadAC_mux0000
);
CU_loadAC : X_FF
generic map(
LOC => "SLICE_X24Y17",
INIT => '0'
)
port map (
I => CU_loadAC_DYMUX_5937,
CE => VCC,
CLK => CU_loadAC_CLKINV_5927,
SET => GND,
RST => CU_loadAC_FFY_RSTAND_5942,
O => CU_loadAC_1652
);
CU_loadAC_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X24Y17",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_loadAC_FFY_RSTAND_5942
);
CU_next_state_mux0012_7_37 : X_LUT4
generic map(
INIT => X"F888",
LOC => "SLICE_X18Y13"
)
port map (
ADR0 => CU_next_state_mux0012_7_11_0,
ADR1 => CU_next_state_mux0012_4_23_0,
ADR2 => CU_N9_0,
ADR3 => CU_next_state(6),
O => CU_next_state_mux0012(7)
);
CU_next_state_6 : X_FF
generic map(
LOC => "SLICE_X18Y13",
INIT => '0'
)
port map (
I => CU_next_state_6_DYMUX_5960,
CE => VCC,
CLK => CU_next_state_6_CLKINV_5951,
SET => GND,
RST => CU_next_state_6_FFY_RSTAND_5965,
O => CU_next_state(6)
);
CU_next_state_6_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X18Y13",
PATHPULSE => 638 ps
)
port map (
I => rst_IBUF_1438,
O => CU_next_state_6_FFY_RSTAND_5965
);
CU_next_state_mux0012_5_Q : X_LUT4
generic map(
INIT => X"0005",
LOC => "SLICE_X23Y14"
)
port map (
ADR0 => CU_N7,
ADR1 => VCC,
ADR2 => exec_STA,
ADR3 => N14_0,
O => CU_next_state_mux0012(5)
);
CU_next_state_8 : X_FF
generic map(
LOC => "SLICE_X23Y14",
INIT => '0'
)
port map (
I => CU_next_state_9_DYMUX_5988,
CE => VCC,
CLK => CU_next_state_9_CLKINV_5978,
SET => GND,
RST => CU_next_state_9_SRINV_5979,
O => CU_next_state(8)
);
CU_next_state_mux0012_4_37 : X_LUT4
generic map(
INIT => X"ECA0",
LOC => "SLICE_X23Y14"
)
port map (
ADR0 => CU_N9_0,
ADR1 => CU_next_state_mux0012_4_23_0,
ADR2 => CU_next_state(9),
ADR3 => CU_next_state_mux0012_4_11_0,
O => CU_next_state_mux0012(4)
);
CU_next_state_9 : X_FF
generic map(
LOC => "SLICE_X23Y14",
INIT => '0'
)
port map (
I => CU_next_state_9_DXMUX_6002,
CE => VCC,
CLK => CU_next_state_9_CLKINV_5978,
SET => GND,
RST => CU_next_state_9_SRINV_5979,
O => CU_next_state(9)
);
CU_Result_0_F_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X1Y18"
)
port map (
ADR0 => VCC,
ADR1 => CU_state_timer(0),
ADR2 => VCC,
ADR3 => VCC,
O => CU_Result_0_F
);
debug_out_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD48",
PATHPULSE => 638 ps
)
port map (
I => CU_stop_s_1511,
O => debug_out_O
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_17_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(17)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_16_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(16)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_15_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(15)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_14_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(14)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_13_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(13)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_12_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(12)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_11_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(11)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_10_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(10)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_9_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(9)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_8_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(8)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_7_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => NZ_data_N_1484,
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(7)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_6_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => AC_reg(6),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(6)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_5_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => AC_reg(5),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(5)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_4_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => AC_reg(4),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(4)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_3_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => AC_reg(3),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(3)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_2_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => AC_reg(2),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(2)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_1_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => AC_reg(1),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(1)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_A_0_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => AC_reg(0),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_A(0)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_17_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(17)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_16_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(16)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_15_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(15)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_14_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(14)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_13_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(13)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_12_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(12)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_11_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(11)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_10_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(10)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_9_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(9)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_8_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(8)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_7_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(7)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_6_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(6),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(6)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_5_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(5),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(5)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_4_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(4),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(4)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_3_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(3),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(3)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_2_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(2),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(2)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_1_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(1),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(1)
);
NlwBufferBlock_alu_Mmult_MULTIPLICATION_mult0000_B_0_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(0),
O => NlwBufferSignal_alu_Mmult_MULTIPLICATION_mult0000_B(0)
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_7_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(7),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_7_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_6_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(6),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_6_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_5_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(5),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_5_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_4_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(4),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_4_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_3_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(3),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_3_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_2_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(2),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_2_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_1_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(1),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_1_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_0_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_E_M_reg(0),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_ADDRA_0_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_0_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(0),
O => NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_0_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_1_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(1),
O => NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_1_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_8_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(2),
O => NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_8_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_9_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(3),
O => NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_9_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_16_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(4),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_16_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_17_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(5),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_17_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_24_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(6),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_24_Q
);
NlwBufferBlock_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_25_Q : X_BUF
generic map(
PATHPULSE => 638 ps
)
port map (
I => R_D_M_reg(7),
O =>
NlwBufferSignal_MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s3_init_ram_dpram_dp36x36_ram_DIA_25_Q
);
NlwBlock_neander_VCC : X_ONE
port map (
O => VCC
);
NlwBlock_neander_GND : X_ZERO
port map (
O => GND
);
NlwInverterBlock_alu_MULTIPLICATION_1_CLK : X_INV
port map (
I => alu_MULTIPLICATION_1_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_1_CLK
);
NlwInverterBlock_alu_MULTIPLICATION_2_CLK : X_INV
port map (
I => alu_MULTIPLICATION_3_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_2_CLK
);
NlwInverterBlock_alu_MULTIPLICATION_0_CLK : X_INV
port map (
I => alu_MULTIPLICATION_1_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_0_CLK
);
NlwInverterBlock_alu_MULTIPLICATION_3_CLK : X_INV
port map (
I => alu_MULTIPLICATION_3_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_3_CLK
);
NlwInverterBlock_alu_MULTIPLICATION_4_CLK : X_INV
port map (
I => alu_MULTIPLICATION_5_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_4_CLK
);
NlwInverterBlock_alu_MULTIPLICATION_5_CLK : X_INV
port map (
I => alu_MULTIPLICATION_5_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_5_CLK
);
NlwInverterBlock_alu_MULTIPLICATION_6_CLK : X_INV
port map (
I => alu_MULTIPLICATION_7_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_6_CLK
);
NlwInverterBlock_alu_MULTIPLICATION_7_CLK : X_INV
port map (
I => alu_MULTIPLICATION_7_CLKINVNOT,
O => NlwInverterSignal_alu_MULTIPLICATION_7_CLK
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| mit | e01203d048a7225aaa32413daa8918d5 | 0.574723 | 2.832837 | false | false | false | false |
plessl/zippy | vhdl/routel.vhd | 1 | 5,357 | ------------------------------------------------------------------------------
-- ZIPPY routing element (8 inputs, 1 output, 3 tristate outputs)
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/routel.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/09/06
-- $Id: routel.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- Routing element in engine. Route input data from interconnect to
-- processing element.
-- Each routing element has 8 inputs (local interconect and bus taps) and
-- 1 output that can be connected to the neighbor cells direct inputs as well
-- as 3 outputs with tristate buffers (that are used to drive the south buses).
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
entity RoutEl is
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ConfigxI : in routConfigRec;
-- access to routing
InputxDI : in cellInputRec;
OutputxZO : out CellOutputRec;
-- access to processing element
ProcElInxDO : out procelInputArray; -- inputs to processing element
ProcElOutxDI : in std_logic_vector(DATAWIDTH-1 downto 0)); -- output of PE
end RoutEl;
architecture simple of RoutEl is
begin -- simple
-----------------------------------------------------------------------------
-- INPUT DRIVERS to processing element
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Generate input drivers that drive the cell inputs signals to the
-- processing element inputs. The desired input for a procel input is
-- selected by enabling tristate buffers on a bus (not with a multiplexer, as
-- used in the initial versions of the code)
-----------------------------------------------------------------------------
gen_inputdrivers : for inp in ConfigxI.i'range generate
-- generate drivers for local interconnect inputs
gen_local : for localcon in ConfigxI.i(inp).LocalxE'range generate
localcondrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.LocalxDI(localcon),
OExEI => ConfigxI.i(inp).LocalxE(localcon),
OutxZO => ProcelInxDO(inp)
);
end generate gen_local;
-- generate drivers for HBusN inputs
gen_hbusn : for hbusn in ConfigxI.i(inp).HBusNxE'range generate
hbusndrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.HBusNxDI(hbusn),
OExEI => ConfigxI.i(inp).HBusNxE(hbusn),
OutxZO => ProcelInxDO(inp)
);
end generate gen_hbusn;
-- generate drivers for HBusS inputs
gen_hbuss : for hbuss in ConfigxI.i(inp).HBusSxE'range generate
hbussdrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.HBusSxDI(hbuss),
OExEI => ConfigxI.i(inp).HBusSxE(hbuss),
OutxZO => ProcelInxDO(inp)
);
end generate gen_hbuss;
-- generate drivers for VBusE inputs
gen_vbuse : for vbuse in ConfigxI.i(inp).VBusExE'range generate
vbusedrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.VBusExDI(vbuse),
OExEI => ConfigxI.i(inp).VBusExE(vbuse),
OutxZO => ProcelInxDO(inp)
);
end generate gen_vbuse;
end generate gen_inputdrivers;
-----------------------------------------------------------------------------
-- OUTPUT DRIVERS from processing elements
-----------------------------------------------------------------------------
-- direct output path
OutputxZO.LocalxDO <= ProcElOutxDI;
-- generate drivers for HBusN outputs
gen_drvouthbusn : for hbusn in ConfigxI.o.HBusNxE'range generate
hbusndrvout : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => ProcElOutxDI,
OExEI => ConfigxI.o.HBusNxE(hbusn),
OutxZO => OutputxZO.HBusNxDZ(hbusn)
);
end generate gen_drvouthbusn;
-- generate drivers for HBusS outputs
gen_drvouthbuss : for hbuss in ConfigxI.o.HBusSxE'range generate
hbussdrvout : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => ProcElOUtxDI,
OExEI => ConfigxI.o.HBusSxE(hbuss),
OutxZO => OutputxZO.HBusSxDZ(hbuss)
);
end generate gen_drvouthbuss;
-- generate drivers for VBusE inputs
gen_drvoutvbuse : for vbuse in ConfigxI.o.VBusExE'range generate
vbusedrvout : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => ProcElOUtxDI,
OExEI => ConfigxI.o.VBusExE(vbuse),
OutxZO => OutputxZO.VBusExDZ(vbuse)
);
end generate gen_drvoutvbuse;
end simple;
| bsd-3-clause | 6f39bced5c6cecde715971446ca86973 | 0.557775 | 3.947679 | false | true | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/reg8.vhd | 1 | 926 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 23:58:40 05/02/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg8bits is
port (
data_in : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
load : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end reg8bits;
architecture Behavioral of reg8bits is
signal reg : std_logic_vector (7 downto 0);
constant reg_delay: TIME := 2 ns;
begin
process (clk, rst)
begin
if (rst = '1') then
reg <= "00000000";
elsif (clk = '1' and clk'EVENT) then
if (load = '1') then
reg <= data_in;
end if;
end if;
end process;
data_out <= reg;
end Behavioral; | mit | 3f2cb8023da081ba7032b248b87f6774 | 0.656587 | 2.772455 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_pull.vhd | 1 | 2,632 | library ieee;
use ieee.std_logic_1164.all;
use work.AuxPkg.all;
use work.ComponentsPkg.all;
entity tb_Pull is
end tb_Pull;
architecture arch of tb_Pull is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, pull_up, pull_down, partbus);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal ModexS : std_logic;
signal BusxZ : std_logic_vector(WIDTH-1 downto 0) := (others => 'Z');
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : PullBus
generic map (
WIDTH => WIDTH)
port map (
ModexSI => ModexS,
BusxZO => BusxZ);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
ModexS <= '0';
BusxZ <= (others => 'Z');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= pull_up;
ModexS <= '1';
wait for CLK_PERIOD;
tbStatus <= pull_down;
ModexS <= '0';
wait for CLK_PERIOD;
tbStatus <= partbus;
BusxZ <= (5 downto 4 => '1', 2 downto 1 => '0', others => 'Z');
wait for CLK_PERIOD;
tbStatus <= idle;
ModexS <= '0';
BusxZ <= (others => 'Z');
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 466f2186fbce334f235953019087b5f2 | 0.459347 | 4.286645 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/tbdAudioCodecAvalon/hdl/TbdAudioCodecAvalon-Struct-a.vhd | 1 | 1,368 | architecture Struct of TbdAudioCodecAvalon is
component Audio is
port (
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_clk : in std_logic := 'X'; -- clk
audio_clk_clk : out std_logic; -- clk
i2s_adcdat : in std_logic := 'X'; -- adcdat
i2s_adclrck : in std_logic := 'X'; -- adclrck
i2s_bclk : in std_logic := 'X'; -- bclk
i2s_dacdat : out std_logic; -- dacdat
i2s_daclrck : in std_logic := 'X'; -- daclrck
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic -- SCLK
);
end component Audio;
begin -- architecture Struct
u0 : component Audio
port map (
reset_reset_n => KEY(0), -- reset.reset_n
clk_clk => CLOCK_50, -- clk.clk
audio_clk_clk => AUD_XCK, -- audio_clk.clk
i2s_adcdat => AUD_ADCDAT, -- i2s.adcdat
i2s_adclrck => AUD_ADCLRCK, -- .adclrck
i2s_bclk => AUD_BCLK, -- .bclk
i2s_dacdat => AUD_DACDAT, -- .dacdat
i2s_daclrck => AUD_DACLRCK, -- .daclrck
i2c_SDAT => FPGA_I2C_SDAT, -- i2c.SDAT
i2c_SCLK => FPGA_I2C_SCLK -- .SCLK
);
end architecture Struct;
| gpl-3.0 | a6f6e8bdba1aefa23ccd446292ad8a28 | 0.466374 | 3.196262 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPackages/pkgToString/src/tostring_pkg.vhd | 1 | 2,033 | library ieee;
use ieee.std_logic_1164.all;
package ToStringPkg is
function to_character (
a : std_ulogic
) return character;
function to_string (
a : std_ulogic_vector
) return string;
end ToStringPkg;
package body ToStringPkg is
---------------------------------------------------------------------------
-- converting a std_ulogic_vector to a string
---------------------------------------------------------------------------
function to_character (
a : std_ulogic
) return character is
variable a_char : character;
begin
case a is
when 'U' => a_char := 'U';
when 'X' => a_char := 'X';
when '0' => a_char := '0';
when '1' => a_char := '1';
when 'W' => a_char := 'W';
when 'L' => a_char := 'L';
when 'H' => a_char := 'H';
when 'Z' => a_char := 'Z';
when '-' => a_char := '-';
end case;
return a_char;
end to_character;
function to_string (
a : std_ulogic_vector
) return string is
constant a_length : integer := a'length;
variable a_str : string(1 to a'length);
variable a_copy : std_ulogic_vector(a'length-1 downto 0) := a;
-- a copy is made of a because a may not use a 0-based index,
-- it could be 7 downto 4, for example
begin
-- convert each bit of the vector to a char
for i in 1 to a'length loop
-- conversion is done by assigning from the msb of a_copy from the
-- left downto the lsb so that the textual "image" of a_str follows
-- that of a_copy and thus a itself. Without the length-i trick
-- a_copy would effectively be reversed onto a_str as a_str is declared
-- with a "to" range as opposed to a_copy's downto range.
a_str(i) := to_character(std_ulogic(a_copy(a_length-i)));
end loop;
return a_str;
end;
end ToStringPkg;
| gpl-3.0 | c25fd3a06fce4bf6271b3db9cae6e705 | 0.497787 | 3.955253 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstor/tb_tstor.vhd | 1 | 11,661 | ------------------------------------------------------------------------------
-- Testbench for the alu_or function of the zunit
--
-- Project :
-- File : tb_tstor.vhd
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/22
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- This testbench tests the alu_or function of the zunit.
--
-- The primary goal of this testbench is to provide an example of a testbench
-- that can be used for standalone simulation and co-simulation to verify the
-- correct function of the zunit.
--
-- There a 2 main purposes of the testbench:
-- a) specific testing of newly added components and features
-- b) regression testing of the whole architecture
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-22 CP created (based on the tb_zarch testbench by Rolf Enzler)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTOR.all;
entity tb_tstor is
end tb_tstor;
architecture arch of tb_tstor is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 8; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec :=
tstorcfg;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstor_cfg.h";
type fifo_array is array (0 to (3*NDATA)-1) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------
-- test vectors
-- out = a or b
-- array contains: contents for fifo0, contents for fifo1, expected result
-----------------------------------------------------------------------------
constant TESTV : fifo_array :=
( x"1111", x"8888", x"9999",
x"7DA5", x"8208", x"FFAD",
x"D5D8", x"B020", x"F5F8",
x"1234", x"5678", x"567C",
x"AFFE", x"CAFE", x"EFFE",
x"1234", x"4321", x"5335",
x"B0E0", x"0E0F", x"BEEF",
x"ABBA", x"FEED", x"FFFF"
);
-- b"0000_0000_0000_0000", -- a 0000
-- b"0000_1111_0000_1111", -- b 0F0F
-- b"0000_1111_0000_1111", -- out 0F0F
--
-- b"0000_0000_0000_0000", -- a 0000
-- b"0000_0000_0000_0000", -- b 0000
-- b"0000_0000_0000_0000", -- out 0000
--
-- b"0111_1101_1010_0101", -- a 7DA5
-- b"1000_0010_0000_1000", -- b 8208
-- b"1111_1111_1010_1101", -- out FFAD
--
-- b"1101_0101_1101_1000", -- a D5D8
-- b"1011_0000_0010_0000", -- b B020
-- b"1111_0101_1111_1000" -- out F5F8
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(15 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(15 downto 0) := (others => '0');
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- -----------------------------------------------
-- reset (ZREG_RST:W)
-- -----------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-- -----------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3);
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i*3))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- push data into FIFO1 (ZREG_FIFO1:W)
-- -----------------------------------------------
tbStatus <= push_data_fifo1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3+1);
-- assert false
-- report "writing to FIFO1:" & hstr(TESTV(i*3+1))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-- -----------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-- -----------------------------------------------
-- computation running
-- -----------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
-- -----------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-- -----------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := TESTV(3*i+2);
response := DataOutxD(15 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- -----------------------------------------------
-- done; stop simulation
-- -----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & str(cycle) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | c58046f8f7e0d4eecb2a747cdfc5794c | 0.453049 | 3.920982 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_schedulestore.vhd | 1 | 7,415 | ------------------------------------------------------------------------------
-- Testbench for schedulestore.vhd
--
-- Project :
-- File : tb_schedulestore.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-16
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_ScheduleStore is
end tb_ScheduleStore;
architecture arch of tb_ScheduleStore is
constant WRDWIDTH : integer := 32;
constant CONWIDTH : integer := 8;
constant CYCWIDTH : integer := 8;
constant ADRWIDTH : integer := 6;
constant FILLWIDTH : integer := WRDWIDTH-(CONWIDTH+CYCWIDTH+ADRWIDTH+1);
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, progSchedule, loadSPC, resetSPC);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal SPCclrxEI : std_logic;
signal SPCloadxEI : std_logic;
signal WExEI : std_logic;
signal IAddrxDI : std_logic_vector(ADRWIDTH-1 downto 0);
signal IWordxDI : std_logic_vector(WRDWIDTH-1 downto 0);
signal ContextxDO : std_logic_vector(CONWIDTH-1 downto 0);
signal CyclesxDO : std_logic_vector(CYCWIDTH-1 downto 0);
signal LastxSO : std_logic;
-- testbench signals
signal IContextxD : std_logic_vector(CONWIDTH-1 downto 0);
signal ICyclesxD : std_logic_vector(CYCWIDTH-1 downto 0);
signal INextAdrxD : std_logic_vector(ADRWIDTH-1 downto 0);
signal ILastxD : std_logic;
signal IFillxD : std_logic_vector(FILLWIDTH-1 downto 0) := (others => '0');
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ScheduleStore
generic map (
WRDWIDTH => WRDWIDTH,
CONWIDTH => CONWIDTH,
CYCWIDTH => CYCWIDTH,
ADRWIDTH => ADRWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExEI,
IAddrxDI => IAddrxDI,
IWordxDI => IWordxDI,
SPCclrxEI => SPCclrxEI,
SPCloadxEI => SPCloadxEI,
ContextxDO => ContextxDO,
CyclesxDO => CyclesxDO,
LastxSO => LastxSO);
----------------------------------------------------------------------------
-- instruction word encoding
----------------------------------------------------------------------------
IWordxDI <= IFillxD & IContextxD & ICyclesxD & INextAdrxD & ILastxD;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal WExEI : out std_logic;
signal IAddrxDI : out std_logic_vector(ADRWIDTH-1 downto 0);
signal IContextxD : out std_logic_vector(CONWIDTH-1 downto 0);
signal ICyclesxD : out std_logic_vector(CYCWIDTH-1 downto 0);
signal INextAdrxD : out std_logic_vector(ADRWIDTH-1 downto 0);
signal ILastxD : out std_logic;
signal SPCclrxEI : out std_logic;
signal SPCloadxEI : out std_logic) is
begin
WExEI <= '0';
IAddrxDI <= (others => '0');
IContextxD <= (others => '0');
ICyclesxD <= (others => '0');
INextAdrxD <= (others => '0');
ILastxD <= '0';
SPCclrxEI <= '0';
SPCloadxEI <= '0';
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
--
-- program schedule into schedule store
--
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(0, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(10, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(100, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(1, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(1, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(11, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(101, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(2, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(2, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(12, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(102, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(3, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= progSchedule;
IAddrxDI <= std_logic_vector(to_unsigned(3, ADRWIDTH));
IContextxD <= std_logic_vector(to_unsigned(13, CONWIDTH));
ICyclesxD <= std_logic_vector(to_unsigned(103, CYCWIDTH));
INextAdrxD <= std_logic_vector(to_unsigned(4, ADRWIDTH));
ILastxD <= '0';
WExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
wait for CLK_PERIOD;
--
-- load schedule PC n times
--
for i in 0 to 3 loop
tbStatus <= loadSPC;
SPCloadxEI <= '1';
wait for CLK_PERIOD;
end loop; -- i
--
-- reset schedule PC (points to store address 0)
--
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
tbStatus <= resetSPC;
SPCclrxEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(WExEI, IAddrxDI, IContextxD, ICyclesxD, INextAdrxD, ILastxD, SPCclrxEI, SPCloadxEI);
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 1063bdde1476bfa0152587f739a8724d | 0.555765 | 3.649114 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/artix7/transceiver.vhd | 1 | 49,381 | ----------------------------------------------------------------------------------
-- Module Name: transceiver - Behavioral
--
-- Description: A wrapper around the Xilinx 7-series GTX transceiver
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-18 | Move bit reordering here from the 8b/10b encoder
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Transceiver is
generic (
use_hw_8b10b_support : std_logic -- NOT YET IMPLEMENTED
);
Port ( mgmt_clk : in STD_LOGIC;
powerup_channel : in STD_LOGIC_VECTOR;
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
swing_0p4 : in STD_LOGIC;
swing_0p6 : in STD_LOGIC;
swing_0p8 : in STD_LOGIC;
tx_running : out STD_LOGIC_VECTOR := (others => '0');
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
symbolclk : out STD_LOGIC;
in_symbols : in std_logic_vector(79 downto 0);
debug : out std_logic_vector(7 downto 0) := (others => '0');
gtptxp : out std_logic_vector;
gtptxn : out std_logic_vector);
end transceiver;
architecture Behavioral of transceiver is
signal txchardispmode : std_logic_vector( 4*gtptxp'length-1 downto 0) := (others => '0');
signal txchardispval : std_logic_vector( 4*gtptxp'length-1 downto 0) := (others => '0');
signal txdata_for_tx : std_logic_vector( 32*gtptxp'length-1 downto 0) := (others => '0');
signal txdata_iskchark : std_logic_vector( 4*gtptxp'length-1 downto 0) := (others => '0');
component gtx_tx_reset_controller is
port ( clk : in std_logic;
ref_clk : in std_logic;
powerup_channel : in std_logic;
tx_running : out std_logic;
txreset : out std_logic;
txuserrdy : out std_logic;
txpmareset : out std_logic;
txpcsreset : out std_logic;
pllpd : out std_logic;
pllreset : out std_logic;
plllocken : out std_logic;
plllock : in std_logic;
resetsel : out std_logic;
txresetdone : in std_logic);
end component;
signal refclk0 : std_logic;
signal refclk1 : std_logic;
signal ref_clk_fabric : std_logic_vector(gtptxp'high downto 0); -- need to connect;
signal txreset : std_logic_vector(gtptxp'high downto 0);
signal txresetdone : std_logic_vector(gtptxp'high downto 0);
signal txpcsreset : std_logic_vector(gtptxp'high downto 0);
signal txpmareset : std_logic_vector(gtptxp'high downto 0);
signal txuserrdy : std_logic_vector(gtptxp'high downto 0);
signal pll0pd : std_logic_vector(gtptxp'high downto 0);
signal pll0reset : std_logic_vector(gtptxp'high downto 0);
signal pll0locken : std_logic_vector(gtptxp'high downto 0);
signal pll0lock : std_logic;
signal resetsel : std_logic_vector(gtptxp'high downto 0);
signal preemp_level : std_logic_vector(4 downto 0);
signal swing_level : std_logic_vector(3 downto 0);
constant PLL0_FBDIV_IN : integer := 4;
constant PLL1_FBDIV_IN : integer := 1;
constant PLL0_FBDIV_45_IN : integer := 5;
constant PLL1_FBDIV_45_IN : integer := 4;
constant PLL0_REFCLK_DIV_IN : integer := 1;
constant PLL1_REFCLK_DIV_IN : integer := 1;
signal PLL0CLK : STD_LOGIC;
signal PLL0REFCLK : STD_LOGIC;
signal PLL1CLK : STD_LOGIC;
signal PLL1REFCLK : STD_LOGIC;
signal TXUSRCLK : STD_LOGIC_vector(gtptxp'length-1 downto 0);
signal TXUSRCLK2 : STD_LOGIC_vector(gtptxp'length-1 downto 0);
signal tx_out_clk : STD_LOGIC_vector(gtptxp'length-1 downto 0);
signal tx_out_clk_buffered : STD_LOGIC;
begin
-- TXOUTCLKFABRIC <= ref_clk_fabric;
-- TXOUTCLK <= tx_out_clk_buffered;
symbolclk <= tx_out_clk_buffered;
preemp_level <= "10100" when preemp_6p0 = '1' else -- +6.0 db from table 3-30 in UG476
"01101" when preemp_3p5 = '1' else -- +3.5 db
"00000"; -- +0.0 db
swing_level <= "1000" when swing_0p8 = '1' else -- 0.8 V
"0101" when swing_0p6 = '1' else -- 0.6 V
"0010"; -- 0.4 V
i_bufg: BUFG PORT MAP (
i => tx_out_clk(0),
o => tx_out_clk_buffered
);
------------- GT txdata_i Assignments for 20 bit datapath -------
I_IBUFDS_GTE2_0 : IBUFDS_GTE2
port map
(
O => refclk0,
ODIV2 => open,
CEB => '0',
I => refclk0_p,
IB => refclk0_n
);
I_IBUFDS_GTE2_1 : IBUFDS_GTE2
port map
(
O => refclk1,
ODIV2 => open,
CEB => '0',
I => refclk1_p,
IB => refclk1_n
);
gtpe2_common_i : GTPE2_COMMON
generic map
(
-- Simulation attributes
-- SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
-- SIM_PLL0REFCLK_SEL => SIM_PLL0REFCLK_SEL,
-- SIM_PLL1REFCLK_SEL => SIM_PLL1REFCLK_SEL,
-- SIM_VERSION => ("2.0"),
PLL0_FBDIV => PLL0_FBDIV_IN ,
PLL0_FBDIV_45 => PLL0_FBDIV_45_IN ,
PLL0_REFCLK_DIV => PLL0_REFCLK_DIV_IN,
PLL1_FBDIV => PLL1_FBDIV_IN ,
PLL1_FBDIV_45 => PLL1_FBDIV_45_IN ,
PLL1_REFCLK_DIV => PLL1_REFCLK_DIV_IN,
------------------COMMON BLOCK Attributes---------------
BIAS_CFG => (x"0000000000050001"),
COMMON_CFG => (x"00000000"),
----------------------------PLL Attributes----------------------------
PLL0_CFG => (x"01F03DC"),
PLL0_DMON_CFG => ('0'),
PLL0_INIT_CFG => (x"00001E"),
PLL0_LOCK_CFG => (x"1E8"),
PLL1_CFG => (x"01F03DC"),
PLL1_DMON_CFG => ('0'),
PLL1_INIT_CFG => (x"00001E"),
PLL1_LOCK_CFG => (x"1E8"),
PLL_CLKOUT_CFG => (x"00"),
----------------------------Reserved Attributes----------------------------
RSVD_ATTR0 => (x"0000"),
RSVD_ATTR1 => (x"0000")
)
port map
(
DMONITOROUT => open,
------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
DRPADDR => (others => '0'),
DRPCLK => '0',
DRPDI => (others => '0'),
DRPDO => open,
DRPEN => '0',
DRPRDY => open,
DRPWE => '0',
----------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
GTEASTREFCLK0 => '0',
GTEASTREFCLK1 => '0',
GTGREFCLK1 => '0',
GTREFCLK0 => refclk0,
GTREFCLK1 => refclk1,
GTWESTREFCLK0 => '0',
GTWESTREFCLK1 => '0',
PLL0OUTCLK => pll0clk,
PLL0OUTREFCLK => pll0refclk,
PLL1OUTCLK => pll1clk,
PLL1OUTREFCLK => pll1refclk,
-------------------------- Common Block - PLL Ports ------------------------
PLL0FBCLKLOST => open,
PLL0LOCK => pll0lock,
PLL0LOCKDETCLK => mgmt_clk,
PLL0LOCKEN => '1',
PLL0PD => pll0pd(0),
PLL0REFCLKLOST => open,
PLL0REFCLKSEL => "001", -- ref clock 0
PLL0RESET => pll0reset(0),
PLL1FBCLKLOST => open,
PLL1LOCK => open,
PLL1LOCKDETCLK => '0',
PLL1LOCKEN => '1',
PLL1PD => '1',
PLL1REFCLKLOST => open,
PLL1REFCLKSEL => "001",
PLL1RESET => '0',
---------------------------- Common Block - Ports --------------------------
BGRCALOVRDENB => '1',
GTGREFCLK0 => '0',
PLLRSVD1 => "0000000000000000",
PLLRSVD2 => "00000",
REFCLKOUTMONITOR0 => open,
REFCLKOUTMONITOR1 => open,
------------------------ Common Block - RX AFE Ports -----------------------
PMARSVDOUT => open,
--------------------------------- QPLL Ports -------------------------------
BGBYPASSB => '1',
BGMONITORENB => '1',
BGPDB => '1',
BGRCALOVRD => "11111",
PMARSVD => "00000000",
RCALENB => '1'
);
g_tx: for i in 0 to gtptxp'high generate
TXUSRCLK(i) <= tx_out_clk_buffered;
TXUSRCLK2(i) <= tx_out_clk_buffered;
g_sw_8b10b: if use_hw_8b10b_support = '0' generate
txdata_for_tx(32*i+ 0) <= in_symbols(9+20*i);
txdata_for_tx(32*i+ 1) <= in_symbols(8+20*i);
txdata_for_tx(32*i+ 2) <= in_symbols(7+20*i);
txdata_for_tx(32*i+ 3) <= in_symbols(6+20*i);
txdata_for_tx(32*i+ 4) <= in_symbols(5+20*i);
txdata_for_tx(32*i+ 5) <= in_symbols(4+20*i);
txdata_for_tx(32*i+ 6) <= in_symbols(3+20*i);
txdata_for_tx(32*i+ 7) <= in_symbols(2+20*i);
txchardispval (4*i+ 0) <= in_symbols(1+20*i);
txchardispmode(4*i+ 0) <= in_symbols(0+20*i);
txdata_iskchark(4*i+0) <= '0'; -- does nothing!
txdata_for_tx(32*i+ 8) <= in_symbols(19+20*i);
txdata_for_tx(32*i+ 9) <= in_symbols(18+20*i);
txdata_for_tx(32*i+10) <= in_symbols(17+20*i);
txdata_for_tx(32*i+11) <= in_symbols(16+20*i);
txdata_for_tx(32*i+12) <= in_symbols(15+20*i);
txdata_for_tx(32*i+13) <= in_symbols(14+20*i);
txdata_for_tx(32*i+14) <= in_symbols(13+20*i);
txdata_for_tx(32*i+15) <= in_symbols(12+20*i);
txchardispval (4*i+1) <= in_symbols(11+20*i);
txchardispmode(4*i+1) <= in_symbols(10+20*i);
txdata_iskchark(4*i+ 1) <= '0'; -- does nothing!
end generate;
g_ww_8b10b: if use_hw_8b10b_support = '1' generate
txdata_for_tx(32*i+ 7 downto 32*i+ 0) <= in_symbols(7+20*i downto 0+20*i);
txdata_iskchark(4*i+ 0) <= in_symbols(8+20*i);
txchardispval(4*i+ 0) <= '0';
txchardispmode(4*i+ 0) <= in_symbols(9+20*i);
txdata_for_tx(32*i+ 15 downto 32*i+ 8) <= in_symbols(17+20*i downto 10+20*i);
txdata_iskchark(4*i+1) <= in_symbols(18+20*i);
txchardispval(4*i+1) <= '0';
txchardispmode(4*i+1) <= in_symbols(19+20*i);
end generate;
i_gtx_tx_reset_controller: gtx_tx_reset_controller
port map ( clk => mgmt_clk,
ref_clk => ref_clk_fabric(i),
powerup_channel => powerup_channel(i),
tx_running => tx_running(i),
pllpd => pll0pd(i),
pllreset => pll0reset(i),
plllocken => pll0locken(i),
plllock => pll0lock,
txreset => txreset(i),
txpmareset => txpmareset(i),
txpcsreset => txpcsreset(i),
txuserrdy => txuserrdy(i),
resetsel => resetsel(i),
txresetdone => txresetdone(i));
gtpe2_i : GTPE2_CHANNEL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => ("TRUE"),
SIM_RESET_SPEEDUP => ("TRUE"),
SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
------------------RX Byte and Word Alignment Attributes---------------
ALIGN_COMMA_DOUBLE => ("FALSE"),
ALIGN_COMMA_ENABLE => ("1111111111"),
ALIGN_COMMA_WORD => (1),
ALIGN_MCOMMA_DET => ("TRUE"),
ALIGN_MCOMMA_VALUE => ("1010000011"),
ALIGN_PCOMMA_DET => ("TRUE"),
ALIGN_PCOMMA_VALUE => ("0101111100"),
SHOW_REALIGN_COMMA => ("TRUE"),
RXSLIDE_AUTO_WAIT => (7),
RXSLIDE_MODE => ("OFF"),
RX_SIG_VALID_DLY => (10),
------------------RX 8B/10B Decoder Attributes---------------
RX_DISPERR_SEQ_MATCH => ("FALSE"),
DEC_MCOMMA_DETECT => ("FALSE"),
DEC_PCOMMA_DETECT => ("FALSE"),
DEC_VALID_COMMA_ONLY => ("FALSE"),
------------------------RX Clock Correction Attributes----------------------
CBCC_DATA_SOURCE_SEL => ("ENCODED"),
CLK_COR_SEQ_2_USE => ("FALSE"),
CLK_COR_KEEP_IDLE => ("FALSE"),
CLK_COR_MAX_LAT => (9),
CLK_COR_MIN_LAT => (7),
CLK_COR_PRECEDENCE => ("TRUE"),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_LEN => (1),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2 => ("0000000000"),
CLK_COR_SEQ_1_3 => ("0000000000"),
CLK_COR_SEQ_1_4 => ("0000000000"),
CLK_CORRECT_USE => ("FALSE"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0100000000"),
CLK_COR_SEQ_2_2 => ("0000000000"),
CLK_COR_SEQ_2_3 => ("0000000000"),
CLK_COR_SEQ_2_4 => ("0000000000"),
------------------------RX Channel Bonding Attributes----------------------
CHAN_BOND_KEEP_ALIGN => ("FALSE"),
CHAN_BOND_MAX_SKEW => (1),
CHAN_BOND_SEQ_LEN => (1),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => ("FALSE"),
FTS_DESKEW_SEQ_ENABLE => ("1111"),
FTS_LANE_DESKEW_CFG => ("1111"),
FTS_LANE_DESKEW_EN => ("FALSE"),
---------------------------RX Margin Analysis Attributes----------------------------
ES_CONTROL => ("000000"),
ES_ERRDET_EN => ("FALSE"),
ES_EYE_SCAN_EN => ("FALSE"),
ES_HORZ_OFFSET => (x"010"),
ES_PMA_CFG => ("0000000000"),
ES_PRESCALE => ("00000"),
ES_QUALIFIER => (x"00000000000000000000"),
ES_QUAL_MASK => (x"00000000000000000000"),
ES_SDATA_MASK => (x"00000000000000000000"),
ES_VERT_OFFSET => ("000000000"),
-------------------------FPGA RX Interface Attributes-------------------------
RX_DATA_WIDTH => (20),
---------------------------PMA Attributes----------------------------
OUTREFCLK_SEL_INV => ("11"),
PMA_RSV => (x"00000333"),
PMA_RSV2 => (x"00002040"),
PMA_RSV3 => ("00"),
PMA_RSV4 => ("0000"),
RX_BIAS_CFG => ("0000111100110011"),
DMONITOR_CFG => (x"000A00"),
RX_CM_SEL => ("01"),
RX_CM_TRIM => ("0000"),
RX_DEBUG_CFG => ("00000000000000"),
RX_OS_CFG => ("0000010000000"),
TERM_RCAL_CFG => ("100001000010000"),
TERM_RCAL_OVRD => ("000"),
TST_RSV => (x"00000000"),
RX_CLK25_DIV => (6),
TX_CLK25_DIV => (6),
UCODEER_CLR => ('0'),
---------------------------PCI Express Attributes----------------------------
PCS_PCIE_EN => ("FALSE"),
---------------------------PCS Attributes----------------------------
PCS_RSVD_ATTR => (x"000000000000"),
-------------RX Buffer Attributes------------
RXBUF_ADDR_MODE => ("FAST"),
RXBUF_EIDLE_HI_CNT => ("1000"),
RXBUF_EIDLE_LO_CNT => ("0000"),
RXBUF_EN => ("TRUE"),
RX_BUFFER_CFG => ("000000"),
RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
RXBUF_RESET_ON_EIDLE => ("FALSE"),
RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
RXBUFRESET_TIME => ("00001"),
RXBUF_THRESH_OVFLW => (61),
RXBUF_THRESH_OVRD => ("FALSE"),
RXBUF_THRESH_UNDFLW => (4),
RXDLY_CFG => (x"001F"),
RXDLY_LCFG => (x"030"),
RXDLY_TAP_CFG => (x"0000"),
RXPH_CFG => (x"C00002"),
RXPHDLY_CFG => (x"084020"),
RXPH_MONITOR_SEL => ("00000"),
RX_XCLK_SEL => ("RXREC"),
RX_DDI_SEL => ("000000"),
RX_DEFER_RESET_BUF_EN => ("TRUE"),
-----------------------CDR Attributes-------------------------
RXCDR_CFG => (x"0001107FE206021081010"),
RXCDR_FR_RESET_ON_EIDLE => ('0'),
RXCDR_HOLD_DURING_EIDLE => ('0'),
RXCDR_PH_RESET_ON_EIDLE => ('0'),
RXCDR_LOCK_CFG => ("001001"),
-------------------RX Initialization and Reset Attributes-------------------
RXCDRFREQRESET_TIME => ("00001"),
RXCDRPHRESET_TIME => ("00001"),
RXISCANRESET_TIME => ("00001"),
RXPCSRESET_TIME => ("00001"),
RXPMARESET_TIME => ("00011"),
-------------------RX OOB Signaling Attributes-------------------
RXOOB_CFG => ("0000110"),
-------------------------RX Gearbox Attributes---------------------------
RXGEARBOX_EN => ("FALSE"),
GEARBOX_MODE => ("000"),
-------------------------PRBS Detection Attribute-----------------------
RXPRBS_ERR_LOOPBACK => ('0'),
-------------Power-Down Attributes----------
PD_TRANS_TIME_FROM_P2 => (x"03c"),
PD_TRANS_TIME_NONE_P2 => (x"3c"),
PD_TRANS_TIME_TO_P2 => (x"64"),
-------------RX OOB Signaling Attributes----------
SAS_MAX_COM => (64),
SAS_MIN_COM => (36),
SATA_BURST_SEQ_LEN => ("0101"),
SATA_BURST_VAL => ("100"),
SATA_EIDLE_VAL => ("100"),
SATA_MAX_BURST => (8),
SATA_MAX_INIT => (21),
SATA_MAX_WAKE => (7),
SATA_MIN_BURST => (4),
SATA_MIN_INIT => (12),
SATA_MIN_WAKE => (4),
-------------RX Fabric Clock Output Control Attributes----------
TRANS_TIME_RATE => (x"0E"),
--------------TX Buffer Attributes----------------
TXBUF_EN => ("TRUE"),
TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
TXDLY_CFG => (x"001F"),
TXDLY_LCFG => (x"030"),
TXDLY_TAP_CFG => (x"0000"),
TXPH_CFG => (x"0780"),
TXPHDLY_CFG => (x"084020"),
TXPH_MONITOR_SEL => ("00000"),
TX_XCLK_SEL => ("TXOUT"),
-------------------------FPGA TX Interface Attributes-------------------------
TX_DATA_WIDTH => (20),
-------------------------TX Configurable Driver Attributes-------------------------
TX_DEEMPH0 => ("000000"),
TX_DEEMPH1 => ("000000"),
TX_EIDLE_ASSERT_DELAY => ("110"),
TX_EIDLE_DEASSERT_DELAY => ("100"),
TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
TX_MAINCURSOR_SEL => ('0'),
TX_DRIVE_MODE => ("DIRECT"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
-------------------------TX Gearbox Attributes--------------------------
TXGEARBOX_EN => ("FALSE"),
-------------------------TX Initialization and Reset Attributes--------------------------
TXPCSRESET_TIME => ("00001"),
TXPMARESET_TIME => ("00001"),
-------------------------TX Receiver Detection Attributes--------------------------
TX_RXDETECT_CFG => (x"1832"),
TX_RXDETECT_REF => ("100"),
------------------ JTAG Attributes ---------------
ACJTAG_DEBUG_MODE => ('0'),
ACJTAG_MODE => ('0'),
ACJTAG_RESET => ('0'),
------------------ CDR Attributes ---------------
CFOK_CFG => (x"49000040E80"),
CFOK_CFG2 => ("0100000"),
CFOK_CFG3 => ("0100000"),
CFOK_CFG4 => ('0'),
CFOK_CFG5 => (x"0"),
CFOK_CFG6 => ("0000"),
RXOSCALRESET_TIME => ("00011"),
RXOSCALRESET_TIMEOUT => ("00000"),
------------------ PMA Attributes ---------------
CLK_COMMON_SWING => ('0'),
RX_CLKMUX_EN => ('1'),
TX_CLKMUX_EN => ('1'),
ES_CLK_PHASE_SEL => ('0'),
USE_PCS_CLK_PHASE_SEL => ('0'),
PMA_RSV6 => ('0'),
PMA_RSV7 => ('0'),
------------------ TX Configuration Driver Attributes ---------------
TX_PREDRIVER_MODE => ('0'),
PMA_RSV5 => ('0'),
SATA_PLL_CFG => ("VCO_3000MHZ"),
------------------ RX Fabric Clock Output Control Attributes ---------------
RXOUT_DIV => (2),
------------------ TX Fabric Clock Output Control Attributes ---------------
TXOUT_DIV => (2),
------------------ RX Phase Interpolator Attributes---------------
RXPI_CFG0 => ("000"),
RXPI_CFG1 => ('1'),
RXPI_CFG2 => ('1'),
--------------RX Equalizer Attributes-------------
ADAPT_CFG0 => (x"00000"),
RXLPMRESET_TIME => ("0001111"),
RXLPM_BIAS_STARTUP_DISABLE => ('0'),
RXLPM_CFG => ("0110"),
RXLPM_CFG1 => ('0'),
RXLPM_CM_CFG => ('0'),
RXLPM_GC_CFG => ("111100010"),
RXLPM_GC_CFG2 => ("001"),
RXLPM_HF_CFG => ("00001111110000"),
RXLPM_HF_CFG2 => ("01010"),
RXLPM_HF_CFG3 => ("0000"),
RXLPM_HOLD_DURING_EIDLE => ('0'),
RXLPM_INCM_CFG => ('0'),
RXLPM_IPCM_CFG => ('1'),
RXLPM_LF_CFG => ("000000001111110000"),
RXLPM_LF_CFG2 => ("01010"),
RXLPM_OSINT_CFG => ("100"),
------------------ TX Phase Interpolator PPM Controller Attributes---------------
TXPI_CFG0 => ("00"),
TXPI_CFG1 => ("00"),
TXPI_CFG2 => ("00"),
TXPI_CFG3 => ('0'),
TXPI_CFG4 => ('0'),
TXPI_CFG5 => ("000"),
TXPI_GREY_SEL => ('0'),
TXPI_INVSTROBE_SEL => ('0'),
TXPI_PPMCLK_SEL => ("TXUSRCLK2"),
TXPI_PPM_CFG => (x"00"),
TXPI_SYNFREQ_PPM => ("000"),
------------------ LOOPBACK Attributes---------------
LOOPBACK_CFG => ('0'),
PMA_LOOPBACK_CFG => ('0'),
------------------RX OOB Signalling Attributes---------------
RXOOB_CLK_CFG => ("PMA"),
------------------TX OOB Signalling Attributes---------------
TXOOB_CFG => ('0'),
------------------RX Buffer Attributes---------------
RXSYNC_MULTILANE => ('1'),
RXSYNC_OVRD => ('0'),
RXSYNC_SKIP_DA => ('0'),
------------------TX Buffer Attributes---------------
TXSYNC_MULTILANE => ('0'),
TXSYNC_OVRD => ('0'),
TXSYNC_SKIP_DA => ('0')
)
port map
(
--------------------------------- CPLL Ports -------------------------------
GTRSVD => "0000000000000000",
PCSRSVDIN => "0000000000000000",
TSTIN => "11111111111111111111",
---------------------------- Channel - DRP Ports --------------------------
DRPADDR => (others => '0'),
DRPCLK => '0',
DRPDI => (others => '0'),
DRPDO => open,
DRPEN => '0',
DRPRDY => open,
DRPWE => '0',
------------------------------- Clocking Ports -----------------------------
RXSYSCLKSEL => "11",
TXSYSCLKSEL => "00",
----------------- FPGA TX Interface Datapath Configuration ----------------
TX8B10BEN => use_hw_8b10b_support,
------------------------ GTPE2_CHANNEL Clocking Ports ----------------------
PLL0CLK => pll0clk,
PLL0REFCLK => pll0refclk,
PLL1CLK => pll1clk,
PLL1REFCLK => pll1refclk,
------------------------------- Loopback Ports -----------------------------
LOOPBACK => (others => '0'),
----------------------------- PCI Express Ports ----------------------------
PHYSTATUS => open,
RXRATE => (others => '0'),
RXVALID => open,
----------------------------- PMA Reserved Ports ---------------------------
PMARSVDIN3 => '0',
PMARSVDIN4 => '0',
------------------------------ Power-Down Ports ----------------------------
RXPD => "11",
TXPD => "00",
-------------------------- RX 8B/10B Decoder Ports -------------------------
SETERRSTATUS => '0',
--------------------- RX Initialization and Reset Ports --------------------
EYESCANRESET => '0',
RXUSERRDY => '0',
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR => open,
EYESCANMODE => '0',
EYESCANTRIGGER => '0',
------------------------------- Receive Ports ------------------------------
CLKRSVD0 => '0',
CLKRSVD1 => '0',
DMONFIFORESET => '0',
DMONITORCLK => '0',
RXPMARESETDONE => open,
SIGVALIDCLK => '0',
------------------------- Receive Ports - CDR Ports ------------------------
RXCDRFREQRESET => '0',
RXCDRHOLD => '0',
RXCDRLOCK => open,
RXCDROVRDEN => '0',
RXCDRRESET => '0',
RXCDRRESETRSV => '0',
RXOSCALRESET => '0',
RXOSINTCFG => "0010",
RXOSINTDONE => open,
RXOSINTHOLD => '0',
RXOSINTOVRDEN => '0',
RXOSINTPD => '0',
RXOSINTSTARTED => open,
RXOSINTSTROBE => '0',
RXOSINTSTROBESTARTED => open,
RXOSINTTESTOVRDEN => '0',
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => open,
---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
RX8B10BEN => '0',
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXDATA => open,
RXUSRCLK => '0',
RXUSRCLK2 => '0',
------------------- Receive Ports - Pattern Checker Ports ------------------
RXPRBSERR => open,
RXPRBSSEL => (others => '0'),
------------------- Receive Ports - Pattern Checker ports ------------------
RXPRBSCNTRESET => '0',
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXCHARISCOMMA => open,
RXCHARISK => open,
RXDISPERR => open,
RXNOTINTABLE => open,
------------------------ Receive Ports - RX AFE Ports ----------------------
GTPRXN => '0',
GTPRXP => '0',
PMARSVDIN2 => '0',
PMARSVDOUT0 => open,
PMARSVDOUT1 => open,
------------------- Receive Ports - RX Buffer Bypass Ports -----------------
RXBUFRESET => '0',
RXBUFSTATUS => open,
RXDDIEN => '0',
RXDLYBYPASS => '1',
RXDLYEN => '0',
RXDLYOVRDEN => '0',
RXDLYSRESET => '0',
RXDLYSRESETDONE => open,
RXPHALIGN => '0',
RXPHALIGNDONE => open,
RXPHALIGNEN => '0',
RXPHDLYPD => '1',
RXPHDLYRESET => '0',
RXPHMONITOR => open,
RXPHOVRDEN => '0',
RXPHSLIPMONITOR => open,
RXSTATUS => open,
RXSYNCALLIN => '0',
RXSYNCDONE => open,
RXSYNCIN => '0',
RXSYNCMODE => '0',
RXSYNCOUT => open,
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED => open,
RXBYTEREALIGN => open,
RXCOMMADET => open,
RXCOMMADETEN => '0',
RXMCOMMAALIGNEN => '0',
RXPCOMMAALIGNEN => '0',
RXSLIDE => '0',
------------------ Receive Ports - RX Channel Bonding Ports ----------------
RXCHANBONDSEQ => open,
RXCHBONDEN => '0',
RXCHBONDI => "0000",
RXCHBONDLEVEL => (others => '0'),
RXCHBONDMASTER => '0',
RXCHBONDO => open,
RXCHBONDSLAVE => '0',
----------------- Receive Ports - RX Channel Bonding Ports ----------------
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DMONITOROUT => open,
RXADAPTSELTEST => (others => '0'),
RXDFEXYDEN => '0',
RXOSINTEN => '1',
RXOSINTID0 => (others => '0'),
RXOSINTNTRLEN => '0',
RXOSINTSTROBEDONE => open,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXLPMLFOVRDEN => '0',
RXLPMOSINTNTRLEN => '0',
-------------------- Receive Ports - RX Equailizer Ports -------------------
RXLPMHFHOLD => '0',
RXLPMHFOVRDEN => '0',
RXLPMLFHOLD => '0',
--------------------- Receive Ports - RX Equalizer Ports -------------------
RXOSHOLD => '0',
RXOSOVRDEN => '0',
------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
RXRATEDONE => open,
----------- Receive Ports - RX Fabric Clock Output Control Ports ----------
RXRATEMODE => '0',
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK => open,
RXOUTCLKFABRIC => open,
RXOUTCLKPCS => open,
RXOUTCLKSEL => "010",
---------------------- Receive Ports - RX Gearbox Ports --------------------
RXDATAVALID => open,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
--------------------- Receive Ports - RX Gearbox Ports --------------------
RXGEARBOXSLIP => '0',
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET => '1',
RXLPMRESET => '1',
RXOOBRESET => '0',
RXPCSRESET => '0',
RXPMARESET => '0',
------------------- Receive Ports - RX OOB Signaling ports -----------------
RXCOMSASDET => open,
RXCOMWAKEDET => open,
------------------ Receive Ports - RX OOB Signaling ports -----------------
RXCOMINITDET => open,
------------------ Receive Ports - RX OOB signalling Ports -----------------
RXELECIDLE => open,
RXELECIDLEMODE => "11",
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => '0',
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE => open,
--------------------------- TX Buffer Bypass Ports -------------------------
TXPHDLYTSTCLK => '0',
------------------------ TX Configurable Driver Ports ----------------------
TXPOSTCURSOR => "00000",
TXPOSTCURSORINV => '0',
TXPRECURSOR => preemp_level,
TXPRECURSORINV => '0',
-------------------- TX Fabric Clock Output Control Ports ------------------
TXRATEMODE => '0',
--------------------- TX Initialization and Reset Ports --------------------
CFGRESET => '0',
GTTXRESET => txreset(i),
PCSRSVDOUT => open,
TXUSERRDY => txuserrdy(i),
----------------- TX Phase Interpolator PPM Controller Ports ---------------
TXPIPPMEN => '0',
TXPIPPMOVRDEN => '0',
TXPIPPMPD => '0',
TXPIPPMSEL => '1',
TXPIPPMSTEPSIZE => (others => '0'),
---------------------- Transceiver Reset Mode Operation --------------------
GTRESETSEL => resetsel(i),
RESETOVRD => '0',
------------------------------- Transmit Ports -----------------------------
TXPMARESETDONE => open,
----------------- Transmit Ports - Configurable Driver Ports ---------------
PMARSVDIN0 => '0',
PMARSVDIN1 => '0',
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXDATA => txdata_for_tx(31+32*i downto 32*i),
TXUSRCLK => txusrclk(i),
TXUSRCLK2 => txusrclk2(i),
--------------------- Transmit Ports - PCI Express Ports -------------------
TXELECIDLE => '0',
TXMARGIN => (others => '0'),
TXRATE => (others => '0'),
TXSWING => '0',
------------------ Transmit Ports - Pattern Generator Ports ----------------
TXPRBSFORCEERR => '0',
------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
TX8B10BBYPASS => (others => '0'),
TXCHARDISPMODE => txchardispmode(3+4*i downto 4*i),
TXCHARDISPVAL => txchardispval(3+4*i downto 4*i),
TXCHARISK => txdata_iskchark(3+4*i downto 4*i),
------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
TXDLYBYPASS => '1',
TXDLYEN => '0',
TXDLYHOLD => '0',
TXDLYOVRDEN => '0',
TXDLYSRESET => '0',
TXDLYSRESETDONE => open,
TXDLYUPDOWN => '0',
TXPHALIGN => '0',
TXPHALIGNDONE => open,
TXPHALIGNEN => '0',
TXPHDLYPD => '0',
TXPHDLYRESET => '0',
TXPHINIT => '0',
TXPHINITDONE => open,
TXPHOVRDEN => '0',
---------------------- Transmit Ports - TX Buffer Ports --------------------
TXBUFSTATUS => open,
------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
TXSYNCALLIN => '0',
TXSYNCDONE => open,
TXSYNCIN => '0',
TXSYNCMODE => '0',
TXSYNCOUT => open,
--------------- Transmit Ports - TX Configurable Driver Ports --------------
GTPTXN => gtptxn(i),
GTPTXP => gtptxp(i),
TXBUFDIFFCTRL => "100",
TXDEEMPH => '0',
TXDIFFCTRL => swing_level,
TXDIFFPD => '0',
TXINHIBIT => '0',
TXMAINCURSOR => "0000000",
TXPISOPD => '0',
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK => tx_out_clk(i),
TXOUTCLKFABRIC => ref_clk_fabric(i), --txoutclkfabric,
TXOUTCLKPCS => open,
TXOUTCLKSEL => "010",
TXRATEDONE => open,
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXGEARBOXREADY => open,
TXHEADER => (others => '0'),
TXSEQUENCE => (others => '0'),
TXSTARTSEQ => '0',
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXPCSRESET => txpcsreset(i),
TXPMARESET => txpmareset(i),
TXRESETDONE => txresetdone(i),
------------------ Transmit Ports - TX OOB signalling Ports ----------------
TXCOMFINISH => open,
TXCOMINIT => '0',
TXCOMSAS => '0',
TXCOMWAKE => '0',
TXPDELECIDLEMODE => '0',
----------------- Transmit Ports - TX Polarity Control Ports ---------------
TXPOLARITY => '0',
--------------- Transmit Ports - TX Receiver Detection Ports --------------
TXDETECTRX => '0',
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL => (others => '0')
);
end generate;
end Behavioral;
| mit | 5c654811d5860f05b3a9b959cfaca528 | 0.345254 | 4.715527 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpTemplate/tbdTemplate/hdl/PlatformHps-Struct-a.vhd | 2 | 5,593 | architecture Struct of PlatformHps is
-- qsys component
component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic; -- SCLK
i2s_adcdat : in std_logic := 'X'; -- adcdat
i2s_adclrck : in std_logic := 'X'; -- adclrck
i2s_bclk : in std_logic := 'X'; -- bclk
i2s_dacdat : out std_logic; -- dacdat
i2s_daclrck : in std_logic := 'X'; -- daclrck
keys_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
xck_clk : out std_logic; -- clk
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hex0_2_export : out std_logic_vector(20 downto 0); -- export
hex3_5_export : out std_logic_vector(20 downto 0) -- export
);
end component Platform;
signal hex0_2, hex3_5 : std_logic_vector(20 downto 0);
signal keys_p : std_logic_vector(2 downto 0);
begin -- architecture Struct
-- hex
HEX0 <= not hex0_2(6 downto 0);
HEX1 <= not hex0_2(13 downto 7);
HEX2 <= not hex0_2(20 downto 14);
HEX3 <= not hex3_5(6 downto 0);
HEX4 <= not hex3_5(13 downto 7);
HEX5 <= not hex3_5(20 downto 14);
--keys
keys_p <= not KEY(3 downto 1);
-- qsys system
u0 : component Platform
port map (
clk_clk => CLOCK_50, -- clk.clk
i2c_SDAT => FPGA_I2C_SDAT, -- i2c.SDAT
i2c_SCLK => FPGA_I2C_SCLK, -- .SCLK
i2s_adcdat => AUD_ADCDAT, -- i2s.adcdat
i2s_adclrck => AUD_ADCLRCK, -- .adclrck
i2s_bclk => AUD_BCLK, -- .bclk
i2s_dacdat => AUD_DACDAT, -- .dacdat
i2s_daclrck => AUD_DACLRCK, -- .daclrck
keys_export => keys_p, -- keys.export
leds_export => LEDR, -- leds.export
memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a
memory_mem_ba => HPS_DDR3_BA, -- .mem_ba
memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck
memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n
memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke
memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n
memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n
memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n
memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n
memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n
memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq
memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs
memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n
memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt
memory_mem_dm => HPS_DDR3_DM, -- .mem_dm
memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin
reset_reset_n => KEY(0), -- reset.reset_n
switches_export => SW, -- switches.export
xck_clk => AUD_XCK, -- xck.clk
hps_io_hps_io_gpio_inst_GPIO53 => HPS_LED, -- hps_io.hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => HPS_KEY, -- .hps_io_gpio_inst_GPIO54
hex0_2_export => hex0_2, -- hex0_2.export
hex3_5_export => hex3_5 -- hex3_5.export
);
end architecture Struct;
| gpl-3.0 | 015579a18b62bf4780b767f775d2599d | 0.445199 | 3.242319 | false | false | false | false |
hamsternz/FPGA_DisplayPort | test_benches/tb_pixel_receiver.vhd | 1 | 5,323 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:15:58 10/12/2015
-- Design Name:
-- Module Name: C:/repos/HDMI2USB-numato-opsis-sample-code/video/displayport/output/tb_pixel_receiver.vhd
-- Project Name: displayport_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: pixel_receiver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_pixel_receiver IS
END tb_pixel_receiver;
ARCHITECTURE behavior OF tb_pixel_receiver IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pixel_receiver
PORT(
pixel_clk : IN std_logic;
pixel_data : IN std_logic_vector(23 downto 0);
pixel_hblank : IN std_logic;
pixel_hsync : IN std_logic;
pixel_vblank : IN std_logic;
pixel_vsync : IN std_logic;
ready : OUT std_logic;
h_visible : OUT std_logic_vector(12 downto 0);
v_visible : OUT std_logic_vector(12 downto 0);
h_total : OUT std_logic_vector(12 downto 0);
v_total : OUT std_logic_vector(12 downto 0);
h_sync_wdith : OUT std_logic_vector(12 downto 0);
v_sync_width : OUT std_logic_vector(12 downto 0);
h_start : OUT std_logic_vector(12 downto 0);
v_start : OUT std_logic_vector(12 downto 0);
h_sync_active_high : IN std_logic;
v_sync_active_high : IN std_logic;
dp_clk : IN std_logic;
dp_ch0_data : OUT std_logic_vector(8 downto 0);
dp_ch1_data : OUT std_logic_vector(8 downto 0);
dp_ch2_data : OUT std_logic_vector(8 downto 0);
dp_ch3_data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
--Inputs
signal pixel_clk : std_logic := '0';
signal pixel_data : std_logic_vector(23 downto 0) := (others => '0');
signal pixel_hblank : std_logic := '0';
signal pixel_hsync : std_logic := '0';
signal pixel_vblank : std_logic := '0';
signal pixel_vsync : std_logic := '0';
signal h_sync_active_high : std_logic := '0';
signal v_sync_active_high : std_logic := '0';
signal dp_clk : std_logic := '0';
--Outputs
signal ready : std_logic;
signal h_visible : std_logic_vector(12 downto 0);
signal v_visible : std_logic_vector(12 downto 0);
signal h_total : std_logic_vector(12 downto 0);
signal v_total : std_logic_vector(12 downto 0);
signal h_sync_wdith : std_logic_vector(12 downto 0);
signal v_sync_width : std_logic_vector(12 downto 0);
signal h_start : std_logic_vector(12 downto 0);
signal v_start : std_logic_vector(12 downto 0);
signal dp_ch0_data : std_logic_vector(8 downto 0);
signal dp_ch1_data : std_logic_vector(8 downto 0);
signal dp_ch2_data : std_logic_vector(8 downto 0);
signal dp_ch3_data : std_logic_vector(8 downto 0);
-- Clock period definitions
constant pixel_clk_period : time := 25 ns;
constant dp_clk_period : time := 3.7 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pixel_receiver PORT MAP (
pixel_clk => pixel_clk,
pixel_data => pixel_data,
pixel_hblank => pixel_hblank,
pixel_hsync => pixel_hsync,
pixel_vblank => pixel_vblank,
pixel_vsync => pixel_vsync,
ready => ready,
h_visible => h_visible,
v_visible => v_visible,
h_total => h_total,
v_total => v_total,
h_sync_wdith => h_sync_wdith,
v_sync_width => v_sync_width,
h_start => h_start,
v_start => v_start,
h_sync_active_high => h_sync_active_high,
v_sync_active_high => v_sync_active_high,
dp_clk => dp_clk,
dp_ch0_data => dp_ch0_data,
dp_ch1_data => dp_ch1_data,
dp_ch2_data => dp_ch2_data,
dp_ch3_data => dp_ch3_data
);
-- Clock process definitions
pixel_clk_process :process
begin
pixel_clk <= '0';
wait for pixel_clk_period/2;
pixel_clk <= '1';
wait for pixel_clk_period/2;
end process;
dp_clk_process :process
begin
dp_clk <= '0';
wait for dp_clk_period/2;
dp_clk <= '1';
wait for dp_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for pixel_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | c2340f548e49a3d36d47be43e0fb7b66 | 0.577306 | 3.490492 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/ipcore_dir/dualBRAM/simulation/dualBRAM_synth.vhd | 1 | 10,352 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dualBRAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY dualBRAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE dualBRAM_synth_ARCH OF dualBRAM_synth IS
COMPONENT dualBRAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: dualBRAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| mit | 44ad122882ca211df4439c88d4322083 | 0.555255 | 3.600696 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/test_source_800_600_RGB_444_colourbars_ch1.vhd | 1 | 29,157 | ----------------------------------------------------------------------------------
-- Module Name: test_source_800_600_RGB_444_colourbars_ch1 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case 800x600 colour bars.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test_source_800_600_RGB_444_colourbars_ch1 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end test_source_800_600_RGB_444_colourbars_ch1;
architecture arch of test_source_800_600_RGB_444_colourbars_ch1 is
type a_test_data_blocks is array (0 to 64*17-1) of std_logic_vector(8 downto 0);
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0xAA
constant SPARE : std_logic_vector(8 downto 0) := "011111111"; -- 0xFF
constant ZERO : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant PIX_80 : std_logic_vector(8 downto 0) := "011001100"; -- 0x80
constant PIX_0 : std_logic_vector(8 downto 0) := "000000000"; -- 0x80
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant FS : std_logic_vector(8 downto 0) := "111111110"; -- K30.7
constant FE : std_logic_vector(8 downto 0) := "111110111"; -- K23.7
constant VB_VS : std_logic_vector(8 downto 0) := "000000001"; -- 0x00 VB-ID with Vertical blank asserted
constant VB_NVS : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 VB-ID without Vertical blank asserted
constant Mvid : std_logic_vector(8 downto 0) := "001101000"; -- 0x68
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
-- constant HtotH : std_logic_vector(8 downto 0) := "000000100"; -- Total 1056
-- constant HTotL : std_logic_vector(8 downto 0) := "000100000";
-- constant HstH : std_logic_vector(8 downto 0) := "000000000"; -- Start 128 + 88 = 216
-- constant HstL : std_logic_vector(8 downto 0) := "011011000";
-- constant HswH : std_logic_vector(8 downto 0) := "000000000"; -- Sync width 128
-- constant HswL : std_logic_vector(8 downto 0) := "010000000";
-- constant HwidH : std_logic_vector(8 downto 0) := "000000011"; -- Active width 800
-- constant HwidL : std_logic_vector(8 downto 0) := "000100000";
-- constant VtotH : std_logic_vector(8 downto 0) := "000000010"; -- Total Lines 628
-- constant VtotL : std_logic_vector(8 downto 0) := "001110100";
-- constant VstH : std_logic_vector(8 downto 0) := "000000000"; -- Start = 4+23 = 27
-- constant VstL : std_logic_vector(8 downto 0) := "000011011";
-- constant VswH : std_logic_vector(8 downto 0) := "000000000"; -- Vert Sync Width 4
-- constant VswL : std_logic_vector(8 downto 0) := "000000100";
-- constant VheiH : std_logic_vector(8 downto 0) := "000000010"; -- Active lines 600
-- constant VheiL : std_logic_vector(8 downto 0) := "001011000";
-- constant MISC0 : std_logic_vector(8 downto 0) := "000100001"; -- MISC0 - Sync, RGB, Full range, 8bpp
-- constant MISC1 : std_logic_vector(8 downto 0) := "000000000"; -- MISC1
-- constant MvidH : std_logic_vector(8 downto 0) := "000000001"; -- M = 0x012F68
-- constant MvidM : std_logic_vector(8 downto 0) := "000101111";
-- constant MvidL : std_logic_vector(8 downto 0) := "001101000";
-- constant NvidH : std_logic_vector(8 downto 0) := "000001000"; -- N = 0x080000
-- constant NvidM : std_logic_vector(8 downto 0) := "000000000";
-- constant NvidL : std_logic_vector(8 downto 0) := "000000000";
constant test_data_blocks : a_test_data_blocks := (
--- Block 0 - Junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 1 - 8 white pixels and padding
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 2 - 2 white pixels and 6 yellow and padding
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 3 - 8 yellow and padding
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 4 - 4 yellow and 4 cyan padding
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_80, PIX_80, PIX_0, PIX_80, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 5 - 8 cyan padding
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 6 - 6 cyan and 2 green + padding
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_80, PIX_0, PIX_80, PIX_80,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 7 - 8 green + padding
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
PIX_0, PIX_80, PIX_0, PIX_0, PIX_80, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 8 - 8 magent + padding
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 9 - 2 magent + 6 red + padding
PIX_80, PIX_0, PIX_80, PIX_80, PIX_0, PIX_80,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 10 - 4 red + padding
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 11 - 4 red + 4 blue + padding
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_80, PIX_0, PIX_0, PIX_80, PIX_0, PIX_0,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 12 - 8 Blue + padding
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 13 - 8 x Blue, Blank Start, VB-ID (no vsync), Mvid, MAud and junk
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
BS, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 14 - 8 x Blue, Blank Start, VB-ID (+vsync), Mvid, MAud and junk
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
PIX_0, PIX_0, PIX_80, PIX_0, PIX_0, PIX_80,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 15 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 16 - just blank end
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, BE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE);
signal index : unsigned (10 downto 0) := (others => '0'); -- Index up to 32 x 64 symbol blocks
signal d0: std_logic_vector(8 downto 0) := (others => '0');
signal d1: std_logic_vector(8 downto 0) := (others => '0');
signal line_count : unsigned(9 downto 0) := (others => '0');
signal row_count : unsigned(7 downto 0) := (others => '0');
signal switch_point : std_logic := '0';
begin
M_value <= x"012F68";
N_value <= x"080000";
H_visible <= x"320"; -- 800
V_visible <= x"258"; -- 600
H_total <= x"420"; -- 1056
V_total <= x"274"; -- 628
H_sync_width <= x"080"; -- 128
V_sync_width <= x"004"; -- 4
H_start <= x"0D8"; -- 216
V_start <= x"01b"; -- 37
H_vsync_active_high <= '0';
V_vsync_active_high <= '0';
flag_sync_clock <= '1';
flag_YCCnRGB <= '0';
flag_422n444 <= '0';
flag_range_reduced <= '0';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "001";
ready <= '1';
data(72) <= switch_point;
data(71 downto 18) <= (others => '0');
data(17 downto 0) <= d1 & d0;
process(clk)
begin
if rising_edge(clk) then
d0 <= test_data_blocks(to_integer(index+0));
d1 <= test_data_blocks(to_integer(index+1));
if index(5 downto 0) = 52 then
index(5 downto 0) <= (others => '0');
if row_count = 131 then
row_count <= (others => '0');
if line_count = 627 then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
row_count <= row_count +1;
end if;
--- Block 0 - Junk
--- Block 1 - Mains Stream attribuutes, junk and blank end
--- Block 2 - 8 white pixels and padding
--- Block 3 - 2 white pixels and 6 yellow and padding
--- Block 4 - 8 yellow and padding
--- Block 5 - 4 yellow and 4 cyan padding
--- Block 6 - 8 cyan padding
--- Block 7 - 6 cyan and 2 green + padding
--- Block 8 - 8 green + padding
--- Block 9 - 8 magent + padding
--- Block 10 - 2 magent + 6 red + padding
--- Block 11 - 8 red + padding
--- Block 12 - 4 red + 4 blue + padding
--- Block 13 - 8 Blue + padding
--- Block 14 - 8 x Blue, Blank Start, VB-ID (no vsync), Mvid, MAud and junk
--- Block 15 - 8 x Blue, Blank Start, VB-ID (+vsync), Mvid, MAud and junk
--- Block 16 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
--- Block 17 - just blank end
if line_count = 0 then
if row_count < 1 then index(10 downto 6) <= "10000"; -- Just blank end BE
elsif row_count < 14 then index(10 downto 6) <= "00001"; -- White *8 plus fill
elsif row_count < 15 then index(10 downto 6) <= "00010"; -- White + Yellow plus fill
elsif row_count < 29 then index(10 downto 6) <= "00011"; -- Yellow Pixels plus fill
elsif row_count < 30 then index(10 downto 6) <= "00100"; -- Yellow + Cyan plus fill
elsif row_count < 42 then index(10 downto 6) <= "00101"; -- Cyan Pixels plus fill
elsif row_count < 43 then index(10 downto 6) <= "00110"; -- Cyan + green Pixels plus fill
elsif row_count < 56 then index(10 downto 6) <= "00111"; -- Green plus fill
elsif row_count < 71 then index(10 downto 6) <= "01000"; -- Magenta plus fill
elsif row_count < 72 then index(10 downto 6) <= "01001"; -- Magenta + red plus fill
elsif row_count < 86 then index(10 downto 6) <= "01010"; -- red Pixels plus fill
elsif row_count < 87 then index(10 downto 6) <= "01011"; -- red + blue Pixels plus fill
elsif row_count < 100 then index(10 downto 6) <= "01100"; -- blue plus fill
elsif row_count = 100 then index(10 downto 6) <= "01101"; -- Pixels BS and VS-ID block (no VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
elsif line_count < 599 then -- lines of active video (except first and last)
if row_count < 1 then index(10 downto 6) <= "10000"; -- Just blank end BE
elsif row_count < 14 then index(10 downto 6) <= "00001"; -- White *8 plus fill
elsif row_count < 15 then index(10 downto 6) <= "00010"; -- White + Yellow plus fill
elsif row_count < 29 then index(10 downto 6) <= "00011"; -- Yellow Pixels plus fill
elsif row_count < 30 then index(10 downto 6) <= "00100"; -- Yellow + Cyan plus fill
elsif row_count < 42 then index(10 downto 6) <= "00101"; -- Cyan Pixels plus fill
elsif row_count < 43 then index(10 downto 6) <= "00110"; -- Cyan + green Pixels plus fill
elsif row_count < 56 then index(10 downto 6) <= "00111"; -- Green plus fill
elsif row_count < 71 then index(10 downto 6) <= "01000"; -- Magenta plus fill
elsif row_count < 72 then index(10 downto 6) <= "01001"; -- Magenta + red plus fill
elsif row_count < 86 then index(10 downto 6) <= "01010"; -- red Pixels plus fill
elsif row_count < 87 then index(10 downto 6) <= "01011"; -- red + blue Pixels plus fill
elsif row_count < 100 then index(10 downto 6) <= "01100"; -- blue plus fill
elsif row_count = 100 then index(10 downto 6) <= "01101"; -- Pixels BS and VS-ID block (no VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
elsif line_count = 599 then -- Last line of active video
if row_count < 1 then index(10 downto 6) <= "10000"; -- Just blank end
elsif row_count < 14 then index(10 downto 6) <= "00001"; -- White *8 plus fill
elsif row_count < 15 then index(10 downto 6) <= "00010"; -- White + Yellow plus fill
elsif row_count < 29 then index(10 downto 6) <= "00011"; -- Yellow Pixels plus fill
elsif row_count < 30 then index(10 downto 6) <= "00100"; -- Yellow + Cyan plus fill
elsif row_count < 42 then index(10 downto 6) <= "00101"; -- Cyan Pixels plus fill
elsif row_count < 43 then index(10 downto 6) <= "00110"; -- Cyan + green Pixels plus fill
elsif row_count < 56 then index(10 downto 6) <= "00111"; -- Green plus fill
elsif row_count < 71 then index(10 downto 6) <= "01000"; -- Magenta plus fill
elsif row_count < 72 then index(10 downto 6) <= "01001"; -- Magenta + red plus fill
elsif row_count < 86 then index(10 downto 6) <= "01010"; -- red Pixels plus fill
elsif row_count < 87 then index(10 downto 6) <= "01011"; -- red + blue Pixels plus fill
elsif row_count < 100 then index(10 downto 6) <= "01100"; -- blue plus fill
elsif row_count = 100 then index(10 downto 6) <= "01110"; -- blue Pixels BS and VS-ID block (with VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
else
-----------------------------------------------------------------
-- Allow switching to/from the idle pattern duein the vertical blank
-----------------------------------------------------------------
if row_count < 100 then
switch_point <= '1';
else
switch_point <= '0';
end if;
if row_count = 100 then
index(10 downto 6) <= "01111"; -- Dummy symbols, BS and VS-ID block (with VBLANK flag)
else
index(10 downto 6) <= "00000"; -- Dummy symbols
end if;
end if;
else
index <= index + 2;
end if;
end if;
end process;
end architecture; | mit | c3e5eb8af7a7547ef3b3dab88098d43a | 0.496244 | 3.449716 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_zunit-fir4sh.vhd | 1 | 8,910 | ------------------------------------------------------------------------------
-- Testbench for zunit.vhd
-- configures a 4-tap FIR (coefficients are shifts)
--
-- Project :
-- File : tb_zunit-fir4sh.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/28
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_FIR.all;
architecture fir4sh of tb_ZUnit is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data, inlevel, wr_ncycl, rd_ncycl, running,
outlevel, pop_data);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec := fir4shift;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "fir4sh.h";
begin -- fir4sh
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
constant NDATA : integer := 12; -- nr. of data elements
constant NRUNCYCLES : integer := 12; -- nr. of run cycles
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- -----------------------------------------------
-- reset (ZREG_RST:W)
-- -----------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- push data into in buffer (ZREG_FIFO0:W)
-- -----------------------------------------------
tbStatus <= push_data;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- DataInxD <= std_logic_vector(to_signed(80, IFWIDTH));
-- wait for CLK_PERIOD;
-- for i in 12 to NDATA loop
for i in 1 to NDATA loop
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-- -----------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-- -----------------------------------------------
-- computation running
-- -----------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 0 to NRUNCYCLES-1 loop
wait for CLK_PERIOD;
end loop; -- i
-- -----------------------------------------------
-- pop data from out buffer (ZREG_FIFO1:R)
-- -----------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
for i in 0 to NDATA loop
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- done; stop simulation
-- -----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end fir4sh;
| bsd-3-clause | 89139514f9d014e90626d4d66b40001e | 0.461728 | 3.877285 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpStream/unitValidExtractor/hdl/ValidExtractor_tb.vhd | 1 | 2,688 | -------------------------------------------------------------------------------
-- Title : Testbench for design "ValidExtractor"
-- Project :
-------------------------------------------------------------------------------
-- File : ValidExtractor_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- Created : 2017-12-12
-- Last update: 2017-12-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-12-12 1.0 fxst Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity ValidExtractor_tb is
end entity ValidExtractor_tb;
-------------------------------------------------------------------------------
architecture bhv of ValidExtractor_tb is
constant strobe_time : time := 1000 ns;
-- component generics
constant data_width_g : natural := 24;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal asi_valid : std_logic := '0';
signal asi_data : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
signal aso_valid : std_logic;
signal aso_data : std_logic_vector(data_width_g-1 downto 0);
signal coe_sample_strobe : std_logic;
begin -- architecture bhv
-- component instantiation
DUT : entity work.ValidExtractor
generic map (
data_width_g => data_width_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
asi_valid => asi_valid,
asi_data => asi_data,
aso_valid => aso_valid,
aso_data => aso_data,
coe_sample_strobe => coe_sample_strobe);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
-- strobe generation
valid : process is
begin -- process
wait for strobe_time;
wait until rising_edge(csi_clk);
asi_valid <= '1';
wait until rising_edge(csi_clk);
asi_valid <= '0';
end process;
-- waveform generation
WaveGen_Proc : process
begin
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
wait;
end process WaveGen_Proc;
end architecture bhv;
-------------------------------------------------------------------------------
| gpl-3.0 | 0635c10da05d0335e8b40aa6fddfa85e | 0.432292 | 4.472546 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm/tb_tstadpcm.vhd | 1 | 12,152 | ------------------------------------------------------------------------------
-- Testbench for the ADPCM configuration for the zippy array
--
-- Project :
-- File : $Id: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/15
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
-- This testbnech tests the ADPCM configuration for the zunit
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTADPCM.all;
entity tb_tstadpcm is
end tb_tstadpcm;
architecture arch of tb_tstadpcm is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant DELAY : integer := 2; -- processing delay of circuit,
-- due to pipelining
signal NDATA : integer := 0; -- nr. of data elements
signal NRUNCYCLES : integer := 0; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec := tstadpcmcfg;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstadpcm_cfg.h";
file TVFILE : text open read_mode is "test.adpcm.txt"; -- adpcm encoded
-- input file
file ERFILE : text open read_mode is "test.pcm.txt"; -- decoded file in
-- PCM format
--------------------------------------------------------------------
-- test vectors
-- out = c(0) ? a : b
--
-- The testbench feeds input a also to the mux input, i.e. the output of the
-- multiplexer is alway determined by the LSB of input A
--------------------------------------------------------------------
begin -- arch
assert (N_ROWS = 7) report "configuration needs N_ROWS=7" severity failure;
assert (N_COLS = 7) report "configuration needs N_COLS=7" severity failure;
assert (N_HBUSN >= 2) report "configuration needs N_HBUSN>=2" severity failure;
assert (N_HBUSS >= 2) report "configuration needs N_HBUSS>=2" severity failure;
assert (N_VBUSE >= 1) report "configuration needs N_VBUSE>=1" severity failure;
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable l : line;
variable tv : std_logic_vector(3 downto 0);
variable tvstring : string(tv'range);
variable expr : std_logic_vector(15 downto 0);
variable exprstring : string(expr'range);
variable tvcount : integer := 0;
begin -- process stimuliTb
-- while not endfile(TVFILE) loop
--
-- readline(TVFILE, l);
-- read(l, tvstring);
-- tv := to_std_logic_vector(tvstring); -- from txt_util
--
-- readline(ERFILE, l);
-- read(l, exprstring);
-- expr := to_std_logic_vector(exprstring);
--
-- assert false
-- report "tv=" & str(tv) & " expr= " & str(expr)
-- severity note;
-- end loop;
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
while not endfile(TVFILE) loop
readline(TVFILE, l);
read(l, tvstring);
tv := to_std_logic_vector(tvstring); -- defined in txt_util
DataInxD <= (others => '0');
DataInxD(3 downto 0) <= tv;
tvcount := tvcount + 1;
wait for CLK_PERIOD;
end loop;
-- determine length of data from input file
NDATA <= tvcount;
NRUNCYCLES <= tvcount + DELAY;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
-------------------------------------------------
-- pop 2 words from out buffer (ZREG_FIFO1:R)
-- delay of circuit due to registers (pipelining)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for DELAY*CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO1:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
if not endfile(ERFILE) then
readline(ERFILE, l);
read(l, exprstring);
expr := to_std_logic_vector(exprstring);
else
expr := (others => '0');
end if;
expectedresponse := std_logic_vector(resize(signed(expr), DATAWIDTH));
response := DataOutxD(DATAWIDTH-1 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 61e7aa1d6869c11174c9a3a686d7e485 | 0.46766 | 4.15311 | false | false | false | false |
hamsternz/FPGA_DisplayPort | test_benches/tb_training_and_channel_delay.vhd | 1 | 4,889 | ----------------------------------------------------------------------------------
-- Module Name: tb_training_and_channel_delay - Behavioral
--
-- Description: A testbench for training_and_channel_delay
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_training_and_channel_delay is
end entity;
architecture tb of tb_training_and_channel_delay is
component training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
send_pattern_1 : in std_logic;
send_pattern_2 : in std_logic;
data_in : in std_logic_vector(19 downto 0);
data_out : out std_logic_vector(19 downto 0)
);
end component;
signal clk : std_logic := '0';
signal channel_delay : std_logic_vector(1 downto 0) := (others => '0');
signal send_pattern_1 : std_logic := '0';
signal send_pattern_2 : std_logic := '1';
signal data_in : std_logic_vector(19 downto 0) := (others => '0');
signal data_out_0 : std_logic_vector(19 downto 0) := (others => '0');
signal data_out_1 : std_logic_vector(19 downto 0) := (others => '0');
begin
clk_proc: process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
stim_proc: process
begin
for i in 1 to 100 loop
wait until rising_edge(clk);
end loop;
send_pattern_2 <= '0';
data_in <= x"CCCCC";
wait until rising_edge(clk);
data_in <= x"33333";
end process;
uut0: training_and_channel_delay port map (
clk => clk,
channel_delay => "00",
send_pattern_1 => send_pattern_1,
send_pattern_2 => send_pattern_2,
data_in => data_in,
data_out => data_out_0
);
uut1: training_and_channel_delay port map (
clk => clk,
channel_delay => "01",
send_pattern_1 => send_pattern_1,
send_pattern_2 => send_pattern_2,
data_in => data_in,
data_out => data_out_1
);
end architecture; | mit | a7c2dde7d6ebe37e533a86be61c1caa7 | 0.515034 | 4.225583 | false | false | false | false |
plessl/zippy | vhdl/reg.vhd | 1 | 3,529 | ------------------------------------------------------------------------------
-- Various registers for the usage in the zippy architecture
--
-- Project :
-- File : $Id: $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Changed : $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
-- Merged all files that defined registers.
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity Reg_En is
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end Reg_En;
architecture simple of Reg_En is
begin -- simple
Reg : process (ClkxC, RstxRB)
begin -- process Reg
if RstxRB = '0' then -- asynchronous reset (active low)
DoutxDO <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if EnxEI = '1' then
DoutxDO <= DinxDI;
end if;
end if;
end process Reg;
end simple;
------------------------------------------------------------------------------
-- Register with synchronous clear and enable (clear has precedence)
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity Reg_Clr_En is
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxEI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end Reg_Clr_En;
architecture simple of Reg_Clr_En is
begin -- simple
Reg : process (ClkxC, RstxRB)
begin -- process Reg
if RstxRB = '0' then -- asynchronous reset (active low)
DoutxDO <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if ClrxEI = '1' then -- clear has precedence
DoutxDO <= (others => '0');
elsif EnxEI = '1' then
DoutxDO <= DinxDI;
end if;
end if;
end process Reg;
end simple;
------------------------------------------------------------------------------
-- Register with asynchronous clear and synchronous enable
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity Reg_AClr_En is
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxABI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end Reg_AClr_En;
architecture simple of Reg_AClr_En is
begin -- simple
Reg : process (ClkxC, RstxRB, ClrxABI)
begin -- process Reg
if RstxRB = '0' or ClrxABI = '0' then -- asynchronous reset (active low)
DoutxDO <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if EnxEI = '1' then
DoutxDO <= DinxDI;
end if;
end if;
end process Reg;
end simple;
| bsd-3-clause | 8c89d518999f891453086d31165262cd | 0.51771 | 3.699161 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/test_source.vhd | 1 | 23,968 | ----------------------------------------------------------------------------------
-- Module Name: test_source - Behavioral
--
-- Description: Provides a valid stream of DisplayPort Video data
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_source is
Port ( clk : in STD_LOGIC;
stream_channel_count : out std_logic_vector(2 downto 0);
ready : out STD_LOGIC;
data : out STD_LOGIC_VECTOR (72 downto 0));
end test_source;
architecture Behavioral of test_source is
component test_source_800_600_RGB_444_colourbars_ch1 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_800_600_RGB_444_ch1 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_3840_2160_YCC_422_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_800_600_RGB_444_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_800_600_RGB_444_ch4 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component insert_main_stream_attrbutes_one_channel is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
component insert_main_stream_attrbutes_two_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
component insert_main_stream_attrbutes_four_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
signal M_value : std_logic_vector(23 downto 0);
signal N_value : std_logic_vector(23 downto 0);
signal H_visible : std_logic_vector(11 downto 0);
signal V_visible : std_logic_vector(11 downto 0);
signal H_total : std_logic_vector(11 downto 0);
signal V_total : std_logic_vector(11 downto 0);
signal H_sync_width : std_logic_vector(11 downto 0);
signal V_sync_width : std_logic_vector(11 downto 0);
signal H_start : std_logic_vector(11 downto 0);
signal V_start : std_logic_vector(11 downto 0);
signal H_vsync_active_high : std_logic;
signal V_vsync_active_high : std_logic;
signal flag_sync_clock : std_logic;
signal flag_YCCnRGB : std_logic;
signal flag_422n444 : std_logic;
signal flag_YCC_colour_709 : std_logic;
signal flag_range_reduced : std_logic;
signal flag_interlaced_even : std_logic;
signal flags_3d_Indicators : std_logic_vector(1 downto 0);
signal bits_per_colour : std_logic_vector(4 downto 0);
signal raw_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
begin
--i_test_source: test_source_3840_2160_YCC_422_ch2 port map (
--i_test_source: test_source_800_600_RGB_444_ch1 port map (
--i_test_source: test_source_800_600_RGB_444_ch2 port map (
--i_test_source: test_source_800_600_RGB_444_ch4 port map (
i_test_source: test_source_800_600_RGB_444_colourbars_ch1 port map (
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
stream_channel_count => stream_channel_count,
clk => clk,
ready => ready,
data => raw_data
);
i_insert_main_stream_attrbutes_one_channel: insert_main_stream_attrbutes_one_channel port map (
--i_insert_main_stream_attrbutes_two_channels: insert_main_stream_attrbutes_two_channels port map (
--i_insert_main_stream_attrbutes_four_channels: insert_main_stream_attrbutes_four_channels port map (
clk => clk,
active => '1',
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
-----------------------------------------------------
-- The stream of pixel data coming in
-----------------------------------------------------
in_data => raw_data,
-----------------------------------------------------
-- The stream of pixel data going out
-----------------------------------------------------
out_data => data
);
end Behavioral; | mit | bb20bc18acccb8ec1899e2666b1cfa08 | 0.448807 | 4.431953 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/ipcore_dir/dualBRAM/example_design/dualBRAM_exdes.vhd | 1 | 5,387 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dualBRAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY dualBRAM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END dualBRAM_exdes;
ARCHITECTURE xilinx OF dualBRAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT dualBRAM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : dualBRAM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| mit | 94f9010bb680bed8e691d325fddca83c | 0.55077 | 4.580782 | false | false | false | false |
plessl/zippy | vhdl/contextregfile.vhd | 1 | 2,522 | ------------------------------------------------------------------------------
-- Context register file
--
-- Project :
-- File : contextregfile.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/06
-- Last changed: $LastChangedDate: 2005-01-13 18:02:10 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- generates the register file that holds the state of a context. Used
-- in the processing element.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-06 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
entity ContextRegFile is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
EnxEI : in std_logic;
DinxDI : in data_word;
DoutxDO : out data_word);
end ContextRegFile;
architecture simple of ContextRegFile is
signal Clr : std_logic_vector(N_CONTEXTS-1 downto 0);
signal En : std_logic_vector(N_CONTEXTS-1 downto 0);
signal Dout : data_vector(N_CONTEXTS-1 downto 0);
begin -- simple
Regs : for i in N_CONTEXTS-1 downto 0 generate
Reg_i : Reg_Clr_En
generic map (
WIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxEI => Clr(i),
EnxEI => En(i),
DinxDI => DinxDI,
DoutxDO => Dout(i));
end generate Regs;
-- FIXME: this can be written more elegantly
ClrDemux : process (ClrContextxSI, ClrContextxEI)
begin
for i in N_CONTEXTS-1 downto 0 loop
Clr(i) <= '0';
end loop; -- i
Clr(to_integer(unsigned(ClrContextxSI))) <= ClrContextxEI;
end process ClrDemux;
EnDemux : process (ContextxSI, EnxEI)
begin
for i in N_CONTEXTS-1 downto 0 loop
En(i) <= '0';
end loop; -- i
En(to_integer(unsigned(ContextxSI))) <= EnxEI;
end process EnDemux;
-- out mux
DoutxDO <= Dout(to_integer(unsigned(ContextxSI)));
end simple;
| bsd-3-clause | 4d54079b9123d71fdac74a37ed232ecb | 0.553529 | 3.618364 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/unitI2SToAvalonST/hdl/I2SToAvalonST-Rtl-a.vhd | 1 | 2,961 | architecture Rtl of I2SToAvalonST is
type aInputState is (Waiting, ReceivingSerData);
-- bclk set, for sync and delay
type aSyncSet is record
Meta : std_logic;
Sync : std_logic;
Dlyd : std_logic;
end record;
constant cInitValSync : aSyncSet := (
Meta => '0',
Sync => '0',
Dlyd => '0'
);
type aRegSet is record
State : aInputState; -- current state
D : std_logic_vector(gDataWidth-1 downto 0); -- data
BitIdx : unsigned(gDataWidthLen-1 downto 0); -- current bit index in data
Bclk : aSyncSet; -- bclk signals
Lrc : aSyncSet; -- left or rigth channel
LeftVal : std_logic; -- left channel valid
RightVal : std_logic; -- right channel valid
end record;
constant cInitValR : aRegSet := (
State => Waiting,
D => (others => '0'),
Bclk => cInitValSync,
Lrc => cInitValSync,
LeftVal => '0',
RightVal => '0',
BitIdx => (others => '0')
);
signal R, NxR : aRegSet;
begin -- architecture Rtl
-- register process
Reg : process(iClk, inReset)
begin
-- low active reset
if inReset = '0' then
R <= cInitValR;
-- rising clk edge
elsif rising_edge(iClk) then
R <= NxR;
end if;
end process;
Comb : process (R, iLRC, iBCLK, iDAT) is
begin -- process
-- default
NxR <= R;
-- reset valid flags
NxR.LeftVal <= '0';
NxR.RightVal <= '0';
-- sync input and delay
NxR.Bclk.Meta <= iBCLK;
NxR.Bclk.Sync <= R.Bclk.Meta;
NxR.Bclk.Dlyd <= R.Bclk.Sync;
NxR.Lrc.Meta <= iLRC;
NxR.Lrc.Sync <= R.Lrc.Meta;
NxR.Lrc.Dlyd <= R.Lrc.Sync;
case R.State is
-- waiting for input data
when Waiting =>
-- rising edge on LRC - Left Channel
if (R.Lrc.Dlyd = '0' and R.Lrc.Sync = '1')
-- falling edge on LRC - Right Channel
or (R.Lrc.Dlyd = '1' and R.Lrc.Sync = '0') then
NxR.BitIdx <= to_unsigned(gDataWidth-1, NxR.BitIdx'length);
NxR.State <= ReceivingSerData;
end if;
when ReceivingSerData =>
-- read input data
NxR.D(to_integer(R.BitIdx)) <= iDAT;
-- rising edge on BCLK
if R.Bclk.Dlyd = '0' and R.Bclk.Sync = '1' then
-- check bit index
if R.BitIdx = 0 then
-- end of frame
NxR.State <= Waiting;
if R.Lrc.Sync = '1' then
-- left channel valid
NxR.LeftVal <= '1';
else
-- right channel valid
NxR.RightVal <= '1';
end if;
else
-- decrease bit index
NxR.BitIdx <= R.BitIdx - 1;
end if;
end if;
end case;
end process;
-- output
oLeftData <= R.D;
oLeftValid <= R.LeftVal;
oRightData <= R.D;
oRightValid <= R.RightVal;
end architecture Rtl;
| gpl-3.0 | 98132662b0023de6670aff3bdfacda9b | 0.525836 | 3.415225 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpStream/unitMMtoST/hdl/MMtoST-ea.vhd | 1 | 13,228 | -------------------------------------------------------------------------------
-- Title : Avalon MM to Avalon ST
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Memory Mapped Slave to Avalon Streaming with Left and Right Channel
-- Used to stream audio data from the soc linux to the fpga
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MMtoST is
generic (
data_width_g : natural := 24;
fifo_depth_g : natural := 128;
fifo_adr_width_g : natural := 8 -- log2(fifo_depth_g) , at least 4
);
port (
csi_clk : in std_logic;
rsi_reset_n : in std_logic;
-- memory mapped interface s0
avs_s0_chipselect : in std_logic;
avs_s0_write : in std_logic;
avs_s0_read : in std_logic;
avs_s0_address : in std_logic_vector(1 downto 0);
avs_s0_writedata : in std_logic_vector(31 downto 0);
avs_s0_readdata : out std_logic_vector(31 downto 0);
-- interrupt sender
irs_irq : out std_logic;
-- avalon streaming left and right channel
asi_left_valid : in std_logic;
asi_left_data : in std_logic_vector(data_width_g-1 downto 0);
asi_right_valid : in std_logic;
asi_right_data : in std_logic_vector(data_width_g-1 downto 0);
aso_left_valid : out std_logic;
aso_left_data : out std_logic_vector(data_width_g-1 downto 0);
aso_right_valid : out std_logic;
aso_right_data : out std_logic_vector(data_width_g-1 downto 0)
);
end entity MMtoST;
architecture Rtl of MMtoST is
-- audio in registers
signal read_interrupt_en : std_ulogic;
signal clear_read_fifos : std_ulogic;
signal read_interrupt : std_ulogic;
-- audio out registers
signal write_interrupt_en : std_ulogic;
signal clear_write_fifos : std_ulogic;
signal write_interrupt : std_ulogic;
-- fifospace registers
signal left_channel_read_available : unsigned(fifo_adr_width_g-1 downto 0);
signal right_channel_read_available : unsigned(fifo_adr_width_g-1 downto 0);
signal left_channel_write_space : unsigned(fifo_adr_width_g-1 downto 0);
signal right_channel_write_space : unsigned(fifo_adr_width_g-1 downto 0);
-- audio signal
signal new_left_channel_audio : std_logic_vector(data_width_g-1 downto 0);
signal new_right_channel_audio : std_logic_vector(data_width_g-1 downto 0);
-- read and write strobes
signal rd_left : std_ulogic;
signal rd_right : std_ulogic;
signal wr_left : std_ulogic;
signal wr_right : std_ulogic;
-- fifo read stdulogicvector
signal asi_left_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
signal asi_right_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
signal aso_left_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
signal aso_right_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
-- fifo empty and full signals
signal asi_left_fifo_empty : std_ulogic;
signal asi_right_fifo_empty : std_ulogic;
signal aso_left_fifo_empty : std_ulogic;
signal aso_right_fifo_empty : std_ulogic;
signal asi_left_fifo_full : std_ulogic;
signal asi_right_fifo_full : std_ulogic;
signal aso_left_fifo_full : std_ulogic;
signal aso_right_fifo_full : std_ulogic;
-- fifo space
signal aso_left_fifo_space : unsigned(fifo_adr_width_g-1 downto 0);
signal aso_right_fifo_space : unsigned(fifo_adr_width_g-1 downto 0);
-- address constants
constant control_c : std_logic_vector(1 downto 0) := "00";
constant fifospace_c : std_logic_vector(1 downto 0) := "01";
constant leftdata_c : std_logic_vector(1 downto 0) := "10";
constant rightdata_c : std_logic_vector(1 downto 0) := "11";
begin -- architecture Rtl
-- interrupt sender register
irq_reg : process (csi_clk, rsi_reset_n) is
begin -- process irq_reg
if rsi_reset_n = '0' then -- asynchronous reset (active low)
irs_irq <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
irs_irq <= read_interrupt or write_interrupt;
end if;
end process irq_reg;
-- memory mapped read
mm_read : process (csi_clk, rsi_reset_n) is
begin -- process mm_read
if rsi_reset_n = '0' then -- asynchronous reset (active low)
avs_s0_readdata <= (others => '0');
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s0_chipselect = '1' then
-- default
avs_s0_readdata <= (others => '0');
-- select address
case avs_s0_address is
when control_c =>
avs_s0_readdata(31 downto 10) <= (others => '-');
avs_s0_readdata(9) <= write_interrupt;
avs_s0_readdata(8) <= read_interrupt;
avs_s0_readdata(7 downto 4) <= (others => '-');
avs_s0_readdata(3) <= clear_write_fifos;
avs_s0_readdata(2) <= clear_read_fifos;
avs_s0_readdata(1) <= write_interrupt_en;
avs_s0_readdata(0) <= read_interrupt_en;
when fifospace_c =>
avs_s0_readdata(31 downto 24) <= std_logic_vector(left_channel_write_space);
avs_s0_readdata(23 downto 16) <= std_logic_vector(right_channel_write_space);
avs_s0_readdata(15 downto 8) <= std_logic_vector(left_channel_read_available);
avs_s0_readdata(7 downto 0) <= std_logic_vector(right_channel_read_available);
when leftdata_c =>
avs_s0_readdata(data_width_g-1 downto 0) <= new_left_channel_audio;
when rightdata_c =>
avs_s0_readdata(data_width_g-1 downto 0) <= new_right_channel_audio;
when others =>
avs_s0_readdata <= (others => 'X');
end case;
else
avs_s0_readdata <= (others => '0');
end if;
end if;
end process mm_read;
-- memory mapped write
mm_write : process (csi_clk, rsi_reset_n) is
begin -- process mm_write
if rsi_reset_n = '0' then -- asynchronous reset (active low)
read_interrupt_en <= '0';
write_interrupt_en <= '0';
clear_read_fifos <= '0';
clear_write_fifos <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s0_chipselect = '1' and avs_s0_write = '1' then
case avs_s0_address is
when control_c =>
read_interrupt_en <= avs_s0_writedata(0);
write_interrupt_en <= avs_s0_writedata(1);
clear_read_fifos <= avs_s0_writedata(2);
clear_write_fifos <= avs_s0_writedata(3);
when leftdata_c =>
when rightdata_c =>
when others => null;
end case;
end if;
end if;
end process mm_write;
-- interrupt behavior
-- irq is set when the fifo is filled to 75% or more
-- when less it will be cleared
irq_bhv : process (csi_clk, rsi_reset_n) is
begin -- process irq_bhv
if rsi_reset_n = '0' then -- asynchronous reset (active low)
read_interrupt <= '0';
write_interrupt <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
-- read interrupt
if read_interrupt_en = '1' then
read_interrupt <= asi_left_fifo_full or asi_right_fifo_full
or left_channel_read_available(fifo_adr_width_g-1)
or (left_channel_read_available(fifo_adr_width_g-2) and left_channel_read_available(fifo_adr_width_g-3))
or right_channel_read_available(fifo_adr_width_g-1)
or (right_channel_read_available(fifo_adr_width_g-2) and right_channel_read_available(fifo_adr_width_g-3));
else
read_interrupt <= '0';
end if;
-- write interrupt
if write_interrupt_en = '1' then
write_interrupt <= aso_left_fifo_empty or aso_right_fifo_empty or
left_channel_write_space(fifo_adr_width_g-1)
or (left_channel_write_space(fifo_adr_width_g-2) and left_channel_write_space(fifo_adr_width_g-3))
or right_channel_write_space(fifo_adr_width_g-1)
or (right_channel_write_space(fifo_adr_width_g-2) and right_channel_write_space(fifo_adr_width_g-3));
else
write_interrupt <= '0';
end if;
end if;
end process irq_bhv;
-- combinatoric logic for read and write strobe
rd_wr_stb : process (avs_s0_address, avs_s0_chipselect, avs_s0_read, avs_s0_write) is
begin -- process rd_wr_stb
rd_left <= '0';
rd_right <= '0';
wr_left <= '0';
wr_right <= '0';
if avs_s0_chipselect = '1' then
case avs_s0_address is
when leftdata_c =>
if avs_s0_read = '1' then
rd_left <= '1';
end if;
if avs_s0_write = '1' then
wr_left <= '1';
end if;
when rightdata_c =>
if avs_s0_read = '1' then
rd_right <= '1';
end if;
if avs_s0_write = '1' then
wr_right <= '1';
end if;
when others => null;
end case;
end if;
end process rd_wr_stb;
-- st -> MM fifo
asi_left_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => asi_left_valid,
rd_i => rd_left,
wr_data_i => to_StduLogicVector(asi_left_data),
rd_data_o => asi_left_fifo_data,
clear_i => clear_read_fifos,
full_o => asi_left_fifo_full,
empty_o => asi_left_fifo_empty,
space_o => left_channel_read_available);
new_left_channel_audio <= to_StdLogicVector(asi_left_fifo_data) when asi_left_fifo_empty = '0'
else (others => '0') when asi_left_fifo_empty = '1'
else (others => 'X');
-- st -> MM fifo
asi_right_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => asi_right_valid,
rd_i => rd_right,
wr_data_i => to_StduLogicVector(asi_right_data),
rd_data_o => asi_right_fifo_data,
clear_i => clear_read_fifos,
full_o => asi_right_fifo_full,
empty_o => asi_right_fifo_empty,
space_o => right_channel_read_available);
new_right_channel_audio <= to_StdLogicVector(asi_right_fifo_data) when asi_right_fifo_empty = '0'
else (others => '0') when asi_right_fifo_empty = '1'
else (others => 'X');
-- MM -> st fifo
aso_left_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => wr_left,
rd_i => asi_left_valid,
wr_data_i => to_stdulogicvector(avs_s0_writedata(data_width_g-1 downto 0)),
rd_data_o => aso_left_fifo_data,
clear_i => clear_write_fifos,
full_o => aso_left_fifo_full,
empty_o => aso_left_fifo_empty,
space_o => aso_left_fifo_space);
aso_left_data <= to_stdLogicVector(aso_left_fifo_data) when aso_left_fifo_empty = '0'
else (others => '0') when aso_left_fifo_empty = '1'
else (others => 'X');
-- calculate remaining space
left_channel_write_space <= fifo_depth_g - aso_left_fifo_space;
-- MM -> st fifo
aso_right_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => wr_right,
rd_i => asi_right_valid,
wr_data_i => to_stdulogicvector(avs_s0_writedata(data_width_g-1 downto 0)),
rd_data_o => aso_right_fifo_data,
clear_i => clear_write_fifos,
full_o => aso_right_fifo_full,
empty_o => aso_right_fifo_empty,
space_o => aso_right_fifo_space);
aso_right_data <= to_stdLogicVector(aso_right_fifo_data) when aso_right_fifo_empty = '0'
else (others => '0') when aso_right_fifo_empty = '1'
else (others => 'X');
-- calculate remaining space
right_channel_write_space <= fifo_depth_g - aso_right_fifo_space;
-- delay valid with one clk cycle, because read needs one clk cycle
dly_valid : process (csi_clk, rsi_reset_n) is
begin -- process dly_valid
if rsi_reset_n = '0' then -- asynchronous reset (active low)
aso_left_valid <= '0';
aso_right_valid <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
aso_left_valid <= asi_left_valid;
aso_right_valid <= asi_right_valid;
end if;
end process dly_valid;
end architecture Rtl;
| gpl-3.0 | 957e068a33cfbc4c5f70973da889f99e | 0.571817 | 3.296287 | false | false | false | false |
kenkendk/sme | src/SME.VHDL/Templates/system_types.vhdl | 1 | 86,022 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- package containing system types of SME
package SYSTEM_TYPES is
pure function clog2 (A : NATURAL) return INTEGER;
subtype T_SYSTEM_BOOL is std_logic;
subtype T_SYSTEM_UINT8 is unsigned(7 downto 0);
subtype T_SYSTEM_UINT16 is unsigned(15 downto 0);
subtype T_SYSTEM_UINT32 is unsigned(31 downto 0);
subtype T_SYSTEM_UINT64 is unsigned(63 downto 0);
subtype T_SYSTEM_INT8 is signed(7 downto 0);
subtype T_SYSTEM_INT16 is signed(15 downto 0);
subtype T_SYSTEM_INT32 is signed(31 downto 0);
subtype T_SYSTEM_INT64 is signed(63 downto 0);
subtype T_SYSTEM_FLOAT is std_logic_vector(31 downto 0);
subtype T_SYSTEM_DOUBLE is std_logic_vector(63 downto 0);
type T_SYSTEM_BOOL_ARRAY is array(natural range <>) of T_SYSTEM_BOOL;
type T_SYSTEM_UINT8_ARRAY is array(natural range <>) of T_SYSTEM_UINT8;
type T_SYSTEM_UINT16_ARRAY is array(natural range <>) of T_SYSTEM_UINT16;
type T_SYSTEM_UINT32_ARRAY is array(natural range <>) of T_SYSTEM_UINT32;
type T_SYSTEM_UINT64_ARRAY is array(natural range <>) of T_SYSTEM_UINT64;
type T_SYSTEM_INT8_ARRAY is array(natural range <>) of T_SYSTEM_INT8;
type T_SYSTEM_INT16_ARRAY is array(natural range <>) of T_SYSTEM_INT16;
type T_SYSTEM_INT32_ARRAY is array(natural range <>) of T_SYSTEM_INT32;
type T_SYSTEM_INT64_ARRAY is array(natural range <>) of T_SYSTEM_INT64;
type T_SYSTEM_FLOAT_ARRAY is array(natural range <>) of T_SYSTEM_FLOAT;
type T_SYSTEM_DOUBLE_ARRAY is array(natural range <>) of T_SYSTEM_DOUBLE;
subtype T_UINT1 is unsigned(0 downto 0);
subtype T_UINT2 is unsigned(1 downto 0);
subtype T_UINT3 is unsigned(2 downto 0);
subtype T_UINT4 is unsigned(3 downto 0);
subtype T_UINT5 is unsigned(4 downto 0);
subtype T_UINT6 is unsigned(5 downto 0);
subtype T_UINT7 is unsigned(6 downto 0);
subtype T_UINT9 is unsigned(8 downto 0);
subtype T_UINT10 is unsigned(9 downto 0);
subtype T_UINT11 is unsigned(10 downto 0);
subtype T_UINT12 is unsigned(11 downto 0);
subtype T_UINT13 is unsigned(12 downto 0);
subtype T_UINT14 is unsigned(13 downto 0);
subtype T_UINT15 is unsigned(14 downto 0);
subtype T_UINT17 is unsigned(16 downto 0);
subtype T_UINT18 is unsigned(17 downto 0);
subtype T_UINT19 is unsigned(18 downto 0);
subtype T_UINT20 is unsigned(19 downto 0);
subtype T_UINT21 is unsigned(20 downto 0);
subtype T_UINT22 is unsigned(21 downto 0);
subtype T_UINT23 is unsigned(22 downto 0);
subtype T_UINT24 is unsigned(23 downto 0);
subtype T_UINT25 is unsigned(24 downto 0);
subtype T_UINT26 is unsigned(25 downto 0);
subtype T_UINT27 is unsigned(26 downto 0);
subtype T_UINT28 is unsigned(27 downto 0);
subtype T_UINT29 is unsigned(28 downto 0);
subtype T_UINT30 is unsigned(29 downto 0);
subtype T_UINT31 is unsigned(30 downto 0);
subtype T_UINT33 is unsigned(32 downto 0);
subtype T_UINT34 is unsigned(33 downto 0);
subtype T_UINT35 is unsigned(34 downto 0);
subtype T_UINT36 is unsigned(35 downto 0);
subtype T_UINT37 is unsigned(36 downto 0);
subtype T_UINT38 is unsigned(37 downto 0);
subtype T_UINT39 is unsigned(38 downto 0);
subtype T_UINT40 is unsigned(39 downto 0);
subtype T_UINT41 is unsigned(40 downto 0);
subtype T_UINT42 is unsigned(41 downto 0);
subtype T_UINT43 is unsigned(42 downto 0);
subtype T_UINT44 is unsigned(43 downto 0);
subtype T_UINT45 is unsigned(44 downto 0);
subtype T_UINT46 is unsigned(45 downto 0);
subtype T_UINT47 is unsigned(46 downto 0);
subtype T_UINT48 is unsigned(47 downto 0);
subtype T_UINT49 is unsigned(48 downto 0);
subtype T_UINT50 is unsigned(49 downto 0);
subtype T_UINT51 is unsigned(50 downto 0);
subtype T_UINT52 is unsigned(51 downto 0);
subtype T_UINT53 is unsigned(52 downto 0);
subtype T_UINT54 is unsigned(53 downto 0);
subtype T_UINT55 is unsigned(54 downto 0);
subtype T_UINT56 is unsigned(55 downto 0);
subtype T_UINT57 is unsigned(56 downto 0);
subtype T_UINT58 is unsigned(57 downto 0);
subtype T_UINT59 is unsigned(58 downto 0);
subtype T_UINT60 is unsigned(59 downto 0);
subtype T_UINT61 is unsigned(60 downto 0);
subtype T_UINT62 is unsigned(61 downto 0);
subtype T_UINT63 is unsigned(62 downto 0);
subtype T_INT1 is signed(0 downto 0);
subtype T_INT2 is signed(1 downto 0);
subtype T_INT3 is signed(2 downto 0);
subtype T_INT4 is signed(3 downto 0);
subtype T_INT5 is signed(4 downto 0);
subtype T_INT6 is signed(5 downto 0);
subtype T_INT7 is signed(6 downto 0);
subtype T_INT9 is signed(8 downto 0);
subtype T_INT10 is signed(9 downto 0);
subtype T_INT11 is signed(10 downto 0);
subtype T_INT12 is signed(11 downto 0);
subtype T_INT13 is signed(12 downto 0);
subtype T_INT14 is signed(13 downto 0);
subtype T_INT15 is signed(14 downto 0);
subtype T_INT17 is signed(16 downto 0);
subtype T_INT18 is signed(17 downto 0);
subtype T_INT19 is signed(18 downto 0);
subtype T_INT20 is signed(19 downto 0);
subtype T_INT21 is signed(20 downto 0);
subtype T_INT22 is signed(21 downto 0);
subtype T_INT23 is signed(22 downto 0);
subtype T_INT24 is signed(23 downto 0);
subtype T_INT25 is signed(24 downto 0);
subtype T_INT26 is signed(25 downto 0);
subtype T_INT27 is signed(26 downto 0);
subtype T_INT28 is signed(27 downto 0);
subtype T_INT29 is signed(28 downto 0);
subtype T_INT30 is signed(29 downto 0);
subtype T_INT31 is signed(30 downto 0);
subtype T_INT33 is signed(32 downto 0);
subtype T_INT34 is signed(33 downto 0);
subtype T_INT35 is signed(34 downto 0);
subtype T_INT36 is signed(35 downto 0);
subtype T_INT37 is signed(36 downto 0);
subtype T_INT38 is signed(37 downto 0);
subtype T_INT39 is signed(38 downto 0);
subtype T_INT40 is signed(39 downto 0);
subtype T_INT41 is signed(40 downto 0);
subtype T_INT42 is signed(41 downto 0);
subtype T_INT43 is signed(42 downto 0);
subtype T_INT44 is signed(43 downto 0);
subtype T_INT45 is signed(44 downto 0);
subtype T_INT46 is signed(45 downto 0);
subtype T_INT47 is signed(46 downto 0);
subtype T_INT48 is signed(47 downto 0);
subtype T_INT49 is signed(48 downto 0);
subtype T_INT50 is signed(49 downto 0);
subtype T_INT51 is signed(50 downto 0);
subtype T_INT52 is signed(51 downto 0);
subtype T_INT53 is signed(52 downto 0);
subtype T_INT54 is signed(53 downto 0);
subtype T_INT55 is signed(54 downto 0);
subtype T_INT56 is signed(55 downto 0);
subtype T_INT57 is signed(56 downto 0);
subtype T_INT58 is signed(57 downto 0);
subtype T_INT59 is signed(58 downto 0);
subtype T_INT60 is signed(59 downto 0);
subtype T_INT61 is signed(60 downto 0);
subtype T_INT62 is signed(61 downto 0);
subtype T_INT63 is signed(62 downto 0);
type T_UINT1_ARRAY is array(natural range <>) of T_UINT1;
type T_UINT2_ARRAY is array(natural range <>) of T_UINT2;
type T_UINT3_ARRAY is array(natural range <>) of T_UINT3;
type T_UINT4_ARRAY is array(natural range <>) of T_UINT4;
type T_UINT5_ARRAY is array(natural range <>) of T_UINT5;
type T_UINT6_ARRAY is array(natural range <>) of T_UINT6;
type T_UINT7_ARRAY is array(natural range <>) of T_UINT7;
type T_UINT9_ARRAY is array(natural range <>) of T_UINT9;
type T_UINT10_ARRAY is array(natural range <>) of T_UINT10;
type T_UINT11_ARRAY is array(natural range <>) of T_UINT11;
type T_UINT12_ARRAY is array(natural range <>) of T_UINT12;
type T_UINT13_ARRAY is array(natural range <>) of T_UINT13;
type T_UINT14_ARRAY is array(natural range <>) of T_UINT14;
type T_UINT15_ARRAY is array(natural range <>) of T_UINT15;
type T_UINT17_ARRAY is array(natural range <>) of T_UINT17;
type T_UINT18_ARRAY is array(natural range <>) of T_UINT18;
type T_UINT19_ARRAY is array(natural range <>) of T_UINT19;
type T_UINT20_ARRAY is array(natural range <>) of T_UINT20;
type T_UINT21_ARRAY is array(natural range <>) of T_UINT21;
type T_UINT22_ARRAY is array(natural range <>) of T_UINT22;
type T_UINT23_ARRAY is array(natural range <>) of T_UINT23;
type T_UINT24_ARRAY is array(natural range <>) of T_UINT24;
type T_UINT25_ARRAY is array(natural range <>) of T_UINT25;
type T_UINT26_ARRAY is array(natural range <>) of T_UINT26;
type T_UINT27_ARRAY is array(natural range <>) of T_UINT27;
type T_UINT28_ARRAY is array(natural range <>) of T_UINT28;
type T_UINT29_ARRAY is array(natural range <>) of T_UINT29;
type T_UINT30_ARRAY is array(natural range <>) of T_UINT30;
type T_UINT31_ARRAY is array(natural range <>) of T_UINT31;
type T_UINT33_ARRAY is array(natural range <>) of T_UINT33;
type T_UINT34_ARRAY is array(natural range <>) of T_UINT34;
type T_UINT35_ARRAY is array(natural range <>) of T_UINT35;
type T_UINT36_ARRAY is array(natural range <>) of T_UINT36;
type T_UINT37_ARRAY is array(natural range <>) of T_UINT37;
type T_UINT38_ARRAY is array(natural range <>) of T_UINT38;
type T_UINT39_ARRAY is array(natural range <>) of T_UINT39;
type T_UINT40_ARRAY is array(natural range <>) of T_UINT40;
type T_UINT41_ARRAY is array(natural range <>) of T_UINT41;
type T_UINT42_ARRAY is array(natural range <>) of T_UINT42;
type T_UINT43_ARRAY is array(natural range <>) of T_UINT43;
type T_UINT44_ARRAY is array(natural range <>) of T_UINT44;
type T_UINT45_ARRAY is array(natural range <>) of T_UINT45;
type T_UINT46_ARRAY is array(natural range <>) of T_UINT46;
type T_UINT47_ARRAY is array(natural range <>) of T_UINT47;
type T_UINT48_ARRAY is array(natural range <>) of T_UINT48;
type T_UINT49_ARRAY is array(natural range <>) of T_UINT49;
type T_UINT50_ARRAY is array(natural range <>) of T_UINT50;
type T_UINT51_ARRAY is array(natural range <>) of T_UINT51;
type T_UINT52_ARRAY is array(natural range <>) of T_UINT52;
type T_UINT53_ARRAY is array(natural range <>) of T_UINT53;
type T_UINT54_ARRAY is array(natural range <>) of T_UINT54;
type T_UINT55_ARRAY is array(natural range <>) of T_UINT55;
type T_UINT56_ARRAY is array(natural range <>) of T_UINT56;
type T_UINT57_ARRAY is array(natural range <>) of T_UINT57;
type T_UINT58_ARRAY is array(natural range <>) of T_UINT58;
type T_UINT59_ARRAY is array(natural range <>) of T_UINT59;
type T_UINT60_ARRAY is array(natural range <>) of T_UINT60;
type T_UINT61_ARRAY is array(natural range <>) of T_UINT61;
type T_UINT62_ARRAY is array(natural range <>) of T_UINT62;
type T_UINT63_ARRAY is array(natural range <>) of T_UINT63;
type T_INT1_ARRAY is array(natural range <>) of T_INT1;
type T_INT2_ARRAY is array(natural range <>) of T_INT2;
type T_INT3_ARRAY is array(natural range <>) of T_INT3;
type T_INT4_ARRAY is array(natural range <>) of T_INT4;
type T_INT5_ARRAY is array(natural range <>) of T_INT5;
type T_INT6_ARRAY is array(natural range <>) of T_INT6;
type T_INT7_ARRAY is array(natural range <>) of T_INT7;
type T_INT9_ARRAY is array(natural range <>) of T_INT9;
type T_INT10_ARRAY is array(natural range <>) of T_INT10;
type T_INT11_ARRAY is array(natural range <>) of T_INT11;
type T_INT12_ARRAY is array(natural range <>) of T_INT12;
type T_INT13_ARRAY is array(natural range <>) of T_INT13;
type T_INT14_ARRAY is array(natural range <>) of T_INT14;
type T_INT15_ARRAY is array(natural range <>) of T_INT15;
type T_INT17_ARRAY is array(natural range <>) of T_INT17;
type T_INT18_ARRAY is array(natural range <>) of T_INT18;
type T_INT19_ARRAY is array(natural range <>) of T_INT19;
type T_INT20_ARRAY is array(natural range <>) of T_INT20;
type T_INT21_ARRAY is array(natural range <>) of T_INT21;
type T_INT22_ARRAY is array(natural range <>) of T_INT22;
type T_INT23_ARRAY is array(natural range <>) of T_INT23;
type T_INT24_ARRAY is array(natural range <>) of T_INT24;
type T_INT25_ARRAY is array(natural range <>) of T_INT25;
type T_INT26_ARRAY is array(natural range <>) of T_INT26;
type T_INT27_ARRAY is array(natural range <>) of T_INT27;
type T_INT28_ARRAY is array(natural range <>) of T_INT28;
type T_INT29_ARRAY is array(natural range <>) of T_INT29;
type T_INT30_ARRAY is array(natural range <>) of T_INT30;
type T_INT31_ARRAY is array(natural range <>) of T_INT31;
type T_INT33_ARRAY is array(natural range <>) of T_INT33;
type T_INT34_ARRAY is array(natural range <>) of T_INT34;
type T_INT35_ARRAY is array(natural range <>) of T_INT35;
type T_INT36_ARRAY is array(natural range <>) of T_INT36;
type T_INT37_ARRAY is array(natural range <>) of T_INT37;
type T_INT38_ARRAY is array(natural range <>) of T_INT38;
type T_INT39_ARRAY is array(natural range <>) of T_INT39;
type T_INT40_ARRAY is array(natural range <>) of T_INT40;
type T_INT41_ARRAY is array(natural range <>) of T_INT41;
type T_INT42_ARRAY is array(natural range <>) of T_INT42;
type T_INT43_ARRAY is array(natural range <>) of T_INT43;
type T_INT44_ARRAY is array(natural range <>) of T_INT44;
type T_INT45_ARRAY is array(natural range <>) of T_INT45;
type T_INT46_ARRAY is array(natural range <>) of T_INT46;
type T_INT47_ARRAY is array(natural range <>) of T_INT47;
type T_INT48_ARRAY is array(natural range <>) of T_INT48;
type T_INT49_ARRAY is array(natural range <>) of T_INT49;
type T_INT50_ARRAY is array(natural range <>) of T_INT50;
type T_INT51_ARRAY is array(natural range <>) of T_INT51;
type T_INT52_ARRAY is array(natural range <>) of T_INT52;
type T_INT53_ARRAY is array(natural range <>) of T_INT53;
type T_INT54_ARRAY is array(natural range <>) of T_INT54;
type T_INT55_ARRAY is array(natural range <>) of T_INT55;
type T_INT56_ARRAY is array(natural range <>) of T_INT56;
type T_INT57_ARRAY is array(natural range <>) of T_INT57;
type T_INT58_ARRAY is array(natural range <>) of T_INT58;
type T_INT59_ARRAY is array(natural range <>) of T_INT59;
type T_INT60_ARRAY is array(natural range <>) of T_INT60;
type T_INT61_ARRAY is array(natural range <>) of T_INT61;
type T_INT62_ARRAY is array(natural range <>) of T_INT62;
type T_INT63_ARRAY is array(natural range <>) of T_INT63;
-- converts an integer to UINT1
pure function UINT1(v: integer) return T_UINT1;
-- converts a std_logic_vector to UINT1
pure function UINT1(v: std_logic_vector) return T_UINT1;
-- converts an integer to UINT2
pure function UINT2(v: integer) return T_UINT2;
-- converts a std_logic_vector to UINT2
pure function UINT2(v: std_logic_vector) return T_UINT2;
-- converts an integer to UINT3
pure function UINT3(v: integer) return T_UINT3;
-- converts a std_logic_vector to UINT3
pure function UINT3(v: std_logic_vector) return T_UINT3;
-- converts an integer to UINT4
pure function UINT4(v: integer) return T_UINT4;
-- converts a std_logic_vector to UINT4
pure function UINT4(v: std_logic_vector) return T_UINT4;
-- converts an integer to UINT5
pure function UINT5(v: integer) return T_UINT5;
-- converts a std_logic_vector to UINT5
pure function UINT5(v: std_logic_vector) return T_UINT5;
-- converts an integer to UINT6
pure function UINT6(v: integer) return T_UINT6;
-- converts a std_logic_vector to UINT6
pure function UINT6(v: std_logic_vector) return T_UINT6;
-- converts an integer to UINT7
pure function UINT7(v: integer) return T_UINT7;
-- converts a std_logic_vector to UINT7
pure function UINT7(v: std_logic_vector) return T_UINT7;
-- converts an integer to UINT9
pure function UINT9(v: integer) return T_UINT9;
-- converts a std_logic_vector to UINT9
pure function UINT9(v: std_logic_vector) return T_UINT9;
-- converts an integer to UINT10
pure function UINT10(v: integer) return T_UINT10;
-- converts a std_logic_vector to UINT10
pure function UINT10(v: std_logic_vector) return T_UINT10;
-- converts an integer to UINT11
pure function UINT11(v: integer) return T_UINT11;
-- converts a std_logic_vector to UINT11
pure function UINT11(v: std_logic_vector) return T_UINT11;
-- converts an integer to UINT12
pure function UINT12(v: integer) return T_UINT12;
-- converts a std_logic_vector to UINT12
pure function UINT12(v: std_logic_vector) return T_UINT12;
-- converts an integer to UINT13
pure function UINT13(v: integer) return T_UINT13;
-- converts a std_logic_vector to UINT13
pure function UINT13(v: std_logic_vector) return T_UINT13;
-- converts an integer to UINT14
pure function UINT14(v: integer) return T_UINT14;
-- converts a std_logic_vector to UINT14
pure function UINT14(v: std_logic_vector) return T_UINT14;
-- converts an integer to UINT15
pure function UINT15(v: integer) return T_UINT15;
-- converts a std_logic_vector to UINT15
pure function UINT15(v: std_logic_vector) return T_UINT15;
-- converts an integer to UINT17
pure function UINT17(v: integer) return T_UINT17;
-- converts a std_logic_vector to UINT17
pure function UINT17(v: std_logic_vector) return T_UINT17;
-- converts an integer to UINT18
pure function UINT18(v: integer) return T_UINT18;
-- converts a std_logic_vector to UINT18
pure function UINT18(v: std_logic_vector) return T_UINT18;
-- converts an integer to UINT19
pure function UINT19(v: integer) return T_UINT19;
-- converts a std_logic_vector to UINT19
pure function UINT19(v: std_logic_vector) return T_UINT19;
-- converts an integer to UINT20
pure function UINT20(v: integer) return T_UINT20;
-- converts a std_logic_vector to UINT20
pure function UINT20(v: std_logic_vector) return T_UINT20;
-- converts an integer to UINT21
pure function UINT21(v: integer) return T_UINT21;
-- converts a std_logic_vector to UINT21
pure function UINT21(v: std_logic_vector) return T_UINT21;
-- converts an integer to UINT22
pure function UINT22(v: integer) return T_UINT22;
-- converts a std_logic_vector to UINT22
pure function UINT22(v: std_logic_vector) return T_UINT22;
-- converts an integer to UINT23
pure function UINT23(v: integer) return T_UINT23;
-- converts a std_logic_vector to UINT23
pure function UINT23(v: std_logic_vector) return T_UINT23;
-- converts an integer to UINT24
pure function UINT24(v: integer) return T_UINT24;
-- converts a std_logic_vector to UINT24
pure function UINT24(v: std_logic_vector) return T_UINT24;
-- converts an integer to UINT25
pure function UINT25(v: integer) return T_UINT25;
-- converts a std_logic_vector to UINT25
pure function UINT25(v: std_logic_vector) return T_UINT25;
-- converts an integer to UINT26
pure function UINT26(v: integer) return T_UINT26;
-- converts a std_logic_vector to UINT26
pure function UINT26(v: std_logic_vector) return T_UINT26;
-- converts an integer to UINT27
pure function UINT27(v: integer) return T_UINT27;
-- converts a std_logic_vector to UINT27
pure function UINT27(v: std_logic_vector) return T_UINT27;
-- converts an integer to UINT28
pure function UINT28(v: integer) return T_UINT28;
-- converts a std_logic_vector to UINT28
pure function UINT28(v: std_logic_vector) return T_UINT28;
-- converts an integer to UINT29
pure function UINT29(v: integer) return T_UINT29;
-- converts a std_logic_vector to UINT29
pure function UINT29(v: std_logic_vector) return T_UINT29;
-- converts an integer to UINT30
pure function UINT30(v: integer) return T_UINT30;
-- converts a std_logic_vector to UINT30
pure function UINT30(v: std_logic_vector) return T_UINT30;
-- converts an integer to UINT31
pure function UINT31(v: integer) return T_UINT31;
-- converts a std_logic_vector to UINT31
pure function UINT31(v: std_logic_vector) return T_UINT31;
-- converts an integer to UINT33
pure function UINT33(v: integer) return T_UINT33;
-- converts a std_logic_vector to UINT33
pure function UINT33(v: std_logic_vector) return T_UINT33;
-- converts an integer to UINT34
pure function UINT34(v: integer) return T_UINT34;
-- converts a std_logic_vector to UINT34
pure function UINT34(v: std_logic_vector) return T_UINT34;
-- converts an integer to UINT35
pure function UINT35(v: integer) return T_UINT35;
-- converts a std_logic_vector to UINT35
pure function UINT35(v: std_logic_vector) return T_UINT35;
-- converts an integer to UINT36
pure function UINT36(v: integer) return T_UINT36;
-- converts a std_logic_vector to UINT36
pure function UINT36(v: std_logic_vector) return T_UINT36;
-- converts an integer to UINT37
pure function UINT37(v: integer) return T_UINT37;
-- converts a std_logic_vector to UINT37
pure function UINT37(v: std_logic_vector) return T_UINT37;
-- converts an integer to UINT38
pure function UINT38(v: integer) return T_UINT38;
-- converts a std_logic_vector to UINT38
pure function UINT38(v: std_logic_vector) return T_UINT38;
-- converts an integer to UINT39
pure function UINT39(v: integer) return T_UINT39;
-- converts a std_logic_vector to UINT39
pure function UINT39(v: std_logic_vector) return T_UINT39;
-- converts an integer to UINT40
pure function UINT40(v: integer) return T_UINT40;
-- converts a std_logic_vector to UINT40
pure function UINT40(v: std_logic_vector) return T_UINT40;
-- converts an integer to UINT41
pure function UINT41(v: integer) return T_UINT41;
-- converts a std_logic_vector to UINT41
pure function UINT41(v: std_logic_vector) return T_UINT41;
-- converts an integer to UINT42
pure function UINT42(v: integer) return T_UINT42;
-- converts a std_logic_vector to UINT42
pure function UINT42(v: std_logic_vector) return T_UINT42;
-- converts an integer to UINT43
pure function UINT43(v: integer) return T_UINT43;
-- converts a std_logic_vector to UINT43
pure function UINT43(v: std_logic_vector) return T_UINT43;
-- converts an integer to UINT44
pure function UINT44(v: integer) return T_UINT44;
-- converts a std_logic_vector to UINT44
pure function UINT44(v: std_logic_vector) return T_UINT44;
-- converts an integer to UINT45
pure function UINT45(v: integer) return T_UINT45;
-- converts a std_logic_vector to UINT45
pure function UINT45(v: std_logic_vector) return T_UINT45;
-- converts an integer to UINT46
pure function UINT46(v: integer) return T_UINT46;
-- converts a std_logic_vector to UINT46
pure function UINT46(v: std_logic_vector) return T_UINT46;
-- converts an integer to UINT47
pure function UINT47(v: integer) return T_UINT47;
-- converts a std_logic_vector to UINT47
pure function UINT47(v: std_logic_vector) return T_UINT47;
-- converts an integer to UINT48
pure function UINT48(v: integer) return T_UINT48;
-- converts a std_logic_vector to UINT48
pure function UINT48(v: std_logic_vector) return T_UINT48;
-- converts an integer to UINT49
pure function UINT49(v: integer) return T_UINT49;
-- converts a std_logic_vector to UINT49
pure function UINT49(v: std_logic_vector) return T_UINT49;
-- converts an integer to UINT50
pure function UINT50(v: integer) return T_UINT50;
-- converts a std_logic_vector to UINT50
pure function UINT50(v: std_logic_vector) return T_UINT50;
-- converts an integer to UINT51
pure function UINT51(v: integer) return T_UINT51;
-- converts a std_logic_vector to UINT51
pure function UINT51(v: std_logic_vector) return T_UINT51;
-- converts an integer to UINT52
pure function UINT52(v: integer) return T_UINT52;
-- converts a std_logic_vector to UINT52
pure function UINT52(v: std_logic_vector) return T_UINT52;
-- converts an integer to UINT53
pure function UINT53(v: integer) return T_UINT53;
-- converts a std_logic_vector to UINT53
pure function UINT53(v: std_logic_vector) return T_UINT53;
-- converts an integer to UINT54
pure function UINT54(v: integer) return T_UINT54;
-- converts a std_logic_vector to UINT54
pure function UINT54(v: std_logic_vector) return T_UINT54;
-- converts an integer to UINT55
pure function UINT55(v: integer) return T_UINT55;
-- converts a std_logic_vector to UINT55
pure function UINT55(v: std_logic_vector) return T_UINT55;
-- converts an integer to UINT56
pure function UINT56(v: integer) return T_UINT56;
-- converts a std_logic_vector to UINT56
pure function UINT56(v: std_logic_vector) return T_UINT56;
-- converts an integer to UINT57
pure function UINT57(v: integer) return T_UINT57;
-- converts a std_logic_vector to UINT57
pure function UINT57(v: std_logic_vector) return T_UINT57;
-- converts an integer to UINT58
pure function UINT58(v: integer) return T_UINT58;
-- converts a std_logic_vector to UINT58
pure function UINT58(v: std_logic_vector) return T_UINT58;
-- converts an integer to UINT59
pure function UINT59(v: integer) return T_UINT59;
-- converts a std_logic_vector to UINT59
pure function UINT59(v: std_logic_vector) return T_UINT59;
-- converts an integer to UINT60
pure function UINT60(v: integer) return T_UINT60;
-- converts a std_logic_vector to UINT60
pure function UINT60(v: std_logic_vector) return T_UINT60;
-- converts an integer to UINT61
pure function UINT61(v: integer) return T_UINT61;
-- converts a std_logic_vector to UINT61
pure function UINT61(v: std_logic_vector) return T_UINT61;
-- converts an integer to UINT62
pure function UINT62(v: integer) return T_UINT62;
-- converts a std_logic_vector to UINT62
pure function UINT62(v: std_logic_vector) return T_UINT62;
-- converts an integer to UINT63
pure function UINT63(v: integer) return T_UINT63;
-- converts a std_logic_vector to UINT63
pure function UINT63(v: std_logic_vector) return T_UINT63;
-- converts an integer to INT1
pure function INT1(v: integer) return T_INT1;
-- converts a std_logic_vector to INT1
pure function INT1(v: std_logic_vector) return T_INT1;
-- converts an integer to INT2
pure function INT2(v: integer) return T_INT2;
-- converts a std_logic_vector to INT2
pure function INT2(v: std_logic_vector) return T_INT2;
-- converts an integer to INT3
pure function INT3(v: integer) return T_INT3;
-- converts a std_logic_vector to INT3
pure function INT3(v: std_logic_vector) return T_INT3;
-- converts an integer to INT4
pure function INT4(v: integer) return T_INT4;
-- converts a std_logic_vector to INT4
pure function INT4(v: std_logic_vector) return T_INT4;
-- converts an integer to INT5
pure function INT5(v: integer) return T_INT5;
-- converts a std_logic_vector to INT5
pure function INT5(v: std_logic_vector) return T_INT5;
-- converts an integer to INT6
pure function INT6(v: integer) return T_INT6;
-- converts a std_logic_vector to INT6
pure function INT6(v: std_logic_vector) return T_INT6;
-- converts an integer to INT7
pure function INT7(v: integer) return T_INT7;
-- converts a std_logic_vector to INT7
pure function INT7(v: std_logic_vector) return T_INT7;
-- converts an integer to INT9
pure function INT9(v: integer) return T_INT9;
-- converts a std_logic_vector to INT9
pure function INT9(v: std_logic_vector) return T_INT9;
-- converts an integer to INT10
pure function INT10(v: integer) return T_INT10;
-- converts a std_logic_vector to INT10
pure function INT10(v: std_logic_vector) return T_INT10;
-- converts an integer to INT11
pure function INT11(v: integer) return T_INT11;
-- converts a std_logic_vector to INT11
pure function INT11(v: std_logic_vector) return T_INT11;
-- converts an integer to INT12
pure function INT12(v: integer) return T_INT12;
-- converts a std_logic_vector to INT12
pure function INT12(v: std_logic_vector) return T_INT12;
-- converts an integer to INT13
pure function INT13(v: integer) return T_INT13;
-- converts a std_logic_vector to INT13
pure function INT13(v: std_logic_vector) return T_INT13;
-- converts an integer to INT14
pure function INT14(v: integer) return T_INT14;
-- converts a std_logic_vector to INT14
pure function INT14(v: std_logic_vector) return T_INT14;
-- converts an integer to INT15
pure function INT15(v: integer) return T_INT15;
-- converts a std_logic_vector to INT15
pure function INT15(v: std_logic_vector) return T_INT15;
-- converts an integer to INT17
pure function INT17(v: integer) return T_INT17;
-- converts a std_logic_vector to INT17
pure function INT17(v: std_logic_vector) return T_INT17;
-- converts an integer to INT18
pure function INT18(v: integer) return T_INT18;
-- converts a std_logic_vector to INT18
pure function INT18(v: std_logic_vector) return T_INT18;
-- converts an integer to INT19
pure function INT19(v: integer) return T_INT19;
-- converts a std_logic_vector to INT19
pure function INT19(v: std_logic_vector) return T_INT19;
-- converts an integer to INT20
pure function INT20(v: integer) return T_INT20;
-- converts a std_logic_vector to INT20
pure function INT20(v: std_logic_vector) return T_INT20;
-- converts an integer to INT21
pure function INT21(v: integer) return T_INT21;
-- converts a std_logic_vector to INT21
pure function INT21(v: std_logic_vector) return T_INT21;
-- converts an integer to INT22
pure function INT22(v: integer) return T_INT22;
-- converts a std_logic_vector to INT22
pure function INT22(v: std_logic_vector) return T_INT22;
-- converts an integer to INT23
pure function INT23(v: integer) return T_INT23;
-- converts a std_logic_vector to INT23
pure function INT23(v: std_logic_vector) return T_INT23;
-- converts an integer to INT24
pure function INT24(v: integer) return T_INT24;
-- converts a std_logic_vector to INT24
pure function INT24(v: std_logic_vector) return T_INT24;
-- converts an integer to INT25
pure function INT25(v: integer) return T_INT25;
-- converts a std_logic_vector to INT25
pure function INT25(v: std_logic_vector) return T_INT25;
-- converts an integer to INT26
pure function INT26(v: integer) return T_INT26;
-- converts a std_logic_vector to INT26
pure function INT26(v: std_logic_vector) return T_INT26;
-- converts an integer to INT27
pure function INT27(v: integer) return T_INT27;
-- converts a std_logic_vector to INT27
pure function INT27(v: std_logic_vector) return T_INT27;
-- converts an integer to INT28
pure function INT28(v: integer) return T_INT28;
-- converts a std_logic_vector to INT28
pure function INT28(v: std_logic_vector) return T_INT28;
-- converts an integer to INT29
pure function INT29(v: integer) return T_INT29;
-- converts a std_logic_vector to INT29
pure function INT29(v: std_logic_vector) return T_INT29;
-- converts an integer to INT30
pure function INT30(v: integer) return T_INT30;
-- converts a std_logic_vector to INT30
pure function INT30(v: std_logic_vector) return T_INT30;
-- converts an integer to INT31
pure function INT31(v: integer) return T_INT31;
-- converts a std_logic_vector to INT31
pure function INT31(v: std_logic_vector) return T_INT31;
-- converts an integer to INT33
pure function INT33(v: integer) return T_INT33;
-- converts a std_logic_vector to INT33
pure function INT33(v: std_logic_vector) return T_INT33;
-- converts an integer to INT34
pure function INT34(v: integer) return T_INT34;
-- converts a std_logic_vector to INT34
pure function INT34(v: std_logic_vector) return T_INT34;
-- converts an integer to INT35
pure function INT35(v: integer) return T_INT35;
-- converts a std_logic_vector to INT35
pure function INT35(v: std_logic_vector) return T_INT35;
-- converts an integer to INT36
pure function INT36(v: integer) return T_INT36;
-- converts a std_logic_vector to INT36
pure function INT36(v: std_logic_vector) return T_INT36;
-- converts an integer to INT37
pure function INT37(v: integer) return T_INT37;
-- converts a std_logic_vector to INT37
pure function INT37(v: std_logic_vector) return T_INT37;
-- converts an integer to INT38
pure function INT38(v: integer) return T_INT38;
-- converts a std_logic_vector to INT38
pure function INT38(v: std_logic_vector) return T_INT38;
-- converts an integer to INT39
pure function INT39(v: integer) return T_INT39;
-- converts a std_logic_vector to INT39
pure function INT39(v: std_logic_vector) return T_INT39;
-- converts an integer to INT40
pure function INT40(v: integer) return T_INT40;
-- converts a std_logic_vector to INT40
pure function INT40(v: std_logic_vector) return T_INT40;
-- converts an integer to INT41
pure function INT41(v: integer) return T_INT41;
-- converts a std_logic_vector to INT41
pure function INT41(v: std_logic_vector) return T_INT41;
-- converts an integer to INT42
pure function INT42(v: integer) return T_INT42;
-- converts a std_logic_vector to INT42
pure function INT42(v: std_logic_vector) return T_INT42;
-- converts an integer to INT43
pure function INT43(v: integer) return T_INT43;
-- converts a std_logic_vector to INT43
pure function INT43(v: std_logic_vector) return T_INT43;
-- converts an integer to INT44
pure function INT44(v: integer) return T_INT44;
-- converts a std_logic_vector to INT44
pure function INT44(v: std_logic_vector) return T_INT44;
-- converts an integer to INT45
pure function INT45(v: integer) return T_INT45;
-- converts a std_logic_vector to INT45
pure function INT45(v: std_logic_vector) return T_INT45;
-- converts an integer to INT46
pure function INT46(v: integer) return T_INT46;
-- converts a std_logic_vector to INT46
pure function INT46(v: std_logic_vector) return T_INT46;
-- converts an integer to INT47
pure function INT47(v: integer) return T_INT47;
-- converts a std_logic_vector to INT47
pure function INT47(v: std_logic_vector) return T_INT47;
-- converts an integer to INT48
pure function INT48(v: integer) return T_INT48;
-- converts a std_logic_vector to INT48
pure function INT48(v: std_logic_vector) return T_INT48;
-- converts an integer to INT49
pure function INT49(v: integer) return T_INT49;
-- converts a std_logic_vector to INT49
pure function INT49(v: std_logic_vector) return T_INT49;
-- converts an integer to INT50
pure function INT50(v: integer) return T_INT50;
-- converts a std_logic_vector to INT50
pure function INT50(v: std_logic_vector) return T_INT50;
-- converts an integer to INT51
pure function INT51(v: integer) return T_INT51;
-- converts a std_logic_vector to INT51
pure function INT51(v: std_logic_vector) return T_INT51;
-- converts an integer to INT52
pure function INT52(v: integer) return T_INT52;
-- converts a std_logic_vector to INT52
pure function INT52(v: std_logic_vector) return T_INT52;
-- converts an integer to INT53
pure function INT53(v: integer) return T_INT53;
-- converts a std_logic_vector to INT53
pure function INT53(v: std_logic_vector) return T_INT53;
-- converts an integer to INT54
pure function INT54(v: integer) return T_INT54;
-- converts a std_logic_vector to INT54
pure function INT54(v: std_logic_vector) return T_INT54;
-- converts an integer to INT55
pure function INT55(v: integer) return T_INT55;
-- converts a std_logic_vector to INT55
pure function INT55(v: std_logic_vector) return T_INT55;
-- converts an integer to INT56
pure function INT56(v: integer) return T_INT56;
-- converts a std_logic_vector to INT56
pure function INT56(v: std_logic_vector) return T_INT56;
-- converts an integer to INT57
pure function INT57(v: integer) return T_INT57;
-- converts a std_logic_vector to INT57
pure function INT57(v: std_logic_vector) return T_INT57;
-- converts an integer to INT58
pure function INT58(v: integer) return T_INT58;
-- converts a std_logic_vector to INT58
pure function INT58(v: std_logic_vector) return T_INT58;
-- converts an integer to INT59
pure function INT59(v: integer) return T_INT59;
-- converts a std_logic_vector to INT59
pure function INT59(v: std_logic_vector) return T_INT59;
-- converts an integer to INT60
pure function INT60(v: integer) return T_INT60;
-- converts a std_logic_vector to INT60
pure function INT60(v: std_logic_vector) return T_INT60;
-- converts an integer to INT61
pure function INT61(v: integer) return T_INT61;
-- converts a std_logic_vector to INT61
pure function INT61(v: std_logic_vector) return T_INT61;
-- converts an integer to INT62
pure function INT62(v: integer) return T_INT62;
-- converts a std_logic_vector to INT62
pure function INT62(v: std_logic_vector) return T_INT62;
-- converts an integer to INT63
pure function INT63(v: integer) return T_INT63;
-- converts a std_logic_vector to INT63
pure function INT63(v: std_logic_vector) return T_INT63;
-- converts an integer to SYSTEM_UINT8
pure function SYSTEM_UINT8(v: integer) return T_SYSTEM_UINT8;
-- converts a std_logic_vector to SYSTEM_UINT8
pure function SYSTEM_UINT8(v: std_logic_vector) return T_SYSTEM_UINT8;
-- converts an integer to SYSTEM_UINT16
pure function SYSTEM_UINT16(v: integer) return T_SYSTEM_UINT16;
-- converts a std_logic_vector to SYSTEM_UINT16
pure function SYSTEM_UINT16(v: std_logic_vector) return T_SYSTEM_UINT16;
-- converts an integer to SYSTEM_UINT32
pure function SYSTEM_UINT32(v: integer) return T_SYSTEM_UINT32;
-- converts a std_logic_vector to SYSTEM_UINT32
pure function SYSTEM_UINT32(v: std_logic_vector) return T_SYSTEM_UINT32;
-- converts an integer to SYSTEM_UINT64
pure function SYSTEM_UINT64(v: integer) return T_SYSTEM_UINT64;
-- converts a std_logic_vector to SYSTEM_UINT64
pure function SYSTEM_UINT64(v: std_logic_vector) return T_SYSTEM_UINT64;
-- converts an integer to SYSTEM_INT8
pure function SYSTEM_INT8(v: integer) return T_SYSTEM_INT8;
-- converts a std_logic_vector to SYSTEM_UINT8
pure function SYSTEM_INT8(v: std_logic_vector) return T_SYSTEM_INT8;
-- converts an integer to SYSTEM_INT16
pure function SYSTEM_INT16(v: integer) return T_SYSTEM_INT16;
-- converts a std_logic_vector to SYSTEM_UINT16
pure function SYSTEM_INT16(v: std_logic_vector) return T_SYSTEM_INT16;
-- converts an integer to SYSTEM_INT32
pure function SYSTEM_INT32(v: integer) return T_SYSTEM_INT32;
-- converts a std_logic_vector to SYSTEM_UINT32
pure function SYSTEM_INT32(v: std_logic_vector) return T_SYSTEM_INT32;
-- converts an integer to SYSTEM_INT64
pure function SYSTEM_INT64(v: integer) return T_SYSTEM_INT64;
-- converts a std_logic_vector to SYSTEM_UINT64
pure function SYSTEM_INT64(v: std_logic_vector) return T_SYSTEM_INT64;
end SYSTEM_TYPES;
package body SYSTEM_TYPES is
pure function clog2 (A : NATURAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if A = 1 or A = 0 then -- trivial rejection and acceptance
return A;
end if;
Y := real(A);
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
if Y > 0.0 then
N := N + 1; -- round up to the nearest log2
end if;
return N;
end function clog2;
-- converts an integer to UINT1
pure function UINT1(v: integer) return T_UINT1 is
begin
return TO_UNSIGNED(v, T_UINT1'length);
end UINT1;
-- converts a std_logic_vector to UINT1
pure function UINT1(v: std_logic_vector) return T_UINT1 is
begin
return RESIZE(UNSIGNED(v), T_UINT1'length);
end UINT1;
-- converts an integer to UINT2
pure function UINT2(v: integer) return T_UINT2 is
begin
return TO_UNSIGNED(v, T_UINT2'length);
end UINT2;
-- converts a std_logic_vector to UINT2
pure function UINT2(v: std_logic_vector) return T_UINT2 is
begin
return RESIZE(UNSIGNED(v), T_UINT2'length);
end UINT2;
-- converts an integer to UINT3
pure function UINT3(v: integer) return T_UINT3 is
begin
return TO_UNSIGNED(v, T_UINT3'length);
end UINT3;
-- converts a std_logic_vector to UINT3
pure function UINT3(v: std_logic_vector) return T_UINT3 is
begin
return RESIZE(UNSIGNED(v), T_UINT3'length);
end UINT3;
-- converts an integer to UINT4
pure function UINT4(v: integer) return T_UINT4 is
begin
return TO_UNSIGNED(v, T_UINT4'length);
end UINT4;
-- converts a std_logic_vector to UINT4
pure function UINT4(v: std_logic_vector) return T_UINT4 is
begin
return RESIZE(UNSIGNED(v), T_UINT4'length);
end UINT4;
-- converts an integer to UINT5
pure function UINT5(v: integer) return T_UINT5 is
begin
return TO_UNSIGNED(v, T_UINT5'length);
end UINT5;
-- converts a std_logic_vector to UINT5
pure function UINT5(v: std_logic_vector) return T_UINT5 is
begin
return RESIZE(UNSIGNED(v), T_UINT5'length);
end UINT5;
-- converts an integer to UINT6
pure function UINT6(v: integer) return T_UINT6 is
begin
return TO_UNSIGNED(v, T_UINT6'length);
end UINT6;
-- converts a std_logic_vector to UINT6
pure function UINT6(v: std_logic_vector) return T_UINT6 is
begin
return RESIZE(UNSIGNED(v), T_UINT6'length);
end UINT6;
-- converts an integer to UINT7
pure function UINT7(v: integer) return T_UINT7 is
begin
return TO_UNSIGNED(v, T_UINT7'length);
end UINT7;
-- converts a std_logic_vector to UINT7
pure function UINT7(v: std_logic_vector) return T_UINT7 is
begin
return RESIZE(UNSIGNED(v), T_UINT7'length);
end UINT7;
-- converts an integer to UINT9
pure function UINT9(v: integer) return T_UINT9 is
begin
return TO_UNSIGNED(v, T_UINT9'length);
end UINT9;
-- converts a std_logic_vector to UINT9
pure function UINT9(v: std_logic_vector) return T_UINT9 is
begin
return RESIZE(UNSIGNED(v), T_UINT9'length);
end UINT9;
-- converts an integer to UINT10
pure function UINT10(v: integer) return T_UINT10 is
begin
return TO_UNSIGNED(v, T_UINT10'length);
end UINT10;
-- converts a std_logic_vector to UINT10
pure function UINT10(v: std_logic_vector) return T_UINT10 is
begin
return RESIZE(UNSIGNED(v), T_UINT10'length);
end UINT10;
-- converts an integer to UINT11
pure function UINT11(v: integer) return T_UINT11 is
begin
return TO_UNSIGNED(v, T_UINT11'length);
end UINT11;
-- converts a std_logic_vector to UINT11
pure function UINT11(v: std_logic_vector) return T_UINT11 is
begin
return RESIZE(UNSIGNED(v), T_UINT11'length);
end UINT11;
-- converts an integer to UINT12
pure function UINT12(v: integer) return T_UINT12 is
begin
return TO_UNSIGNED(v, T_UINT12'length);
end UINT12;
-- converts a std_logic_vector to UINT12
pure function UINT12(v: std_logic_vector) return T_UINT12 is
begin
return RESIZE(UNSIGNED(v), T_UINT12'length);
end UINT12;
-- converts an integer to UINT13
pure function UINT13(v: integer) return T_UINT13 is
begin
return TO_UNSIGNED(v, T_UINT13'length);
end UINT13;
-- converts a std_logic_vector to UINT13
pure function UINT13(v: std_logic_vector) return T_UINT13 is
begin
return RESIZE(UNSIGNED(v), T_UINT13'length);
end UINT13;
-- converts an integer to UINT14
pure function UINT14(v: integer) return T_UINT14 is
begin
return TO_UNSIGNED(v, T_UINT14'length);
end UINT14;
-- converts a std_logic_vector to UINT14
pure function UINT14(v: std_logic_vector) return T_UINT14 is
begin
return RESIZE(UNSIGNED(v), T_UINT14'length);
end UINT14;
-- converts an integer to UINT15
pure function UINT15(v: integer) return T_UINT15 is
begin
return TO_UNSIGNED(v, T_UINT15'length);
end UINT15;
-- converts a std_logic_vector to UINT15
pure function UINT15(v: std_logic_vector) return T_UINT15 is
begin
return RESIZE(UNSIGNED(v), T_UINT15'length);
end UINT15;
-- converts an integer to UINT17
pure function UINT17(v: integer) return T_UINT17 is
begin
return TO_UNSIGNED(v, T_UINT17'length);
end UINT17;
-- converts a std_logic_vector to UINT17
pure function UINT17(v: std_logic_vector) return T_UINT17 is
begin
return RESIZE(UNSIGNED(v), T_UINT17'length);
end UINT17;
-- converts an integer to UINT18
pure function UINT18(v: integer) return T_UINT18 is
begin
return TO_UNSIGNED(v, T_UINT18'length);
end UINT18;
-- converts a std_logic_vector to UINT18
pure function UINT18(v: std_logic_vector) return T_UINT18 is
begin
return RESIZE(UNSIGNED(v), T_UINT18'length);
end UINT18;
-- converts an integer to UINT19
pure function UINT19(v: integer) return T_UINT19 is
begin
return TO_UNSIGNED(v, T_UINT19'length);
end UINT19;
-- converts a std_logic_vector to UINT19
pure function UINT19(v: std_logic_vector) return T_UINT19 is
begin
return RESIZE(UNSIGNED(v), T_UINT19'length);
end UINT19;
-- converts an integer to UINT20
pure function UINT20(v: integer) return T_UINT20 is
begin
return TO_UNSIGNED(v, T_UINT20'length);
end UINT20;
-- converts a std_logic_vector to UINT20
pure function UINT20(v: std_logic_vector) return T_UINT20 is
begin
return RESIZE(UNSIGNED(v), T_UINT20'length);
end UINT20;
-- converts an integer to UINT21
pure function UINT21(v: integer) return T_UINT21 is
begin
return TO_UNSIGNED(v, T_UINT21'length);
end UINT21;
-- converts a std_logic_vector to UINT21
pure function UINT21(v: std_logic_vector) return T_UINT21 is
begin
return RESIZE(UNSIGNED(v), T_UINT21'length);
end UINT21;
-- converts an integer to UINT22
pure function UINT22(v: integer) return T_UINT22 is
begin
return TO_UNSIGNED(v, T_UINT22'length);
end UINT22;
-- converts a std_logic_vector to UINT22
pure function UINT22(v: std_logic_vector) return T_UINT22 is
begin
return RESIZE(UNSIGNED(v), T_UINT22'length);
end UINT22;
-- converts an integer to UINT23
pure function UINT23(v: integer) return T_UINT23 is
begin
return TO_UNSIGNED(v, T_UINT23'length);
end UINT23;
-- converts a std_logic_vector to UINT23
pure function UINT23(v: std_logic_vector) return T_UINT23 is
begin
return RESIZE(UNSIGNED(v), T_UINT23'length);
end UINT23;
-- converts an integer to UINT24
pure function UINT24(v: integer) return T_UINT24 is
begin
return TO_UNSIGNED(v, T_UINT24'length);
end UINT24;
-- converts a std_logic_vector to UINT24
pure function UINT24(v: std_logic_vector) return T_UINT24 is
begin
return RESIZE(UNSIGNED(v), T_UINT24'length);
end UINT24;
-- converts an integer to UINT25
pure function UINT25(v: integer) return T_UINT25 is
begin
return TO_UNSIGNED(v, T_UINT25'length);
end UINT25;
-- converts a std_logic_vector to UINT25
pure function UINT25(v: std_logic_vector) return T_UINT25 is
begin
return RESIZE(UNSIGNED(v), T_UINT25'length);
end UINT25;
-- converts an integer to UINT26
pure function UINT26(v: integer) return T_UINT26 is
begin
return TO_UNSIGNED(v, T_UINT26'length);
end UINT26;
-- converts a std_logic_vector to UINT26
pure function UINT26(v: std_logic_vector) return T_UINT26 is
begin
return RESIZE(UNSIGNED(v), T_UINT26'length);
end UINT26;
-- converts an integer to UINT27
pure function UINT27(v: integer) return T_UINT27 is
begin
return TO_UNSIGNED(v, T_UINT27'length);
end UINT27;
-- converts a std_logic_vector to UINT27
pure function UINT27(v: std_logic_vector) return T_UINT27 is
begin
return RESIZE(UNSIGNED(v), T_UINT27'length);
end UINT27;
-- converts an integer to UINT28
pure function UINT28(v: integer) return T_UINT28 is
begin
return TO_UNSIGNED(v, T_UINT28'length);
end UINT28;
-- converts a std_logic_vector to UINT28
pure function UINT28(v: std_logic_vector) return T_UINT28 is
begin
return RESIZE(UNSIGNED(v), T_UINT28'length);
end UINT28;
-- converts an integer to UINT29
pure function UINT29(v: integer) return T_UINT29 is
begin
return TO_UNSIGNED(v, T_UINT29'length);
end UINT29;
-- converts a std_logic_vector to UINT29
pure function UINT29(v: std_logic_vector) return T_UINT29 is
begin
return RESIZE(UNSIGNED(v), T_UINT29'length);
end UINT29;
-- converts an integer to UINT30
pure function UINT30(v: integer) return T_UINT30 is
begin
return TO_UNSIGNED(v, T_UINT30'length);
end UINT30;
-- converts a std_logic_vector to UINT30
pure function UINT30(v: std_logic_vector) return T_UINT30 is
begin
return RESIZE(UNSIGNED(v), T_UINT30'length);
end UINT30;
-- converts an integer to UINT31
pure function UINT31(v: integer) return T_UINT31 is
begin
return TO_UNSIGNED(v, T_UINT31'length);
end UINT31;
-- converts a std_logic_vector to UINT31
pure function UINT31(v: std_logic_vector) return T_UINT31 is
begin
return RESIZE(UNSIGNED(v), T_UINT31'length);
end UINT31;
-- converts an integer to UINT33
pure function UINT33(v: integer) return T_UINT33 is
begin
return TO_UNSIGNED(v, T_UINT33'length);
end UINT33;
-- converts a std_logic_vector to UINT33
pure function UINT33(v: std_logic_vector) return T_UINT33 is
begin
return RESIZE(UNSIGNED(v), T_UINT33'length);
end UINT33;
-- converts an integer to UINT34
pure function UINT34(v: integer) return T_UINT34 is
begin
return TO_UNSIGNED(v, T_UINT34'length);
end UINT34;
-- converts a std_logic_vector to UINT34
pure function UINT34(v: std_logic_vector) return T_UINT34 is
begin
return RESIZE(UNSIGNED(v), T_UINT34'length);
end UINT34;
-- converts an integer to UINT35
pure function UINT35(v: integer) return T_UINT35 is
begin
return TO_UNSIGNED(v, T_UINT35'length);
end UINT35;
-- converts a std_logic_vector to UINT35
pure function UINT35(v: std_logic_vector) return T_UINT35 is
begin
return RESIZE(UNSIGNED(v), T_UINT35'length);
end UINT35;
-- converts an integer to UINT36
pure function UINT36(v: integer) return T_UINT36 is
begin
return TO_UNSIGNED(v, T_UINT36'length);
end UINT36;
-- converts a std_logic_vector to UINT36
pure function UINT36(v: std_logic_vector) return T_UINT36 is
begin
return RESIZE(UNSIGNED(v), T_UINT36'length);
end UINT36;
-- converts an integer to UINT37
pure function UINT37(v: integer) return T_UINT37 is
begin
return TO_UNSIGNED(v, T_UINT37'length);
end UINT37;
-- converts a std_logic_vector to UINT37
pure function UINT37(v: std_logic_vector) return T_UINT37 is
begin
return RESIZE(UNSIGNED(v), T_UINT37'length);
end UINT37;
-- converts an integer to UINT38
pure function UINT38(v: integer) return T_UINT38 is
begin
return TO_UNSIGNED(v, T_UINT38'length);
end UINT38;
-- converts a std_logic_vector to UINT38
pure function UINT38(v: std_logic_vector) return T_UINT38 is
begin
return RESIZE(UNSIGNED(v), T_UINT38'length);
end UINT38;
-- converts an integer to UINT39
pure function UINT39(v: integer) return T_UINT39 is
begin
return TO_UNSIGNED(v, T_UINT39'length);
end UINT39;
-- converts a std_logic_vector to UINT39
pure function UINT39(v: std_logic_vector) return T_UINT39 is
begin
return RESIZE(UNSIGNED(v), T_UINT39'length);
end UINT39;
-- converts an integer to UINT40
pure function UINT40(v: integer) return T_UINT40 is
begin
return TO_UNSIGNED(v, T_UINT40'length);
end UINT40;
-- converts a std_logic_vector to UINT40
pure function UINT40(v: std_logic_vector) return T_UINT40 is
begin
return RESIZE(UNSIGNED(v), T_UINT40'length);
end UINT40;
-- converts an integer to UINT41
pure function UINT41(v: integer) return T_UINT41 is
begin
return TO_UNSIGNED(v, T_UINT41'length);
end UINT41;
-- converts a std_logic_vector to UINT41
pure function UINT41(v: std_logic_vector) return T_UINT41 is
begin
return RESIZE(UNSIGNED(v), T_UINT41'length);
end UINT41;
-- converts an integer to UINT42
pure function UINT42(v: integer) return T_UINT42 is
begin
return TO_UNSIGNED(v, T_UINT42'length);
end UINT42;
-- converts a std_logic_vector to UINT42
pure function UINT42(v: std_logic_vector) return T_UINT42 is
begin
return RESIZE(UNSIGNED(v), T_UINT42'length);
end UINT42;
-- converts an integer to UINT43
pure function UINT43(v: integer) return T_UINT43 is
begin
return TO_UNSIGNED(v, T_UINT43'length);
end UINT43;
-- converts a std_logic_vector to UINT43
pure function UINT43(v: std_logic_vector) return T_UINT43 is
begin
return RESIZE(UNSIGNED(v), T_UINT43'length);
end UINT43;
-- converts an integer to UINT44
pure function UINT44(v: integer) return T_UINT44 is
begin
return TO_UNSIGNED(v, T_UINT44'length);
end UINT44;
-- converts a std_logic_vector to UINT44
pure function UINT44(v: std_logic_vector) return T_UINT44 is
begin
return RESIZE(UNSIGNED(v), T_UINT44'length);
end UINT44;
-- converts an integer to UINT45
pure function UINT45(v: integer) return T_UINT45 is
begin
return TO_UNSIGNED(v, T_UINT45'length);
end UINT45;
-- converts a std_logic_vector to UINT45
pure function UINT45(v: std_logic_vector) return T_UINT45 is
begin
return RESIZE(UNSIGNED(v), T_UINT45'length);
end UINT45;
-- converts an integer to UINT46
pure function UINT46(v: integer) return T_UINT46 is
begin
return TO_UNSIGNED(v, T_UINT46'length);
end UINT46;
-- converts a std_logic_vector to UINT46
pure function UINT46(v: std_logic_vector) return T_UINT46 is
begin
return RESIZE(UNSIGNED(v), T_UINT46'length);
end UINT46;
-- converts an integer to UINT47
pure function UINT47(v: integer) return T_UINT47 is
begin
return TO_UNSIGNED(v, T_UINT47'length);
end UINT47;
-- converts a std_logic_vector to UINT47
pure function UINT47(v: std_logic_vector) return T_UINT47 is
begin
return RESIZE(UNSIGNED(v), T_UINT47'length);
end UINT47;
-- converts an integer to UINT48
pure function UINT48(v: integer) return T_UINT48 is
begin
return TO_UNSIGNED(v, T_UINT48'length);
end UINT48;
-- converts a std_logic_vector to UINT48
pure function UINT48(v: std_logic_vector) return T_UINT48 is
begin
return RESIZE(UNSIGNED(v), T_UINT48'length);
end UINT48;
-- converts an integer to UINT49
pure function UINT49(v: integer) return T_UINT49 is
begin
return TO_UNSIGNED(v, T_UINT49'length);
end UINT49;
-- converts a std_logic_vector to UINT49
pure function UINT49(v: std_logic_vector) return T_UINT49 is
begin
return RESIZE(UNSIGNED(v), T_UINT49'length);
end UINT49;
-- converts an integer to UINT50
pure function UINT50(v: integer) return T_UINT50 is
begin
return TO_UNSIGNED(v, T_UINT50'length);
end UINT50;
-- converts a std_logic_vector to UINT50
pure function UINT50(v: std_logic_vector) return T_UINT50 is
begin
return RESIZE(UNSIGNED(v), T_UINT50'length);
end UINT50;
-- converts an integer to UINT51
pure function UINT51(v: integer) return T_UINT51 is
begin
return TO_UNSIGNED(v, T_UINT51'length);
end UINT51;
-- converts a std_logic_vector to UINT51
pure function UINT51(v: std_logic_vector) return T_UINT51 is
begin
return RESIZE(UNSIGNED(v), T_UINT51'length);
end UINT51;
-- converts an integer to UINT52
pure function UINT52(v: integer) return T_UINT52 is
begin
return TO_UNSIGNED(v, T_UINT52'length);
end UINT52;
-- converts a std_logic_vector to UINT52
pure function UINT52(v: std_logic_vector) return T_UINT52 is
begin
return RESIZE(UNSIGNED(v), T_UINT52'length);
end UINT52;
-- converts an integer to UINT53
pure function UINT53(v: integer) return T_UINT53 is
begin
return TO_UNSIGNED(v, T_UINT53'length);
end UINT53;
-- converts a std_logic_vector to UINT53
pure function UINT53(v: std_logic_vector) return T_UINT53 is
begin
return RESIZE(UNSIGNED(v), T_UINT53'length);
end UINT53;
-- converts an integer to UINT54
pure function UINT54(v: integer) return T_UINT54 is
begin
return TO_UNSIGNED(v, T_UINT54'length);
end UINT54;
-- converts a std_logic_vector to UINT54
pure function UINT54(v: std_logic_vector) return T_UINT54 is
begin
return RESIZE(UNSIGNED(v), T_UINT54'length);
end UINT54;
-- converts an integer to UINT55
pure function UINT55(v: integer) return T_UINT55 is
begin
return TO_UNSIGNED(v, T_UINT55'length);
end UINT55;
-- converts a std_logic_vector to UINT55
pure function UINT55(v: std_logic_vector) return T_UINT55 is
begin
return RESIZE(UNSIGNED(v), T_UINT55'length);
end UINT55;
-- converts an integer to UINT56
pure function UINT56(v: integer) return T_UINT56 is
begin
return TO_UNSIGNED(v, T_UINT56'length);
end UINT56;
-- converts a std_logic_vector to UINT56
pure function UINT56(v: std_logic_vector) return T_UINT56 is
begin
return RESIZE(UNSIGNED(v), T_UINT56'length);
end UINT56;
-- converts an integer to UINT57
pure function UINT57(v: integer) return T_UINT57 is
begin
return TO_UNSIGNED(v, T_UINT57'length);
end UINT57;
-- converts a std_logic_vector to UINT57
pure function UINT57(v: std_logic_vector) return T_UINT57 is
begin
return RESIZE(UNSIGNED(v), T_UINT57'length);
end UINT57;
-- converts an integer to UINT58
pure function UINT58(v: integer) return T_UINT58 is
begin
return TO_UNSIGNED(v, T_UINT58'length);
end UINT58;
-- converts a std_logic_vector to UINT58
pure function UINT58(v: std_logic_vector) return T_UINT58 is
begin
return RESIZE(UNSIGNED(v), T_UINT58'length);
end UINT58;
-- converts an integer to UINT59
pure function UINT59(v: integer) return T_UINT59 is
begin
return TO_UNSIGNED(v, T_UINT59'length);
end UINT59;
-- converts a std_logic_vector to UINT59
pure function UINT59(v: std_logic_vector) return T_UINT59 is
begin
return RESIZE(UNSIGNED(v), T_UINT59'length);
end UINT59;
-- converts an integer to UINT60
pure function UINT60(v: integer) return T_UINT60 is
begin
return TO_UNSIGNED(v, T_UINT60'length);
end UINT60;
-- converts a std_logic_vector to UINT60
pure function UINT60(v: std_logic_vector) return T_UINT60 is
begin
return RESIZE(UNSIGNED(v), T_UINT60'length);
end UINT60;
-- converts an integer to UINT61
pure function UINT61(v: integer) return T_UINT61 is
begin
return TO_UNSIGNED(v, T_UINT61'length);
end UINT61;
-- converts a std_logic_vector to UINT61
pure function UINT61(v: std_logic_vector) return T_UINT61 is
begin
return RESIZE(UNSIGNED(v), T_UINT61'length);
end UINT61;
-- converts an integer to UINT62
pure function UINT62(v: integer) return T_UINT62 is
begin
return TO_UNSIGNED(v, T_UINT62'length);
end UINT62;
-- converts a std_logic_vector to UINT62
pure function UINT62(v: std_logic_vector) return T_UINT62 is
begin
return RESIZE(UNSIGNED(v), T_UINT62'length);
end UINT62;
-- converts an integer to UINT63
pure function UINT63(v: integer) return T_UINT63 is
begin
return TO_UNSIGNED(v, T_UINT63'length);
end UINT63;
-- converts a std_logic_vector to UINT63
pure function UINT63(v: std_logic_vector) return T_UINT63 is
begin
return RESIZE(UNSIGNED(v), T_UINT63'length);
end UINT63;
-- converts an integer to INT1
pure function INT1(v: integer) return T_INT1 is
begin
return TO_SIGNED(v, T_INT1'length);
end INT1;
-- converts a std_logic_vector to INT1
pure function INT1(v: std_logic_vector) return T_INT1 is
begin
return RESIZE(SIGNED(v), T_INT1'length);
end INT1;
-- converts an integer to INT2
pure function INT2(v: integer) return T_INT2 is
begin
return TO_SIGNED(v, T_INT2'length);
end INT2;
-- converts a std_logic_vector to INT2
pure function INT2(v: std_logic_vector) return T_INT2 is
begin
return RESIZE(SIGNED(v), T_INT2'length);
end INT2;
-- converts an integer to INT3
pure function INT3(v: integer) return T_INT3 is
begin
return TO_SIGNED(v, T_INT3'length);
end INT3;
-- converts a std_logic_vector to INT3
pure function INT3(v: std_logic_vector) return T_INT3 is
begin
return RESIZE(SIGNED(v), T_INT3'length);
end INT3;
-- converts an integer to INT4
pure function INT4(v: integer) return T_INT4 is
begin
return TO_SIGNED(v, T_INT4'length);
end INT4;
-- converts a std_logic_vector to INT4
pure function INT4(v: std_logic_vector) return T_INT4 is
begin
return RESIZE(SIGNED(v), T_INT4'length);
end INT4;
-- converts an integer to INT5
pure function INT5(v: integer) return T_INT5 is
begin
return TO_SIGNED(v, T_INT5'length);
end INT5;
-- converts a std_logic_vector to INT5
pure function INT5(v: std_logic_vector) return T_INT5 is
begin
return RESIZE(SIGNED(v), T_INT5'length);
end INT5;
-- converts an integer to INT6
pure function INT6(v: integer) return T_INT6 is
begin
return TO_SIGNED(v, T_INT6'length);
end INT6;
-- converts a std_logic_vector to INT6
pure function INT6(v: std_logic_vector) return T_INT6 is
begin
return RESIZE(SIGNED(v), T_INT6'length);
end INT6;
-- converts an integer to INT7
pure function INT7(v: integer) return T_INT7 is
begin
return TO_SIGNED(v, T_INT7'length);
end INT7;
-- converts a std_logic_vector to INT7
pure function INT7(v: std_logic_vector) return T_INT7 is
begin
return RESIZE(SIGNED(v), T_INT7'length);
end INT7;
-- converts an integer to INT9
pure function INT9(v: integer) return T_INT9 is
begin
return TO_SIGNED(v, T_INT9'length);
end INT9;
-- converts a std_logic_vector to INT9
pure function INT9(v: std_logic_vector) return T_INT9 is
begin
return RESIZE(SIGNED(v), T_INT9'length);
end INT9;
-- converts an integer to INT10
pure function INT10(v: integer) return T_INT10 is
begin
return TO_SIGNED(v, T_INT10'length);
end INT10;
-- converts a std_logic_vector to INT10
pure function INT10(v: std_logic_vector) return T_INT10 is
begin
return RESIZE(SIGNED(v), T_INT10'length);
end INT10;
-- converts an integer to INT11
pure function INT11(v: integer) return T_INT11 is
begin
return TO_SIGNED(v, T_INT11'length);
end INT11;
-- converts a std_logic_vector to INT11
pure function INT11(v: std_logic_vector) return T_INT11 is
begin
return RESIZE(SIGNED(v), T_INT11'length);
end INT11;
-- converts an integer to INT12
pure function INT12(v: integer) return T_INT12 is
begin
return TO_SIGNED(v, T_INT12'length);
end INT12;
-- converts a std_logic_vector to INT12
pure function INT12(v: std_logic_vector) return T_INT12 is
begin
return RESIZE(SIGNED(v), T_INT12'length);
end INT12;
-- converts an integer to INT13
pure function INT13(v: integer) return T_INT13 is
begin
return TO_SIGNED(v, T_INT13'length);
end INT13;
-- converts a std_logic_vector to INT13
pure function INT13(v: std_logic_vector) return T_INT13 is
begin
return RESIZE(SIGNED(v), T_INT13'length);
end INT13;
-- converts an integer to INT14
pure function INT14(v: integer) return T_INT14 is
begin
return TO_SIGNED(v, T_INT14'length);
end INT14;
-- converts a std_logic_vector to INT14
pure function INT14(v: std_logic_vector) return T_INT14 is
begin
return RESIZE(SIGNED(v), T_INT14'length);
end INT14;
-- converts an integer to INT15
pure function INT15(v: integer) return T_INT15 is
begin
return TO_SIGNED(v, T_INT15'length);
end INT15;
-- converts a std_logic_vector to INT15
pure function INT15(v: std_logic_vector) return T_INT15 is
begin
return RESIZE(SIGNED(v), T_INT15'length);
end INT15;
-- converts an integer to INT17
pure function INT17(v: integer) return T_INT17 is
begin
return TO_SIGNED(v, T_INT17'length);
end INT17;
-- converts a std_logic_vector to INT17
pure function INT17(v: std_logic_vector) return T_INT17 is
begin
return RESIZE(SIGNED(v), T_INT17'length);
end INT17;
-- converts an integer to INT18
pure function INT18(v: integer) return T_INT18 is
begin
return TO_SIGNED(v, T_INT18'length);
end INT18;
-- converts a std_logic_vector to INT18
pure function INT18(v: std_logic_vector) return T_INT18 is
begin
return RESIZE(SIGNED(v), T_INT18'length);
end INT18;
-- converts an integer to INT19
pure function INT19(v: integer) return T_INT19 is
begin
return TO_SIGNED(v, T_INT19'length);
end INT19;
-- converts a std_logic_vector to INT19
pure function INT19(v: std_logic_vector) return T_INT19 is
begin
return RESIZE(SIGNED(v), T_INT19'length);
end INT19;
-- converts an integer to INT20
pure function INT20(v: integer) return T_INT20 is
begin
return TO_SIGNED(v, T_INT20'length);
end INT20;
-- converts a std_logic_vector to INT20
pure function INT20(v: std_logic_vector) return T_INT20 is
begin
return RESIZE(SIGNED(v), T_INT20'length);
end INT20;
-- converts an integer to INT21
pure function INT21(v: integer) return T_INT21 is
begin
return TO_SIGNED(v, T_INT21'length);
end INT21;
-- converts a std_logic_vector to INT21
pure function INT21(v: std_logic_vector) return T_INT21 is
begin
return RESIZE(SIGNED(v), T_INT21'length);
end INT21;
-- converts an integer to INT22
pure function INT22(v: integer) return T_INT22 is
begin
return TO_SIGNED(v, T_INT22'length);
end INT22;
-- converts a std_logic_vector to INT22
pure function INT22(v: std_logic_vector) return T_INT22 is
begin
return RESIZE(SIGNED(v), T_INT22'length);
end INT22;
-- converts an integer to INT23
pure function INT23(v: integer) return T_INT23 is
begin
return TO_SIGNED(v, T_INT23'length);
end INT23;
-- converts a std_logic_vector to INT23
pure function INT23(v: std_logic_vector) return T_INT23 is
begin
return RESIZE(SIGNED(v), T_INT23'length);
end INT23;
-- converts an integer to INT24
pure function INT24(v: integer) return T_INT24 is
begin
return TO_SIGNED(v, T_INT24'length);
end INT24;
-- converts a std_logic_vector to INT24
pure function INT24(v: std_logic_vector) return T_INT24 is
begin
return RESIZE(SIGNED(v), T_INT24'length);
end INT24;
-- converts an integer to INT25
pure function INT25(v: integer) return T_INT25 is
begin
return TO_SIGNED(v, T_INT25'length);
end INT25;
-- converts a std_logic_vector to INT25
pure function INT25(v: std_logic_vector) return T_INT25 is
begin
return RESIZE(SIGNED(v), T_INT25'length);
end INT25;
-- converts an integer to INT26
pure function INT26(v: integer) return T_INT26 is
begin
return TO_SIGNED(v, T_INT26'length);
end INT26;
-- converts a std_logic_vector to INT26
pure function INT26(v: std_logic_vector) return T_INT26 is
begin
return RESIZE(SIGNED(v), T_INT26'length);
end INT26;
-- converts an integer to INT27
pure function INT27(v: integer) return T_INT27 is
begin
return TO_SIGNED(v, T_INT27'length);
end INT27;
-- converts a std_logic_vector to INT27
pure function INT27(v: std_logic_vector) return T_INT27 is
begin
return RESIZE(SIGNED(v), T_INT27'length);
end INT27;
-- converts an integer to INT28
pure function INT28(v: integer) return T_INT28 is
begin
return TO_SIGNED(v, T_INT28'length);
end INT28;
-- converts a std_logic_vector to INT28
pure function INT28(v: std_logic_vector) return T_INT28 is
begin
return RESIZE(SIGNED(v), T_INT28'length);
end INT28;
-- converts an integer to INT29
pure function INT29(v: integer) return T_INT29 is
begin
return TO_SIGNED(v, T_INT29'length);
end INT29;
-- converts a std_logic_vector to INT29
pure function INT29(v: std_logic_vector) return T_INT29 is
begin
return RESIZE(SIGNED(v), T_INT29'length);
end INT29;
-- converts an integer to INT30
pure function INT30(v: integer) return T_INT30 is
begin
return TO_SIGNED(v, T_INT30'length);
end INT30;
-- converts a std_logic_vector to INT30
pure function INT30(v: std_logic_vector) return T_INT30 is
begin
return RESIZE(SIGNED(v), T_INT30'length);
end INT30;
-- converts an integer to INT31
pure function INT31(v: integer) return T_INT31 is
begin
return TO_SIGNED(v, T_INT31'length);
end INT31;
-- converts a std_logic_vector to INT31
pure function INT31(v: std_logic_vector) return T_INT31 is
begin
return RESIZE(SIGNED(v), T_INT31'length);
end INT31;
-- converts an integer to INT33
pure function INT33(v: integer) return T_INT33 is
begin
return TO_SIGNED(v, T_INT33'length);
end INT33;
-- converts a std_logic_vector to INT33
pure function INT33(v: std_logic_vector) return T_INT33 is
begin
return RESIZE(SIGNED(v), T_INT33'length);
end INT33;
-- converts an integer to INT34
pure function INT34(v: integer) return T_INT34 is
begin
return TO_SIGNED(v, T_INT34'length);
end INT34;
-- converts a std_logic_vector to INT34
pure function INT34(v: std_logic_vector) return T_INT34 is
begin
return RESIZE(SIGNED(v), T_INT34'length);
end INT34;
-- converts an integer to INT35
pure function INT35(v: integer) return T_INT35 is
begin
return TO_SIGNED(v, T_INT35'length);
end INT35;
-- converts a std_logic_vector to INT35
pure function INT35(v: std_logic_vector) return T_INT35 is
begin
return RESIZE(SIGNED(v), T_INT35'length);
end INT35;
-- converts an integer to INT36
pure function INT36(v: integer) return T_INT36 is
begin
return TO_SIGNED(v, T_INT36'length);
end INT36;
-- converts a std_logic_vector to INT36
pure function INT36(v: std_logic_vector) return T_INT36 is
begin
return RESIZE(SIGNED(v), T_INT36'length);
end INT36;
-- converts an integer to INT37
pure function INT37(v: integer) return T_INT37 is
begin
return TO_SIGNED(v, T_INT37'length);
end INT37;
-- converts a std_logic_vector to INT37
pure function INT37(v: std_logic_vector) return T_INT37 is
begin
return RESIZE(SIGNED(v), T_INT37'length);
end INT37;
-- converts an integer to INT38
pure function INT38(v: integer) return T_INT38 is
begin
return TO_SIGNED(v, T_INT38'length);
end INT38;
-- converts a std_logic_vector to INT38
pure function INT38(v: std_logic_vector) return T_INT38 is
begin
return RESIZE(SIGNED(v), T_INT38'length);
end INT38;
-- converts an integer to INT39
pure function INT39(v: integer) return T_INT39 is
begin
return TO_SIGNED(v, T_INT39'length);
end INT39;
-- converts a std_logic_vector to INT39
pure function INT39(v: std_logic_vector) return T_INT39 is
begin
return RESIZE(SIGNED(v), T_INT39'length);
end INT39;
-- converts an integer to INT40
pure function INT40(v: integer) return T_INT40 is
begin
return TO_SIGNED(v, T_INT40'length);
end INT40;
-- converts a std_logic_vector to INT40
pure function INT40(v: std_logic_vector) return T_INT40 is
begin
return RESIZE(SIGNED(v), T_INT40'length);
end INT40;
-- converts an integer to INT41
pure function INT41(v: integer) return T_INT41 is
begin
return TO_SIGNED(v, T_INT41'length);
end INT41;
-- converts a std_logic_vector to INT41
pure function INT41(v: std_logic_vector) return T_INT41 is
begin
return RESIZE(SIGNED(v), T_INT41'length);
end INT41;
-- converts an integer to INT42
pure function INT42(v: integer) return T_INT42 is
begin
return TO_SIGNED(v, T_INT42'length);
end INT42;
-- converts a std_logic_vector to INT42
pure function INT42(v: std_logic_vector) return T_INT42 is
begin
return RESIZE(SIGNED(v), T_INT42'length);
end INT42;
-- converts an integer to INT43
pure function INT43(v: integer) return T_INT43 is
begin
return TO_SIGNED(v, T_INT43'length);
end INT43;
-- converts a std_logic_vector to INT43
pure function INT43(v: std_logic_vector) return T_INT43 is
begin
return RESIZE(SIGNED(v), T_INT43'length);
end INT43;
-- converts an integer to INT44
pure function INT44(v: integer) return T_INT44 is
begin
return TO_SIGNED(v, T_INT44'length);
end INT44;
-- converts a std_logic_vector to INT44
pure function INT44(v: std_logic_vector) return T_INT44 is
begin
return RESIZE(SIGNED(v), T_INT44'length);
end INT44;
-- converts an integer to INT45
pure function INT45(v: integer) return T_INT45 is
begin
return TO_SIGNED(v, T_INT45'length);
end INT45;
-- converts a std_logic_vector to INT45
pure function INT45(v: std_logic_vector) return T_INT45 is
begin
return RESIZE(SIGNED(v), T_INT45'length);
end INT45;
-- converts an integer to INT46
pure function INT46(v: integer) return T_INT46 is
begin
return TO_SIGNED(v, T_INT46'length);
end INT46;
-- converts a std_logic_vector to INT46
pure function INT46(v: std_logic_vector) return T_INT46 is
begin
return RESIZE(SIGNED(v), T_INT46'length);
end INT46;
-- converts an integer to INT47
pure function INT47(v: integer) return T_INT47 is
begin
return TO_SIGNED(v, T_INT47'length);
end INT47;
-- converts a std_logic_vector to INT47
pure function INT47(v: std_logic_vector) return T_INT47 is
begin
return RESIZE(SIGNED(v), T_INT47'length);
end INT47;
-- converts an integer to INT48
pure function INT48(v: integer) return T_INT48 is
begin
return TO_SIGNED(v, T_INT48'length);
end INT48;
-- converts a std_logic_vector to INT48
pure function INT48(v: std_logic_vector) return T_INT48 is
begin
return RESIZE(SIGNED(v), T_INT48'length);
end INT48;
-- converts an integer to INT49
pure function INT49(v: integer) return T_INT49 is
begin
return TO_SIGNED(v, T_INT49'length);
end INT49;
-- converts a std_logic_vector to INT49
pure function INT49(v: std_logic_vector) return T_INT49 is
begin
return RESIZE(SIGNED(v), T_INT49'length);
end INT49;
-- converts an integer to INT50
pure function INT50(v: integer) return T_INT50 is
begin
return TO_SIGNED(v, T_INT50'length);
end INT50;
-- converts a std_logic_vector to INT50
pure function INT50(v: std_logic_vector) return T_INT50 is
begin
return RESIZE(SIGNED(v), T_INT50'length);
end INT50;
-- converts an integer to INT51
pure function INT51(v: integer) return T_INT51 is
begin
return TO_SIGNED(v, T_INT51'length);
end INT51;
-- converts a std_logic_vector to INT51
pure function INT51(v: std_logic_vector) return T_INT51 is
begin
return RESIZE(SIGNED(v), T_INT51'length);
end INT51;
-- converts an integer to INT52
pure function INT52(v: integer) return T_INT52 is
begin
return TO_SIGNED(v, T_INT52'length);
end INT52;
-- converts a std_logic_vector to INT52
pure function INT52(v: std_logic_vector) return T_INT52 is
begin
return RESIZE(SIGNED(v), T_INT52'length);
end INT52;
-- converts an integer to INT53
pure function INT53(v: integer) return T_INT53 is
begin
return TO_SIGNED(v, T_INT53'length);
end INT53;
-- converts a std_logic_vector to INT53
pure function INT53(v: std_logic_vector) return T_INT53 is
begin
return RESIZE(SIGNED(v), T_INT53'length);
end INT53;
-- converts an integer to INT54
pure function INT54(v: integer) return T_INT54 is
begin
return TO_SIGNED(v, T_INT54'length);
end INT54;
-- converts a std_logic_vector to INT54
pure function INT54(v: std_logic_vector) return T_INT54 is
begin
return RESIZE(SIGNED(v), T_INT54'length);
end INT54;
-- converts an integer to INT55
pure function INT55(v: integer) return T_INT55 is
begin
return TO_SIGNED(v, T_INT55'length);
end INT55;
-- converts a std_logic_vector to INT55
pure function INT55(v: std_logic_vector) return T_INT55 is
begin
return RESIZE(SIGNED(v), T_INT55'length);
end INT55;
-- converts an integer to INT56
pure function INT56(v: integer) return T_INT56 is
begin
return TO_SIGNED(v, T_INT56'length);
end INT56;
-- converts a std_logic_vector to INT56
pure function INT56(v: std_logic_vector) return T_INT56 is
begin
return RESIZE(SIGNED(v), T_INT56'length);
end INT56;
-- converts an integer to INT57
pure function INT57(v: integer) return T_INT57 is
begin
return TO_SIGNED(v, T_INT57'length);
end INT57;
-- converts a std_logic_vector to INT57
pure function INT57(v: std_logic_vector) return T_INT57 is
begin
return RESIZE(SIGNED(v), T_INT57'length);
end INT57;
-- converts an integer to INT58
pure function INT58(v: integer) return T_INT58 is
begin
return TO_SIGNED(v, T_INT58'length);
end INT58;
-- converts a std_logic_vector to INT58
pure function INT58(v: std_logic_vector) return T_INT58 is
begin
return RESIZE(SIGNED(v), T_INT58'length);
end INT58;
-- converts an integer to INT59
pure function INT59(v: integer) return T_INT59 is
begin
return TO_SIGNED(v, T_INT59'length);
end INT59;
-- converts a std_logic_vector to INT59
pure function INT59(v: std_logic_vector) return T_INT59 is
begin
return RESIZE(SIGNED(v), T_INT59'length);
end INT59;
-- converts an integer to INT60
pure function INT60(v: integer) return T_INT60 is
begin
return TO_SIGNED(v, T_INT60'length);
end INT60;
-- converts a std_logic_vector to INT60
pure function INT60(v: std_logic_vector) return T_INT60 is
begin
return RESIZE(SIGNED(v), T_INT60'length);
end INT60;
-- converts an integer to INT61
pure function INT61(v: integer) return T_INT61 is
begin
return TO_SIGNED(v, T_INT61'length);
end INT61;
-- converts a std_logic_vector to INT61
pure function INT61(v: std_logic_vector) return T_INT61 is
begin
return RESIZE(SIGNED(v), T_INT61'length);
end INT61;
-- converts an integer to INT62
pure function INT62(v: integer) return T_INT62 is
begin
return TO_SIGNED(v, T_INT62'length);
end INT62;
-- converts a std_logic_vector to INT62
pure function INT62(v: std_logic_vector) return T_INT62 is
begin
return RESIZE(SIGNED(v), T_INT62'length);
end INT62;
-- converts an integer to INT63
pure function INT63(v: integer) return T_INT63 is
begin
return TO_SIGNED(v, T_INT63'length);
end INT63;
-- converts a std_logic_vector to INT63
pure function INT63(v: std_logic_vector) return T_INT63 is
begin
return RESIZE(SIGNED(v), T_INT63'length);
end INT63;
-- converts an integer to SYSTEM_UINT8
pure function SYSTEM_UINT8(v: integer) return T_SYSTEM_UINT8 is
begin
return TO_UNSIGNED(v, T_SYSTEM_UINT8'length);
end SYSTEM_UINT8;
-- converts a std_logic_vector to SYSTEM_UINT8
pure function SYSTEM_UINT8(v: std_logic_vector) return T_SYSTEM_UINT8 is
begin
return RESIZE(UNSIGNED(v), T_SYSTEM_UINT8'length);
end SYSTEM_UINT8;
-- converts an integer to SYSTEM_UINT16
pure function SYSTEM_UINT16(v: integer) return T_SYSTEM_UINT16 is
begin
return TO_UNSIGNED(v, T_SYSTEM_UINT16'length);
end SYSTEM_UINT16;
-- converts a std_logic_vector to SYSTEM_UINT16
pure function SYSTEM_UINT16(v: std_logic_vector) return T_SYSTEM_UINT16 is
begin
return RESIZE(UNSIGNED(v), T_SYSTEM_UINT16'length);
end SYSTEM_UINT16;
-- converts an integer to SYSTEM_UINT32
pure function SYSTEM_UINT32(v: integer) return T_SYSTEM_UINT32 is
begin
return TO_UNSIGNED(v, T_SYSTEM_UINT32'length);
end SYSTEM_UINT32;
-- converts a std_logic_vector to SYSTEM_UINT32
pure function SYSTEM_UINT32(v: std_logic_vector) return T_SYSTEM_UINT32 is
begin
return RESIZE(UNSIGNED(v), T_SYSTEM_UINT32'length);
end SYSTEM_UINT32;
-- converts an integer to SYSTEM_UINT64
pure function SYSTEM_UINT64(v: integer) return T_SYSTEM_UINT64 is
begin
return TO_UNSIGNED(v, T_SYSTEM_UINT64'length);
end SYSTEM_UINT64;
-- converts a std_logic_vector to SYSTEM_UINT64
pure function SYSTEM_UINT64(v: std_logic_vector) return T_SYSTEM_UINT64 is
begin
return RESIZE(UNSIGNED(v), T_SYSTEM_UINT64'length);
end SYSTEM_UINT64;
-- converts an integer to SYSTEM_INT8
pure function SYSTEM_INT8(v: integer) return T_SYSTEM_INT8 is
begin
return TO_SIGNED(v, T_SYSTEM_INT8'length);
end SYSTEM_INT8;
-- converts a std_logic_vector to SYSTEM_INT8
pure function SYSTEM_INT8(v: std_logic_vector) return T_SYSTEM_INT8 is
begin
return RESIZE(SIGNED(v), T_SYSTEM_INT8'length);
end SYSTEM_INT8;
-- converts an integer to SYSTEM_INT16
pure function SYSTEM_INT16(v: integer) return T_SYSTEM_INT16 is
begin
return TO_SIGNED(v, T_SYSTEM_INT16'length);
end SYSTEM_INT16;
-- converts a std_logic_vector to SYSTEM_INT16
pure function SYSTEM_INT16(v: std_logic_vector) return T_SYSTEM_INT16 is
begin
return RESIZE(SIGNED(v), T_SYSTEM_INT16'length);
end SYSTEM_INT16;
-- converts an integer to SYSTEM_INT32
pure function SYSTEM_INT32(v: integer) return T_SYSTEM_INT32 is
begin
return TO_SIGNED(v, T_SYSTEM_INT32'length);
end SYSTEM_INT32;
-- converts a std_logic_vector to SYSTEM_INT32
pure function SYSTEM_INT32(v: std_logic_vector) return T_SYSTEM_INT32 is
begin
return RESIZE(SIGNED(v), T_SYSTEM_INT32'length);
end SYSTEM_INT32;
-- converts an integer to SYSTEM_INT64
pure function SYSTEM_INT64(v: integer) return T_SYSTEM_INT64 is
begin
return TO_SIGNED(v, T_SYSTEM_INT64'length);
end SYSTEM_INT64;
-- converts a std_logic_vector to SYSTEM_INT64
pure function SYSTEM_INT64(v: std_logic_vector) return T_SYSTEM_INT64 is
begin
return RESIZE(SIGNED(v), T_SYSTEM_INT64'length);
end SYSTEM_INT64;
end SYSTEM_TYPES;
| mit | 5758df38ac76d420566793b1c6bd3669 | 0.673006 | 3.465893 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpDsp/unitDds/hdl/Dds_tb.vhd | 1 | 4,841 | -------------------------------------------------------------------------------
-- Title : Direct Digital Synthesis Testbench
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : DDS with RAM Table, Table can be defined over MM Interface
-- The Phase Incremen can also be set over an extra MM Interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_float_types.all;
use ieee.fixed_pkg.all;
use work.Global.all;
use work.sin_4096.all;
-------------------------------------------------------------------------------
entity Dds_tb is
end entity Dds_tb;
-------------------------------------------------------------------------------
architecture Bhv of Dds_tb is
constant strobe_time : time := 1 sec/real(default_sample_rate_c);
-- component generics
constant data_width_g : natural := 24;
constant phase_bits_g : natural := 20;
constant phase_dither_g : natural := 8;
constant wave_table_width_g : natural := 14;
constant wave_table_len_g : natural := 4096;
constant wave_table_addr_bits_g : natural := 12;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic := '0';
signal coe_sample_strobe : std_logic := '0';
signal avs_s0_write : std_logic := '0';
signal avs_s0_address : std_logic_vector(wave_table_addr_bits_g-1 downto 0) := (others => '0');
signal avs_s0_writedata : std_logic_vector(31 downto 0) := (others => '0');
signal avs_s1_write : std_logic := '0';
signal avs_s1_address : std_logic := '0';
signal avs_s1_writedata : std_logic_vector(31 downto 0) := (others => '0');
signal aso_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_valid : std_logic;
begin -- architecture Bhv
-- component instantiation
DUT : entity work.Dds
generic map (
data_width_g => data_width_g,
phase_bits_g => phase_bits_g,
phase_dither_g => phase_dither_g,
wave_table_width_g => wave_table_width_g,
wave_table_len_g => wave_table_len_g,
wave_table_addr_bits_g => wave_table_addr_bits_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
coe_sample_strobe => coe_sample_strobe,
avs_s0_write => avs_s0_write,
avs_s0_address => avs_s0_address,
avs_s0_writedata => avs_s0_writedata,
avs_s1_write => avs_s1_write,
avs_s1_address => avs_s1_address,
avs_s1_writedata => avs_s1_writedata,
aso_data => aso_data,
aso_valid => aso_valid);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
-- sample strobe generation
sample_strobe : process is
begin -- process
wait for strobe_time;
wait until rising_edge(csi_clk);
coe_sample_strobe <= '1';
wait until rising_edge(csi_clk);
coe_sample_strobe <= '0';
end process;
-- write sinus table into ram
avs_s0 : process is
begin -- process avs_s0
for idx in 0 to sin_table_c'length-1 loop
wait until rising_edge(csi_clk);
avs_s0_address <= std_logic_vector(to_unsigned(idx, avs_s0_address'length));
avs_s0_write <= '1';
avs_s0_writedata(wave_table_width_g-1 downto 0)
<= to_slv(to_sfixed(sin_table_c(idx), 0, -(wave_table_width_g-1)));
end loop; -- idx
end process avs_s0;
-- waveform generation
WaveGen_Proc : process
-- write function for mm interface
procedure avs_s1_wr (
constant addr : in std_ulogic;
constant data : in natural) is
begin
avs_s1_address <= addr;
avs_s1_writedata <= std_logic_vector(to_unsigned(data, avs_s1_writedata'length));
avs_s1_write <= '1';
wait for 20 ns;
avs_s1_write <= '0';
end avs_s1_wr;
begin
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
for i in 0 to wave_table_len_g loop
wait until rising_edge(csi_clk);
end loop;
wait for 20 ns;
-- enable
avs_s1_wr('0',1);
-- phase increment
wait for 5000 ns;
avs_s1_wr('1',4096);
wait for 10 ms;
avs_s1_wr('1',10000);
wait for 10 ms;
avs_s1_wr('1',3000);
wait;
end process WaveGen_Proc;
end architecture Bhv;
-------------------------------------------------------------------------------
| gpl-3.0 | 5fbe046330fd69c433ee6e211228c2ab | 0.503202 | 3.709579 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/test_source_800_600_RGB_444_ch4.vhd | 1 | 13,969 | ----------------------------------------------------------------------------------
-- Module Name: test_source_800_600_RGB_444_ch4 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case 800x600 white screen.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-13 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test_source_800_600_RGB_444_ch4 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end test_source_800_600_RGB_444_ch4;
architecture arch of test_source_800_600_RGB_444_ch4 is
type a_test_data_blocks is array (0 to 64*6-1) of std_logic_vector(8 downto 0);
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0xAA
constant SPARE : std_logic_vector(8 downto 0) := "011111111"; -- 0xFF
constant ZERO : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant PIX_80 : std_logic_vector(8 downto 0) := "011001100"; -- 0x80
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant FS : std_logic_vector(8 downto 0) := "111111110"; -- K30.7
constant FE : std_logic_vector(8 downto 0) := "111110111"; -- K23.7
constant VB_VS : std_logic_vector(8 downto 0) := "000000001"; -- 0x00 VB-ID with Vertical blank asserted
constant VB_NVS : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 VB-ID without Vertical blank asserted
constant Mvid : std_logic_vector(8 downto 0) := "001101000"; -- 0x68
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant test_data_blocks : a_test_data_blocks := (
--- Block 0 - Junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 1 - 8 white pixels and padding
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
BS, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 5 - just blank end
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, BE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE);
signal index : unsigned (8 downto 0) := (others => '0'); -- Index up to 32 x 64 symbol blocks
signal d0: std_logic_vector(8 downto 0) := (others => '0');
signal d1: std_logic_vector(8 downto 0) := (others => '0');
signal line_count : unsigned(9 downto 0) := (others => '0');
signal row_count : unsigned(7 downto 0) := (others => '0');
signal switch_point : std_logic := '0';
begin
M_value <= x"012F68";
N_value <= x"080000";
H_visible <= x"320"; -- 800
V_visible <= x"258"; -- 600
H_total <= x"420"; -- 1056
V_total <= x"274"; -- 628
H_sync_width <= x"080"; -- 128
V_sync_width <= x"004"; -- 4
H_start <= x"0D8"; -- 216
V_start <= x"01b"; -- 37
H_vsync_active_high <= '0';
V_vsync_active_high <= '0';
flag_sync_clock <= '1';
flag_YCCnRGB <= '0';
flag_422n444 <= '0';
flag_range_reduced <= '0';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "100";
ready <= '1';
data(72) <= switch_point;
data(71 downto 54) <= d1 & d0;
data(53 downto 36) <= d1 & d0;
data(35 downto 18) <= d1 & d0;
data(17 downto 0) <= d1 & d0;
process(clk)
begin
if rising_edge(clk) then
d0 <= test_data_blocks(to_integer(index+0));
d1 <= test_data_blocks(to_integer(index+1));
if index(5 downto 0) = 52 then
index(5 downto 0) <= (others => '0');
if row_count = 131 then
row_count <= (others => '0');
if line_count = 627 then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
row_count <= row_count +1;
end if;
--- Block 0 - Junk
--- Block 1- 8 white pixels and padding
--- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
--- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
--- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
--- Block 5 - just blank end
index(8 downto 6) <= "000"; -- Dummy symbols
switch_point <= '0';
if line_count < 599 then -- lines of active video (except first and last)
if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE
elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill
elsif row_count = 100 then index(8 downto 6) <= "010"; -- Pixels BS and VS-ID block (no VBLANK flag)
end if;
elsif line_count = 599 then -- Last line of active video
if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE
elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill
elsif row_count = 100 then index(8 downto 6) <= "011"; -- Pixels BS and VS-ID block (with VBLANK flag)
end if;
else
-----------------------------------------------------------------
-- Allow switching to/from the idle pattern during the vertical blank
-----------------------------------------------------------------
if row_count < 100 then switch_point <= '1';
elsif row_count = 100 then index(8 downto 6) <= "100"; -- Dummy symbols, BS and VS-ID block (with VBLANK flag)
end if;
end if;
else
index <= index + 2;
end if;
end if;
end process;
end architecture; | mit | 898fd24b2425617ce9d10b27cd949476 | 0.516644 | 3.705305 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstbitat0/tstbitat0_cfg.vhd | 1 | 3,658 | ------------------------------------------------------------------------------
-- Configuration for tstbitat0 testbench
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/tb_arch/tstbitat0/tstbitat0_cfg.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/26
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- Changes:
-- 2004-10-26 CP created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTBITAT0 is
function tstbitat0cfg return engineConfigRec;
end CfgLib_TSTBITAT0;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTBITAT0 is
----------------------------------------------------------------------------
-- tstbitat0 configuration
-- configure alu in cell row 2, col 3
-- connect INP0 and INP1 to inputs and OP0 to output
----------------------------------------------------------------------------
function tstbitat0cfg return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- configure cell_2_3
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_TSTBITAT0;
-- feed input 0 from hbusn_2.0
cfg.gridConf(2)(3).routConf.i(0).HBusNxE(0) := '1';
-- feed input 1 from hbusn_2.1
cfg.gridConf(2)(3).routConf.i(1).HBusNxE(1) := '1';
-- drive output to hbus_3.1 (HBus_CD1)
cfg.gridConf(2)(3).routConf.o.HBusNxE(1) := '1';
-- feed busses of engine from input ports
cfg.inputDriverConf(0)(2)(1) := '1'; -- connect INP0 to hbusn_2.1
cfg.inputDriverConf(1)(2)(0) := '1'; -- connect INP1 to hbusn_2.0
-- engine outputs
cfg.outputDriverConf(0)(3)(1) := '1'; -- connect OP0 to hbusn_3.1
-- i/o port controller
-- activate write to output FIFO0 after 2 cycles
cfg.outportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEUP;
cfg.outportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.outportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(1, CCNTWIDTH));
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
-- deactivate read from input FIFO0 2 cycles before end
cfg.inportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
cfg.inportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.inportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
cfg.inportConf(1).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
cfg.inportConf(1).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.inportConf(1).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_CMP0;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstbitat0cfg;
end CfgLib_TSTBITAT0;
| bsd-3-clause | c42978b4b04515b288594af2338b49b2 | 0.54702 | 3.334549 | false | true | false | false |
hamsternz/FPGA_DisplayPort | src/extract_timings.vhd | 1 | 13,253 | ----------------------------------------------------------------------------------
-- Module Name: extract_timings.vhd - Behavioral
--
-- Description: Extract the timing constants from a VGA style 800x600 signal
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-13 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity extract_timings is
Port ( pixel_clk : in STD_LOGIC;
pixel_hblank : in STD_LOGIC;
pixel_hsync : in STD_LOGIC;
pixel_vblank : in STD_LOGIC;
pixel_vsync : in STD_LOGIC;
--------------------------------------------------
-- These should be stable when ready is asserted
--------------------------------------------------
ready : out std_logic := '0';
h_visible : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
v_visible : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
h_total : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
v_total : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
h_sync_width : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
v_sync_width : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
h_start : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
v_start : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
h_sync_active_high : out std_logic := '0';
v_sync_active_high : out std_logic := '0');
end extract_timings;
architecture Behavioral of extract_timings is
signal h_count : unsigned(12 downto 0) := (others => '0');
signal h_sync_start_count : unsigned(12 downto 0) := (others => '0');
signal v_count : unsigned(12 downto 0) := (others => '0');
signal v_sync_start_count : unsigned(12 downto 0) := (others => '0');
signal h_sync_width_i : unsigned(12 downto 0) := (others => '0');
signal v_sync_width_i : unsigned(12 downto 0) := (others => '0');
signal h_start_i : unsigned(12 downto 0) := (others => '0');
signal v_start_i : unsigned(12 downto 0) := (others => '0');
signal h_total_i : unsigned(12 downto 0) := (others => '0');
signal v_total_i : unsigned(12 downto 0) := (others => '0');
signal h_visible_i : unsigned(12 downto 0) := (others => '0');
signal v_visible_i : unsigned(12 downto 0) := (others => '0');
signal h_sync_when_active_i : std_logic := '0';
signal v_sync_when_active_i : std_logic := '0';
signal pc_hblank_last : std_logic := '0';
signal pc_hsync_last : std_logic := '0';
signal pc_line_start_toggle : std_logic := '0';
signal pc_vblank_last : std_logic := '0';
signal pc_vsync_last : std_logic := '0';
signal seen_enough : unsigned(1 downto 0);
begin
h_visible <= std_logic_vector(h_visible_i);
v_visible <= std_logic_vector(v_visible_i);
h_total <= std_logic_vector(h_total_i);
v_total <= std_logic_vector(v_total_i);
h_sync_width <= std_logic_vector(h_sync_width_i);
v_sync_width <= std_logic_vector(v_sync_width_i);
h_start <= std_logic_vector(h_start_i);
v_start <= std_logic_vector(v_start_i);
h_sync_active_high <= h_sync_when_active_i;
v_sync_active_high <= v_sync_when_active_i;
process(pixel_clk)
begin
if rising_edge(pixel_clk) then
--------------------------------------------------
-- Counting the number of width and lines
-- of the input screen and other screen attributes
--------------------------------------------------
if pixel_hblank = '1' and pc_hblank_last = '0' then
if h_visible_i /= h_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
h_visible_i <= h_count;
-------------------------------------------
-- Remember the hsync state when the active
-- pixels end, this can be used to detect
-- an active high or active low hsync pulse
-------------------------------------------
h_sync_when_active_i <= not pixel_hsync;
end if;
----------------------------------
-- Start counting hsync and hstart
-- when the hsync signal becomes active
----------------------------------
if pixel_hsync = h_sync_when_active_i and pc_hsync_last = not h_sync_when_active_i then
h_sync_start_count <= (0 => '1', others => '0');
else
h_sync_start_count <= h_sync_start_count + 1;
end if;
-------------------------------------------------------
-- Capture the hsync width on the change of hsync signal
-------------------------------------------------------
if pixel_hsync = not h_sync_when_active_i and pc_hsync_last = h_sync_when_active_i then
if h_sync_width_i /= h_sync_start_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
h_sync_width_i <= h_sync_start_count;
end if;
----------------------------------------------------------
-- Cycles from start of sync to start of active pixel data
----------------------------------------------------------
if pixel_hblank = '0' and pc_hblank_last = '1' then
if h_start_i /= h_sync_start_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
h_start_i <= h_sync_start_count;
end if;
-------------------------------------------
-- Capture the visible and total line width
-------------------------------------=-----
if pixel_hblank = '0' and pc_hblank_last = '1' then
-- Capture the horizontal width
if h_total_i /= h_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
h_total_i <= h_count;
end if;
if pixel_hblank = '0' and pc_hblank_last = '1' then
h_count <= (others => '0');
h_count(0) <= '1';
else
h_count <= h_count + 1;
end if;
----------------------------------
-- Now for the vertical timings. Count
-- from when the first pixel (where hblank
-- is and vblank are both zero).
----------------------------------
if pixel_hblank = '0' and pc_hblank_last = '1' then
----------------------------------
-- Start counting vsync and vstart
-- when the vsync signal becomes active
----------------------------------
if pixel_vsync = v_sync_when_active_i and pc_vsync_last = not v_sync_when_active_i then
v_sync_start_count <= (0 => '1', others => '0');
else
v_sync_start_count <= v_sync_start_count + 1;
end if;
if pixel_vsync = not v_sync_when_active_i and pc_vsync_last = v_sync_when_active_i then
if v_sync_width_i /= v_sync_start_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
v_sync_width_i <= v_sync_start_count;
end if;
if pc_vblank_last = '1' and pixel_vblank = '0' then
if v_start_i /= v_sync_start_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
v_start_i <= v_sync_start_count;
end if;
----------------------------------------------
-- Count the visible lines on the screen
----------------------------------------------
if pixel_vblank = '1' and pc_vblank_last = '0' then
if v_visible_i /= v_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
v_visible_i <= v_count;
v_sync_when_active_i <= not pixel_vsync;
end if;
----------------------------------------------
-- Finally count the total lines on the screen
----------------------------------------------
if pixel_vblank = '0' and pc_vblank_last = '1' then
if v_total_i /= v_count then
seen_enough <= (others => '0'); -- unstable or must be changing video resolutions??
end if;
v_total_i <= v_count;
end if;
---------------------------------
-- See if things have been stable
-- throughthe entire frame
---------------------------------
if pixel_vblank = '0' and pc_vblank_last = '1' then
if seen_enough < 2 then
seen_enough <= seen_enough + 1;
end if;
end if;
--------------------------
-- Advance the row counter
--------------------------
if pixel_vblank = '0' and pc_vblank_last = '1' then
v_count <= (0=>'1', others => '0');
else
v_count <= v_count + 1;
end if;
pc_vblank_last <= pixel_vblank;
pc_vsync_last <= pixel_vsync;
end if;
pc_hblank_last <= pixel_hblank;
pc_hsync_last <= pixel_hsync;
--------------------------------------------------
-- We have to see two frames with identical is
-- timings before we declare that the source ready
--------------------------------------------------
if seen_enough = 2 then
ready <= '1';
else
ready <= '0';
end if;
end if;
end process;
end Behavioral;
| mit | e24dbc8741db3f5954496a49808893e4 | 0.444352 | 4.494066 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstrom/tstrom_cfg.vhd | 1 | 5,123 | ------------------------------------------------------------------------------
-- Library for a simple ZUnit configuration with just a single cell
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/tb_arch/tstrom/tstrom_cfg.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/11/16
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- Changes:
-- 2004-11-16 CP created
-------------------------------------------------------------------------------
-- The configuration defines a single cell at row:2, column: 3
-- Cell performs the alu_rom operation, cell output is registered.
--
-- The input data to the cell is fed from FIFO0 and routed via the
-- horizontal north buses hbusn_2.0
--
-- The output of cell 2/3 is routed to output port OP1, using the hbusn_3.1
-- (HBus_CD1) bus.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTROM is
function tstromcfg return engineConfigRec;
end CfgLib_TSTROM;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTROM is
----------------------------------------------------------------------------
-- tstor configuration
-- configure alu in cell row 2, col 3
-- connect INP0 to inputs and OP0 to output
----------------------------------------------------------------------------
function tstromcfg return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin -- tstorcfg
-- feed busses of engine from input ports
cfg.inputDriverConf(0)(2)(0) := '1'; -- connect INP0 to hbusn_2.0
-- configure cell r2c3
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_ROM;
-- feed input 0 from hbusn_2.0
cfg.gridConf(2)(3).routConf.i(0).HBusNxE(0) := '1';
-- drive output to hbus_3.1 (HBus_CD1)
cfg.gridConf(2)(3).routConf.o.HBusNxE(1) := '1';
-- engine outputs
cfg.outputDriverConf(0)(3)(1) := '1'; -- connect OP0 to hbusn_3.1
-- memory (ROM) configuration
cfg.memoryConf(2)(0) := std_logic_vector(to_signed( 1,DATAWIDTH));
cfg.memoryConf(2)(1) := std_logic_vector(to_signed( -2,DATAWIDTH));
cfg.memoryConf(2)(2) := std_logic_vector(to_signed( 3,DATAWIDTH));
cfg.memoryConf(2)(3) := std_logic_vector(to_signed( -5,DATAWIDTH));
cfg.memoryConf(2)(4) := std_logic_vector(to_signed( 7,DATAWIDTH));
cfg.memoryConf(2)(5) := std_logic_vector(to_signed(-11,DATAWIDTH));
cfg.memoryConf(2)(6) := std_logic_vector(to_signed( 13,DATAWIDTH));
cfg.memoryConf(2)(7) := std_logic_vector(to_signed(-17,DATAWIDTH));
cfg.memoryConf(2)(8) := std_logic_vector(to_signed( 19,DATAWIDTH));
cfg.memoryConf(2)(9) := std_logic_vector(to_signed(-23,DATAWIDTH));
cfg.memoryConf(2)(10) := std_logic_vector(to_signed( 29,DATAWIDTH));
cfg.memoryConf(2)(11) := std_logic_vector(to_signed(-31,DATAWIDTH));
cfg.memoryConf(2)(12) := std_logic_vector(to_signed( 37,DATAWIDTH));
cfg.memoryConf(2)(13) := std_logic_vector(to_signed(-41,DATAWIDTH));
cfg.memoryConf(2)(14) := std_logic_vector(to_signed( 43,DATAWIDTH));
cfg.memoryConf(2)(15) := std_logic_vector(to_signed(-47,DATAWIDTH));
cfg.memoryConf(2)(16) := std_logic_vector(to_signed( 53,DATAWIDTH));
cfg.memoryConf(2)(17) := std_logic_vector(to_signed(-59,DATAWIDTH));
cfg.memoryConf(2)(18) := std_logic_vector(to_signed( 61,DATAWIDTH));
cfg.memoryConf(2)(19) := std_logic_vector(to_signed(-67,DATAWIDTH));
-- i/o port controller
-- activate write to output FIFO0 after 2 cycles
cfg.outportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEUP;
cfg.outportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.outportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(1, CCNTWIDTH));
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
-- deactivate read from input FIFO0 2 cycles before end
cfg.inportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
cfg.inportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.inportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF; -- InPort1 deactivated
return cfg;
end tstromcfg;
end CfgLib_TSTROM;
| bsd-3-clause | 247f42c6ac0da38894461e14ced6dfba | 0.569588 | 3.381518 | false | true | false | false |
mpownby/emucore | new_hardware/williams_special_chip/vhdl/WilliamsSC/main.vhd | 1 | 3,521 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:19:40 08/05/2014
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port (
AH : out std_logic_vector(15 downto 8);
AL : inout std_logic_vector(7 downto 0);
BA_BS_N : in std_logic;
CS_N : in std_logic;
D : inout std_logic_vector(7 downto 0);
E_N : in std_logic;
HALT_N : in std_logic;
HTCF_N : out std_logic;
CLK_4MHZ : in std_logic;
R_WN : inout std_logic;
RESET_N : in std_logic;
TCF_N : in std_logic;
U_LN : in std_logic;
WINH_N : out std_logic);
end main;
architecture Behavioral of main is
--mode bits
signal srcstride : std_logic;
signal dststride : std_logic;
signal synce : std_logic;
signal transparency : std_logic;
signal solid : std_logic;
signal shift : std_logic;
signal inhl : std_logic;
signal inhu : std_logic;
--registers
signal color : std_logic_vector(7 downto 0);
signal src : std_logic_vector(15 downto 0);
signal dst : std_logic_vector(15 downto 0);
signal width : std_logic_vector(7 downto 0);
signal height : std_logic_vector(7 downto 0);
signal reqhalt : std_logic := '0';
signal doblit : std_logic := '0';
signal csqueued : std_logic := '0';
begin
AH(15 downto 8) <= "11111111";
--AL(7 downto 0) <= "11111111";
--D(7 downto 0) <= "11111111";
HTCF_N <= '1';
--R_WN <= '1';
WINH_N <= '1';
watch_cs : process(E_N,RESET_N)
begin
if (RESET_N='0') then
-- todo
else
if (falling_edge(E_N)) then
if (CS_N='0') then
csqueued <= '1';
end if;
end if;
end if;
end process;
loadreg: process(CLK_4MHZ,RESET_N)
begin
if(RESET_N='0') then
doblit<='0';
else
if(rising_edge(CLK_4MHZ)) then
if (csqueued = '1') then
case AL(2 downto 0) IS
when "000" =>
--set mode bits
srcstride <= D(0);
dststride <= D(1);
synce <= D(2);
transparency <= D(3);
solid <= D(4);
shift <= D(5);
inhl <= D(6);
inhu <= D(7);
--start blit
doblit <= '1';
when "001" =>
--set color replacement
color <= D;
when "010" =>
--set src high
src(15 downto 8) <= D;
when "011" =>
--set src low
src(7 downto 0) <= D;
when "100" =>
--set dest high
dst(15 downto 8) <= D;
when "101" =>
--set dest low
dst(7 downto 0) <= D;
when "110" =>
--set width
width <= D xor "00000100";
when "111" =>
--set height
height <= D xor "00000100";
when others =>
end case;
-- wait for CS to be lowered again
csqueued <= '0';
end if; -- CS was lowered
end if; -- rising edge of CLK_4MHZ
end if; -- else if RESET_N is not low
end process;
end Behavioral;
| bsd-2-clause | 5de2c42da0bc10b0132bcc8bc21b4bc0 | 0.542744 | 3.118689 | false | false | false | false |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd | 1 | 4,380 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-2.0 | e1e56e3f3ab5377a3e4bec1c5c91301f | 0.574886 | 4.634921 | false | false | false | false |
hamsternz/FPGA_DisplayPort | test_benches/tb_transceiver.vhd | 1 | 5,707 | ----------------------------------------------------------------------------------
-- Module Name: tb_transceiver_test - Behavioral
--
-- Description: A testbench for the transceiver_test
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_transceiver is
end entity;
architecture arch of tb_transceiver is
component Transceiver is
generic( use_hw_8b10b_support : std_logic := '0');
Port ( mgmt_clk : in STD_LOGIC;
powerup_channel : in STD_LOGIC_VECTOR;
gclk27 : in STD_LOGIC;
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
swing_0p4 : in STD_LOGIC;
swing_0p6 : in STD_LOGIC;
swing_0p8 : in STD_LOGIC;
tx_running : out STD_LOGIC_VECTOR := (others => '0');
symbolclk : out STD_LOGIC;
in_symbols : in std_logic_vector(79 downto 0);
gtptxp : out std_logic_vector(3 downto 0);
gtptxn : out std_logic_vector(3 downto 0));
end component;
signal symbols : std_logic_vector(79 downto 0 ) := (others => '0');
signal clk : std_logic := '0';
signal symbolclk : std_logic := '0';
signal tx_running : std_logic_vector(3 downto 0);
signal powerup_channel : std_logic_vector(3 downto 0) := "0000";
signal gtptxp : std_logic_vector(3 downto 0);
signal gtptxn : std_logic_vector(3 downto 0);
signal gclk27 : STD_LOGIC := '1';
begin
uut: transceiver generic map (
use_hw_8b10b_support => '1'
) PORT MAP (
mgmt_clk => clk,
powerup_channel => powerup_channel,
gclk27 => gclk27,
preemp_0p0 => '1',
preemp_3p5 => '0',
preemp_6p0 => '0',
swing_0p4 => '1',
swing_0p6 => '0',
swing_0p8 => '0',
tx_running => tx_running,
symbolclk => symbolclk,
in_symbols => symbols,
gtptxp => gtptxp,
gtptxn => gtptxn
);
process(symbolclk)
begin
if rising_edge(symbolclk) then
if symbols(3 downto 0) = x"A" then
symbols <= x"00000" & x"00000" & "0110111100" & "0110111100" & "0110111100" & "0000000000";
else
symbols <= x"00000" & x"00000" & "0110111100" & "0110111100" & "0001001010" & "0001001010";
end if;
end if;
end process;
process
begin
wait for 5 ns;
clk <= '1';
wait for 5 ns;
clk <= '0';
end process;
process
begin
gclk27 <='0';
wait for 18.5 ns;
gclk27 <='1';
wait for 18.5 ns;
end process;
process
begin
wait for 25 ns;
powerup_channel <= "0011";
wait;
end process;
end architecture; | mit | 47421172fccacd51b18bc2bdc1ba4589 | 0.500613 | 4.150545 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_reg_aclr_en.vhd | 1 | 4,270 | ------------------------------------------------------------------------------
-- Testbench for reg_aclr_en.vhd
--
-- Project :
-- File : tb_reg_aclr_en.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/05
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Reg_aclr_en is
end tb_Reg_aclr_en;
architecture arch of tb_Reg_aclr_en is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, en, dis, clr, clr_en);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxAB : std_logic;
signal EnxE : std_logic;
signal DinxD : std_logic_vector(WIDTH-1 downto 0);
signal DoutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Reg_AClr_En
generic map (
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxABI => ClrxAB,
EnxEI => EnxE,
DinxDI => DinxD,
DoutxDO => DoutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
ClrxAB <= '1';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(0, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= en;
ClrxAB <= '1';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(1, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxAB <= '1';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(2, WIDTH));
wait for CLK_PERIOD;
tbStatus <= en;
ClrxAB <= '1';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(3, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxAB <= '1';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(4, WIDTH));
wait for CLK_PERIOD;
tbStatus <= clr;
ClrxAB <= '0';
EnxE <= '0';
DinxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= en;
ClrxAB <= '1';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(5, WIDTH));
wait for CLK_PERIOD;
tbStatus <= dis;
ClrxAB <= '1';
EnxE <= '0';
DinxD <= std_logic_vector(to_unsigned(6, WIDTH));
wait for CLK_PERIOD;
tbStatus <= clr_en;
ClrxAB <= '0';
EnxE <= '1';
DinxD <= std_logic_vector(to_unsigned(7, WIDTH));
wait for CLK_PERIOD;
tbStatus <= done;
ClrxAB <= '1';
EnxE <= '0';
DinxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 564447931c512baaffbc735e7c751baf | 0.466745 | 3.703382 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpStream/unitChannelMux/hdl/ChannelMux-Rtl-a.vhd | 1 | 3,445 | -------------------------------------------------------------------------------
-- Title : Channel Mux
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Unit Mux left and right channel
-------------------------------------------------------------------------------
architecture Rtl of ChannelMux is
---------------------------------------------------------------------------
-- Types and constants
---------------------------------------------------------------------------
subtype aMuxSel is std_logic_vector (3 downto 0);
signal MuxSel : aMuxSel;
constant cSilence : std_logic_vector(gDataWidth-1 downto 0) := (others => '0');
begin
-- combinatoric output logic
out_mux : process(MuxSel, asi_left_data, asi_left_valid, asi_right_data, asi_right_valid) is
variable L, R : std_logic_vector(gDataWidth-1 downto 0);
begin -- process out_mux
-- mute left channel
case MuxSel(3) is
when '0' => L := asi_left_data;
when '1' => L := cSilence;
when others => L := (others => 'X');
end case;
-- mute right channel
case MuxSel(2) is
when '0' => R := asi_right_data;
when '1' => R := cSilence;
when others => R := (others => 'X');
end case;
-- function cross or skip
case MuxSel(1) is
-- cross channels
when '0' =>
-- cross or straight
case MuxSel(0) is
when '0' => -- straight
aso_left_data <= L;
aso_left_valid <= asi_left_valid;
aso_right_data <= R;
aso_right_valid <= asi_right_valid;
when '1' => -- cross
aso_left_data <= R;
aso_left_valid <= asi_right_valid;
aso_right_data <= L;
aso_right_valid <= asi_left_valid;
when others =>
aso_left_data <= (others => 'X');
aso_left_valid <= 'X';
aso_right_data <= (others => 'X');
aso_right_valid <= 'X';
end case;
-- skip channel
when '1' =>
-- both L or R
case MuxSel(0) is
when '0' => -- both left
aso_left_data <= L;
aso_left_valid <= asi_left_valid;
aso_right_data <= L;
aso_right_valid <= asi_left_valid;
when '1' => -- both right
aso_left_data <= R;
aso_left_valid <= asi_right_valid;
aso_right_data <= R;
aso_right_valid <= asi_right_valid;
when others =>
aso_left_data <= (others => 'X');
aso_left_valid <= 'X';
aso_right_data <= (others => 'X');
aso_right_valid <= 'X';
end case;
when others =>
aso_left_data <= (others => 'X');
aso_left_valid <= 'X';
aso_right_data <= (others => 'X');
aso_right_valid <= 'X';
end case;
end process out_mux;
-- MM INTERFACE for configuration
SetConfigReg : process (csi_clk, rsi_reset_n) is
begin
if rsi_reset_n = not('1') then -- low active reset
MuxSel <= (others => '0');
elsif rising_edge(csi_clk) then -- rising
if avs_s0_write = '1' then
MuxSel <= avs_s0_writedata(MuxSel'range);
end if;
end if;
end process;
end architecture Rtl;
| gpl-3.0 | ba8362c6f5f05fbfe7e8602fd82ff2a4 | 0.439478 | 3.857783 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/hotplug_decode.vhd | 1 | 5,372 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: hotplug_decode - Behavioral
--
-- Description: The Hot Plug Detect signal has two uses, one is to to signal the
-- physical connection of a sink device, and the other is to signal
-- an interrupt if the state changes.
--
-- An interrupt is signalled by a 500us to 1ms '0' pulse. But from
-- the spec any pulse under 2ms is to be interperated as and IRQ
--
-- NOTE: Assumes that clk is running at 100MHz.
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hotplug_decode is
port (clk : in std_logic;
hpd : in std_logic;
irq : out std_logic := '0';
present : out std_logic := '0');
end entity;
architecture arch of hotplug_decode is
signal hpd_meta1 : std_logic := '0';
signal hpd_meta2 : std_logic := '0';
signal hpd_synced : std_logic := '0';
signal hpd_last : std_logic := '0';
signal pulse_count : unsigned (17 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
irq <= '0';
if hpd_last = '0' then
if pulse_count = 2000000 then
if hpd_synced = '0' then
----------------------------------
-- Sink has gone away for over 1ms
----------------------------------
present <= '0';
else
----------------------------------
-- Sink has been connected
----------------------------------
present <= '1';
end if;
else
-------------------------------------
if hpd_synced = '1' then
-------------------------------------
-- Signal is back, but less than 2ms
-- so signal an IRQ...
-------------------------------------
irq <= '1';
end if;
pulse_count <= pulse_count + 1;
end if;
else
-------------------------------------------
-- Reset the width counter while waiting
-- for the HPD signal to fall.
-------------------------------------------
pulse_count <= (others => '0');
end if;
hpd_last <= hpd_synced;
hpd_synced <= hpd_meta1;
hpd_meta1 <= hpd_meta2;
hpd_meta2 <= hpd;
end if;
end process;
end architecture;
| mit | bd1358ff04a4626ad4486ee4b2bb3be9 | 0.457185 | 5.106464 | false | false | false | false |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd | 1 | 12,589 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (9 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(9 DOWNTO 0):= hex_to_std_logic_vector("0",10);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (42999 downto 0) of std_logic_vector(9 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(9 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
10,
43000);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>43000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 43000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| gpl-2.0 | 92b2134e1b3b3d9a3df3b90de972371a | 0.54778 | 3.677768 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/ipcore_dir/dualBRAM/simulation/bmg_stim_gen.vhd | 1 | 15,668 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(8,8);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(256,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(7 DOWNTO 0) <= WRITE_ADDR_A(7 DOWNTO 0);
READ_ADDR_INT_A(7 DOWNTO 0) <= READ_ADDR_A(7 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(7 DOWNTO 0) <= WRITE_ADDR_B(7 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(7 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(7 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>8,
DOUT_WIDTH => 8,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>8,
DOUT_WIDTH =>8 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;
| mit | 4b53947cfb8101e29754bb1353d2f993 | 0.574483 | 3.207369 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPrimitives/unitFIFO/hdl/FIFO-ea.vhd | 1 | 3,561 | -------------------------------------------------------------------------------
-- Title : FIFO
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : FIFO - memory
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FIFO is
generic (
data_width_g : natural := 24;
depth_g : natural := 128;
adr_width_g : natural := 8); -- log2(depth_g)
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
wr_i : in std_ulogic; -- write enable
rd_i : in std_ulogic; -- read enable
wr_data_i : in std_ulogic_vector(data_width_g-1 downto 0);
rd_data_o : out std_ulogic_vector(data_width_g-1 downto 0);
clear_i : in std_ulogic;
full_o : out std_ulogic;
empty_o : out std_ulogic;
-- used space
space_o : out unsigned(adr_width_g-1 downto 0)
);
end entity FIFO;
architecture Rtl of FIFO is
type mem_t is array (0 to depth_g-1) of std_ulogic_vector(data_width_g-1 downto 0);
signal memory : mem_t;
subtype ptr_t is natural range 0 to depth_g-1;
--signal rd_ptr, wr_ptr : ptr_t;
signal rd_ptr, wr_ptr : unsigned(adr_width_g-2 downto 0);
signal space : unsigned(adr_width_g-1 downto 0);
signal full, empty : std_ulogic;
signal rd_data : std_ulogic_vector(data_width_g-1 downto 0);
begin -- architecture Rtl
-- memory
wr_mem : process (clk_i) is
begin
if rising_edge(clk_i) then
if wr_i = '1' then
memory(to_integer(wr_ptr)) <= wr_data_i;
end if;
end if;
end process wr_mem;
rd_mem : process (clk_i) is
begin
if rising_edge(clk_i) then
rd_data <= memory(to_integer(rd_ptr));
end if;
end process rd_mem;
-- pointer logic
ptr_logic : process (clk_i, rst_i) is
variable used_space : unsigned(adr_width_g-1 downto 0) := to_unsigned(0, adr_width_g);
begin -- process ptr_logic
if rst_i = '0' then -- asynchronous reset (active low)
rd_ptr <= (others => '0');
wr_ptr <= (others => '0');
space <= to_unsigned(0, adr_width_g);
full <= '0';
empty <= '0';
elsif rising_edge(clk_i) then -- rising clock edge
if wr_i = '1' and full = '0' then
if wr_ptr = depth_g-1 then
wr_ptr <= (others => '0');
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
if rd_i = '1' and empty = '0' then
if rd_ptr = depth_g-1 then
rd_ptr <= (others => '0');
else
rd_ptr <= rd_ptr + 1;
end if;
end if;
if empty = '1' then
space <= (others => '0');
elsif empty = '0' then
space <= to_unsigned(0, space'length) + (wr_ptr - rd_ptr);
end if;
if wr_ptr = rd_ptr then
empty <= '1';
else
empty <= '0';
end if;
if wr_ptr = (rd_ptr - 1) then
full <= '1';
else
full <= '0';
end if;
if clear_i = '1' then
wr_ptr <= (others => '0');
rd_ptr <= (others => '0');
empty <= '1';
full <= '0';
end if;
end if;
end process ptr_logic;
-- output used space
space_o <= space;
empty_o <= empty;
full_o <= full;
-- if fifo is empty - read silence
rd_data_o <= rd_data when empty = '0'
else (others => '0') when empty = '1'
else (others => 'X');
end architecture Rtl;
| gpl-3.0 | a14576aea94475983d97d66be4e4f96a | 0.49312 | 3.331151 | false | false | false | false |
plessl/zippy | vhdl/flipflop.vhd | 1 | 2,132 | ------------------------------------------------------------------------------
-- Flip-Flops
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/flipflop.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/07
-- $Id: flipflop.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity FlipFlop is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end FlipFlop;
architecture simple of FlipFlop is
begin -- simple
FF : process (ClkxC, RstxRB)
begin -- process Reg
if RstxRB = '0' then -- asynchronous reset (active low)
DoutxDO <= '0';
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if EnxEI = '1' then
DoutxDO <= DinxDI;
end if;
end if;
end process FF;
end simple;
------------------------------------------------------------------------------
-- Flip-Flop with Clear
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity FlipFlop_Clr is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxEI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end FlipFlop_Clr;
architecture simple of FlipFlop_Clr is
begin -- simple
FF : process (ClkxC, RstxRB)
begin -- process Reg
if RstxRB = '0' then -- asynchronous reset (active low)
DoutxDO <= '0';
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if ClrxEI = '1' then -- clear has precedence
DoutxDO <= '0';
elsif EnxEI = '1' then
DoutxDO <= DinxDI;
end if;
end if;
end process FF;
end simple;
| bsd-3-clause | 7c679e02ca8c0ad271c79a9eddfb2c26 | 0.512664 | 3.547421 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/hdl/PlatformHps-e.vhd | 1 | 3,445 | library ieee;
use ieee.std_logic_1164.all;
entity PlatformHps is
port(
-- Clock
CLOCK_50 : in std_logic;
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- KEY
KEY : in std_logic_vector(3 downto 0);
-- Switches
SW : in std_logic_vector(9 downto 0);
--7SEG
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : in std_logic;
AUD_XCK : out std_logic;
-- GPIOs
GPIO_1_D2 : in std_logic;
GPIO_1_D3 : in std_logic;
GPIO_1_D4 : in std_logic;
GPIO_1_D5 : in std_logic;
GPIO_1_D6 : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0) := (others => 'X');
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0) := (others => 'X');
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0) := (others => 'X');
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_RZQ : in std_logic := 'X';
HPS_KEY : inout std_logic;
HPS_LED : inout std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity PlatformHps;
| gpl-3.0 | 8ec53c4a8adae50420a321459dfc9e88 | 0.573004 | 2.812245 | false | false | false | false |
plessl/zippy | vhdl/archConfigPkg.vhd | 1 | 2,270 | ------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
-- These are the default architecture parameters. A configuration is
-- expected to provide its own configuration for these parameters. As VHDL
-- does not support overriding of constants (or something similar) each
-- testbench in tb_arch provides its own modified copy of this file, and
-- the architecture is compiled from scratch within the tb_arch/xx
-- directory.
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
| bsd-3-clause | 9e21eac3fc19b89bc47e36d02e2545e4 | 0.57533 | 4.549098 | false | true | false | false |
rhalstea/cidr_15_fpga_join | probe_engine/vhdl/generic_fifo.vhd | 2 | 2,632 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Fall Through FIFO
entity generic_fifo is
generic (
DATA_WIDTH : natural := 8;
DATA_DEPTH : natural := 32;
AFULL_POS : natural := 24
);
port (
clk : in std_logic;
rst : in std_logic;
afull_out : out std_logic;
write_en_in : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
empty_out : out std_logic;
read_en_in : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_fifo;
architecture Behavioral of generic_fifo is
type FIFO_T is array (DATA_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory_s : FIFO_T;
signal push_pointer_s : natural;
signal pop_pointer_s : natural;
signal afull_s : std_logic;
signal empty_s : std_logic;
begin
-- Push element onto the FIFO
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
push_pointer_s <= 0;
elsif write_en_in = '1' then
memory_s(push_pointer_s) <= data_in;
if push_pointer_s >= DATA_DEPTH-1 then
push_pointer_s <= 0;
else
push_pointer_s <= push_pointer_s + 1;
end if;
end if;
end if;
end process;
-- Pop element from the FIFO
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
pop_pointer_s <= 0;
elsif read_en_in = '1' and empty_s = '0' then
if pop_pointer_s >= DATA_DEPTH-1 then
pop_pointer_s <= 0;
else
pop_pointer_s <= pop_pointer_s + 1;
end if;
end if;
end if;
end process;
empty_s <= '1' when push_pointer_s = pop_pointer_s else '0';
afull_s <= '1' when ((push_pointer_s > pop_pointer_s) and (push_pointer_s - pop_pointer_s > AFULL_POS)) or
((push_pointer_s < pop_pointer_s) and (DATA_DEPTH-1 - pop_pointer_s + push_pointer_s > AFULL_POS))
else '0';
empty_out <= empty_s;
afull_out <= afull_s;
data_out <= memory_s(pop_pointer_s);
end Behavioral;
| bsd-3-clause | 425fd53044f4c7efb1c68bd63e48f664 | 0.456307 | 3.859238 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/unitFIR/hdl/pkgFIR.vhd | 1 | 1,001 | library ieee;
use ieee.std_logic_1164.all;
--use ieee.fixed_pkg.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
package pkgFIR is
-- ************************************************************
-- filter constants
-- ************************************************************
--constant cOrder : natural := 16; -- maximum order of the filter
--constant cBitRange : natural := 24; -- bit range of input data
--*************************************************************
-- constants fro activating and deactivating std_ulogic flags
--*************************************************************
--constant cActivated : std_ulogic := '1';
--constant cInactivated : std_ulogic := '0';
--constant cnActivated : std_ulogic := '0';
--constant cnInactivated : std_ulogic := '1';
--type CoeffType is (TypeA, TypeB);
--typedef for coefficients (b[] = nominator, a[] = denominator)
--for a FIR only b[] is neccessary
end package; | gpl-3.0 | 7f5561d6d43818145fc04ddc4e9de93a | 0.521479 | 4.223629 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt_tpsched/tb_tstadpcm_virt_tpsched.vhd | 1 | 15,467 | ------------------------------------------------------------------------------
-- Testbench for the ADPCM configuration for the zippy array
--
-- Project :
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- URL : $URL: $
-- $Id: $
------------------------------------------------------------------------------
-- This testbench tests the ADPCM configuration for the zunit
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTADPCM_VIRT.all;
entity tb_tstadpcm_virt_tpsched is
end tb_tstadpcm_virt_tpsched;
architecture arch of tb_tstadpcm_virt_tpsched is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 1024; -- nr. of data elements
constant DELAY : integer := 2; -- processing delay of circuit,
-- due to pipeliningq
constant CONTEXTS : integer := 3;
type tbstatusType is (tbstart, idle, done, rst, wr_context0, wr_context1,
wr_context2, set_cmptr, set_virtctxtno, set_virtctxsched,
set_cntxt, start_scheduler,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
signal processSample : integer := -1;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration signals
signal Context0Cfg : engineConfigRec := tstadpcmcfg_p0;
signal Context1Cfg : engineConfigRec := tstadpcmcfg_p1;
signal Context2Cfg : engineConfigRec := tstadpcmcfg_p2;
signal Context0xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context0Cfg);
signal Context1xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context1Cfg);
signal Context2xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context2Cfg);
signal Context0Prt : cfgPartArray := partition_config(Context0xD);
signal Context1Prt : cfgPartArray := partition_config(Context1xD);
signal Context2Prt : cfgPartArray := partition_config(Context2xD);
file HFILE : text open write_mode is "tstadpcm_virt_tpsched_cfg.h";
-- set dumpResults to true if the response and the expected response
-- shall be dumped to HFILE for post simulation verification
-- (instead of doing the verification in the testbench)
signal dumpResults : boolean := false;
file RESFILE : text open write_mode is "tstadpcm_virt_tpsched_cfg.simout";
type fifo_array is array (0 to (3*NDATA)-1) of
std_logic_vector(DATAWIDTH-1 downto 0);
file TVFILE : text open read_mode is "test.adpcm.txt"; -- adpcm encoded
-- input file
file ERFILE : text open read_mode is "test.pcm.txt"; -- decoded file in
-- PCM format
begin -- arch
assert (N_COLS = 4) report "configuration requires N_COLS = 4" severity failure;
assert (N_ROWS = 4) report "configuration requires N_ROWS = 4" severity failure;
assert (N_HBUSN >= 2) report "configuration requires N_HBUSN >=2" severity failure;
assert (N_HBUSS >= 1) report "configuration requires N_HBUSS >=1" severity failure;
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
variable contextArr : contextPartArray :=
(others => (others => (others => '0')));
begin -- process hFileGen
contextArr(0) := Context0Prt;
contextArr(1) := Context1Prt;
contextArr(2) := Context2Prt;
-- need only 3 contexts
gen_contexthfile2(HFILE, contextArr);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable l : line;
variable tv : std_logic_vector(3 downto 0);
variable tvstring : string(tv'range);
variable expr : std_logic_vector(15 downto 0);
variable exprstring : string(expr'range);
variable tvcount : integer := 0;
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 0 (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_context0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in Context0Prt'low to Context0Prt'high loop
DataInxD <= Context0Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 1 (ZREG_CFGMEM1:W)
-- -----------------------------------------------
tbStatus <= wr_context1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM1, IFWIDTH));
for i in Context1Prt'low to Context1Prt'high loop
DataInxD <= Context1Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 2 (ZREG_CFGMEM2:W)
-- -----------------------------------------------
tbStatus <= wr_context2;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM2, IFWIDTH));
for i in Context2Prt'low to Context2Prt'high loop
DataInxD <= Context2Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
while not endfile(TVFILE) loop
readline(TVFILE, l);
read(l, tvstring);
tv := to_std_logic_vector(tvstring); -- defined in txt_util
DataInxD <= (others => '0');
DataInxD(3 downto 0) <= tv;
tvcount := tvcount + 1;
wait for CLK_PERIOD;
end loop;
assert false
report "Fill FIFO: " & str(tvcount) & " words written to FIFO0"
severity note;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- setup temporal partitioning scheduler
---------------------------------------------------------------------------
-- enable the temporal partitioning scheduler (ZREG_CONTEXTSCHEDSEL:W)
tbStatus <= set_virtctxsched;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CONTEXTSCHEDSEL, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
wait for CLK_PERIOD;
-- set the number of contexts (ZREG_VIRTCONTEXTNO:W)
tbStatus <= set_virtctxtno;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_VIRTCONTEXTNO, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(CONTEXTS, IFWIDTH));
wait for CLK_PERIOD;
-- write cycle count register (ZREG_CYCLECNT:W)
-- since this application uses the temporal partitioning scheduler
-- this number specifies the number of user-cycles
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NDATA+DELAY, IFWIDTH));
wait for CLK_PERIOD;
-- start temporal partitioning scheduler (ZREG_SCHEDSTART:W)
tbStatus <= start_scheduler;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_SCHEDSTART, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
wait for CLK_PERIOD;
-- run circuit with temporal partitioning
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for (NDATA+DELAY)*CONTEXTS*CLK_PERIOD;
-- idle cycle (not required)
tbStatus <= idle;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- pop DELAY words from out buffer (ZREG_FIFO1:R)
-- delay of circuit due to registers (pipelining)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for DELAY*CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO1:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
if dumpResults then
print(RESFILE, "result / expected result");
end if;
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
if not endfile(ERFILE) then
readline(ERFILE, l);
read(l, exprstring);
expr := to_std_logic_vector(exprstring);
else
expr := (others => '0');
end if;
expectedresponse := std_logic_vector(resize(signed(expr), DATAWIDTH));
response := DataOutxD(DATAWIDTH-1 downto 0);
if dumpResults then
print (RESFILE, str(to_integer(signed(response))) & " " &
str(to_integer(signed(expectedresponse))));
else
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end if;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | e60ec3452718e3385bffa65addfda270 | 0.503653 | 4.025768 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/artix7/gtx_tx_reset_controller.vhd | 1 | 7,776 | ----------------------------------------------------------------
-- Module Name: gtx_tx_reset_controller - Behavioral
--
-- Description: Controls the power-up and reset of a GTX
-- high speed Transceiver
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-17 | Syncrhonise txresetdone to remove timing errors
------------------------------------------------------------------------------------
----------------------------------------------------------------
-- Transceiver and channel PLL control
-- ===================================
--
-- 1. Initial reset state
-- Set GTTXRESET High,
-- Set GTTXPMARESET low
-- Set TXPCSRESET low.
-- Set CPLLPD high
-- Set GTRESETSEL low.
--
-- 2. Hold CPLLPD high until reference clock is seen on fabric
--
-- 3. Wait at least 500ns
--
-- 4. Start up the channel PLL
-- Drop CPLLPD
-- Assert CPLLLOCKEN
--
-- 5. Wait for CPLLLOCK to go high
--
-- 6. Start up the high speed transceiver
-- Assert GTTXUSERRDY
-- Drop GTTXRESET (you can use the CPLLLOCK signal is OK)
--
-- 7. Monitor GTTXRESETDONE until it goes high
--
-- The transceiver's TX Should then be operational.
--
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gtx_tx_reset_controller is
port ( clk : in std_logic;
ref_clk : in std_logic;
powerup_channel : in std_logic;
tx_running : out std_logic := '0';
txreset : out std_logic := '1';
txuserrdy : out std_logic := '0';
txpmareset : out std_logic := '1';
txpcsreset : out std_logic := '1';
pllpd : out std_logic := '1';
pllreset : out std_logic;
plllocken : out std_logic := '1';
plllock : in std_logic;
resetsel : out std_logic := '0';
txresetdone : in std_logic);
end entity;
architecture arch of gtx_tx_reset_controller is
signal state : std_logic_vector(3 downto 0) := x"0";
signal counter : unsigned(7 downto 0) := (others => '0');
signal ref_clk_counter : unsigned(7 downto 0) := (others => '0');
signal ref_clk_detect_last : std_logic := '0';
signal ref_clk_detect : std_logic := '0';
signal ref_clk_detect_meta : std_logic := '0';
signal txresetdone_meta : std_logic := '0';
signal txresetdone_i : std_logic := '0';
begin
process(ref_clk)
begin
if rising_edge(ref_clk) then
ref_clk_counter <= ref_clk_counter + 1;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
counter <= counter + 1;
case state is
when x"0" => -- reset state;
txreset <= '1';
txuserrdy <= '0';
txpmareset <= '0';
txpcsreset <= '0';
pllpd <= '1';
pllreset <= '1';
plllocken <= '0';
resetsel <= '0';
state <= x"1";
when x"1" => -- wait for reference clock
counter <= (others => '0');
if ref_clk_detect /= ref_clk_detect_last then
state <= x"2";
end if;
when x"2" => -- wait for 500ns
-- counter will set high bit after 128 cycles
if counter(counter'high) = '1' then
state <= x"3";
end if;
when x"3" => -- start up the PLL
pllpd <= '0';
pllreset <= '0';
plllocken <= '1';
state <= x"4";
when x"4" => -- Waiting for the PLL to lock
if plllock = '1' then
state <= x"5";
end if;
when x"5" => -- Starting up the GTX
txreset <= '0';
state <= x"6";
counter <= (others => '0');
when x"6" => -- wait for 500ns
-- counter will set high bit after 128 cycles
if counter(counter'high) = '1' then
state <= x"7";
end if;
when x"7" =>
txuserrdy <= '1';
if txresetdone_i = '1' then
state <= x"8";
end if;
when x"8" =>
tx_running <= '1';
when others => -- Monitoring for it to have started up;
state <= x"0";
end case;
if powerup_channel = '0' then
state <= x"0";
end if;
ref_clk_detect_last <= ref_clk_detect;
ref_clk_detect <= ref_clk_detect_meta;
ref_clk_detect_meta <= ref_clk_counter(ref_clk_counter'high);
txresetdone_i <= txresetdone_meta;
txresetdone_meta <= txresetdone;
end if;
end process;
end architecture;
| mit | 7895b1c5dfe83cd30c25979c0287412e | 0.467721 | 4.440891 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/neander.vhd | 1 | 8,408 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 09:49:46 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity neander is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
debug_out: out STD_LOGIC
);
end neander;
architecture Behavioral of neander is
component controlunit is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable_neander : in STD_LOGIC;
N : in STD_LOGIC;
Z : in STD_LOGIC;
execNOP, execSTA, execLDA, execADD, execOR, execSHR, execSHL, execMUL,
execAND, execNOT, execJMP, execJN, execJZ, execHLT : in STD_LOGIC;
sel_ula : out STD_LOGIC_VECTOR(2 downto 0);
loadAC : out STD_LOGIC;
loadPC : out STD_LOGIC;
loadREM : out STD_LOGIC;
loadRDM : out STD_LOGIC;
loadRI : out STD_LOGIC;
loadN : out STD_LOGIC;
loadZ : out STD_LOGIC;
wr_enable_mem : out STD_LOGIC_VECTOR (0 downto 0);
sel : out STD_LOGIC; -- mux_rem: 0 for PC, 1 for RDM
PC_inc : out STD_LOGIC;
sel_mux_RDM : out STD_LOGIC; -- mux_rdm: 0 for MEM, 1 for AC
stop : out STD_LOGIC
);
end component;
COMPONENT dualBRAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
component PC_register is
port (
clk : in std_logic;
rst : in std_logic;
cargaPC : in std_logic;
incrementaPC: in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component;
component mux is
port (
REG1 : in std_logic_vector(7 downto 0);
REG2 : in std_logic_vector(7 downto 0);
sel : in std_logic;
S : out std_logic_vector(7 downto 0)
);
end component;
component reg8bits is
port (
data_in : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
load : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component decoder is
port (
instruction_in : in STD_LOGIC_VECTOR (7 downto 0);
s_exec_NOP : out STD_LOGIC;
s_exec_STA : out STD_LOGIC;
s_exec_LDA : out STD_LOGIC;
s_exec_ADD : out STD_LOGIC;
s_exec_OR : out STD_LOGIC;
s_exec_SHR : out STD_LOGIC;
s_exec_SHL : out STD_LOGIC;
s_exec_MUL : out STD_LOGIC;
s_exec_AND : out STD_LOGIC;
s_exec_NOT : out STD_LOGIC;
s_exec_JMP : out STD_LOGIC;
s_exec_JN : out STD_LOGIC;
s_exec_JZ : out STD_LOGIC;
s_exec_HLT : out STD_LOGIC
);
end component;
component regNZ is
port (
N_in : in STD_LOGIC;
Z_in : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadN : in STD_LOGIC;
loadZ : in STD_LOGIC;
N_out : out STD_LOGIC;
Z_out : out STD_LOGIC
);
end component;
component ula is
Port (
X : in STD_LOGIC_VECTOR (7 downto 0);
Y : in STD_LOGIC_VECTOR (7 downto 0);
selector : in STD_LOGIC_VECTOR (2 downto 0);
N : out STD_LOGIC;
Z : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (7 downto 0);
carryMUL : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
-------------------------
-- PROGRAM SIGNALS
-------------------------
-- operation signal
signal exec_NOP : STD_LOGIC;
signal exec_STA : STD_LOGIC;
signal exec_LDA : STD_LOGIC;
signal exec_ADD : STD_LOGIC;
signal exec_OR : STD_LOGIC;
signal exec_SHR : STD_LOGIC;
signal exec_SHL : STD_LOGIC;
signal exec_MUL : STD_LOGIC;
signal exec_AND : STD_LOGIC;
signal exec_NOT : STD_LOGIC;
signal exec_JMP : STD_LOGIC;
signal exec_JN : STD_LOGIC;
signal exec_JZ : STD_LOGIC;
signal exec_HLT : STD_LOGIC;
-- load signals
signal AC_load : STD_LOGIC;
signal N_load : STD_LOGIC;
signal Z_load : STD_LOGIC;
signal RI_load : STD_LOGIC;
signal REM_load : STD_LOGIC;
signal RDM_load : STD_LOGIC;
signal PC_load : STD_LOGIC;
-- ULA
signal ULA_selector : STD_LOGIC_VECTOR (2 downto 0);
signal ULA_N : STD_LOGIC;
signal ULA_Z : STD_LOGIC;
signal ULA_output : STD_LOGIC_VECTOR (7 downto 0);
signal ULA_carryMUL : STD_LOGIC_VECTOR (7 downto 0);
-- AC
signal AC_output : STD_LOGIC_VECTOR (7 downto 0);
-- NZ
signal NZ_outputN : STD_LOGIC;
signal NZ_outputZ : STD_LOGIC;
-- RI
signal RI_output : STD_LOGIC_VECTOR (7 downto 0);
-- RDM
signal RDM_output : STD_LOGIC_VECTOR (7 downto 0);
-- REM
signal REM_output : STD_LOGIC_VECTOR (7 downto 0);
-- MPX
signal MPX_output : STD_LOGIC_VECTOR (7 downto 0);
signal MPX_sel : STD_LOGIC;
-- MUX para o RDM
signal muxrdm_output : STD_LOGIC_VECTOR (7 downto 0);
signal muxrdm_sel : STD_LOGIC;
-- PC
signal PC_increment : STD_LOGIC;
signal PC_output : STD_LOGIC_VECTOR (7 downto 0);
-- MEM
signal wr_enable : STD_LOGIC_VECTOR (0 downto 0);
signal MEM_output : STD_LOGIC_VECTOR (7 downto 0);
signal MEM_output2 : STD_LOGIC_VECTOR (7 downto 0);
begin
AC: reg8bits
port map (
data_in => ULA_output, clk => clk, rst => rst, load => AC_load, data_out => AC_output
);--
RI: reg8bits
port map (
data_in => RDM_output, clk => clk, rst => rst, load => RI_load, data_out => RI_output
);--
R_E_M: reg8bits
port map (
data_in => MPX_output, clk => clk, rst => rst, load => REM_load, data_out => REM_output
);
R_D_M: reg8bits
port map (
data_in => muxrdm_output, clk => clk, rst => rst, load => RDM_load, data_out => RDM_output
);--
NZ : regNZ
port map (
N_in => ULA_N, Z_in => ULA_Z, clk => clk, rst => rst, loadN => N_load, loadZ => Z_load,
N_out => NZ_outputN, Z_out => NZ_outputZ
);--
alu: ula
port map (
X => AC_output, Y => RDM_output, selector => ULA_selector, N => ULA_N, Z => ULA_Z, output => ULA_output, carryMUL => ULA_carryMUL
);--
dec: decoder
port map (
instruction_in => RI_output,
s_exec_NOP => exec_NOP, s_exec_STA => exec_STA, s_exec_LDA => exec_LDA,
s_exec_ADD => exec_ADD, s_exec_OR => exec_OR, s_exec_SHR => exec_SHR,
s_exec_SHL => exec_SHL, s_exec_MUL => exec_MUL, s_exec_AND => exec_AND,
s_exec_NOT => exec_NOT, s_exec_JMP => exec_JMP,
s_exec_JN => exec_JN, s_exec_JZ => exec_JZ, s_exec_HLT => exec_HLT
);--
mpx: mux
port map ( -- mpx: 0 for PC, 1 for RDM
REG1 => PC_output, REG2 => RDM_output, sel => MPX_sel, S => MPX_output
);--
mux_rdm: mux
port map ( -- mux_rdm: 0 for MEM, 1 for AC
REG1 => MEM_output, REG2 => AC_output, sel => muxrdm_sel, S => muxrdm_output
);
PC: PC_register
port map (
clk => clk, rst => rst, cargaPC => PC_load,
incrementaPC => PC_increment, data_in => RDM_output, data_out => PC_output
);--
CU: controlunit
port map (
clk => clk, rst => rst, enable_neander => enable, N => NZ_outputN, Z => NZ_outputZ,
-- operation signals
execNOP => exec_NOP, execSTA => exec_STA, execLDA => exec_LDA,
execADD => exec_ADD, execOR => exec_OR, execSHR => exec_SHR,
execSHL => exec_SHL, execMUL => exec_MUL, execAND => exec_AND,
execNOT => exec_NOT, execJMP => exec_JMP, execJN => exec_JN,
execJZ => exec_JZ, execHLT => exec_HLT,
sel_ula => ULA_selector,
loadAC => AC_load , loadPC => PC_load, loadREM => REM_load,
loadRDM => RDM_load, loadRI => RI_load,
loadN => N_load , loadZ => Z_load,
wr_enable_mem => wr_enable,
sel => MPX_sel, PC_inc => PC_increment,
sel_mux_RDM => muxrdm_sel, stop => debug_out
);
MEM : dualBRAM
PORT MAP (
clka => clk,
wea => wr_enable,
addra => REM_output,
dina => RDM_output,
douta => MEM_output,
clkb => clk,
web => "0",
addrb => "00000000",
dinb => "00000000",
doutb => MEM_output2
);
end Behavioral;
| mit | 29f78566e6a64728709b89d07fdc7fe2 | 0.591817 | 2.774917 | false | false | false | false |
plessl/zippy | vhdl/schedulectrl.vhd | 1 | 3,750 | ------------------------------------------------------------------------------
-- Schedule controller; implemented as a Mealy FSM
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/schedulectrl.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-16
-- $Id: schedulectrl.vhd 242 2005-04-07 09:17:51Z plessl $
------------------------------------------------------------------------------
-- The schedule controller implements the sequencing of the contexts. The
-- sequence is specified in the context sequence program store (see Rolfs PhD
-- thesis pp 77ff).
--
-- The controller stays in idle mode, until the sequencing is
-- acitvated (StartxEI = '1'). After activation it switches to the
-- first context and executes it (run state) until the number of
-- execution cycles for this context has been reached (RunningSI =
-- '0'). If the last context has been executed (LastxSI=0) the
-- scheduler is stopped, otherwise the scheduler switches to the next
-- context as specified with the next address field in the instruction
-- word.
--
-- FIXME: Maybe the switch context state could be removed, thus the
-- context could be switched in a single cycle. While this doesn't
-- make much of a difference in performance when contexts are executed
-- for many cycles, it makes a differenece when the context has to be switched
-- every cycle, which is the case for certain virtualization modes.
--
-- FIXME: The sequencer could be extended to provide a little more microcode
-- features. E.g. the ability to run a certain schedule repeatedly.
--
-- FIXME: Rolf mentioned something about status flags, that can be polled from
-- CPUs. What flags can be polled?
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ScheduleCtrl is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
StartxEI : in std_logic;
RunningxSI : in std_logic;
LastxSI : in std_logic;
SwitchxEO : out std_logic; -- initiate context switch
BusyxSO : out std_logic); -- busy status flag
end ScheduleCtrl;
architecture simple of ScheduleCtrl is
type state is (idle, switch, run);
signal currstate : state;
signal nextstate : state;
begin -- simple
--
-- computation of next state and current outputs
--
process (LastxSI, RunningxSI, StartxEI, currstate)
begin -- process
-- default assignments
nextstate <= currstate;
SwitchxEO <= '0';
BusyxSO <= '0';
-- non-default transitions and current outputs
case currstate is
when idle =>
if StartxEI = '1' then
SwitchxEO <= '1';
BusyxSO <= '1';
nextstate <= switch;
end if;
when switch =>
BusyxSO <= '1';
nextstate <= run;
when run =>
BusyxSO <= '1';
if (RunningxSI = '0') and (LastxSI = '0') then
SwitchxEO <= '1';
nextstate <= switch;
elsif (RunningxSI = '0') and (LastxSI = '1') then
nextstate <= idle;
end if;
-- have all parasitic states flow into idle state
when others =>
nextstate <= idle;
end case;
end process;
--
-- updating of state
--
process (ClkxC, RstxRB)
begin -- process
if RstxRB = '0' then -- asynchronous reset (active low)
currstate <= idle;
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
currstate <= nextstate;
end if;
end process;
end simple;
| bsd-3-clause | fd67dbec9e177eaa90df14b110d12c86 | 0.604533 | 4.027927 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/hdl/PlatformHps-Struct-a.vhd | 1 | 15,059 | architecture Struct of PlatformHps is
-- qsys component
component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
dds_left_strobe_export : in std_logic := 'X'; -- export
dds_right_strobe_export : in std_logic := 'X'; -- export
hex0_2_export : out std_logic_vector(20 downto 0); -- export
hex3_5_export : out std_logic_vector(20 downto 0); -- export
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic; -- SCLK
keys_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
xck_clk : out std_logic; -- clk
i2s_codec_iadcdat : in std_logic := 'X'; -- iadcdat
i2s_codec_iadclrc : in std_logic := 'X'; -- iadclrc
i2s_codec_ibclk : in std_logic := 'X'; -- ibclk
i2s_codec_idaclrc : in std_logic := 'X'; -- idaclrc
i2s_codec_odacdat : out std_logic; -- odacdat
i2s_gpio_iadcdat : in std_logic := 'X'; -- iadcdat
i2s_gpio_iadclrc : in std_logic := 'X'; -- iadclrc
i2s_gpio_ibclk : in std_logic := 'X'; -- ibclk
i2s_gpio_idaclrc : in std_logic := 'X'; -- idaclrc
strobe_export : out std_logic; -- export
white_noise_left_strobe_export : in std_logic := 'X'; -- export
white_noise_right_strobe_export : in std_logic := 'X'; -- export
i2s_gpio_odacdat : out std_logic -- odacdat
);
end component Platform;
signal hex0_2, hex3_5 : std_logic_vector(20 downto 0);
signal keys_p : std_logic_vector(2 downto 0);
signal sample_strobe : std_ulogic;
begin -- architecture Struct
-- hex
HEX0 <= not hex0_2(6 downto 0);
HEX1 <= not hex0_2(13 downto 7);
HEX2 <= not hex0_2(20 downto 14);
HEX3 <= not hex3_5(6 downto 0);
HEX4 <= not hex3_5(13 downto 7);
HEX5 <= not hex3_5(20 downto 14);
--keys
keys_p <= not KEY(3 downto 1);
-- qsys system
u0 : component Platform
port map (
clk_clk => CLOCK_50, -- clk.clk
i2c_SDAT => FPGA_I2C_SDAT, -- i2c.SDAT
i2c_SCLK => FPGA_I2C_SCLK, -- .SCLK
i2s_codec_iadcdat => AUD_ADCDAT, -- CODEC I2S Interface
i2s_codec_iadclrc => AUD_ADCLRCK,
i2s_codec_ibclk => AUD_BCLK,
i2s_codec_idaclrc => AUD_DACLRCK,
i2s_codec_odacdat => AUD_DACDAT,
i2s_gpio_iadcdat => GPIO_1_D2, -- GPIO I2S Interface
i2s_gpio_iadclrc => GPIO_1_D3,
i2s_gpio_ibclk => GPIO_1_D4,
i2s_gpio_idaclrc => GPIO_1_D5,
i2s_gpio_odacdat => GPIO_1_D6,
keys_export => keys_p, -- keys.export
leds_export => LEDR, -- leds.export
memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a
memory_mem_ba => HPS_DDR3_BA, -- .mem_ba
memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck
memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n
memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke
memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n
memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n
memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n
memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n
memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n
memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq
memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs
memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n
memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt
memory_mem_dm => HPS_DDR3_DM, -- .mem_dm
memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin
reset_reset_n => KEY(0), -- reset.reset_n
switches_export => SW, -- switches.export
xck_clk => AUD_XCK, -- xck.clk
hps_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_io_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_io_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_io_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_io_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_io_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_io_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL,
hps_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT,
hps_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK,
hps_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT,
hps_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK,
hps_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_io_hps_io_gpio_inst_GPIO54 => HPS_KEY,
hps_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
hex0_2_export => hex0_2,
hex3_5_export => hex3_5,
dds_left_strobe_export => sample_strobe,
dds_right_strobe_export => sample_strobe,
strobe_export => sample_strobe,
white_noise_left_strobe_export => sample_strobe,
white_noise_right_strobe_export => sample_strobe
);
end architecture Struct;
| gpl-3.0 | ee0fc18a9f44830bd10e621068332794 | 0.497377 | 2.789737 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/top_level.vhd | 1 | 13,601 | ----------------------------------------------------------------------------------
-- Module Name: top_level - Behavioral
--
-- Description: Top level of my DisplayPort design.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-29 | Updated for Opsis
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top_level is
port (
clk100 : in std_logic;
debug : out std_logic_vector(7 downto 0) := (others => '0');
------------------------------
gtptxp : out std_logic_vector(1 downto 0);
gtptxn : out std_logic_vector(1 downto 0);
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
------------------------------
dp_tx_hp_detect : in std_logic;
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic
);
end top_level;
architecture Behavioral of top_level is
constant use_hw_8b10b_support : std_logic := '1'; -- Note HW 8b/10b not yet working for SPartan 6
COMPONENT channel_management
PORT(
clk100 : IN std_logic;
debug : out std_logic_vector(7 downto 0);
hpd : IN std_logic;
stream_channel_count : IN std_logic_vector(2 downto 0);
source_channel_count : IN std_logic_vector(2 downto 0);
tx_clock_train : out std_logic;
tx_align_train : out std_logic;
tx_running : IN std_logic_vector(3 downto 0);
aux_tx_p : INOUT std_logic;
aux_tx_n : INOUT std_logic;
aux_rx_p : INOUT std_logic;
aux_rx_n : INOUT std_logic;
tx_powerup_channel : OUT std_logic_vector(3 downto 0);
tx_preemp_0p0 : OUT std_logic;
tx_preemp_3p5 : OUT std_logic;
tx_preemp_6p0 : OUT std_logic;
tx_swing_0p4 : OUT std_logic;
tx_swing_0p6 : OUT std_logic;
tx_swing_0p8 : OUT std_logic;
tx_link_established : OUT std_logic
);
END COMPONENT;
component test_source is
port (
clk : in std_logic;
stream_channel_count : out std_logic_vector(2 downto 0);
ready : out std_logic;
data : out std_logic_vector(72 downto 0)
);
end component;
COMPONENT main_stream_processing
generic( use_hw_8b10b_support : std_logic);
PORT(
symbol_clk : IN std_logic;
tx_link_established : IN std_logic;
source_ready : IN std_logic;
tx_clock_train : IN std_logic;
tx_align_train : IN std_logic;
in_data : IN std_logic_vector(72 downto 0);
tx_symbols : OUT std_logic_vector(79 downto 0)
);
END COMPONENT;
component Transceiver is
generic( use_hw_8b10b_support : std_logic);
Port ( mgmt_clk : in STD_LOGIC;
powerup_channel : in STD_LOGIC_vector;
debug : out std_logic_vector(7 downto 0);
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
swing_0p4 : in STD_LOGIC;
swing_0p6 : in STD_LOGIC;
swing_0p8 : in STD_LOGIC;
tx_running : out STD_LOGIC_vector;
symbolclk : out STD_LOGIC;
in_symbols : in std_logic_vector(79 downto 0);
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
gtptxp : out std_logic_vector(1 downto 0);
gtptxn : out std_logic_vector(1 downto 0));
end component;
component video_generator is
Port ( clk : in STD_LOGIC;
h_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
h_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
h_front_len : in std_logic_vector(11 downto 0) := (others => '0');
h_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
v_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
v_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
v_front_len : in std_logic_vector(11 downto 0) := (others => '0');
v_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
vid_blank : out STD_LOGIC;
vid_hsync : out STD_LOGIC;
vid_vsync : out STD_LOGIC);
end component;
--------------------------------------------------------------------------
signal tx_powerup : std_logic := '0';
signal tx_clock_train : std_logic := '0';
signal tx_align_train : std_logic := '0';
---------------------------------------------
-- Transceiver signals
---------------------------------------------
signal txresetdone : std_logic := '0';
signal txoutclk : std_logic := '0';
signal symbolclk : std_logic := '0';
signal tx_running : std_logic_vector(3 downto 0) := (others => '0');
signal tx_powerup_channel : std_logic_vector(3 downto 0);
signal tx_preemp_0p0 : std_logic := '1';
signal tx_preemp_3p5 : STD_LOGIC := '0';
signal tx_preemp_6p0 : STD_LOGIC := '0';
signal tx_swing_0p4 : STD_LOGIC := '1';
signal tx_swing_0p6 : STD_LOGIC := '0';
signal tx_swing_0p8 : STD_LOGIC := '0';
------------------------------------------------
signal tx_link_established : std_logic := '0';
------------------------------------------------
signal tx_debug : std_logic_vector(7 downto 0);
signal mgmt_debug:std_logic_vector(7 downto 0);
constant source_channel_count : std_logic_vector(2 downto 0) := "010";
signal stream_channel_count : std_logic_vector(2 downto 0) := "000";
signal test_signal_ready : std_logic;
signal msa_merged_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
signal tx_symbols : std_logic_vector(79 downto 0) := (others => '0');
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
begin
i_channel_management: channel_management PORT MAP(
clk100 => clk100,
debug => mgmt_debug,
hpd => dp_tx_hp_detect,
aux_tx_p => dp_tx_aux_p,
aux_tx_n => dp_tx_aux_n,
aux_rx_p => dp_rx_aux_p,
aux_rx_n => dp_rx_aux_n,
stream_channel_count => stream_channel_count,
source_channel_count => source_channel_count,
tx_clock_train => tx_clock_train,
tx_align_train => tx_align_train,
tx_powerup_channel => tx_powerup_channel,
tx_preemp_0p0 => tx_preemp_0p0,
tx_preemp_3p5 => tx_preemp_3p5,
tx_preemp_6p0 => tx_preemp_6p0,
tx_swing_0p4 => tx_swing_0p4,
tx_swing_0p6 => tx_swing_0p6,
tx_swing_0p8 => tx_swing_0p8,
tx_running => tx_running,
tx_link_established => tx_link_established
);
i_test_source: test_source port map (
clk => symbolclk,
stream_channel_count => stream_channel_count,
ready => test_signal_ready,
data => msa_merged_data
);
----------------------------------------------------------------------
Inst_main_stream_processing: main_stream_processing generic map (
use_hw_8b10b_support => use_hw_8b10b_support
) PORT MAP(
symbol_clk => symbolclk,
tx_link_established => tx_link_established,
source_ready => test_signal_ready,
tx_clock_train => tx_clock_train,
tx_align_train => tx_align_train,
in_data => msa_merged_data,
tx_symbols => tx_symbols
);
i_tx0: Transceiver generic map (
use_hw_8b10b_support => use_hw_8b10b_support
) Port map (
mgmt_clk => clk100,
powerup_channel => tx_powerup_channel,
tx_running => tx_running,
debug => tx_debug,
preemp_0p0 => tx_preemp_0p0,
preemp_3p5 => tx_preemp_3p5,
preemp_6p0 => tx_preemp_6p0,
swing_0p4 => tx_swing_0p4,
swing_0p6 => tx_swing_0p6,
swing_0p8 => tx_swing_0p8,
in_symbols => tx_symbols,
gtptxp => gtptxp,
gtptxn => gtptxn,
symbolclk => symbolclk,
refclk0_p => refclk0_p,
refclk0_n => refclk0_n,
refclk1_p => refclk1_p,
refclk1_n => refclk1_n);
-- debug(0) <= tx_link_established;
debug(0) <= mgmt_debug(0);
-- debug(0) <= tx_clock_train;
--process(symbolclk)
-- begin
--
-- -- SHow the HBLANK as a debug of the video stream.
-- if rising_edge(symbolclk) then
-- -- Look for BS symbols
-- if sr_inserted_data(8 downto 0) = "110111100" or sr_inserted_data(17 downto 9) = "110111100" then
-- debug(0) <= toggle and tx_link_established; --'1';
-- toggle <= not toggle;
-- end if;
-- -- Look for BE symbols
-- if sr_inserted_data(8 downto 0) = "111111011" or sr_inserted_data(17 downto 9) = "111111011" then
-- debug(0) <= toggle and tx_link_established; --'0';
-- toggle <= not toggle;
-- end if;
-- end if;
-- end process;
--process(gclk)
-- begin
-- if rising_edge(gclk) then
-- count <= count + 1;
-- case count(10 downto 8) is
-- when "000" => debug(0) <= not count(7);
-- when "001" => debug(0) <= tx_debug(0);
-- when "010" => debug(0) <= tx_debug(1);
-- when "011" => debug(0) <= tx_debug(2);
-- when "100" => debug(0) <= tx_debug(3);
-- when "101" => debug(0) <= tx_debug(4);
-- when "110" => debug(0) <= tx_debug(5);
-- when others => debug(0) <= tx_debug(6);
-- end case;
-- end if;
-- end process;
end Behavioral;
| mit | 21a7b06af06b8c8c1c90d7943bd900ab | 0.486802 | 3.628869 | false | false | false | false |
plessl/zippy | vhdl/engclearctrl.vhd | 1 | 3,145 | ------------------------------------------------------------------------------
-- Engine clear controller; implemented as a Mealy FSM
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/engclearctrl.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-18
-- $Id: engclearctrl.vhd 242 2005-04-07 09:17:51Z plessl $
------------------------------------------------------------------------------
-- FIXME: purpose of this code is not entierly clear to me
--
-- If a context switch is initiated via the registerface, the state of a
-- context can be either reset (cleared) or retained (store). This controller
-- performs the clearing or storing of state, when the context sequencer is used.
--
-- decmode: decode mode (idle?)
-- storemode: store state of current context on context switch
-- clearmode: clear state of context at context switch
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity EngClearCtrl is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
DecEngClrxEI : in std_logic;
SchedStartxEI : in std_logic;
SchedSwitchxEI : in std_logic;
SchedBusyxSI : in std_logic;
SchedEngClrxSI : in std_logic;
EngClrxEO : out std_logic);
end EngClearCtrl;
architecture simple of EngClearCtrl is
type state is (decmode, schedstoremode, schedclearmode);
signal currstate : state;
signal nextstate : state;
begin -- simple
--
-- computation of next state and current outputs
--
process (DecEngClrxEI, SchedBusyxSI, SchedEngClrxSI, SchedStartxEI,
SchedSwitchxEI, currstate)
begin -- process
-- default assignments
nextstate <= currstate;
EngClrxEO <= DecEngClrxEI;
-- non-default transitions and current outputs
case currstate is
when decmode =>
if SchedStartxEI = '1' then
if SchedEngClrxSI = '0' then
EngClrxEO <= '0';
nextstate <= schedstoremode;
else
EngClrxEO <= SchedSwitchxEI;
nextstate <= schedclearmode;
end if;
end if;
when schedstoremode =>
if SchedBusyxSI = '1' then
EngClrxEO <= '0';
else
nextstate <= decmode;
end if;
when schedclearmode =>
if SchedBusyxSI = '1' then
EngClrxEO <= SchedSwitchxEI;
else
nextstate <= decmode;
end if;
when others => -- take care of parasitic states
nextstate <= decmode;
end case;
end process;
--
-- updating of state
--
process (ClkxC, RstxRB)
begin -- process
if RstxRB = '0' then -- asynchronous reset (active low)
currstate <= decmode;
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
currstate <= nextstate;
end if;
end process;
end simple;
| bsd-3-clause | a5a2041ba3bdd974fa635e47b45874b9 | 0.572973 | 3.89715 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstfir8_virt/tstfir8_virt_cfg.vhd | 1 | 14,595 | ------------------------------------------------------------------------------
-- Library of ZUnit FIR filter configurations
--
-- Project :
-- File : cfglib_fir.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/21
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- library of FIR filter configurations for the 4x4 zippy array, as used in
-- a couple of case studies (ERSA,FPL,Micpro,Rolfs PhD thesis)
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-08 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_FIR is
type coeffArray is array (natural range <>) of integer;
function fir8mult (coeff : coeffArray) return engineConfigRec;
function fir8mult_b (coeff : coeffArray) return engineConfigRec;
end CfgLib_FIR;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_FIR is
-----------------------------------------------------------------------------
-- FIXME
-----------------------------------------------------------------------------
--
-- This configuration library needs to be validated with a testbench again,
-- since quite a lot of things have changed in the zippy architecture.
--
-- The 4tap FIR filters have been removed and moved to their own testbench
-- tstfir4. The fir8shif configuration has also been removed.
--
-- The coordinate system of the engine has been changed from Rolfs scheme
--
-- |A3|A2|A1|A0|
-- |B3|B2|B1|B0|
-- |C3|C2|C1|C0|
-- |D3|D2|D1|D0|
--
-- to a more commonly used scheme
--
-- |00|01|02|03|
-- |10|11|12|13|
-- |20|21|22|23|
-- |30|31|32|33|
--
--
-- This implies, that the configurations need to be mirrored on a vertical
-- axis, which was done, but has not been verified so far.
----------------------------------------------------------------------------
-- 8-tap FIR filter
----------------------------------------------------------------------------
-- Changed:
-- old order of coefficients: (k7,k6,k5,k4,k3,k2,k1,k0)
-- new order of coefficients: (k0,k1,k2,k3,k4,k5,k6,k7)
--
function fir8mult (coeff : coeffArray) return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin -- fir8mult
-- row 0 multiplies:
for i in 0 to 3 loop
cfg.gridConf(0)(i).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(i).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(i).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(i).procConf.AluOpxS := ALU_OP_MULTLO;
-- last 4 coefficients of impulse response
cfg.gridConf(0)(i).procConf.ConstOpxD :=
std_logic_vector(to_signed(coeff(7-i), DATAWIDTH));
cfg.gridConf(0)(i).routConf.i(0).HBusNxE(0) := '1'; -- hbusn_0.0 (inport 0)
end loop;
---------------------------------------------------------------------------
-- row 1 adds:
---------------------------------------------------------------------------
-- c_1_1
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_REG;
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(1).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(1).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_NW) := '1'; -- NW neighb.
cfg.gridConf(1)(1).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
-- c_1_2
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(2).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
-- c_1_3
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(3).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(3).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(1)(3).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
cfg.gridConf(1)(3).routConf.o.HBusNxE(0) := '1'; -- hbusn_2.0
-------------------------------------------------------------------------------
-- row 2 adds:
-------------------------------------------------------------------------------
-- c_2_0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(0).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(0).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(0).routConf.i(0).HBusNxE(0) := '1'; -- hbusn_2.0
cfg.gridConf(2)(0).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
-- c_2_1
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(1).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(1).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(1).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
-- c_2_2
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(2).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(2).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(2)(2).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
-- c_2_3
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(3).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(2)(3).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
cfg.gridConf(2)(3).routConf.o.HBusNxE(1) := '1'; -- hbusn_3.1 (oport 1)
-- row 3 multiplies:
for i in 0 to 3 loop
cfg.gridConf(3)(i).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(i).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(i).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(i).procConf.AluOpxS := ALU_OP_MULTLO;
-- first 4 coefficients of impulse response
cfg.gridConf(3)(i).procConf.ConstOpxD :=
std_logic_vector(to_signed(coeff(3-i), DATAWIDTH));
cfg.gridConf(3)(i).routConf.i(0).HBusNxE(0) := '1'; -- hbusn_0.0 (inport 0)
end loop;
---------------------------------------------------------------------------
-- engine inputs and outputs
---------------------------------------------------------------------------
-- engine input
cfg.inputDriverConf(0)(0)(0) := '1'; -- hbusn_0.0
cfg.inputDriverConf(0)(3)(0) := '1'; -- hbusn_3.0
-- engine outputs
cfg.outputDriverConf(1)(3)(1) := '1'; -- output hbusn_3.1 to OUTP1
-- IP0 controller (activated)
cfg.inportConf(0).LUT4FunctxD := X"FFFF";
-- IP1 controller (deactivated)
cfg.inportConf(1).LUT4FunctxD := X"0000";
-- OP0 controller (deactivated)
cfg.outportConf(0).LUT4FunctxD := X"0000";
-- OP1 controller (activated)
cfg.outportConf(1).LUT4FunctxD := X"FFFF";
return cfg;
end fir8mult;
----------------------------------------------------------------------------
-- 8-tap FIR filter (2nd version)
----------------------------------------------------------------------------
-- input on inport 1; output on outport 0
function fir8mult_b (coeff : coeffArray) return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin -- fir8mult_b
---------------------------------------------------------------------------
-- row 0 multiplies:
---------------------------------------------------------------------------
for i in 0 to 3 loop
cfg.gridConf(0)(i).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(i).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(i).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(i).procConf.AluOpxS := ALU_OP_MULTLO;
cfg.gridConf(0)(i).procConf.ConstOpxD :=
std_logic_vector(to_signed(coeff(7-i), DATAWIDTH));
cfg.gridConf(0)(i).routConf.i(0).HBusNxE(0) := '1'; -- hbusn_0.0 (inport 1)
end loop; -- i
---------------------------------------------------------------------------
-- row 1 adds:
---------------------------------------------------------------------------
-- c_1_1
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_REG;
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(1).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(1).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_NW) := '1'; -- NW neighb.
cfg.gridConf(1)(1).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
-- c_1_2
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(2).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
-- c_1_3
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(3).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(3).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(1)(3).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
cfg.gridConf(1)(3).routConf.o.HBusNxE(0) := '1'; -- hbusn_2.0
---------------------------------------------------------------------------
-- row 2 adds:
---------------------------------------------------------------------------
-- c_2_0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(0).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(0).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(0).routConf.i(0).HBusNxE(0) := '1'; -- hbusn_3.0
cfg.gridConf(2)(0).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
-- c_2_1
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(1).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(1).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(1).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
-- c_2_2
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(2).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(2).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(2)(2).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
-- c_2_3
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(2)(3).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(2)(3).routConf.i(1).LocalxE(LOCAL_S) := '1'; -- S neighb.
cfg.gridConf(2)(3).routConf.o.HBusNxE(1) := '1'; -- hbusn_3.1 (oport 0)
---------------------------------------------------------------------------
-- row 3 multiplies:
---------------------------------------------------------------------------
for i in 0 to 3 loop
cfg.gridConf(3)(i).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(i).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(i).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(i).procConf.AluOpxS := ALU_OP_MULTLO;
cfg.gridConf(3)(i).procConf.ConstOpxD :=
std_logic_vector(to_signed(coeff(i), DATAWIDTH));
cfg.gridConf(3)(i).routConf.o.HBusNxE(0) := '1'; -- hbusn_0.0 (inport 1)
end loop;
---------------------------------------------------------------------------
-- engine inputs and outputs
---------------------------------------------------------------------------
-- engine input
cfg.inputDriverConf(1)(0)(0) := '1'; -- hbusn_0.0
cfg.inputDriverConf(1)(3)(0) := '1'; -- hbusn_3.0
-- engine outputs
cfg.outputDriverConf(0)(3)(1) := '1'; -- hbusn_3.1
-- IP0 controller (deactivated)
cfg.inportConf(0).LUT4FunctxD := X"0000";
-- IP1 controller (activated)
cfg.inportConf(1).LUT4FunctxD := X"FFFF";
-- OP0 controller (activated)
cfg.outportConf(0).LUT4FunctxD := X"FFFF";
-- OP1 controller (deactivated)
cfg.outportConf(1).LUT4FunctxD := X"0000";
return cfg;
end fir8mult_b;
end CfgLib_FIR;
| bsd-3-clause | dcef94168b0787f2b52360b0b29feda6 | 0.477903 | 3.177662 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_engine.vhd | 1 | 20,400 | ------------------------------------------------------------------------------
-- Testbench for engine.vhd
--
-- Project :
-- File : tb_engine.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/02
-- Last changed: $LastChangedDate: 2004-10-29 17:42:55 +0200 (Fri, 29 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_FIR.all;
entity tb_Engine is
end tb_Engine;
architecture arch of tb_Engine is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, pass_const, addu, fir4shft_cfg,
fir4shft_pulse, fir4shft_square, fir4shft_inputs,
fir8shft_cfg, fir8shft_pulse, fir8shft_square,
fir8shft_inputs, fir4mult_cfg, fir4mult_pulse,
fir4mult_square, fir4mult_inputs, fir8mult_cfg,
fir8mult_pulse, fir8mult_square, fir8mult_inputs,
ip0_en, ip1_en, op0_en, op1_en);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxAB : std_logic := '1';
signal CExE : std_logic := '1';
signal Cfg : engineConfigRec;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0) := (others => '0');
signal InPort0xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal InPort1xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal OutPort0xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal OutPort1xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal CycleDnCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal CycleUpCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal InPort0xE : std_logic;
signal InPort1xE : std_logic;
signal OutPort0xE : std_logic;
signal OutPort1xE : std_logic;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Engine
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxABI => ClrxAB,
CExEI => CExE,
ConfigxI => Cfg,
ContextxSI => ContextxS,
CycleDnCntxDI => CycleDnCntxD,
CycleUpCntxDI => CycleUpCntxD,
InPort0xDI => InPort0xD,
InPort1xDI => InPort1xD,
OutPort0xDO => OutPort0xD,
OutPort1xDO => OutPort1xD,
InPort0xEO => InPort0xE,
InPort1xEO => InPort1xE,
OutPort0xEO => OutPort0xE,
OutPort1xEO => OutPort1xE);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
Cfg <= init_engineConfig;
InPort0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
InPort1xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
--------------------------------------------------------------------------
-- TEST I/O PORT ENABLES
--------------------------------------------------------------------------
tbStatus <= ip0_en;
Cfg.inport0Conf.LUT4FunctxD <= X"FFFF";
Cfg.inport1Conf.LUT4FunctxD <= X"0000";
Cfg.outport0Conf.LUT4FunctxD <= X"0000";
Cfg.outport1Conf.LUT4FunctxD <= X"0000";
wait for CLK_PERIOD;
tbStatus <= ip1_en;
Cfg.inport0Conf.LUT4FunctxD <= X"0000";
Cfg.inport1Conf.LUT4FunctxD <= X"FFFF";
Cfg.outport0Conf.LUT4FunctxD <= X"0000";
Cfg.outport1Conf.LUT4FunctxD <= X"0000";
wait for CLK_PERIOD;
tbStatus <= op0_en;
Cfg.inport0Conf.LUT4FunctxD <= X"0000";
Cfg.inport1Conf.LUT4FunctxD <= X"0000";
Cfg.outport0Conf.LUT4FunctxD <= X"FFFF";
Cfg.outport1Conf.LUT4FunctxD <= X"0000";
wait for CLK_PERIOD;
tbStatus <= op1_en;
Cfg.inport0Conf.LUT4FunctxD <= X"0000";
Cfg.inport1Conf.LUT4FunctxD <= X"0000";
Cfg.outport0Conf.LUT4FunctxD <= X"0000";
Cfg.outport1Conf.LUT4FunctxD <= X"FFFF";
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_engineConfig;
InPort0xD <= (others => '0');
InPort1xD <= (others => '0');
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- EXPERIMENT 1
--------------------------------------------------------------------------
-- each cell passes its constant op (= cell no. +100) to its output
-- engine outputs A0 and D1, resp.
tbStatus <= pass_const;
for r in 0 to N_ROWS-1 loop
for c in 0 to N_COLS-1 loop
Cfg.gridConf(r)(c).procConf.Op0MuxS <= "10";
Cfg.gridConf(r)(c).procConf.Op1MuxS <= "00";
Cfg.gridConf(r)(c).procConf.OutMuxS <= '0';
Cfg.gridConf(r)(c).procConf.AluOpxS <= alu_pass0;
Cfg.gridConf(r)(c).procConf.ConstOpxD <=
std_logic_vector(to_unsigned(r*N_COLS+c+100, DATAWIDTH));
Cfg.gridConf(r)(c).routConf.Route0MuxS <= O"0";
Cfg.gridConf(r)(c).routConf.Route1MuxS <= O"0";
end loop; -- c
end loop; -- r
Cfg.gridConf(1)(0).routConf.Tri0OExE <= '1'; -- B0 tristate output
Cfg.gridConf(3)(1).routConf.Tri1OExE <= '1'; -- D1 tristate output
Cfg.Out0MuxS <= O"2"; -- output B0 via HBus_BC0
Cfg.Out1MuxS <= O"7"; -- output D1 via HBus_DA1
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_engineConfig;
InPort0xD <= (others => '0');
InPort1xD <= (others => '0');
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- EXPERIMENT 2
--------------------------------------------------------------------------
-- addition: C2 = B2 + B1 -> output 0
tbStatus <= addu;
-- config B2
Cfg.gridConf(1)(2).procConf.Op0MuxS <= "00";
Cfg.gridConf(1)(2).procConf.AluOpxS <= alu_pass0;
Cfg.gridConf(1)(2).routConf.Route0MuxS <= "001"; -- HBus_AB1 (inport 1)
Cfg.gridConf(1)(2).routConf.Tri0OExE <= '0';
Cfg.gridConf(1)(2).routConf.Tri1OExE <= '0';
Cfg.gridConf(1)(2).routConf.Tri2OExE <= '0';
-- config B1
Cfg.gridConf(1)(1).procConf.Op0MuxS <= "00";
Cfg.gridConf(1)(1).procConf.AluOpxS <= alu_pass0;
Cfg.gridConf(1)(1).routConf.Route0MuxS <= "000"; -- HBus_AB0 (inport 0)
Cfg.gridConf(1)(1).routConf.Tri0OExE <= '0';
Cfg.gridConf(1)(1).routConf.Tri1OExE <= '1'; -- HBus_BC1 (outport 1)
Cfg.gridConf(1)(1).routConf.Tri2OExE <= '0';
-- config C2
Cfg.gridConf(2)(2).procConf.Op0MuxS <= "00"; -- input
Cfg.gridConf(2)(2).procConf.Op0MuxS <= "00"; -- input
Cfg.gridConf(2)(2).procConf.AluOpxS <= alu_addu;
Cfg.gridConf(2)(2).routConf.Route0MuxS <= "110"; -- north neighbour
Cfg.gridConf(2)(2).routConf.Route1MuxS <= "101"; -- NE neighbour
Cfg.gridConf(2)(2).routConf.Tri0OExE <= '1'; -- HBus_CD0 (outport 0)
Cfg.gridConf(2)(2).routConf.Tri1OExE <= '0';
Cfg.gridConf(2)(2).routConf.Tri2OExE <= '0';
-- engine input
Cfg.Inp0OExE(2) <= '1'; -- HBus_AB0
Cfg.Inp1OExE(3) <= '1'; -- HBus_AB1
-- engine output
Cfg.Out0MuxS <= O"4"; -- output C2 via HBus_CD0
Cfg.Out1MuxS <= O"3"; -- output B1 via HBus_BC1
-- inputs
InPort0xD <= std_logic_vector(to_unsigned(22, DATAWIDTH));
InPort1xD <= std_logic_vector(to_unsigned(33, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(3, DATAWIDTH));
InPort1xD <= std_logic_vector(to_unsigned(14, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(15, DATAWIDTH));
InPort1xD <= std_logic_vector(to_unsigned(22, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_engineConfig;
InPort0xD <= (others => '0');
InPort1xD <= (others => '0');
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- EXPERIMENT 3
--------------------------------------------------------------------------
-- 4-tap FIR filter
tbStatus <= fir4shft_cfg;
Cfg <= fir4shift;
InPort0xD <= (others => '0');
wait for CLK_PERIOD;
-- EXPERIMENT 3A ---------------------------------------------------------
-- 4-tap FIR filter: pulse response
tbStatus <= fir4shft_pulse;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*6;
-- EXPERIMENT 3B ---------------------------------------------------------
-- 4-tap FIR filter: square response
tbStatus <= fir4shft_square;
-- inputs
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*6;
-- EXPERIMENT 3C ---------------------------------------------------------
-- 4-tap FIR filter: inputs
tbStatus <= fir4shft_inputs;
-- inputs
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(36, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(44, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(32, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(48, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*6;
tbStatus <= idle;
Cfg <= init_engineConfig;
InPort0xD <= (others => '0');
InPort1xD <= (others => '0');
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- EXPERIMENT 4
--------------------------------------------------------------------------
-- 8-tap FIR filter
tbStatus <= fir8shft_cfg;
Cfg <= fir8shift;
InPort0xD <= (others => '0');
wait for CLK_PERIOD;
-- EXPERIMENT 4A ---------------------------------------------------------
-- 8-tap FIR filter: pulse response
tbStatus <= fir8shft_pulse;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*9;
-- EXPERIMENT 4B ---------------------------------------------------------
-- 8-tap FIR filter: square response
tbStatus <= fir8shft_square;
-- inputs
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*10;
-- EXPERIMENT 4C ---------------------------------------------------------
-- 8-tap FIR filter: inputs
tbStatus <= fir8shft_inputs;
-- inputs
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(72, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(88, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(64, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(96, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(88, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(72, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(72, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(88, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(64, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(96, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(88, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(72, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(80, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*9;
tbStatus <= idle;
Cfg <= init_engineConfig;
InPort0xD <= (others => '0');
InPort1xD <= (others => '0');
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- EXPERIMENT 5
--------------------------------------------------------------------------
-- 4-tap FIR filter (with arbitrary coefficients)
tbStatus <= fir4mult_cfg;
Cfg <= fir4mult((2, -2, -1, 1));
InPort0xD <= (others => '0');
wait for CLK_PERIOD;
-- EXPERIMENT 5A ---------------------------------------------------------
-- 4-tap FIR filter: pulse response
tbStatus <= fir4mult_pulse;
InPort0xD <= std_logic_vector(to_signed(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*6;
-- EXPERIMENT 5B ---------------------------------------------------------
-- 4-tap FIR filter: square response
tbStatus <= fir4mult_square;
-- inputs
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*6;
tbStatus <= idle;
Cfg <= init_engineConfig;
InPort0xD <= (others => '0');
InPort1xD <= (others => '0');
wait for CLK_PERIOD;
--------------------------------------------------------------------------
-- EXPERIMENT 6
--------------------------------------------------------------------------
-- 8-tap FIR filter (with arbitrary coefficients)
tbStatus <= fir8mult_cfg;
Cfg <= fir8mult((-1, 1, 4, 8, 8, 4, 1, -1));
-- Cfg <= fir8mult((-18979, 12237, 76169, 131070, 131070, 76169, 12237, -18979));
InPort0xD <= (others => '0');
wait for CLK_PERIOD;
-- EXPERIMENT 6A ---------------------------------------------------------
-- 8-tap FIR filter: pulse response
tbStatus <= fir8mult_pulse;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*10;
-- EXPERIMENT 6B ---------------------------------------------------------
-- 8-tap FIR filter: square response
tbStatus <= fir8mult_square;
-- inputs
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*10;
-- EXPERIMENT 6C ---------------------------------------------------------
-- 8-tap FIR filter: inputs
tbStatus <= fir8mult_inputs;
-- inputs
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(2, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(4, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(3, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(2, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(5, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(2, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(1, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(4, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(4, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(3, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(5, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(2, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= std_logic_vector(to_signed(3, DATAWIDTH));
wait for CLK_PERIOD;
InPort0xD <= (others => '0');
wait for CLK_PERIOD*10;
tbStatus <= done;
Cfg <= init_engineConfig;
InPort0xD <= (others => '0');
InPort1xD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 93724c8b4f6bc4510806bd66340c5f47 | 0.537451 | 3.525143 | false | false | false | false |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd | 1 | 9,970 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3
-- C_XDEVICEFAMILY : spartan3
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 10
-- C_READ_WIDTH_A : 10
-- C_WRITE_DEPTH_A : 43000
-- C_READ_DEPTH_A : 43000
-- C_ADDRA_WIDTH : 16
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 10
-- C_READ_WIDTH_B : 10
-- C_WRITE_DEPTH_B : 43000
-- C_READ_DEPTH_B : 43000
-- C_ADDRB_WIDTH : 16
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-2.0 | 88cbf3b5bcf1749f60786504d07ef169 | 0.495386 | 3.770802 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstpass_virt/tstpass_virt_cfg.vhd | 1 | 4,294 | ------------------------------------------------------------------------------
--
-- Id : $Id: $
-- File : $Url: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/27
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTPASS_VIRT is
function tstpasscfg_p0 return engineConfigRec;
function tstpasscfg_p1 return engineConfigRec;
end CfgLib_TSTPASS_VIRT;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTPASS_VIRT is
----------------------------------------------------------------------------
-- tstpass partition p0 configuration
----------------------------------------------------------------------------
function tstpasscfg_p0 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- c_0_0 op0
cfg.gridConf(0)(0).procConf.AluOpxS := ALU_OP_ADD;
-- i.0
cfg.gridConf(0)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(0)(0).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(1).LocalxE(LOCAL_S) := '1';
-- o.0
cfg.gridConf(0)(0).procConf.OutMuxS := O_NOREG;
-- c_0_1 opt01
cfg.gridConf(0)(1).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- o.0
--cfg.gridConf(0)(1).procConf.OpMuxS(0) := O_REG_CTX_THIS;
-- superfluous, result is registered anyway. ??
-- none, transfer register from ctx0 to ctx1
-- c_1_0 opt10
--cfg.gridConf(0)(1).procConf.AluOpxS := alu_pass0;
-- i.0
-- none, transfer register from ctx1 to ctx0
-- o.0
cfg.gridConf(1)(0).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(1)(0).procConf.OutCtxRegSelxS := i2ctx(1);
-- input drivers
cfg.inputDriverConf(0)(0)(0) := '1';
-- output drivers
-- none
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_ON;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstpasscfg_p0;
----------------------------------------------------------------------------
-- tstpass partition p1 configuration
----------------------------------------------------------------------------
function tstpasscfg_p1 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- c_0_1 opt01
-- i.0
-- none transfer from ctx0 to ctx1
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(0)(1).procConf.OutCtxRegSelxS := i2ctx(0);
-- drive hbusn_1.0, which is connected to outport
cfg.gridConf(0)(1).routConf.o.HBusNxE(0) := '1';
-- c_1_0 opt10
cfg.gridConf(1)(0).procConf.AluOpxS := ALU_OP_PASS0;
-- i.0
cfg.gridConf(1)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- o.0
-- none, transfer register from ctx1 to ctx0
-- input drivers
-- none
-- output drivers
cfg.outputDriverConf(1)(1)(0) := '1';
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_ON;
return cfg;
end tstpasscfg_p1;
end CfgLib_TSTPASS_VIRT;
| bsd-3-clause | 32daeb713b47796165c7473a7877ba35 | 0.504891 | 3.448996 | false | true | false | false |
ASP-SoC/ASP-SoC | libASP/grpPrimitives/unitFIFO/hdl/FIFO_tb.vhd | 1 | 2,515 | -------------------------------------------------------------------------------
-- Title : FIFO - testbench
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : FIFO - memory with overflow overwrite bhv
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity FIFO_tb is
end entity FIFO_tb;
-------------------------------------------------------------------------------
architecture Bhv of FIFO_tb is
-- component generics
constant data_width_g : natural := 4;
constant depth_g : natural := 8;
constant adr_width_g : natural := 3;
-- component ports
signal rst_i : std_ulogic;
signal wr_i : std_ulogic;
signal rd_i : std_ulogic;
signal wr_data_i : std_ulogic_vector(data_width_g-1 downto 0);
signal rd_data_o : std_ulogic_vector(data_width_g-1 downto 0);
signal space_o : unsigned(adr_width_g-1 downto 0);
signal empty_o : std_ulogic;
signal full_o : std_ulogic;
signal clear_i : std_ulogic;
-- clock
signal Clk : std_ulogic := '1';
begin -- architecture Bhv
-- component instantiation
DUT : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => depth_g,
adr_width_g => adr_width_g)
port map (
clk_i => Clk,
rst_i => rst_i,
wr_i => wr_i,
rd_i => rd_i,
wr_data_i => wr_data_i,
rd_data_o => rd_data_o,
clear_i => clear_i,
empty_o => empty_o,
full_o => full_o,
space_o => space_o);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
rst_i <= '0' after 0 ns,
'1' after 40 ns;
clear_i <= '0' after 0 ns,
'1' after 200 ns;
wr_i <= '0';
rd_i <= '0';
wr_data_i <= "0000";
wait for 100 ns;
wait until rising_edge(Clk);
wr_data_i <= "0001";
wr_i <= '1';
wait until rising_edge(Clk);
wr_i <= '0';
wr_data_i <= "----";
wait for 100 ns;
wait until rising_edge(Clk);
rd_i <= '1';
wait until rising_edge(Clk);
rd_i <= '0';
wait;
end process WaveGen_Proc;
end architecture Bhv;
-------------------------------------------------------------------------------
| gpl-3.0 | 6089dda6617a9fb339c94746d424da51 | 0.446918 | 3.787651 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/unitAudioCodecAvalon/hdl/AudioCodecAvalon-Struct-a.vhd | 1 | 1,073 | architecture Struct of AudioCodecAvalon is
begin -- architecture Struct
-- Avalon ST to I2S
AvalonSTToI2S_1 : entity work.AvalonSTToI2S
generic map (
gDataWidth => gDataWidth,
gDataWidthLen => gDataWidthLen)
port map (
iClk => csi_clk,
inReset => rsi_reset_n,
iLRC => AUD_DACLRCK,
iBCLK => AUD_BCLK,
oDAT => AUD_DACDAT,
iLeftData => asi_left_data,
iLeftValid => asi_left_valid,
iRightData => asi_right_data,
iRightValid => asi_right_valid);
-- I2S to Avalon ST
I2SToAvalonST_1 : entity work.I2SToAvalonST
generic map (
gDataWidth => gDataWidth,
gDataWidthLen => gDataWidthLen)
port map (
iClk => csi_clk,
inReset => rsi_reset_n,
iDAT => AUD_ADCDAT,
iLRC => AUD_ADCLRCK,
iBCLK => AUD_BCLK,
oLeftData => aso_left_data,
oLeftValid => aso_left_valid,
oRightData => aso_right_data,
oRightValid => aso_right_valid);
end architecture Struct;
| gpl-3.0 | 158aabb8436cb1ae6056edf867c571cf | 0.572227 | 3.529605 | false | false | false | false |
plessl/zippy | vhdl/fifo.vhd | 1 | 7,971 | ------------------------------------------------------------------------------
-- FIFO with fill level status output
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/fifo.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/25
-- $Id: fifo.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- FIFO: Data at RdDataxDO is not registered but a direct combinational
-- result of the read address RdAddrxDI.
-- The FIFO uses separate read and write address ports and data ports
--
-- The FIFO provides the followign status flags:
-- EmptyxSO FIFO is empty
-- FullxSO FIFO is full
-- FillLevelxDO Number of words in FIFO
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- FIFO memory block (1 read port / 1 write port)
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
entity FifoMem is
generic (
WIDTH : integer;
DEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
WrAddrxDI : in std_logic_vector(log2(DEPTH)-1 downto 0);
WrDataxDI : in std_logic_vector(WIDTH-1 downto 0);
RdAddrxDI : in std_logic_vector(log2(DEPTH)-1 downto 0);
RdDataxDO : out std_logic_vector(WIDTH-1 downto 0));
end FifoMem;
architecture simple of FifoMem is
type memArray is array (DEPTH-1 downto 0) of
std_logic_vector(WIDTH-1 downto 0);
signal MemBlock : memArray;
begin -- simple
RdDataxDO <= MemBlock(to_integer(unsigned(RdAddrxDI)));
WriteMemBlock : process (ClkxC, RstxRB)
begin
if RstxRB = '0' then
for i in MemBlock'range loop
MemBlock(i) <= (others => '0');
end loop;
elsif ClkxC'event and ClkxC = '1' then
if WExEI = '1' then
MemBlock(to_integer(unsigned(WrAddrxDI))) <= WrDataxDI;
end if;
end if;
end process WriteMemBlock;
end simple;
-----------------------------------------------------------------------------
-- FIFO
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.AuxPkg.all;
entity Fifo is
generic (
WIDTH : integer;
DEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
RExEI : in std_logic;
DinxDI : in std_logic_vector(WIDTH-1 downto 0);
DoutxDO : out std_logic_vector(WIDTH-1 downto 0);
EmptyxSO : out std_logic;
FullxSO : out std_logic;
FillLevelxDO : out std_logic_vector(log2(DEPTH) downto 0));
end Fifo;
architecture simple of Fifo is
component FifoMem
generic (
WIDTH : integer;
DEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
WrAddrxDI : in std_logic_vector(log2(DEPTH)-1 downto 0);
WrDataxDI : in std_logic_vector(WIDTH-1 downto 0);
RdAddrxDI : in std_logic_vector(log2(DEPTH)-1 downto 0);
RdDataxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
signal ReadPtrxD : std_logic_vector(log2(DEPTH)-1 downto 0);
signal WritePtrxD : std_logic_vector(log2(DEPTH)-1 downto 0);
signal FillLevelxD : unsigned(log2(DEPTH) downto 0);
signal MemOutxD : std_logic_vector(WIDTH-1 downto 0);
signal EmptyxS : std_logic;
signal FullxS : std_logic;
signal ReadCondxS : std_logic; -- read condition status
signal WriteCondxS : std_logic; -- write condition status
signal ClearxE : std_logic;
begin -- simple
FMem : FifoMem
generic map (
WIDTH => WIDTH,
DEPTH => DEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WriteCondxS,
WrAddrxDI => WritePtrxD,
WrDataxDI => DinxDI,
RdAddrxDI => ReadPtrxD,
RdDataxDO => MemOutxD);
OutReg : Reg_clr_en
generic map (
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxEI => ClearxE,
EnxEI => ReadCondxS,
DinxDI => MemOutxD,
DoutxDO => DoutxDO);
ReadPtr : process (ClkxC, RstxRB)
begin
if RstxRB = '0' then -- asynchronous reset (active low)
ReadPtrxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if (ReadCondxS = '1') then
ReadPtrxD <= std_logic_vector(unsigned(ReadPtrxD) + 1);
end if;
end if;
end process ReadPtr;
WritePtr : process (ClkxC, RstxRB)
begin
if RstxRB = '0' then -- asynchronous reset (active low)
WritePtrxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if (WriteCondxS = '1') then
WritePtrxD <= std_logic_vector(unsigned(WritePtrxD) + 1);
end if;
end if;
end process WritePtr;
FillLevel : process (ClkxC, RstxRB)
begin
if RstxRB = '0' then -- asynchronous reset (active low)
FillLevelxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if (ReadCondxS = '1') and (WriteCondxS = '0') then -- read
FillLevelxD <= FillLevelxD - 1;
end if;
if (WriteCondxS = '1') and (ReadCondxS = '0') then -- write
FillLevelxD <= FillLevelxD + 1;
end if;
-- if read/write: do nothing
end if;
end process FillLevel;
-- combinational logic
EmptyxS <= '1' when (FillLevelxD = 0) else '0';
FullxS <= FillLevelxD(FillLevelxD'high);
ReadCondxS <= '1' when (RExEI = '1' and EmptyxS = '0') else '0';
WriteCondxS <= '1' when (WExEI = '1' and FullxS = '0') else '0';
-- Previous versions used a very strange implementation of the FIFO, which
-- did explicitly reset the FIFO output register after a word was read. Now
-- the FIFO output remains constant until a new word is requested.
--
-- ClearxE <= not ReadCondxS;
--
-- NOTE:
-- Be aware that the new word is available only with one cycle of delay due
-- to the register. While this is not a problem for single context
-- configuration where a word is read from the FIFO in every cycle,
-- difficulties arise for virtualized circuits: If the first context requests
-- a new word, the word is available only in the next cycle, thus context 0
-- operates on the old value of the FIFO, where subsequent contexts operate
-- on the next FIFO value. This leads to problems, if a primary output (FIFO
-- output) is read be other contexts than the first context, since the
-- contexts operate not on the same primary input in that case!
--
-- This problem can be solved, if the last (instead of the first) context is
-- requesting a new word from the FIFO. Like this, the last context operates
-- still on the 'last' FIFO output value, while the new FIFO output will be
-- available when context 0 is activated.
--
ClearxE <= '0';
-- outputs
FullxSO <= FullxS;
EmptyxSO <= EmptyxS;
FillLevelxDO <= std_logic_vector(FillLevelxD);
Observe : process (ClkxC)
begin
if ClkxC'event and ClkxC = '1' then -- rising clock edge
-- read on empty
assert (RExEI = '1') nand (EmptyxS = '1')
report "read request on empty FIFO"
severity warning;
-- write on full
assert (WExEI = '1') nand (FullxS = '1')
report "write request on full FIFO"
severity warning;
end if;
end process Observe;
end simple;
| bsd-3-clause | bc806e05766b0e25288c7d134389470d | 0.585121 | 3.686864 | false | false | false | false |
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