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viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II | ProgramaVHDL/serialinterface.vhd | 2 | 10,731 | --#############################################################################
--
-- Controlador de interface serial com autobaud - versão sem CTS nem RTS!
--
-- Descrição:
-- Trata-se de uma implementação full-duplex de um controlador de
-- interface serial que pode se adaptar à velocidade de transmissão
-- do periférico. Ele interage com um processador via handshake assíncrono
-- de comunicação, também chamado aqui hospedeiro ou host. A interface
-- com o host é de 8 bits, também full-duplex.
-- Operação:
-- Após a inicialização do controlador (via reset), o periférico deve
-- mandar o dado 0x55 (equivalente a 01010101 em binário) na sua velocidade.
-- Este valor habilita a interface a ajustar sua velocidade àquela do
-- periférico. A velocidade do host não é controlada mas tipicamente deve
-- ser bem mais alta que esta, tal como 30MHz/50MHz/100MHz ou até mais alta.
-- A interface opera com o relógio do host.
-- Assume-se aqui que a velocidade do periférico será tipicamente entre
-- 1.200 e 115.200 bits por segundo (ou qualquer velocidade entre estas,
-- em múltiplos de 1.200 bps) a faixa de velocidades de uma interface serial
-- típica.
-- Observações:
-- Nada é assumido sobre a necessidade de sincronizar o relógio do host
-- e do periférico.
--
-- Sinais da Interface
-- clock -- clock
-- reset -- reset (ativo em 1)
--
-- rxd -- envia dados pela serial
-- txd -- dados vindos da serial
--
-- tx_data -- barramento que contem o byte que vem do pc
-- tx_av -- indica que existe um dado disponivel no tx_data
--
-- rx_data -- byte a ser transmitido para o pc
-- rx_start -- indica byte disponivel no rx_data (ativo em 1)
-- rx_busy -- fica em '1' enquando envia ao PC (do rx_start ao fim)
--
-- +------------------+
-- | SERIAL |<---- clock
-- | +--------+ |<---- reset
-- TXD | | | |
-- --------->| |=========> tx_data (8bits)
-- | | SENDER | |
-- | | |---------> tx_av
-- | | | |
-- Lado | +--------+ | Lado
-- Periférico | | Hospedeiro
-- | +--------+ |
-- | | | |
-- RXD | | |<========== rx_data (8bits)
-- <---------|RECEIVER|<---------- rx_start
-- | | |----------> rx_busy
-- | | | |
-- | +--------+ |
-- +------------------+
--
-- Revisado por Fernando Moraes em 20/maio/2002
-- Alterado por Ney Calazans em Ago/2017
--
--#############################################################################
--*****************************************************************************
-- Módulo de interface com periférico serial
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity serialinterface is
port(
clock: in std_logic;
reset: in std_logic;
rxd: out std_logic;
txd: in std_logic;
rx_data: in std_logic_vector (7 downto 0);
rx_start: in std_logic;
rx_busy: out std_logic;
tx_data: out std_logic_vector (7 downto 0);
tx_av: out std_logic
);
end serialinterface;
architecture serialinterface of serialinterface is
-- sinais do circuito autobaud
type Sreg_type is (S1, S2, S3, S4, S5);
signal Sreg : Sreg_type; -- Esta é a saída do registrador de estado da MEF autobaud
signal ctr0 : STD_LOGIC_VECTOR(16 downto 0); -- conta o número de clocks do
-- hospedeiro durante os 4 primeiros tempos em que txd está em 0 durante a
-- transmissão de um dado de aferição (0x55) pelo periférico
signal PUpEdgeCt : STD_LOGIC_VECTOR (1 downto 0); -- conta o número de bordas de subida
-- durante a transmissão de um dado de aferição (0x55) pelo periférico
-- sinais de geracao do clock da serial
signal host_cycles : STD_LOGIC_VECTOR(13 downto 0);
signal counter : STD_LOGIC_VECTOR(13 downto 0);
signal serial_clk: STD_LOGIC;
-- sinais de recepção
signal word, busy: STD_LOGIC_VECTOR (8 downto 0);
signal go : STD_LOGIC;
-- sinais de transmissão
signal regin : STD_LOGIC_VECTOR(9 downto 0); -- 10 bits: start/byte/stop
signal resync, r : STD_LOGIC;
begin
--*****************************************************************************
-- MEF Autobaud: Inicialmente, o periférico deve enviar 55H (0101 0101) para
-- esta MEF. Esta conta quantos pulsos de clock 'cabem' em cada '0'.
-- Logo, conta-se 4 vezes. Para se obter o semi-período, divide-se a
-- contagem obtida no estado S5 por 8 (oito).
--
-- Atenção: Note-se que a ordem de envio dos bits é do bit menos significativo
-- (bit 0 da palavra) para o mais significativo (bit 7).
--*****************************************************************************
Autobaud_FSM: process (reset, clock)
begin
if Reset = '1' then
Sreg <= S1; -- Estado inicial da máquina de autobaud é S1
PUpEdgeCt <= "00"; -- Contador de bordas de subida em txd inicia com 0
host_cycles <= (OTHERS=>'0'); -- host_cycles é calculado pelo autobaud
ctr0 <=(OTHERS=>'0'); -- é o contador de clocks que cabem em quatro
-- tempos de 0 bit
elsif clock'event and clock = '1' then
case Sreg is
when S1 => if txd = '0' then -- a primeira descida de txd é o start bit,
Sreg <= S2; -- que dispara o cálculo da MEF autobaud
ctr0 <= (OTHERS=>'0');
end if;
when S2 => ctr0 <= ctr0 + 1; -- Incrementa o número de pulsos de clock
-- do host que vem do periférico durante a transmissão
-- do dado de aferição (0x55)
if txd = '1' then
Sreg <= S3;
PUpEdgeCt <= PUpEdgeCt + '1';
end if;
when S3 => if PUpEdgeCt /= "00" and txd = '0' then
Sreg <= S2;
elsif PUpEdgeCt = "00" and txd = '0' then
Sreg <= S4;
end if;
when S4 => if txd = '1' then -- espera em S4 até aparecer o stop bit (txd='1')
Sreg <= S5; -- Quando isto acontece MEF autobaud concluiu.
end if;
when S5 => Sreg <= S5; -- Em S5, armazena o número de ciclos contados
host_cycles <= ctr0(16 downto 3); -- dividido por 8
end case;
end if;
end process;
--*****************************************************************************
-- SENDER
--*****************************************************************************
-- Processo de envio de dados do periférico ao hospedeiro.
-- Sinais: txd (periférico) e tx_data e tx_av (hospedeiro)
-- Registrador de deslocamento de 10 bits que lê o dado vindo da serial.
process (resync, serial_clk)
begin
if resync = '1' then
regin <= (others=>'1'); -- inicializa todos os bits do registrador com '1'
elsif serial_clk'event and serial_clk='1' then
regin <= txd & regin(9 downto 1); -- bit vindo do periférico
-- entra pela esquerda do registrador de deslocamento
end if;
end process;
-- O processo abaixo detecta o start bit, gerando o sinal de resincronismo
-- resync. O sinal host_cycles em 0 funciona como um reset do processo.
process (clock, host_cycles)
begin
if host_cycles=0 then
r <= '0';
resync <= '1';
tx_data <= (others=>'0'); -- zera os 8 bits de tx_data
tx_av <= '0';
elsif clock'event and clock='1' then
if r='0' and txd='0' then --- start bit
r <= '1';
resync <= '1';
tx_av <= '0';
elsif r='1' and regin(0)='0' then --- start bit chegou no último bit
r <= '0';
tx_data <= regin(8 downto 1); -- tx_data recebe os bits de dados recebidos
tx_av <= '1'; -- ativa o sinal de dado discponível
else
resync <= '0';
tx_av <= '0';
end if;
end if;
end process;
--*****************************************************************************
-- RECEIVER - Sinais rxd (periférico), rx_data, rx_start, rx_busy (hospedeiro)
--*****************************************************************************
-- Processo de geração do clock para a transmissão serial (serial_clk).
-- De tempos em tempos este é resincronizado, para ajuste da recepção
-- dos dados provenientes do hospedeiro.
process(resync, clock)
begin
if resync='1' then
counter <= (0=>'1', others=>'0'); -- escreve 1 em counter
serial_clk <='0'; -- ressincroniza o clock da serial
elsif clock'event and clock='0' then
if counter = host_cycles then -- aguarda que se passem host_cycles
serial_clk <= not serial_clk; -- gera borda sincronizada
counter <= (0=>'1', others=>'0'); -- escreve 1 em counter
else
counter <= counter + 1; -- maior parte das vezes passa aqui
end if;
end if;
end process;
-- Registrador de deslocamento - fica colocando '1' na linha de dados.
-- Quando o usuário requer dados (pulso em rx_start) coloca-se o start bit e o
-- byte a ser transmitido
process(rx_start, reset, serial_clk)
begin
if rx_start='1' or reset='1' then
go <= rx_start ;
rx_busy <= rx_start ;
word <= (others=>'1'); -- todos os 9 bits em '1' inicialmente
busy <= (others=>'0'); -- busy, inicialmente livre p/ receber 9 bits
elsif serial_clk'event and serial_clk ='1' then
go <= '0'; -- desce o go um ciclo depois
if go='1' then
word <= rx_data & '0'; -- armazena o byte que é enviado à serial
busy <= (8=>'0', others=>'1');
else
word <= '1' & word(8 downto 1); -- desloca para a esquerda word
busy <= '0' & busy(8 downto 1); -- e busy
rx_busy <= busy(0); -- rx_busy fica ocupado enquanto enviando start e bits
-- de dados
end if;
end if;
end process;
rxd <= word(0); -- bit de saída, que vai para o periférico. Pode mudar a cada
-- borda de serial_clk
end serialinterface; | mit | dc237954a6c727b0add37c338c9a6573 | 0.511043 | 3.719584 | false | false | false | false |
willtmwu/vhdlExamples | Project/project_nrf_subprogV2.vhd | 1 | 7,317 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package project_nrf_subprogV2 is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Char HEX constants, must be 0-9 and/or lower case a-f. For internal subprog use for now
constant CHAR_0_i : STD_LOGIC_VECTOR(7 downto 0) := x"30";
constant CHAR_9_i : STD_LOGIC_VECTOR(7 downto 0) := x"39";
constant CHAR_A_i : STD_LOGIC_VECTOR(7 downto 0) := x"61";
constant CHAR_F_i : STD_LOGIC_VECTOR(7 downto 0) := x"66";
subtype nib is std_logic_vector(3 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype half_w is std_logic_vector(15 downto 0);
function Hamming_hByte_encoder ( X : nib ) return byte;
function Hamming_Byte_encoder ( X : byte ) return half_w;
function Hamming_hByte_decoder ( X : byte ) return nib;
function Hamming_Byte_decoder ( X : half_w ) return byte;
function CHAR_TO_HEX ( X : byte ) return nib;
function HEX_TO_CHAR ( X : nib ) return byte;
-- std_logic_vector(4 downto 0) to bcd std_logic_vector(7 downto 0);
subtype input_num is std_logic_vector(4 downto 0); -- 5 bit
subtype BCD_HEX is std_logic_vector(7 downto 0); -- hex
function to_BCD (X: input_num) return BCD_HEX;
end project_nrf_subprogV2;
package body project_nrf_subprogV2 is
-- Lower (a -> f) and 0->9 ASCII char translated to hex. 0xf on err
function CHAR_TO_HEX (X:byte) return nib is
variable tmpByte : byte := (others => '0');
variable retNib : nib := (others => '0');
begin
if (X>=CHAR_A_i and X<=CHAR_F_i) then
tmpByte := X-CHAR_A_i;
elsif (X>=CHAR_0_i and X<=CHAR_F_i) then
tmpByte := X-CHAR_0_i;
else
tmpByte := (others => '0');
end if;
retNib := tmpByte(3 downto 0);
return retNib;
end CHAR_TO_HEX;
-- Hex 0-F translated to ASCII char. 0x00 on err
function HEX_TO_CHAR (X:nib) return byte is
variable tmpByte : byte := (others => '0');
variable tmpOffset: byte := (others => '0');
begin
tmpOffset(3 downto 0) := X;
if (X>="0000" and X<="1001") then
tmpByte := CHAR_0_i+tmpOffset;
elsif (X>="1010" and X<="1111") then
tmpByte := CHAR_A_i+tmpOffset-"00001010";
else
tmpByte := (others => '0');
end if;
return tmpByte;
end HEX_TO_CHAR;
-- Byte in, 16-bit out
function Hamming_Byte_encoder (X : byte ) return half_w is
variable lowerByte : byte := (others => '0');
variable upperByte : byte := (others => '0');
variable ret_half_w: half_w := (others => '0');
begin
lowerByte := Hamming_hByte_encoder( X(3 downto 0) );
upperByte := Hamming_hByte_encoder( X(7 downto 4) );
ret_half_w(7 downto 0) := lowerByte;
ret_half_w(15 downto 8) := upperByte;
return ret_half_w;
end Hamming_Byte_encoder;
-- 4 bit in, 8 encoded out
function Hamming_hByte_encoder (X : nib) return byte is
variable H0 : std_logic := '0';
variable H1 : std_logic := '0';
variable H2 : std_logic := '0';
variable P : std_logic := '0';
variable encoded : std_logic_vector(7 downto 0) := (others => '0');
begin
H0 := X(1) XOR X(2) XOR X(3);
H1 := X(0) XOR X(2) XOR X(3);
H2 := X(0) XOR X(1) XOR X(3);
P := X(0) XOR X(1) XOR X(2); -- CHECK LOGIC
encoded := X & H2 & H1 & H0 & P;
return encoded;
end Hamming_hByte_encoder;
-- 16 bits in, byte out
function Hamming_Byte_decoder (X : half_w ) return byte is
variable lowerNib : nib := (others => '0');
variable upperNib : nib := (others => '0');
variable retByte : byte := (others => '0');
begin
lowerNib := Hamming_hByte_decoder( X(7 downto 0) );
upperNib := Hamming_hByte_decoder( X(15 downto 8) );
retByte(3 downto 0) := lowerNib;
retByte(7 downto 4) := upperNib;
return retByte;
end Hamming_Byte_decoder;
-- 8 Bits in, 4 bits decoded out
function Hamming_hByte_decoder(X : byte) return nib is
variable S0 : std_logic := '0';
variable S1 : std_logic := '0';
variable S2 : std_logic := '0';
variable P : std_logic := '0';
variable D : std_logic_vector(7 downto 0) := (others => '0');
variable R : std_logic_vector(3 downto 0) := (others => '0');
begin
D := X;
S0 := D(1) XOR D(5) XOR D(6) XOR D(7);
S1 := D(2) XOR D(4) XOR D(6) XOR D(7);
S2 := D(3) XOR D(4) XOR D(5) XOR D(7);
-- Method 1
-- if ( (S0 = '1') and (S1 = '1') and (S2 = '1') ) then
-- D(7) := D(7) XOR '1'; -- Rel D3
-- elsif ( (S0 XOR S1 XOR S2) = '1' ) then
-- D(1) := D(1) XOR S0; -- H0
-- D(2) := D(2) XOR S1; -- H1
-- D(3) := D(3) XOR S2; -- H2
-- else
-- D(4) := D(4) XOR NOT(S0); -- Rel D0
-- D(5) := D(5) XOR NOT(S1); -- Rel D1
-- D(6) := D(6) XOR NOT(S2); -- Rel D2
-- end if;
-- Method 2
D(1) := D(1) XOR (S0 AND NOT(S1) AND NOT(S2));
D(2) := D(2) XOR (NOT(S0) AND S1 AND NOT(S2));
D(3) := D(3) XOR (NOT(S0) AND NOT(S1) AND S2);
D(4) := D(4) XOR (NOT(S0) AND S1 AND S2);
D(5) := D(5) XOR (S0 AND NOT(S1) AND S2);
D(6) := D(6) XOR (S0 AND S1 AND NOT(S2));
D(7) := D(7) XOR (S0 AND S1 AND S2);
R := D(7 downto 4);
return R;
end Hamming_hByte_decoder;
function to_BCD (X: input_num) return BCD_HEX is
variable retHEX : BCD_HEX := (others => '0');
begin
if ( X = "00000") then
retHex := x"00";
elsif (X = "00001") then
retHex := x"01";
elsif (X = "00010") then
retHex := x"02";
elsif (X = "00011") then
retHex := x"03";
elsif (X = "00100") then
retHex := x"04";
elsif (X = "00101") then
retHex := x"05";
elsif (X = "00110") then
retHex := x"06";
elsif (X = "00111") then
retHex := x"07";
elsif (X = "01000") then
retHex := x"08";
elsif (X = "01001") then
retHex := x"09";
elsif (X = "01010") then
retHex := x"10";
elsif (X = "01011") then
retHex := x"11";
elsif (X = "01100") then
retHex := x"12";
elsif (X = "01101") then
retHex := x"13";
elsif (X = "01110") then
retHex := x"14";
elsif (X = "01111") then
retHex := x"15";
elsif (X = "10000") then
retHex := x"16";
elsif (X = "10001") then
retHex := x"17";
elsif (X = "10010") then
retHex := x"18";
elsif (X = "10011") then
retHex := x"19";
elsif (X = "10100") then
retHex := x"20";
elsif (X = "10101") then
retHex := x"21";
elsif (X = "10110") then
retHex := x"22";
elsif (X = "10111") then
retHex := x"23";
elsif (X = "11000") then
retHex := x"24";
elsif (X = "11001") then
retHex := x"25";
elsif (X = "11010") then
retHex := x"26";
elsif (X = "11011") then
retHex := x"27";
elsif (X = "11100") then
retHex := x"28";
elsif (X = "11101") then
retHex := x"29";
elsif (X = "11110") then
retHex := x"30";
elsif (X = "11111") then
retHex := x"31";
end if;
return retHex;
end to_BCD;
end project_nrf_subprogV2;
| apache-2.0 | dd5f5eec3ccb247b78fe764ef4517a45 | 0.550636 | 2.628233 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/midi_decoder_tb/midi_decoder_tb.vhd | 1 | 3,471 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.uart_constants.all;
use virtual_button_lib.uart_functions.all;
entity midi_decoder_tb is end;
architecture tb of midi_decoder_tb is
signal clk_50mhz : std_logic;
signal pb_0 : std_logic := '0';
signal pb_1 : std_logic := '0';
signal sw_0 : std_logic := '1';
signal sw_1 : std_logic := '0';
signal led_0 : std_logic;
signal led_1 : std_logic;
signal pi_to_fpga_pin : std_logic := '1';
signal fpga_to_pi_pin : std_logic;
signal light_square_data : std_logic;
constant cpol : integer := 0;
constant cpha : integer := 0;
signal send : boolean;
signal force_cs_low : boolean := false;
signal ready : boolean;
signal data : std_logic_vector(7 downto 0);
signal cs_n : std_logic := '1';
signal sclk : std_logic;
signal mosi : std_logic := '0';
signal miso : std_logic;
constant block_size : integer := 200;
begin
mock_spi_master_1 : entity work.mock_spi_master
port map (
frequency => 5_000_000,
cpol => cpol,
cpha => cpha,
send => send,
force_cs_low => force_cs_low,
ready => ready,
data => data,
cs_n => cs_n,
sclk => sclk,
mosi => mosi);
top_1 : entity work.top
port map (
clk_50mhz => clk_50mhz,
pb_0 => pb_0,
pb_1 => pb_1,
sw_0 => sw_0,
sw_1 => sw_1,
led_0 => led_0,
led_1 => led_1,
pi_to_fpga_pin => pi_to_fpga_pin,
fpga_to_pi_pin => fpga_to_pi_pin,
sclk => sclk,
cs_n => cs_n,
mosi => mosi,
miso => miso,
light_square_data => light_square_data);
-- Clock process definitions
clk_process : process
begin
clk_50mhz <= '0';
wait for clk_period/2;
clk_50mhz <= '1';
wait for clk_period/2;
end process;
stim_proc : process
type charfile is file of character;
file midi_file : charfile;
variable remaining_bytes : integer := 0;
variable read_char : character;
variable midi_byte : std_logic_vector(7 downto 0);
begin
sw_0 <= '0';
wait for 1 us;
sw_0 <= '1';
wait for 1 us;
file_open(midi_file, "deck.mid", read_mode);
--file_open(midi_file, "zeroes_file", read_mode);
while not endfile(midi_file) loop
if remaining_bytes /= 0 then
read(midi_file, read_char);
midi_byte := std_logic_vector(to_unsigned(character'pos(read_char), 8));
end if;
if not ready then
wait until ready;
end if;
if remaining_bytes = 0 then
data <= std_logic_vector(to_unsigned(block_size, 8));
remaining_bytes := block_size;
else
data <= midi_byte;
remaining_bytes := remaining_bytes - 1;
end if;
wait for 1 ps;
send <= true;
wait for 1 ps;
send <= false;
wait for 1 ps;
end loop;
uart_send(std_logic_vector(to_unsigned(character'pos('q'), 8)), 115200, pi_to_fpga_pin);
wait;
end process;
end;
| bsd-2-clause | ece433aee1b5acbd63aecd8aa607cb4f | 0.525497 | 3.457171 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_64_32.vhd | 1 | 86,222 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_32.vhd
-- /___/ /\ Timestamp: Wed Jul 16 14:06:02 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_32.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_32.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_32.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_32.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_32
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_32 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_32;
architecture STRUCTURE of fifo_generator_64_32 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_19 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_20 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_21 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_38 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_39 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_42 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_44 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_45 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_64 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_65 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_67 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_71 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_72 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_73 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_74 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_75 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_76 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_45;
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_73,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_64
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_72,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_73
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_67
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_75,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_76
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_71,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_72
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_65,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_75,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_74
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_74,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_75
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_66,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_65
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_71
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_72,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_44
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_72,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_45
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_72,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_74,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_76,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_65,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_67,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_44,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => N22
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I4 => N22,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_42
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb82 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93 : LUT6
generic map(
INIT => X"FFFFFFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_42,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_64,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_39
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_38
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000142 : LUT6
generic map(
INIT => X"D4C4C4C4DCCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_37,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_39,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_38,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_21
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182 : LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_18,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_44,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_20
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000232 : LUT6
generic map(
INIT => X"EEAAECA8AAAAA8A8"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_20,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_17,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_21,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_19,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb132 : LUT6
generic map(
INIT => X"FF44FF0444440404"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_64,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_44,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_41,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_43,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2 : LUT4
generic map(
INIT => X"0C04"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_44,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP :
RAMB36SDP_EXP
generic map(
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_SCRUB => FALSE,
EN_ECC_WRITE => FALSE,
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000000000000",
SRVAL => X"000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
RDENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
RDENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WRENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WRENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SSRU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
SSRL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDCLKU => clk,
RDCLKL => clk,
WRCLKU => clk,
WRCLKL => clk,
RDRCLKU => clk,
RDRCLKL => clk,
REGCEU => N0,
REGCEL => N0,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED
,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED
,
DI(63) => din(63),
DI(62) => din(62),
DI(61) => din(61),
DI(60) => din(60),
DI(59) => din(59),
DI(58) => din(58),
DI(57) => din(57),
DI(56) => din(56),
DI(55) => din(55),
DI(54) => din(54),
DI(53) => din(53),
DI(52) => din(52),
DI(51) => din(51),
DI(50) => din(50),
DI(49) => din(49),
DI(48) => din(48),
DI(47) => din(47),
DI(46) => din(46),
DI(45) => din(45),
DI(44) => din(44),
DI(43) => din(43),
DI(42) => din(42),
DI(41) => din(41),
DI(40) => din(40),
DI(39) => din(39),
DI(38) => din(38),
DI(37) => din(37),
DI(36) => din(36),
DI(35) => din(35),
DI(34) => din(34),
DI(33) => din(33),
DI(32) => din(32),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => N0,
DIP(6) => N0,
DIP(5) => N0,
DIP(4) => N0,
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
RDADDRL(15) => N1,
RDADDRL(14) => N0,
RDADDRL(13) => N0,
RDADDRL(12) => N0,
RDADDRL(11) => N0,
RDADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED
,
RDADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED
,
RDADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED
,
RDADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED
,
RDADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED
,
RDADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED
,
RDADDRU(14) => N0,
RDADDRU(13) => N0,
RDADDRU(12) => N0,
RDADDRU(11) => N0,
RDADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED
,
RDADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED
,
RDADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED
,
RDADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED
,
RDADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED
,
RDADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED
,
WRADDRL(15) => N1,
WRADDRL(14) => N0,
WRADDRL(13) => N0,
WRADDRL(12) => N0,
WRADDRL(11) => N0,
WRADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED
,
WRADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED
,
WRADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED
,
WRADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED
,
WRADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED
,
WRADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED
,
WRADDRU(14) => N0,
WRADDRU(13) => N0,
WRADDRU(12) => N0,
WRADDRU(11) => N0,
WRADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED
,
WRADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED
,
WRADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED
,
WRADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED
,
WRADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED
,
WRADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED
,
WEU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DO(63) => dout(63),
DO(62) => dout(62),
DO(61) => dout(61),
DO(60) => dout(60),
DO(59) => dout(59),
DO(58) => dout(58),
DO(57) => dout(57),
DO(56) => dout(56),
DO(55) => dout(55),
DO(54) => dout(54),
DO(53) => dout(53),
DO(52) => dout(52),
DO(51) => dout(51),
DO(50) => dout(50),
DO(49) => dout(49),
DO(48) => dout(48),
DO(47) => dout(47),
DO(46) => dout(46),
DO(45) => dout(45),
DO(44) => dout(44),
DO(43) => dout(43),
DO(42) => dout(42),
DO(41) => dout(41),
DO(40) => dout(40),
DO(39) => dout(39),
DO(38) => dout(38),
DO(37) => dout(37),
DO(36) => dout(36),
DO(35) => dout(35),
DO(34) => dout(34),
DO(33) => dout(33),
DO(32) => dout(32),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED
,
DOP(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED
,
DOP(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED
,
DOP(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED
,
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | dd500d7740fcda213daf809eaf772e7f | 0.695461 | 2.802783 | false | false | false | false |
scarter93/RSA-Encryption | mod_exp_comparison.vhd | 1 | 6,053 | -- Entity name: modular_exponentiation
-- Author: Luis Gallet
-- Contact: [email protected]
-- Date: March 28th, 2016
-- Description:
-- Module responsible of performing encryption and decryption. It uses the
-- montgomery_comparison.vhd to perform multiplication and modulo operations.
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lpm;
use lpm.lpm_components.all;
entity mod_exp_comparison is
generic(WIDTH_IN : integer := 32
);
port(
N : in unsigned(WIDTH_IN-1 downto 0); --Number
--Exp : in unsigned(WIDTH_IN-1 downto 0); --Exponent
--M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
enc_dec: in std_logic;
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0)
);
end entity;
architecture behavior of mod_exp_comparison is
constant zero : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
--------------------------------------32 bit constants------------------------------------------------
--constant K : unsigned (WIDTH_IN-1 downto 0) := "00000110010001101110000100100000101111011101110010111101100011001010101111001011011010101000010100001011000100011101101000011110";
constant M : unsigned (WIDTH_IN-1 downto 0) := "10000100010001111000010010000101";
constant dec_Exp : unsigned(WIDTH_IN-1 downto 0) := "00101010110001011001000101000101";
constant enc_Exp : unsigned(WIDTH_IN-1 downto 0) := "00000000000000010000000000000001";
-------------------------------------------------------------------------------------------------------
-- Intermidiate signals
signal temp_A1,temp_A2 : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal temp_B1, temp_B2 : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal temp_d_ready, temp_d_ready2 : std_logic := '0';
signal temp_M1, temp_M2 : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal latch_in, latch_in2 : std_logic := '0';
signal temp_M : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal temp_C : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
-- FSM states
type STATE_TYPE is (s0, s1, s2, s3, s4, s5, s6, s7, s8);
signal state: STATE_TYPE := s0;
component montgomery_comparison
Generic(WIDTH_IN : integer := 8
);
Port( A : in unsigned(WIDTH_IN-1 downto 0);
B : in unsigned(WIDTH_IN-1 downto 0);
N : in unsigned(WIDTH_IN-1 downto 0);
latch : in std_logic;
clk : in std_logic;
reset : in std_logic;
data_ready : out std_logic;
M : out unsigned(WIDTH_IN-1 downto 0)
);
end component;
begin
-- Montgomery comparison components
mont_mult_1: montgomery_comparison
generic map(WIDTH_IN => WIDTH_IN)
port map(
A => temp_A1,
B => temp_B1,
N => temp_M,
latch => latch_in,
clk => clk,
reset => reset,
data_ready => temp_d_ready,
M => temp_M1
);
mont_mult_2: montgomery_comparison
generic map(WIDTH_IN => WIDTH_IN)
port map(
A => temp_A2,
B => temp_B2,
N => temp_M,
latch => latch_in2,
clk => clk,
reset => reset,
data_ready => temp_d_ready2,
M => temp_M2
);
C <= temp_C;
sqr_mult : Process(clk, reset, N)
variable count : integer := 0;
variable shift_count : integer := 0;
variable temp_N : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable P : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable P_old : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable R : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable temp_Exp : unsigned(WIDTH_IN-1 downto 0);
variable temp_mod : unsigned(WIDTH_IN-1 downto 0);
begin
if reset = '1' then
count := 0;
shift_count := 0;
temp_N := (others => '0');
P := (others => '0');
R := (others => '0');
temp_Exp := (others => '0');
temp_mod := (others => '0');
temp_M <= (others => '0');
state <= s0;
elsif rising_edge(clk) then
case state is
-- Check if there are new inputs available
when s0 =>
--(M = zero) OR (Exp = zero) OR
if((N = zero)) OR ((temp_M = M) AND (temp_N = N)) then
state <= s0;
else
temp_mod := M;
state <= s1;
end if;
-- If MSB of modulus is not 1 then shift it left until a 1 is found and count how many times it was shifted
when s1 =>
if(temp_mod(WIDTH_IN-1) = '1')then
if(enc_dec = '1')then
temp_Exp := enc_Exp;
else
temp_Exp := dec_Exp;
end if;
--temp_Exp := Exp;
temp_M <= M;
temp_N := N;
state <= s2;
else
temp_mod := (shift_left(temp_mod,natural(1)));
shift_count := shift_count + 1;
state <= s1;
end if;
-- Assign initial values to P and R
when s2 =>
P_old := temp_N;
R := to_unsigned(1,WIDTH_IN);
state <= s3;
-- Check Listing 1 in report. This operation is inside the for loop and it is always performed
when s3 =>
temp_A1 <= P_old;
temp_B1 <= P_old;
latch_in <= '1';
if(temp_d_ready = '0')then
state <= s4;
end if;
-- If LSB of the exponent is 1 then compute R, else go to state 7
when s4 =>
latch_in <= '0';
if(temp_d_ready = '1')then
P := temp_M1;
if(temp_Exp(0) = '1')then
state <= s5;
else
state <= s7;
end if;
end if;
when s5 =>
temp_A2 <= R;
temp_B2 <= P_old;
latch_in2 <= '1';
if(temp_d_ready2 = '0')then
state <= s6;
end if;
when s6 =>
latch_in2 <= '0';
if(temp_d_ready2 = '1') then
R := temp_M2;
state <= s7;
end if;
-- If the statement is true, it means that we have checked all bits in the exponent or exponent is zero and we compute the output
when s7 =>
if (count = (WIDTH_IN-1)-shift_count) OR (temp_Exp = zero) then
temp_C <= R;
state <= s8;
else -- if the statement is false, then we shift the exponent right and increment count
temp_Exp := (shift_right(temp_Exp, natural(1)));
P_old := P;
count := count + 1;
state <= s3;
end if;
when s8 =>
count := 0;
shift_count := 0;
P := (others => '0');
R := (others => '0');
temp_mod := (others => '0');
state <= s0;
end case;
end if;
end process sqr_mult;
end behavior; | mit | 4e78f07ee98923fc5e30f48906ef8f98 | 0.606476 | 2.852498 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/ovl_implication_rtl.vhd | 1 | 5,573 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_implication is
constant assert_name : string := "OVL_IMPLICATION";
constant path : string := rtl'path_name;
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal antecedent_expr_x01 : std_logic;
signal consequent_expr_x01 : std_logic;
shared variable error_count : natural;
shared variable cover_count : natural;
begin
antecedent_expr_x01 <= to_x01(antecedent_expr);
consequent_expr_x01 <= to_x01(consequent_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
elsif ((antecedent_expr_x01 = '1') and (consequent_expr_x01 = '0')) then
fire(0) <= '1';
ovl_error_proc("Antecedent does not have consequent", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(0) <= '0';
end if;
end if;
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif ((consequent_expr_x01 = '0') and ovl_is_x(antecedent_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("antecedent_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
elsif ((antecedent_expr_x01 = '1') and (ovl_is_x(consequent_expr_x01))) then
fire(1) <= '1';
ovl_error_proc("consequent_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (antecedent_expr_x01 = '1') then
fire(2) <= '1';
ovl_cover_proc("antecedent covered", assert_name, path, controls, cover_count);
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or (not cover_basic)) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit | de7307faf0587533126929640a0941fe | 0.48735 | 3.935734 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/input_output.vhd | 1 | 5,838 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_output is
PORT ( CLK_I : in std_logic;
T2 : in std_logic;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
HALT : in STD_LOGIC;
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
-- temperature
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
CLR : out STD_LOGIC;
-- input/output
IO_RD : in std_logic;
IO_WR : in std_logic;
IO_ADR : in std_logic_vector( 7 downto 0);
IO_RDAT : out std_logic_vector( 7 downto 0);
IO_WDAT : in std_logic_vector( 7 downto 0);
INT : out STD_LOGIC
);
end input_output;
architecture Behavioral of input_output is
COMPONENT temperature
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
TEMP_SPO : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic
);
END COMPONENT;
COMPONENT uart_baudgen
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
RD : IN std_logic;
WR : IN std_logic;
TX_DATA : IN std_logic_vector(7 downto 0);
RX_SERIN : IN std_logic;
TX_SEROUT : OUT std_logic;
RX_DATA : OUT std_logic_vector(7 downto 0);
RX_READY : OUT std_logic;
TX_BUSY : OUT std_logic
);
END COMPONENT;
signal L_IO_ADR : std_logic_vector(7 downto 0);
signal IO_RD_SERIAL : std_logic;
signal IO_WR_SERIAL : std_logic;
signal RX_READY : std_logic;
signal TX_BUSY : std_logic;
signal RX_DATA : std_logic_vector(7 downto 0);
signal TEMP_DO : std_logic_vector(7 downto 0);
signal FLAG : std_logic;
signal LCLR : std_logic;
signal C1_N, C2_N : std_logic; -- switch debounce, active low
signal RX_INT_ENABLED : std_logic;
signal TX_INT_ENABLED : std_logic;
signal TIM_INT_ENABLED : std_logic;
signal TIMER_INT : std_logic;
signal TIMER : std_logic_vector(14 downto 0);
signal CLK_COUNT : std_logic_vector(15 downto 0);
signal CLK_COUNT_EN : std_logic;
signal CLK_HALT_MSK : std_logic;
signal CLK_HALT_VAL : std_logic;
begin
tempr: temperature
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => LCLR,
DATA_OUT => TEMP_DO,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
uart: uart_baudgen
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => LCLR,
RD => IO_RD_SERIAL,
WR => IO_WR_SERIAL,
TX_DATA => IO_WDAT,
TX_SEROUT => SER_OUT,
RX_SERIN => SER_IN,
RX_DATA => RX_DATA,
RX_READY => RX_READY,
TX_BUSY => TX_BUSY
);
CLR <= LCLR;
INT <= (RX_INT_ENABLED and RX_READY)
or (TX_INT_ENABLED and not TX_BUSY)
or (TIM_INT_ENABLED and TIMER_INT);
-- IO read process
--
process(L_IO_ADR, IO_RD, IO_WR, RX_DATA, TEMP_DO, SWITCH,
TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
RX_INT_ENABLED, RX_READY)
begin
IO_RD_SERIAL <= '0';
IO_WR_SERIAL <= '0';
case L_IO_ADR is
when X"00" => IO_RDAT <= RX_DATA;
IO_RD_SERIAL <= IO_RD;
IO_WR_SERIAL <= IO_WR;
when X"01" => IO_RDAT <= '0'
& (TIM_INT_ENABLED and TIMER_INT)
& (TX_INT_ENABLED and not TX_BUSY)
& (RX_INT_ENABLED and RX_READY)
& '0'
& TIMER_INT
& TX_BUSY
& RX_READY;
when X"02" => IO_RDAT <= TEMP_DO;
when X"03" => IO_RDAT <= SWITCH(7 downto 0);
when X"05" => IO_RDAT <= CLK_COUNT(7 downto 0);
when others => IO_RDAT <= CLK_COUNT(15 downto 8);
end case;
end process;
-- IO write and timer process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
L_IO_ADR <= IO_ADR;
if (LCLR = '1') then
LED <= X"00";
RX_INT_ENABLED <= '0';
TX_INT_ENABLED <= '0';
TIM_INT_ENABLED <= '0';
TIMER_INT <= '0';
TIMER <= "000" & X"000";
else
if (IO_WR = '1') then
case L_IO_ADR is
when X"00" => -- handled by uart
when X"01" => -- handled by uart
when X"02" => LED <= IO_WDAT;
when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
TX_INT_ENABLED <= IO_WDAT(1);
TIM_INT_ENABLED <= IO_WDAT(2);
when X"04" => TIMER_INT <= '0';
when X"05" => CLK_COUNT_EN <= '1';
CLK_COUNT <= X"0000";
CLK_HALT_VAL <= IO_WDAT(0);
CLK_HALT_MSK <= IO_WDAT(1);
when X"06" => CLK_COUNT_EN <= '0';
when others =>
end case;
end if;
TIMER <= TIMER + 1;
if (TIMER = 19999) then -- 1 ms
TIMER_INT <= '1';
TIMER <= "000" & X"000";
end if;
if (CLK_COUNT_EN = '1' and
(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
CLK_COUNT <= CLK_COUNT + 1;
end if;
end if;
end if;
end if;
end process;
-- reset debounce process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
-- switch debounce
if (SWITCH(8) = '1' or SWITCH(9) = '1') then
LCLR <= '1';
C2_N <= '0';
C1_N <= '0';
else
LCLR <= not C2_N;
C2_N <= C1_N;
C1_N <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 2c35b1e46542d4ceec075a74552c7bd9 | 0.535115 | 2.65847 | false | false | false | false |
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II | ProgramaVHDL/mult_div.vhd | 2 | 5,816 | -----------------------------------------------------------------------
-- MULTIPLICAÇÃO POR SOMAS SUCESSIVAS
--
-- Mcando, Mcador - Multiplicando e Multiplicador, de N bits
-- start, endop - Início e fim de operação de multiplicação
-- produto - Resultado, com 2N bits
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity multiplica is
generic(N: integer := 32);
port( Mcando: in std_logic_vector((N-1) downto 0);
Mcador: in std_logic_vector((N-1) downto 0);
clock,start: in std_logic;
endop: out std_logic;
produto: out std_logic_vector(2*N-1 downto 0));
end;
architecture multiplica of multiplica is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal cont: integer;
begin
--
-- registradores regP, regB, produto, endop e contador de execução
--
process(start, clock)
begin
if start='1'then
regP( N*2 downto N) <= (others=>'0');
regP( N-1 downto 0) <= Mcador;
regB <= '0' & Mcando;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=calc and regP(0)='1' then
regP(N*2 downto N) <= regP(N*2 downto N) + regB;
elsif EA=desloca then
regP <= '0' & regP(N*2 downto 1);
cont <= cont + 1;
elsif EA=termina then
produto <= regP( N*2-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a multiplicação
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= calc;
when calc => EA <= desloca;
when desloca => if cont=N then
EA <= termina;
else
EA <= calc;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end multiplica;
-----------------------------------------------------------------------
-- DIVISÃO
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity divide is
generic(N: integer := 16);
port( divisor: in std_logic_vector( (N-1) downto 0);
dividendo: in std_logic_vector( (N-1) downto 0);
clock,start : in std_logic;
endop : out std_logic;
quociente : out std_logic_vector( N-1 downto 0);
resto : out std_logic_vector( N-1 downto 0));
end;
architecture divide of divide is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal diferenca : std_logic_vector( N downto 0);
signal cont: integer;
begin
diferenca <= regP( N*2 downto N) - regB( N downto 0);
process(start, clock)
begin
if start='1'then
regP(N*2 downto N) <= (others=>'0');
regP(N-1 downto 0) <= dividendo;
regB <= '0' & divisor;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=desloca then
regP <= regP( N*2-1 downto 0) & regP(N*2);
elsif EA=calc then
if diferenca(N)='1' then
regP(0)<='0';
else
regP(0)<='1';
regP(N*2 downto N) <= diferenca;
end if;
cont <= cont + 1;
elsif EA=termina then
resto <= regP( N*2-1 downto N);
quociente <= regP( N-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a DIVISAO
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= desloca;
when desloca => EA <= calc;
when calc => if cont=N then
EA <= termina;
else
EA <= desloca;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end divide;
| mit | 511142a4d62a0ded053202976eb4e245 | 0.411107 | 4.353293 | false | false | false | false |
willtmwu/vhdlExamples | Project/RAM_BLOCK.vhd | 1 | 1,192 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: RAM_BLOCK.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: RAM block for 64 Nibbles
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_BLOCK is
port( clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(5 downto 0);
d_i : in std_logic_vector(3 downto 0);
d_o : out std_logic_vector(3 downto 0));
end RAM_BLOCK;
architecture syn of RAM_BLOCK is
type ram_type is array (63 downto 0) of std_logic_vector (3 downto 0);
signal RAM: ram_type := (others => (others => '0'));
begin
process (clk) begin
if rising_edge(clk) then
if en = '1' then
if (addr <= 63) then
if we = '1' then
RAM(conv_integer(addr))<=d_i;
end if;
d_o<=RAM(conv_integer(addr));
end if;
end if;
end if;
end process;
end syn; | apache-2.0 | 52c6aeac822645e15523490bc8fce6e2 | 0.531879 | 3.072165 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/spi/spi_tb.vhd | 1 | 3,295 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity spi_tb is
end spi_tb;
architecture behavior of spi_tb is
constant cpol : integer := 0;
constant cpha : integer := 0;
--hw interface
signal ctrl : ctrl_t := ('0', '0');
signal cs_n : std_logic := '1';
signal sclk : std_logic := '0';
signal mosi : std_logic := '0';
signal miso : std_logic;
signal request_more_from_mcu : std_logic;
-- Clock period definitions
constant block_size : integer := 10;
signal new_mcu_to_fpga_data : std_logic;
signal mcu_to_fpga_data : std_logic_vector(spi_word_length - 1 downto 0);
signal enqueue_fpga_to_mcu_data : std_logic;
signal fpga_to_mcu_data : std_logic_vector(spi_word_length - 1 downto 0) := (others => '0');
signal next_byte_index : integer range 0 to block_size - 1;
-- mock spi master signals
signal ready : boolean;
signal send : boolean;
signal master_data : std_logic_vector(spi_word_length - 1 downto 0);
signal force_cs_low : boolean := false;
begin
-- Instantiate the Unit Under Test (UUT)
uut : entity virtual_button_lib.spi_top
generic map(
block_size => block_size,
cpol => 0,
cpha => 0
)
port map (
ctrl => ctrl,
cs_n => cs_n,
sclk => sclk,
mosi => mosi,
miso => miso,
request_more_from_mcu => request_more_from_mcu,
new_mcu_to_fpga_data => new_mcu_to_fpga_data,
mcu_to_fpga_data => mcu_to_fpga_data,
enqueue_fpga_to_mcu_data => enqueue_fpga_to_mcu_data,
fpga_to_mcu_data => fpga_to_mcu_data,
next_byte_index => next_byte_index
);
mock_spi_master_1: entity work.mock_spi_master
port map (
frequency => 5_000_000,
cpol => cpol,
cpha => cpha,
send => send,
force_cs_low => force_cs_low,
ready => ready,
data => mcu_to_fpga_data,
cs_n => cs_n,
sclk => sclk,
mosi => mosi);
-- Clock process definitions
clk_process : process
begin
ctrl.clk <= '0';
wait for clk_period/2;
ctrl.clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
ctrl.reset_n <= '0';
wait for 1 us;
ctrl.reset_n <= '1';
wait;
end process;
fpga_send_proc : process
begin
wait for 10 us;
wait until falling_edge(ctrl.clk);
fpga_to_mcu_data <= std_logic_vector(unsigned(fpga_to_mcu_data) + 1);
enqueue_fpga_to_mcu_data <= '1';
wait until falling_edge(ctrl.clk);
enqueue_fpga_to_mcu_data <= '0';
end process;
mcu_send_proc : process
begin
wait for 50 us;
if request_more_from_mcu = '1' then
for i in 0 to 10 loop
if not ready then
wait until ready;
end if;
send <= true;
wait for 1 ps;
send <= false;
end loop;
end if;
end process;
end;
| bsd-2-clause | 08e9929899702b54346559ae83640fb9 | 0.542033 | 3.490466 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_cycle_sequence_rtl.vhd | 1 | 10,459 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_cycle_sequence is
constant assert_name : string := "OVL_CYCLE_SEQUENCE";
constant path : string := "";
constant trig_on_most_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_MOST_PIPE);
constant trig_on_first_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_PIPE);
constant trig_on_first_nopipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_NOPIPE);
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal event_sequence_x01 : std_logic_vector(num_cks - 1 downto 0);
signal seq_queue : std_logic_vector(num_cks - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
event_sequence_x01 <= to_x01(event_sequence);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Shared logic --
------------------------------------------------------------------------------
ovl_seq_queue_gen : if (ovl_2state_is_on(controls, property_type) or
((controls.cover_ctrl = OVL_ON) and (coverage_level_ctrl /= OVL_COVER_NONE))) generate
ovl_seq_queue_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
seq_queue <= (others => '0');
else
if (trig_on_first_nopipe) then
seq_queue(num_cks - 1) <= not(or_reduce(seq_queue(num_cks - 1 downto 1))) and
event_sequence_x01(num_cks - 1);
else
seq_queue(num_cks - 1) <= event_sequence_x01(num_cks - 1);
end if;
seq_queue(num_cks - 2 downto 0) <= seq_queue(num_cks - 1 downto 1) and
event_sequence_x01(num_cks - 2 downto 0);
end if;
end if;
end process ovl_seq_queue_p;
end generate ovl_seq_queue_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
else
fire(0) <= '0';
if (trig_on_first_pipe or trig_on_first_nopipe) then
if (and_reduce((seq_queue(num_cks -1 downto 1) and event_sequence_x01(num_cks - 2 downto 0)) or
not(seq_queue(num_cks -1 downto 1))) = '0') then
fire(0) <= '1';
ovl_error_proc("First event occured but it is not followed by the rest of the events in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
else -- trig_on_most_pipe
if ((not(seq_queue(1)) or (seq_queue(1) and event_sequence_x01(0))) = '0') then
fire(0) <= '1';
ovl_error_proc("First num_cks-1 events occured but they are not followed by the last event in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
function init_valid_sequence_gate return std_logic_vector is
variable set : std_logic_vector(num_cks - 2 downto 0);
begin
if (num_cks > 2) then
set(num_cks - 2 downto 1) := (others => '1');
end if;
if (trig_on_most_pipe) then set(0) := '0'; else set(0) := '1'; end if;
return set;
end function init_valid_sequence_gate;
variable valid_first_event : std_logic;
variable valid_sequence : std_logic;
variable valid_last_event : std_logic;
constant valid_sequence_gate : std_logic_vector(num_cks - 2 downto 0) := init_valid_sequence_gate;
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
valid_first_event := event_sequence_x01(num_cks - 1);
valid_last_event := seq_queue(1) and event_sequence_x01(0);
valid_sequence := xor_reduce(seq_queue(num_cks - 1 downto 1) and event_sequence_x01(num_cks - 2 downto 0) and
valid_sequence_gate);
if (reset_n = '0') then
fire(1) <= '0';
else
fire(1) <= '0';
if (ovl_is_x(valid_first_event)) then
if (trig_on_most_pipe or trig_on_first_pipe) then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
elsif (not(or_reduce(seq_queue(num_cks - 1 downto 1))) = '1') then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (ovl_is_x(valid_sequence)) then
if (trig_on_first_pipe or trig_on_first_nopipe) then
fire(1) <= '1';
ovl_error_proc("Subsequent events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (trig_on_most_pipe) then
if (ovl_is_x(valid_last_event)) then
if (seq_queue(1) = '1') then
fire(1) <= '1';
ovl_error_proc("Last event in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (((trig_on_first_pipe or trig_on_first_nopipe) and (event_sequence_x01(num_cks - 1) = '1')) or
(trig_on_most_pipe and (seq_queue(1) = '1'))) then
fire(2) <= '1';
ovl_cover_proc("sequence_trigger covered", assert_name, path, controls, cover_count);
else
fire(2) <= '0';
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or not cover_basic) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit | ab19509f7ca9d4fb5a8838a008cca509 | 0.491156 | 3.931955 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/rtl-debugging/debug_contents_count.vhd | 1 | 1,220 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.ws2812_data.all;
use virtual_button_lib.ws2812_constant_colours.all;
entity debug_contents_count is
generic (spi_tx_ram_depth : integer);
port(
ctrl : in ctrl_t;
contents_count : in integer range 0 to spi_tx_ram_depth;
contents_count_debug : out ws2812_array_t(0 to 7)
);
end;
architecture rtl of debug_contents_count is
constant debug_colour : ws2812_t := ws2812_yellow;
constant num_debug_leds : integer := 8;
constant contents_per_led : integer := spi_tx_ram_depth / num_debug_leds;
begin
debug_fullness : for i in 1 to 8 generate
go : process(ctrl.clk) is
constant threshold : integer range 0 to spi_tx_ram_depth := contents_per_led * i;
begin
if rising_edge(ctrl.clk) then
if contents_count > threshold or contents_count = spi_tx_ram_depth then
contents_count_debug(i - 1) <= debug_colour;
else
contents_count_debug(i - 1) <= ws2812_clear;
end if;
end if;
end process;
end generate;
end;
| bsd-2-clause | 6b9b4e9e4e369a27ff48cad5fbe75104 | 0.668033 | 3.297297 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_32_d32.vhd | 1 | 87,500 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_32_d32.vhd
-- /___/ /\ Timestamp: Wed Jul 16 15:01:57 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_32_d32.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_32_d32.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_d32.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_d32.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_32_d32
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_32_d32 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end fifo_generator_32_d32;
architecture STRUCTURE of fifo_generator_32_d32 is
signal N0 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_126 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_127 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_128 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_129 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_133 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_134 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_135 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_136 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_137 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_138 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM62_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM61_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 31 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44;
dout(31) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31);
dout(30) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30);
dout(29) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29);
dout(28) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28);
dout(27) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27);
dout(26) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26);
dout(25) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25);
dout(24) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24);
dout(23) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23);
dout(22) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22);
dout(21) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21);
dout(20) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20);
dout(19) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19);
dout(18) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18);
dout(17) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17);
dout(16) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16);
dout(15) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15);
dout(14) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14);
dout(13) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13);
dout(12) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12);
dout(11) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11);
dout(10) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10);
dout(9) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9);
dout(8) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8);
dout(7) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7);
dout(6) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6);
dout(5) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5);
dout(4) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4);
dout(3) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3);
dout(2) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2);
dout(1) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1);
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_135,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_126
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_134,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_135
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_128,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_129
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_137,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_138
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_133,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_134
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_127,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_128
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_137,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_136
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_136,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_137
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_128,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_127
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_133
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM62 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(31),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM62_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM61 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(30),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM61_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(25),
DIA(0) => din(24),
DIB(1) => din(27),
DIB(0) => din(26),
DIC(1) => din(29),
DIC(0) => din(28),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(19),
DIA(0) => din(18),
DIB(1) => din(21),
DIB(0) => din(20),
DIC(1) => din(23),
DIC(0) => din(22),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(7),
DIA(0) => din(6),
DIB(1) => din(9),
DIB(0) => din(8),
DIC(1) => din(11),
DIC(0) => din(10),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(1),
DIA(0) => din(0),
DIB(1) => din(3),
DIB(0) => din(2),
DIC(1) => din(5),
DIC(0) => din(4),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(13),
DIA(0) => din(12),
DIB(1) => din(15),
DIB(0) => din(14),
DIC(1) => din(17),
DIC(0) => din(16),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_31 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_30 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_29 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_28 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_27 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_26 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_25 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_24 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_23 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_22 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_21 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_20 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_19 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_18 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_17 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_16 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_15 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_14 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_13 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_12 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_11 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_10 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_134,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_134,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_134,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_136,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_138,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_127,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_129,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => N22
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I4 => N22,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb82 : LUT4
generic map(
INIT => X"7BDE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93 : LUT6
generic map(
INIT => X"FFFFFFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_126,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104 : LUT6
generic map(
INIT => X"8020401008020401"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000142 : LUT6
generic map(
INIT => X"8E8A8A8AAEAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049 : LUT6
generic map(
INIT => X"7FBFDFEFF7FBFDFE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182 : LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000232 : LUT6
generic map(
INIT => X"EAEAEAC8AAAAAA88"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb132 : LUT6
generic map(
INIT => X"F4F4F0F444440044"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_126,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2 : LUT4
generic map(
INIT => X"0C04"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 4f90734af2bd439a22a6b7ae2dfc6c6b | 0.661966 | 2.476859 | false | false | false | false |
willtmwu/vhdlExamples | Basic Event Logic/clockedRegister.vhd | 1 | 1,432 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:09:07 08/08/2014
-- Design Name:
-- Module Name: clockedRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clockedRegister is
Port ( D : in STD_LOGIC_VECTOR (15 downto 0);
E : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end clockedRegister;
architecture Behavioral of clockedRegister is
begin
PROCESS( reset, clk)BEGIN
if reset = '0' then
Q <= (others => '0');
elsif clk'event and clk = '1' then
if (E = '1') then
Q <= D;
end if;
end if;
END PROCESS;
end Behavioral;
| apache-2.0 | a3f785390a6e29b45618bff15e9a6fc6 | 0.553771 | 3.738903 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_zero_one_hot.vhd | 1 | 1,181 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_zero_one_hot is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_zero_one_hot;
| mit | 0a3e5f75103b33a5bd74ff0d0dd5b233 | 0.568163 | 3.317416 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstmux/tb_tstmux.vhd | 1 | 11,454 | ------------------------------------------------------------------------------
-- Testbench for the tstmux function of the zunit
--
-- Project :
-- File : tb_tstmux.vhd
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/15
-- Last changed: $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
-- $Id: tb_tstmux.vhd 136 2004-10-26 12:50:34Z plessl $
------------------------------------------------------------------------------
-- This testbench tests the tstmux function of the zunit.
--
-- The primary goals of this testbench are:
-- test extension of cell to support 3 inputs (operands)
-- test ternary operators (mux is a ternary operator)
-- test the alu_mux function
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-27 CP created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTMUX.all;
entity tb_tstmux is
end tb_tstmux;
architecture arch of tb_tstmux is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 10; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec :=
tstmuxcfg;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstmux_cfg.h";
type fifo_array is array (0 to (3*NDATA)-1) of
std_logic_vector(15 downto 0);
--------------------------------------------------------------------
-- test vectors
-- out = c(0) ? a : b
--
-- The testbench feeds input a also to the mux input, i.e. the output of the
-- multiplexer is alway determined by the LSB of input A
--------------------------------------------------------------------
constant TESTV : fifo_array :=
(
-- a b out
X"1234", X"5678", X"1234",
X"1235", X"5678", X"5678",
X"AFFE", X"CAFE", X"AFFE",
X"AEFF", X"CAFE", X"CAFE",
X"BEEF", X"DEAD", X"DEAD",
X"DEAF", X"BEEF", X"BEEF",
X"FEED", X"ABBA", X"ABBA",
X"1111", X"2222", X"2222",
X"0001", X"0002", X"0002",
X"2323", X"2BAD", X"2BAD"
);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(15 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(15 downto 0) := (others => '0');
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3);
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i*3))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO1 (ZREG_FIFO1:W)
-------------------------------------------------
tbStatus <= push_data_fifo1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3+1);
-- assert false
-- report "writing to FIFO1:" & hstr(TESTV(i*3+1))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := TESTV(3*i+2);
response := DataOutxD(15 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 347a380fed2cc58a4f88cd6e274ffee1 | 0.450934 | 4.061702 | false | true | false | false |
plessl/zippy | vhdl/testbenches/tb_configmem.vhd | 1 | 4,864 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
use work.ComponentsPkg.all;
entity tb_ConfigMem is
end tb_ConfigMem;
architecture arch of tb_ConfigMem is
-- constants
constant CFGWIDTH : integer := ENGN_CFGLEN;
constant PTRWIDTH : integer := 10; -- 2**PTRWIDTH > CFGWIDTH
constant SLCWIDTH : integer := 8;
constant N_SLICES : integer := (CFGWIDTH-1)/SLCWIDTH+1;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, write_slice, load_memptr);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data signals
signal WExE : std_logic;
signal CfgSlicexD : std_logic_vector(SLCWIDTH-1 downto 0);
signal LoadSlicePtrxE : std_logic;
signal SlicePtrxD : std_logic_vector(PTRWIDTH-1 downto 0);
signal ConfigWordxD : std_logic_vector(CFGWIDTH-1 downto 0);
signal ConfigWord : engineConfigRec;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ConfigMem
generic map (
CFGWIDTH => CFGWIDTH,
PTRWIDTH => PTRWIDTH,
SLCWIDTH => SLCWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
CfgSlicexDI => CfgSlicexD,
LoadSlicePtrxEI => LoadSlicePtrxE,
SlicePtrxDI => SlicePtrxD,
ConfigWordxDO => ConfigWordxD);
----------------------------------------------------------------------------
-- configuration conversion to record (for test purposes)
----------------------------------------------------------------------------
ConfigWord <= to_engineConfig_rec(ConfigWordxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
WExE <= '0';
CfgSlicexD <= (others => '0');
LoadSlicePtrxE <= '0';
SlicePtrxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= write_slice;
WExE <= '1';
CfgSlicexD <= std_logic_vector(to_unsigned(254, SLCWIDTH));
wait for CLK_PERIOD;
WExE <= '0';
wait for CLK_PERIOD;
tbStatus <= idle;
WExE <= '0';
CfgSlicexD <= (others => '0');
LoadSlicePtrxE <= '0';
SlicePtrxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= write_slice;
WExE <= '1';
CfgSlicexD <= std_logic_vector(to_unsigned(254, SLCWIDTH));
wait for CLK_PERIOD;
WExE <= '0';
wait for CLK_PERIOD;
tbStatus <= idle;
WExE <= '0';
CfgSlicexD <= (others => '0');
LoadSlicePtrxE <= '0';
SlicePtrxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= write_slice;
WExE <= '1';
CfgSlicexD <= std_logic_vector(to_unsigned(254, SLCWIDTH));
wait for CLK_PERIOD;
for i in 4 to N_SLICES+2 loop
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle;
WExE <= '0';
CfgSlicexD <= (others => '0');
LoadSlicePtrxE <= '0';
SlicePtrxD <= (others => '0');
wait for CLK_PERIOD;
tbStatus <= load_memptr;
LoadSlicePtrxE <= '1';
SlicePtrxD <= std_logic_vector(to_unsigned(3, PTRWIDTH));
tbStatus <= done;
WExE <= '0';
CfgSlicexD <= (others => '0');
LoadSlicePtrxE <= '0';
SlicePtrxD <= (others => '0');
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 3a38386d20fd8e013141122de4621980 | 0.488898 | 3.900561 | false | true | false | false |
quicky2000/top_test_sharp_screen | mire_screen.vhd | 1 | 3,395 | --
-- This file is part of top_test_sharp_screen
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mire_screen is
port (
clk : in std_logic; -- Clock input
rst : in std_logic;
clk_out : out std_logic;
vsync : out std_logic;
hsync : out std_logic;
enable : out std_logic;
r : out std_logic_vector ( 5 downto 0);
g : out std_logic_vector ( 5 downto 0);
b : out std_logic_vector ( 5 downto 0)
);
end mire_screen;
architecture behavorial of mire_screen is
constant THd : positive := 640; -- Width of display
constant TVd : positive := 480; -- Height of display
constant TH : positive := 800; -- Horizontal sync signal cycle width in clock cycle
constant THp : positive := 96; -- Horizontal sync signal pulse width in clock cyle
constant TVs : positive := 34; -- Vertical start period in clock cycle
constant TV : positive := 525; -- Vertical sync signal period in clock cycle
begin -- behavorial
clk_out <= clk;
process(clk,rst)
variable x_counter : positive range 1 to TH := 1; -- counter for x axis
variable y_counter : positive range 1 to TV := 1; -- counter for y axis
variable x : natural range 0 to THd := 0; -- x coordinate of active pixel
variable y : natural range 0 to TVd := 0; -- x coordinate of active pixel
begin
if rst = '1' then
x_counter := 1;
y_counter := 1;
vsync <= '0';
hsync <= '0';
enable <= '0';
r <= (others => '0');
g <= (others => '0');
b <= (others => '0');
x := 0;
y := 0;
elsif rising_edge(clk) then
if y_counter < 2 then
vsync <= '0';
else
vsync <= '1';
end if;
if x_counter < TH then
x_counter := x_counter + 1;
else
x_counter := 1;
if y_counter < TV then
y_counter := y_counter + 1;
else
y_counter := 1;
y := 0;
end if;
if y_counter > TVs and y < TVd then
y := y +1;
end if;
end if;
if x_counter <= THp then
hsync <= '0';
x := 0;
else
hsync <= '1';
if x < THd then
x := x + 1;
enable <= '1';
if x = 1 or x = 640 or y = 1 or y = 480 then
r <= (others => '1');
b <= (others => '0');
else
r <= (others => '0');
b <= (others => '1');
end if;
else
r <= (others => '0');
g <= (others => '0');
b <= (others => '0');
enable <= '0';
end if;
end if;
end if;
end process;
end behavorial;
| gpl-3.0 | 497c6c7e57fd34a5052fcd1cde294aea | 0.55081 | 3.67027 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstfir4/tb_tstfir4.vhd | 1 | 10,561 | ------------------------------------------------------------------------------
-- Testbench for the tstfir4 function of the zunit
--
-- Project :
-- File : tb_tstfir4.vhd
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/15
-- $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
-- $Id: tb_tstfir4.vhd 217 2005-01-13 16:52:03Z plessl $
------------------------------------------------------------------------------
-- This testbench tests the tstfir4 function of the zunit.
--
-- The primary goals of this testbench are:
-- test extension of cell to support 3 inputs (operands)
-- test ternary operators (mux is a ternary operator)
-- test the alu_mux function
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-28 CP created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTFIR4.all;
entity tb_tstfir4 is
end tb_tstfir4;
architecture arch of tb_tstfir4 is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- test vector and expected response
constant COEFS : coeff4array := (1,2,3,1);
constant NDATA : integer := 20; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type fifo_array is array (0 to NDATA-1) of natural;
constant TESTV : fifo_array :=
(1,0,0,1,2,0,0,2,3,0,0,3,1,0,0,1,0,0,0,0);
-- (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
constant EXPRESP : fifo_array :=
(1,2,3,2,4,7,7,4,7,12,11,6,7,11,6,2,2,3,1,0);
-- (1,2,3,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
-- configuration stuff
signal Cfg : engineConfigRec := tstfir4cfg(COEFS);
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstfir4_cfg.h";
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(DATAWIDTH-1 downto 0) <= std_logic_vector(to_unsigned(TESTV(i), DATAWIDTH));
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := std_logic_vector(to_unsigned(EXPRESP(i),DATAWIDTH));
response := DataOutxD(DATAWIDTH-1 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity note;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 9e6a51e3220c3bd2d4e7853ef52bbbef | 0.461888 | 3.940672 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/test_source_800_600_RGB_444_ch2.vhd | 1 | 13,944 | ----------------------------------------------------------------------------------
-- Module Name: test_source_800_600_RGB_444_ch2 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case 800x600 white screen.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-15 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test_source_800_600_RGB_444_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end test_source_800_600_RGB_444_ch2;
architecture arch of test_source_800_600_RGB_444_ch2 is
type a_test_data_blocks is array (0 to 64*6-1) of std_logic_vector(8 downto 0);
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0xAA
constant SPARE : std_logic_vector(8 downto 0) := "011111111"; -- 0xFF
constant ZERO : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant PIX_80 : std_logic_vector(8 downto 0) := "011001100"; -- 0x80
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant FS : std_logic_vector(8 downto 0) := "111111110"; -- K30.7
constant FE : std_logic_vector(8 downto 0) := "111110111"; -- K23.7
constant VB_VS : std_logic_vector(8 downto 0) := "000000001"; -- 0x00 VB-ID with Vertical blank asserted
constant VB_NVS : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 VB-ID without Vertical blank asserted
constant Mvid : std_logic_vector(8 downto 0) := "001101000"; -- 0x68
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant test_data_blocks : a_test_data_blocks := (
--- Block 0 - Junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 1 - 8 white pixels and padding
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
BS, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 5 - just blank end
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, BE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE);
signal index : unsigned (8 downto 0) := (others => '0'); -- Index up to 32 x 64 symbol blocks
signal d0: std_logic_vector(8 downto 0) := (others => '0');
signal d1: std_logic_vector(8 downto 0) := (others => '0');
signal line_count : unsigned(9 downto 0) := (others => '0');
signal row_count : unsigned(7 downto 0) := (others => '0');
signal switch_point : std_logic := '0';
begin
M_value <= x"012F68";
N_value <= x"080000";
H_visible <= x"320"; -- 800
V_visible <= x"258"; -- 600
H_total <= x"420"; -- 1056
V_total <= x"274"; -- 628
H_sync_width <= x"080"; -- 128
V_sync_width <= x"004"; -- 4
H_start <= x"0D8"; -- 216
V_start <= x"01b"; -- 37
H_vsync_active_high <= '0';
V_vsync_active_high <= '0';
flag_sync_clock <= '1';
flag_YCCnRGB <= '0';
flag_422n444 <= '0';
flag_range_reduced <= '0';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "010";
ready <= '1';
data(72) <= switch_point;
data(71 downto 36) <= (others => '0');
data(35 downto 18) <= d1 & d0;
data(17 downto 0) <= d1 & d0;
process(clk)
begin
if rising_edge(clk) then
d0 <= test_data_blocks(to_integer(index+0));
d1 <= test_data_blocks(to_integer(index+1));
if index(5 downto 0) = 52 then
index(5 downto 0) <= (others => '0');
if row_count = 131 then
row_count <= (others => '0');
if line_count = 627 then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
row_count <= row_count +1;
end if;
--- Block 0 - Junk
--- Block 1- 8 white pixels and padding
--- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
--- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
--- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
--- Block 5 - just blank end
index(8 downto 6) <= "000"; -- Dummy symbols
switch_point <= '0';
if line_count < 599 then -- lines of active video (except first and last)
if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE
elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill
elsif row_count = 100 then index(8 downto 6) <= "010"; -- Pixels BS and VS-ID block (no VBLANK flag)
end if;
elsif line_count = 599 then -- Last line of active video
if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE
elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill
elsif row_count = 100 then index(8 downto 6) <= "011"; -- Pixels BS and VS-ID block (with VBLANK flag)
end if;
else
-----------------------------------------------------------------
-- Allow switching to/from the idle pattern during the vertical blank
-----------------------------------------------------------------
if row_count < 100 then switch_point <= '1';
elsif row_count = 100 then index(8 downto 6) <= "100"; -- Dummy symbols, BS and VS-ID block (with VBLANK flag)
end if;
end if;
else
index <= index + 2;
end if;
end if;
end process;
end architecture; | mit | 8b78da4881b0f3252b2993d23e228f70 | 0.516495 | 3.691819 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/decoder.vhd | 1 | 2,410 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 10:13:01 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder is
Port (
instruction_in : in STD_LOGIC_VECTOR (7 downto 0);
s_exec_NOP, s_exec_STA, s_exec_LDA, s_exec_ADD, s_exec_OR, s_exec_SHR, s_exec_SHL, s_exec_MUL,
s_exec_AND, s_exec_NOT, s_exec_JMP, s_exec_JN, s_exec_JZ, s_exec_HLT : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
begin
-- 0000 -> NOP
-- 0001 -> STA
-- 0010 -> LDA
-- 0011 -> ADD
-- 0100 -> OR
-- 0101 -> AND
-- 0110 -> NOT
-- 0111 -> SHR
-- 1000 -> JMP
-- 1001 -> JN
-- 1010 -> JZ
-- 1011 -> SHL
-- 1100 -> MUL
-- 1111 -> HLT
process(instruction_in)
begin
s_exec_NOP <= '0';
s_exec_STA <= '0';
s_exec_LDA <= '0';
s_exec_ADD <= '0';
s_exec_OR <= '0';
s_exec_AND <= '0';
s_exec_NOT <= '0';
s_exec_JMP <= '0';
s_exec_JN <= '0';
s_exec_JZ <= '0';
s_exec_HLT <= '0';
s_exec_SHR <= '0';
s_exec_SHL <= '0';
s_exec_MUL <= '0';
if (instruction_in(7 downto 4) = "0000") then -- NOP
s_exec_NOP <= '1';
elsif (instruction_in(7 downto 4) = "0001") then -- STA
s_exec_STA <= '1';
elsif (instruction_in(7 downto 4) = "0010") then -- LDA
s_exec_LDA <= '1';
elsif (instruction_in(7 downto 4) = "0011") then -- ADD
s_exec_ADD <= '1';
elsif (instruction_in(7 downto 4) = "0100") then -- OR
s_exec_OR <= '1';
elsif (instruction_in(7 downto 4) = "0101") then -- AND
s_exec_AND <= '1';
elsif (instruction_in(7 downto 4) = "0110") then -- NOT
s_exec_NOT <= '1';
elsif (instruction_in(7 downto 4) = "1000") then -- JMP
s_exec_JMP <= '1';
elsif (instruction_in(7 downto 4) = "1001") then -- JN
s_exec_JN <= '1';
elsif (instruction_in(7 downto 4) = "1010") then -- JZ
s_exec_JZ <= '1';
elsif (instruction_in(7 downto 4) = "1111") then -- HLT
s_exec_HLT <= '1';
elsif (instruction_in(7 downto 4) = "0111") then -- SHR
s_exec_SHR <= '1';
elsif (instruction_in(7 downto 4) = "1011") then -- SHL
s_exec_SHL <= '1';
elsif (instruction_in(7 downto 4) = "1100") then -- MUL
s_exec_MUL <= '1';
end if;
end process;
end Behavioral; | mit | f41ad9de5597ef484ede81d199dbaf26 | 0.554772 | 2.518286 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpStream/unitMMtoST/hdl/MMtoST_tb.vhd | 1 | 7,343 | -------------------------------------------------------------------------------
-- Title : Avalon MM to Avalon ST Testbench
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Memory Mapped Slave to Avalon Streaming with Left and Right Channel
-- Used to stream audio data from the soc linux t the fpga
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity MMtoST_tb is
end entity MMtoST_tb;
-------------------------------------------------------------------------------
architecture Bhv of MMtoST_tb is
constant strobe_time_c : time := 1000 ns;
-- component generics
constant data_width_g : natural := 24;
constant fifo_depth_g : natural := 128;
constant fifo_adr_width_g : natural := 8;
-- address constants
constant control_c : std_logic_vector(1 downto 0) := "00";
constant fifospace_c : std_logic_vector(1 downto 0) := "01";
constant leftdata_c : std_logic_vector(1 downto 0) := "10";
constant rightdata_c : std_logic_vector(1 downto 0) := "11";
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal avs_s0_chipselect : std_logic;
signal avs_s0_write : std_logic;
signal avs_s0_read : std_logic;
signal avs_s0_address : std_logic_vector(1 downto 0);
signal avs_s0_writedata : std_logic_vector(31 downto 0);
signal avs_s0_readdata : std_logic_vector(31 downto 0);
signal irs_irq : std_logic;
signal asi_left_valid : std_logic;
signal asi_left_data : std_logic_vector(data_width_g-1 downto 0);
signal asi_right_valid : std_logic;
signal asi_right_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_left_valid : std_logic;
signal aso_left_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_right_valid : std_logic;
signal aso_right_data : std_logic_vector(data_width_g-1 downto 0);
begin -- architecture Bhv
-- component instantiation
DUT : entity work.MMtoST
generic map (
data_width_g => data_width_g,
fifo_depth_g => fifo_depth_g,
fifo_adr_width_g => fifo_adr_width_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
avs_s0_chipselect => avs_s0_chipselect,
avs_s0_write => avs_s0_write,
avs_s0_read => avs_s0_read,
avs_s0_address => avs_s0_address,
avs_s0_writedata => avs_s0_writedata,
avs_s0_readdata => avs_s0_readdata,
irs_irq => irs_irq,
asi_left_valid => asi_left_valid,
asi_left_data => asi_left_data,
asi_right_valid => asi_right_valid,
asi_right_data => asi_right_data,
aso_left_valid => aso_left_valid,
aso_left_data => aso_left_data,
aso_right_valid => aso_right_valid,
aso_right_data => aso_right_data);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
std_gen : process is
begin -- process std_gen
asi_left_valid <= '0';
asi_right_valid <= '0';
wait for strobe_time_c;
wait until rising_edge(csi_clk);
asi_left_valid <= '1';
wait until rising_edge(csi_clk);
asi_left_valid <= '0';
asi_right_valid <= '1';
wait until rising_edge(csi_clk);
asi_right_valid <= '0';
end process std_gen;
-- waveform generation
WaveGen_Proc : process
variable count_v : unsigned(data_width_g-1 downto 0) := (others => '0');
begin
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
asi_right_data <= std_logic_vector(count_v);
asi_left_data <= std_logic_vector(count_v);
wait until rising_edge(csi_clk);
avs_s0_chipselect <= '0';
avs_s0_write <= '0';
avs_s0_read <= '0';
avs_s0_address <= control_c;
avs_s0_writedata <= (others => '0');
wait until rising_edge(csi_clk);
avs_s0_chipselect <= '1';
avs_s0_address <= fifospace_c;
wait for 20 * strobe_time_c;
wait until rising_edge(csi_clk);
avs_s0_address <= control_c;
-- read interrupt enable
wait until rising_edge(csi_clk);
avs_s0_address <= control_c;
avs_s0_writedata <= (0 => '1', 1 => '0', others => '0');
avs_s0_write <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata <= (others => '0');
-- write data
wait until rising_edge(csi_clk);
avs_s0_address <= leftdata_c;
avs_s0_read <= '1';
wait until rising_edge(csi_clk);
avs_s0_read <= '0';
avs_s0_writedata <= (others => '1');
wait until rising_edge(csi_clk);
avs_s0_write <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
wait for 1000 ns;
for i in 0 to 1023 loop
wait until rising_edge(asi_right_valid);
asi_right_data <= std_logic_vector(count_v);
asi_left_data <= std_logic_vector(count_v);
-- read value and write back
wait until rising_edge(csi_clk);
avs_s0_address <= leftdata_c;
avs_s0_read <= '1';
wait until rising_edge(csi_clk);
avs_s0_read <= '0';
avs_s0_writedata <= avs_s0_readdata;
wait until rising_edge(csi_clk);
avs_s0_write <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
wait until rising_edge(csi_clk);
avs_s0_address <= rightdata_c;
avs_s0_read <= '1';
wait until rising_edge(csi_clk);
avs_s0_read <= '0';
avs_s0_writedata <= avs_s0_readdata;
wait until rising_edge(csi_clk);
avs_s0_write <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
count_v := count_v + 1;
end loop; -- i
-- check empty flag
for a in 0 to 30 loop
-- read value and write back
wait until rising_edge(csi_clk);
avs_s0_address <= leftdata_c;
avs_s0_read <= '1';
wait until rising_edge(csi_clk);
avs_s0_read <= '0';
avs_s0_writedata <= avs_s0_readdata;
wait until rising_edge(csi_clk);
avs_s0_write <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
wait until rising_edge(csi_clk);
avs_s0_address <= rightdata_c;
avs_s0_read <= '1';
wait until rising_edge(csi_clk);
avs_s0_read <= '0';
avs_s0_writedata <= avs_s0_readdata;
wait until rising_edge(csi_clk);
avs_s0_write <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
end loop; -- a
-- clear fifos
wait until rising_edge(csi_clk);
avs_s0_address <= control_c;
avs_s0_writedata <= (2 => '1', 3 => '1', others => '0');
avs_s0_write <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata <= (others => '0');
wait for 20 * strobe_time_c;
assert false report "End of simulation!" severity failure;
wait;
end process WaveGen_Proc;
end architecture Bhv;
-------------------------------------------------------------------------------
| gpl-3.0 | 6b0c9078e28ffeb19ac36e23ae521892 | 0.539834 | 3.272282 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/idle_pattern_inserter.vhd | 1 | 8,911 | ----------------------------------------------------------------------------------
-- Module Name: idle_pattern_inserter - Behavioral
--
-- Description: Cleanly switches from an internally generated idle pattern
-- and the input stream.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-19 | Expanded to four channels
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity idle_pattern_inserter is
port (
clk : in std_logic;
channel_ready : in std_logic;
source_ready : in std_logic;
in_data : in std_logic_vector(72 downto 0); -- Bit 72 is the switch point indicator
out_data : out std_logic_vector(71 downto 0) := (others => '0')
);
end entity;
architecture arch of idle_pattern_inserter is
signal count_to_switch : unsigned(16 downto 0) := (others => '0');
signal source_ready_last : std_logic := '0';
signal idle_switch_point : std_logic := '0';
signal idle_count : unsigned(12 downto 0) := (others => '0');
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0x3
constant VB_ID : std_logic_vector(8 downto 0) := "000001001"; -- 0x09 VB-ID with no video asserted
constant Mvid : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
signal idle_data: std_logic_vector(17 downto 0) := (others => '0');
signal channel_ready_i : std_logic;
signal channel_ready_meta : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if count_to_switch(16) = '1' then
out_data <= in_data(71 downto 0);
else
-- send idle pattern
out_data <= idle_data & idle_data & idle_data & idle_data;
end if;
if count_to_switch(16) = '0' then
-- The last tick over requires the source to be ready
-- and to be asserting that it is in the switch point.
if count_to_switch(15 downto 0) = x"FFFF" then
-- Bit 72 is the switch point indicator
if source_ready = '1' and in_data(72)= '1' and idle_switch_point = '1' then
count_to_switch <= count_to_switch + 1;
end if;
else
-- Wait while we send out at least 64k of idle patterns
count_to_switch <= count_to_switch + 1;
end if;
end if;
------------------------------------------------------------------------
-- If either the source drops or the channel is not ready, then reset
-- to emitting the idle pattern.
------------------------------------------------------------------------
if channel_ready_i = '0' or (source_ready = '0' and source_ready_last = '1') then
count_to_switch <= (others => '0');
end if;
source_ready_last <= source_ready;
-------------------------------------------------------------------------------
-- We can either be odd or even aligned, depending on where the last BS symbol
-- was seen. We need to send the next one 8192 symbols later (4096 cycles)
-------------------------------------------------------------------------------
idle_switch_point <= '0';
-- For the even aligment
if idle_count = 0 then
idle_data <= DUMMY & DUMMY;
elsif idle_count = 2 then
idle_data <= VB_ID & BS;
elsif idle_count = 4 then
idle_data <= Maud & Mvid;
elsif idle_count = 6 then
idle_data <= Mvid & VB_ID ;
elsif idle_count = 8 then
idle_data <= VB_ID & Maud;
elsif idle_count = 10 then
idle_data <= Maud & Mvid;
elsif idle_count = 12 then
idle_data <= Mvid & VB_ID;
elsif idle_count = 14 then
idle_data <= DUMMY & Maud;
-- For the odd aligment
elsif idle_count = 1 then
idle_data <= BS & DUMMY;
elsif idle_count = 3 then
idle_data <= Mvid & VB_ID;
elsif idle_count = 5 then
idle_data <= VB_ID & Maud;
elsif idle_count = 7 then
idle_data <= Maud & Mvid;
elsif idle_count = 9 then
idle_data <= Mvid & VB_ID;
elsif idle_count = 11 then
idle_data <= VB_ID & Maud;
elsif idle_count = 12 then
idle_data <= Mvid & VB_ID;
elsif idle_count = 13 then
idle_data <= Maud & Mvid;
elsif idle_count = 15 then
idle_data <= DUMMY & DUMMY;
else
idle_data <= DUMMY & DUMMY; -- can switch to the actual video at any other time
idle_switch_point <= '1'; -- other than when the BS, VB-ID, Mvid, Maud sequence
end if;
idle_count <= idle_count + 2;
-------------------------------------------------------
-- Sync with thE BS stream of the input signal but only
-- if we are switched over to it (indicated by the high
-- bit of count_to_switch being set)
-------------------------------------------------------
if count_to_switch(16) = '1' then
if in_data(8 downto 0) = BS then
idle_count <= to_unsigned(2,idle_count'length);
elsif in_data(17 downto 9) = BS then
idle_count <= to_unsigned(1,idle_count'length);
end if;
end if;
channel_ready_i <= channel_ready_meta;
channel_ready_meta <= channel_ready;
end if;
end process;
end architecture; | mit | aaa605d0e5c73d4584519f325487d822 | 0.474694 | 4.576785 | false | false | false | false |
plessl/zippy | cosim/cosim.vhd | 1 | 3,767 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- DUT (define in zunit.vhd)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- CLK GENERATOR
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity clkdrv is
port (
ClkxC : out std_logic
);
end clkdrv;
architecture arch of clkdrv is
begin -- arch
clkgen : process
begin
ClkxC <= '0';
wait for 50 ns;
ClkxC <= '1';
wait for 50 ns;
end process;
end arch;
-------------------------------------------------------------------------------
-- DRIVER
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity driver is
port(
WExEI : out bit;
RExEI : out bit;
DataxDI : out integer;
DataxDO : in integer;
AddrxDI : out natural
);
end driver;
architecture arch of driver is
attribute foreign : string;
attribute foreign of arch : architecture is "server_init server.so";
begin
end arch;
-------------------------------------------------------------------------------
-- TESTBENCH
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.archConfigPkg.all;
use work.ZarchPkg.all;
use work.ComponentsPkg.all;
entity verification is
end verification;
architecture arch of verification is
component driver
port(
WExEI : out bit;
RExEI : out bit;
DataxDI : out integer;
DataxDO : in integer;
AddrxDI : out integer
);
end component;
component clkdrv
port (
ClkxC : out std_logic
);
end component;
signal ClkxC : std_logic := '0';
signal RstxRB : std_logic := '0';
signal FromDriver_DataxDI : integer := 0;
signal FromDriver_AddrxDI : natural := 0;
signal ToDriver_DataxDO : integer := 0;
signal FromDriver_WExEI : bit := '0';
signal FromDriver_RExEI : bit := '0';
signal ToDut_DataxDI : std_logic_vector(IFWIDTH-1 downto 0) := (others => '0');
signal ToDut_AddrxDI : std_logic_vector(IFWIDTH-1 downto 0) := (others => '0');
signal FromDut_DataxDO : std_logic_vector(IFWIDTH-1 downto 0) := (others => '0');
signal ToDut_WExEI : std_logic := '0';
signal ToDut_RExEI : std_logic := '0';
begin
RstxRB <= '0', '1' after 1 ns;
i_dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
WExEI => ToDut_WExEI,
RExEI => ToDut_RExEI,
DataxDI => ToDut_DataxDI, -- std_logic_vector
DataxDO => FromDut_DataxDO, -- std_logic_vector
AddrxDI => ToDut_AddrxDI, -- std_logic_vector
ClkxC => ClkxC,
RstxRB => RstxRB
);
i_driver : driver
port map (
WExEI => FromDriver_WExEI,
RExEI => FromDriver_RExEI,
DataxDI => FromDriver_DataxDI, -- integer
DataxDO => ToDriver_DataxDO, -- integer
AddrxDI => FromDriver_AddrxDI -- natural
);
i_clkdrv : clkdrv
port map (
ClkxC => ClkxC);
ToDut_DataxDI <= std_logic_vector(TO_SIGNED(FromDriver_DataxDI, IFWIDTH));
ToDut_AddrxDI <= std_logic_vector(TO_UNSIGNED(FromDriver_AddrxDI, IFWIDTH));
ToDriver_DataxDO <= TO_INTEGER(signed(FromDut_DataxDO));
ToDut_WExEI <= to_stdulogic(FromDriver_WExEI);
ToDut_RExEI <= to_stdulogic(FromDriver_RExEI);
end arch;
| bsd-3-clause | 4884cae39278044fd9ba501b3331ecc6 | 0.503318 | 3.952781 | false | false | false | false |
huljar/present-vhdl | src/sbox.vhd | 1 | 1,090 | library ieee;
use ieee.std_logic_1164.all;
entity sbox is
port(data_in: in std_logic_vector(3 downto 0);
data_out: out std_logic_vector(3 downto 0)
);
end sbox;
architecture behavioral of sbox is
begin
process(data_in)
begin
case data_in is
when x"0" => data_out <= x"C";
when x"1" => data_out <= x"5";
when x"2" => data_out <= x"6";
when x"3" => data_out <= x"B";
when x"4" => data_out <= x"9";
when x"5" => data_out <= x"0";
when x"6" => data_out <= x"A";
when x"7" => data_out <= x"D";
when x"8" => data_out <= x"3";
when x"9" => data_out <= x"E";
when x"A" => data_out <= x"F";
when x"B" => data_out <= x"8";
when x"C" => data_out <= x"4";
when x"D" => data_out <= x"7";
when x"E" => data_out <= x"1";
when x"F" => data_out <= x"2";
when others => null; -- GHDL complains without this statement
end case;
end process;
end behavioral;
| mit | 07ae034dab2b389f9f5897db86312889 | 0.458716 | 3.114286 | false | false | false | false |
huljar/present-vhdl | src/present_top.vhd | 1 | 2,908 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity present_top is
generic(k: key_enum);
port(plaintext: in std_logic_vector(63 downto 0);
key: in std_logic_vector(key_bits(k)-1 downto 0);
clk: in std_logic;
reset: in std_logic;
ciphertext: out std_logic_vector(63 downto 0)
);
end present_top;
architecture behavioral of present_top is
signal data_state,
data_key_added,
data_substituted,
data_permuted: std_logic_vector(63 downto 0);
signal key_state,
key_updated: std_logic_vector(key_bits(k)-1 downto 0);
signal round_counter: std_logic_vector(4 downto 0);
component sub_layer
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component perm_layer
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component key_schedule
generic(k: key_enum);
port(data_in: in std_logic_vector(key_bits(k)-1 downto 0);
round_counter: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(key_bits(k)-1 downto 0)
);
end component;
begin
SL: sub_layer port map(
data_in => data_key_added,
data_out => data_substituted
);
PL: perm_layer port map(
data_in => data_substituted,
data_out => data_permuted
);
KS: key_schedule generic map(
k => k
) port map(
data_in => key_state,
round_counter => round_counter,
data_out => key_updated
);
data_key_added <= data_state xor key_state(key_bits(k)-1 downto key_bits(k)-64);
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
data_state <= plaintext;
key_state <= key;
round_counter <= "00001";
ciphertext <= (others => '0');
else
data_state <= data_permuted;
key_state <= key_updated;
round_counter <= std_logic_vector(unsigned(round_counter) + 1);
-- when we are "past" the final round, i.e. the 31st round was finished,
-- the round counter addition overflows back to zero. Now set the output
-- signal to the ciphertext.
case round_counter is
when "00000" => ciphertext <= data_key_added;
when others => ciphertext <= (others => '0');
end case;
--if round_counter = "00000" then
-- ciphertext <= data_key_added;
--end if;
end if;
end if;
end process;
end behavioral;
| mit | 794b67f6be13cd2ca2b4039527127238 | 0.541609 | 3.861886 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/Tbd/hdl/TbdFIR-Struct-a.vhd | 1 | 1,355 | architecture Struct of TbdFIR is
component Audio is
port (
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_clk : in std_logic := 'X'; -- clk
audio_clk_clk : out std_logic; -- clk
i2s_adcdat : in std_logic := 'X'; -- adcdat
i2s_adclrck : in std_logic := 'X'; -- adclrck
i2s_bclk : in std_logic := 'X'; -- bclk
i2s_dacdat : out std_logic; -- dacdat
i2s_daclrck : in std_logic := 'X'; -- daclrck
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic -- SCLK
);
end component Audio;
begin -- architecture Struct
u0 : component Audio
port map (
reset_reset_n => KEY(0), -- reset.reset_n
clk_clk => CLOCK_50, -- clk.clk
audio_clk_clk => AUD_XCK, -- audio_clk.clk
i2s_adcdat => AUD_ADCDAT, -- i2s.adcdat
i2s_adclrck => AUD_ADCLRCK, -- .adclrck
i2s_bclk => AUD_BCLK, -- .bclk
i2s_dacdat => AUD_DACDAT, -- .dacdat
i2s_daclrck => AUD_DACLRCK, -- .daclrck
i2c_SDAT => FPGA_I2C_SDAT, -- i2c.SDAT
i2c_SCLK => FPGA_I2C_SCLK -- .SCLK
);
end architecture Struct;
| gpl-3.0 | 999753777930ad397fb708a17bdf34d4 | 0.461255 | 3.188235 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/insert_main_stream_attrbutes_two_channels.vhd | 1 | 13,448 | ----------------------------------------------------------------------------------
-- Module Name: insert_main_stream_attrbutes_two_channels.vhd - Behavioral
--
-- Description: Add the Main Stream Attributes into a DisplayPort stream.
--
-- Places the MSA after the first VIB-ID which has the vblank
-- bit set (after allowing for repeated VB-ID/Mvid/Maud sequences
--
-- The MSA requires up to 39 cycles (for signal channel) or
-- Only 12 cycles (for four channels).
--
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity insert_main_stream_attrbutes_two_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flag_YCC_colour_709 : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0) := (others => '0'));
end entity;
architecture arch of insert_main_stream_attrbutes_two_channels is
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
type t_msa is array(0 to 39) of std_logic_vector(8 downto 0);
signal msa : t_msa := (others => (others => '0'));
signal Misc0 : std_logic_vector(7 downto 0);
signal Misc1 : std_logic_vector(7 downto 0);
signal count : signed(4 downto 0) := (others => '0');
signal last_was_bs : std_logic := '0';
signal armed : std_logic := '0';
begin
with bits_per_colour select misc0(7 downto 5)<= "000" when "00110", -- 6 bpc
"001" when "01000", -- 8 bpp
"010" when "01010", -- 10 bpp
"011" when "01100", -- 12 bpp
"100" when "10000", -- 16 bpp
"001" when others; -- default to 8
misc0(4) <= flag_YCC_colour_709;
misc0(3) <= flag_range_reduced;
misc0(2 downto 1) <= "00" when flag_YCCnRGB = '0' else -- RGB444
"01" when flag_422n444 = '1' else -- YCC422
"10"; -- YCC444
misc0(0) <= flag_sync_clock;
misc1 <= "00000" & flags_3d_Indicators & flag_interlaced_even;
--------------------------------------------
-- Build data fields for 4 lane case.
-- SS and SE symbols are set in declaration.
--------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- default to copying the input data across
out_data <= in_data;
case count is
when "00000" => NULL; -- while waiting for BS symbol
when "00001" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00010" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00011" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00100" => out_data(17 downto 0) <= SS & SS;
when "00101" => out_data(17 downto 0) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "00110" => out_data(17 downto 0) <= "0" & "0000" & H_total(11 downto 8) & "0" & M_value( 7 downto 0);
when "00111" => out_data(17 downto 0) <= "0" & "0000" & V_total(11 downto 8) & "0" & H_total( 7 downto 0);
when "01000" => out_data(17 downto 0) <= "0" & H_vsync_active_high & "000" & H_sync_width(11 downto 8) & "0" & V_total( 7 downto 0);
when "01001" => out_data(17 downto 0) <= "0" & M_value(23 downto 16) & "0" & H_sync_width(7 downto 0);
when "01010" => out_data(17 downto 0) <= "0" & M_value( 7 downto 0) & "0" & M_value(15 downto 8);
when "01011" => out_data(17 downto 0) <= "0" & H_visible( 7 downto 0) & "0" & "0000" & H_visible(11 downto 8);
when "01100" => out_data(17 downto 0) <= "0" & V_visible( 7 downto 0) & "0" & "0000" & V_visible(11 downto 8);
when "01101" => out_data(17 downto 0) <= "0" & "00000000" & "0" & "00000000";
when "01110" => out_data(17 downto 0) <= "0" & "00000000" & SE;
when others => NULL;
end case;
case count is
when "00000" => NULL; -- while waiting for BS symbol
when "00001" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00010" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00011" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00100" => out_data(35 downto 18) <= SS & SS;
when "00101" => out_data(35 downto 18) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "00110" => out_data(35 downto 18) <= "0" & "0000" & H_Start(11 downto 8) & "0" & M_value( 7 downto 0);
when "00111" => out_data(35 downto 18) <= "0" & "0000" & V_start(11 downto 8) & "0" & H_start( 7 downto 0);
when "01000" => out_data(35 downto 18) <= "0" & V_vsync_active_high & "000" & V_sync_width(11 downto 8) & "0" & V_start( 7 downto 0);
when "01001" => out_data(35 downto 18) <= "0" & M_value(23 downto 16) & "0" & V_sync_width(7 downto 0);
when "01010" => out_data(35 downto 18) <= "0" & M_value( 7 downto 0) & "0" & M_value(15 downto 8);
when "01011" => out_data(35 downto 18) <= "0" & N_value(15 downto 8) & "0" & N_value(23 downto 16);
when "01100" => out_data(35 downto 18) <= "0" & Misc0 & "0" & N_value( 7 downto 0);
when "01101" => out_data(35 downto 18) <= "0" & "00000000" & "0" & Misc1;
when "01110" => out_data(35 downto 18) <= "0" & "00000000" & SE;
when others => NULL;
end case;
-----------------------------------------------------------
-- Update the counter
------------------------------------------------------------
if count = "01110" then
count <= (others => '0');
elsif count /= "00000" then
count <= count + 1;
end if;
---------------------------------------------
-- Was the BS in the channel 0's data1 symbol
-- during the last cycle?
---------------------------------------------
if last_was_bs = '1' then
---------------------------------
-- This time in_ch0_data0 = VB-ID
-- First, see if this is a line in
-- the VSYNC
---------------------------------
if in_data(0) = '1' then
if armed = '1' then
count <= "00001";
armed <= '0';
end if;
else
-- Not in the Vblank. so arm the trigger to send the MSA
-- when the next BS with Vblank asserted occurs
armed <= active;
end if;
end if;
---------------------------------------------
-- Is the BS in the channel 0's data0 symbol?
---------------------------------------------
if in_data(8 downto 0) = BS then
---------------------------------
-- This time in_data(17 downto 9) = VB-ID
-- First, see if this is a line in
-- the VSYNC
---------------------------------
if in_data(9) = '1' then
if armed = '1' then
count <= "00001";
armed <= '0';
end if;
else
-- Not in the Vblank. so arm the trigger to send the MSA
-- when the next BS with Vblank asserted occurs
armed <= '1';
end if;
end if;
---------------------------------------------
-- Is the BS in the channel 0's data1 symbol?
---------------------------------------------
if in_data(17 downto 9) = BS then
last_was_bs <= '1';
else
last_was_bs <= '0';
end if;
end if;
end process;
end architecture;
| mit | 041d907ee35979c0fcc92ffc4e8c61a9 | 0.427127 | 4.338065 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstrom/tb_tstrom.vhd | 1 | 9,763 | ------------------------------------------------------------------------------
-- Testbench for the alu_rom function of the zunit
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/tb_arch/tstrom/tb_tstrom.vhd $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/11/16
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- This testbench tests the alu_rom function of the zunit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTROM.all;
entity tb_tstrom is
end tb_tstrom;
architecture arch of tb_tstrom is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 20; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec := tstromcfg;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstrom_cfg.h";
type fifo_array is array (0 to NDATA-1) of integer;
type nat_array is array (0 to NDATA-1) of integer;
-----------------------------------------------------------------------------
-- test vectors
-- out = a or b
-- array contains: contents for fifo0, contents for fifo1, expected result
-----------------------------------------------------------------------------
constant TESTV : nat_array :=
(
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
);
constant EXPRES : fifo_array :=
(
1, -2, 3, -5, 7,
-11, 13, -17, 19, -23,
29, -31, 37, -41, 43,
-47, 53, -59, 61, -67
);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : integer;
variable expectedresponse : integer;
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- -----------------------------------------------
-- reset (ZREG_RST:W)
-- -----------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-- -----------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(DATAWIDTH-1 downto 0) <=
std_logic_vector(to_unsigned(TESTV(i),DATAWIDTH));
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-- -----------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-- -----------------------------------------------
-- computation running
-- -----------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
-- -----------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-- -----------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := EXPRES(i);
response := to_integer(signed(DataOutxD(DATAWIDTH-1 downto 0)));
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & str(response) &
" does NOT match expected response "
& str(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & str(response) & " matches expected " &
"response " & str(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- -----------------------------------------------
-- done; stop simulation
-- -----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & str(cycle) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 2d9bb48eb5ea75a7dbf012f68df5e078 | 0.453754 | 4.009446 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/vga_to_dp_stream/pixel_receiver.vhd | 1 | 18,622 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:32:01 10/12/2015
-- Design Name:
-- Module Name: pixel_receiver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pixel_receiver is
Port ( pixel_clk : in STD_LOGIC;
pixel_data : in STD_LOGIC_VECTOR (23 downto 0);
pixel_hblank : in STD_LOGIC;
pixel_hsync : in STD_LOGIC;
pixel_vblank : in STD_LOGIC;
pixel_vsync : in STD_LOGIC;
--------------------------------------------------
-- These should be stable when ready is asserted
--------------------------------------------------
h_visible : in STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
dp_clk : in STD_LOGIC;
ch0_data_0 : out STD_LOGIC_VECTOR (8 downto 0);
ch0_data_1 : out STD_LOGIC_VECTOR (8 downto 0));
end pixel_receiver;
architecture Behavioral of pixel_receiver is
constant BLANK_END : std_logic_vector(8 downto 0) := "111111011"; -- 0x1FB
constant BLANK_START : std_logic_vector(8 downto 0) := "110111100"; -- 0x1BC
constant FILL_END : std_logic_vector(8 downto 0) := "111110111"; -- 0x1F7
constant FILL_START : std_logic_vector(8 downto 0) := "111111110"; -- 0x1FE
constant VBID : std_logic_vector(8 downto 0) := "000000000"; -- 0x1FE
constant Mvid : std_logic_vector(8 downto 0) := "000000001"; -- 0x1FE
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x1FE
constant dummy : std_logic_vector(8 downto 0) := "000001111"; -- 0x00F
constant use_Zero : std_logic_vector(3 downto 0) := "0000";
constant use_data : std_logic_vector(3 downto 0) := "0001";
constant use_BE : std_logic_vector(3 downto 0) := "0010";
constant use_BS : std_logic_vector(3 downto 0) := "0011";
constant use_FS : std_logic_vector(3 downto 0) := "0100";
constant use_FE : std_logic_vector(3 downto 0) := "0101";
constant use_VBID : std_logic_vector(3 downto 0) := "0110";
constant use_MVID : std_logic_vector(3 downto 0) := "0111";
constant use_MAUD : std_logic_vector(3 downto 0) := "1000";
component memory_32x36_r128x9 is
Port ( clk_a : in STD_LOGIC;
data_a : in STD_LOGIC_VECTOR (35 downto 0);
addr_a : in STD_LOGIC_VECTOR (4 downto 0);
we_a : in STD_LOGIC;
clk_bc : in STD_LOGIC;
addr_b : in STD_LOGIC_VECTOR (6 downto 0);
data_b_0 : out STD_LOGIC_VECTOR (8 downto 0);
data_b_1 : out STD_LOGIC_VECTOR (8 downto 0));
end component;
constant TU_SIZE : natural := 54;
constant DATA_PER_TU : natural := 24;
-----------------------------
-- In the pixel clock domain
-----------------------------
signal pc_mem_data_formatted : std_logic_vector(35 downto 0) := (others => '0');
signal pc_mem_we : std_logic := '0';
signal pc_mem_addr : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
signal pc_line_start_toggle : std_logic := '0';
signal pixel_blank : std_logic := '0';
signal pc_hblank_last : std_logic := '0';
-----------------------------
-- Between clock domain
-----------------------------
signal line_start_toggle_meta_0p0 : std_logic := '0';
signal line_start_toggle_meta_0p5 : std_logic := '0';
signal vblank_meta : std_logic := '0';
----------------------------------
-- In the DisplayPort clock domain
----------------------------------
signal dp_output_selector : STD_LOGIC_VECTOR(7 downto 0);
signal dp_line_start_toggle_last : std_logic := '0';
signal dp_line_start_toggle_0p0 : std_logic := '0';
signal dp_line_start_toggle_0p5 : std_logic := '0';
signal dp_sending : std_logic := '0';
signal dp_mem_addr : STD_LOGIC_VECTOR(6 downto 0) := (others => '0');
signal dp_word_in_tu : unsigned(5 downto 0) := (others => '0');
signal dp_countdown_to_start : unsigned(5 downto 0) := (others => '0');
signal dp_pixels_sent : unsigned(11 downto 0) := (others => '0');
signal dp_mem_data_ch0_0 : STD_LOGIC_VECTOR(8 downto 0) := (others => '0');
signal dp_mem_data_ch0_1 : STD_LOGIC_VECTOR(8 downto 0) := (others => '0');
signal dp_vblank : std_logic := '0';
signal dp_send_vbid_count : unsigned(3 downto 0) := (others => '0');
begin
pixel_blank <= pixel_hblank or pixel_vblank;
ch0_buffer: memory_32x36_r128x9 port map (
clk_a => pixel_clk,
addr_a => pc_mem_addr,
data_a => pc_mem_data_formatted,
we_a => pc_mem_we,
clk_bc => dp_clk,
addr_b => dp_mem_addr,
data_b_0 => dp_mem_data_ch0_0,
data_b_1 => dp_mem_data_ch0_1
);
data_transfer_proc: process(pixel_clk)
begin
--------------------------------
-- Just write all the pixels to
-- memory, but reset address to
-- zero when hbank drops.
--------------------------------
if rising_edge(pixel_clk) then
pc_mem_data_formatted <= (others => '0');
pc_mem_data_formatted( 8 downto 0) <= pixel_blank & pixel_data( 7 downto 0);
pc_mem_data_formatted(17 downto 9) <= pixel_blank & pixel_data(15 downto 8);
pc_mem_data_formatted(26 downto 18) <= pixel_blank & pixel_data(23 downto 16);
pc_mem_we <= '1';
pc_mem_addr <= std_logic_vector(unsigned(pc_mem_addr)+ 1);
if pc_hblank_last = '1' and pixel_hblank = '0' then
---------------------------------------------
-- Reset the write address, so the DP side an
-- sync up in 64 DisplayPort cycles
---------------------------------------------
pc_mem_addr <= (others => '0');
---------------------------------------------
-- Signal to the DP domain that we have
-- started receiving a new line
---------------------------------------------
pc_line_start_toggle <= not pc_line_start_toggle;
end if;
pc_hblank_last <= pixel_hblank;
end if;
end process;
process(dp_clk)
begin
if falling_edge(dp_clk) then
line_start_toggle_meta_0p5 <= pc_line_start_toggle;
end if;
if rising_edge(dp_clk) then
---------------------------------------
-- This can just be continually updated.
-- It might get ovewritten later on
---
-- (and relies on delayed asignments to
-- work).
---------------------------------------
dp_word_in_tu <= dp_word_in_tu + 2;
------------------------------------------------------------
-- The tricky bits - advancing the memory address
-- for the dual ported RAMs. Once again relies on
-- delayed assignments to work.
--
-- Option 1: Advance by two. When two data words are sent
-- Option 2: Advance by one. When only one data word is sent
-- Option 3: No advancing
------------------------------------------------------------
if dp_countdown_to_start = 2 then
-- Set to 0
dp_mem_addr <= (0=>'0', others => '1');
elsif dp_countdown_to_start = 1 then -- BE followed with data
-- Set to -1;
dp_mem_addr <= (others => '1');
elsif dp_word_in_tu = DATA_PER_TU-1 or -- Data follows by BE or FS
dp_word_in_tu = TU_SIZE-1 then -- FE followed with first data of new TU
-- Advance by one, skipping over the adresses that end in "11"
if dp_mem_addr( 1 downto 0) = "10" then
dp_mem_addr <= std_logic_vector(unsigned(dp_mem_addr) + 2);
dp_pixels_sent <= dp_pixels_sent + 1;
else
dp_mem_addr <= std_logic_vector(unsigned(dp_mem_addr) + 1);
end if;
elsif dp_word_in_tu < DATA_PER_TU-1 then
-- Advance by two, skipping over the adresses that end in "11"
if dp_mem_addr( 1 downto 0) = "01" or dp_mem_addr( 1 downto 0) = "10" then
dp_mem_addr <= std_logic_vector(unsigned(dp_mem_addr) + 3);
else
dp_mem_addr <= std_logic_vector(unsigned(dp_mem_addr) + 2);
dp_pixels_sent <= dp_pixels_sent + 1;
end if;
end if;
---------------------------------
-- Set the output for this cycle
---------------------------------
case dp_output_selector(3 downto 0) is
when use_BE => ch0_data_0 <= BLANK_END;
when use_data => ch0_data_0 <= dp_mem_data_ch0_0;
when use_BS => ch0_data_0 <= BLANK_START;
when use_FS => ch0_data_0 <= FILL_START;
when use_FE => ch0_data_0 <= FILL_END;
when use_VBID => ch0_data_0 <= VBID;
when use_Mvid => ch0_data_0 <= Mvid;
when use_Maud => ch0_data_0 <= Maud;
when others => ch0_data_0 <= "000000000";
end case;
case dp_output_selector(7 downto 4) is
when use_BE => ch0_data_1 <= BLANK_END;
when use_data => ch0_data_1 <= dp_mem_data_ch0_1;
when use_BS => ch0_data_1 <= BLANK_START;
when use_FS => ch0_data_1 <= FILL_START;
when use_FE => ch0_data_1 <= FILL_END;
when use_VBID => ch0_data_1 <= VBID;
when use_Mvid => ch0_data_1 <= Mvid;
when use_Maud => ch0_data_0 <= Maud;
when others => ch0_data_1 <= "000000000";
end case;
---------------------------------
-- Default to sending 00F
---------------------------------
dp_output_selector <= use_Zero & use_Zero;
---------------------------------------
-- Do we need to set up for a new line?
---------------------------------------
if dp_line_start_toggle_0p0 /= dp_line_start_toggle_last then
-- Starting in the first alignment
dp_countdown_to_start <= to_unsigned(TU_SIZE-2,6);
dp_sending <= '0';
elsif dp_line_start_toggle_0p5 /= dp_line_start_toggle_0p0 then
-- Starting in the other alignment
dp_countdown_to_start <= to_unsigned(TU_SIZE-1,6);
dp_sending <= '0';
end if;
if dp_countdown_to_start = 2 then
if dp_vblank = '0' then
dp_output_selector <= use_BE & use_Zero;
end if;
dp_sending <= '1';
dp_mem_addr <= (others => '1'); -- NOTE -1
dp_word_in_tu <= (others => '0');
dp_pixels_sent <= (others => '0');
dp_countdown_to_start <= dp_countdown_to_start - 2;
elsif dp_countdown_to_start = 1 then
if dp_vblank = '0' then
dp_output_selector <= use_data & use_BE;
end if;
dp_sending <= '1';
dp_mem_addr <= (others => '1'); -- NOTE -1
dp_word_in_tu <= (1=>'1',others => '0');
dp_pixels_sent <= (others => '0');
dp_countdown_to_start <= dp_countdown_to_start - 2;
elsif dp_countdown_to_start > 0 then
dp_countdown_to_start <= dp_countdown_to_start - 2;
end if;
if dp_sending = '1' then
if dp_word_in_tu < DATA_PER_TU then
if dp_vblank = '0' then
dp_output_selector <= use_Data & use_Data;
end if;
elsif dp_word_in_tu = DATA_PER_TU then
-----------------------------------
-- Did we just send the last active
-- pixe data for the line?
-----------------------------------
if dp_pixels_sent = unsigned(h_visible) then
----------------------------------
-- Yes, start the blanking interval
----------------------------------
dp_output_selector <= use_VBID & use_BS;
dp_sending <= '0';
dp_send_vbid_count <= "1011";
else
-----------------------------------
-- No, we need to add fill sequence
-- However there are three different
-- options depending on how much of
-- the TU is holding active data.
-----------------------------------
if dp_vblank = '0' then
if DATA_PER_TU = TU_SIZE-1 then
dp_output_selector <= use_Data & use_FE;
elsif DATA_PER_TU = TU_SIZE-2 then
dp_output_selector <= use_FE & use_FS;
else
dp_output_selector <= use_Zero & use_FS;
end if;
end if;
end if;
elsif dp_word_in_tu = DATA_PER_TU-1 then
-----------------------------------
-- Did we just send the last active
-- pixe data for the line?
-----------------------------------
if dp_pixels_sent = unsigned(h_visible)-1 then
----------------------------------
-- Yes, start the blaning interval
----------------------------------
dp_output_selector <= use_BS & use_DATA;
dp_sending <= '0';
else
-----------------------------------
-- No, we need to add fill sequence
--
-- Only one special case when all but
-- one word in the TU is used for active
-- data - the FS must be replaced with a a FE
-----------------------------------
if dp_vblank = '0' then
if DATA_PER_TU = TU_SIZE-1 then
dp_output_selector <= use_FS & use_DATA;
else
dp_output_selector <= use_FE & use_DATA;
end if;
end if;
end if;
elsif dp_word_in_tu = TU_SIZE-2 then
if dp_vblank = '0' then
dp_output_selector <= use_FS & use_Zero;
end if;
elsif dp_word_in_tu = TU_SIZE-1 then
if dp_vblank = '0' then
dp_output_selector <= use_DATA & use_FS;
end if;
end if;
end if;
case dp_send_vbid_count is
when "1100" => dp_output_selector <= use_Mvid & use_VBID;
when "1011" => dp_output_selector <= use_Maud & use_Mvid;
when "1010" => dp_output_selector <= use_VBID & use_Maud;
when "1001" => dp_output_selector <= use_Mvid & use_VBID;
when "1000" => dp_output_selector <= use_Maud & use_Mvid;
when "0111" => dp_output_selector <= use_VBID & use_Maud;
when "0110" => dp_output_selector <= use_Mvid & use_VBID;
when "0101" => dp_output_selector <= use_Maud & use_Mvid;
when "0100" => dp_output_selector <= use_VBID & use_Maud;
when "0011" => dp_output_selector <= use_Mvid & use_VBID;
when "0010" => dp_output_selector <= use_Maud & use_Mvid;
when "0001" => dp_output_selector <= use_zero & use_Maud;
when others => NULL;
end case;
--------------------------------------------------
-- Deciding when to send VBID and how much to send
--------------------------------------------------
if dp_sending = '1' then
----------------------------------------
-- Assuming one active channel, so send
-- VBID, MVID and MAUD 4 times.
--
-- WHen dp_word_in_tu is even, the first
-- VBID is sent in the same transfer as
-- the BS symbol, so we don't need it
----------------------------------------
if dp_word_in_tu = DATA_PER_TU then
dp_send_vbid_count <= "1011";
elsif dp_word_in_tu = DATA_PER_TU - 1 then
dp_send_vbid_count <= "1100";
end if;
elsif dp_send_vbid_count > 1 then
dp_send_vbid_count <= dp_send_vbid_count - 2;
else
dp_send_vbid_count <= (others => '0');
end if;
-------------------------------------
-- Remeber the state of the toggle,
-- to see when a new line has started
-------------------------------------
dp_line_start_toggle_last <= dp_line_start_toggle_0p0;
---------------------------------------------------------------
-- Bring the linestart toggle into the DisplayPort clock domain
---------------------------------------------------------------
dp_line_start_toggle_0p0 <= line_start_toggle_meta_0p0;
dp_line_start_toggle_0p5 <= line_start_toggle_meta_0p5;
line_start_toggle_meta_0p0 <= pc_line_start_toggle;
dp_vblank <= vblank_meta;
vblank_meta <= pixel_vblank;
end if;
end process;
end Behavioral;
| mit | f662482ad03cc1b8f4ab7805866c9bbd | 0.43121 | 4.115359 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_gmux.vhd | 1 | 6,190 | ------------------------------------------------------------------------------
-- Testbench for gmux.vhd
--
-- Project :
-- File : tb_gmux.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/15
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_GMux is
end tb_GMux;
architecture arch of tb_GMux is
constant NINP : integer := 8; -- 8:1 MUX
constant NSEL : integer := log2(NINP);
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, sel0, sel1, sel2, sel3, sel4, sel5, sel6,
sel7);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal SelxS : std_logic_vector(NSEL-1 downto 0);
signal InpxD : std_logic_vector(NINP*WIDTH-1 downto 0);
signal In0xD : std_logic_vector(WIDTH-1 downto 0);
signal In1xD : std_logic_vector(WIDTH-1 downto 0);
signal In2xD : std_logic_vector(WIDTH-1 downto 0);
signal In3xD : std_logic_vector(WIDTH-1 downto 0);
signal In4xD : std_logic_vector(WIDTH-1 downto 0);
signal In5xD : std_logic_vector(WIDTH-1 downto 0);
signal In6xD : std_logic_vector(WIDTH-1 downto 0);
signal In7xD : std_logic_vector(WIDTH-1 downto 0);
signal OutxD : std_logic_vector(WIDTH-1 downto 0);
component GMux
generic (
NINP : integer;
WIDTH : integer);
port (
SelxSI : in std_logic_vector(log2(NINP)-1 downto 0);
InxDI : in std_logic_vector(NINP*WIDTH-1 downto 0);
OutxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : GMux
generic map (
NINP => NINP,
WIDTH => WIDTH)
port map (
SelxSI => SelxS,
InxDI => InpxD,
OutxDO => OutxD);
----------------------------------------------------------------------------
-- input encoding
----------------------------------------------------------------------------
InpxD <= In7xD & In6xD & In5xD & In4xD & In3xD & In2xD & In1xD & In0xD;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
In1xD <= std_logic_vector(to_unsigned(1, WIDTH));
In2xD <= std_logic_vector(to_unsigned(2, WIDTH));
In3xD <= std_logic_vector(to_unsigned(3, WIDTH));
In4xD <= std_logic_vector(to_unsigned(4, WIDTH));
In5xD <= std_logic_vector(to_unsigned(5, WIDTH));
In6xD <= std_logic_vector(to_unsigned(6, WIDTH));
In7xD <= std_logic_vector(to_unsigned(7, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= sel0; -- sel0
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel1; -- sel1
SelxS <= std_logic_vector(to_unsigned(1, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel2; -- sel2
SelxS <= std_logic_vector(to_unsigned(2, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel3; -- sel3
SelxS <= std_logic_vector(to_unsigned(3, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel4; -- sel4
SelxS <= std_logic_vector(to_unsigned(4, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel5; -- sel5
SelxS <= std_logic_vector(to_unsigned(5, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel6; -- sel6
SelxS <= std_logic_vector(to_unsigned(6, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel7; -- sel7
SelxS <= std_logic_vector(to_unsigned(7, NSEL));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
tbStatus <= sel1; -- sel1, vary input
SelxS <= std_logic_vector(to_unsigned(1, NSEL));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(30, WIDTH));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(31, WIDTH));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(32, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 4387ccdbfc99bdd536031b61cabeb466 | 0.509855 | 3.691115 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/scrambler_reset_inserter.vhd | 1 | 4,710 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: scrambler_reset_inserter - Behavioral
--
-- Description: Replaces one in 512 Blank Start (BS) symbols with
-- a Scrambler Reset (SR).
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-10-13 | Optimize out 72 registers :-)
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity scrambler_reset_inserter is
port (
clk : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0) := (others => '0')
);
end entity;
architecture arch of scrambler_reset_inserter is
signal bs_count : unsigned(8 downto 0) := (others => '0'); -- Cycles from 0 to 511
signal substitue_next : std_logic := '0';
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
begin
process(in_data,bs_count,substitue_next)
begin
out_data <= in_data;
if in_data(8 downto 0) = BS then
if substitue_next = '1' then
out_data( 8 downto 0) <= SR;
out_data(26 downto 18) <= SR;
out_data(44 downto 36) <= SR;
out_data(62 downto 54) <= SR;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
------------------------------------------------
-- Subsitute every 512nd Blank start (BS) symbol
-- with a Scrambler Reset (SR) symbol.
------------------------------------------------
if in_data(8 downto 0) = BS then
if bs_count = 0 then
substitue_next <= '1';
else
substitue_next <= '0';
end if;
bs_count <= bs_count + 1;
end if;
end if;
end process;
end architecture; | mit | b2fe3034006ce5682ca5edaf1329b7e6 | 0.501486 | 4.389562 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/vga_to_dp_stream/memory_32x36_r128x9.vhd | 1 | 2,484 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:22:40 10/12/2015
-- Design Name:
-- Module Name: memory_32x36_r128x9 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity memory_32x36_r128x9 is
Port ( clk_a : in STD_LOGIC;
addr_a : in STD_LOGIC_VECTOR (4 downto 0);
data_a : in STD_LOGIC_VECTOR (35 downto 0);
we_a : in STD_LOGIC;
clk_bc : in STD_LOGIC;
addr_b : in STD_LOGIC_VECTOR (6 downto 0);
data_b_0 : out STD_LOGIC_VECTOR (8 downto 0) := (others => '0');
data_b_1 : out STD_LOGIC_VECTOR (8 downto 0) := (others => '0'));
end memory_32x36_r128x9;
architecture Behavioral of memory_32x36_r128x9 is
type a_mem is array(0 to 31) of std_logic_vector(35 downto 0);
signal mem : a_mem := (others => (others => '0'));
signal this_b : std_logic_vector(addr_b'high-2 downto 0);
signal next_b : std_logic_vector(addr_b'high-2 downto 0);
begin
this_b <= std_logic_vector(unsigned(addr_b(addr_b'high downto 2))+1);
next_b <= std_logic_vector(unsigned(addr_b(addr_b'high downto 2))+1);
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
mem(to_integer(unsigned(addr_a))) <= data_a;
end if;
end if;
end process;
process(clk_bc)
begin
if rising_edge(clk_bc) then
case addr_b(1 downto 0) is
when "00" => data_b_0 <= mem(to_integer(unsigned(this_b)))( 8 downto 0);
data_b_1 <= mem(to_integer(unsigned(this_b)))(17 downto 9);
when "01" => data_b_0 <= mem(to_integer(unsigned(this_b)))(17 downto 9);
data_b_1 <= mem(to_integer(unsigned(this_b)))(26 downto 18);
when others => data_b_0 <= mem(to_integer(unsigned(this_b)))(26 downto 18);
data_b_1 <= mem(to_integer(unsigned(next_b)))( 8 downto 0);
end case;
end if;
end process;
end Behavioral;
| mit | ed7d9b185bc73d39093d4c107a2373fa | 0.504026 | 3.352227 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/unitAvalonSTToI2S/hdl/AvalonSTToI2S_tb.vhd | 1 | 2,901 | -------------------------------------------------------------------------------
-- Title : Testbench for design "AvalonSTToI2S"
-- Project :
-------------------------------------------------------------------------------
-- File : AvalonSTToI2S_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- Created : 2017-05-23
-- Last update: 2017-05-23
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-05-23 1.0 fxst Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity AvalonSTToI2S_tb is
end entity AvalonSTToI2S_tb;
-------------------------------------------------------------------------------
architecture Bhv of AvalonSTToI2S_tb is
-- component generics
constant gDataWidth : natural := 8;
constant gDataWidthLen : natural := 5;
-- component ports
signal iClk : std_logic := '1';
signal inReset : std_logic := '0';
signal iLRC : std_logic := '0';
signal iBCLK : std_logic := '1';
signal oDAT : std_logic;
signal iLeftData : std_logic_vector(gDataWidth-1 downto 0);
signal iLeftValid : std_logic := '0';
signal iRightData : std_logic_vector(gDataWidth-1 downto 0);
signal iRightValid : std_logic := '0';
begin -- architecture Bhv
-- component instantiation
DUT : entity work.AvalonSTToI2S
generic map (
gDataWidth => gDataWidth,
gDataWidthLen => gDataWidthLen)
port map (
iClk => iClk,
inReset => inReset,
iLRC => iLRC,
iBCLK => iBCLK,
oDAT => oDAT,
iLeftData => iLeftData,
iLeftValid => iLeftValid,
iRightData => iRightData,
iRightValid => iRightValid);
-- clock generation
iClk <= not iClk after 10 ns;
-- BCLK generation
iBCLK <= not iBCLK after 10 us;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
inReset <= '1' after 10 ns;
iLeftData <= "11110001" after 100 ns,
"00000000" after 500 ns;
iLeftValid <= '1' after 100 ns,
'0' after 120 ns;
iRightData <= "10001111" after 400 ns,
"00000000" after 600 ns;
iRightValid <= '1' after 400 ns,
'0' after 420 ns;
iLRC <= '0' after 0 ns,
'1' after 30 us,
'0' after 600 us;
wait;
end process WaveGen_Proc;
end architecture Bhv;
| gpl-3.0 | 5cb6d0a4d2356002085326ce452292d8 | 0.455016 | 4.408815 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/regNZ.vhd | 1 | 989 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 08:58:01 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity regNZ is
port (
N_in : in STD_LOGIC;
Z_in : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
loadN : in STD_LOGIC;
loadZ : in STD_LOGIC;
N_out : out STD_LOGIC;
Z_out : out STD_LOGIC
);
end regNZ;
architecture Behavioral of regNZ is
signal data_N: STD_LOGIC;
signal data_Z: STD_LOGIC;
begin
process (clk, rst)
begin
if (rst = '1') then
data_N <= '0';
data_Z <= '0';
elsif (clk = '1' and clk'EVENT) then
if (loadN = '1') then
data_N <= N_in;
end if;
if (loadZ = '1') then
data_Z <= Z_in;
end if;
end if;
end process;
N_out <= data_N;
Z_out <= data_Z;
end Behavioral; | mit | 67e107cd5cf8b462cc3f729d1bdeef1f | 0.584429 | 2.542416 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_cycledncntr.vhd | 1 | 4,436 | ------------------------------------------------------------------------------
-- Testbench for cycledncntr.vhd
--
-- Project :
-- File : tb_cycledncntr.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_CycleDnCntr is
end tb_CycleDnCntr;
architecture arch of tb_CycleDnCntr is
constant CNTWIDTH : integer := 8; -- Counter width
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, load, countdown, done);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT I/O signals
signal LoadxE : std_logic;
signal CinxD : std_logic_vector(CNTWIDTH-1 downto 0);
signal OnxS : std_logic;
signal CoutxD : std_logic_vector(CNTWIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : CycleDnCntr
generic map (
CNTWIDTH => CNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
LoadxEI => LoadxE,
CinxDI => CinxD,
OnxSO => OnxS,
CoutxDO => CoutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
LoadxE <= '0';
CinxD <= std_logic_vector(to_unsigned(0, CNTWIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= load; -- load start value
LoadxE <= '1';
CinxD <= std_logic_vector(to_unsigned(9, CNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= countdown; -- countdown
LoadxE <= '0';
CinxD <= std_logic_vector(to_unsigned(0, CNTWIDTH));
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= load; -- load start value
LoadxE <= '1'; -- (should *not* be loaded)
CinxD <= std_logic_vector(to_unsigned(9, CNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= countdown; -- countdown
LoadxE <= '0';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= load; -- load start value
LoadxE <= '1';
CinxD <= std_logic_vector(to_unsigned(4, CNTWIDTH));
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
LoadxE <= '0';
tbStatus <= countdown; -- countdown
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= done; -- done
LoadxE <= '0';
CinxD <= std_logic_vector(to_unsigned(0, CNTWIDTH));
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | a44e6d152f372ec98978feffa72854b7 | 0.490532 | 4.077206 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpDsp/unitDds/hdl/Dds-Rtl-a.vhd | 1 | 4,155 | -------------------------------------------------------------------------------
-- Title : Direct Digital Synthesis
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : DDS with RAM Table, Table can be defined over MM Interface
-- The Phase Incremen can also be set over an extra MM Interface
-------------------------------------------------------------------------------
architecture Rtl of Dds is
-- RAM
subtype entry_t is u_sfixed(0 downto -(wave_table_width_g-1));
type memory_t is array (wave_table_len_g-1 downto 0) of entry_t;
function init_ram
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
begin
if wave_table_len_g = 4096 then
for idx in 0 to wave_table_len_g-1 loop
-- init rom with gWaveTable values
tmp(idx) := to_sfixed(sin_table_c(idx), 0, -(wave_table_width_g-1));
end loop;
end if;
return tmp;
end init_ram;
-- doesn't work with init ram function, quartus generates no memory
signal wave_table : memory_t;-- := init_ram;
--attribute ramstyle : string;
--attribute ramstyle of wave_table : signal is "MLAB";
signal ram_addr : natural range 0 to wave_table'length-1;
signal ram_d : entry_t;
-- phase increment register
signal phase_inc : natural range 0 to 2**phase_bits_g;
-- phase register
signal phase : unsigned(phase_bits_g-1 downto 0);
-- enable register
signal enable : std_ulogic;
-- output signal
signal dds_data : u_sfixed(0 downto -(data_width_g-1));
begin -- architecture rtl
-----------------------------------------------------------------------------
-- RAM
-- write ram
ram_wr : process (csi_clk) is
begin -- process ram_wr
if rising_edge(csi_clk) then -- rising clock edge
if avs_s0_write = '1' then
wave_table(to_integer(unsigned(avs_s0_address))) <=
to_sfixed(avs_s0_writedata(wave_table_width_g-1 downto 0), wave_table(0));
end if;
end if;
end process ram_wr;
-- read ram
ram_rd : process (csi_clk) is
begin -- process ram_rd
if rising_edge(csi_clk) then -- rising clock edge
ram_d <= wave_table(ram_addr);
end if;
end process ram_rd;
-----------------------------------------------------------------------------
-- Avalon MM Slave Port s1
-- phase increment register
phase_inc_reg : process (csi_clk, rsi_reset_n) is
begin -- process phase_inc_reg
if rsi_reset_n = '0' then -- asynchronous reset (active low)
phase_inc <= 0;
enable <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s1_write = '1' then
case avs_s1_address is
when '0' => enable <= avs_s1_writedata(0);
when '1' => phase_inc <= to_integer(unsigned(avs_s1_writedata));
when others => null;
end case;
end if;
end if;
end process phase_inc_reg;
-----------------------------------------------------------------------------
-- Avalon ST source
aso_data <= to_slv(dds_data) when enable = '1' else (others => '0');
aso_valid <= coe_sample_strobe;
-----------------------------------------------------------------------------
-- DDS
-- calculate next phase
phase_calc : process (csi_clk, rsi_reset_n) is
begin -- process phase_cals
if rsi_reset_n = '0' then -- asynchronous reset (active low)
phase <= to_unsigned(0, phase'length);
elsif rising_edge(csi_clk) then -- rising clock edge
if coe_sample_strobe = '1' then
phase <= phase + phase_inc;
end if;
if enable = '0' then
phase <= to_unsigned(0, phase'length);
end if;
end if;
end process phase_calc;
-- calculate wave table address from phase
ram_addr <= to_integer(phase(phase'left downto phase'right + phase_dither_g));
-- resize data read from ram to size of output data
dds_data <= resize(ram_d, dds_data'left, dds_data'right);
-----------------------------------------------------------------------------
end architecture rtl;
| gpl-3.0 | c55b59f50ee5ec58d11de6b8373be67c | 0.523466 | 3.991354 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/channel_managemnt.vhd | 1 | 19,354 | ----------------------------------------------------------------------------------
-- Module Name: channel_management - Behavioral
--
-- Description: Manages standing up the DisplayPort Channel
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity channel_management is
Port ( clk100 : in STD_LOGIC;
debug : out std_logic_vector(7 downto 0);
hpd : in std_logic;
aux_tx_p : inout std_logic;
aux_tx_n : inout std_logic;
aux_rx_p : inout std_logic;
aux_rx_n : inout std_logic;
-- Datapath requirements
stream_channel_count : std_logic_vector(2 downto 0);
source_channel_count : std_logic_vector(2 downto 0);
-- Datapath control
tx_clock_train : out std_logic;
tx_align_train : out std_logic;
-- Transceiver management
tx_powerup_channel : out STD_LOGIC_VECTOR(3 downto 0) := (others =>'0');
tx_preemp_0p0 : out STD_LOGIC := '0';
tx_preemp_3p5 : out STD_LOGIC := '0';
tx_preemp_6p0 : out STD_LOGIC := '0';
tx_swing_0p4 : out STD_LOGIC := '0';
tx_swing_0p6 : out STD_LOGIC := '0';
tx_swing_0p8 : out STD_LOGIC := '0';
tx_running : in std_logic_vector(3 downto 0);
tx_link_established : OUT std_logic
);
end channel_management;
architecture Behavioral of channel_management is
component hotplug_decode is
port (clk : in std_logic;
hpd : in std_logic;
irq : out std_logic := '0';
present : out std_logic := '0');
end component;
component test_source is
port (
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0)
);
end component;
component link_signal_mgmt is
Port ( mgmt_clk : in STD_LOGIC;
tx_powerup : in STD_LOGIC; -- Used to requiest the powerup of all transceives
status_de : in std_logic;
adjust_de : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
sink_channel_count : in std_logic_vector(2 downto 0);
source_channel_count : in std_logic_vector(2 downto 0);
stream_channel_count : in std_logic_vector(2 downto 0);
active_channel_count : out std_logic_vector(2 downto 0);
powerup_channel : out std_logic_vector(3 downto 0); -- used to request powerup individuat channels
clock_locked : out STD_LOGIC;
equ_locked : out STD_LOGIC;
symbol_locked : out STD_LOGIC;
align_locked : out STD_LOGIC;
preemp_0p0 : out STD_LOGIC;
preemp_3p5 : out STD_LOGIC;
preemp_6p0 : out STD_LOGIC;
swing_0p4 : out STD_LOGIC;
swing_0p6 : out STD_LOGIC;
swing_0p8 : out STD_LOGIC);
end component;
component aux_channel is
port (
clk : in std_logic;
debug_pmod : out std_logic_vector(7 downto 0);
------------------------------
edid_de : out std_logic;
dp_reg_de : out std_logic;
adjust_de : out std_logic;
status_de : out std_logic;
aux_addr : out std_logic_vector(7 downto 0);
aux_data : out std_logic_vector(7 downto 0);
------------------------------
link_count : in std_logic_vector(2 downto 0);
------------------------------
-- Hot plug signals
hpd_irq : in std_logic;
hpd_present : in std_logic;
------------------------------
swing_0p4 : in std_logic;
swing_0p6 : in std_logic;
swing_0p8 : in std_logic;
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
clock_locked : in STD_LOGIC;
equ_locked : in STD_LOGIC;
symbol_locked : in STD_LOGIC;
align_locked : in STD_LOGIC;
------------------------------
tx_powerup : out std_logic := '0';
tx_clock_train : out std_logic := '0';
tx_align_train : out std_logic := '0';
tx_link_established : out std_logic := '0';
------------------------------
dp_tx_hp_detect : in std_logic;
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic
);
end component;
component edid_decode is
port ( clk : in std_logic;
edid_de : in std_logic;
edid_data : in std_logic_vector(7 downto 0);
edid_addr : in std_logic_vector(7 downto 0);
invalidate : in std_logic;
valid : out std_logic := '0';
support_RGB444 : out std_logic := '0';
support_YCC444 : out std_logic := '0';
support_YCC422 : out std_logic := '0';
pixel_clock_x10k : out std_logic_vector(15 downto 0) := (others => '0');
h_visible_len : out std_logic_vector(11 downto 0) := (others => '0');
h_blank_len : out std_logic_vector(11 downto 0) := (others => '0');
h_front_len : out std_logic_vector(11 downto 0) := (others => '0');
h_sync_len : out std_logic_vector(11 downto 0) := (others => '0');
v_visible_len : out std_logic_vector(11 downto 0) := (others => '0');
v_blank_len : out std_logic_vector(11 downto 0) := (others => '0');
v_front_len : out std_logic_vector(11 downto 0) := (others => '0');
v_sync_len : out std_logic_vector(11 downto 0) := (others => '0');
interlaced : out std_logic := '0');
end component;
component dp_register_decode is
port ( clk : in std_logic;
de : in std_logic;
data : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(7 downto 0);
invalidate : in std_logic;
valid : out std_logic := '0';
revision : out std_logic_vector(7 downto 0) := (others => '0');
link_rate_2_70 : out std_logic := '0';
link_rate_1_62 : out std_logic := '0';
extended_framing : out std_logic := '0';
link_count : out std_logic_vector(3 downto 0) := (others => '0');
max_downspread : out std_logic_vector(7 downto 0) := (others => '0');
coding_supported : out std_logic_vector(7 downto 0) := (others => '0');
port0_capabilities : out std_logic_vector(15 downto 0) := (others => '0');
port1_capabilities : out std_logic_vector(15 downto 0) := (others => '0');
norp : out std_logic_vector(7 downto 0) := (others => '0')
);
end component;
component training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0);
out_data0forceneg : out std_logic;
out_data1forceneg : out std_logic
);
end component;
signal edid_de : std_logic;
signal dp_reg_de : std_logic;
signal adjust_de : std_logic;
signal status_de : std_logic;
signal aux_data : std_logic_vector(7 downto 0);
signal aux_addr : std_logic_vector(7 downto 0);
signal invalidate : std_logic;
signal tx_powerup : std_logic;
signal preemp_0p0_i : STD_LOGIC := '0';
signal preemp_3p5_i : STD_LOGIC := '0';
signal preemp_6p0_i : STD_LOGIC := '0';
signal swing_0p4_i : STD_LOGIC := '0';
signal swing_0p6_i : STD_LOGIC := '0';
signal swing_0p8_i : STD_LOGIC := '0';
signal support_RGB444 : std_logic := '0';
signal support_YCC444 : std_logic := '0';
signal support_YCC422 : std_logic := '0';
--------------------------------------------
-- EDID data
---------------------------------------------
signal edid_valid : std_logic := '0';
signal pixel_clock_x10k : std_logic_vector(15 downto 0) := (others => '0');
signal h_visible_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_blank_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_front_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_sync_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_visible_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_blank_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_front_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_sync_len : std_logic_vector(11 downto 0) := (others => '0');
signal interlaced : std_logic := '0';
--------------------------------------------
-- Display port data
---------------------------------------------
signal dp_valid : std_logic := '0';
signal dp_revision : std_logic_vector(7 downto 0) := (others => '0');
signal dp_link_rate_2_70 : std_logic := '0';
signal dp_link_rate_1_62 : std_logic := '0';
signal dp_extended_framing : std_logic := '0';
signal dp_link_count : std_logic_vector(3 downto 0) := (others => '0');
signal dp_max_downspread : std_logic_vector(7 downto 0) := (others => '0');
signal dp_coding_supported : std_logic_vector(7 downto 0) := (others => '0');
signal dp_port0_capabilities : std_logic_vector(15 downto 0) := (others => '0');
signal dp_port1_capabilities : std_logic_vector(15 downto 0) := (others => '0');
signal dp_norp : std_logic_vector(7 downto 0) := (others => '0');
--------------------------------------------------------------------------
---------------------------------------------
-- Transceiver signals
---------------------------------------------
signal txresetdone : std_logic := '0';
signal txoutclk : std_logic := '0';
signal symbolclk : std_logic := '0';
signal clock_locked : std_logic := '0';
signal equ_locked : std_logic := '0';
signal symbol_locked : std_logic := '0';
signal align_locked : std_logic := '0';
------------------------------------------------
signal interface_debug : std_logic_vector(7 downto 0);
signal mgmt_debug : std_logic_vector(7 downto 0);
signal sink_channel_count : std_logic_vector(2 downto 0) := "000";
signal active_channel_count : std_logic_vector(2 downto 0) := "000";
signal hpd_irq : std_logic;
signal hpd_present : std_logic;
begin
-- Feed the number of links from the registers into the link management logic
sink_channel_count <= dp_link_count(2 downto 0);
tx_preemp_0p0 <= preemp_0p0_i;
tx_preemp_3p5 <= preemp_3p5_i;
tx_preemp_6p0 <= preemp_6p0_i;
tx_swing_0p4 <= swing_0p4_i;
tx_swing_0p6 <= swing_0p6_i;
tx_swing_0p8 <= swing_0p8_i;
i_hotplug_decode: hotplug_decode port map (
clk => clk100,
hpd => hpd,
irq => hpd_irq,
present => hpd_present);
i_aux_channel: aux_channel port map (
clk => clk100,
debug_pmod => debug,
------------------------------
edid_de => edid_de,
dp_reg_de => dp_reg_de,
adjust_de => adjust_de,
status_de => status_de,
aux_addr => aux_addr,
aux_data => aux_data,
------------------------------
link_count => active_channel_count,
hpd_irq => hpd_irq,
hpd_present => hpd_present,
------------------------------
preemp_0p0 => preemp_0p0_i,
preemp_3p5 => preemp_3p5_i,
preemp_6p0 => preemp_6p0_i,
swing_0p4 => swing_0p4_i,
swing_0p6 => swing_0p6_i,
swing_0p8 => swing_0p8_i,
clock_locked => clock_locked,
equ_locked => equ_locked,
symbol_locked => symbol_locked,
align_locked => align_locked,
------------------------------
tx_powerup => tx_powerup,
tx_clock_train => tx_clock_train,
tx_align_train => tx_align_train,
tx_link_established => tx_link_established,
------------------------------
dp_tx_hp_detect => hpd,
dp_tx_aux_p => aux_tx_p,
dp_tx_aux_n => aux_tx_n,
dp_rx_aux_p => aux_rx_p,
dp_rx_aux_n => aux_rx_n
);
i_edid_decode: edid_decode port map (
clk => clk100,
edid_de => edid_de,
edid_addr => aux_addr,
edid_data => aux_data,
invalidate => '0',
valid => edid_valid,
support_RGB444 => support_RGB444,
support_YCC444 => support_YCC444,
support_YCC422 => support_YCC422,
pixel_clock_x10k => pixel_clock_x10k,
h_visible_len => h_visible_len,
h_blank_len => h_blank_len,
h_front_len => h_front_len,
h_sync_len => h_sync_len,
v_visible_len => v_visible_len,
v_blank_len => v_blank_len,
v_front_len => v_front_len,
v_sync_len => v_sync_len,
interlaced => interlaced);
i_dp_reg_decode: dp_register_decode port map (
clk => clk100,
de => dp_reg_de,
addr => aux_addr,
data => aux_data,
invalidate => '0',
valid => dp_valid,
revision => dp_revision,
link_rate_2_70 => dp_link_rate_2_70,
link_rate_1_62 => dp_link_rate_1_62,
extended_framing => dp_extended_framing,
link_count => dp_link_count,
max_downspread => dp_max_downspread,
coding_supported => dp_coding_supported,
port0_capabilities => dp_port0_capabilities,
port1_capabilities => dp_port1_capabilities,
norp => dp_norp
);
i_link_signal_mgmt: link_signal_mgmt Port map (
mgmt_clk => clk100,
tx_powerup => tx_powerup,
status_de => status_de,
adjust_de => adjust_de,
addr => aux_addr,
data => aux_data,
sink_channel_count => sink_channel_count,
source_channel_count => source_channel_count,
active_channel_count => active_channel_count,
stream_channel_count => stream_channel_count,
powerup_channel => tx_powerup_channel,
clock_locked => clock_locked,
equ_locked => equ_locked,
symbol_locked => symbol_locked,
align_locked => align_locked,
preemp_0p0 => preemp_0p0_i,
preemp_3p5 => preemp_3p5_i,
preemp_6p0 => preemp_6p0_i,
swing_0p4 => swing_0p4_i,
swing_0p6 => swing_0p6_i,
swing_0p8 => swing_0p8_i);
end Behavioral; | mit | 471de4c2b6a2aacb468bfd8de423ca0d | 0.467862 | 3.918607 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/data_stream.vhd | 1 | 23,091 | ----------------------------------------------------------------------------------
-- Module Name: data_stream_test - Behavioral
--
-- Description: For sumulating the data stream, without the TX modules.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-29 | Updated for Opsis
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_stream_test is
port (
symbolclk : in STD_LOGIC;
symbols : out std_logic_vector(79 downto 0)
);
end data_stream_test;
architecture Behavioral of data_stream_test is
component test_source_800_600_RGB_444_ch4 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_3840_2160_YCC_422_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component insert_main_stream_attrbutes_four_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
signal M_value : std_logic_vector(23 downto 0);
signal N_value : std_logic_vector(23 downto 0);
signal H_visible : std_logic_vector(11 downto 0);
signal V_visible : std_logic_vector(11 downto 0);
signal H_total : std_logic_vector(11 downto 0);
signal V_total : std_logic_vector(11 downto 0);
signal H_sync_width : std_logic_vector(11 downto 0);
signal V_sync_width : std_logic_vector(11 downto 0);
signal H_start : std_logic_vector(11 downto 0);
signal V_start : std_logic_vector(11 downto 0);
signal H_vsync_active_high : std_logic;
signal V_vsync_active_high : std_logic;
signal flag_sync_clock : std_logic;
signal flag_YCCnRGB : std_logic;
signal flag_422n444 : std_logic;
signal flag_YCC_colour_709 : std_logic;
signal flag_range_reduced : std_logic;
signal flag_interlaced_even : std_logic;
signal flags_3d_Indicators : std_logic_vector(1 downto 0);
signal bits_per_colour : std_logic_vector(4 downto 0);
component insert_main_stream_attrbutes_two_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
component idle_pattern_inserter is
port (
clk : in std_logic;
channel_ready : in std_logic;
source_ready : in std_logic;
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler_reset_inserter is
port (
clk : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler is
port (
clk : in std_logic;
bypass0 : in std_logic;
bypass1 : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0)
);
end component;
component data_to_8b10b is
port (
clk : in std_logic;
forceneg : in std_logic_vector(1 downto 0);
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(19 downto 0)
);
end component;
component training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0);
out_data0forceneg : out std_logic;
out_data1forceneg : out std_logic
);
end component;
signal support_RGB444 : std_logic := '0';
signal support_YCC444 : std_logic := '0';
signal support_YCC422 : std_logic := '0';
--------------------------------------------
-- EDID data
---------------------------------------------
signal edid_valid : std_logic := '0';
signal pixel_clock_x10k : std_logic_vector(15 downto 0) := (others => '0');
signal h_visible_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_blank_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_front_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_sync_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_visible_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_blank_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_front_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_sync_len : std_logic_vector(11 downto 0) := (others => '0');
signal interlaced : std_logic := '0';
--------------------------------------------
-- Display port data
---------------------------------------------
signal dp_valid : std_logic := '0';
signal dp_revision : std_logic_vector(7 downto 0) := (others => '0');
signal dp_link_rate_2_70 : std_logic := '0';
signal dp_link_rate_1_62 : std_logic := '0';
signal dp_extended_framing : std_logic := '0';
signal dp_link_count : std_logic_vector(3 downto 0) := (others => '0');
signal dp_max_downspread : std_logic_vector(7 downto 0) := (others => '0');
signal dp_coding_supported : std_logic_vector(7 downto 0) := (others => '0');
signal dp_port0_capabilities : std_logic_vector(15 downto 0) := (others => '0');
signal dp_port1_capabilities : std_logic_vector(15 downto 0) := (others => '0');
signal dp_norp : std_logic_vector(7 downto 0) := (others => '0');
--------------------------------------------------------------------------
signal tx_powerup : std_logic := '0';
signal tx_clock_train : std_logic := '0';
signal tx_align_train : std_logic := '0';
signal data_channel_0 : std_logic_vector(19 downto 0):= (others => '0');
------------------------------------------------
signal tx_debug : std_logic_vector(7 downto 0);
signal sink_channel_count : std_logic_vector(2 downto 0) := "000";
signal source_channel_count : std_logic_vector(2 downto 0) := "010";
signal active_channel_count : std_logic_vector(2 downto 0) := "000";
signal stream_channel_count : std_logic_vector(2 downto 0) := "000";
signal test_signal : std_logic_vector(8 downto 0);
signal scramble_bypass : std_logic;
signal test_signal_ready : std_logic;
signal test_signal_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
signal msa_merged_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
signal signal_data : std_logic_vector(71 downto 0) := (others => '0');
signal sr_inserted_data : std_logic_vector(71 downto 0) := (others => '0');
signal scrambled_data : std_logic_vector(71 downto 0) := (others => '0');
signal final_data : std_logic_vector(71 downto 0) := (others => '0');
signal force_parity_neg : std_logic_vector( 7 downto 0) := (others => '0');
signal hpd_irq : std_logic;
signal hpd_present : std_logic;
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant delay_index : std_logic_vector(7 downto 0) := "11100100"; -- 3,2,1,0 for use as a lookup table in the generate loop
signal count : unsigned(15 downto 0) := (others => '0');
begin
sink_channel_count <= dp_link_count(2 downto 0);
i_test_source: test_source_800_600_RGB_444_ch4 port map (
--i_test_source: test_source_3840_2160_YCC_422_ch2 port map (
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
stream_channel_count => stream_channel_count,
clk => symbolclk,
ready => test_signal_ready,
data => test_signal_data
);
--i_insert_main_stream_attrbutes_one_channel: insert_main_stream_attrbutes_one_channel port map (
--i_insert_main_stream_attrbutes_two_channels: insert_main_stream_attrbutes_two_channels port map (
i_insert_main_stream_attrbutes_four_channels: insert_main_stream_attrbutes_four_channels port map (
clk => symbolclk,
active => '1',
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
-----------------------------------------------------
-- The stream of pixel data coming in
-----------------------------------------------------
in_data => test_signal_data,
-----------------------------------------------------
-- The stream of pixel data going out
-----------------------------------------------------
out_data => msa_merged_data
);
i_idle_pattern_inserter: idle_pattern_inserter port map (
clk => symbolclk,
channel_ready => '1',
source_ready => test_signal_ready,
in_data => msa_merged_data,
out_data => signal_data
);
i_scrambler_reset_inserter: scrambler_reset_inserter
port map (
clk => symbolclk,
in_data => signal_data,
out_data => sr_inserted_data
);
g_per_channel: for i in 0 to 3 generate
i_scrambler: scrambler
port map (
clk => symbolclk,
bypass0 => '1',
bypass1 => '1',
in_data => sr_inserted_data(17+i*18 downto 0+i*18),
out_data => scrambled_data(17+i*18 downto 0+i*18)
);
i_train_channel: training_and_channel_delay port map (
clk => symbolclk,
channel_delay => delay_index(1+i*2 downto 0+i*2),
clock_train => tx_clock_train,
align_train => tx_align_train,
in_data => scrambled_data(17+i*18 downto 0+i*18),
out_data => final_data(17+i*18 downto 0+i*18),
out_data0forceneg => force_parity_neg(0+i*2),
out_data1forceneg => force_parity_neg(1+i*2)
);
i_data_to_8b10b: data_to_8b10b port map (
clk => symbolclk,
in_data => final_data(17+i*18 downto 0+i*18),
out_data => symbols(19+i*20 downto 0+i*20),
forceneg => force_parity_neg(1+i*2 downto 0+i*2)
);
end generate;
end Behavioral;
| mit | bd59f5a4aa58d3ea08cdc41f89155b7a | 0.479278 | 4.105067 | false | false | false | false |
huljar/present-vhdl | src/key_schedule.vhd | 1 | 1,675 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity key_schedule is
generic(k: key_enum);
port(data_in: in std_logic_vector(key_bits(k)-1 downto 0);
round_counter: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(key_bits(k)-1 downto 0)
);
end key_schedule;
architecture structural of key_schedule is
signal shifted: std_logic_vector(key_bits(k)-1 downto 0);
component sbox
port(data_in: in std_logic_vector(3 downto 0);
data_out: out std_logic_vector(3 downto 0)
);
end component;
begin
SCHEDULE_80: if k = K_80 generate
shifted <= data_in(18 downto 0) & data_in(79 downto 19);
SB: sbox port map(
data_in => shifted(79 downto 76),
data_out => data_out(79 downto 76)
);
data_out(75 downto 20) <= shifted(75 downto 20);
data_out(19 downto 15) <= shifted(19 downto 15) xor round_counter;
data_out(14 downto 0) <= shifted(14 downto 0);
end generate;
SCHEDULE_128: if k = K_128 generate
shifted <= data_in(66 downto 0) & data_in(127 downto 67);
SB1: sbox port map(
data_in => shifted(127 downto 124),
data_out => data_out(127 downto 124)
);
SB2: sbox port map(
data_in => shifted(123 downto 120),
data_out => data_out(123 downto 120)
);
data_out(119 downto 67) <= shifted(119 downto 67);
data_out(66 downto 62) <= shifted(66 downto 62) xor round_counter;
data_out(61 downto 0) <= shifted(61 downto 0);
end generate;
end structural;
| mit | d9e0115d3786067126f9186f8a9f8f76 | 0.592836 | 3.460744 | false | false | false | false |
plessl/zippy | vhdl/cycledncntr.vhd | 1 | 2,170 | ------------------------------------------------------------------------------
-- Cycles Down Counter
--
-- Project :
-- File : cycledncntr.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-07 11:06:32 +0200 (Thu, 07 Oct 2004) $
------------------------------------------------------------------------------
-- Loadable cycle counter that controls the execution of the
-- array. The counter value is decreased until it reaches zero. It
-- cannot be loaded while counting down.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CycleDnCntr is
generic (
CNTWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CinxDI : in std_logic_vector(CNTWIDTH-1 downto 0);
OnxSO : out std_logic;
CoutxDO : out std_logic_vector(CNTWIDTH-1 downto 0));
end CycleDnCntr;
architecture simple of CycleDnCntr is
signal CountxD : unsigned(CNTWIDTH-1 downto 0);
signal NotZeroxS : std_logic;
begin -- simple
Comparator : process (CountxD)
begin -- process Comparator
if CountxD > 0 then
NotZeroxS <= '1';
else
NotZeroxS <= '0';
end if;
end process Comparator;
Counter : process (ClkxC, RstxRB)
begin -- process Counter
if RstxRB = '0' then -- asynchronous reset (active low)
CountxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if NotZeroxS = '1' then
CountxD <= CountxD - 1;
elsif LoadxEI = '1' then -- only loadable if count > 0
CountxD <= unsigned(CinxDI);
end if;
end if;
end process Counter;
CoutxDO <= std_logic_vector(CountxD);
OnxSO <= NotZeroxS;
end simple;
| bsd-3-clause | 388d3a7804d48e0e5f27afd53228c02e | 0.538249 | 3.875 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/unitAudioCodecAvalon/hdl/AudioCodecAvalon_tb.vhd | 1 | 3,498 | -------------------------------------------------------------------------------
-- Title : Testbench for design "AudioCodecAvalon"
-- Project :
-------------------------------------------------------------------------------
-- File : AudioCodecAvalon_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- Created : 2017-05-23
-- Last update: 2017-05-23
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-05-23 1.0 fxst Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity AudioCodecAvalon_tb is
end entity AudioCodecAvalon_tb;
-------------------------------------------------------------------------------
architecture Bhv of AudioCodecAvalon_tb is
-- component generics
constant gDataWidth : natural := 8;
constant gDataWidthLen : natural := 5;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic := '0';
signal AUD_ADCDAT : std_logic;
signal AUD_ADCLRCK : std_logic;
signal AUD_BCLK : std_logic := '1';
signal AUD_DACDAT : std_logic;
signal AUD_DACLRCK : std_logic;
signal asi_left_data : std_logic_vector(gDataWidth-1 downto 0);
signal asi_left_valid : std_logic;
signal asi_right_data : std_logic_vector(gDataWidth-1 downto 0);
signal asi_right_valid : std_logic;
signal aso_left_data : std_logic_vector(gDataWidth-1 downto 0);
signal aso_left_valid : std_logic;
signal aso_right_data : std_logic_vector(gDataWidth-1 downto 0);
signal aso_right_valid : std_logic;
signal LRC : std_logic := '0';
begin -- architecture Bhv
-- component instantiation
DUT : entity work.AudioCodecAvalon
generic map (
gDataWidth => gDataWidth,
gDataWidthLen => gDataWidthLen)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
AUD_ADCDAT => AUD_ADCDAT,
AUD_ADCLRCK => AUD_ADCLRCK,
AUD_BCLK => AUD_BCLK,
AUD_DACDAT => AUD_DACDAT,
AUD_DACLRCK => AUD_DACLRCK,
asi_left_data => asi_left_data,
asi_left_valid => asi_left_valid,
asi_right_data => asi_right_data,
asi_right_valid => asi_right_valid,
aso_left_data => aso_left_data,
aso_left_valid => aso_left_valid,
aso_right_data => aso_right_data,
aso_right_valid => aso_right_valid);
-- clock generation
csi_clk <= not csi_clk after 10 ns; -- 50MHz
-- BCLK generation 48kHz
AUD_BCLK <= not AUD_BCLK after 10 us;
-- LRC generation
LRC <= not LRC after 190 us;
AUD_ADCDAT <= AUD_DACDAT;
AUD_ADCLRCK <= LRC;
AUD_DACLRCK <= LRC;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
rsi_reset_n <= '1' after 10 ns;
asi_left_data <= "11110001" after 0 ns;
asi_left_valid <= '1' after 60 ns;
asi_right_data <= "10001111" after 60 ns;
asi_right_valid <= '1' after 80 ns;
wait;
end process WaveGen_Proc;
end architecture Bhv;
| gpl-3.0 | ab12cfc1afd8b05727f66de3c908a2f5 | 0.505432 | 3.952542 | false | false | false | false |
plessl/zippy | vhdl/SchedulerTemporalPartitioning.vhd | 1 | 4,791 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
entity SchedulerTemporalPartitioning is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
--
ScheduleStartxEI : in std_logic;
ScheduleDonexSO : out std_logic;
-- number of temporal contexts used in temporal partition
NoTpContextsxSI : in unsigned(CNTXTWIDTH-1 downto 0);
-- number of user clock-cycles to run
NoTpUserCyclesxSI : in unsigned(CCNTWIDTH-1 downto 0);
-- signals to engine
CExEO : out std_logic;
ClrContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEO : out std_logic;
ContextxSO : out std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDO : out std_logic_vector(CCNTWIDTH-1 downto 0)
);
end SchedulerTemporalPartitioning;
architecture arch of SchedulerTemporalPartitioning is
signal currentUserCycle : unsigned(CCNTWIDTH-1 downto 0);
signal currentSubCycle : unsigned(CNTXTWIDTH-1 downto 0);
signal nextUserCycle : unsigned(CCNTWIDTH-1 downto 0);
signal nextSubCycle : unsigned(CNTXTWIDTH-1 downto 0);
--signal scheduleStarted : std_logic;
type state_type is (sIdle, sRunning);
signal StatexS, NextStatexS : state_type;
begin -- arch
process (NoTpContextsxSI, NoTpUserCyclesxSI, ScheduleStartxEI, StatexS,
currentSubCycle, currentUserCycle)
begin -- process
case StatexS is
when sIdle =>
ScheduleDonexSO <= '1';
CExEO <= '0';
nextUserCycle <= NoTpUserCyclesxSI;
nextSubCycle <= to_unsigned(0, currentSubCycle'length);
if (ScheduleStartxEI = '1') then
nextUserCycle <= to_unsigned(0, currentUserCycle'length);
NextStatexS <= sRunning;
end if;
when sRunning =>
ScheduleDonexSO <= '0';
CExEO <= '1';
-- stop schedule when last subcycle of last usercycle is reached
if ((currentUserCycle = (NoTpUserCyclesxSI-1)) and
(currentSubCycle = (NoTpContextsxSI-1))) then
-- Set the nextUserCycle to the max number of user
-- cycles. That way, the cycle down counter (CycleDnCntxDO)
-- remains at 0 after the temporal partitioning scheduler
-- has finished. This enables to detect the end of a run of
-- the temporal partitioning sequencer.
nextUserCycle <= NoTpUserCyclesxSI;
nextSubCycle <= to_unsigned(0, currentSubCycle'length);
NextStatexS <= sIdle;
elsif (currentSubCycle = (NoTpContextsxSI-1)) then
-- increment currentSubCycles modulo number of Tp contexts,
-- and increment user cycle whenever last context is reached
nextUserCycle <= currentUserCycle + 1;
nextSubCycle <= to_unsigned(0, currentSubCycle'length);
else
nextSubCycle <= currentSubCycle + 1;
end if;
when others =>
NextStatexS <= sIdle;
end case;
end process;
process (ClkxC, RstxRB, currentSubCycle, currentUserCycle)
begin
if (RstxRB = '0') then
StatexS <= sIdle;
currentUserCycle <= to_unsigned(0, currentUserCycle'length);
currentSubCycle <= to_unsigned(0, currentSubCycle'length);
elsif (rising_edge(ClkxC)) then
StatexS <= NextStatexS;
currentUserCycle <= nextUserCycle;
currentSubCycle <= nextSubCycle;
end if;
end process;
ClrContextxEO <= '0';
ClrContextxSO <= (others => '0');
ContextxSO <= std_logic_vector(currentSubCycle);
CycleUpCntxDO <= std_logic_vector(currentUserCycle);
CycleDnCntxDO <= std_logic_vector(NoTpUserCyclesxSI - currentUserCycle);
end arch;
-------------------------------------------------------------------------
-- port declaration of engine
-------------------------------------------------------------------------------
-- port (
-- ClkxC : in std_logic;
-- RstxRB : in std_logic;
-- CExEI : in std_logic;
-- ConfigxI : in engineConfigRec;
-- ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
-- ClrContextxEI : in std_logic;
-- ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
-- CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
-- CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
-- InPortxDI : in engineInoutDataType;
-- OutPortxDO : out engineInoutDataType;
-- InPortxEO : out std_logic_vector(N_IOP-1 downto 0);
-- OutPortxEO : out std_logic_vector(N_IOP-1 downto 0);
-- )
| bsd-3-clause | d14ff70e4ac37370d27e945669523cce | 0.621791 | 3.757647 | false | false | false | false |
tmeissner/raspberrypi | raspiFpga/src/RaspiFpgaCtrlE.vhd | 1 | 7,868 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RaspiFpgaCtrlE is
port (
--+ System if
Rst_n_i : in std_logic;
Clk_i : in std_logic;
--+ local register if
LocalWen_o : out std_logic;
LocalRen_o : out std_logic;
LocalAdress_o : out std_logic_vector(7 downto 0);
LocalData_i : in std_logic_vector(7 downto 0);
LocalData_o : out std_logic_vector(7 downto 0);
LocalAck_i : in std_logic;
LocalError_i : in std_logic;
--+ EFB if
EfbSpiIrq_i : in std_logic;
--+ RNG if
RngStart_o : out std_logic;
RngWait_o : out std_logic_vector(7 downto 0);
RngRun_o : out std_logic_vector(7 downto 0);
RngDataValid_i : in std_logic;
RngData_i : in std_logic_vector(7 downto 0)
);
end entity RaspiFpgaCtrlE;
architecture rtl of RaspiFpgaCtrlE is
--+ EFB SPI slave register addresses
constant C_SPICR0 : std_logic_vector(7 downto 0) := x"54"; --* ctrl reg 0
constant C_SPICR1 : std_logic_vector(7 downto 0) := x"55"; --* ctrl reg 1
constant C_SPICR2 : std_logic_vector(7 downto 0) := x"56"; --* ctrl reg 2
constant C_SPIBR : std_logic_vector(7 downto 0) := x"57"; --* clk pre-scale
constant C_SPICSR : std_logic_vector(7 downto 0) := x"58"; --* master chip select
constant C_SPITXDR : std_logic_vector(7 downto 0) := x"59"; --* transmit data
constant C_SPIISR : std_logic_vector(7 downto 0) := x"5A"; --* status
constant C_SPIRXDR : std_logic_vector(7 downto 0) := x"5B"; --* receive data
constant C_SPIIRQ : std_logic_vector(7 downto 0) := x"5C"; --* interrupt request
constant C_SPIIRQEN : std_logic_vector(7 downto 0) := x"5D"; --* interrupt request enable
--+ Register file addresses
constant C_REG_RNGSTATUS : natural := 0;
constant C_REG_RNGWAIT : natural := 1;
constant C_REG_RNGRUN : natural := 2;
constant C_REG_RNGDATA : natural := 3;
type t_cmdctrl_fsm is (IDLE, INIT_SET, INIT_ACK, TXDR_SET, TXDR_ACK, INT_WAIT,
RXDR_SET, RXDR_ACK, INT_CLEAR_SET, INT_CLEAR_ACK);
signal s_cmdctrl_fsm : t_cmdctrl_fsm;
type t_wb_master is record
adr : std_logic_vector(7 downto 0);
data : std_logic_vector(7 downto 0);
end record t_wb_master;
type t_wb_master_array is array (natural range <>) of t_wb_master;
constant C_INIT : t_wb_master_array := ((C_SPICR1, x"80"),
(C_SPICR2, x"00"),
(C_SPIIRQEN, x"08"));
signal s_init_cnt : natural range 0 to C_INIT'length;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
signal s_register : t_byte_array(0 to 127);
signal s_register_we : std_logic;
signal s_register_address : natural range s_register'range;
type t_spi_frame is (NOP, HEADER, WRITE_DATA, READ_DATA);
signal s_spi_frame : t_spi_frame;
begin
--+ FSM to write/request data from the wishbone master
--+ Combinatoral outputs
LocalWen_o <= '1' when s_cmdctrl_fsm = INIT_SET or s_cmdctrl_fsm = TXDR_SET or s_cmdctrl_fsm = INT_CLEAR_SET else '0';
LocalRen_o <= '1' when s_cmdctrl_fsm = RXDR_SET else '0';
LocalAdress_o <= C_INIT(s_init_cnt).adr when s_cmdctrl_fsm = INIT_SET else
C_SPITXDR when s_cmdctrl_fsm = TXDR_SET else
C_SPIRXDR when s_cmdctrl_fsm = RXDR_SET else
C_SPIIRQ when s_cmdctrl_fsm = INT_CLEAR_SET else
(others => '0');
LocalData_o <= C_INIT(s_init_cnt).data when s_cmdctrl_fsm = INIT_SET else
s_register(s_register_address) when s_cmdctrl_fsm = TXDR_SET and s_spi_frame = READ_DATA else
x"FF";
--+ FSM to write/request data from the wishbone master
--+ State logic/register
CmdCtrlP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Rst_n_i = '0') then
s_cmdctrl_fsm <= IDLE;
else
FsmC : case s_cmdctrl_fsm is
when IDLE =>
s_cmdctrl_fsm <= INIT_SET;
when INIT_SET =>
s_cmdctrl_fsm <= INIT_ACK;
when INIT_ACK =>
if (LocalAck_i = '1') then
if (s_init_cnt = C_INIT'length) then
s_cmdctrl_fsm <= TXDR_SET;
else
s_cmdctrl_fsm <= INIT_SET;
end if;
end if;
when TXDR_SET =>
s_cmdctrl_fsm <= TXDR_ACK;
when TXDR_ACK =>
if (LocalAck_i = '1') then
s_cmdctrl_fsm <= INT_WAIT;
end if;
when INT_WAIT =>
if (EfbSpiIrq_i = '1') then
s_cmdctrl_fsm <= RXDR_SET;
end if;
when RXDR_SET =>
s_cmdctrl_fsm <= RXDR_ACK;
when RXDR_ACK =>
if (LocalAck_i = '1') then
s_cmdctrl_fsm <= INT_CLEAR_SET;
end if;
when INT_CLEAR_SET =>
s_cmdctrl_fsm <= INT_CLEAR_ACK;
when INT_CLEAR_ACK =>
if (LocalAck_i = '1') then
s_cmdctrl_fsm <= TXDR_SET;
end if;
when others =>
null;
end case FsmC;
end if;
end if;
end process CmdCtrlP;
--+ FSM to write/request data from the wishbone master
--+ Registered outputs
CmdRegisterP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Rst_n_i = '0') then
s_init_cnt <= 0;
s_spi_frame <= NOP;
s_register_address <= 0;
else
case s_cmdctrl_fsm is
when IDLE =>
s_init_cnt <= 0;
s_spi_frame <= NOP;
s_register_address <= 0;
when INIT_SET =>
s_init_cnt <= s_init_cnt + 1;
when RXDR_ACK =>
if (LocalAck_i = '1') then
if (s_spi_frame = HEADER) then
s_register_address <= to_integer(unsigned(LocalData_i(6 downto 0)));
if (LocalData_i(7) = '0') then
s_spi_frame <= READ_DATA;
else
s_spi_frame <= WRITE_DATA;
end if;
else
if (LocalData_i = x"00") then
s_spi_frame <= HEADER;
else
s_spi_frame <= NOP;
end if;
end if;
end if;
when others =>
null;
end case;
end if;
end if;
end process CmdRegisterP;
--+ Register bank write enable
s_register_we <= LocalAck_i when s_cmdctrl_fsm = RXDR_ACK and s_spi_frame = WRITE_DATA else '0';
--+ Register bank 127x8
RegisterFileP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Rst_n_i = '0') then
s_register <= (others => (others => '0'));
s_register(C_REG_RNGWAIT) <= x"0F";
s_register(C_REG_RNGRUN) <= x"0F";
else
s_register(C_REG_RNGSTATUS)(0) <= '0'; -- reset RNG start after each clock cycle
if (s_register_we = '1') then
s_register(s_register_address) <= LocalData_i;
end if;
-- register RNG data
if (RngDataValid_i = '1') then
s_register(C_REG_RNGSTATUS)(1) <= '1';
s_register(C_REG_RNGDATA) <= RngData_i;
end if;
-- clear RNG done flag when RNG was started
if (s_register(C_REG_RNGSTATUS)(0) = '1') then
s_register(C_REG_RNGSTATUS)(1) <= '0';
end if;
end if;
end if;
end process RegisterFileP;
--+ RNG control outputs
RngStart_o <= s_register(C_REG_RNGSTATUS)(0);
RngWait_o <= s_register(C_REG_RNGWAIT);
RngRun_o <= s_register(C_REG_RNGRUN);
end architecture rtl;
| gpl-2.0 | 89dadc521087a7526583062620e793a2 | 0.531901 | 3.310055 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/video_generator.vhd | 1 | 3,107 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20.08.2015 21:08:13
-- Design Name:
-- Module Name: video_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity video_generator is
Port ( clk : in STD_LOGIC;
h_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
h_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
h_front_len : in std_logic_vector(11 downto 0) := (others => '0');
h_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
v_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
v_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
v_front_len : in std_logic_vector(11 downto 0) := (others => '0');
v_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
vid_blank : out STD_LOGIC;
vid_hsync : out STD_LOGIC;
vid_vsync : out STD_LOGIC);
end video_generator;
architecture Behavioral of video_generator is
signal h_counter : unsigned(11 downto 0) := (others => '0');
signal v_counter : unsigned(11 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
-- Generate the sync and blanking signals
if h_counter >= unsigned(h_front_len) and h_counter < unsigned(h_front_len) + unsigned(h_sync_len) then
vid_hsync <= '1';
else
vid_hsync <= '0';
end if;
if v_counter >= unsigned(v_front_len) and v_counter < unsigned(v_front_len) + unsigned(v_sync_len) then
vid_vsync <= '1';
else
vid_vsync <= '0';
end if;
if h_counter < unsigned(h_blank_len) or v_counter < unsigned(v_blank_len) then
vid_blank <= '1';
else
vid_blank <= '0';
end if;
-- Manage the counters
if h_counter = unsigned(h_visible_len)+unsigned(h_blank_len)-1 then
h_counter <= (others => '0');
if v_counter = unsigned(v_visible_len)+unsigned(v_blank_len)-1 then
v_counter <= (others => '0');
else
v_counter <= v_counter+1;
end if;
else
h_counter <= h_counter + 1;
end if;
end if;
end process;
end Behavioral;
| mit | b63b83034ed43b0d6aa40c87efeda270 | 0.485999 | 3.86924 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_mux8to1.vhd | 1 | 5,268 | ------------------------------------------------------------------------------
-- Testbench for mux8to1.vhd
--
-- Project :
-- File : tb_mux8to1.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/15
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Mux8to1 is
end tb_Mux8to1;
architecture arch of tb_Mux8to1 is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, sel0, sel1, sel2, sel3, sel4, sel5, sel6,
sel7);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal SelxS : std_logic_vector(2 downto 0);
signal In0xD : std_logic_vector(WIDTH-1 downto 0);
signal In1xD : std_logic_vector(WIDTH-1 downto 0);
signal In2xD : std_logic_vector(WIDTH-1 downto 0);
signal In3xD : std_logic_vector(WIDTH-1 downto 0);
signal In4xD : std_logic_vector(WIDTH-1 downto 0);
signal In5xD : std_logic_vector(WIDTH-1 downto 0);
signal In6xD : std_logic_vector(WIDTH-1 downto 0);
signal In7xD : std_logic_vector(WIDTH-1 downto 0);
signal OutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut: Mux8to1
generic map (
WIDTH => WIDTH)
port map (
SelxSI => SelxS,
In0xDI => In0xD,
In1xDI => In1xD,
In2xDI => In2xD,
In3xDI => In3xD,
In4xDI => In4xD,
In5xDI => In5xD,
In6xDI => In6xD,
In7xDI => In7xD,
OutxDO => OutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
SelxS <= O"0";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
In1xD <= std_logic_vector(to_unsigned(1, WIDTH));
In2xD <= std_logic_vector(to_unsigned(2, WIDTH));
In3xD <= std_logic_vector(to_unsigned(3, WIDTH));
In4xD <= std_logic_vector(to_unsigned(4, WIDTH));
In5xD <= std_logic_vector(to_unsigned(5, WIDTH));
In6xD <= std_logic_vector(to_unsigned(6, WIDTH));
In7xD <= std_logic_vector(to_unsigned(7, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= sel0; -- sel0
SelxS <= O"0";
wait for CLK_PERIOD;
tbStatus <= sel1; -- sel1
SelxS <= O"1";
wait for CLK_PERIOD;
tbStatus <= sel2; -- sel2
SelxS <= O"2";
wait for CLK_PERIOD;
tbStatus <= sel3; -- sel3
SelxS <= O"3";
wait for CLK_PERIOD;
tbStatus <= sel4; -- sel4
SelxS <= O"4";
wait for CLK_PERIOD;
tbStatus <= sel5; -- sel5
SelxS <= O"5";
wait for CLK_PERIOD;
tbStatus <= sel6; -- sel6
SelxS <= O"6";
wait for CLK_PERIOD;
tbStatus <= sel7; -- sel7
SelxS <= O"7";
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= O"0";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
tbStatus <= sel1; -- sel1, vary input
SelxS <= O"1";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(30, WIDTH));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(31, WIDTH));
wait for CLK_PERIOD;
In1xD <= std_logic_vector(to_unsigned(32, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= O"0";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | cd3a04b6b31d790b8ac1f5a7fc017b05 | 0.495254 | 3.67364 | false | false | false | false |
huljar/present-vhdl | sim/present128_axis_tb.vhd | 1 | 4,862 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:37:59 02/28/2017
-- Design Name:
-- Module Name: /home/julian/Projekt/Xilinx Projects/present-vhdl/src/present_tb.vhd
-- Project Name: present-vhdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: present_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_textio.ALL;
USE work.util.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY present128_axis_tb IS
END present128_axis_tb;
ARCHITECTURE behavior OF present128_axis_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT axi_stream_wrapper
GENERIC(
k : key_enum
);
PORT(
ACLK : IN std_logic;
ARESETN : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(31 downto 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TVALID : IN std_logic;
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TDATA : OUT std_logic_vector(31 downto 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TREADY : IN std_logic
);
END COMPONENT;
--Inputs
signal ACLK : std_logic := '0';
signal ARESETN : std_logic := '0';
signal S_AXIS_TDATA : std_logic_vector(31 downto 0) := (others => '0');
signal S_AXIS_TLAST : std_logic := '0';
signal S_AXIS_TVALID : std_logic := '0';
signal M_AXIS_TREADY : std_logic := '0';
--Outputs
signal S_AXIS_TREADY : std_logic;
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(31 downto 0);
signal M_AXIS_TLAST : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
-- Other signals
signal ciphertext : std_logic_vector(63 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: axi_stream_wrapper GENERIC MAP (
k => K_128
) PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
-- Clock process definitions
clk_process: process
begin
ACLK <= '0';
wait for clk_period/2;
ACLK <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable ct: line;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- write plaintext
ARESETN <= '1';
S_AXIS_TVALID <= '1';
S_AXIS_TDATA <= x"01234567";
wait for clk_period;
assert (S_AXIS_TREADY = '1') report "ERROR: axi slave is not ready!" severity error;
wait for clk_period;
S_AXIS_TDATA <= x"89ABCDEF";
wait for clk_period;
-- write key
S_AXIS_TDATA <= x"01234567";
wait for clk_period;
S_AXIS_TDATA <= x"89ABCDEF";
wait for clk_period;
S_AXIS_TDATA <= x"01234567";
wait for clk_period;
S_AXIS_TDATA <= x"89ABCDEF";
wait for clk_period;
S_AXIS_TDATA <= (others => '0');
S_AXIS_TVALID <= '0';
wait for clk_period;
assert (S_AXIS_TREADY = '0') report "ERROR: axi slave is still ready after reading data!" severity error;
-- wait for processing
wait for clk_period*34;
assert (M_AXIS_TVALID = '1') report "ERROR: axi master is not ready in time!" severity error;
-- read ciphertext
M_AXIS_TREADY <= '1';
wait for clk_period;
ciphertext(63 downto 32) <= M_AXIS_TDATA;
wait for clk_period;
ciphertext(31 downto 0) <= M_AXIS_TDATA;
wait for clk_period;
assert (M_AXIS_TVALID = '0') report "ERROR: axi master is still valid after writing all output!" severity error;
M_AXIS_TREADY <= '0';
-- print ciphertext
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: 0E9D28685E671DD6)";
deallocate(ct);
wait;
end process;
END;
| mit | 6cbbf2b104017892ecdc4a850ad3be02 | 0.592966 | 3.683333 | false | false | false | false |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd | 1 | 6,876 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-2.0 | 6dbb670d554805973ed23ba9fd7f6a82 | 0.580279 | 3.736957 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_cell.vhd | 1 | 5,192 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity tb_Cell is
end tb_Cell;
architecture arch of tb_Cell is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, add, shift);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxAB : std_logic := '1';
signal CExE : std_logic := '1';
signal Cfg : cellConfigRec;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0) := (others => '0');
signal In0xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In1xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In2xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In3xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In4xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In5xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In6xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In7xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal OutxD : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out0xZ : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out1xZ : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out2xZ : std_logic_vector(DATAWIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Cell
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxABI => ClrxAB,
CExEI => CExE,
ConfigxI => Cfg,
ContextxSI => ContextxS,
In0xDI => In0xD,
In1xDI => In1xD,
In2xDI => In2xD,
In3xDI => In3xD,
In4xDI => In4xD,
In5xDI => In5xD,
In6xDI => In6xD,
In7xDI => In7xD,
OutxDO => OutxD,
Out0xZO => Out0xZ,
Out1xZO => Out1xZ,
Out2xZO => Out2xZ);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
In0xD <= std_logic_vector(to_unsigned(01, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(10, DATAWIDTH));
In2xD <= std_logic_vector(to_unsigned(20, DATAWIDTH));
In3xD <= std_logic_vector(to_unsigned(30, DATAWIDTH));
In4xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
In5xD <= std_logic_vector(to_unsigned(50, DATAWIDTH));
In6xD <= std_logic_vector(to_unsigned(60, DATAWIDTH));
In7xD <= std_logic_vector(to_unsigned(70, DATAWIDTH));
tbStatus <= rst;
Cfg <= init_cellConfig;
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= add;
Cfg.routConf.Route0MuxS <= "011";
Cfg.routConf.Route1MuxS <= "110";
Cfg.routConf.Tri0OExE <= '1';
Cfg.routConf.Tri1OExE <= '1';
Cfg.routConf.Tri2OExE <= '1';
Cfg.procConf.Op0MuxS <= "00";
Cfg.procConf.Op1MuxS <= "00";
Cfg.procConf.OutMuxS <= '0';
Cfg.procConf.AluOpxS <= alu_addu;
Cfg.procConf.ConstOpxD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_cellConfig;
wait for CLK_PERIOD;
tbStatus <= shift;
Cfg.routConf.Route0MuxS <= "010";
Cfg.routConf.Route1MuxS <= "000";
Cfg.routConf.Tri0OExE <= '1';
Cfg.routConf.Tri1OExE <= '0';
Cfg.routConf.Tri2OExE <= '1';
Cfg.procConf.Op0MuxS <= "00";
Cfg.procConf.Op1MuxS <= "10";
Cfg.procConf.OutMuxS <= '0';
Cfg.procConf.AluOpxS <= alu_sll;
Cfg.procConf.ConstOpxD <= std_logic_vector(to_unsigned(2, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_cellConfig;
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | a154c46415c9caac4971b93e6cb54742 | 0.528891 | 3.570839 | false | false | false | false |
hamsternz/FPGA_DisplayPort | test_benches/tb_test_source_3840_2160.vhd | 1 | 15,777 | ----------------------------------------------------------------------------------
-- Module Name: tb_test_source_3840_2160 - Behavioral
--
-- Description: A testbench for tb_test_source
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_test_source_3840_2160 is
end entity;
architecture arch of tb_test_source_3840_2160 is
component test_source_3840_2160_YCC_422_ch2 is
port (
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component insert_main_stream_attrbutes_two_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0) := (others => '0'));
end component;
component idle_pattern_inserter is
port (
clk : in std_logic;
channel_ready : in std_logic;
source_ready : in std_logic;
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(71 downto 0) := (others => '0')
);
end component;
component scrambler_reset_inserter is
port (
clk : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler is
port (
clk : in std_logic;
bypass0 : in std_logic;
bypass1 : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0)
);
end component;
component training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0);
out_data0forceneg : out std_logic;
out_data1forceneg : out std_logic
);
end component;
component data_to_8b10b is
port (
clk : in std_logic;
forceneg : in std_logic_vector(1 downto 0);
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(19 downto 0) := (others => '0')
);
end component;
signal clk : std_logic;
signal test_signal_data : std_logic_vector(72 downto 0);
signal test_signal_ready : std_logic;
signal msa_merged_data : std_logic_vector(72 downto 0);
signal signal_data : std_logic_vector(71 downto 0);
signal sr_inserted_data : std_logic_vector(71 downto 0);
signal scramble_bypass : std_logic := '1';
signal scrambled_data : std_logic_vector(17 downto 0);
signal ch0_data : std_logic_vector(17 downto 0);
signal ch0_forceneg : std_logic_vector(1 downto 0);
signal ch0_symbols : std_logic_vector(19 downto 0);
signal dec0 : std_logic_vector(8 downto 0);
signal rd : unsigned(9 downto 0) := (others => '0');
signal c0s0 : std_logic_vector(8 downto 0);
signal c0s1 : std_logic_vector(8 downto 0);
signal c1s0 : std_logic_vector(8 downto 0);
signal c1s1 : std_logic_vector(8 downto 0);
signal ccount : unsigned(15 downto 0) := (others => '0');
begin
i_test_source: test_source_3840_2160_YCC_422_ch2 port map (
clk => clk,
ready => test_signal_ready,
data => test_signal_data
);
i_insert_main_stream_attrbutes_two_channels: insert_main_stream_attrbutes_two_channels port map (
clk => clk,
active => '1',
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value => x"07DA13", -- For 265MHz/270Mhz
N_value => x"080000",
H_visible => x"F00", -- 3840
H_total => x"FC0", -- 4032
H_sync_width => x"030", -- 128
H_start => x"0A0", -- 160
V_visible => x"870", -- 2160
V_total => x"88F", -- 2191
V_sync_width => x"003", -- 3
V_start => x"01A", -- 26
H_vsync_active_high => '1',
V_vsync_active_high => '1',
flag_sync_clock => '1',
flag_YCCnRGB => '1',
flag_422n444 => '1',
flag_range_reduced => '1',
flag_interlaced_even => '0',
flag_YCC_colour_709 => '0',
flags_3d_Indicators => (others => '0'),
bits_per_colour => "01000",
-- M_value => x"012F68",
-- N_value => x"080000",
-- H_visible => x"320", -- 800
-- V_visible => x"258", -- 600
-- H_total => x"420", -- 1056
-- V_total => x"274", -- 628
-- H_sync_width => x"080", -- 128
-- V_sync_width => x"004", -- 4
-- H_start => x"0D8", -- 216
-- V_start => x"01b", -- 37
-- H_vsync_active_high => '0',
-- V_vsync_active_high => '0',
-- flag_sync_clock => '1',
-- flag_YCCnRGB => '0',
-- flag_422n444 => '0',
-- flag_range_reduced => '0',
-- flag_interlaced_even => '0',
-- flag_YCC_colour_709 => '0',
-- flags_3d_Indicators => (others => '0'),
-- bits_per_colour => "01000",
-----------------------------------------------------
-- The stream of pixel data coming in
-----------------------------------------------------
in_data => test_signal_data,
-----------------------------------------------------
-- The stream of pixel data going out
-----------------------------------------------------
out_data => msa_merged_data);
i_idle_pattern_inserter: idle_pattern_inserter port map (
clk => clk,
channel_ready => '1',
source_ready => test_signal_ready,
in_data => msa_merged_data,
out_data => signal_data
);
i_scrambler_reset_inserter : scrambler_reset_inserter
port map (
clk => clk,
in_data => signal_data,
out_data => sr_inserted_data
);
-- Bypass the scrambler for the test pattens.
c0s0 <= sr_inserted_data( 8 downto 0);
c0s1 <= sr_inserted_data(17 downto 9);
c1s0 <= sr_inserted_data(26 downto 18);
c1s1 <= sr_inserted_data(35 downto 27);
scramble_bypass <= '1'; -- tx_clock_train or tx_align_train;
i_scrambler : scrambler
port map (
clk => clk,
bypass0 => scramble_bypass,
bypass1 => scramble_bypass,
in_data => sr_inserted_data(17 downto 0),
out_data => scrambled_data(17 downto 0)
);
i_train_channel0: training_and_channel_delay port map (
clk => clk,
channel_delay => "00",
clock_train => '0',
align_train => '0',
in_data => scrambled_data(17 downto 0),
out_data => ch0_data,
out_data0forceneg => ch0_forceneg(0),
out_data1forceneg => ch0_forceneg(1)
);
i_data_to_8b10b: data_to_8b10b port map (
clk => clk,
in_data => ch0_data,
forceneg => ch0_forceneg,
out_data => ch0_symbols
);
process(clK)
begin
if rising_edge(clk) then
rd <= rd - to_unsigned(10,10)
+ unsigned(ch0_symbols(0 downto 0))
+ unsigned(ch0_symbols(1 downto 1))
+ unsigned(ch0_symbols(2 downto 2))
+ unsigned(ch0_symbols(3 downto 3))
+ unsigned(ch0_symbols(4 downto 4))
+ unsigned(ch0_symbols(5 downto 5))
+ unsigned(ch0_symbols(6 downto 6))
+ unsigned(ch0_symbols(7 downto 7))
+ unsigned(ch0_symbols(8 downto 8))
+ unsigned(ch0_symbols(9 downto 9))
+ unsigned(ch0_symbols(10 downto 10))
+ unsigned(ch0_symbols(11 downto 11))
+ unsigned(ch0_symbols(12 downto 12))
+ unsigned(ch0_symbols(13 downto 13))
+ unsigned(ch0_symbols(14 downto 14))
+ unsigned(ch0_symbols(15 downto 15))
+ unsigned(ch0_symbols(16 downto 16))
+ unsigned(ch0_symbols(17 downto 17))
+ unsigned(ch0_symbols(18 downto 18))
+ unsigned(ch0_symbols(19 downto 19));
end if;
end process;
--data_dec0: dec_8b10b port map (
-- RESET => '0',
-- RBYTECLK => clk,
-- AI => ch0_symbols(0),
-- BI => ch0_symbols(1),
-- CI => ch0_symbols(2),
-- DI => ch0_symbols(3),
-- EI => ch0_symbols(4),
-- II => ch0_symbols(5),
-- FI => ch0_symbols(6),
-- GI => ch0_symbols(7),
-- HI => ch0_symbols(8),
-- JI => ch0_symbols(9),
--
-- KO => dec0(8),
-- HO => dec0(7),
-- GO => dec0(6),
-- FO => dec0(5),
-- EO => dec0(4),
-- DO => dec0(3),
-- CO => dec0(2),
-- BO => dec0(1),
-- AO => dec0(0)
-- );
process(clK)
begin
if rising_edge(clK) then
if c0s0 = "111111011" then
if c0s1(8) = '1' then
ccount <= (others => '0');
else
ccount <= (0=>'1',others => '0');
end if;
elsif c0s1 = "111111011" then
ccount <= (others => '0');
elsif c0s0(8) = '0' and c0s1(8) = '0' then
ccount <= ccount + 2;
elsif c0s0(8) = '0' or c0s1(8) = '0' then
ccount <= ccount +1;
end if;
end if;
end process;
process
begin
clk <= '1';
wait for 3.703 ns;
clk <= '0';
wait for 3.703 ns;
end process;
end architecture;
| mit | 679583c64fed306c0716001c86d12823 | 0.44267 | 3.96407 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_procel.vhd | 1 | 10,711 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity tb_ProcEl is
end tb_ProcEl;
architecture arch of tb_ProcEl is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, alu, alu_mult, outreg, op0inreg, op0const,
op0feedback, op1inreg, op1const, op1feedback);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxAB : std_logic := '1';
signal CExE : std_logic := '1';
signal Cfg : procConfigRec;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0) := (others => '0');
signal In0xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In1xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal OutxD : std_logic_vector(DATAWIDTH-1 downto 0);
-- aux. signal for multiplication (full width)
signal MultUxD : unsigned(2*DATAWIDTH-1 downto 0);
signal MultSxD : signed(2*DATAWIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ProcEl
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxABI => ClrxAB,
CExEI => CExE,
ConfigxI => Cfg,
ContextxSI => ContextxS,
In0xDI => In0xD,
In1xDI => In1xD,
OutxDO => OutxD);
-- aux. multiplications
MultUxD <= unsigned(In0xD) * unsigned(In1xD);
MultSxD <= signed(In0xD) * signed(In1xD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= alu; -- test ALU functionality
In0xD <= std_logic_vector(to_unsigned(7, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
Cfg.AluOpxS <= alu_pass0;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_pass1;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_neg0;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_neg1;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_add;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_sub;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_addu;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_subu;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multlo;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multuhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multulo;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_and;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_nand;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_or;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_nor;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_xor;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_xnor;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_not0;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_not1;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_sll;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_srl;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_rol;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_ror;
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= alu_mult; -- test multiplication modes
In0xD <= std_logic_vector(to_signed(-7, DATAWIDTH));
In1xD <= std_logic_vector(to_signed(1, DATAWIDTH));
Cfg.AluOpxS <= alu_multhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multlo;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multuhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multulo;
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_signed(-7, DATAWIDTH));
In1xD <= std_logic_vector(to_signed(2, DATAWIDTH));
Cfg.AluOpxS <= alu_multhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multlo;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multuhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multulo;
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_signed(-7, DATAWIDTH));
In1xD <= std_logic_vector(to_signed(-1, DATAWIDTH));
Cfg.AluOpxS <= alu_multhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multlo;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multuhi;
wait for CLK_PERIOD;
Cfg.AluOpxS <= alu_multulo;
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= outreg; -- test output mux
Cfg.OutMuxS <= '1';
Cfg.AluOpxS <= alu_add;
In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(5, DATAWIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(2, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(3, DATAWIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= op0inreg; -- test operand 0 mux
Cfg.Op0MuxS <= "01"; -- registered input
Cfg.AluOpxS <= alu_add;
In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(5, DATAWIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(2, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(3, DATAWIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= op0const; -- test operand 0 mux
Cfg.Op0MuxS <= "10"; -- constant operand
Cfg.AluOpxS <= alu_pass0;
Cfg.ConstOpxD <= std_logic_vector(to_unsigned(13, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= op0feedback; -- test operand 0 mux
Cfg.Op0MuxS <= "11"; -- feed back registered result
Cfg.AluOpxS <= alu_add;
In1xD <= std_logic_vector(to_unsigned(10, DATAWIDTH));
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= op1inreg; -- test operand 1 mux
Cfg.Op1MuxS <= "01"; -- registered input
Cfg.AluOpxS <= alu_add;
In0xD <= std_logic_vector(to_unsigned(1, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(5, DATAWIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(2, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(3, DATAWIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(4, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= op1const; -- test operand 1 mux
Cfg.Op1MuxS <= "10"; -- constant operand
Cfg.AluOpxS <= alu_pass1;
Cfg.ConstOpxD <= std_logic_vector(to_unsigned(13, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
tbStatus <= op1feedback; -- test operand 1 mux
Cfg.Op1MuxS <= "11"; -- feed back registered result
Cfg.AluOpxS <= alu_add;
In0xD <= std_logic_vector(to_unsigned(10, DATAWIDTH));
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_procConfig;
In0xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 41fd569c68c1fd67f2526fe842173099 | 0.564933 | 3.456276 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt/vtest/adpcm_p0.vhd | 1 | 3,448 | -- c_0_1 op4a
cfg.gridConf(0)(1).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_CONST;
cfg.gridConf(0)(1).procConf.ConstOpxD := i2cfgconst(88);
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(1).procConf.ConstOpxD := i2cfgconst(88);
-- i.2
cfg.gridConf(0)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(2).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
-- c_1_0 op4b
cfg.gridConf(1)(0).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(1)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(1)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(0).procConf.ConstOpxD := i2cfgconst(0);
-- i.2
cfg.gridConf(1)(0).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(2).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(1)(0).procConf.OutMuxS := O_NOREG;
-- c_1_1 op4c
cfg.gridConf(1)(1).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(1).LocalxE(LOCAL_N) := '1';
-- i.2
cfg.gridConf(1)(1).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(2).LocalxE(LOCAL_SE) := '1';
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
-- c_2_0 op1
cfg.gridConf(2)(0).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(0).LocalxE(LOCAL_S) := '1';
-- i.1
cfg.gridConf(2)(0).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(2)(0).routConf.i(1).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(2)(0).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(0).routConf.o.HBusSxE(1) := '1';
-- c_2_1 op19
cfg.gridConf(2)(1).procConf.AluOpxS := alu_rom;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op2
cfg.gridConf(2)(2).procConf.AluOpxS := alu_gt;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(2).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(2).procConf.ConstOpxD := i2cfgconst(88);
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op3
cfg.gridConf(2)(3).procConf.AluOpxS := alu_lt;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(3).procConf.ConstOpxD := i2cfgconst(0);
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
-- c_3_0 op0
cfg.gridConf(3)(0).procConf.AluOpxS := alu_rom;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(0).routConf.i(0).HBusNxE(1) := '1';
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 opt120
cfg.gridConf(3)(1).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(3)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(1).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- c_3_2 feedthrough_c_3_2
cfg.gridConf(3)(2).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- input drivers
cfg.inputDriverConf(0)(3)(1) := '1';
-- output drivers
| bsd-3-clause | 085f392b2194bebcf8f83d8942256aa4 | 0.647332 | 2.072115 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/unitFIR/hdl/unitFIR-Rtl-a.vhd | 1 | 6,607 | -------------------------------------------------------------------------------
-- Title : Finite Impulse Response Filter
-- Author : Steiger Martin <[email protected]>
-------------------------------------------------------------------------------
-- Description : Simple FIR filter structure for damping, amplifying and
-- compounding audio signals
-------------------------------------------------------------------------------
architecture Rtl of FIR is
constant sfixed_high : integer := 0;
constant sfixed_low : integer := -(gDataWidth-1);
constant sfixed_no_ovf : integer := -(gDataWidth/2 -1);
type aCoeffArray is array (gMaxNumCoeffs - 1 downto 0) of sfixed(sfixed_high downto sfixed_low);
subtype aStageAddr is integer range 0 to gMaxNumCoeffs -1;
type aStage is array(0 to gMaxNumCoeffs -1) of sfixed(sfixed_high downto sfixed_low); -- register array for input values
-- *************************
-- FSM STATE DEFINES
-- *************************
type aFilterState is (IDLE, MULT);
-- *************************
-- RECORDS
-- *************************
type filt_record is record
FiltData : sfixed(sfixed_high downto sfixed_low); -- filtered data
MovSample : sfixed(sfixed_high downto sfixed_low);
StageCnt : integer range 0 to gMaxNumCoeffs; -- stage index
CoeffCnt : integer range 0 to gMaxNumCoeffs; -- coeff index
State : aFilterState; -- FSM state
valid : std_ulogic; -- valid signal if filtering for current input value is finished
WriteIndex : integer range 0 to gMaxNumCoeffs; -- write index for stage ring buffer
ReadIndex : integer range 0 to gMaxNumCoeffs; -- read index for stage ring buffer
NumOfReads : integer; -- check signal for number of reads from stages and coeffs
FiltOut : sfixed(sfixed_high downto sfixed_low); -- filter output data
end record;
-- *************************
-- DEFAULT RECORD VALUES
-- *************************
constant filt_def_config : filt_record := (
to_sfixed(0.0, sfixed_high, sfixed_low),
to_sfixed(0.0, sfixed_high, sfixed_low),
0,
0,
IDLE,
--(others => to_sfixed(0.0, sfixed_high, sfixed_low)),
cInactivated,
0,
1,
0,
to_sfixed(0.0, sfixed_high, sfixed_low)
);
-- create the ram memory for the coefficients and the stages (the delayed values z^-1)
signal Coeff : aCoeffArray;
signal Stages : aStage ;
-- create the structures for the FSM
signal R, NxR : filt_record;
subtype result_type is std_logic_vector (gDataWidth-1 downto 0); -- for casting sfixed to std_logic_vector
begin
-- ******************************************************************************
-- READ FROM AND WRITE INTO COEFFICIENT RAM AREA
-- ******************************************************************************
RAMReadWrite: process(csi_clk)
begin
if (rising_edge(csi_clk)) then
if(avs_s0_write = cActivated) then
if(unsigned(avs_s0_address)) < gMaxNumCoeffs then -- write into RAM
Coeff(to_integer(unsigned(avs_s0_address))) <= to_sfixed(avs_s0_writedata(gDataWidth - 1 downto 0), sfixed_high, sfixed_low);
end if;
end if;
avs_s0_readdata(gDataWidth-1 downto 0) <= result_type(Coeff(to_integer(unsigned(avs_s0_address))));
end if;
end process;
-- ******************************************************************************
-- REGISTER PROCESS FOR FILTER
-- ******************************************************************************
REG: process(csi_clk, rsi_reset_n)
begin
if (rsi_reset_n = cnActivated) then
R <= filt_def_config;
elsif (rising_edge(csi_clk)) then
R <= NxR;
end if;
end process;
-- ******************************************************************************
-- COMBINATORICAL PROCESS: FOR MULTIPLICATION AND STORING WITHIN THE STAGES
-- ******************************************************************************
COMB: process(R, asi_valid, asi_data, Coeff)
-- TEMPORARY VARIABLES, NO STORING FUNCTION
variable tmp : sfixed(sfixed_high downto sfixed_low);
variable tmp_b : sfixed(sfixed_high downto sfixed_low);
variable tmp_stages : sfixed(sfixed_high downto sfixed_low);
variable tmp_coeffs : sfixed(sfixed_high downto sfixed_low);
begin
-- default assignments
NxR <= R;
tmp := to_sfixed(0.0, sfixed_high, sfixed_low);
tmp_b := to_sfixed(0.0, sfixed_high, sfixed_low);
tmp_stages := to_sfixed(0.0, sfixed_high, sfixed_low);
tmp_coeffs := to_sfixed(0.0, sfixed_high, sfixed_low);
case(R.State) is
when IDLE => -- wait until input data is valid
if asi_valid = cActivated then
NxR.FiltOut <= R.FiltData;
NxR.FiltData <= to_sfixed(0.0, sfixed_high, sfixed_low); -- reset tmp filter data
NxR.MovSample <= to_sfixed(asi_data, sfixed_high, sfixed_low);
NxR.State <= MULT; -- set next stage
NxR.StageCnt <= R.ReadIndex;
NxR.NumOfReads <= 0;
NxR.CoeffCnt <= 0; -- reset the sub FSM
end if;
NxR.valid <= cInactivated;
when MULT => -- multiply stages and coefficients
-- NxR.valid <= cInactivated;
Stages(R.WriteIndex) <= R.MovSample; --to_sfixed(asi_data, sfixed_high, sfixed_low); -- write new data into stages
-- TODO: do exchange stages value and movSample
--NxR.MovSample <= Stage
--TODO: check the overflow of stagecnt
if (R.CoeffCnt < gMaxNumCoeffs ) then --and R.StageCnt < gNumberOfCoeffs) then --multiply (ATTENTION: size <= 32 Bit)
-- do multiplication of one sample
tmp_coeffs := Coeff(R.CoeffCnt);
tmp_stages := Stages(R.StageCnt);
tmp := resize((tmp_coeffs *tmp_stages), tmp);
--tmp_b := resize(tmp + resize(R.FiltData, tmp), tmp_b);
-- do the addition of all coefficients
NxR.FiltData <= resize(tmp + R.FiltData, NxR.FiltData);
-- NxR.FiltData <= tmp_b;
NxR.CoeffCnt <= R.CoeffCnt + 1;
NxR.StageCnt <= R.StageCnt + 1;
NxR.NumOfReads <= R.NumOfReads + 1;
end if;
if (R.StageCnt >= gMaxNumCoeffs-1) then -- restart (ringbuffer read not finished)
NxR.StageCnt <= 0;
end if;
if (R.NumOfReads >= gMaxNumCoeffs-1) then -- stages finished
if(R.WriteIndex >= gMaxNumCoeffs-1) then
NxR.WriteIndex <= 0;
else
NxR.WriteIndex <= R.WriteIndex + 1;
end if;
if(R.ReadIndex >= gMaxNumCoeffs-1) then
NxR.ReadIndex <= 0;
else
NxR.ReadIndex <= R.ReadIndex + 1;
end if;
NxR.valid <= cActivated;
NxR.State <= IDLE;
end if;
when others => NxR.State <= IDLE;
end case;
end process;
--aso_valid <= asi_valid;
aso_valid <= R.valid;
aso_data <= to_slv(R.FiltOut); --when R.valid = cActivated else to_slv(R.LastFiltered);
end architecture Rtl;
| gpl-3.0 | 9ecae54694da740adb40156efc3de3ce | 0.588013 | 3.477368 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPackages/pkgGlobal/src/Global-p.vhd | 1 | 4,084 | -------------------------------------------------------------------------------
-- Title : Global Project Package
-- Project : ASP-SoC
-------------------------------------------------------------------------------
-- Description: Global definitons
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
package Global is
-----------------------------------------------------------------------------
-- Definitions that are not project specific.
-----------------------------------------------------------------------------
-- Avoid the traps of inverted logic and make the code more text like by
-- reducing numbers.
constant cActivated : std_ulogic := '1';
constant cInactivated : std_ulogic := '0';
-- Now the same for inverted logic.
constant cnActivated : std_ulogic := '0';
constant cnInactivated : std_ulogic := '1';
-- constants for generic parameter gEdgeDetector
constant cDetectRisingEdge : natural := 0;
constant cDetectFallingEdge : natural := 1;
constant cDetectAnyEdge : natural := 2;
-----------------------------------------------------------------------------
-- Project specific definitions that will typically exist for every project.
-----------------------------------------------------------------------------
-- Reset polarity
-- This constant is not used in this project. Instead a low active reset
-- is used.
constant cResetActive : std_ulogic := cnActivated;
-- fract_real
subtype fract_real is real range
-1.0 to 0.99999999999999999999999999999999999999999999999999999999999999999;
type fract_set_t is array (natural range<>) of fract_real;
-- default sample rate
constant default_sample_rate_c : natural := 44117;
constant sample_time : time := 1 sec / real(default_sample_rate_c);
-- data width
-- for streaming interface and audio data
constant data_width_c : natural := 24;
-- intern data type for audio signals and coeffs
subtype audio_data_t is u_sfixed(0 downto -(data_width_c-1));
-- constant for audio data
constant silence_c : audio_data_t := (others => '0');
constant one_c : audio_data_t := (0 => '0', others => '1');
------------------------------------------------------------------------------
-- Function Definitions
------------------------------------------------------------------------------
-- function log2 returns the logarithm of base 2 as an integer
function LogDualis(cNumber : natural) return natural;
function ResizeTruncAbsVal(arg : u_sfixed; size_res : u_sfixed) return sfixed;
end Global;
package body Global is
-- Function LogDualis returns the logarithm of base 2 as an integer.
-- Although the implementation of this function was not done with synthesis
-- efficiency in mind, the function has to be synthesizable, because it is
-- often used in static calculations.
function LogDualis(cNumber : natural) return natural is
-- Initialize explicitly (will have warnings for uninitialized variables
-- from Quartus synthesis otherwise).
variable vClimbUp : natural := 1;
variable vResult : natural := 0;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
function ResizeTruncAbsVal(arg : u_sfixed; -- input
size_res : u_sfixed) -- for size only
return sfixed is
variable vLSB : u_sfixed(arg'range) := (size_res'right => '1', others => '0');
variable vTmp : u_sfixed(arg'left + 1 downto arg'right);
variable vRes : u_sfixed(size_res'range);
begin
if (size_res'length < arg'length) and arg(arg'left) = '1' then
vTmp := arg + vLSB;
else
vTmp := '0' & arg;
end if;
vRes := resize(vTmp, size_res, fixed_saturate, fixed_truncate);
return vRes;
end function;
end Global;
| gpl-3.0 | 8496e16d98e2bdfb03029a72c1ef2d8f | 0.561949 | 4.699655 | false | false | false | false |
plessl/zippy | vhdl/schedulestore.vhd | 1 | 5,076 | ------------------------------------------------------------------------------
-- Schedule store
--
-- Project :
-- File : schedulestore.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-16
-- Last changed: $LastChangedDate: 2004-10-07 11:06:32 +0200 (Thu, 07 Oct 2004) $
------------------------------------------------------------------------------
-- Schedule store implements the RAM used for storing the context scheduler
-- entries. Further the schedule store decodes the information in the schedule
-- RAM i.e. it provides the current context, cycles and next context address
-- to the context scheduler.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-06 CP added documentation
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- memory block
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
entity ScheduleStoreMem is
generic (
WIDTH : integer;
DEPTH : integer); -- context width
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
AddrxDI : in std_logic_vector(log2(DEPTH)-1 downto 0);
DataxDI : in std_logic_vector(WIDTH-1 downto 0);
DataxDO : out std_logic_vector(WIDTH-1 downto 0));
end ScheduleStoreMem;
architecture simple of ScheduleStoreMem is
type memArray is array (DEPTH-1 downto 0) of
std_logic_vector(WIDTH-1 downto 0);
signal MemBlock : memArray;
begin -- simple
DataxDO <= MemBlock(to_integer(unsigned(AddrxDI)));
WriteMemBlock : process (ClkxC, RstxRB)
begin
if RstxRB = '0' then
for i in MemBlock'range loop
MemBlock(i) <= (others => '0');
end loop;
elsif ClkxC'event and ClkxC = '1' then
if WExEI = '1' then
MemBlock(to_integer(unsigned(AddrxDI))) <= DataxDI;
end if;
end if;
end process WriteMemBlock;
end simple;
-----------------------------------------------------------------------------
-- Schedule Store
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity ScheduleStore is
generic (
WRDWIDTH : integer; -- width of instruction word
CONWIDTH : integer; -- width of context field
CYCWIDTH : integer; -- width of cycles field
ADRWIDTH : integer); -- width of address field
-- (defines depth of schedule store)
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
IAddrxDI : in std_logic_vector(ADRWIDTH-1 downto 0);
IWordxDI : in std_logic_vector(WRDWIDTH-1 downto 0);
SPCclrxEI : in std_logic;
SPCloadxEI : in std_logic;
ContextxDO : out std_logic_vector(CONWIDTH-1 downto 0);
CyclesxDO : out std_logic_vector(CYCWIDTH-1 downto 0);
LastxSO : out std_logic);
end ScheduleStore;
architecture simple of ScheduleStore is
component ScheduleStoreMem
generic (
WIDTH : integer;
DEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
AddrxDI : in std_logic_vector(log2(DEPTH)-1 downto 0);
DataxDI : in std_logic_vector(WIDTH-1 downto 0);
DataxDO : out std_logic_vector(WIDTH-1 downto 0));
end component;
signal InstxD : std_logic_vector(WRDWIDTH-1 downto 0);
signal AddrxD : std_logic_vector(ADRWIDTH-1 downto 0);
signal SPCAddrxD : std_logic_vector(ADRWIDTH-1 downto 0);
signal SPCNextAddrxD : std_logic_vector(ADRWIDTH-1 downto 0);
begin -- simple
SchedStoreMem : ScheduleStoreMem
generic map (
WIDTH => WRDWIDTH,
DEPTH => 2**ADRWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExEI,
AddrxDI => AddrxD,
DataxDI => IWordxDI,
DataxDO => InstxD);
SchedPC : Reg_Clr_En
generic map (
WIDTH => ADRWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxEI => SPCclrxEI,
EnxEI => SPCloadxEI,
DinxDI => SPCNextAddrxD,
DoutxDO => SPCAddrxD);
AdrMux : Mux2to1
generic map (
WIDTH => ADRWIDTH)
port map (
SelxSI => WExEI,
In0xDI => SPCAddrxD,
In1xDI => IAddrxDI,
OutxDO => AddrxD);
-- instruction word decoding
ContextxDO <= InstxD(CONWIDTH+CYCWIDTH+ADRWIDTH downto CYCWIDTH+ADRWIDTH+1);
CyclesxDO <= InstxD(CYCWIDTH+ADRWIDTH downto ADRWIDTH+1);
SPCNextAddrxD <= InstxD(ADRWIDTH downto 1);
LastxSO <= InstxD(0);
end simple;
| bsd-3-clause | a62f9ea04475aa421f8129894d30b60a | 0.548857 | 3.868902 | false | false | false | false |
hamsternz/FPGA_DisplayPort | test_benches/tb_800x600_compare.vhd | 1 | 11,775 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:05:06 10/15/2015
-- Design Name:
-- Module Name: C:/repos/HDMI2USB-numato-opsis-sample-code/video/displayport/output/tb_800x600_compare.vhd
-- Project Name: displayport_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: test_source_800_600_RGB_444_colourbars_ch1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_800x600_compare IS
END tb_800x600_compare;
ARCHITECTURE behavior OF tb_800x600_compare IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test_source_800_600_RGB_444_colourbars_ch1
PORT(
M_value : OUT std_logic_vector(23 downto 0);
N_value : OUT std_logic_vector(23 downto 0);
H_visible : OUT std_logic_vector(11 downto 0);
V_visible : OUT std_logic_vector(11 downto 0);
H_total : OUT std_logic_vector(11 downto 0);
V_total : OUT std_logic_vector(11 downto 0);
H_sync_width : OUT std_logic_vector(11 downto 0);
V_sync_width : OUT std_logic_vector(11 downto 0);
H_start : OUT std_logic_vector(11 downto 0);
V_start : OUT std_logic_vector(11 downto 0);
H_vsync_active_high : OUT std_logic;
V_vsync_active_high : OUT std_logic;
flag_sync_clock : OUT std_logic;
flag_YCCnRGB : OUT std_logic;
flag_422n444 : OUT std_logic;
flag_YCC_colour_709 : OUT std_logic;
flag_range_reduced : OUT std_logic;
flag_interlaced_even : OUT std_logic;
flags_3d_Indicators : OUT std_logic_vector(1 downto 0);
bits_per_colour : OUT std_logic_vector(4 downto 0);
stream_channel_count : OUT std_logic_vector(2 downto 0);
clk : IN std_logic;
ready : OUT std_logic;
data : OUT std_logic_vector(72 downto 0)
);
END COMPONENT;
COMPONENT test_source_800_600_RGB_444_ch1
PORT(
M_value : OUT std_logic_vector(23 downto 0);
N_value : OUT std_logic_vector(23 downto 0);
H_visible : OUT std_logic_vector(11 downto 0);
V_visible : OUT std_logic_vector(11 downto 0);
H_total : OUT std_logic_vector(11 downto 0);
V_total : OUT std_logic_vector(11 downto 0);
H_sync_width : OUT std_logic_vector(11 downto 0);
V_sync_width : OUT std_logic_vector(11 downto 0);
H_start : OUT std_logic_vector(11 downto 0);
V_start : OUT std_logic_vector(11 downto 0);
H_vsync_active_high : OUT std_logic;
V_vsync_active_high : OUT std_logic;
flag_sync_clock : OUT std_logic;
flag_YCCnRGB : OUT std_logic;
flag_422n444 : OUT std_logic;
flag_YCC_colour_709 : OUT std_logic;
flag_range_reduced : OUT std_logic;
flag_interlaced_even : OUT std_logic;
flags_3d_Indicators : OUT std_logic_vector(1 downto 0);
bits_per_colour : OUT std_logic_vector(4 downto 0);
stream_channel_count : OUT std_logic_vector(2 downto 0);
clk : IN std_logic;
ready : OUT std_logic;
data : OUT std_logic_vector(72 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal a_M_value : std_logic_vector(23 downto 0);
signal a_N_value : std_logic_vector(23 downto 0);
signal a_H_visible : std_logic_vector(11 downto 0);
signal a_V_visible : std_logic_vector(11 downto 0);
signal a_H_total : std_logic_vector(11 downto 0);
signal a_V_total : std_logic_vector(11 downto 0);
signal a_H_sync_width : std_logic_vector(11 downto 0);
signal a_V_sync_width : std_logic_vector(11 downto 0);
signal a_H_start : std_logic_vector(11 downto 0);
signal a_V_start : std_logic_vector(11 downto 0);
signal a_H_vsync_active_high : std_logic;
signal a_V_vsync_active_high : std_logic;
signal a_flag_sync_clock : std_logic;
signal a_flag_YCCnRGB : std_logic;
signal a_flag_422n444 : std_logic;
signal a_flag_YCC_colour_709 : std_logic;
signal a_flag_range_reduced : std_logic;
signal a_flag_interlaced_even : std_logic;
signal a_flags_3d_Indicators : std_logic_vector(1 downto 0);
signal a_bits_per_colour : std_logic_vector(4 downto 0);
signal a_stream_channel_count : std_logic_vector(2 downto 0);
signal a_ready : std_logic;
signal a_data : std_logic_vector(72 downto 0);
signal b_M_value : std_logic_vector(23 downto 0);
signal b_N_value : std_logic_vector(23 downto 0);
signal b_H_visible : std_logic_vector(11 downto 0);
signal b_V_visible : std_logic_vector(11 downto 0);
signal b_H_total : std_logic_vector(11 downto 0);
signal b_V_total : std_logic_vector(11 downto 0);
signal b_H_sync_width : std_logic_vector(11 downto 0);
signal b_V_sync_width : std_logic_vector(11 downto 0);
signal b_H_start : std_logic_vector(11 downto 0);
signal b_V_start : std_logic_vector(11 downto 0);
signal b_H_vsync_active_high : std_logic;
signal b_V_vsync_active_high : std_logic;
signal b_flag_sync_clock : std_logic;
signal b_flag_YCCnRGB : std_logic;
signal b_flag_422n444 : std_logic;
signal b_flag_YCC_colour_709 : std_logic;
signal b_flag_range_reduced : std_logic;
signal b_flag_interlaced_even : std_logic;
signal b_flags_3d_Indicators : std_logic_vector(1 downto 0);
signal b_bits_per_colour : std_logic_vector(4 downto 0);
signal b_stream_channel_count : std_logic_vector(2 downto 0);
signal b_ready : std_logic;
signal b_data : std_logic_vector(72 downto 0);
signal d_M_value : std_logic_vector(23 downto 0);
signal d_N_value : std_logic_vector(23 downto 0);
signal d_H_visible : std_logic_vector(11 downto 0);
signal d_V_visible : std_logic_vector(11 downto 0);
signal d_H_total : std_logic_vector(11 downto 0);
signal d_V_total : std_logic_vector(11 downto 0);
signal d_H_sync_width : std_logic_vector(11 downto 0);
signal d_V_sync_width : std_logic_vector(11 downto 0);
signal d_H_start : std_logic_vector(11 downto 0);
signal d_V_start : std_logic_vector(11 downto 0);
signal d_H_vsync_active_high : std_logic;
signal d_V_vsync_active_high : std_logic;
signal d_flag_sync_clock : std_logic;
signal d_flag_YCCnRGB : std_logic;
signal d_flag_422n444 : std_logic;
signal d_flag_YCC_colour_709 : std_logic;
signal d_flag_range_reduced : std_logic;
signal d_flag_interlaced_even : std_logic;
signal d_flags_3d_Indicators : std_logic_vector(1 downto 0);
signal d_bits_per_colour : std_logic_vector(4 downto 0);
signal d_stream_channel_count : std_logic_vector(2 downto 0);
signal d_ready : std_logic;
signal d_data : std_logic_vector(72 downto 0);
-- Clock period definitions
constant flag_sync_clock_period : time := 10 ns;
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut1: test_source_800_600_RGB_444_colourbars_ch1 PORT MAP (
M_value => a_M_value,
N_value => a_N_value,
H_visible => a_H_visible,
V_visible => a_V_visible,
H_total => a_H_total,
V_total => a_V_total,
H_sync_width => a_H_sync_width,
V_sync_width => a_V_sync_width,
H_start => a_H_start,
V_start => a_V_start,
H_vsync_active_high => a_H_vsync_active_high,
V_vsync_active_high => a_V_vsync_active_high,
flag_sync_clock => a_flag_sync_clock,
flag_YCCnRGB => a_flag_YCCnRGB,
flag_422n444 => a_flag_422n444,
flag_YCC_colour_709 => a_flag_YCC_colour_709,
flag_range_reduced => a_flag_range_reduced,
flag_interlaced_even => a_flag_interlaced_even,
flags_3d_Indicators => a_flags_3d_Indicators,
bits_per_colour => a_bits_per_colour,
stream_channel_count => a_stream_channel_count,
clk => clk,
ready => a_ready,
data => a_data
);
uut2: test_source_800_600_RGB_444_ch1 PORT MAP (
M_value => b_M_value,
N_value => b_N_value,
H_visible => b_H_visible,
V_visible => b_V_visible,
H_total => b_H_total,
V_total => b_V_total,
H_sync_width => b_H_sync_width,
V_sync_width => b_V_sync_width,
H_start => b_H_start,
V_start => b_V_start,
H_vsync_active_high => b_H_vsync_active_high,
V_vsync_active_high => b_V_vsync_active_high,
flag_sync_clock => b_flag_sync_clock,
flag_YCCnRGB => b_flag_YCCnRGB,
flag_422n444 => b_flag_422n444,
flag_YCC_colour_709 => b_flag_YCC_colour_709,
flag_range_reduced => b_flag_range_reduced,
flag_interlaced_even => b_flag_interlaced_even,
flags_3d_Indicators => b_flags_3d_Indicators,
bits_per_colour => b_bits_per_colour,
stream_channel_count => b_stream_channel_count,
clk => clk,
ready => b_ready,
data => b_data
);
d_M_value <= a_M_value xor b_M_value;
d_N_value <= a_N_value xor b_N_value;
d_H_visible <= a_H_visible xor b_H_visible;
d_V_visible <= a_V_visible xor b_V_visible;
d_H_total <= a_H_total xor b_H_total;
d_V_total <= a_V_total xor b_V_total;
d_H_sync_width <= a_H_sync_width xor b_H_sync_width;
d_V_sync_width <= a_V_sync_width xor b_V_sync_width;
d_H_start <= a_H_start xor b_H_start;
d_V_start <= a_V_start xor b_V_start;
d_H_vsync_active_high <= a_H_vsync_active_high xor b_H_vsync_active_high;
d_V_vsync_active_high <= a_V_vsync_active_high xor b_V_vsync_active_high;
d_flag_sync_clock <= a_flag_sync_clock xor b_flag_sync_clock;
d_flag_YCCnRGB <= a_flag_YCCnRGB xor b_flag_YCCnRGB;
d_flag_422n444 <= a_flag_422n444 xor b_flag_422n444;
d_flag_YCC_colour_709 <= a_flag_YCC_colour_709 xor b_flag_YCC_colour_709;
d_flag_range_reduced <= a_flag_range_reduced xor b_flag_range_reduced;
d_flag_interlaced_even <= a_flag_interlaced_even xor b_flag_interlaced_even;
d_flags_3d_Indicators <= a_flags_3d_Indicators xor b_flags_3d_Indicators;
d_bits_per_colour <= a_bits_per_colour xor b_bits_per_colour;
d_stream_channel_count <= a_stream_channel_count xor b_stream_channel_count;
d_ready <= a_ready xor b_ready;
d_data <= a_data xor b_data;
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for flag_sync_clock_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | a53fdfa10cf37d93d4ae9f3acbe39c04 | 0.607728 | 3.184154 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt/vtest/adpcm_p1.vhd | 1 | 5,514 | -- c_0_0 opt232
cfg.gridConf(0)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(0)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- c_0_1 op13
cfg.gridConf(0)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(0)(1).routConf.i(1).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
-- c_0_2 op14
cfg.gridConf(0)(2).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(0)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(0)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(1).LocalxE(LOCAL_W) := '1';
-- i.2
cfg.gridConf(0)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(2).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(2).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(2).routConf.o.VBusExE(1) := '1';
-- c_0_3 op6
cfg.gridConf(0)(3).procConf.AluOpxS := alu_and;
-- i.0
cfg.gridConf(0)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(3).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(0)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(3).procConf.ConstOpxD := i2cfgconst(7);
-- o.0
cfg.gridConf(0)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(3).routConf.o.HBusNxE(0) := '1';
-- c_1_0 opt230
cfg.gridConf(1)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(1)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- c_1_1 op8
cfg.gridConf(1)(1).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(1).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
cfg.gridConf(1)(1).routConf.o.HBusNxE(0) := '1';
-- c_1_2 op15
cfg.gridConf(1)(2).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_S) := '1';
-- o.0
cfg.gridConf(1)(2).procConf.OutMuxS := O_NOREG;
-- c_1_3 op9
cfg.gridConf(1)(3).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(3).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(1)(3).procConf.OutMuxS := O_NOREG;
-- c_2_0 opt231
cfg.gridConf(2)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- c_2_1 op17
cfg.gridConf(2)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).HBusSxE(0) := '1';
-- i.1
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op11
cfg.gridConf(2)(2).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(2).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op16
cfg.gridConf(2)(3).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(0).VBusExE(1) := '1';
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(1).LocalxE(LOCAL_NW) := '1';
-- i.2
cfg.gridConf(2)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(2).HBusNxE(0) := '1';
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(3).routConf.o.HBusSxE(0) := '1';
-- c_3_0 op10
cfg.gridConf(3)(0).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(0).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(3)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(0).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 opt120
cfg.gridConf(3)(1).procConf.AluOpxS := alu_pass0;
-- o.0
cfg.gridConf(3)(1).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(3)(1).procConf.OutCtxRegSelxS := i2ctx(0);
cfg.gridConf(3)(1).routConf.o.HBusSxE(1) := '1';
-- c_3_2 op7
cfg.gridConf(3)(2).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- i.1
cfg.gridConf(3)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(2).procConf.ConstOpxD := i2cfgconst(4);
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- c_3_3 op12
cfg.gridConf(3)(3).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(3)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(3).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(3)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(3).procConf.ConstOpxD := i2cfgconst(3);
-- o.0
cfg.gridConf(3)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(3).routConf.o.HBusNxE(0) := '1';
-- input drivers
cfg.inputDriverConf(0)(0)(1) := '1';
-- output drivers
| bsd-3-clause | 41553d37bc70b6f6bf72d7d0e9346118 | 0.647624 | 2.058999 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/testePlaca/binToBCD.vhd | 1 | 828 |
-- Create Date: 17:41:55 05/14/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity binToBCD is
Port ( binary : in STD_LOGIC_VECTOR (7 downto 0);
bcd : out STD_LOGIC_VECTOR (9 downto 0)
);
end binToBCD;
architecture Behavioral of binToBCD is
begin
process(binary)
variable var : STD_LOGIC_VECTOR (17 downto 0);
begin
var := "000000000000000000";
var(10 downto 3) := binary;
for i in 0 to 4 loop
if var(11 downto 8) > 4 then
var(11 downto 8) := var(11 downto 8) + 3;
end if;
if var(15 downto 12) > 4 then
var(15 downto 12) := var(15 downto 12) + 3;
end if;
var(17 downto 1) := var(16 downto 0);
end loop;
bcd <= var(17 downto 8);
end process;
end Behavioral;
| mit | 0b189c6651c95cfd3a21dc6d8c972be8 | 0.638889 | 2.816327 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/unitFirFilter/hdl/FirFilter-Rtl-a.vhd | 1 | 6,893 | -------------------------------------------------------------------------------
-- Title : FIR - Filter
-- Author : Franz Steinbacher, Michael Wurm
-------------------------------------------------------------------------------
-- Description : Finite Impule Response Filter with Avalon MM interface for
-- coeffs configuration.
-------------------------------------------------------------------------------
architecture Rtl of FirFilter is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type aMemory is array (0 to coeff_num_g-1) of audio_data_t;
subtype audio_data_t is u_sfixed(0 downto -(data_width_g-1));
type aFirStates is (NewVal, MulSum);
type aFirParam is record
firState : aFirStates;
writeAdr : unsigned(coeff_addr_width_g-1 downto 0);
readAdr : unsigned(coeff_addr_width_g-1 downto 0);
coeffAdr : unsigned(coeff_addr_width_g-1 downto 0);
valDry : std_ulogic;
dDry : audio_data_t;
sum : audio_data_t;
mulRes : audio_data_t;
valWet : std_ulogic;
end record aFirParam;
----------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------
constant cInitFirParam : aFirParam := (firState => NewVal,
writeAdr => (others => '0'),
readAdr => (others => '0'),
coeffAdr => (others => '0'),
valDry => '0',
dDry => (others => '0'),
sum => (others => '0'),
mulRes => (others => '0'),
valWet => '0'
);
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
procedure incr_addr (
signal in_addr : in unsigned(coeff_addr_width_g-1 downto 0);
signal out_addr : out unsigned(coeff_addr_width_g-1 downto 0)
) is
begin
if (in_addr = (coeff_num_g - 1)) then
out_addr <= (others => '0');
else
out_addr <= in_addr + 1;
end if;
end incr_addr;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
signal InputRam : aMemory := (others => (others => '0'));
signal CoeffRam : aMemory;
signal R : aFirParam := cInitFirParam;
signal nxR : aFirParam := cInitFirParam;
signal readVal : audio_data_t := (others => '0');
signal coeffVal : audio_data_t := (others => '0');
-- enable register
signal enable : std_ulogic;
constant pass_in_to_out_c : std_ulogic := '0';
constant filter_c : std_ulogic := '1';
begin
-----------------------------------------------------------------------------
-- MM slave for enable
-----------------------------------------------------------------------------
s1_enable : process (csi_clk, rsi_reset_n) is
begin -- process
if rsi_reset_n = '0' then -- asynchronous reset (active low)
enable <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s1_write = '1' then
enable <= avs_s1_writedata(0);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Coeff RAM
-----------------------------------------------------------------------------
-- write ram
ram_wr : process (csi_clk) is
begin -- process ram_wr
if rising_edge(csi_clk) then -- rising clock edge
if avs_s0_write = '1' then
CoeffRam(to_integer(unsigned(avs_s0_address))) <=
to_sfixed(avs_s0_writedata(data_width_g-1 downto 0), CoeffRam(0));
end if;
end if;
end process ram_wr;
-- read ram
ram_rd : process (csi_clk) is
begin -- process ram_rd
if rising_edge(csi_clk) then -- rising clock edge
coeffVal <= CoeffRam(to_integer(R.coeffAdr));
end if;
end process ram_rd;
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Outputs
----------------------------------------------------------------------------
-- valid
with enable select
aso_valid <=
asi_valid when pass_in_to_out_c,
R.valWet when filter_c,
'X' when others;
-- data
with enable select
aso_data <=
asi_data when pass_in_to_out_c,
to_slv(R.sum) when filter_c,
(others => 'X') when others;
----------------------------------------------------------------------------
-- FSMD
----------------------------------------------------------------------------
Comb : process (R, asi_valid, readVal, coeffVal) is
begin
nxR <= R;
case R.firState is
when NewVal =>
nxR.valWet <= '0';
nxR.sum <= (others => '0');
-- wait here for new sample
if asi_valid = '1' then
nxR.firState <= MulSum;
incr_addr(R.readAdr, nxR.readAdr);
end if;
when MulSum =>
nxR.mulRes <= ResizeTruncAbsVal(readVal * coeffVal, R.mulRes);
nxR.sum <= ResizeTruncAbsVal(R.sum + R.mulRes, R.sum);
if R.coeffAdr = coeff_num_g-1 then
nxR.firState <= NewVal;
nxR.coeffAdr <= (others => '0');
nxR.valWet <= '1';
incr_addr(R.writeAdr, nxR.writeAdr);
end if;
incr_addr(R.coeffAdr, nxR.coeffAdr);
incr_addr(R.readAdr, nxR.readAdr);
when others =>
nxR.firState <= NewVal;
end case;
end process Comb;
----------------------------------------------------------------------------
-- Read and write RAM
----------------------------------------------------------------------------
AccessInputRam : process (csi_clk) is
begin
if rising_edge(csi_clk) then
if asi_valid = '1' then
InputRam(to_integer(R.writeAdr)) <= to_sfixed(asi_data, InputRam(0));
end if;
readVal <= InputRam(to_integer(R.readAdr));
end if;
end process AccessInputRam;
----------------------------------------------------------------------------
-- Register process
----------------------------------------------------------------------------
reg : process (csi_clk, rsi_reset_n) is
begin
if rsi_reset_n = '0' then
R <= cInitFirParam;
elsif rising_edge(csi_clk) then
R <= nxR;
end if;
end process reg;
end architecture;
| gpl-3.0 | b2ecbfb0edb5c85c83372ba06d964322 | 0.391412 | 4.60762 | false | false | false | false |
plessl/zippy | vhdl/decoder.vhd | 1 | 6,574 | ------------------------------------------------------------------------------
-- ZUnit Decoder
--
-- Project :
-- File : decoder.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2005-04-07 11:17:51 +0200 (Thu, 07 Apr 2005) $
------------------------------------------------------------------------------
-- address decoder that decodes the read/write commands on the host
-- interface and generates the appropriate control signals
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-06 CP added documentation
-------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- see ZArchPkg for ZUnit Register Mapping and Functions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
entity Decoder is
generic (
REGWIDTH : integer);
port (
RstxRB : in std_logic;
WrReqxEI : in std_logic;
RdReqxEI : in std_logic;
RegNrxDI : in std_logic_vector(REGWIDTH-1 downto 0);
SystRstxRBO : out std_logic; -- system reset
CCloadxEO : out std_logic; -- cycle counter load
VirtContextNoxEO : out std_logic; -- load number of contexts for
-- virtualization (temporal partitioning)
ContextSchedulerSelectxEO : out std_logic;
Fifo0WExEO : out std_logic; -- FIFO0 WE
Fifo0RExEO : out std_logic; -- FIFO0 RE
Fifo1WExEO : out std_logic; -- FIFO1 WE
Fifo1RExEO : out std_logic; -- FIFO1 RE
CMWExEO : out std_logic_vector(N_CONTEXTS-1 downto 0); -- CfgMem WE
CMLoadPtrxEO : out std_logic_vector(N_CONTEXTS-1 downto 0); -- CfgMemPtr
CSRxEO : out std_logic; -- context sel. load
EngClrCntxtxEO : out std_logic; -- engine clear context
SSWExEO : out std_logic; -- schedule store WE
SSIAddrxDO : out std_logic_vector(SIW_ADRWIDTH-1 downto 0); -- address
ScheduleStartxE : out std_logic; -- schedule start
DoutMuxSO : out std_logic_vector(2 downto 0)); -- Dout mux
end Decoder;
architecture simple of Decoder is
signal SoftRstxRB : std_logic;
begin -- simple
-- system reset
SystRstxRBO <= RstxRB and SoftRstxRB;
Decode : process (WrReqxEI, RdReqxEI, RegNrxDI)
begin -- process Decode
-- default signal assignments
SoftRstxRB <= '1';
CCloadxEO <= '0';
Fifo0WExEO <= '0';
Fifo0RExEO <= '0';
Fifo1WExEO <= '0';
Fifo1RExEO <= '0';
CMWExEO <= (others => '0');
CMLoadPtrxEO <= (others => '0');
CSRxEO <= '0';
EngClrCntxtxEO <= '0';
SSWExEO <= '0';
SSIAddrxDO <= (others => '0');
ScheduleStartxE <= '0';
DoutMuxSO <= (others => '0');
VirtContextNoxEO <= '0';
ContextSchedulerSelectxEO <= '0';
if WrReqxEI = '1' then -- WRITE REQUESTS
case to_integer(unsigned(RegNrxDI)) is
when ZREG_RST =>
SoftRstxRB <= '0';
when ZREG_FIFO0 =>
Fifo0WExEO <= '1';
when ZREG_FIFO1 =>
Fifo1WExEO <= '1';
when ZREG_CYCLECNT =>
CCloadxEO <= '1';
when ZREG_VIRTCONTEXTNO =>
VirtContextNoxEO <= '1';
when ZREG_CONTEXTSCHEDSEL =>
ContextSchedulerSelectxEO <= '1';
when ZREG_CFGMEM0 =>
CMWExEO(0) <= '1';
when ZREG_CFGMEM0PTR =>
CMLoadPtrxEO(0) <= '1';
when ZREG_CFGMEM1 =>
CMWExEO(1) <= '1';
when ZREG_CFGMEM1PTR =>
CMLoadPtrxEO(1) <= '1';
when ZREG_CFGMEM2 =>
CMWExEO(2) <= '1';
when ZREG_CFGMEM2PTR =>
CMLoadPtrxEO(2) <= '1';
when ZREG_CFGMEM3 =>
CMWExEO(3) <= '1';
when ZREG_CFGMEM3PTR =>
CMLoadPtrxEO(3) <= '1';
when ZREG_CFGMEM4 =>
CMWExEO(4) <= '1';
when ZREG_CFGMEM4PTR =>
CMLoadPtrxEO(4) <= '1';
when ZREG_CFGMEM5 =>
CMWExEO(5) <= '1';
when ZREG_CFGMEM5PTR =>
CMLoadPtrxEO(5) <= '1';
when ZREG_CFGMEM6 =>
CMWExEO(6) <= '1';
when ZREG_CFGMEM6PTR =>
CMLoadPtrxEO(6) <= '1';
when ZREG_CFGMEM7 =>
CMWExEO(7) <= '1';
when ZREG_CFGMEM7PTR =>
CMLoadPtrxEO(7) <= '1';
when ZREG_CONTEXTSEL =>
CSRxEO <= '1';
when ZREG_CONTEXTSELCLR =>
CSRxEO <= '1';
EngClrCntxtxEO <= '1';
when ZREG_SCHEDSTART =>
ScheduleStartxE <= '1';
when ZREG_SCHEDIWORD00 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "000";
when ZREG_SCHEDIWORD01 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "001";
when ZREG_SCHEDIWORD02 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "010";
when ZREG_SCHEDIWORD03 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "011";
when ZREG_SCHEDIWORD04 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "100";
when ZREG_SCHEDIWORD05 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "101";
when ZREG_SCHEDIWORD06 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "110";
when ZREG_SCHEDIWORD07 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "111";
when others => assert false report "Corrupt ZREG access" severity error;
end case;
elsif RdReqxEI = '1' then -- READ REQUESTS
case to_integer(unsigned(RegNrxDI)) is
when ZREG_FIFO0 =>
Fifo0RExEO <= '1';
DoutMuxSO <= O"0";
when ZREG_FIFO0LEV =>
DoutMuxSO <= O"1";
when ZREG_FIFO1 =>
Fifo1RExEO <= '1';
DoutMuxSO <= O"2";
when ZREG_FIFO1LEV =>
DoutMuxSO <= O"3";
when ZREG_VIRTCONTEXTNO =>
DoutMuxSO <= O"4";
when ZREG_SCHEDSTATUS =>
DoutMuxSO <= O"6";
when ZREG_CYCLECNT =>
DoutMuxSO <= O"7";
when others => assert false report "Corrupt ZREG access" severity error;
end case;
end if;
end process Decode;
end simple;
| bsd-3-clause | 63fb402674bb4a0d65cd2ad9f50f930c | 0.502738 | 3.470961 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/transceiver_clocking.vhd | 1 | 3,600 | ----------------------------------------------------------------------------------
-- Module Name: transceiver_clocking - Behavioral
--
-- Description: Input buffers for the GTX reference clock
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity transceiver_clocking is
Port ( refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
gtrefclk0 : out STD_LOGIC;
gtrefclk1 : out STD_LOGIC);
end transceiver_clocking;
architecture Behavioral of transceiver_clocking is
signal buffered_clk0 : std_logic;
signal buffered_clk1 : std_logic;
begin
i_buff0: IBUFDS_GTE2 port map (
I => refclk0_p,
IB => refclk0_n,
CEB => '0',
O => gtrefclk0
);
i_buff1: IBUFDS_GTE2 port map (
I => refclk1_p,
IB => refclk1_n,
CEB => '0',
O => gtrefclk1
);
end Behavioral;
| mit | c417ba3b35b7b0df5ef829ec63fb88dc | 0.541389 | 4.597701 | false | false | false | false |
huljar/present-vhdl | sim/present80_axis_tb.vhd | 1 | 4,622 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:37:59 02/28/2017
-- Design Name:
-- Module Name: /home/julian/Projekt/Xilinx Projects/present-vhdl/src/present_tb.vhd
-- Project Name: present-vhdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: present_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_textio.ALL;
USE work.util.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY present80_axis_tb IS
END present80_axis_tb;
ARCHITECTURE behavior OF present80_axis_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT axi_stream_wrapper
GENERIC(
k : key_enum
);
PORT(
ACLK : IN std_logic;
ARESETN : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(31 downto 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TVALID : IN std_logic;
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TDATA : OUT std_logic_vector(31 downto 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TREADY : IN std_logic
);
END COMPONENT;
--Inputs
signal ACLK : std_logic := '0';
signal ARESETN : std_logic := '0';
signal S_AXIS_TDATA : std_logic_vector(31 downto 0) := (others => '0');
signal S_AXIS_TLAST : std_logic := '0';
signal S_AXIS_TVALID : std_logic := '0';
signal M_AXIS_TREADY : std_logic := '0';
--Outputs
signal S_AXIS_TREADY : std_logic;
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(31 downto 0);
signal M_AXIS_TLAST : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
-- Other signals
signal ciphertext : std_logic_vector(63 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: axi_stream_wrapper GENERIC MAP (
k => K_80
) PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
-- Clock process definitions
clk_process: process
begin
ACLK <= '0';
wait for clk_period/2;
ACLK <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable ct: line;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- write plaintext
ARESETN <= '1';
S_AXIS_TVALID <= '1';
S_AXIS_TDATA <= (others => '0');
wait for clk_period;
assert (S_AXIS_TREADY = '1') report "ERROR: axi slave is not ready!" severity error;
wait for clk_period*2;
-- write key
S_AXIS_TDATA <= (others => '1');
wait for clk_period*4;
S_AXIS_TDATA <= (others => '0');
S_AXIS_TVALID <= '0';
wait for clk_period;
assert (S_AXIS_TREADY = '0') report "ERROR: axi slave is still ready after reading data!" severity error;
-- wait for processing
wait for clk_period*34;
assert (M_AXIS_TVALID = '1') report "ERROR: axi master is not ready in time!" severity error;
-- read ciphertext
M_AXIS_TREADY <= '1';
wait for clk_period;
ciphertext(63 downto 32) <= M_AXIS_TDATA;
wait for clk_period;
ciphertext(31 downto 0) <= M_AXIS_TDATA;
wait for clk_period;
assert (M_AXIS_TVALID = '0') report "ERROR: axi master is still valid after writing all output!" severity error;
M_AXIS_TREADY <= '0';
-- print ciphertext
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: E72C46C0F5945049)";
deallocate(ct);
wait;
end process;
END;
| mit | 0008f7b6c9be2509705c66529890ec91 | 0.592168 | 3.691693 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/scrambler_all_channels.vhd | 1 | 7,582 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: scrambler_all_channels - Behavioral
-- Description: A x^16+x^5+x^4+x^3+1 LFSR scxrambler for DisplayPort
--
-- Scrambler LFSR is reset when a K.28.0 passes through it,
-- as per the DisplayPort spec.
--
-- Verified against the table in Apprndix C of the "PCI Express Base
-- Specification 2.1" which uses the same polynomial.
--
-- Here are the first 32 output words when data values of "00" are scrambled:
--
-- | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
-- ---+------------------------------------------------
-- 00 | FF 17 C0 14 B2 E7 02 82 72 6E 28 A6 BE 6D BF 8D
-- 10 | BE 40 A7 E6 2C D3 E2 B2 07 02 77 2A CD 34 BE E0
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity scrambler_all_channels is
Port ( clk : in STD_LOGIC;
bypass0 : in STD_LOGIC;
bypass1 : in STD_LOGIC;
in_data : in STD_LOGIC_VECTOR (71 downto 0);
out_data : out STD_LOGIC_VECTOR (71 downto 0) := (others => '0'));
end scrambler_all_channels;
architecture Behavioral of scrambler_all_channels is
type a_delay_line is array(0 to 7) of STD_LOGIC_VECTOR (17 downto 0);
signal lfsr_state : STD_LOGIC_VECTOR (15 downto 0) := (others => '1');
constant SR : STD_LOGIC_VECTOR ( 8 downto 0) := "100011100"; -- K28.0 ia used to reset the scrambler
signal scramble_delay : a_delay_line := (others => (others => '0'));
begin
process(clk)
variable s0 : STD_LOGIC_VECTOR (15 downto 0);
variable s1 : STD_LOGIC_VECTOR (15 downto 0);
variable flipping : STD_LOGIC_VECTOR (17 downto 0);
begin
if rising_edge(clk) then
s0 := lfsr_state;
-- generate intermediate scrambler state
if in_data(8 downto 0) = SR then
s1 := x"FFFF";
else
s1(0) := s0(8);
s1(1) := s0(9);
s1(2) := s0(10);
s1(3) := s0(11) xor s0(8);
s1(4) := s0(12) xor s0(8) xor s0(9);
s1(5) := s0(13) xor s0(8) xor s0(9) xor s0(10);
s1(6) := s0(14) xor s0(9) xor s0(10) xor s0(11);
s1(7) := s0(15) xor s0(10) xor s0(11) xor s0(12);
s1(8) := s0(0) xor s0(11) xor s0(12) xor s0(13);
s1(9) := s0(1) xor s0(12) xor s0(13) xor s0(14);
s1(10) := s0(2) xor s0(13) xor s0(14) xor s0(15);
s1(11) := s0(3) xor s0(14) xor s0(15);
s1(12) := s0(4) xor s0(15);
s1(13) := s0(5);
s1(14) := s0(6);
s1(15) := s0(7);
end if;
-- Update scrambler state
if in_data(17 downto 9) = SR then
lfsr_state <= x"FFFF";
else
lfsr_state(0) <= s1(8);
lfsr_state(1) <= s1(9);
lfsr_state(2) <= s1(10);
lfsr_state(3) <= s1(11) xor s1(8);
lfsr_state(4) <= s1(12) xor s1(8) xor s1(9);
lfsr_state(5) <= s1(13) xor s1(8) xor s1(9) xor s1(10);
lfsr_state(6) <= s1(14) xor s1(9) xor s1(10) xor s1(11);
lfsr_state(7) <= s1(15) xor s1(10) xor s1(11) xor s1(12);
lfsr_state(8) <= s1(0) xor s1(11) xor s1(12) xor s1(13);
lfsr_state(9) <= s1(1) xor s1(12) xor s1(13) xor s1(14);
lfsr_state(10) <= s1(2) xor s1(13) xor s1(14) xor s1(15);
lfsr_state(11) <= s1(3) xor s1(14) xor s1(15);
lfsr_state(12) <= s1(4) xor s1(15);
lfsr_state(13) <= s1(5);
lfsr_state(14) <= s1(6);
lfsr_state(15) <= s1(7);
end if;
--------------------------------------------
-- Calculate a vector of bits to be flipped
--------------------------------------------
if in_data(8) = '0' and bypass0 = '0' then
flipping(8 downto 0) := '0' & s0(8) & s0(9) & s0(10) & s0(11) & s0(12) & s0(13) & s0(14) & s0(15);
else
flipping(8 downto 0) := (others => '0');
end if;
if in_data(17) = '0' and bypass1 = '0' then
flipping(17 downto 9) := '0' & s1(8) & s1(9) & s1(10) & s1(11) & s1(12) & s1(13) & s1(14) & s1(15);
else
flipping(17 downto 9) := (others => '0');
end if;
--------------------------------------------
-- Apply vector to channel 0
--------------------------------------------
out_data <= in_data xor (flipping & flipping & flipping & flipping );
end if;
end process;
end Behavioral;
| mit | d5e26ed420d3935aea4d4458e029aaa7 | 0.470852 | 3.624283 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstmux/tstmux_cfg.vhd | 1 | 3,971 | ------------------------------------------------------------------------------
-- Configuration for mux testbench
--
-- Project :
-- File : $URL: $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/27
-- Last changed: $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
-- ZUnit configuration for MUX testbench. This testbench is used for testing
-- the multiplexer function alu_mux. The ALU MUX instruction needs special
-- testing, since it is the first ternary operation on the Zippy array.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-37 CP created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTMUX is
function tstmuxcfg return engineConfigRec;
end CfgLib_TSTMUX;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTMUX is
----------------------------------------------------------------------------
-- tstmux configuration
-- configure alu in cell row 2, col 3
-- connect INP0 and INP1 to inputs and OP0 to output
----------------------------------------------------------------------------
function tstmuxcfg return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- configure cell_2_3
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(3).procConf.OutMuxS := O_REG;
cfg.gridConf(2)(3).procConf.AluOpxS := ALU_OP_MUX;
-- feed input 0 from hbusn_2.0
cfg.gridConf(2)(3).routConf.i(0).HBusNxE(1) := '1';
-- feed input 1 from hbusn_2.1
cfg.gridConf(2)(3).routConf.i(1).HBusNxE(0) := '1';
-- feed input 2 also from hbusn_2.0
cfg.gridConf(2)(3).routConf.i(2).HBusNxE(1) := '1';
-- drive output to hbusn_3.1 (HBus_CD1)
cfg.gridConf(2)(3).routConf.o.HBusNxE(1) := '1';
-- feed busses of engine from input ports
cfg.inputDriverConf(0)(2)(1) := '1'; -- connect INP0 to hbusn_2.1
cfg.inputDriverConf(1)(2)(0) := '1'; -- connect INP1 to hbusn_2.0
-- engine outputs
cfg.outputDriverConf(0)(3)(1) := '1'; -- connect OP0 to hbusn_3.1
-- i/o port controller
-- activate write to output FIFO0 after 2 cycles
cfg.outportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEUP;
cfg.outportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.outportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(1, CCNTWIDTH));
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
-- deactivate read from input FIFO0 2 cycles before end
cfg.inportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
cfg.inportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.inportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
cfg.inportConf(1).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
cfg.inportConf(1).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.inportConf(1).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_CMP0;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstmuxcfg;
end CfgLib_TSTMUX;
| bsd-3-clause | bfd5223bac149bc56730f9c9f4bca188 | 0.540922 | 3.48028 | false | true | false | false |
hamsternz/FPGA_DisplayPort | src/aux_interface.vhd | 1 | 21,664 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: aux_interface - Behavioral
--
-- Description: The low-level interface to the DisplayPort AUX channel.
--
-- This encapsulates a small RX and TX FIFO. To use place all the words you want
-- to send into the TX fifo, and then monitor 'busy' and 'timeout'. Any received
-- data will be in the RX FIFO.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity aux_interface is
port (
clk : in std_logic;
debug_pmod : out std_logic_vector(7 downto 0);
------------------------------
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic;
------------------------------
tx_wr_en : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_full : out std_logic;
------------------------------
rx_rd_en : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_empty : out std_logic;
------------------------------
busy : out std_logic := '0';
timeout : out std_logic := '0'
);
end aux_interface;
architecture arch of aux_interface is
type a_small_buffer is array (0 to 31) of std_logic_vector(7 downto 0);
------------------------------------------
-- A small fifo to send data from
------------------------------------------
type t_tx_state is (tx_idle, tx_sync, tx_start, tx_send_data, tx_stop, tx_flush, tx_waiting);
signal tx_state : t_tx_state := tx_idle;
signal tx_fifo : a_small_buffer;
signal tx_rd_ptr : unsigned(4 downto 0) := (others => '0');
signal tx_wr_ptr : unsigned(4 downto 0) := (others => '0');
signal tx_wr_ptr_plus_1 : unsigned(4 downto 0) := (others => '0');
signal timeout_count : unsigned(15 downto 0) := (others => '0');
signal tx_empty : std_logic := '0';
signal tx_full_i : std_logic := '0';
signal tx_rd_data : std_logic_vector(7 downto 0) := (others => '0');
signal tx_rd_en : std_logic := '0';
signal snoop : std_logic := '0';
signal serial_data : std_logic := '0';
signal tristate : std_logic := '0';
signal bit_counter : unsigned(7 downto 0) := (others => '0');
constant bit_counter_max : unsigned(7 downto 0) := to_unsigned(49, 8);
signal data_sr : std_logic_vector(15 downto 0);
signal busy_sr : std_logic_vector(15 downto 0);
type t_rx_state is (rx_waiting, rx_receiving_data, rx_done);
signal rx_state : t_rx_state := rx_waiting;
signal rx_fifo : a_small_buffer;
signal rx_wr_ptr : unsigned(4 downto 0) := (others => '0');
signal rx_wr_ptr_plus_1 : unsigned(4 downto 0) := (others => '0');
signal rx_rd_ptr : unsigned(4 downto 0) := (others => '0');
signal rx_reset : std_logic;
signal rx_empty_i : std_logic := '0';
signal rx_full : std_logic := '0';
signal rx_wr_data : std_logic_vector(7 downto 0) := (others => '0');
signal rx_wr_en : std_logic := '0';
signal rx_count : unsigned(5 downto 0) := (others => '0');
signal rx_buffer : std_logic_vector(15 downto 0) := (others => '0');
signal rx_bits : std_logic_vector(15 downto 0) := (others => '0');
signal rx_a_bit : std_logic := '0';
signal rx_last : std_logic := '0';
signal rx_synced : std_logic := '0';
signal rx_meta : std_logic := '0';
signal rx_raw : std_logic := '0';
signal rx_finished : std_logic := '0';
signal rx_holdoff : std_logic_vector(9 downto 0) :=(others => '0');
begin
debug_pmod(3 downto 0) <= "000" & snoop;
----------------------------------------------
-- Async logic for the FIFO state and pointers
----------------------------------------------
rx_wr_ptr_plus_1 <= rx_wr_ptr+1;
tx_wr_ptr_plus_1 <= tx_wr_ptr+1;
rx_empty_i <= '1' when rx_wr_ptr = rx_rd_ptr else '0';
rx_full <= '1' when rx_wr_ptr_plus_1 = rx_rd_ptr else '0';
tx_empty <= '1' when tx_wr_ptr = tx_rd_ptr else '0';
tx_full_i <= '1' when tx_wr_ptr_plus_1 = tx_rd_ptr else '0';
rx_empty <= rx_empty_i;
tx_full <= tx_full_i;
busy <= '0' when tx_empty = '1' and tx_state = tx_idle else '1';
clk_proc: process(clk)
begin
if rising_edge(clk) then
----------------------------------
-- Defaults, overwritten as needed
----------------------------------
tx_rd_en <= '0';
rx_reset <= '0';
timeout <= '0';
-----------------------------------
-- Is it time to send the next bit?
-----------------------------------
if bit_counter = bit_counter_max then
bit_counter <= (others => '0');
serial_data <= data_sr(data_sr'high);
tristate <= not busy_sr(busy_sr'high);
data_sr <= data_sr(data_sr'high-1 downto 0) & '0';
busy_sr <= busy_sr(busy_sr'high-1 downto 0) & '0';
---------------------------------------------------
-- Logic to signal the RX module ignore the data we
-- are actually sending for 10 cycles. This is save
-- as the sync pattern is quite long.
-------------------------------------------
if tx_state = tx_waiting then
rx_holdoff <= rx_holdoff(rx_holdoff'high-1 downto 0) & '0';
else
rx_holdoff <= (others => '1');
end if;
--------------------------------------------------
-- Debug signals that are presented to the outside
--------------------------------------------------
case tx_state is
when tx_idle => debug_pmod(7 downto 4) <= x"0";
when tx_sync => debug_pmod(7 downto 4) <= x"1";
when tx_start => debug_pmod(7 downto 4) <= x"2";
when tx_send_data => debug_pmod(7 downto 4) <= x"3";
when tx_stop => debug_pmod(7 downto 4) <= x"4";
when tx_flush => debug_pmod(7 downto 4) <= x"5";
when tx_waiting => debug_pmod(7 downto 4) <= x"6";
when others => debug_pmod(7 downto 4) <= x"A";
end case;
-------------------------------------
-- What to do with with the FSM state
-------------------------------------
if busy_sr(busy_sr'high-1) = '0' then
case tx_state is
when tx_idle =>
if tx_empty = '0' then
data_sr <= "0101010101010101";
busy_sr <= "1111111111111111";
tx_state <= tx_sync;
end if;
when tx_sync =>
data_sr <= "0101010101010101";
busy_sr <= "1111111111111111";
tx_state <= tx_start;
when tx_start =>
-----------------------------------------------------
-- Just send the start pattern.
--
-- The TX fifo must have something in it to get here.
-----------------------------------------------------
data_sr <= "1111000000000000";
busy_sr <= "1111111100000000";
tx_state <= tx_send_data;
rx_reset <= '1';
tx_rd_en <= '1';
when tx_send_data =>
data_sr <= tx_rd_data(7) & not tx_rd_data(7) & tx_rd_data(6) & not tx_rd_data(6)
& tx_rd_data(5) & not tx_rd_data(5) & tx_rd_data(4) & not tx_rd_data(4)
& tx_rd_data(3) & not tx_rd_data(3) & tx_rd_data(2) & not tx_rd_data(2)
& tx_rd_data(1) & not tx_rd_data(1) & tx_rd_data(0) & not tx_rd_data(0);
busy_sr <= "1111111111111111";
if tx_empty = '1' then
-- Send this word, and follow it up with a STOP
tx_state <= tx_stop;
else
-- Send this word, and also read the next one from the FIFO
tx_rd_en <= '1';
end if;
when tx_stop =>
------------------------
-- Send the STOP pattern
------------------------
data_sr <= "1111000000000000";
busy_sr <= "1111111100000000";
tx_state <= tx_flush;
when tx_flush =>
---------------------------------------------
-- Just wait here until we are no longer busy
---------------------------------------------
tx_state <= tx_waiting;
when others => NULL;
end case;
end if;
else
------------------------------------
-- Not time yet to send the next bit
------------------------------------
bit_counter <= bit_counter + 1;
end if;
-----------------------------------------------
-- How the RX process indicates that we are now
-- free to send another transaction
-----------------------------------------------
if tx_state = tx_waiting and rx_finished = '1' then
tx_state <= tx_idle;
end if;
---------------------------------------------
-- Managing the TX FIFO
-- As soon as a word appears in the FIFO it
-- is sent. As it takes 8us to send a byte, the
-- FIFO can be filled quicker than data is sent,
-- ensuring we don't have underrun the TX FIFO
-- and send a short message.
---------------------------------------------
if tx_full_i = '0' and tx_wr_en = '1' then
tx_fifo(to_integer(tx_wr_ptr)) <= tx_data;
tx_wr_ptr <= tx_wr_ptr+1;
end if;
if tx_empty = '0' and tx_rd_en = '1' then
tx_rd_data <= tx_fifo(to_integer(tx_rd_ptr));
tx_rd_ptr <= tx_rd_ptr + 1;
end if;
--------------------------------------------------
-- Managing the RX FIFO
--
-- The contents of the FIFO is reset during the TX
-- of a new transaction. Pointer updates are
-- seperated from the data read / writes to allow
-- the reset to work.
--------------------------------------------------
if rx_full = '0' and rx_wr_en = '1' then
rx_fifo(to_integer(rx_wr_ptr)) <= rx_wr_data;
end if;
if rx_empty_i = '0' and rx_rd_en = '1' then
rx_data <= rx_fifo(to_integer(rx_rd_ptr));
end if;
if rx_reset = '1' then
rx_wr_ptr <= rx_rd_ptr;
else
if rx_full = '0' and rx_wr_en = '1' then
rx_wr_ptr <= rx_wr_ptr+1;
end if;
if rx_empty_i = '0' and rx_rd_en = '1' then
rx_rd_ptr <= rx_rd_ptr + 1;
end if;
end if;
------------------------------------------
-- Manage the timeout. If it is
-- waiting for a reply for over 400us then
-- signal a timeout to the upper FSM.
------------------------------------------
if bit_counter = bit_counter_max then
if tx_state = tx_waiting and tx_state = tx_waiting then
if timeout_count = 39999 then
tx_state <= tx_idle;
timeout <= '1';
else
timeout_count <= timeout_count + 1;
end if;
else
timeout_count <= (others => '0');
end if;
end if;
end if;
end process;
i_IOBUFDS_0 : IOBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => rx_raw,
IO => dp_tx_aux_p,
IOB => dp_tx_aux_n,
I => serial_data,
T => tristate
);
rx_proc: process(clk)
begin
if rising_edge(clk) then
rx_wr_en <= '0';
rx_finished <= '0';
----------------------------------
-- Is it time to sample a new half-bit?
----------------------------------
if rx_count = 49 then
rx_a_bit <= '1';
rx_buffer <= rx_buffer(rx_buffer'high-1 downto 0) & rx_synced;
rx_bits <= rx_bits(rx_bits'high-1 downto 0) & '1';
rx_count <= (others => '0');
else
rx_count <= rx_count+1;
rx_a_bit <= '0';
end if;
----------------------------------------
-- Have we just sampled a new half-bit?
----------------------------------------
if rx_a_bit = '1' then
case rx_state is
when rx_waiting =>
-----------------------------------------------------
-- Are we seeing the end of the SYNC/START sequence?
-----------------------------------------------------
if rx_buffer = "0101010111110000" then
rx_bits <= (others => '0');
if rx_holdoff(rx_holdoff'high) = '0' then
--------------------------------------
-- Yes, switch to receiving bits, but,
-- but only if the TX modules hasn't
-- transmitted for a short while....
--------------------------------------
rx_state <= rx_receiving_data;
end if;
end if;
when rx_receiving_data =>
---------------------------------------------------------
-- Have we just received the 16th half-bit of the a byte?
---------------------------------------------------------
if rx_bits(rx_bits'high) = '1' then
rx_bits <= (others => '0');
------------------------------------------------
-- Are we missing transistions that are required
-- for valid data bytes?
--
-- Or in other words, is this an error or (more
-- usually) the STOP pattern?
-------------------------------------------------
if rx_buffer(15) = rx_buffer(14) or rx_buffer(13) = rx_buffer(12) or
rx_buffer(11) = rx_buffer(10) or rx_buffer( 9) = rx_buffer( 8) or
rx_buffer( 7) = rx_buffer( 6) or rx_buffer( 5) = rx_buffer( 4) or
rx_buffer( 3) = rx_buffer( 2) or rx_buffer( 1) = rx_buffer( 0) then
----------------------------------------------------------
-- Yes, We finished receiving data, or truncate any errors
----------------------------------------------------------
rx_state <= rx_waiting;
if rx_holdoff(rx_holdoff'high) = '0' then
rx_finished <= '1';
end if;
else
---------------------------------------------------
-- Looks like a valid byte, so write it to the FIFO
----------------------------------------------------
rx_wr_data <= rx_buffer(15) & rx_buffer(13) & rx_buffer(11) & rx_buffer(9)
& rx_buffer( 7) & rx_buffer( 5) & rx_buffer( 3) & rx_buffer(1);
rx_wr_en <= '1';
end if;
end if;
when rx_done =>
null; -- waiting to be reset (so I ignore noise!)
when others =>
rx_state <= rx_waiting;
end case;
end if;
-------------------------------------------------
-- Detect the change on the AUX line, and
-- make sure we sample the data mid-way through
-- the half-bit (e.g 0.25us, 0.75us, 1.25 us...)
-- from when the last transition was seen.
------------------------------------------------
if rx_synced /= rx_last then
rx_count <= to_unsigned(25, 6);
end if;
-------------------------------------------------
-- The transmitted resets the RX FSM when it is
-- sending a request. This is a counter measure
-- against line noise when neigher end is driving
-- the link.
-------------------------------------------------
if rx_reset = '1' then
rx_state <= rx_waiting;
end if;
rx_last <= rx_synced;
----------------------------
-- Synchronise the RX signal
----------------------------
rx_synced <= rx_meta;
snoop <= rx_meta;
--------------------------------------------------------
-- This is done to convert Zs or Xs in simulations to 0s
--------------------------------------------------------
if rx_raw = '1' then
rx_meta <= '1';
else
rx_meta <= '0';
end if;
end if;
end process;
-- Stub off the unused inputs
i_IOBUFDS_1 : IOBUFDS
generic map (
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => open,
IO => dp_rx_aux_p,
IOB => dp_rx_aux_n,
I => '0',
T => '1'
);
end architecture; | mit | db2e2099e0d352e0cd50e0764b36c7b2 | 0.392033 | 4.593723 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPrimitives/unitMultiply/hdl/tbMultiply-Bhv-ea.vhd | 1 | 4,573 | -------------------------------------------------------------------------------
-- Title : Multiply
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Unit Multiply multiplies L and R channel with a factor
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
use work.Global.all;
use work.sin_4096.all;
entity tbMultiply is
end entity tbMultiply;
architecture bhv of tbMultiply is
--constant strobe_time : time := 1 sec/real(44117);
constant strobe_time : time := 200 ns;
constant data_width_g : natural := 24;
constant left_fact : real := 0.5;
constant right_fact : real := 0.5;
subtype audio_data_t is u_sfixed(0 downto -(data_width_g-1));
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal avs_s0_write : std_logic;
signal avs_s0_address : std_logic;
signal avs_s0_writedata : std_logic_vector(31 downto 0) := (others => '0');
signal asi_left_data : std_logic_vector(data_width_g-1 downto 0);
signal asi_left_valid : std_logic;
signal asi_right_data : std_logic_vector(data_width_g-1 downto 0);
signal asi_right_valid : std_logic;
signal aso_left_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_left_valid : std_logic;
signal aso_right_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_right_valid : std_logic;
signal left_data : audio_data_t;
signal right_data : audio_data_t;
-- test time
constant test_time_c : time := 20 ns;
-- audio data
signal sample_strobe, strobe2 : std_ulogic := '0';
signal audio_data : u_sfixed(0 downto -(data_width_g-1)) := (others => '0');
begin
DUT : entity work.Multiply
generic map (
data_width_g => data_width_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
avs_s0_write => avs_s0_write,
avs_s0_address => avs_s0_address,
avs_s0_writedata => avs_s0_writedata,
asi_left_data => asi_left_data,
asi_left_valid => asi_left_valid,
asi_right_data => asi_right_data,
asi_right_valid => asi_right_valid,
aso_left_data => aso_left_data,
aso_left_valid => aso_left_valid,
aso_right_data => aso_right_data,
aso_right_valid => aso_right_valid);
left_data <= to_sfixed(aso_left_data, 0, -(data_width_g-1));
right_data <= to_sfixed(aso_right_data, 0, -(data_width_g-1));
-- clk generation
csi_clk <= not csi_clk after 10 ns;
-- sample strobe generation
strobe : process is
begin -- process
wait for strobe_time;
wait until rising_edge(csi_clk);
sample_strobe <= '1';
wait until rising_edge(csi_clk);
sample_strobe <= '0';
end process;
strobe_2 : process is
begin
wait until sample_strobe = '1';
wait until rising_edge(csi_clk);
strobe2 <= '1';
wait until rising_edge(csi_clk);
strobe2 <= '0';
end process strobe_2;
-- sinus as audio data
aud_data : process is
begin -- process
for idx in 0 to sin_table_c'length-1 loop
wait until rising_edge(sample_strobe);
audio_data <= to_sfixed(sin_table_c(idx), 0, -(data_width_g-1));
end loop; -- idx
end process aud_data;
-- channel left and right with sinus
--asi_right_data <= to_slv(to_sfixed(real(0.5), 0, -(data_width_g-1)));
asi_right_data <= to_slv(audio_data);
asi_left_data <= to_slv(audio_data);
asi_right_valid <= sample_strobe;
asi_left_valid <= sample_strobe;
test_process : process is
begin -- process
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
avs_s0_write <= '0';
wait for 100 ns;
-- write factors
-- left
avs_s0_address <= '0';
avs_s0_writedata(data_width_g-1 downto 0) <= to_slv(to_sfixed(left_fact, 0, -(data_width_g-1)));
avs_s0_write <= '1';
wait for 20 ns;
avs_s0_write <= '0';
wait for 20 ns;
-- right
avs_s0_address <= '1';
avs_s0_writedata(data_width_g-1 downto 0) <= to_slv(to_sfixed(right_fact, 0, -(data_width_g-1)));
avs_s0_write <= '1';
wait for 20 ns;
avs_s0_write <= '0';
wait;
end process;
end architecture bhv;
| gpl-3.0 | d1f56eebcbd649689779b88ba6cbaf08 | 0.552591 | 3.304191 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/aux_channel.vhd | 1 | 35,744 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: aux_channel - Behavioral
--
-- Description: A more usable interface for sending/receiving data over the
-- DisplayPort AUX channel. It also implements the timeout.
--
------------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity aux_channel is
port (
clk : in std_logic;
debug_pmod : out std_logic_vector(7 downto 0);
------------------------------
edid_de : out std_logic;
dp_reg_de : out std_logic;
adjust_de : out std_logic;
status_de : out std_logic;
aux_addr : out std_logic_vector(7 downto 0);
aux_data : out std_logic_vector(7 downto 0);
------------------------------
link_count : in std_logic_vector(2 downto 0);
------------------------------
hpd_irq : in std_logic;
hpd_present : in std_logic;
------------------------------
tx_powerup : out std_logic := '0';
tx_clock_train : out std_logic := '0';
tx_align_train : out std_logic := '0';
tx_link_established : out std_logic := '0';
-------------------------------
swing_0p4 : in std_logic;
swing_0p6 : in std_logic;
swing_0p8 : in std_logic;
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
clock_locked : in STD_LOGIC;
equ_locked : in STD_LOGIC;
symbol_locked : in STD_LOGIC;
align_locked : in STD_LOGIC;
------------------------------
dp_tx_hp_detect : in std_logic;
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic
);
end entity;
architecture arch of aux_channel is
type t_state is ( error, reset, check_presence,
-- Gathering Display information
edid_block0, edid_block1, edid_block2, edid_block3,
edid_block4, edid_block5, edid_block6, edid_block7,
-- Gathering display Port information
read_sink_count, read_registers,
-- Link configuration states
set_channel_coding, set_speed_270, set_downspread, set_link_count_1, set_link_count_2, set_link_count_4,
-- Link training - clock recovery
clock_training, clock_voltage_0p4, clock_voltage_0p6, clock_voltage_0p8, clock_wait, clock_test, clock_adjust, clock_wait_after,
-- Link training - alignment and preemphasis
align_training,
align_p0_V0p4, align_p0_V0p6, align_p0_V0p8,
align_p1_V0p4, align_p1_V0p6, align_p1_V0p8,
align_p2_V0p4, align_p2_V0p6, align_p2_V0p8,
align_wait0, align_wait1, align_wait2, align_wait3,
align_test, align_adjust, align_wait_after,
-- Link up.
switch_to_normal, link_established,
--
check_link, check_wait
);
signal state : t_state := error;
signal next_state : t_state := error;
signal state_on_success : t_state := error;
signal retry_now : std_logic := '0';
signal retry_count : unsigned(26 downto 0) := (9=>'1',others => '0');
signal link_check_now : std_logic := '0';
signal link_check_count : unsigned(26 downto 0) := (9=>'1',others => '0');
signal count_100us : unsigned(14 downto 0) := to_unsigned(1000,15);
component dp_aux_messages is
port ( clk : in std_logic;
-- Interface to send messages
msg_de : in std_logic;
msg : in std_logic_vector(7 downto 0);
busy : out std_logic;
--- Interface to the AUX Channel
aux_tx_wr_en : out std_logic;
aux_tx_data : out std_logic_vector(7 downto 0)
);
end component;
component aux_interface is
port (
clk : in std_logic;
debug_pmod : out std_logic_vector(7 downto 0);
------------------------------
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic;
------------------------------
tx_wr_en : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_full : out std_logic;
------------------------------
rx_rd_en : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_empty : out std_logic;
------------------------------
busy : out std_logic;
timeout : out std_logic
);
end component;
signal adjust_de_active : std_logic := '0';
signal dp_reg_de_active : std_logic := '0';
signal edid_de_active : std_logic := '0';
signal status_de_active : std_logic := '0';
signal msg_de : std_logic := '0';
signal msg : std_logic_vector(7 downto 0);
signal msg_busy : std_logic := '0';
signal aux_tx_wr_en : std_logic;
signal aux_tx_data : std_logic_vector(7 downto 0);
signal aux_rx_rd_en : std_logic;
signal aux_rx_data : std_logic_vector(7 downto 0);
signal aux_rx_empty : std_logic;
signal link_count_sink : std_logic_vector(7 downto 0);
signal channel_busy : std_logic;
signal channel_timeout : std_logic;
signal expected : unsigned(7 downto 0);
signal rx_byte_count : unsigned(7 downto 0) := (others => '0');
signal aux_addr_i : unsigned(7 downto 0) := (others => '0');
signal reset_addr_on_change : std_logic;
signal just_read_from_rx :std_logic := '0';
signal powerup_mask : std_logic_vector(3 downto 0);
signal debug_pmod_i : std_logic_vector(7 downto 0);
begin
debug_pmod(0) <= debug_pmod_i(0);
debug_pmod(1) <= status_de_active;
debug_pmod(2) <= adjust_de_active;
i_aux_messages: dp_aux_messages port map (
clk => clk,
-- Interface to send messages
msg_de => msg_de,
msg => msg,
busy => msg_busy,
--- Interface to the AUX Channel
aux_tx_wr_en => aux_tx_wr_en,
aux_tx_data => aux_tx_data
);
i_channel: aux_interface port map (
clk => clk,
debug_pmod => debug_pmod_i,
------------------------------
dp_tx_aux_p => dp_tx_aux_p,
dp_tx_aux_n => dp_tx_aux_n,
dp_rx_aux_p => dp_rx_aux_p,
dp_rx_aux_n => dp_rx_aux_n,
------------------------------
tx_wr_en => aux_tx_wr_en,
tx_data => aux_tx_data,
------------------------------
rx_rd_en => aux_rx_rd_en,
rx_data => aux_rx_data,
rx_empty => aux_rx_empty,
------------------------------
busy => channel_busy,
timeout => channel_timeout
);
aux_rx_rd_en <= (not channel_busy) and (not aux_rx_empty);
clk_proc: process(clK)
begin
if rising_edge(clk) then
-------------------------------------------
-- Are we going to change state this cycle?
-------------------------------------------
msg_de <= '0';
if next_state /= state then
-------------------------------------------------------------
-- Get ready to count how many reply bytes have been received
-------------------------------------------------------------
rx_byte_count <= (others => '0');
---------------------------------------------------
-- Controlling which FSM state to go to on success
---------------------------------------------------
case next_state is
when reset => state_on_success <= check_presence;
when check_presence => state_on_success <= edid_block0;
when edid_block0 => state_on_success <= edid_block1;
when edid_block1 => state_on_success <= edid_block2;
when edid_block2 => state_on_success <= edid_block3;
when edid_block3 => state_on_success <= edid_block4;
when edid_block4 => state_on_success <= edid_block5;
when edid_block5 => state_on_success <= edid_block6;
when edid_block6 => state_on_success <= edid_block7;
when edid_block7 => state_on_success <= read_sink_count;
when read_sink_count => state_on_success <= read_registers;
when read_registers => state_on_success <= set_channel_coding;
when set_channel_coding => state_on_success <= set_speed_270;
when set_speed_270 => state_on_success <= set_downspread;
when set_downspread => case link_count is
when "001" => state_on_success <= set_link_count_1;
when "010" => state_on_success <= set_link_count_2;
when "100" => state_on_success <= set_link_count_4;
when others => state_on_success <= error;
end case;
when set_link_count_1 => state_on_success <= clock_training;
when set_link_count_2 => state_on_success <= clock_training;
when set_link_count_4 => state_on_success <= clock_training;
------- Display Port clock training -------------------
when clock_training => state_on_success <= clock_voltage_0p4;
when clock_voltage_0p4 => state_on_success <= clock_wait;
when clock_voltage_0p6 => state_on_success <= clock_wait;
when clock_voltage_0p8 => state_on_success <= clock_wait;
when clock_wait => state_on_success <= clock_test;
when clock_test => state_on_success <= clock_adjust;
when clock_adjust => state_on_success <= clock_wait_after;
when clock_wait_after => if clock_locked = '1' then
state_on_success <= align_training;
elsif swing_0p8 = '1' then
state_on_success <= clock_voltage_0p8;
elsif swing_0p6 = '1' then
state_on_success <= clock_voltage_0p6;
else
state_on_success <= clock_voltage_0p4;
end if;
------- Display Port Alignment traning ------------
when align_training => if swing_0p8 = '1' then
state_on_success <= align_p0_V0p8;
elsif swing_0p6 = '1' then
state_on_success <= align_p0_V0p6;
else
state_on_success <= align_p0_V0p4;
end if;
when align_p0_V0p4 => state_on_success <= align_wait0;
when align_p0_V0p6 => state_on_success <= align_wait0;
when align_p0_V0p8 => state_on_success <= align_wait0;
when align_p1_V0p4 => state_on_success <= align_wait0;
when align_p1_V0p6 => state_on_success <= align_wait0;
when align_p1_V0p8 => state_on_success <= align_wait0;
when align_p2_V0p4 => state_on_success <= align_wait0;
when align_p2_V0p6 => state_on_success <= align_wait0;
when align_p2_V0p8 => state_on_success <= align_wait0;
when align_wait0 => state_on_success <= align_wait1;
when align_wait1 => state_on_success <= align_wait2;
when align_wait2 => state_on_success <= align_wait3;
when align_wait3 => state_on_success <= align_test;
when align_test => state_on_success <= align_adjust;
when align_adjust => state_on_success <= align_wait_after;
when align_wait_after => if symbol_locked = '1' then
state_on_success <= switch_to_normal;
elsif swing_0p8 = '1' then
if preemp_6p0 = '1' then
state_on_success <= align_p2_V0p8;
elsif preemp_3p5 = '1' then
state_on_success <= align_p1_V0p8;
else
state_on_success <= align_p0_V0p8;
end if;
elsif swing_0p6 = '1' then
if preemp_6p0 = '1' then
state_on_success <= align_p2_V0p6;
elsif preemp_3p5 = '1' then
state_on_success <= align_p1_V0p6;
else
state_on_success <= align_p0_V0p6;
end if;
else
if preemp_6p0 = '1' then
state_on_success <= align_p2_V0p4;
elsif preemp_3p5 = '1' then
state_on_success <= align_p1_V0p4;
else
state_on_success <= align_p0_V0p4;
end if;
end if;
when switch_to_normal => state_on_success <= link_established;
when link_established => state_on_success <= link_established;
when check_link => state_on_success <= check_wait;
when check_wait => if clock_locked = '1' and equ_locked = '1' and symbol_locked = '1' and align_locked = '1' then
state_on_success <= link_established;
else
state_on_success <= error;
end if;
when error => state_on_success <= error;
when others =>
end case;
------------------------------------------------------------
-- Controlling what message will be sent, how many words are
-- expected back, and where it will be routed
--
-- NOTE: If you set 'expected' incorrectly then bytes will
-- get left in the RX FIFO, potentially corrupting things
------------------------------------------------------------
msg_de <= '1';
status_de_active <= '0';
adjust_de_active <= '0';
dp_reg_de_active <= '0';
edid_de_active <= '0';
reset_addr_on_change <= '0';
case next_state is
when reset => msg <= x"00"; expected <= x"00";
when check_presence => msg <= x"01"; expected <= x"01"; reset_addr_on_change <= '1';
when edid_block0 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when edid_block1 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when edid_block2 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when edid_block3 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when edid_block4 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when edid_block5 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when edid_block6 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when edid_block7 => msg <= x"02"; expected <= x"11"; edid_de_active <= '1';
when read_sink_count => msg <= x"03"; expected <= x"02"; reset_addr_on_change <= '1';
when read_registers => msg <= x"04"; expected <= x"0D"; dp_reg_de_active <= '1';
when set_channel_coding => msg <= x"06"; expected <= x"01";
when set_speed_270 => msg <= x"07"; expected <= x"01";
when set_downspread => msg <= x"08"; expected <= x"01";
when set_link_count_1 => msg <= x"09"; expected <= x"01";
when set_link_count_2 => msg <= x"0A"; expected <= x"01";
when set_link_count_4 => msg <= x"0B"; expected <= x"01";
when clock_training => msg <= x"0C"; expected <= x"01";
when clock_voltage_0p4 => msg <= x"14"; expected <= x"01";
when clock_voltage_0p6 => msg <= x"16"; expected <= x"01";
when clock_voltage_0p8 => msg <= x"18"; expected <= x"01";
when clock_wait => msg <= x"00"; expected <= x"00"; reset_addr_on_change <= '1';
when clock_test => msg <= x"0D"; expected <= x"09"; status_de_active <= '1'; reset_addr_on_change <= '1';
when clock_adjust => msg <= x"0E"; expected <= x"03"; adjust_de_active <= '1';
when clock_wait_after => msg <= x"00"; expected <= x"00";
when align_training => msg <= x"0F"; expected <= x"01";
when align_p0_V0p4 => msg <= x"14"; expected <= x"01";
when align_p0_V0p6 => msg <= x"16"; expected <= x"01";
when align_p0_V0p8 => msg <= x"18"; expected <= x"01";
when align_p1_V0p4 => msg <= x"24"; expected <= x"01";
when align_p1_V0p6 => msg <= x"26"; expected <= x"01";
when align_p1_V0p8 => msg <= x"28"; expected <= x"01";
when align_p2_V0p4 => msg <= x"34"; expected <= x"01";
when align_p2_V0p6 => msg <= x"36"; expected <= x"01";
when align_p2_V0p8 => msg <= x"38"; expected <= x"01";
when align_wait0 => msg <= x"00"; expected <= x"00";
when align_wait1 => msg <= x"00"; expected <= x"00";
when align_wait2 => msg <= x"00"; expected <= x"00";
when align_wait3 => msg <= x"00"; expected <= x"00"; reset_addr_on_change <= '1';
when align_test => msg <= x"0D"; expected <= x"09"; status_de_active <= '1'; reset_addr_on_change <= '1';
when align_adjust => msg <= x"0E"; expected <= x"03"; adjust_de_active <= '1';
when align_wait_after => msg <= x"00"; expected <= x"00";
when switch_to_normal => msg <= x"11"; expected <= x"01";
when link_established => msg <= x"00"; expected <= x"00"; reset_addr_on_change <= '1';
when check_link => msg <= x"0D"; expected <= x"09"; status_de_active <= '1';
when check_wait => msg <= x"00"; expected <= x"00";
when error => msg <= x"00";
when others => msg <= x"00";
end case;
--------------------------------------------------------
-- Set the control signals the state for the link state,
-- transceivers andmain channel pipeline
--------------------------------------------------------
tx_powerup <= '0';
tx_clock_train <= '0';
tx_align_train <= '0';
tx_link_established <= '0';
case next_state is
when clock_training => tx_powerup <= '1'; tx_clock_train <= '1';
when clock_voltage_0p4 => tx_powerup <= '1'; tx_clock_train <= '1';
when clock_voltage_0p6 => tx_powerup <= '1'; tx_clock_train <= '1';
when clock_voltage_0p8 => tx_powerup <= '1'; tx_clock_train <= '1';
when clock_wait => tx_powerup <= '1'; tx_clock_train <= '1';
when clock_test => tx_powerup <= '1'; tx_clock_train <= '1';
when clock_adjust => tx_powerup <= '1'; tx_clock_train <= '1';
when clock_wait_after => tx_powerup <= '1'; tx_clock_train <= '1';
when align_training => tx_powerup <= '1'; tx_align_train <= '1';
when align_p0_V0p4 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p0_V0p6 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p0_V0p8 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p1_V0p4 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p1_V0p6 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p1_V0p8 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p2_V0p4 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p2_V0p6 => tx_powerup <= '1'; tx_align_train <= '1';
when align_p2_V0p8 => tx_powerup <= '1'; tx_align_train <= '1';
when align_wait0 => tx_powerup <= '1'; tx_align_train <= '1';
when align_wait1 => tx_powerup <= '1'; tx_align_train <= '1';
when align_wait2 => tx_powerup <= '1'; tx_align_train <= '1';
when align_wait3 => tx_powerup <= '1'; tx_align_train <= '1';
when align_test => tx_powerup <= '1'; tx_align_train <= '1';
when align_adjust => tx_powerup <= '1'; tx_align_train <= '1';
when align_wait_after => tx_powerup <= '1'; tx_align_train <= '1';
when switch_to_normal => tx_powerup <= '1';
when link_established => tx_powerup <= '1'; tx_link_established <= '1';
when check_link => tx_powerup <= '1'; tx_link_established <= '1';
when check_wait => tx_powerup <= '1'; tx_link_established <= '1';
when others => NULL;
end case;
end if;
--------------------------------------------------------
-- Manage the small timer that counts how long we have
-- been in the current state (used for implementing
-- short waits for some FSM states)
--------------------------------------------------------
if state = next_state then
count_100us <= count_100us - 1;
else
count_100us <= to_unsigned(9999,15);
if reset_addr_on_change = '1' then
aux_addr_i <= (others => '0');
end if;
end if;
state <= next_state;
-------------------------------------------------------------
-- How a short wait is implemented...
--
-- Has the 100us pause expired, when no data was expected?
-- If so, move to the next test.
-------------------------------------------------------------
if expected = x"00" and count_100us(count_100us'high) = '1' then
next_state <= state_on_success;
end if;
--------------------------------------------------------------
-- Processing the data that has been received from the sink
-- over the AUX channel. The data bytes are just streamed out
-- to a downstream component that uses the values, and may
-- set flags that feed back in to control the FSM.
--------------------------------------------------------------
edid_de <= '0';
adjust_de <= '0';
dp_reg_de <= '0';
status_de <= '0';
if channel_busy = '0' then
if just_read_from_rx = '1' then
-- Is this a short read?
if rx_byte_count /= expected-1 and aux_rx_empty = '1' then
next_state <= error;
end if;
if rx_byte_count = x"00" then
--------------------------------------------------
-- Is the Ack missing? This doesn't work correctly
-- if only byte is expected, as it gets overwritten
-- by the following 'if' statement.
--
-- Do not change this behaviour, by what it should do
-- is test for "In progress" or "Again" requests, and
-- retry the current operation.
------------------------------------------------------
if aux_rx_data /= x"00" then
next_state <= error;
end if;
if rx_byte_count = expected-1 and aux_rx_empty = '1' then
next_state <= state_on_success;
end if;
----------------------------------------------
-- Has the Sink indicated that we should retry
-- the current command, to allow the sink time
-- to process the request?
--
-- This only works if there is just one byte
-- in the FIFO. This only works for DPCD
-- transactions that aeert "AUX DEFER"
----------------------------------------------
if aux_rx_data = x"20" then
-- just flip states to force a retry.
state <= state_on_success;
next_state <= state;
end if;
else
-------------------------------------------------------------------
-- Process a non-ack data byte, routing it out using the DE signals
-------------------------------------------------------------------
edid_de <= edid_de_active;
adjust_de <= adjust_de_active;
dp_reg_de <= dp_reg_de_active;
status_de <= status_de_active;
aux_data <= aux_rx_data;
aux_addr <= std_logic_vector(aux_addr_i);
aux_addr_i <= aux_addr_i+1;
if rx_byte_count = expected-1 and aux_rx_empty = '1' then
next_state <= state_on_success;
if reset_addr_on_change = '1' then
aux_addr_i <= (others => '0');
end if;
end if;
end if;
end if;
end if;
-----------------------------------------------------
-- Manage the AUX channel timeout and the retry to
-- establish a link.
-------------------------------------------------------------
-- if channel_timeout = '1' or (state /= reset and state /= link_established and retry_now = '1') then
if channel_timeout = '1' or (state /= reset and state /= link_established and
state /= check_link and state /= check_wait and retry_now = '1') then
next_state <= reset;
state <= error;
end if;
-------------------------------------------------
-- If the link was established, then every
-- now and then check the state of the link
-------------------------------------------------
if state = link_established and link_check_now = '1' then
next_state <= check_link;
end if;
-------------------------------------------------
-- If the full message has been received, then
-- read any waiting data out of the FIFO.
-- Also update the count of bytes read.
-------------------------------------------------
if channel_busy = '0' and aux_rx_empty = '0' then
just_read_from_rx <= '1';
else
just_read_from_rx <= '0';
end if;
if just_read_from_rx = '1' then
rx_byte_count <= rx_byte_count+1;
end if;
-----------------------------------------
-- Manage the reset timer
-----------------------------------------
if retry_count = 0 then
retry_now <= '1';
retry_count <= to_unsigned(49999999,27);
else
retry_now <= '0';
retry_count <= retry_count - 1;
end if;
if link_check_count = 0 then
-- link_check_now <= '1';
-- PPS actually became a 2Hz pulse....
link_check_count <= to_unsigned(99999999,27);
else
link_check_now <= '0';
link_check_count <= link_check_count - 1;
end if;
end if;
end process;
end architecture; | mit | f967056d56a77dbf905ab7ee8d4319bc | 0.393493 | 4.618685 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/test_source_3840_2160_YCC_422_ch2.vhd | 1 | 16,160 | ----------------------------------------------------------------------------------
-- Module Name: test_source_3840_2160_YCC_422_ch2 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case a 3840x2160 @ 30p grey screen.
-- Timings:
-- YCC 422, 8 bits per component
-- H Vis 3840 V Vis 2160
-- H Front 48 V Front 3
-- H Sync 32 V Sync 5
-- H Back 112 V Back 23
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test_source_3840_2160_YCC_422_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end test_source_3840_2160_YCC_422_ch2;
architecture arch of test_source_3840_2160_YCC_422_ch2 is
type a_test_data_blocks is array (0 to 64*18-1) of std_logic_vector(8 downto 0);
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0xAA
constant ZERO : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
signal PIX_Y0 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
signal PIX_Y1 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
signal PIX_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
signal PIX_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant FS : std_logic_vector(8 downto 0) := "111111110"; -- K30.7
constant FE : std_logic_vector(8 downto 0) := "111110111"; -- K23.7
constant VB_VS : std_logic_vector(8 downto 0) := "000000001"; -- 0x00 VB-ID with Vertical blank asserted
constant VB_NVS : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 VB-ID without Vertical blank asserted
constant Mvid : std_logic_vector(8 downto 0) := "001101000"; -- 0x68
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
signal col_count : unsigned(11 downto 0) := (others => '0');
constant max_col_count : unsigned(11 downto 0) := to_unsigned(2053,12); -- (3840+32+48+112)*270/265-1
signal line_count : unsigned(11 downto 0) := (others => '0');
constant max_line_count : unsigned(11 downto 0) := to_unsigned(2190,12); -- 2160+5+3+23 -1
constant max_active_line : unsigned(11 downto 0) := to_unsigned(2159,12); -- 2160 -1
signal block_count : unsigned(5 downto 0) := (others => '0');
signal switch_point : std_logic := '0';
signal active_line : std_logic := '1';
signal phase : std_logic := '0';
begin
------------------------------------------------------------------
-- The M number here is almost magic. Here's how to calculate it.
--
-- The pixel clock is 265MHz, or 53/54 of the DisplayPort's 270MHz
-- symbol rate. As I am using YCC 422 53 pixels are being sent
-- every 54 cycles, allowing a constant TU size of 54 symbols with
-- one FE symbol for padding.
--
-- So you should expect M to be 53/54 * 0x80000 = 0x07DA12.
--
-- And you will be wrong. Bash your head against the wall for a
-- week wrong.
--
-- Here's the right way. A line is sent every 2054 cycles of the
-- 135 MHz clock, or 4108 link symbols. Each line is 4032 pixel
-- clocks (at 265 MHz). So the M value should be 4032/4108*0x80000
-- = 514588.4 = 0x07DA1C.
--
-- That small difference is enough to make things not work.
--
-- So why the difference? It's because line length (4032) doesn't
-- divide evenly by 53. To get this bang-on you would need to add
-- an extra 13 symbols every 52 lines, and as it needs to transmit
-- two symbols per cycle this would be awkward.
--
-- However the second way gives actual pixel clock is 4032/4108*270
-- 265.004,868 MHz.
--
--
-- The upside of this scheme is that an accurate Mvid[7:0] value
-- followingthe BS and VB_ID be constant for all raster lines. So
-- you can use any legal value you like.
--
-- The downside is that you have to drive your pixel generator from
-- the transceiver's reference clock.
--------------------------------------------------------------------
M_value <= x"07DA1C"; -- For 265MHz/270Mhz
N_value <= x"080000";
H_visible <= x"F00"; -- 3840
H_total <= x"FC0"; -- 4032
H_sync_width <= x"030"; -- 128
H_start <= x"0A0"; -- 160
V_visible <= x"870"; -- 2160
V_total <= x"88F"; -- 2191
V_sync_width <= x"003"; -- 3
V_start <= x"01A"; -- 26
H_vsync_active_high <= '1';
V_vsync_active_high <= '1';
flag_sync_clock <= '1';
flag_YCCnRGB <= '1';
flag_422n444 <= '1';
flag_range_reduced <= '1';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "010";
ready <= '1';
data(72) <= switch_point;
data(71 downto 36) <= (others => '0');
process(clk)
begin
if rising_edge(clk) then
switch_point <= '0';
block_count <= block_count+1;
if col_count = 1957 then
-- flick to white (R+G+B)
PIX_Y0 <= std_logic_vector(to_unsigned(174, 9));
PIX_Y1 <= std_logic_vector(to_unsigned(174, 9));
PIX_Cb <= std_logic_vector(to_unsigned(128, 9));
PIX_Cr <= std_logic_vector(to_unsigned(128, 9));
elsif col_count = 279 then
-- Should be yellow (G+R)
PIX_Y0 <= std_logic_vector(to_unsigned(156, 9));
PIX_Y1 <= std_logic_vector(to_unsigned(156, 9));
PIX_Cb <= std_logic_vector(to_unsigned( 47, 9));
PIX_Cr <= std_logic_vector(to_unsigned(141, 9));
elsif col_count = 559 then
-- Should be Cyan (G+B)
PIX_Y0 <= std_logic_vector(to_unsigned(127, 9));
PIX_Y1 <= std_logic_vector(to_unsigned(127, 9));
PIX_Cb <= std_logic_vector(to_unsigned(155, 9));
PIX_Cr <= std_logic_vector(to_unsigned( 47, 9));
elsif col_count = 839 then
-- Should be Green (G)
PIX_Y0 <= std_logic_vector(to_unsigned(109, 9));
PIX_Y1 <= std_logic_vector(to_unsigned(109, 9));
PIX_Cb <= std_logic_vector(to_unsigned( 74, 9));
PIX_Cr <= std_logic_vector(to_unsigned( 60, 9));
elsif col_count = 1118 then
-- Should be Magenta (R+B)
PIX_Y0 <= std_logic_vector(to_unsigned( 81, 9));
PIX_Y1 <= std_logic_vector(to_unsigned( 81, 9));
PIX_Cb <= std_logic_vector(to_unsigned(182, 9));
PIX_Cr <= std_logic_vector(to_unsigned(196, 9));
elsif col_count = 1398 then
-- Should be Red (R)
PIX_Y0 <= std_logic_vector(to_unsigned( 63, 9));
PIX_Y1 <= std_logic_vector(to_unsigned( 63, 9));
PIX_Cb <= std_logic_vector(to_unsigned(101, 9));
PIX_Cr <= std_logic_vector(to_unsigned(209, 9));
elsif col_count = 1678 then
-- Should be Blue (B)
PIX_Y0 <= std_logic_vector(to_unsigned( 34, 9));
PIX_Y1 <= std_logic_vector(to_unsigned( 34, 9));
PIX_Cb <= std_logic_vector(to_unsigned(209, 9));
PIX_Cr <= std_logic_vector(to_unsigned(115, 9));
end if;
if col_count = 0 then
if active_line = '1' then
data(35 downto 0) <= BE & DUMMY & BE & DUMMY;
else
data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
end if;
phase <= '0';
block_count <= (others => '0');
-- we do this here to get the VB_ID field correct
elsif col_count < 1957 then
------------------------------------
-- Pixel data goes here
------------------------------------
if active_line = '1' then
if block_count = 26 then
if phase = '0' then
data(35 downto 0) <= FE & PIX_Cr & FE & PIX_Cb;
else
data(35 downto 0) <= FE & PIX_Y1 & FE & PIX_Y0;
end if;
block_count <= (others => '0');
phase <= not phase;
else
if phase = '0' then
data(35 downto 0) <= PIX_Y1 & PIX_Cr & PIX_Y0 & PIX_Cb;
else
data(35 downto 0) <= PIX_Cr & PIX_Y1 & PIX_Cb & PIX_Y0;
end if;
block_count <= block_count + 1;
end if;
else
data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
switch_point <= '1';
end if;
elsif col_count = 1957 then
if active_line = '1' then
data(35 downto 0) <= VB_NVS & BS & VB_NVS & BS;
else
data(35 downto 0) <= VB_VS & BS & VB_VS & BS;
end if;
elsif col_count = 1958 then
data(35 downto 0) <= Maud & Mvid & Maud & Mvid;
elsif col_count = 1959 then
if active_line = '1' then
data(35 downto 0) <= Mvid & VB_NVS & Mvid & VB_NVS;
else
data(35 downto 0) <= Mvid & VB_VS & Mvid & VB_VS;
end if;
elsif col_count = 1960 then data(35 downto 0) <= DUMMY & Maud & DUMMY & Maud;
else data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
end if;
----------------------------------
-- When to update the active_line,
-- use to set VB-ID field after
-- te BS symbols and control
-- emitting pixels
----------------------------------
if col_count = 1956 then
if line_count = max_active_line then
active_line <= '0';
end if;
end if;
if col_count = max_col_count then
if line_count = max_line_count then
active_line <= '1';
end if;
end if;
----------------------------------
-- Update the counters
----------------------------------
if col_count = max_col_count then
col_count <= (others => '0');
if line_count = max_line_count then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
col_count <= col_count + 1;
end if;
end if;
end process;
end architecture; | mit | 9a46ae8d7649c400afb1e053faa41933 | 0.476423 | 4.025909 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/unitFirFilter/hdl/FirFilter_tb.vhd | 1 | 4,954 | -------------------------------------------------------------------------------
-- Title : Testbench for design "FirFilter"
-------------------------------------------------------------------------------
-- File : FirFilter_tb.vhd
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use work.Global.all;
use work.sin_4096.all;
-------------------------------------------------------------------------------
entity FirFilter_tb is
end entity FirFilter_tb;
-------------------------------------------------------------------------------
architecture Bhv of FirFilter_tb is
constant strobe_time : time := 200 ns;
signal sample_strobe : std_ulogic := '0';
-- filter coeffs
constant fir_coeffs_c : fract_set_t := (0.5, 0.0, 0.0, 0.0);
-- component generics
constant data_width_g : natural := data_width_c;
constant coeff_num_g : natural := fir_coeffs_c'length;
constant coeff_addr_width_g : natural := 4;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal avs_s0_write : std_logic := '0';
signal avs_s0_address : std_logic_vector(coeff_addr_width_g-1 downto 0) := (others => '0');
signal avs_s0_writedata : std_logic_vector(31 downto 0) := (others => '0');
signal avs_s1_write : std_logic;
signal avs_s1_writedata : std_logic_vector(31 downto 0);
signal asi_valid : std_logic;
signal asi_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_valid : std_logic;
signal aso_data : std_logic_vector(data_width_g-1 downto 0);
-- audio data
signal data_in : audio_data_t;
signal data_out : audio_data_t;
begin -- architecture Bhv
data_out <= to_sfixed(aso_data, data_out);
-- component instantiation
DUT : entity work.FirFilter
generic map (
data_width_g => data_width_g,
coeff_num_g => coeff_num_g,
coeff_addr_width_g => coeff_addr_width_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
avs_s0_write => avs_s0_write,
avs_s0_address => avs_s0_address,
avs_s0_writedata => avs_s0_writedata,
avs_s1_write => avs_s1_write,
avs_s1_writedata => avs_s1_writedata,
asi_valid => asi_valid,
asi_data => asi_data,
aso_valid => aso_valid,
aso_data => aso_data);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
-- sample strobe generation
--strobe : process is
--begin -- process
-- wait for strobe_time;
-- wait until rising_edge(csi_clk);
-- sample_strobe <= '1';
-- wait until rising_edge(csi_clk);
-- sample_strobe <= '0';
--end process;
SinGen_1: entity work.SinGen
generic map (
periode_g => 100 us,
sample_time_g => strobe_time)
port map (
clk_i => csi_clk,
data_o => data_in,
data_valid_o => sample_strobe);
-- sinus as audio data
--aud_data : process is
--begin -- process
-- for idx in 0 to sin_table_c'length-1 loop
-- wait until rising_edge(sample_strobe);
-- data_in <= to_sfixed(sin_table_c(idx), 0, -(data_width_g-1));
-- end loop; -- idx
--end process aud_data;
asi_data <= to_slv(data_in);
asi_valid <= sample_strobe;
-- write coeffs
avs_s0 : process is
begin -- process avs_s0
for idx in 0 to coeff_num_g-1 loop
wait until rising_edge(csi_clk);
avs_s0_address <= std_logic_vector(to_unsigned(idx, avs_s0_address'length));
avs_s0_write <= '1';
avs_s0_writedata(data_width_g-1 downto 0) <= to_slv(to_sfixed(fir_coeffs_c(idx), 0, -(data_width_g-1)));
end loop; -- idx
end process avs_s0;
-- waveform generation
WaveGen_Proc : process
begin
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
avs_s1_write <= '0';
avs_s1_writedata <= (others => '-');
-- pass in to out
avs_s1_write <= '1';
avs_s1_writedata(0) <= '0';
wait until rising_edge(csi_clk);
avs_s1_write <= '0';
avs_s1_writedata(0) <= '-';
wait for 500000 ns;
-- enable filter
avs_s1_write <= '1';
avs_s1_writedata(0) <= '1';
wait until rising_edge(csi_clk);
avs_s1_write <= '0';
avs_s1_writedata(0) <= '-';
wait;
end process WaveGen_Proc;
end architecture Bhv;
-------------------------------------------------------------------------------
| gpl-3.0 | 51ec0db53aed46becd41fa3582c122a3 | 0.502826 | 3.518466 | false | false | false | false |
kenkendk/sme | src/SME.VHDL/Templates/csv_util.vhdl | 1 | 7,768 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;
use std.textio.all;
use IEEE.NUMERIC_STD.ALL;
-- Package for reading csv files
package csv_util is
-- Max length of a line in the csv file
constant CSV_LINE_LENGTH_MAX: integer := 256;
-- Type of a csv line
subtype CSV_LINE_T is string(1 to CSV_LINE_LENGTH_MAX);
-- Read until EOL or comma
procedure read_csv_field(ln: inout LINE; ret: out string);
-- Compare variable length strings
function are_strings_equal (ln1: string; ln2: string) return boolean;
-- Debug print text
procedure print(text: string);
-- converts string to STD_LOGIC
function to_std_logic(b: string) return std_logic;
-- converts string STD_LOGIC_VECTOR to string
function to_std_logic_vector(b: string) return std_logic_vector;
-- converts STD_LOGIC into a string
function str(b: std_logic) return string;
-- converts STD_LOGIC_VECTOR into a string
function str(b: std_logic_vector) return string;
-- converts UNSIGNED into a string
function str(b: unsigned) return string;
-- converts SIGNED into a string
function str(b: signed) return string;
-- Returns the first occurrence of a a given character
function index_of_chr(ln: string; c: character) return integer;
-- Returns the first occurrence of a null character
function index_of_null(ln: string) return integer;
-- Returns a substring, from start to finish
function substr(ln: string; start: integer; finish: integer) return string;
-- Trucates strings with embedded null characters
function truncate(ln: string) return string;
-- Converts the input strings unwanted characters to underscore
function to_safe_name(ln: string) return string;
end csv_util;
package body csv_util is
-- prints the given text
procedure print(text: string) is
variable msg: line;
begin
write(msg, text);
writeline(output, msg);
end print;
-- reads a line of the csv file
procedure read_csv_field(ln: inout LINE; ret: out string) is
variable return_string: CSV_LINE_T;
variable read_char: character;
variable read_ok: boolean := true;
variable index: integer := 1;
begin
read(ln, read_char, read_ok);
while read_ok loop
if read_char = ',' then
ret := return_string;
return;
else
return_string(index) := read_char;
index := index + 1;
end if;
read(ln, read_char, read_ok);
end loop;
ret := return_string;
end;
-- returns the index of the given character
function index_of_chr(ln: string; c: character) return integer is
begin
for i in 1 to ln'length loop
if ln(i) = c then
return i;
end if;
end loop;
return ln'length + 1;
end;
-- returns the index of a null character
function index_of_null(ln: string) return integer is
begin
return index_of_chr(ln, NUL);
end;
-- returns a substring of the given string between start and finish
function substr(ln: string; start: integer; finish: integer) return string is
begin
return ln(start to finish);
end;
-- truncates the given string
function truncate(ln: string) return string is
begin
return substr(ln, 1, index_of_null(ln) - 1);
end;
-- converts the given line to a VHDL safe string
function to_safe_name(ln: string) return string is
variable res : string(1 to ln'length) := ln;
begin
for i in 1 to ln'length loop
if ln(i) = '.' or ln(i) = ',' then
res(i) := '_';
end if;
end loop;
return res;
end;
-- returns true if the given strings are equal
function are_strings_equal(ln1: string; ln2: string) return boolean is
variable lhs : string(1 to ln1'length) := ln1;
variable rhs : string(1 to ln2'length) := ln2;
variable maxlen : integer := ln1'length;
begin
if lhs'length = rhs'length and lhs'length = 0 then
return true;
else
if ln2'length < maxlen then
maxlen := ln2'length;
end if;
for i in 1 to maxlen loop
if lhs(i) /= rhs(i) then
return false;
end if;
end loop;
if lhs'length > maxlen then
if not (lhs(maxlen + 1) = NUL or lhs(maxlen + 1) = CR) then
return false;
end if;
end if;
if rhs'length > maxlen then
if not (rhs(maxlen + 1) = NUL or rhs(maxlen + 1) = CR) then
return false;
end if;
end if;
return true;
end if;
end;
-- converts string STD_LOGIC_VECTOR to string
function to_std_logic_vector(b: string) return std_logic_vector is
variable res : std_logic_vector(1 to b'length);
variable v : string(1 to b'length) := b;
begin
if v(1) /= '1' and v(1) /= '0' then
res(1) := std_logic'value(v);
else
for i in 1 to b'length loop
if v(i) = '0' then
res(i) := '0';
elsif v(i) = '1' then
res(i) := '1';
else
res(i) := '-';
end if;
end loop;
end if;
return res;
end to_std_logic_vector;
-- converts string to STD_LOGIC
function to_std_logic(b: string) return std_logic is
variable s: std_logic;
begin
case b(1) is
when 'U' => s := 'U';
when 'X' => s := 'X';
when '0' => s := '0';
when '1' => s := '1';
when 'Z' => s := 'Z';
when 'W' => s := 'W';
when 'L' => s := 'L';
when 'H' => s := 'H';
when '-' => s := '-';
when others => s := '-';
end case;
return s;
end to_std_logic;
-- converts STD_LOGIC into a string
function str(b: std_logic) return string is
variable s: string(1 to 1);
begin
case b is
when 'U' => s(1) := 'U';
when 'X' => s(1) := 'X';
when '0' => s(1) := '0';
when '1' => s(1) := '1';
when 'Z' => s(1) := 'Z';
when 'W' => s(1) := 'W';
when 'L' => s(1) := 'L';
when 'H' => s(1) := 'H';
when '-' => s(1) := '-';
when others => s(1) := '-';
end case;
return s;
end str;
-- converts STD_LOGIC_VECTOR into a string
function str(b: std_logic_vector) return string is
variable res : string(1 to b'length);
variable v : std_logic_vector(1 to b'length) := b;
begin
if v(1) /= '1' and v(1) /= '0' then
return std_logic'image(v(1));
else
for i in 1 to b'length loop
if v(i) = '0' then
res(i) := '0';
elsif v(i) = '1' then
res(i) := '1';
else
res(i) := '-';
end if;
end loop;
return res;
end if;
end str;
-- converts UNSIGNED into a string
function str(b: unsigned) return string is
begin
return str(std_logic_vector(b));
end str;
-- converts SIGNED into a string
function str(b: signed) return string is
begin
return str(std_logic_vector(b));
end str;
end package body csv_util; | mit | 341e44d33e14b28a21ad0ad33b2380fb | 0.52717 | 3.86176 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpDsp/unitAddChannels/hdl/AddChannels_tb.vhd | 1 | 4,631 | -------------------------------------------------------------------------------
-- Title : Add Channels Testbench
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Scale Channels with an factor and add
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_float_types.all;
use ieee.fixed_pkg.all;
use work.Global.all;
use work.sin_4096.all;
-------------------------------------------------------------------------------
entity AddChannels_tb is
end entity AddChannels_tb;
-------------------------------------------------------------------------------
architecture Bhv of AddChannels_tb is
--constant strobe_time : time := 1 sec/real(44117);
constant strobe_time : time := 200 ns;
-- component generics
constant data_width_g : natural := 24;
constant fact_a_g : real := 0.5;
constant fact_b_g : real := 0.5;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic := '0';
signal avs_s0_write : std_logic := '0';
signal avs_s0_writedata : std_logic_vector(31 downto 0) := (others => '0');
signal asi_a_data : std_logic_vector(data_width_g-1 downto 0);
signal asi_a_valid : std_logic;
signal asi_b_data : std_logic_vector(data_width_g-1 downto 0);
signal asi_b_valid : std_logic;
signal aso_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_valid : std_logic;
signal result : sfixed(0 downto -(data_width_g-1));
-- audio data
signal sample_strobe : std_ulogic := '0';
signal audio_data : sfixed(0 downto -(data_width_g-1)) := (others => '0');
begin -- architecture Bhv
result <= to_sfixed(aso_data, result);
-- component instantiation
DUT : entity work.AddChannels
generic map (
data_width_g => data_width_g,
fact_a_g => fact_a_g,
fact_b_g => fact_b_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
avs_s0_write => avs_s0_write,
avs_s0_writedata => avs_s0_writedata,
asi_a_data => asi_a_data,
asi_a_valid => asi_a_valid,
asi_b_data => asi_b_data,
asi_b_valid => asi_b_valid,
aso_data => aso_data,
aso_valid => aso_valid);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
-- sample strobe generation
strobe : process is
begin -- process
wait for strobe_time;
wait until rising_edge(csi_clk);
sample_strobe <= '1';
wait until rising_edge(csi_clk);
sample_strobe <= '0';
end process;
-- sinus as audio data
aud_data : process is
begin -- process
for idx in 0 to sin_table_c'length-1 loop
wait until rising_edge(sample_strobe);
audio_data <= to_sfixed(sin_table_c(idx), 0, -(data_width_g-1));
end loop; -- idx
end process aud_data;
-- channel a and b with sinus
asi_a_data <= to_slv(to_sfixed(real(0.5), 0, -(data_width_g-1)));
asi_b_data <= to_slv(audio_data);
--asi_b_data <= (others => '0');
asi_a_valid <= sample_strobe;
asi_b_valid <= sample_strobe;
-- waveform generation
WaveGen_Proc : process
begin
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
avs_s0_write <= '0';
avs_s0_writedata <= (others => '-');
-- pass a
avs_s0_write <= '1';
avs_s0_writedata(1 downto 0) <= "00";
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(1 downto 0) <= "--";
wait for 500000 ns;
-- pass b
avs_s0_write <= '1';
avs_s0_writedata(1 downto 0) <= "01";
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(1 downto 0) <= "--";
wait for 500000 ns;
-- sum a + b
avs_s0_write <= '1';
avs_s0_writedata(1 downto 0) <= "10";
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(1 downto 0) <= "--";
wait for 500000 ns;
-- mute
avs_s0_write <= '1';
avs_s0_writedata(1 downto 0) <= "11";
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(1 downto 0) <= "--";
wait;
end process WaveGen_Proc;
end architecture Bhv;
-------------------------------------------------------------------------------
| gpl-3.0 | 5df355653fc9a40fd18c8e8d91606a55 | 0.498812 | 3.513657 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/ipcore_dir/dualBRAM/simulation/dualBRAM_tb.vhd | 1 | 4,517 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: dualBRAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY dualBRAM_tb IS
END ENTITY;
ARCHITECTURE dualBRAM_tb_ARCH OF dualBRAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
dualBRAM_synth_inst:ENTITY work.dualBRAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 3d89a9c8f55d00045496d5b890c66790 | 0.61656 | 4.609184 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/main_stream_processing.vhd | 1 | 8,083 | ----------------------------------------------------------------------------------
-- Module Name: main_stream_processing - Behavioral
--
-- Description: Top level of my DisplayPort design.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-15 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity main_stream_processing is
generic( use_hw_8b10b_support : std_logic := '0');
Port ( symbol_clk : in STD_LOGIC;
tx_link_established : in STD_LOGIC;
source_ready : in STD_LOGIC;
tx_clock_train : in STD_LOGIC;
tx_align_train : in STD_LOGIC;
in_data : in STD_LOGIC_VECTOR (72 downto 0);
tx_symbols : out STD_LOGIC_VECTOR (79 downto 0));
end main_stream_processing;
architecture Behavioral of main_stream_processing is
component idle_pattern_inserter is
port (
clk : in std_logic;
channel_ready : in std_logic;
source_ready : in std_logic;
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler_reset_inserter is
port (
clk : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler is
port (
clk : in std_logic;
bypass0 : in std_logic;
bypass1 : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0)
);
end component;
component scrambler_all_channels is
port (
clk : in std_logic;
bypass0 : in std_logic;
bypass1 : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component insert_training_pattern is
port (
clk : in std_logic;
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(79 downto 0)
);
end component;
component skew_channels is
port (
clk : in std_logic;
in_data : in std_logic_vector(79 downto 0);
out_data : out std_logic_vector(79 downto 0)
);
end component;
component data_to_8b10b is
port (
clk : in std_logic;
in_data : in std_logic_vector(19 downto 0);
out_data : out std_logic_vector(19 downto 0)
);
end component;
signal signal_data : std_logic_vector(71 downto 0) := (others => '0');
signal sr_inserted_data : std_logic_vector(71 downto 0) := (others => '0');
signal scrambled_data : std_logic_vector(71 downto 0) := (others => '0');
signal before_skew : std_logic_vector(79 downto 0) := (others => '0');
signal final_data : std_logic_vector(79 downto 0) := (others => '0');
constant delay_index : std_logic_vector(7 downto 0) := "11100100"; -- 3,2,1,0 for use as a lookup table in the generate loop
begin
i_idle_pattern_inserter: idle_pattern_inserter port map (
clk => symbol_clk,
channel_ready => tx_link_established,
source_ready => source_ready,
in_data => in_data,
out_data => signal_data
);
i_scrambler_reset_inserter: scrambler_reset_inserter
port map (
clk => symbol_clk,
in_data => signal_data,
out_data => sr_inserted_data
);
i_scrambler: scrambler_all_channels
port map (
clk => symbol_clk,
bypass0 => '0',
bypass1 => '0',
in_data => sr_inserted_data,
out_data => scrambled_data
);
i_insert_training_pattern: insert_training_pattern port map (
clk => symbol_clk,
clock_train => tx_clock_train,
align_train => tx_align_train,
-- Adds one bit per symbol - the force_neg parity flag
in_data => scrambled_data,
out_data => before_skew
);
i_skew_channels: skew_channels port map (
clk => symbol_clk,
in_data => before_skew,
out_data => final_data
);
g_per_channel: for i in 0 to 3 generate -- lnk_j8_lane_p'high
----------------------------------------------
-- Soft 8b/10b encoder
----------------------------------------------
g2: if use_hw_8b10b_support = '0' generate
i_data_to_8b10b: data_to_8b10b port map (
clk => symbol_clk,
in_data => final_data(19+i*20 downto 0+i*20),
out_data => tx_symbols(19+i*20 downto 0+i*20));
end generate;
g3: if use_hw_8b10b_support = '1' generate
tx_symbols <= final_data;
end generate;
end generate; --- For FOR GENERATE loop
end Behavioral;
| mit | 79bc31d7fa20be869ec00b7a166c6bd2 | 0.501794 | 4.138761 | false | false | false | false |
plessl/zippy | vhdl/auxPkg.vhd | 1 | 4,069 | ------------------------------------------------------------------------------
-- Auxiliary routines
--
-- Project :
-- File : auxPkg.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-16
-- Last changed: $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
-- This packages provides a number of auxiliary routines, in particular for
-- printing and converting characters and numbers.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-06 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.txt_util.all;
package AuxPkg is
-- computes base-2 logarithm of an integer
function log2b (int : integer) return integer;
function log2 (int : integer) return integer;
end AuxPkg;
package body auxPkg is
---------------------------------------------------------------------------
-- computes base-2 logarithm of an integer (inverse function of **)
-- rounds up, i.e. log2(8)=3, log2(9)=log2(16)=4
-- this function is not intended to synthesize directly into hardware,
-- rather it is used to generate constants for synthesized hardware.
-- (adapted from Ray Andraka's posting in comp.arch.fpga; has a different
-- behaviour!)
---------------------------------------------------------------------------
function log2b (int : integer) return integer is
variable temp : integer := int-1;
variable log : integer := 0;
begin -- log2b
assert int /= 0
report "ERROR: function missuse: log2(zero)"
severity failure;
while temp /= 0 loop
temp := temp/2;
log := log+1;
end loop;
return log;
end log2b;
-- simple version (synthesizable); doesn't cover full range!
function log2 (int : integer) return integer is
variable log : integer := 0;
begin -- log2
assert int /= 0
report "ERROR: function missuse: log2(zero)"
severity failure;
case int is
when 1 => log := 1; -- reasonable. ..?
when 2 => log := 1;
when 3 => log := 2;
when 4 => log := 2;
when 5 => log := 3;
when 6 => log := 3;
when 7 => log := 3;
when 8 => log := 3;
when 9 => log := 4;
when 10 => log := 4;
when 11 => log := 4;
when 12 => log := 4;
when 13 => log := 4;
when 14 => log := 4;
when 15 => log := 4;
when 16 => log := 4;
when 17 => log := 5;
when 18 => log := 5;
when 19 => log := 5;
when 20 => log := 5;
when 21 => log := 5;
when 22 => log := 5;
when 23 => log := 5;
when 24 => log := 5;
when 25 => log := 5;
when 26 => log := 5;
when 27 => log := 5;
when 28 => log := 5;
when 29 => log := 5;
when 30 => log := 5;
when 31 => log := 5;
when 32 => log := 5;
when 64 => log := 6;
when 128 => log := 7;
when 256 => log := 8;
when 512 => log := 9;
when 1024 => log := 10;
when 2048 => log := 11;
when 4096 => log := 12;
when 8192 => log := 13;
when 16384 => log := 14;
when 32768 => log := 15;
when 65536 => log := 16;
when 131072 => log := 17;
when 262144 => log := 18;
when 524288 => log := 19;
when 1048576 => log := 20;
when others => assert false
report "ERROR: log2() of value `" & str(int) &
"' not defined; adapt function"
severity error;
end case;
return log;
end log2;
end auxPkg;
| bsd-3-clause | 703981e87992c08b03c26600ae1bb2ab | 0.449742 | 4.093561 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/synlayQuartus/ASP/Platform_inst.vhd | 1 | 20,387 | component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
hex0_2_export : out std_logic_vector(20 downto 0); -- export
hex3_5_export : out std_logic_vector(20 downto 0); -- export
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic; -- SCLK
i2s_codec_iadcdat : in std_logic := 'X'; -- iadcdat
i2s_codec_iadclrc : in std_logic := 'X'; -- iadclrc
i2s_codec_ibclk : in std_logic := 'X'; -- ibclk
i2s_codec_idaclrc : in std_logic := 'X'; -- idaclrc
i2s_codec_odacdat : out std_logic; -- odacdat
i2s_gpio_iadcdat : in std_logic := 'X'; -- iadcdat
i2s_gpio_iadclrc : in std_logic := 'X'; -- iadclrc
i2s_gpio_ibclk : in std_logic := 'X'; -- ibclk
i2s_gpio_idaclrc : in std_logic := 'X'; -- idaclrc
i2s_gpio_odacdat : out std_logic; -- odacdat
keys_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
xck_clk : out std_logic -- clk
);
end component Platform;
u0 : component Platform
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hex0_2_export => CONNECTED_TO_hex0_2_export, -- hex0_2.export
hex3_5_export => CONNECTED_TO_hex3_5_export, -- hex3_5.export
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO0, -- .hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO1, -- .hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO2, -- .hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO3, -- .hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_SS0, -- .hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK => CONNECTED_TO_hps_io_hps_io_qspi_inst_CLK, -- .hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO48, -- .hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
i2c_SDAT => CONNECTED_TO_i2c_SDAT, -- i2c.SDAT
i2c_SCLK => CONNECTED_TO_i2c_SCLK, -- .SCLK
i2s_codec_iadcdat => CONNECTED_TO_i2s_codec_iadcdat, -- i2s_codec.iadcdat
i2s_codec_iadclrc => CONNECTED_TO_i2s_codec_iadclrc, -- .iadclrc
i2s_codec_ibclk => CONNECTED_TO_i2s_codec_ibclk, -- .ibclk
i2s_codec_idaclrc => CONNECTED_TO_i2s_codec_idaclrc, -- .idaclrc
i2s_codec_odacdat => CONNECTED_TO_i2s_codec_odacdat, -- .odacdat
i2s_gpio_iadcdat => CONNECTED_TO_i2s_gpio_iadcdat, -- i2s_gpio.iadcdat
i2s_gpio_iadclrc => CONNECTED_TO_i2s_gpio_iadclrc, -- .iadclrc
i2s_gpio_ibclk => CONNECTED_TO_i2s_gpio_ibclk, -- .ibclk
i2s_gpio_idaclrc => CONNECTED_TO_i2s_gpio_idaclrc, -- .idaclrc
i2s_gpio_odacdat => CONNECTED_TO_i2s_gpio_odacdat, -- .odacdat
keys_export => CONNECTED_TO_keys_export, -- keys.export
leds_export => CONNECTED_TO_leds_export, -- leds.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
switches_export => CONNECTED_TO_switches_export, -- switches.export
xck_clk => CONNECTED_TO_xck_clk -- xck.clk
);
| gpl-3.0 | 6e502c29f349b519b2f05f6c98c0fe53 | 0.463825 | 2.939302 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPrimitives/unitMultiply/hdl/Multiply-Rtl-a.vhd | 1 | 4,108 | -------------------------------------------------------------------------------
-- Title : Multiply
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Unit Multiply multiplies L and R channel with a factor
-------------------------------------------------------------------------------
architecture Rtl of Multiply is
---------------------------------------------------------------------------
-- Types and constants
---------------------------------------------------------------------------
subtype audio_data_t is sfixed(0 downto -(data_width_g-1));
constant silence_c : audio_data_t := (others => '0');
constant one_c : audio_data_t := (0 => '0', others => '1');
signal left_fact : audio_data_t;
signal right_fact : audio_data_t;
signal left_data, right_data : audio_data_t;
--signal right_buf : audio_data_t;
--signal right_buf_pending : std_ulogic;
--signal fact : audio_data_t;
--signal mult_data : audio_data_t;
--signal mult_res : audio_data_t;
begin
-- register process
--reg : process (csi_clk, rsi_reset_n) is
--begin -- process calc
-- if rsi_reset_n = '0' then -- asynchronous reset (active low)
-- right_buf <= silence_c;
-- right_buf_pending <= '0';
-- elsif rising_edge(csi_clk) then -- rising clock edge
-- if asi_left_valid = '1' and asi_right_valid = '1' then
-- right_buf <= to_sfixed(asi_right_data, 0, -(data_width_g-1));
-- right_buf_pending <= '1';
-- else
-- right_buf_pending <= '0';
-- end if;
-- end if;
--end process reg;
-- calc process
--calc : process (asi_left_valid, asi_left_data, asi_right_data, asi_right_valid, mult_res, left_fact, right_fact, right_buf) is
--begin -- process calc
-- -- default
-- aso_left_data <= (others => '0');
-- aso_right_data <= (others => '0');
-- aso_left_valid <= '0';
-- aso_right_valid <= '0';
-- fact <= left_fact;
-- mult_data <= to_sfixed(asi_left_data, 0, -(data_width_g-1));
-- if asi_left_valid = '1' then
-- aso_left_valid <= '1';
-- aso_left_data <= to_slv(mult_res);
-- elsif asi_right_valid = '1' then
-- aso_right_valid <= '1';
-- fact <= right_fact;
-- mult_data <= to_sfixed(asi_right_data, 0, -(data_width_g-1));
-- aso_right_data <= to_slv(mult_res);
-- elsif right_buf_pending = '1' then
-- aso_right_valid <= '1';
-- fact <= right_fact;
-- mult_data <= right_buf;
-- aso_right_data <= to_slv(mult_res);
-- end if;
--end process calc;
--mult : process (fact, mult_data) is
--begin -- process mult
-- mult_res <= resize(mult_data * fact, 0, -(data_width_g-1));
--end process mult;
-- two multiplication operations
left_data <= to_sfixed(asi_left_data, 0, -(data_width_g-1));
aso_left_valid <= asi_left_valid;
aso_left_data <= to_slv(resize(left_data * left_fact, 0, -(data_width_g-1)));
right_data <= to_sfixed(asi_right_data, 0, -(data_width_g-1));
aso_right_valid <= asi_right_valid;
aso_right_data <= to_slv(resize(right_data * right_fact, 0, -(data_width_g-1)));
-- MM INTERFACE for configuration
SetConfigReg : process (csi_clk, rsi_reset_n) is
variable factor : audio_data_t := silence_c;
begin
if rsi_reset_n = not('1') then -- low active reset
left_fact <= one_c;
right_fact <= one_c;
elsif rising_edge(csi_clk) then -- rising
if avs_s0_write = '1' then
-- convert std_logic_vector to sfixed
factor := to_sfixed(avs_s0_writedata(data_width_g-1 downto 0), 0, -(data_width_g-1));
case avs_s0_address is
when '0' => -- factor of left channel
left_fact <= factor;
when '1' => -- factor of right channel
right_fact <= factor;
when others => null;
end case;
end if;
end if;
end process;
end architecture Rtl;
| gpl-3.0 | 4156262d56514f10a65a39da3212f27f | 0.506086 | 3.358953 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/dp_register_decode.vhd | 1 | 5,480 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: dp_register_decode - Behavioral
--
-- Description: Extract the display port parameters from the
-- modes from a stream of display port register values
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dp_register_decode is
port ( clk : in std_logic;
de : in std_logic;
data : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(7 downto 0);
invalidate : in std_logic;
valid : out std_logic := '0';
revision : out std_logic_vector(7 downto 0) := (others => '0');
link_rate_2_70 : out std_logic := '0';
link_rate_1_62 : out std_logic := '0';
extended_framing : out std_logic := '0';
link_count : out std_logic_vector(3 downto 0) := (others => '0');
max_downspread : out std_logic_vector(7 downto 0) := (others => '0');
coding_supported : out std_logic_vector(7 downto 0) := (others => '0');
port0_capabilities : out std_logic_vector(15 downto 0) := (others => '0');
port1_capabilities : out std_logic_vector(15 downto 0) := (others => '0');
norp : out std_logic_vector(7 downto 0) := (others => '0')
);
end dp_register_decode;
architecture arch of dp_register_decode is
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
if de = '1' then
valid <= '0';
case addr is
when x"00" => revision <= data;
when x"01" => case data is
when x"0A" => link_rate_2_70 <= '1'; link_rate_1_62 <= '1';
when x"06" => link_rate_2_70 <= '0'; link_rate_1_62 <= '1';
when others => link_rate_2_70 <= '0'; link_rate_1_62 <= '0';
end case;
when x"02" => extended_framing <= data(7);
link_count <= data(3 downto 0);
when x"03" => max_downspread <= data;
when x"04" => norp <= data;
when x"05" =>
when x"06" => coding_supported <= data;
when x"07" =>
when x"08" => port0_capabilities( 7 downto 0) <= data;
when x"09" => port0_capabilities(15 downto 8) <= data;
when x"0A" => port1_capabilities( 7 downto 0) <= data;
when x"0B" => port1_capabilities(15 downto 8) <= data;
valid <= '1';
when others => NULL;
end case;
------------------------------------------------
-- Allow for an external event to invalidate the
-- outputs (e.g. hot plug)
------------------------------------------------
if invalidate = '1' then
valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
| mit | 413ee0b035992da0763237bf4034836e | 0.512226 | 4.126506 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/link_signal_mgmt.vhd | 1 | 12,089 | ----------------------------------------------------------------------------------
-- Module Name: link_signal_mgmt - Behavioral
--
-- Description: Controls the settings and state of the GTX transceivers based on
-- The registers that are read from the host.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity link_signal_mgmt is
Port ( mgmt_clk : in STD_LOGIC;
tx_powerup : in STD_LOGIC; -- Falling edge is used used as a reset too!
status_de : in std_logic;
adjust_de : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
-------------------------------------------
sink_channel_count : in std_logic_vector(2 downto 0);
source_channel_count : in std_logic_vector(2 downto 0);
stream_channel_count : in std_logic_vector(2 downto 0);
active_channel_count : out std_logic_vector(2 downto 0);
---------------------------------------------------------
powerup_channel : out std_logic_vector(3 downto 0) := (others => '0');
-----------------------------------------
clock_locked : out STD_LOGIC;
equ_locked : out STD_LOGIC;
symbol_locked : out STD_LOGIC;
align_locked : out STD_LOGIC;
preemp_0p0 : out STD_LOGIC := '0';
preemp_3p5 : out STD_LOGIC := '0';
preemp_6p0 : out STD_LOGIC := '0';
swing_0p4 : out STD_LOGIC := '0';
swing_0p6 : out STD_LOGIC := '0';
swing_0p8 : out STD_LOGIC := '0');
end link_signal_mgmt;
architecture arch of link_signal_mgmt is
signal power_mask : std_logic_vector(3 downto 0) := "0000";
signal preemp_level : std_logic_vector(1 downto 0) := "00";
signal voltage_level : std_logic_vector(1 downto 0) := "00";
signal channel_state : std_logic_vector(23 downto 0):= (others => '0');
signal channel_adjust : std_logic_vector(15 downto 0):= (others => '0');
signal active_channel_count_i : std_logic_vector(2 downto 0);
signal pipe_channel_count : std_logic_vector(2 downto 0);
begin
active_channel_count <= active_channel_count_i;
process(mgmt_clk)
begin
if rising_edge(mgmt_clk) then
----------------------------------------------------------
-- Work out how many channels will be active
-- (the min of source_channel_count and sink_channel_count
--
-- Also work out the power-up mask for the transceivers
-----------------------------------------------------------
case source_channel_count is
when "100" =>
case sink_channel_count is
when "100" => pipe_channel_count <= "100";
when "010" => pipe_channel_count <= "010";
when others => pipe_channel_count <= "001";
end case;
when "010" =>
case sink_channel_count is
when "100" => pipe_channel_count <= "010";
when "010" => pipe_channel_count <= "010";
when others => pipe_channel_count <= "001";
end case;
when others =>
pipe_channel_count <= "001";
end case;
case stream_channel_count is
when "100" =>
case pipe_channel_count is
when "100" => active_channel_count_i <= "100"; power_mask <= "1111";
when "010" => active_channel_count_i <= "010"; power_mask <= "0000";
when others => active_channel_count_i <= "000"; power_mask <= "0000";
end case;
when "010" =>
case pipe_channel_count is
when "100" => active_channel_count_i <= "010"; power_mask <= "0011";
when "010" => active_channel_count_i <= "010"; power_mask <= "0011";
when others => active_channel_count_i <= "000"; power_mask <= "0000";
end case;
when others =>
active_channel_count_i <= "001"; power_mask <= "0001";
end case;
---------------------------------------------
-- If the powerup is not asserted, then reset
-- everything.
---------------------------------------------
if tx_powerup = '1' then
powerup_channel <= power_mask;
else
powerup_channel <= (others => '0');
preemp_level <= "00";
voltage_level <= "00";
channel_state <= (others => '0');
channel_adjust <= (others => '0');
end if;
---------------------------------------------
-- Decode the power and pre-emphasis levels
---------------------------------------------
case preemp_level is
when "00" => preemp_0p0 <= '1'; preemp_3p5 <= '0'; preemp_6p0 <= '0';
when "01" => preemp_0p0 <= '0'; preemp_3p5 <= '1'; preemp_6p0 <= '0';
when others => preemp_0p0 <= '0'; preemp_3p5 <= '0'; preemp_6p0 <= '1';
end case;
case voltage_level is
when "00" => swing_0p4 <= '1'; swing_0p6 <= '0'; swing_0p8 <= '0';
when "01" => swing_0p4 <= '0'; swing_0p6 <= '1'; swing_0p8 <= '0';
when others => swing_0p4 <= '0'; swing_0p6 <= '0'; swing_0p8 <= '1';
end case;
-----------------------------------------------
-- Receive the status data from the AUX channel
-----------------------------------------------
if status_de = '1' then
case addr is
when x"02" => channel_state( 7 downto 0) <= data;
when x"03" => channel_state(15 downto 8) <= data;
when x"04" => channel_state(23 downto 16) <= data;
when others => NULL;
end case;
end if;
-----------------------------------------------
-- Receive the channel adjustment request
-----------------------------------------------
if adjust_de = '1' then
case addr is
when x"00" => channel_adjust( 7 downto 0) <= data;
when x"01" => channel_adjust(15 downto 8) <= data;
when others => NULL;
end case;
end if;
-----------------------------------------------
-- Update the status signals based on the
-- register data recieved over from the AUX
-- channel.
-----------------------------------------------
clock_locked <= '0';
equ_locked <= '0';
symbol_locked <= '0';
case active_channel_count_i is
when "001" => if (channel_state(3 downto 0) AND x"1") = x"1" then
clock_locked <= '1';
end if;
if (channel_state(3 downto 0) AND x"3") = x"3" then
equ_locked <= '1';
end if;
if (channel_state(3 downto 0) AND x"7") = x"7" then
symbol_locked <= '1';
end if;
when "010" => if (channel_state(7 downto 0) AND x"11") = x"11" then
clock_locked <= '1';
end if;
if (channel_state(7 downto 0) AND x"33") = x"33" then
equ_locked <= '1';
end if;
if (channel_state(7 downto 0) AND x"77") = x"77" then
symbol_locked <= '1';
end if;
when "100" => if (channel_state(15 downto 0) AND x"1111") = x"1111" then
clock_locked <= '1';
end if;
if (channel_state(15 downto 0) AND x"3333") = x"3333" then
equ_locked <= '1';
end if;
if (channel_state(15 downto 0) AND x"7777") = x"7777" then
symbol_locked <= '1';
end if;
when others => NULL;
end case;
align_locked <= channel_state(16);
end if;
end process;
end architecture; | mit | e8c1a33e932be50ea3cb9ffffe2eb4d0 | 0.408801 | 4.778261 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/training_and_channel_delay.vhd | 1 | 7,928 | ---------------------------------------------------
-- Module: training_and_channel_delay
--
-- Description: Allow the insertion of the training patterns into the symbol
-- stream, and ensure a clean switch-over to the input channel,
--
-- Also adds the 8b10b encoder's "force negative parity" flag
--
-- Also delay the symbols by the inter-channel skew (2 symbols per channel)
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-18 | Resolve clock domain crossing issues
------------------------------------------------------------------------------------
---------------------------------------------------
--
-- This is set up so the change over from test patters
-- to data happens seamlessly - e.g. the value for
-- on data_in when send_patter_1 and send_pattern_2
-- are both become zero is guarranteed to be sent
--
-- +----+--------------------+--------------------+
-- |Word| Training pattern 1 | Training pattern 2 |
-- | | Code MSB LSB | Code MSB LSB |
-- +----+--------------------+-------------------+
-- | 0 | D10.2 1010101010 | K28.5- 0101111100 |
-- | 1 | D10.2 1010101010 | D11.6 0110001011 |
-- | 2 | D10.2 1010101010 | K28.5+ 1010000011 |
-- | 3 | D10.2 1010101010 | D11.6 0110001011 |
-- | 4 | D10.2 1010101010 | D10.2 1010101010 |
-- | 5 | D10.2 1010101010 | D10.2 1010101010 |
-- | 6 | D10.2 1010101010 | D10.2 1010101010 |
-- | 7 | D10.2 1010101010 | D10.2 1010101010 |
-- | 8 | D10.2 1010101010 | D10.2 1010101010 |
-- | 9 | D10.2 1010101010 | D10.2 1010101010 |
-- +----+--------------------+--------------------+
-- Patterns are transmitted LSB first.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(19 downto 0) := (others => '0')
);
end training_and_channel_delay;
architecture arch of training_and_channel_delay is
signal state : std_logic_vector(3 downto 0) := "0000";
signal clock_train_meta : std_logic := '0';
signal clock_train_i : std_logic := '0';
signal align_train_meta : std_logic := '0';
signal align_train_i : std_logic := '0';
signal hold_at_state_one : std_logic_vector(9 downto 0) := "1111111111";
constant CODE_K28_5 : std_logic_vector(8 downto 0) := "110111100";
constant CODE_D11_6 : std_logic_vector(8 downto 0) := "011001011";
constant CODE_D10_2 : std_logic_vector(8 downto 0) := "001001010";
type a_delay_line is array (0 to 8) of std_logic_vector(19 downto 0);
signal delay_line : a_delay_line := (others => (others => '0'));
begin
with channel_delay select out_data <= delay_line(5) when "00",
delay_line(6) when "01",
delay_line(7) when "10",
delay_line(8) when others;
process(clk)
begin
if rising_edge(clk) then
-- Move the dalay line along
delay_line(1 to 8) <= delay_line(0 to 7);
delay_line(0) <= '0' & in_data(17 downto 9) & '0' & in_data(8 downto 0);
-- Do we ened to hold at state 1 until valid data has filtered down the delay line?
if align_train_i = '1' or clock_train_i = '1' then
hold_at_state_one <= (others => '1');
else
hold_at_state_one <= '0' & hold_at_state_one(hold_at_state_one'high downto 1);
end if;
-- Do we need to overwrite the data in slot 5 with the sync patterns?
case state is
when x"5" => state <= x"4"; delay_line(5) <= '0' & CODE_D11_6 & '1' & CODE_K28_5;
when x"4" => state <= x"3"; delay_line(5) <= '0' & CODE_D11_6 & '0' & CODE_K28_5;
when x"3" => state <= x"2"; delay_line(5) <= '0' & CODE_D10_2 & '0' & CODE_D10_2;
when x"2" => state <= x"1"; delay_line(5) <= '0' & CODE_D10_2 & '0' & CODE_D10_2;
when x"1" => state <= x"0"; delay_line(5) <= '0' & CODE_D10_2 & '0' & CODE_D10_2;
if align_train_i = '1' then
state <= x"5";
elsif hold_at_state_one(0) = '1' then
state <= x"1";
end if;
when others => state <= x"0";
if align_train_i = '1' then
state <= x"5";
elsif hold_at_state_one(0) = '1' then
state <= x"1";
end if;
end case;
clock_train_meta <= clock_train;
clock_train_i <= clock_train_meta;
align_train_meta <= align_train;
align_train_i <= align_train_meta;
end if;
end process;
end architecture; | mit | 628def80a06671e8cc60c8d4a821553e | 0.488143 | 3.844811 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpSimulation/unitSinGen/hdl/SinGen_tb.vhd | 1 | 1,467 | -------------------------------------------------------------------------------
-- Title : Testbench for design "SinGen"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use work.Global.all;
-------------------------------------------------------------------------------
entity SinGen_tb is
end entity SinGen_tb;
-------------------------------------------------------------------------------
architecture Bhv of SinGen_tb is
-- component generics
constant periode_g : time := 100 us;
constant sample_time_g : time := 200 ns;
-- component ports
signal data_o : audio_data_t;
signal data_valid_o : std_ulogic;
-- clock
signal Clk : std_logic := '1';
begin -- architecture Bhv
-- component instantiation
DUT : entity work.SinGen
generic map (
periode_g => periode_g,
sample_time_g => sample_time_g)
port map (
clk_i => Clk,
data_o => data_o,
data_valid_o => data_valid_o);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait;
end process WaveGen_Proc;
end architecture Bhv;
-------------------------------------------------------------------------------
| gpl-3.0 | 54c8ae72f33db503d276c93b6e9c8f36 | 0.467621 | 4.570093 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstfir4/tstfir4_cfg.vhd | 1 | 5,491 | ------------------------------------------------------------------------------
-- Configuration for fir testbench
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/tb_arch/tstfir4/tstfir4_cfg.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/27
-- $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
-- $Id: tstfir4_cfg.vhd 217 2005-01-13 16:52:03Z plessl $
------------------------------------------------------------------------------
-- ZUnit configuration for MUX testbench. This testbench is used for testing
-- the multiplexer function alu_mux. The ALU MUX instruction needs special
-- testing, since it is the first ternary operation on the Zippy array.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-28 CP created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTFIR4 is
type coeff4Array is array (0 to 3) of integer;
function tstfir4cfg(coeff : coeff4Array) return engineConfigRec;
end CfgLib_TSTFIR4;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTFIR4 is
----------------------------------------------------------------------------
-- 4-tap FIR filter
----------------------------------------------------------------------------
function tstfir4cfg (coeff : coeff4Array) return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin -- tstfir4cfg
---------------------------------------------------------------------------
-- row 0 multiplies:
---------------------------------------------------------------------------
for i in 0 to 3 loop
cfg.gridConf(0)(i).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(i).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(i).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(i).procConf.AluOpxS := ALU_OP_MULTLO;
cfg.gridConf(0)(i).procConf.ConstOpxD := i2cfgconst(coeff(coeff'length-1 - i));
cfg.gridConf(0)(i).routConf.i(0).HBusNxE(0) := '1'; -- hbusn_0.0
end loop; -- i
---------------------------------------------------------------------------
-- row 1 adds:
---------------------------------------------------------------------------
-- cell_1_1
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(1).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(1).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(1).routConf.i(0).LocalxE(LOCAL_NW) := '1'; -- NW neighb.
cfg.gridConf(1)(1).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
-- cell_1_2
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(2).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
-- cell_1_3
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(3).procConf.OutMuxS := O_REG;
cfg.gridConf(1)(3).procConf.AluOpxS := ALU_OP_ADD; -- add
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_W) := '1'; -- W neighb.
cfg.gridConf(1)(3).routConf.i(1).LocalxE(LOCAL_N) := '1'; -- N neighb.
cfg.gridConf(1)(3).routConf.o.HBusNxE(0) := '1'; -- hbusn_2.0 (oport 0)
-- engine input
cfg.inputDriverConf(0)(0)(0) := '1'; -- hbusn_0.0
-- engine outputs
cfg.outputDriverConf(0)(2)(0) := '1'; -- output on OUTP0 via hbusn_2.0
-- Input from FIFO0 (INP0), deactivate read from input FIFO0 5 cycles
-- before end
cfg.inportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEDOWN;
cfg.inportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.inportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(2, CCNTWIDTH));
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
-- Output to FIFO0 (OP0), activate write to output FIFO0 after 1 cycles
cfg.outportConf(0).Cmp0MuxS := CFG_IOPORT_MUX_CYCLEUP;
cfg.outportConf(0).Cmp0ModusxS := CFG_IOPORT_MODUS_LARGER;
cfg.outportConf(0).Cmp0ConstxD := std_logic_vector(to_unsigned(1, CCNTWIDTH));
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_CMP0;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF; -- InPort1 deactivated
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF; -- OutPort1 deactivated
return cfg;
end tstfir4cfg;
end CfgLib_TSTFIR4;
| bsd-3-clause | d0672f299d8a99112b60650e2ccdceca | 0.497359 | 3.43617 | false | true | false | false |
tmeissner/raspberrypi | raspiFpga/src/FiRoE.vhd | 1 | 1,909 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.components.all;
entity FiRoE is
generic (
IMP : string := "HDL",
TOGGLE : boolean := true
);
port (
FiRo_o : out std_logic;
Run_i : in std_logic
);
end entity FiRoE;
architecture rtl of FiRoE is
--+ signal for inverter loop
signal s_ring : std_logic_vector(15 downto 0);
signal s_tff : std_logic;
--+ attributes for synthesis tool to preserve inverter loop
attribute syn_keep : boolean;
attribute syn_hier : string;
attribute syn_hier of rtl : architecture is "hard";
attribute syn_keep of s_ring : signal is true;
attribute syn_keep of s_tff : signal is true;
--+ Attributes for lattice map tool to not merging inverter loop
attribute nomerge : boolean;
attribute nomerge of s_ring : signal is true;
begin
FiroRingG : for index in 0 to 30 generate
HdlG : if IMP = "HDL" generate
s_ring(index) <= not(s_ring(index - 1));
end generate HdlG;
LutG : if IMP = "LUT" generate
lut : LUT4
generic map (
init => x"FFFF"
)
port map (
Z => s_ring(i-1),
A => s_ring(i),
B => '0',
C => '0',
D => '0'
);
end generate LutG;
end generate FiroRingG;
s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and Run_i;
WithToggleG : if TOGGLE generate
tffP : process(Run_i, s_ring(15)) is
begin
if(Run_i = '0') then
s_tff <= '0';
elsif(rising_edge(s_ring(15))) then
s_tff <= not s_tff;
end if;
end process tffP;
FiRo_o <= s_ring(15) xor s_tff;
end generate WithToggleG;
WithoutToggleG : if not(TOGGLE) generate
FiRo_o <= s_ring(15);
end generate WithoutToggleG;
end architecture rtl;
| gpl-2.0 | 8f6624700c3f0f3e38d6ea178d8f2d30 | 0.592457 | 3.197655 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_cclkgating.vhd | 1 | 3,063 | ------------------------------------------------------------------------------
-- Testbench for cclkgating.vhd
--
-- Project :
-- File : tb_cclkgating.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_CClkGating is
end tb_CClkGating;
architecture arch of tb_CClkGating is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, en, dis, done);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal EnxE : std_logic;
signal CClockxC : std_logic;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : CClkGating
port map (
EnxEI => EnxE,
MClockxCI => ClkxC,
CClockxCO => CClockxC);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
EnxE <= '0';
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= en; -- enable
EnxE <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= dis; -- disable
EnxE <= '0';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= done; -- done
EnxE <= '0';
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 567feca6a52c99624a8ee6a7982d1e13 | 0.452498 | 4.419913 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/unitAvalonSTToI2S/hdl/AvalonSTToI2S-Rtl-a.vhd | 1 | 4,798 | architecture Rtl of AvalonSTToI2S is
type aInputState is (Waiting, LeftChannel, RightChannel);
type aRegion is (Idle, Tx);
-- bclk set, for sync and delay
type aSyncSet is record
Meta : std_logic;
Sync : std_logic;
Dlyd : std_logic;
end record;
constant cInitValSync : aSyncSet := (
Meta => '0',
Sync => '0',
Dlyd => '0'
);
type aRegSet is record
State : aInputState; -- current state
Region : aRegion;
BitIdx : unsigned(gDataWidthLen-1 downto 0); -- current bit index in data
Bclk : aSyncSet; -- bclk signals
Lrc : aSyncSet; -- left or rigth channel
LeftBuf, LeftData : std_logic_vector(gDataWidth-1 downto 0); -- left input data
RightBuf, RightData : std_logic_vector(gDataWidth-1 downto 0); -- right input data
end record;
constant cInitValR : aRegSet := (
State => Waiting,
Region => Idle,
Bclk => cInitValSync,
Lrc => cInitValSync,
BitIdx => (others => '0'),
LeftData => (others => '0'),
LeftBuf => (others => '0'),
RightData => (others => '0'),
RightBuf => (others => '0')
);
signal R, NxR : aRegSet;
begin -- architecture Rtl
-- register process
Reg : process(iClk, inReset)
begin
-- low active reset
if inReset = '0' then
R <= cInitValR;
-- rising clk edge
elsif rising_edge(iClk) then
R <= NxR;
end if;
end process;
Comb : process (R, iLRC, iBCLK, iLeftValid, iRightValid, iLeftData, iRightData) is
begin -- process
-- default
NxR <= R;
-- sync input and delay
NxR.Bclk.Meta <= iBCLK;
NxR.Bclk.Sync <= R.Bclk.Meta;
NxR.Bclk.Dlyd <= R.Bclk.Sync;
NxR.Lrc.Meta <= iLRC;
NxR.Lrc.Sync <= R.Lrc.Meta;
NxR.Lrc.Dlyd <= R.Lrc.Sync;
-- read right data from stream
if iRightValid = '1' then
NxR.RightBuf <= iRightData; -- read data
end if;
-- read left data from stream
if iLeftValid = '1' then
NxR.LeftBuf <= iLeftData; -- read data
end if;
if R.State = LeftChannel or R.Region = Idle then
NxR.RightData <= R.RightBuf; -- read data
end if;
if R.State = RightChannel or R.Region = Idle then
NxR.LeftData <= R.LeftBuf; -- read data
end if;
case R.State is
-- waiting for input data
when Waiting =>
-- default output
oDat <= '0';
-- reset bit index to max index
NxR.BitIdx <= to_unsigned(gDataWidth-1, NxR.BitIdx'length);
if R.Lrc.Dlyd = '0' and R.Lrc.Sync = '1' then
-- rising edge on LRC - Left Channel
NxR.State <= LeftChannel;
NxR.Region <= Tx;
elsif R.Lrc.Dlyd = '1' and R.Lrc.Sync = '0' then
-- falling edge on LRC - Right Channel
NxR.State <= RightChannel;
NxR.Region <= Tx;
end if;
when LeftChannel =>
case R.Region is
when Tx =>
oDAT <= R.LeftData(to_integer(R.BitIdx));
-- falling edge on BCLK
if R.Bclk.Dlyd = '1' and R.Bclk.Sync = '0' then
-- check bit index
if R.BitIdx = 0 then
-- end of frame
NxR.Region <= Idle;
-- reset bit index to max index
NxR.BitIdx <= to_unsigned(gDataWidth-1, NxR.BitIdx'length);
else
-- decrease bit index
NxR.BitIdx <= R.BitIdx - 1;
end if;
end if;
when Idle =>
-- set output DAT to zero
oDAT <= '0';
if R.Lrc.Sync = '0' then
-- Right Channel
NxR.State <= RightChannel;
NxR.Region <= Tx;
end if;
end case;
when RightChannel =>
case R.Region is
when Tx =>
oDAT <= R.RightData(to_integer(R.BitIdx));
-- falling edge on BCLK
if R.Bclk.Dlyd = '1' and R.Bclk.Sync = '0' then
-- check bit index
if R.BitIdx = 0 then
-- end of frame
NxR.Region <= Idle;
-- reset bit index to max index
NxR.BitIdx <= to_unsigned(gDataWidth-1, NxR.BitIdx'length);
else
-- decrease bit index
NxR.BitIdx <= R.BitIdx - 1;
end if;
end if;
when Idle =>
-- set output DAT to zero
oDAT <= '0';
if R.Lrc.Sync = '1' then
-- Right Channel
NxR.State <= LeftChannel;
NxR.Region <= Tx;
end if;
end case;
end case;
end process;
end architecture Rtl;
| gpl-3.0 | ea3bad04b58a26b4b257c2bf35f8ae11 | 0.507295 | 3.69361 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/testePlaca/n.vhd | 1 | 2,240 |
-- Create Date: 17:23:14 05/14/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity n is
port(
clk: in std_logic;
reset: in std_logic;
entrada: in std_logic_vector(7 downto 0);
anode : out STD_LOGIC_VECTOR (3 downto 0);
display_out : out STD_LOGIC_VECTOR (6 downto 0)
);
end n;
architecture Behavioral of n is
component bcdTo7SEG is
port (
clk: in std_logic;
bcd: in std_logic_vector(3 downto 0);
segmented: out std_logic_vector(6 downto 0)
);
end component;
component binToBCD is
Port (
binary : in STD_LOGIC_VECTOR (7 downto 0);
bcd : out STD_LOGIC_VECTOR (9 downto 0)
);
end component;
-- TYPES:
type T_STATE is (S0, S1 ,S2 ,S3);
-- SIGNALS:
signal STATE, NEXT_STATE : T_STATE ;
signal binary_to_bcd_conversor_IN_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal binary_to_bcd_conversor_OUT_DATA : STD_LOGIC_VECTOR (9 downto 0);
signal seg7_IN_DATA : STD_LOGIC_VECTOR (3 downto 0);
signal seg7_OUT_DATA : STD_LOGIC_VECTOR (6 downto 0);
begin
binary_to_bcd: binToBCD port map (
binary => "00000001",
bcd => binary_to_bcd_conversor_OUT_DATA
);
bcd_to_7seg: bcdTo7SEG port map (
clk => clk,
bcd => seg7_IN_DATA,
segmented => seg7_OUT_DATA
);
process (STATE, binary_to_bcd_conversor_OUT_DATA)
begin
case STATE is
when S0 =>
anode <= "1110";
seg7_IN_DATA <= binary_to_bcd_conversor_OUT_DATA (3 downto 0);
NEXT_STATE <= S1;
when S1 =>
anode <= "1101";
seg7_IN_DATA <= binary_to_bcd_conversor_OUT_DATA (7 downto 4);
NEXT_STATE <= S2;
when S2 =>
anode <= "1011";
seg7_IN_DATA <= "00" & binary_to_bcd_conversor_OUT_DATA (9 downto 8);
NEXT_STATE <= S3;
when S3 =>
anode <= "0111";
seg7_IN_DATA <= "0000";
NEXT_STATE <= S0;
when others =>
anode <= "1110";
seg7_IN_DATA <= "0010";
NEXT_STATE <= S0;
end case;
end process;
display_out <= seg7_OUT_DATA;
process(clk, reset)
begin
if (reset = '1') then
STATE <= S0;
else
if (clk'event and clk = '1') then
STATE <= NEXT_STATE;
end if;
end if;
end process;
end Behavioral;
| mit | 73ddf3176b7457c980ef9f0d361b774a | 0.617411 | 2.619883 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/ula.vhd | 1 | 1,897 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 10:44:10 05/03/2016
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
use IEEE.std_logic_arith.all;
USE ieee.numeric_std.all;
entity ula is
Port (
X : in STD_LOGIC_VECTOR (7 downto 0);
Y : in STD_LOGIC_VECTOR (7 downto 0);
selector : in STD_LOGIC_VECTOR (2 downto 0);
N : out STD_LOGIC;
Z : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (7 downto 0);
carryMUL: out STD_LOGIC_VECTOR (7 downto 0) -- need to make this save to address 100, add control unit state
);
end ula;
architecture Behavioral of ula is
signal result : STD_LOGIC_VECTOR(7 downto 0);
signal e1, e2 : STD_LOGIC_VECTOR(7 downto 0);
signal MULTIPLICATION: STD_LOGIC_VECTOR(15 downto 0);
begin
e1 <= X;
e2 <= Y;
process(selector, e1, e2)
begin
-- 000 ADD -- 001 AND
-- 010 OR -- 011 NOT
-- 100 LDA -- 101 SHR
-- 110 SHL -- 111 MUL
case selector is
when "000" => result <= e1 + e2; -- ADD
when "001" => result <= e1 AND e2; -- AND
when "010" => result <= e1 OR e2; -- OR
when "011" => result <= not(e1); -- NOT
when "100" => result <= e2; -- LDA
when "101" => result <= "0" & e1(7 downto 1); -- SHR
when "110" => result <= e1(6 downto 0) & "0"; -- SHL
when "111" => MULTIPLICATION <= e1 * e2; -- MUL
result <= MULTIPLICATION(7 downto 0); -- lsb
when others => result <= e2;
end case;
-- Zero
if(result = "00000000") then
Z <= '1';
else
Z <= '0';
end if;
-- Negative
N <= result(7);
end process;
carryMUL <= MULTIPLICATION(15 downto 8);
output <= result;
end Behavioral; | mit | ff37032ae15d1deb56bcbbe37401e23a | 0.58408 | 2.81037 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/ipcore_dir/dualBRAM.vhd | 1 | 6,086 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file dualBRAM.vhd when simulating
-- the core, dualBRAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY dualBRAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END dualBRAM;
ARCHITECTURE dualBRAM_a OF dualBRAM IS
-- synthesis translate_off
COMPONENT wrapped_dualBRAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_dualBRAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "00",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "dualBRAM.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 256,
c_read_depth_b => 256,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 256,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_dualBRAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END dualBRAM_a;
| mit | 3c085405001b13da5a1ce1870dbb34b2 | 0.537627 | 3.893794 | false | false | false | false |
plessl/zippy | vhdl/fifoctrl.vhd | 1 | 2,928 | ------------------------------------------------------------------------------
-- FIFO controller
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/fifoctrl.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/17
-- $Id: fifoctrl.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- FIFO controller: The controller arbitrates the access to the FIFO
-- between the engine. The engine is given priority over the FIFO access.
--
-- Whenever the engine is running (RunningxSI = 1) the engine can issue a FIFO
-- read or write request EngInPortxEI/EngOutPortxEI).
-- FIXME: Signal names are confusing, rename
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity FifoCtrl is
port (
RunningxSI : in std_logic;
EngInPortxEI : in std_logic;
EngOutPortxEI : in std_logic;
DecFifoWExEI : in std_logic;
DecFifoRExEI : in std_logic;
FifoMuxSO : out std_logic;
FifoWExEO : out std_logic;
FifoRExEO : out std_logic);
end FifoCtrl;
architecture simple of FifoCtrl is
signal EngWriteReqxS : std_logic;
signal EngReadReqxS : std_logic;
signal IFWriteReqxS : std_logic;
signal IFReadReqxS : std_logic;
begin -- simple
EngWriteReqxS <= RunningxSI and EngOutPortxEI;
EngReadReqxS <= RunningxSI and EngInPortxEI;
IFWriteReqxS <= DecFifoWExEI;
IFReadReqxS <= DecFifoRExEI;
FifoMux : process (EngWriteReqxS)
begin
-- always interface write unless engine write request;
-- engine write is priorized over interface write
if (EngWriteReqxS = '1') then
FifoMuxSO <= '1';
else
FifoMuxSO <= '0';
end if;
end process FifoMux;
FifoWE : process (EngWriteReqxS, IFWriteReqxS)
begin
if (EngWriteReqxS = '1') or (IFWriteReqxS = '1') then
FifoWExEO <= '1';
else
FifoWExEO <= '0';
end if;
end process FifoWE;
FifoRE : process (EngReadReqxS, IFReadReqxS)
begin
if (EngReadReqxS = '1') or (IFReadReqxS = '1') then
FifoRExEO <= '1';
else
FifoRExEO <= '0';
end if;
end process FifoRE;
-- assertions
WarnConcWrite : process (EngWriteReqxS, IFWriteReqxS)
begin
assert (EngWriteReqxS = '1') nand (IFWriteReqxS = '1')
report "FifoCtrl: concurrent interface and engine write requests"
severity warning;
end process WarnConcWrite;
WarnConcRead : process (EngReadReqxS, IFReadReqxS)
begin
assert (EngReadReqxS = '1') nand (IFReadReqxS = '1')
report "FifoCtrl: concurrent interface and engine read requests"
severity warning;
end process WarnConcRead;
end simple;
| bsd-3-clause | ca590d8ee134d3d9b40a3ce3d43e1488 | 0.617145 | 3.601476 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_upcounter.vhd | 1 | 3,882 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_UpCounter is
end tb_UpCounter;
architecture arch of tb_UpCounter is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, load, count);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal LoadxE : std_logic;
signal CExE : std_logic;
signal CinxD : std_logic_vector(WIDTH-1 downto 0);
signal CoutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut: UpCounter
generic map (
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
LoadxEI => LoadxE,
CExEI => CExE,
CinxDI => CinxD,
CoutxDO => CoutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
LoadxE <= '0';
CExE <= '0';
CinxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= load; -- load start value
LoadxE <= '1';
CinxD <= std_logic_vector(to_unsigned(2, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
LoadxE <= '0';
CExE <= '0';
CinxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= count; -- count
CExE <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
LoadxE <= '0';
CExE <= '0';
CinxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= load; -- load start value
LoadxE <= '1';
CExE <= '0';
CinxD <= std_logic_vector(to_unsigned(5, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
LoadxE <= '0';
CExE <= '0';
CinxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= count; -- count
CExE <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= done; -- done
LoadxE <= '0';
CExE <= '0';
CinxD <= (others => '0');
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 35105988338c4f7ea2cf46def708eb54 | 0.46033 | 4.018634 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/data_to_8b10b.vhd | 1 | 33,629 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]
--
-- Module Name: data_to_8b10b - Behavioral
--
-- Description: A pipelined implmentation to convert two 8-bit data words and
-- two sets of flags into ANSI 8b/10b symbols for transmission by
-- a high speed serial interface.
--
-- NOTE: The bit order is flipped from what is in the table to match the order
-- in which the transceiver transmits the data (LSB first). The standard
-- requires that it is sent MSB first.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-18 | Move bit reordering into the transceiver
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_to_8b10b is
port (
clk : in std_logic;
in_data : in std_logic_vector(19 downto 0);
out_data : out std_logic_vector(19 downto 0) := (others => '0')
);
end entity;
architecture arch of data_to_8b10b is
signal current_disparity_neg : std_logic := '0';
-- Stage 2 stuff
signal data0_2 : std_logic_vector(7 downto 0) := (others => '0');
signal data0k_2 : std_logic := '0';
signal data1_2 : std_logic_vector(7 downto 0) := (others => '0');
signal data1k_2 : std_logic := '0';
signal disparity0_neg_2 : std_logic := '0';
signal disparity1_neg_2 : std_logic := '0';
-- Stage 1 stuff
signal disparity0_odd_1 : std_logic := '0';
signal data0_1 : std_logic_vector(7 downto 0) := (others => '0');
signal data0k_1 : std_logic := '0';
signal data0forceneg_1 : std_logic := '0';
signal disparity1_odd_1 : std_logic := '0';
signal data1_1 : std_logic_vector(7 downto 0) := (others => '0');
signal data1k_1 : std_logic := '0';
signal data1forceneg_1 : std_logic := '0';
constant disparity_d : std_logic_vector(255 downto 0) :=
"00010110011111100111111011101000" &
"11101001100000011000000100010111" &
"11101001100000011000000100010111" &
"00010110011111100111111011101000" &
"11101001100000011000000100010111" &
"11101001100000011000000100010111" &
"11101001100000011000000100010111" &
"00010110011111100111111011101000";
constant disparity_k : std_logic_vector(255 downto 0) :=
"00000000000000000000000000000000" &
"00010000000000000000000000000000" &
"00010000000000000000000000000000" &
"00000000000000000000000000000000" &
"00010000000000000000000000000000" &
"00010000000000000000000000000000" &
"00010000000000000000000000000000" &
"00000000000000000000000000000000";
type a_symbols is array(0 to 511) of std_logic_vector(9 downto 0);
constant d_symbols : a_symbols := (
-- Pos RD, Neg RD
"0110001011", "1001110100", -- D0.0
"1000101011", "0111010100", -- D1.0
"0100101011", "1011010100", -- D2.0
"1100010100", "1100011011", -- D3.0
"0010101011", "1101010100", -- D4.0
"1010010100", "1010011011", -- D5.0
"0110010100", "0110011011", -- D6.0
"0001110100", "1110001011", -- D7.0
"0001101011", "1110010100", -- D8.0
"1001010100", "1001011011", -- D9.0
"0101010100", "0101011011", -- D10.0
"1101000100", "1101001011", -- D11.0
"0011010100", "0011011011", -- D12.0
"1011000100", "1011001011", -- D13.0
"0111000100", "0111001011", -- D14.0
"1010001011", "0101110100", -- D15.0
"1001001011", "0110110100", -- D16.0
"1000110100", "1000111011", -- D17.0
"0100110100", "0100111011", -- D18.0
"1100100100", "1100101011", -- D19.0
"0010110100", "0010111011", -- D20.0
"1010100100", "1010101011", -- D21.0
"0110100100", "0110101011", -- D22.0
"0001011011", "1110100100", -- D23.0
"0011001011", "1100110100", -- D24.0
"1001100100", "1001101011", -- D25.0
"0101100100", "0101101011", -- D26.0
"0010011011", "1101100100", -- D27.0
"0011100100", "0011101011", -- D28.0
"0100011011", "1011100100", -- D29.0
"1000011011", "0111100100", -- D30.0
"0101001011", "1010110100", -- D31.0
"0110001001", "1001111001", -- D0.1
"1000101001", "0111011001", -- D1.1
"0100101001", "1011011001", -- D2.1
"1100011001", "1100011001", -- D3.1
"0010101001", "1101011001", -- D4.1
"1010011001", "1010011001", -- D5.1
"0110011001", "0110011001", -- D6.1
"0001111001", "1110001001", -- D7.1
"0001101001", "1110011001", -- D8.1
"1001011001", "1001011001", -- D9.1
"0101011001", "0101011001", -- D10.1
"1101001001", "1101001001", -- D11.1
"0011011001", "0011011001", -- D12.1
"1011001001", "1011001001", -- D13.1
"0111001001", "0111001001", -- D14.1
"1010001001", "0101111001", -- D15.1
"1001001001", "0110111001", -- D16.1
"1000111001", "1000111001", -- D17.1
"0100111001", "0100111001", -- D18.1
"1100101001", "1100101001", -- D19.1
"0010111001", "0010111001", -- D20.1
"1010101001", "1010101001", -- D21.1
"0110101001", "0110101001", -- D22.1
"0001011001", "1110101001", -- D23.1
"0011001001", "1100111001", -- D24.1
"1001101001", "1001101001", -- D25.1
"0101101001", "0101101001", -- D26.1
"0010011001", "1101101001", -- D27.1
"0011101001", "0011101001", -- D28.1
"0100011001", "1011101001", -- D29.1
"1000011001", "0111101001", -- D30.1
"0101001001", "1010111001", -- D31.1
"0110000101", "1001110101", -- D0.2
"1000100101", "0111010101", -- D1.2
"0100100101", "1011010101", -- D2.2
"1100010101", "1100010101", -- D3.2
"0010100101", "1101010101", -- D4.2
"1010010101", "1010010101", -- D5.2
"0110010101", "0110010101", -- D6.2
"0001110101", "1110000101", -- D7.2
"0001100101", "1110010101", -- D8.2
"1001010101", "1001010101", -- D9.2
"0101010101", "0101010101", -- D10.2
"1101000101", "1101000101", -- D11.2
"0011010101", "0011010101", -- D12.2
"1011000101", "1011000101", -- D13.2
"0111000101", "0111000101", -- D14.2
"1010000101", "0101110101", -- D15.2
"1001000101", "0110110101", -- D16.2
"1000110101", "1000110101", -- D17.2
"0100110101", "0100110101", -- D18.2
"1100100101", "1100100101", -- D19.2
"0010110101", "0010110101", -- D20.2
"1010100101", "1010100101", -- D21.2
"0110100101", "0110100101", -- D22.2
"0001010101", "1110100101", -- D23.2
"0011000101", "1100110101", -- D24.2
"1001100101", "1001100101", -- D25.2
"0101100101", "0101100101", -- D26.2
"0010010101", "1101100101", -- D27.2
"0011100101", "0011100101", -- D28.2
"0100010101", "1011100101", -- D29.2
"1000010101", "0111100101", -- D30.2
"0101000101", "1010110101", -- D31.2
"0110001100", "1001110011", -- D0.3
"1000101100", "0111010011", -- D1.3
"0100101100", "1011010011", -- D2.3
"1100010011", "1100011100", -- D3.3
"0010101100", "1101010011", -- D4.3
"1010010011", "1010011100", -- D5.3
"0110010011", "0110011100", -- D6.3
"0001110011", "1110001100", -- D7.3
"0001101100", "1110010011", -- D8.3
"1001010011", "1001011100", -- D9.3
"0101010011", "0101011100", -- D10.3
"1101000011", "1101001100", -- D11.3
"0011010011", "0011011100", -- D12.3
"1011000011", "1011001100", -- D13.3
"0111000011", "0111001100", -- D14.3
"1010001100", "0101110011", -- D15.3
"1001001100", "0110110011", -- D16.3
"1000110011", "1000111100", -- D17.3
"0100110011", "0100111100", -- D18.3
"1100100011", "1100101100", -- D19.3
"0010110011", "0010111100", -- D20.3
"1010100011", "1010101100", -- D21.3
"0110100011", "0110101100", -- D22.3
"0001011100", "1110100011", -- D23.3
"0011001100", "1100110011", -- D24.3
"1001100011", "1001101100", -- D25.3
"0101100011", "0101101100", -- D26.3
"0010011100", "1101100011", -- D27.3
"0011100011", "0011101100", -- D28.3
"0100011100", "1011100011", -- D29.3
"1000011100", "0111100011", -- D30.3
"0101001100", "1010110011", -- D31.3
"0110001101", "1001110010", -- D0.4
"1000101101", "0111010010", -- D1.4
"0100101101", "1011010010", -- D2.4
"1100010010", "1100011101", -- D3.4
"0010101101", "1101010010", -- D4.4
"1010010010", "1010011101", -- D5.4
"0110010010", "0110011101", -- D6.4
"0001110010", "1110001101", -- D7.4
"0001101101", "1110010010", -- D8.4
"1001010010", "1001011101", -- D9.4
"0101010010", "0101011101", -- D10.4
"1101000010", "1101001101", -- D11.4
"0011010010", "0011011101", -- D12.4
"1011000010", "1011001101", -- D13.4
"0111000010", "0111001101", -- D14.4
"1010001101", "0101110010", -- D15.4
"1001001101", "0110110010", -- D16.4
"1000110010", "1000111101", -- D17.4
"0100110010", "0100111101", -- D18.4
"1100100010", "1100101101", -- D19.4
"0010110010", "0010111101", -- D20.4
"1010100010", "1010101101", -- D21.4
"0110100010", "0110101101", -- D22.4
"0001011101", "1110100010", -- D23.4
"0011001101", "1100110010", -- D24.4
"1001100010", "1001101101", -- D25.4
"0101100010", "0101101101", -- D26.4
"0010011101", "1101100010", -- D27.4
"0011100010", "0011101101", -- D28.4
"0100011101", "1011100010", -- D29.4
"1000011101", "0111100010", -- D30.4
"0101001101", "1010110010", -- D31.4
"0110001010", "1001111010", -- D0.5
"1000101010", "0111011010", -- D1.5
"0100101010", "1011011010", -- D2.5
"1100011010", "1100011010", -- D3.5
"0010101010", "1101011010", -- D4.5
"1010011010", "1010011010", -- D5.5
"0110011010", "0110011010", -- D6.5
"0001111010", "1110001010", -- D7.5
"0001101010", "1110011010", -- D8.5
"1001011010", "1001011010", -- D9.5
"0101011010", "0101011010", -- D10.5
"1101001010", "1101001010", -- D11.5
"0011011010", "0011011010", -- D12.5
"1011001010", "1011001010", -- D13.5
"0111001010", "0111001010", -- D14.5
"1010001010", "0101111010", -- D15.5
"1001001010", "0110111010", -- D16.5
"1000111010", "1000111010", -- D17.5
"0100111010", "0100111010", -- D18.5
"1100101010", "1100101010", -- D19.5
"0010111010", "0010111010", -- D20.5
"1010101010", "1010101010", -- D21.5
"0110101010", "0110101010", -- D22.5
"0001011010", "1110101010", -- D23.5
"0011001010", "1100111010", -- D24.5
"1001101010", "1001101010", -- D25.5
"0101101010", "0101101010", -- D26.5
"0010011010", "1101101010", -- D27.5
"0011101010", "0011101010", -- D28.5
"0100011010", "1011101010", -- D29.5
"1000011010", "0111101010", -- D30.5
"0101001010", "1010111010", -- D31.5
"0110000110", "1001110110", -- D0.6
"1000100110", "0111010110", -- D1.6
"0100100110", "1011010110", -- D2.6
"1100010110", "1100010110", -- D3.6
"0010100110", "1101010110", -- D4.6
"1010010110", "1010010110", -- D5.6
"0110010110", "0110010110", -- D6.6
"0001110110", "1110000110", -- D7.6
"0001100110", "1110010110", -- D8.6
"1001010110", "1001010110", -- D9.6
"0101010110", "0101010110", -- D10.6
"1101000110", "1101000110", -- D11.6
"0011010110", "0011010110", -- D12.6
"1011000110", "1011000110", -- D13.6
"0111000110", "0111000110", -- D14.6
"1010000110", "0101110110", -- D15.6
"1001000110", "0110110110", -- D16.6
"1000110110", "1000110110", -- D17.6
"0100110110", "0100110110", -- D18.6
"1100100110", "1100100110", -- D19.6
"0010110110", "0010110110", -- D20.6
"1010100110", "1010100110", -- D21.6
"0110100110", "0110100110", -- D22.6
"0001010110", "1110100110", -- D23.6
"0011000110", "1100110110", -- D24.6
"1001100110", "1001100110", -- D25.6
"0101100110", "0101100110", -- D26.6
"0010010110", "1101100110", -- D27.6
"0011100110", "0011100110", -- D28.6
"0100010110", "1011100110", -- D29.6
"1000010110", "0111100110", -- D30.6
"0101000110", "1010110110", -- D31.6
"0110001110", "1001110001", -- D0.7
"1000101110", "0111010001", -- D1.7
"0100101110", "1011010001", -- D2.7
"1100010001", "1100011110", -- D3.7
"0010101110", "1101010001", -- D4.7
"1010010001", "1010011110", -- D5.7
"0110010001", "0110011110", -- D6.7
"0001110001", "1110001110", -- D7.7
"0001101110", "1110010001", -- D8.7
"1001010001", "1001011110", -- D9.7
"0101010001", "0101011110", -- D10.7
"1101001000", "1101001110", -- D11.7
"0011010001", "0011011110", -- D12.7
"1011001000", "1011001110", -- D13.7
"0111001000", "0111001110", -- D14.7
"1010001110", "0101110001", -- D15.7
"1001001110", "0110110001", -- D16.7
"1000110001", "1000110111", -- D17.7
"0100110001", "0100110111", -- D18.7
"1100100001", "1100101110", -- D19.7
"0010110001", "0010110111", -- D20.7
"1010100001", "1010101110", -- D21.7
"0110100001", "0110101110", -- D22.7
"0001011110", "1110100001", -- D23.7
"0011001110", "1100110001", -- D24.7
"1001100001", "1001101110", -- D25.7
"0101100001", "0101101110", -- D26.7
"0010011110", "1101100001", -- D27.7
"0011100001", "0011101110", -- D28.7
"0100011110", "1011100001", -- D29.7
"1000011110", "0111100001", -- D30.7
"0101001110", "1010110001" -- D31.7
);
constant k_symbols : a_symbols := (
-- Pos RD, Neg RD
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K23.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K27.0
"1100001011", "0011110100", -- K28.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K29.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K30.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K31.0
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K23.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K27.1
"1100000110", "0011111001", -- K28.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K29.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K30.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K31.1
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K23.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K27.2
"1100001010", "0011110101", -- K28.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K29.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K30.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K31.2
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K23.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K27.3
"1100001100", "0011110011", -- K28.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K29.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K30.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K31.3
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K23.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K27.4
"1100001101", "0011110010", -- K28.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K29.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K30.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K31.4
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K23.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K27.5
"1100000101", "0011111010", -- K28.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K29.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K30.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K31.5
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K23.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K27.6
"1100001001", "0011110110", -- K28.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K29.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K30.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K31.6
"XXXXXXXXXX", "XXXXXXXXXX", -- K0.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K1.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K2.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K3.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K4.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K5.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K6.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K7.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K8.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K9.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K10.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K11.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K12.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K13.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K14.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K15.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K16.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K17.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K18.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K19.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K20.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K21.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K22.7
"0001010111", "1110101000", -- K23.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K24.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K25.7
"XXXXXXXXXX", "XXXXXXXXXX", -- K26.7
"0010010111", "1101101000", -- K27.7
"1100000111", "0011111000", -- K28.7
"0100010111", "1011101000", -- K29.7
"1000010111", "0111101000", -- K30.7
"XXXXXXXXXX", "XXXXXXXXXX" -- K31.7
);
signal data0 : std_logic_vector(7 downto 0);
signal data1 : std_logic_vector(7 downto 0);
signal data0k : std_logic;
signal data1k : std_logic;
signal data0forceneg : std_logic;
signal data1forceneg : std_logic;
begin
data0 <= in_data(7 downto 0);
data0k <= in_data(8);
data0forceneg <= in_data(9);
data1 <= in_data(17 downto 10);
data1k <= in_data(18);
data1forceneg <= in_data(19);
process(clk)
variable index0 : unsigned(8 downto 0);
variable index1 : unsigned(8 downto 0);
begin
if rising_edge(clk) then
-----------------------------------------------------------
-- Stage 3 - work out the final symbol based on the
-- disparity calcuated in stage 2
----------------------------------------------------------
index0 := unsigned(data0_2 & disparity0_neg_2);
index1 := unsigned(data1_2 & disparity1_neg_2);
if data0k_2 = '1' then
out_data(9 downto 0) <= k_symbols(to_integer(index0));
else
out_data(9 downto 0) <= d_symbols(to_integer(index0));
end if;
if data1k_2 = '1' then
out_data(19 downto 10) <= k_symbols(to_integer(index1));
else
out_data(19 downto 10) <= d_symbols(to_integer(index1));
end if;
-----------------------------------------------------------
-- Stage 2 - work out the disparity for each symbol, and
-- the disparity for the next set of symbols.
----------------------------------------------------------
if data0forceneg = '0' then
if data1forceneg = '0' then
disparity0_neg_2 <= current_disparity_neg;
disparity1_neg_2 <= current_disparity_neg XOR disparity0_odd_1;
current_disparity_neg <= current_disparity_neg XOR disparity0_odd_1 XOR disparity1_odd_1;
else
disparity0_neg_2 <= current_disparity_neg;
disparity1_neg_2 <= '1';
current_disparity_neg <= '1' XOR disparity1_odd_1;
end if;
else
if data1forceneg = '0' then
disparity0_neg_2 <= '1';
disparity1_neg_2 <= '1' XOR disparity0_odd_1;
current_disparity_neg <= '1' XOR disparity0_odd_1 XOR disparity1_odd_1;
else
disparity0_neg_2 <= '1';
disparity1_neg_2 <= '1';
current_disparity_neg <= '1' XOR disparity1_odd_1;
end if;
end if;
data0_2 <= data0_1;
data0k_2 <= data0k_1;
data1_2 <= data1_1;
data1k_2 <= data1k_1;
-----------------------------------------------------------
-- Stage 1 - Look up the disparity for each data word
----------------------------------------------------------
if data0k = '1' then
disparity0_odd_1 <= disparity_k(to_integer(unsigned(data0)));
else
disparity0_odd_1 <= disparity_d(to_integer(unsigned(data0)));
end if;
data0_1 <= data0;
data0k_1 <= data0k;
data0forceneg_1 <= data0forceneg;
if data1k = '1' then
disparity1_odd_1 <= disparity_k(to_integer(unsigned(data1)));
else
disparity1_odd_1 <= disparity_d(to_integer(unsigned(data1)));
end if;
data1_1 <= data1;
data1k_1 <= data1k;
data1forceneg_1 <= data1forceneg;
end if;
end process;
end architecture; | mit | d1f160ed301de099948d4e9563a8d99f | 0.506022 | 3.736971 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPackages/pkgLfsr/src/lfsr-p.vhd | 1 | 12,386 | -------------------------------------------------------------------------------
-- package for lfsr next state determination
-- the determination use the maximum feedback taps
-- the sequence will cycle through all values from 0 to 2^n-1
-- the lfsr should start with state (others => '0')
-- and the state (others => '1') is not allowed,
-- because the lfsr will stuck in this state
-- implementation:
-- must be implementet with n downto 1 because a lfsr has no zero tap
-- lfsr_state : std_ulogic_vector(n downto 1);
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package lfsr is
-- determinate next lfsr state
function lfsr_nx_state (
constant lfsr_state : std_ulogic_vector)
return std_ulogic_vector;
end package lfsr;
package body lfsr is
function lfsr_nx_state (
constant lfsr_state : std_ulogic_vector)
return std_ulogic_vector is
-- feedback taps
-- table from xilinx app note 052
constant lfsr_fb_table_len_c : natural := 168;
type lfsr_fb_table_t is array (
3 to lfsr_fb_table_len_c,
1 to lfsr_fb_table_len_c) of boolean;
constant lfsr_fb_table_c : lfsr_fb_table_t := (
(3 | 2 => true, others => false),
(4 | 3 => true, others => false),
(5 | 3 => true, others => false),
(6 | 5 => true, others => false),
(7 | 6 => true, others => false),
(8 | 6 | 5 | 4 => true, others => false),
(9 | 5 => true, others => false),
(10 | 7 => true, others => false),
(11 | 9 => true, others => false),
(12 | 6 | 4 | 1 => true, others => false),
(13 | 4 | 3 | 1 => true, others => false),
(14 | 5 | 3 | 1 => true, others => false),
(15 | 14 => true, others => false),
(16 | 15 | 13 | 4 => true, others => false),
(17 | 14 => true, others => false),
(18 | 11 => true, others => false),
(19 | 6 | 2 | 1 => true, others => false),
(20 | 17 => true, others => false),
(21 | 19 => true, others => false),
(22 | 21 => true, others => false),
(23 | 18 => true, others => false),
(24 | 23 | 22 | 17 => true, others => false),
(25 | 22 => true, others => false),
(26 | 6 | 2 | 1 => true, others => false),
(27 | 5 | 2 | 1 => true, others => false),
(28 | 25 => true, others => false),
(29 | 27 => true, others => false),
(30 | 6 | 4 | 1 => true, others => false),
(31 | 28 => true, others => false),
(32 | 22 | 2 | 1 => true, others => false),
(33 | 20 => true, others => false),
(34 | 27 | 2 | 1 => true, others => false),
(35 | 33 => true, others => false),
(36 | 25 => true, others => false),
(37 | 5 | 4 | 3 | 2 | 1 => true, others => false),
(38 | 6 | 5 | 1 => true, others => false),
(39 | 35 => true, others => false),
(40 | 38 | 21 | 19 => true, others => false),
(41 | 38 => true, others => false),
(42 | 41 | 20 | 19 => true, others => false),
(43 | 42 | 38 | 37 => true, others => false),
(44 | 43 | 18 | 17 => true, others => false),
(45 | 44 | 42 | 41 => true, others => false),
(46 | 45 | 26 | 25 => true, others => false),
(47 | 42 => true, others => false),
(48 | 47 | 21 | 20 => true, others => false),
(49 | 40 => true, others => false),
(50 | 49 | 24 | 23 => true, others => false),
(51 | 50 | 36 | 35 => true, others => false),
(52 | 49 => true, others => false),
(53 | 52 | 38 | 37 => true, others => false),
(54 | 53 | 18 | 17 => true, others => false),
(55 | 31 => true, others => false),
(56 | 55 | 35 | 34 => true, others => false),
(57 | 50 => true, others => false),
(58 | 39 => true, others => false),
(59 | 58 | 38 | 37 => true, others => false),
(60 | 59 => true, others => false),
(61 | 60 | 46 | 45 => true, others => false),
(62 | 61 | 6 | 5 => true, others => false),
(63 | 62 => true, others => false),
(64 | 63 | 61 | 60 => true, others => false),
(65 | 47 => true, others => false),
(66 | 65 | 57 | 56 => true, others => false),
(67 | 66 | 58 | 57 => true, others => false),
(68 | 59 => true, others => false),
(69 | 67 | 42 | 40 => true, others => false),
(70 | 69 | 55 | 54 => true, others => false),
(71 | 65 => true, others => false),
(72 | 66 | 25 | 19 => true, others => false),
(73 | 48 => true, others => false),
(74 | 73 | 59 | 58 => true, others => false),
(75 | 74 | 65 | 64 => true, others => false),
(76 | 75 | 41 | 40 => true, others => false),
(77 | 76 | 47 | 46 => true, others => false),
(78 | 77 | 59 | 58 => true, others => false),
(79 | 70 => true, others => false),
(80 | 79 | 43 | 42 => true, others => false),
(81 | 77 => true, others => false),
(82 | 79 | 47 | 44 => true, others => false),
(83 | 82 | 38 | 37 => true, others => false),
(84 | 71 => true, others => false),
(85 | 84 | 58 | 57 => true, others => false),
(86 | 85 | 74 | 73 => true, others => false),
(87 | 74 => true, others => false),
(88 | 87 | 17 | 16 => true, others => false),
(89 | 51 => true, others => false),
(90 | 89 | 72 | 71 => true, others => false),
(91 | 90 | 8 | 7 => true, others => false),
(92 | 91 | 80 | 79 => true, others => false),
(93 | 91 => true, others => false),
(94 | 73 => true, others => false),
(95 | 84 => true, others => false),
(96 | 94 | 49 | 47 => true, others => false),
(97 | 91 => true, others => false),
(98 | 87 => true, others => false),
(99 | 97 | 54 | 52 => true, others => false),
(100 | 63 => true, others => false),
(101 | 100 | 95 | 94 => true, others => false),
(102 | 101 | 36 | 35 => true, others => false),
(103 | 94 => true, others => false),
(104 | 103 | 94 | 93 => true, others => false),
(105 | 89 => true, others => false),
(106 | 91 => true, others => false),
(107 | 105 | 44 | 42 => true, others => false),
(108 | 77 => true, others => false),
(109 | 108 | 103 | 102 => true, others => false),
(110 | 109 | 98 | 97 => true, others => false),
(111 | 101 => true, others => false),
(112 | 110 | 69 | 67 => true, others => false),
(113 | 104 => true, others => false),
(114 | 113 | 33 | 32 => true, others => false),
(115 | 114 | 101 | 100 => true, others => false),
(116 | 115 | 46 | 45 => true, others => false),
(117 | 115 | 99 | 97 => true, others => false),
(118 | 85 => true, others => false),
(119 | 111 => true, others => false),
(120 | 113 | 9 | 2 => true, others => false),
(121 | 103 => true, others => false),
(122 | 131 | 63 | 62 => true, others => false),
(123 | 121 => true, others => false),
(124 | 87 => true, others => false),
(125 | 124 | 18 | 17 => true, others => false),
(126 | 125 | 90 | 89 => true, others => false),
(127 | 126 => true, others => false),
(128 | 126 | 101 | 99 => true, others => false),
(129 | 124 => true, others => false),
(130 | 127 => true, others => false),
(131 | 130 | 84 | 83 => true, others => false),
(132 | 103 => true, others => false),
(133 | 132 | 82 | 81 => true, others => false),
(134 | 77 => true, others => false),
(135 | 124 => true, others => false),
(136 | 125 | 11 | 10 => true, others => false),
(137 | 116 => true, others => false),
(138 | 137 | 131 | 130 => true, others => false),
(139 | 136 | 134 | 131 => true, others => false),
(140 | 111 => true, others => false),
(141 | 140 | 110 | 109 => true, others => false),
(142 | 121 => true, others => false),
(143 | 142 | 123 | 122 => true, others => false),
(144 | 143 | 75 | 74 => true, others => false),
(145 | 93 => true, others => false),
(146 | 145 | 87 | 86 => true, others => false),
(147 | 146 | 110 | 109 => true, others => false),
(148 | 121 => true, others => false),
(149 | 148 | 40 | 39 => true, others => false),
(150 | 97 => true, others => false),
(151 | 148 => true, others => false),
(152 | 151 | 87 | 86 => true, others => false),
(153 | 152 => true, others => false),
(154 | 152 | 27 | 25 => true, others => false),
(155 | 154 | 124 | 123 => true, others => false),
(156 | 155 | 41 | 40 => true, others => false),
(157 | 156 | 131 | 130 => true, others => false),
(158 | 157 | 132 | 131 => true, others => false),
(159 | 128 => true, others => false),
(160 | 159 | 142 | 141 => true, others => false),
(161 | 143 => true, others => false),
(162 | 161 | 75 | 74 => true, others => false),
(163 | 162 | 161 | 104 | 103 => true, others => false),
(164 | 163 | 151 | 150 => true, others => false),
(165 | 164 | 135 | 134 => true, others => false),
(166 | 165 | 128 | 127 => true, others => false),
(167 | 161 => true, others => false),
(168 | 166 | 153 | 151 => true, others => false));
constant xnor_neutral_elem_c : std_ulogic := '1';
variable fb_v : std_ulogic := xnor_neutral_elem_c;
begin
assert (lfsr_state'right = 1)
report "LFSR needs to be indexed like n downto 1"
severity failure;
assert (lfsr_state'left <= lfsr_fb_table_len_c)
report "Maximum LFSR length is 168!"
severity failure;
assert (lfsr_state'left >= 3)
report "Minimum LFSR length is 3!"
severity failure;
-- Since the xnor function is commutative and associative
for idx in lfsr_state'range loop
if lfsr_fb_table_c(lfsr_state'length, idx) then
fb_v := fb_v xnor lfsr_state(idx);
end if;
end loop;
-- Shift the computed bit into the LFSR. This is the next state of the LFSR
return lfsr_state(lfsr_state'length-1 downto 1) & fb_v;
end function lfsr_nx_state;
end package body lfsr;
| gpl-3.0 | 22ea5da6a464098406da13567e3924ac | 0.398272 | 4.038474 | false | false | false | false |
hamsternz/FPGA_DisplayPort | test_benches/tb_aux_channel.vhd | 1 | 19,521 | ----------------------------------------------------------------------------------
-- Module Name: tb_aux_channel - Behavioral
--
-- Description: A testbench for the tb_aux_channel
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_aux_channel is
end entity;
architecture arch of tb_aux_channel is
component top_level is
port (
clk : in std_logic;
debug_pmod : out std_logic_vector(7 downto 0) := (others => '0');
switches : in std_logic_vector(7 downto 0) := (others => '0');
leds : out std_logic_vector(7 downto 0) := (others => '0');
------------------------------
refclk0_p : in STD_LOGIC;
refclk0_n : in STD_LOGIC;
refclk1_p : in STD_LOGIC;
refclk1_n : in STD_LOGIC;
gtptxp : out std_logic_vector(1 downto 0);
gtptxn : out std_logic_vector(1 downto 0);
------------------------------
dp_tx_hp_detect : in std_logic;
dp_tx_aux_p : inout std_logic;
dp_tx_aux_n : inout std_logic;
dp_rx_aux_p : inout std_logic;
dp_rx_aux_n : inout std_logic
);
end component;
signal clk : std_logic := '0';
signal debug_pmod : std_logic_vector(7 downto 0) := (others => '0');
signal dp_tx_aux_p : std_logic := '0';
signal dp_tx_aux_n : std_logic := '0';
signal dp_rx_aux_p : std_logic := '0';
signal dp_rx_aux_n : std_logic := '0';
signal dp_tx_hpd : std_logic := '0';
signal refclk0_p : STD_LOGIC;
signal refclk0_n : STD_LOGIC;
signal refclk1_p : STD_LOGIC := '1';
signal refclk1_n : STD_LOGIC := '0';
signal gtptxp : std_logic_vector(1 downto 0);
signal gtptxn : std_logic_vector(1 downto 0);
begin
uut: top_level PORT MAP (
clk => clk,
switches => (others => '0'),
leds => open,
debug_pmod => debug_pmod,
dp_tx_aux_p => dp_tx_aux_p,
dp_tx_aux_n => dp_tx_aux_n,
dp_rx_aux_p => dp_rx_aux_p,
dp_rx_aux_n => dp_rx_aux_n,
dp_tx_hp_detect => dp_tx_hpd,
refclk0_p => refclk0_p,
refclk0_n => refclk0_n,
refclk1_p => refclk1_p,
refclk1_n => refclk1_n,
gtptxp => gtptxp,
gtptxn => gtptxn
);
process
begin
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00s
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
for k in 0 to 7 loop
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Extra for the ACK
for i in 0 to 16 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
for j in 0 to 15 loop
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
for i in 1 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
end loop;
-- Now the display port version read
-- Reply with 00 01
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
-- Now the DisplayPort register read
-- Reply with 00 00 00 00 00 00 00 00 00 00 00 00 00
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 13*8 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
--- register write 1
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00s
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
--- register write 2
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00s
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
--- register write downspread
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00s
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
--- register write set link count
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00s
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
--- register write link tranning pattern # 1
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00s
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
--- register write set link voltages
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00s
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
--- register read - link status
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait until rising_edge(dp_tx_aux_p);
wait for 100 us;
-- Reply with 00 01 00 00
for i in 0 to 15 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
for i in 0 to 6 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
for i in 0 to 7 loop
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 500 ns;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 500 ns;
end loop;
dp_tx_aux_p <= '1';
dp_tx_aux_n <= '0';
wait for 2000 ns;
dp_tx_aux_p <= '0';
dp_tx_aux_n <= '1';
wait for 2000 ns;
dp_tx_aux_p <= 'Z';
dp_tx_aux_n <= 'Z';
wait;
end process;
process
begin
wait for 5 ns;
clk <= '1';
wait for 5 ns;
clk <= '0';
end process;
process
begin
refclk0_p <='1';
refclk0_n <='0';
wait for 3.6 ns;
refclk0_p <='0';
refclk0_n <='1';
wait for 3.6 ns;
end process;
end architecture; | mit | c4bc5e3a738afd7eae5f2ff5f102c504 | 0.408893 | 3.394366 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/unitFIR/hdl/unitSineGen.vhd | 1 | 802 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; --try to use this library as much as possible.
entity sinewave is
port (clk :in std_logic;
dataout : out real
);
end sinewave;
architecture Behavioral of sinewave is
signal i : integer range 0 to 30:=0;
type memory_type is array (0 to 29) of real range -1.0 to 1.0;
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=(0.0,0.21,0.40,0.58,0.75,0.87,0.96,1.0,1.0,0.96,0.87,0.75,0.58,0.40,0.21,0.0,
-0.21,-0.40,-0.58,-0.75,-0.87,-0.96,-1.0,-1.0,-0.96,-0.87,-0.75,-0.58,-0.40,-0.21);
begin
process(clk)
begin
--to check the rising edge of the clock signal
if(rising_edge(clk)) then
dataout <= sine(i);
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | f504738d0c58df1867c01888ec1e2841 | 0.659601 | 2.43769 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/spartan6/gtpa1_dual_reset_controller.vhd | 1 | 6,464 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:51:54 10/02/2015
-- Design Name:
-- Module Name: gtpa1_dual_reset_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gtpa1_dual_reset_controller is
Port ( -- control signals
clk : in STD_LOGIC;
powerup_refclk : in std_logic;
powerup_pll : in std_logic;
required_pll_lock : in std_logic; -- PLL lock for the one that is driving this GTP
usrclklock : in STD_LOGIC; -- PLL lock for the USRCLK/USRCLK2 clock signals
powerup_channel : in STD_LOGIC;
tx_running : out STD_LOGIC;
-- link to GTP signals
refclken : out STD_LOGIC;
pllpowerdown : out STD_LOGIC;
plllock : in STD_LOGIC;
plllocken : out STD_LOGIC;
gtpreset : out STD_LOGIC;
txreset : out STD_LOGIC;
txpowerdown : out STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
gtpresetdone : in STD_LOGIC);
end gtpa1_dual_reset_controller;
architecture Behavioral of gtpa1_dual_reset_controller is
-- Next two are set to none-zero values to speed up simulation
signal count_pll : unsigned(15 downto 0) := (6=>'0',others => '1');
signal count_channel : unsigned(15 downto 0) := (6=>'0',others => '1'); -- enough for 120us @ 100MHz
signal pll_state : std_logic_vector(1 downto 0) := (others => '0');
signal channel_state : std_logic_vector(1 downto 0) := (others => '0');
signal gtpreset_for_pll : std_logic;
signal gtpreset_for_ch : std_logic;
begin
refclken <= powerup_refclk;
gtpreset <= gtpreset_for_pll and gtpreset_for_ch;
pll_fsm: process(clk)
begin
if rising_edge(clk) then
--------------------------------------------
-- Turn on the PLLs if either channel needed
--------------------------------------------
if count_pll(count_pll'high) = '0' then
count_pll <= count_pll + 1;
end if;
case pll_state is
when "00" => -- Disabled
pllpowerdown <= '1';
plllocken <= '0';
gtpreset_for_pll <= '1';
if powerup_pll = '1' and count_pll(count_pll'high) = '1' then
pll_state <= "01";
count_pll <= (others => '0');
end if;
when "01" => -- Power up PLLs
pllpowerdown <= '0';
plllocken <= '1';
gtpreset_for_pll <= '0';
if plllock = '1' then
pll_state <= "10";
elsif count_pll(count_pll'high) = '1' then -- timeout, so retry
pll_state <= "00";
count_pll <= (6=>'0', others => '1');
end if;
when "10" => -- PLL running - look for lost lock
pllpowerdown <= '0';
plllocken <= '1';
gtpreset_for_pll <= '0';
if plllock = '0' or powerup_pll = '0' then
pll_state <= "00";
count_pll <= (6=>'0', others => '1');
end if;
when others =>
pllpowerdown <= '1';
plllocken <= '0';
pll_state <= "00";
gtpreset_for_pll <= '1';
count_pll <= (6=>'0', others => '1');
end case;
end if;
end process;
channel_fsm: process(clk)
begin
if rising_edge(clk) then
----------------------------------------------------
-- Turn on the PLLs if either channel needs to be on
----------------------------------------------------
if count_channel(count_channel'high) = '0' then
count_channel <= count_channel + 1;
end if;
case channel_state is
when "00" => -- Disabled
tx_running <= '0';
gtpreset_for_ch <= '1';
txreset <= '1';
txpowerdown <= "11";
if powerup_channel = '1' and count_channel(count_channel'high) = '1' and required_pll_lock = '1' and usrclklock = '1' then
channel_state <= "10"; ---Note skipping looking for RESETDONE
count_channel <= (others => '0');
end if;
when "01" => -- Power up the channel
tx_running <= '0';
gtpreset_for_ch <= '0';
txreset <= '0';
txpowerdown <= "00";
if gtpresetdone = '1' then
channel_state <= "10";
count_channel <= (others => '0');
elsif count_channel(count_channel'high) = '1' or required_pll_lock = '0' or powerup_channel = '0' or usrclklock = '0' then
-- timeout, or switch the channel off
channel_state <= "00";
count_channel <= (6=>'0', others => '1');
end if;
when "10" => -- Channel up and running
tx_running <= '1';
gtpreset_for_ch <= '0';
txreset <= '0';
txpowerdown <= "00";
if required_pll_lock = '0' or powerup_channel = '0' or usrclklock = '0' then
-- Lock lost or channel to be dropped
channel_state <= "00";
count_channel <= (6=>'0', others => '1');
end if;
when others => --- error state
tx_running <= '0';
txreset <= '1';
gtpreset_for_ch <= '1';
txpowerdown <= "11";
channel_state <= "00";
count_channel <= (6=>'0', others => '1');
end case;
end if;
end process;
end Behavioral;
| mit | 689eee81a130ebe7ac8927adb582b48a | 0.429455 | 4.249836 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/insert_main_stream_attrbutes_four_channels.vhd | 1 | 14,341 | ----------------------------------------------------------------------------------
-- Module Name: insert_main_stream_attrbutes_four_channels.vhd - Behavioral
--
-- Description: Add the Main Stream Attributes into a DisplayPort stream.
--
-- Places the MSA after the first VIB-ID which has the vblank
-- bit set (after allowing for repeated VB-ID/Mvid/Maud sequences
--
-- The MSA requires up to 39 cycles (for signal channel) or
-- Only 12 cycles (for four channels).
--
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-13 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity insert_main_stream_attrbutes_four_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flag_YCC_colour_709 : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0) := (others => '0'));
end entity;
architecture arch of insert_main_stream_attrbutes_four_channels is
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
type t_msa is array(0 to 39) of std_logic_vector(8 downto 0);
signal msa : t_msa := (others => (others => '0'));
signal Misc0 : std_logic_vector(7 downto 0);
signal Misc1 : std_logic_vector(7 downto 0);
signal count : signed(4 downto 0) := (others => '0');
signal last_was_bs : std_logic := '0';
signal armed : std_logic := '0';
begin
with bits_per_colour select misc0(7 downto 5)<= "000" when "00110", -- 6 bpc
"001" when "01000", -- 8 bpp
"010" when "01010", -- 10 bpp
"011" when "01100", -- 12 bpp
"100" when "10000", -- 16 bpp
"001" when others; -- default to 8
misc0(4) <= flag_YCC_colour_709;
misc0(3) <= flag_range_reduced;
misc0(2 downto 1) <= "00" when flag_YCCnRGB = '0' else -- RGB444
"01" when flag_422n444 = '1' else -- YCC422
"10"; -- YCC444
misc0(0) <= flag_sync_clock;
misc1 <= "00000" & flags_3d_Indicators & flag_interlaced_even;
--------------------------------------------
-- Build data fields for 4 lane case.
-- SS and SE symbols are set in declaration.
--------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- default to copying the input data across
out_data <= in_data;
case count is
when "00000" => NULL; -- while waiting for BS symbol
when "00001" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00010" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00011" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00100" => out_data(17 downto 0) <= SS & SS;
when "00101" => out_data(17 downto 0) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "00110" => out_data(17 downto 0) <= "0" & "0000" & H_total(11 downto 8) & "0" & M_value( 7 downto 0);
when "00111" => out_data(17 downto 0) <= "0" & "0000" & V_total(11 downto 8) & "0" & H_total( 7 downto 0);
when "01000" => out_data(17 downto 0) <= "0" & H_vsync_active_high & "000" & H_sync_width(11 downto 8) & "0" & V_total( 7 downto 0);
when "01001" => out_data(17 downto 0) <= SE & "0" & H_sync_width(7 downto 0);
when others => NULL;
end case;
case count is
when "00000" => NULL; -- while waiting for BS symbol
when "00001" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00010" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00011" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00100" => out_data(35 downto 18) <= SS & SS;
when "00101" => out_data(35 downto 18) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "00110" => out_data(35 downto 18) <= "0" & "0000" & H_Start(11 downto 8) & "0" & M_value( 7 downto 0);
when "00111" => out_data(35 downto 18) <= "0" & "0000" & V_start(11 downto 8) & "0" & H_start( 7 downto 0);
when "01000" => out_data(35 downto 18) <= "0" & V_vsync_active_high & "000" & V_sync_width(11 downto 8) & "0" & V_start( 7 downto 0);
when "01001" => out_data(35 downto 18) <= SE & "0" & V_sync_width(7 downto 0);
when others => NULL;
end case;
case count is
when "00000" => NULL; -- while waiting for BS symbol
when "00001" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00010" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00011" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00100" => out_data(53 downto 36) <= SS & SS;
when "00101" => out_data(53 downto 36) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "00110" => out_data(53 downto 36) <= "0" & "0000" & H_visible(11 downto 8) & "0" & M_value( 7 downto 0);
when "00111" => out_data(53 downto 36) <= "0" & "0000" & V_visible(11 downto 8) & "0" & H_visible( 7 downto 0);
when "01000" => out_data(53 downto 36) <= "0" & "00000000" & "0" & V_visible( 7 downto 0);
when "01001" => out_data(53 downto 36) <= SE & "0" & "00000000";
when others => NULL;
end case;
case count is
when "00000" => NULL; -- while waiting for BS symbol
when "00001" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00010" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00011" => NULL; -- reserved for VB-ID, Maud, Mvid
when "00100" => out_data(71 downto 54) <= SS & SS;
when "00101" => out_data(71 downto 54) <= "0" & M_value(15 downto 8) & "0" & M_value(23 downto 16);
when "00110" => out_data(71 downto 54) <= "0" & N_value(23 downto 16) & "0" & M_value( 7 downto 0);
when "00111" => out_data(71 downto 54) <= "0" & N_value( 7 downto 0) & "0" & N_value(15 downto 8);
when "01000" => out_data(71 downto 54) <= "0" & Misc1 & "0" & Misc0;
when "01001" => out_data(71 downto 54) <= SE & "0" & "00000000";
when others => NULL;
end case;
-----------------------------------------------------------
-- Update the counter
------------------------------------------------------------
if count = "01010" then
count <= (others => '0');
elsif count /= "00000" then
count <= count + 1;
end if;
---------------------------------------------
-- Was the BS in the channel 0's data1 symbol
-- during the last cycle?
---------------------------------------------
if last_was_bs = '1' then
---------------------------------
-- This time in_ch0_data0 = VB-ID
-- First, see if this is a line in
-- the VSYNC
---------------------------------
if in_data(0) = '1' then
if armed = '1' then
count <= "00001";
armed <= '0';
end if;
else
-- Not in the Vblank. so arm the trigger to send the MSA
-- when the next BS with Vblank asserted occurs
armed <= active;
end if;
end if;
---------------------------------------------
-- Is the BS in the channel 0's data0 symbol?
---------------------------------------------
if in_data(8 downto 0) = BS then
---------------------------------
-- This time in_data(17 downto 9) = VB-ID
-- First, see if this is a line in
-- the VSYNC
---------------------------------
if in_data(9) = '1' then
if armed = '1' then
count <= "00001";
armed <= '0';
end if;
else
-- Not in the Vblank. so arm the trigger to send the MSA
-- when the next BS with Vblank asserted occurs
armed <= '1';
end if;
end if;
---------------------------------------------
-- Is the BS in the channel 0's data1 symbol?
---------------------------------------------
if in_data(17 downto 9) = BS then
last_was_bs <= '1';
else
last_was_bs <= '0';
end if;
end if;
end process;
end architecture;
| mit | 5a2f9ca96af7fe1a0650c5d9699ec523 | 0.42884 | 4.352352 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpEffects/unitDelay/hdl/Delay-Rtl-a.vhd | 1 | 3,900 | -------------------------------------------------------------------------------
-- Title : Signal Delay Left and Right
-- Author : Michael Wurm <[email protected]>
-------------------------------------------------------------------------------
-- Description : Unit delays left and right channel independent. Each channel's
-- delay can be configured separately.
-------------------------------------------------------------------------------
architecture Rtl of Delay is
---------------------------------------------------------------------------
-- Wires
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
signal DelayValReg : unsigned(LogDualis(gMaxDelay)-1 downto 0);
type aMemory is array (0 to gMaxDelay) of std_logic_vector(asi_data'range);
signal ramBlock : aMemory := (others => (others => '0'));
subtype aRamAddress is integer range 0 to gMaxDelay;
signal Address : aRamAddress;
signal Offset : aRamAddress;
begin
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
aso_valid <= asi_valid;
---------------------------------------------------------------------------
-- Signal assignments
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Logic
---------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Read and write RAM
------------------------------------------------------------------------------
ram_rw : process (csi_clk) is
variable readAddress : aRamAddress;
variable writeAddress : aRamAddress;
begin -- process ram_rw
if rising_edge(csi_clk) then
if Offset = 0 then -- RAM reads old value when reading and writing at the
-- same address
aso_data <= asi_data;
else
readAddress := Address;
writeAddress := (Address + Offset) mod gMaxDelay;
if asi_valid = '1' then
ramBlock(writeAddress) <= asi_data;
end if;
aso_data <= ramBlock(readAddress); --TODO: write back silence
end if;
end if;
end process ram_rw;
------------------------------------------------------------------------------
-- Address pointer logic
------------------------------------------------------------------------------
address_p : process (csi_clk, rsi_reset_n) is
begin -- process address_p
if rsi_reset_n = not('1') then -- asynchronous reset (active low)
Address <= 0;
elsif rising_edge(csi_clk) then -- rising clock edge
-- wait until data is valid
if asi_valid = '1' then
-- increase address
if Address = gMaxDelay-1 then
Address <= 0;
else
Address <= Address + 1;
end if;
end if;
end if;
end process address_p;
-- MM INTERFACE for configuration
SetConfigReg : process (csi_clk) is
begin
if rising_edge(csi_clk) then
if avs_s0_write = '1' then -- bad implementation (jumps in output signal
-- and reapeating parts when changing delay)
--readAddress <= 0;
Offset <= to_integer(unsigned(avs_s0_writedata(LogDualis(gMaxDelay)-1 downto 0)));
--TODO: scale output to 0
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Instantiations
---------------------------------------------------------------------------
end architecture Rtl;
| gpl-3.0 | 7e74f91d38cc596c156e7e0d36438e2c | 0.383333 | 5.945122 | false | false | false | false |
dimitdim/pineapple | strawberry/fpga/blk_mem_gen_v7_3.vhd | 2 | 5,482 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 43000,
c_read_depth_b => 43000,
c_read_width_a => 10,
c_read_width_b => 10,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 43000,
c_write_depth_b => 43000,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 10,
c_write_width_b => 10,
c_xdevicefamily => "spartan3"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
| gpl-2.0 | ee8a962bc2cc9d67aa31b43bed9e1e37 | 0.530463 | 3.820209 | false | false | false | false |
hamsternz/FPGA_DisplayPort | test_benches/tb_scrambler.vhd | 1 | 4,603 | ----------------------------------------------------------------------------------
-- Module Name: tb_scrambler - Behavioral
--
-- Description: A testbench for the scrambler
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_scrambler is
Port ( a : in STD_LOGIC);
end tb_scrambler;
architecture Behavioral of tb_scrambler is
component scrambler is
Port ( clk : in STD_LOGIC;
bypass0 : in STD_LOGIC;
bypass1 : in STD_LOGIC;
data0_in : in STD_LOGIC_VECTOR (7 downto 0);
data0k_in : in STD_LOGIC;
data1_in : in STD_LOGIC_VECTOR (7 downto 0);
data1k_in : in STD_LOGIC;
data0_out : out STD_LOGIC_VECTOR (7 downto 0);
data0k_out : out STD_LOGIC;
data1_out : out STD_LOGIC_VECTOR (7 downto 0);
data1k_out : out STD_LOGIC);
end component;
signal clk : STD_LOGIC := '0';
singal bypass0 : STD_LOGIC := '0';
signal data0_in : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal data0k_in : STD_LOGIC := '0';
singal bypass1 : STD_LOGIC := '0';
signal data1_in : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal data1k_in : STD_LOGIC := '0';
signal data0_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal data0k_out : STD_LOGIC := '0';
signal data1_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal data1k_out : STD_LOGIC := '0';
begin
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
uut: scrambler port map (
clk => clk,
bypass0 => bypass0,
bypass1 => bypass1,
data0_in => data0_in,
data0k_in => data0k_in,
data1_in => data1_in,
data1k_in => data1k_in,
data0_out => data0_out,
data0k_out => data0k_out,
data1_out => data1_out,
data1k_out => data1k_out);
end Behavioral;
| mit | 249c7f7e91ec42296605aa1d6b46cd66 | 0.527917 | 4.117174 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstrom/tstrom_archConfigPkg.vhd | 9 | 1,871 | ------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
| bsd-3-clause | 578e0f5bf3f8fc6e5b35340fab7ae70a | 0.542491 | 4.497596 | false | true | false | false |
ASP-SoC/ASP-SoC | libASP/grpEffects/unitDelay/hdl/Delay_tb.vhd | 1 | 4,091 | -------------------------------------------------------------------------------
-- Title : Testbench for design "Delay"
-- Project :
-------------------------------------------------------------------------------
-- File : Delay_tb.vhd
-- Author : free-hat <free_hat@freehat-Ultrabook>
-- Company :
-- Created : 2017-11-14
-- Last update: 2017-11-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-11-14 1.0 free_hat Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity Delay_tb is
end entity Delay_tb;
-------------------------------------------------------------------------------
architecture bhv of Delay_tb is
-- component generics
constant gMaxDelay : natural := 1024;
constant gDataWidth : natural := 24;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal avs_s0_write : std_logic;
signal avs_s0_writedata : std_logic_vector(31 downto 0);
signal asi_data : std_logic_vector(gDataWidth-1 downto 0);
signal asi_valid : std_logic;
signal aso_data : std_logic_vector(gDataWidth-1 downto 0);
signal aso_valid : std_logic;
begin -- architecture bhv
-- component instantiation
DUT: entity work.Delay
generic map (
gMaxDelay => gMaxDelay,
gDataWidth => gDataWidth)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
avs_s0_write => avs_s0_write,
avs_s0_writedata => avs_s0_writedata,
asi_data => asi_data,
asi_valid => asi_valid,
aso_data => aso_data,
aso_valid => aso_valid);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
rsi_reset_n <= '0';
avs_s0_write <= '0';
avs_s0_writedata <= std_logic_vector(to_unsigned(10,avs_s0_writedata'length));
asi_data <= (others => '0');
--asi_valid <= '0';
wait for 100 ns;
rsi_reset_n <= '1';
wait for 50 ns;
avs_s0_write <= '1';
wait for 50 ns;
avs_s0_write <= '0';
wait for 50 ns;
asi_data <= (others => '1');
wait for 30 ms;
avs_s0_writedata <= std_logic_vector(to_unsigned(1,avs_s0_writedata'length));
avs_s0_write <= '1';
wait for 20 ns;
avs_s0_write <= '0';
asi_data <= (others => '0');
wait for 10 ms;
avs_s0_writedata <= std_logic_vector(to_unsigned(0,avs_s0_writedata'length));
avs_s0_write <= '1';
wait for 20 ns;
avs_s0_write <= '0';
asi_data <= (others => '1');
wait for 10 ms;
avs_s0_writedata <= std_logic_vector(to_unsigned(gMaxDelay-1,avs_s0_writedata'length));
avs_s0_write <= '1';
wait for 20 ns;
avs_s0_write <= '0';
asi_data <= (others => '0');
wait for 20 ms;
wait;
end process WaveGen_Proc;
-- purpose: generate a valid signal every 1/48kHz
-- type : combinational
-- inputs :
-- outputs: asi_valid
valid_48khz: process is
begin -- process valid_48khz
wait until csi_clk = '0';
asi_valid <= '1';
wait until csi_clk = '1';
wait until csi_clk = '0';
asi_valid <= '0';
wait for 20 us;
end process valid_48khz;
end architecture bhv;
-------------------------------------------------------------------------------
configuration Delay_tb_bhv_cfg of Delay_tb is
for bhv
end for;
end Delay_tb_bhv_cfg;
-------------------------------------------------------------------------------
| gpl-3.0 | ea6a976f3f8f886f0f091391cae380bb | 0.470301 | 3.86673 | false | false | false | false |
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