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tommylommykins/logipi-midi-player | hdl/utils.vhd | 1 | 1,544 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package utils is
type ctrl_t is record
clk : std_logic;
reset_n : std_logic;
end record;
function calc_delay_clocks(clock_period : in time;
delay_length : in time) return integer;
function sync_rising_edge(signal sig_d1 : std_logic;
signal sig : std_logic) return std_logic;
function to_slv(c : character) return std_logic_vector;
-- Convert an ascii string to its slv representation.
function to_slv(s : string) return std_logic_vector;
end;
package body utils is
function calc_delay_clocks(clock_period : in time;
delay_length : in time) return integer is
begin
return delay_length / clock_period;
end;
function sync_rising_edge(signal sig_d1 : std_logic;
signal sig : std_logic) return std_logic is
begin
if (sig_d1 = '0') and (sig = '1') then
return '1';
else
return '0';
end if;
end;
function to_slv(c : character) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(character'pos(c), 8));
end;
-- Convert an ascii string to its slv representation.
function to_slv(s : string) return std_logic_vector is
variable ret : std_logic_vector((s'length * 8) - 1 downto 0) := (others => '0');
begin
for i in s'left to s'right loop
ret := ret(ret'left - 8 downto 0) & to_slv(s(i));
end loop;
return ret;
end;
end;
| bsd-2-clause | 609b5e3611f07abda5394e8346ed2c15 | 0.612047 | 3.557604 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/ovl_cycle_sequence_rtl.vhd | 1 | 10,470 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_cycle_sequence is
constant assert_name : string := "OVL_CYCLE_SEQUENCE";
constant path : string := rtl'path_name;
constant trig_on_most_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_MOST_PIPE);
constant trig_on_first_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_PIPE);
constant trig_on_first_nopipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_NOPIPE);
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal event_sequence_x01 : std_logic_vector(num_cks - 1 downto 0);
signal seq_queue : std_logic_vector(num_cks - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
event_sequence_x01 <= to_x01(event_sequence);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Shared logic --
------------------------------------------------------------------------------
ovl_seq_queue_gen : if (ovl_2state_is_on(controls, property_type) or
((controls.cover_ctrl = OVL_ON) and (coverage_level_ctrl /= OVL_COVER_NONE))) generate
ovl_seq_queue_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
seq_queue <= (others => '0');
else
if (trig_on_first_nopipe) then
seq_queue(num_cks - 1) <= not(or_reduce(seq_queue(num_cks - 1 downto 1))) and
event_sequence_x01(num_cks - 1);
else
seq_queue(num_cks - 1) <= event_sequence_x01(num_cks - 1);
end if;
seq_queue(num_cks - 2 downto 0) <= seq_queue(num_cks - 1 downto 1) and
event_sequence_x01(num_cks - 2 downto 0);
end if;
end if;
end process ovl_seq_queue_p;
end generate ovl_seq_queue_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
else
fire(0) <= '0';
if (trig_on_first_pipe or trig_on_first_nopipe) then
if (and_reduce((seq_queue(num_cks -1 downto 1) and event_sequence_x01(num_cks - 2 downto 0)) or
not(seq_queue(num_cks -1 downto 1))) = '0') then
fire(0) <= '1';
ovl_error_proc("First event occured but it is not followed by the rest of the events in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
else -- trig_on_most_pipe
if ((not(seq_queue(1)) or (seq_queue(1) and event_sequence_x01(0))) = '0') then
fire(0) <= '1';
ovl_error_proc("First num_cks-1 events occured but they are not followed by the last event in sequence",
severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
function init_valid_sequence_gate return std_logic_vector is
variable set : std_logic_vector(num_cks - 2 downto 0);
begin
if (num_cks > 2) then
set(num_cks - 2 downto 1) := (others => '1');
end if;
if (trig_on_most_pipe) then set(0) := '0'; else set(0) := '1'; end if;
return set;
end function init_valid_sequence_gate;
variable valid_first_event : std_logic;
variable valid_sequence : std_logic;
variable valid_last_event : std_logic;
constant valid_sequence_gate : std_logic_vector(num_cks - 2 downto 0) := init_valid_sequence_gate;
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
valid_first_event := event_sequence_x01(num_cks - 1);
valid_last_event := seq_queue(1) and event_sequence_x01(0);
valid_sequence := xor_reduce(seq_queue(num_cks - 1 downto 1) and event_sequence_x01(num_cks - 2 downto 0) and
valid_sequence_gate);
if (reset_n = '0') then
fire(1) <= '0';
else
fire(1) <= '0';
if (ovl_is_x(valid_first_event)) then
if (trig_on_most_pipe or trig_on_first_pipe) then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
elsif (not(or_reduce(seq_queue(num_cks - 1 downto 1))) = '1') then
fire(1) <= '1';
ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (ovl_is_x(valid_sequence)) then
if (trig_on_first_pipe or trig_on_first_nopipe) then
fire(1) <= '1';
ovl_error_proc("Subsequent events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
if (trig_on_most_pipe) then
if (ovl_is_x(valid_last_event)) then
if (seq_queue(1) = '1') then
fire(1) <= '1';
ovl_error_proc("Last event in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '1';
ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
end if;
end if;
end if;
end if; -- reset_n = '0'
end if; -- rising_edge(clk)
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (((trig_on_first_pipe or trig_on_first_nopipe) and (event_sequence_x01(num_cks - 1) = '1')) or
(trig_on_most_pipe and (seq_queue(1) = '1'))) then
fire(2) <= '1';
ovl_cover_proc("sequence_trigger covered", assert_name, path, controls, cover_count);
else
fire(2) <= '0';
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or not cover_basic) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit | 2c400d942f2993ee2cfe5bb2e854b28f | 0.491691 | 3.928705 | false | false | false | false |
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II | MaterialDeAuxilo/MIPS-MC_SingleEdge/MIPS-MC_SingleEdge_tb.vhd | 1 | 14,147 | -------------------------------------------------------------------------
--
-- 32 bits PROCESSOR TESTBENCH LITTLE ENDIAN 13/october/2004
--
-- It must be observed that the processor is hold in reset
-- (rstCPU <= '1') at the start of simulation, being activated
-- (rstCPU <= '0') just after the end of the object file reading be the
-- testbench.
--
-- This testbench employs two memories, implying a HARVARD organization
--
-- Changes:
-- 16/05/2012 (Ney Calazans)
-- - Corrected bug in memory filling during reset. The instruction
-- memory fill process, makes the processor produce "ce" signals to
-- memory which ended up by filling data memory with rubbish at
-- the same time. To solve this, the first line of the data memory
-- Dce control signal generation was changed from
-- -- ce='1' or go_d='1' to
-- -- (ce='1' and rstCPU/='1') or go_d='1'
-- - Also, there was a problem with the data memory write operation in
-- monocycle MIPS implementations: when multiple SW instructions
-- were issued one after the other, the write operation was executed
-- in two sets of memory positions at once after the first SW. To
-- solve this the data signal was removed from the memory write
-- process sensitivity list.
-- 10/10/2015 (Ney Calazans)
-- - Signal bw from memory set to '1', since the CPU
-- does not generate it anymore.
-- 28/10/2016 (Ney Calazans)
-- - Also, regX defs were changed to wiresX, to improve
-- code readability.
-- 02/06/2017 (Ney Calazans) - bugfix
-- - tmp_address changed to int_address in the memory definition
-- -IN the definition of the memory read/write processes,
-- CONV_INTEGER(low_address+3)<=MEMORY_SIZE was changed to
-- CONV_INTEGER(low_address)<=MEMORY_SIZE-3
-- This avoids an error that freezes the simulation when the
-- ALU contains a large number (>65533) in its output
-- immediately before an LW or SW instruction.
-------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use std.textio.all;
package aux_functions is
subtype wires32 is std_logic_vector(31 downto 0);
subtype wires16 is std_logic_vector(15 downto 0);
subtype wires8 is std_logic_vector( 7 downto 0);
subtype wires4 is std_logic_vector( 3 downto 0);
-- definição do tipo 'memory', que será utilizado para as memórias de dados/instruções
constant MEMORY_SIZE : integer := 2048;
type memory is array (0 to MEMORY_SIZE) of wires8;
constant TAM_LINHA : integer := 200;
function CONV_VECTOR( letra : string(1 to TAM_LINHA); pos: integer ) return std_logic_vector;
procedure readFileLine(file in_file: TEXT; outStrLine: out string);
end aux_functions;
package body aux_functions is
--
-- converte um caracter de uma dada linha em um std_logic_vector
--
function CONV_VECTOR( letra:string(1 to TAM_LINHA); pos: integer ) return std_logic_vector is
variable bin: wires4;
begin
case (letra(pos)) is
when '0' => bin := "0000";
when '1' => bin := "0001";
when '2' => bin := "0010";
when '3' => bin := "0011";
when '4' => bin := "0100";
when '5' => bin := "0101";
when '6' => bin := "0110";
when '7' => bin := "0111";
when '8' => bin := "1000";
when '9' => bin := "1001";
when 'A' | 'a' => bin := "1010";
when 'B' | 'b' => bin := "1011";
when 'C' | 'c' => bin := "1100";
when 'D' | 'd' => bin := "1101";
when 'E' | 'e' => bin := "1110";
when 'F' | 'f' => bin := "1111";
when others => bin := "0000";
end case;
return bin;
end CONV_VECTOR;
procedure readFileLine(file in_file: TEXT;
outStrLine: out string) is
variable localLine: line;
variable localChar: character;
variable isString: boolean;
begin
readline(in_file, localLine);
for i in outStrLine'range loop
outStrLine(i) := ' ';
end loop;
for i in outStrLine'range loop
read(localLine, localChar, isString);
outStrLine(i) := localChar;
if not isString then -- found end of line
exit;
end if;
end loop;
end readFileLine;
end aux_functions;
--------------------------------------------------------------------------
-- Module implementing a behavioral model of an ASYNCHRONOUS INTERFACE RAM
--------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use std.textio.all;
use work.aux_functions.all;
entity RAM_mem is
generic( START_ADDRESS: wires32 := (others=>'0') );
port( ce_n, we_n, oe_n, bw: in std_logic; address: in wires32; data: inout wires32);
end RAM_mem;
architecture RAM_mem of RAM_mem is
signal RAM : memory;
signal tmp_address: wires32;
alias low_address: wires16 is tmp_address(15 downto 0); -- baixa para 16 bits devido ao CONV_INTEGER --
begin
tmp_address <= address - START_ADDRESS; -- offset do endereçamento --
-- writes in memory ASYNCHRONOUSLY -- LITTLE ENDIAN -------------------
process(ce_n, we_n, low_address) -- Modification in 16/05/2012 for monocycle processors only,
begin
if ce_n='0' and we_n='0' then
if CONV_INTEGER(low_address)>=0 and CONV_INTEGER(low_address)<=MEMORY_SIZE-3 then
if bw='1' then
RAM(CONV_INTEGER(low_address+3)) <= data(31 downto 24);
RAM(CONV_INTEGER(low_address+2)) <= data(23 downto 16);
RAM(CONV_INTEGER(low_address+1)) <= data(15 downto 8);
end if;
RAM(CONV_INTEGER(low_address )) <= data( 7 downto 0);
end if;
end if;
end process;
-- read from memory
process(ce_n, oe_n, low_address)
begin
if ce_n='0' and oe_n='0' and
CONV_INTEGER(low_address)>=0 and CONV_INTEGER(low_address)<=MEMORY_SIZE-3 then
data(31 downto 24) <= RAM(CONV_INTEGER(low_address+3));
data(23 downto 16) <= RAM(CONV_INTEGER(low_address+2));
data(15 downto 8) <= RAM(CONV_INTEGER(low_address+1));
data( 7 downto 0) <= RAM(CONV_INTEGER(low_address ));
else
data(31 downto 24) <= (others=>'Z');
data(23 downto 16) <= (others=>'Z');
data(15 downto 8) <= (others=>'Z');
data( 7 downto 0) <= (others=>'Z');
end if;
end process;
end RAM_mem;
-------------------------------------------------------------------------
-- CPU PROCESSOR SIMULATION TESTBENCH
-------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use STD.TEXTIO.all;
use work.aux_functions.all;
entity CPU_tb is
end CPU_tb;
architecture cpu_tb of cpu_tb is
signal Dadress, Ddata, Iadress, Idata,
i_cpu_address, d_cpu_address, data_cpu, tb_add, tb_data : wires32 := (others => '0' );
signal Dce_n, Dwe_n, Doe_n, Ice_n, Iwe_n, Ioe_n, ck, rst, rstCPU,
go_i, go_d, ce, rw, bw: std_logic;
file ARQ : TEXT open READ_MODE is "Test_Program_Allinst_MIPS_MCS.txt";
begin
Data_mem: entity work.RAM_mem
generic map( START_ADDRESS => x"10010000" )
port map (ce_n=>Dce_n, we_n=>Dwe_n, oe_n=>Doe_n, bw=>bw, address=>Dadress, data=>Ddata);
Instr_mem: entity work.RAM_mem
generic map( START_ADDRESS => x"00400000" )
port map (ce_n=>Ice_n, we_n=>Iwe_n, oe_n=>Ioe_n, bw=>'1', address=>Iadress, data=>Idata);
-- data memory signals --------------------------------------------------------
Dce_n <= '0' when (ce='1' and rstCPU/='1') or go_d='1' else '1'; -- Bug corrected here in 16/05/2012
Doe_n <= '0' when (ce='1' and rw='1') else '1';
Dwe_n <= '0' when (ce='1' and rw='0') or go_d='1' else '1';
Dadress <= tb_add when rstCPU='1' else d_cpu_address;
Ddata <= tb_data when rstCPU='1' else data_cpu when (ce='1' and rw='0') else (others=>'Z');
data_cpu <= Ddata when (ce='1' and rw='1') else (others=>'Z');
-- instructions memory signals --------------------------------------------------------
Ice_n <= '0';
Ioe_n <= '1' when rstCPU='1' else '0'; -- impede leitura enquanto está escrevendo
Iwe_n <= '0' when go_i='1' else '1'; -- escrita durante a leitura do arquivo
Iadress <= tb_add when rstCPU='1' else i_cpu_address;
Idata <= tb_data when rstCPU='1' else (others => 'Z');
cpu: entity work.MIPS_MCS port map(
clock=>ck, reset=>rstCPU,
i_address => i_cpu_address,
instruction => Idata,
ce=>ce, rw=>rw, bw=>bw,
d_address => d_cpu_address,
data => data_cpu
);
rst <='1', '0' after 15 ns; -- generates the reset signal
process -- generates the clock signal
begin
ck <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
----------------------------------------------------------------------------
-- this process loads the instruction memory and the data memory during reset
--
--
-- O PROCESSO ABAIXO É UMA PARSER PARA LER CÓDIGO GERADO PELO SPIM NO
-- SEGUINTE FORMATO:
--
-- Text Segment
-- [0x00400000] 0x3c011001 lui $1, 4097 [d2] ; 16: la $t0, d2
-- [0x00400004] 0x34280004 ori $8, $1, 4 [d2]
-- [0x00400008] 0x8d080000 lw $8, 0($8) ; 17: lw $t0,0($t0)
-- .....
-- [0x00400048] 0x0810000f j 0x0040003c [loop] ; 30: j loop
-- [0x0040004c] 0x01284821 addu $9, $9, $8 ; 32: addu $t1, $t1, $t0
-- [0x00400050] 0x08100014 j 0x00400050 [x] ; 34: j x
-- Data Segment
-- [0x10010000] 0x0000faaa 0x00000083 0x00000000 0x00000000
--
----------------------------------------------------------------------------
process
variable ARQ_LINE : LINE;
variable line_arq : string(1 to TAM_LINHA);
variable code : boolean;
variable i, address_flag : integer;
begin
go_i <= '0';
go_d <= '0';
rstCPU <= '1'; -- hold the processor during file reading
code:=true; -- default value of code is 1 (CODE)
wait until rst = '1';
while NOT (endfile(ARQ)) loop -- INÍCIO DA LEITURA DO ARQUIVO CONTENDO INSTRUÇÃO E DADOS -----
--readline(ARQ, ARQ_LINE);
--read(ARQ_LINE, line_arq(1 to ARQ_LINE'length) );
readFileLine(ARQ, line_arq);
if line_arq(1 to 12)="Text Segment" then
code:=true; -- code
elsif line_arq(1 to 12)="Data Segment" then
code:=false; -- data
else
i := 1; -- LEITORA DE LINHA - analizar o loop abaixo para compreender
address_flag := 0; -- para INSTRUÇÃO é um para (end,inst)
-- para DADO aceita (end, dado 0, dado 1, dado 2 ....)
loop
if line_arq(i) = '0' and line_arq(i+1) = 'x' then -- encontrou indicação de número hexa: '0x'
i := i + 2;
if address_flag=0 then
for w in 0 to 7 loop
tb_add( (31-w*4) downto (32-(w+1)*4)) <= CONV_VECTOR(line_arq,i+w);
end loop;
i := i + 8;
address_flag := 1;
else
for w in 0 to 7 loop
tb_data( (31-w*4) downto (32-(w+1)*4)) <= CONV_VECTOR(line_arq,i+w);
end loop;
i := i + 8;
wait for 0.1 ns;
if code=true then go_i <= '1'; -- the go_i signal enables instruction memory writing
else go_d <= '1'; -- the go_d signal enables data memory writing
end if;
wait for 0.1 ns;
tb_add <= tb_add + 4; -- *great!* consigo ler mais de uma word por linha!
go_i <= '0';
go_d <= '0';
address_flag := 2; -- sinaliza que já leu o conteúdo do endereço;
end if;
end if;
i := i + 1;
-- sai da linha quando chegou no seu final OU já leu par(endereço, instrução) no caso de código
exit when i=TAM_LINHA or (code=true and address_flag=2);
end loop;
end if;
end loop; -- FINAL DA LEITURA DO ARQUIVO CONTENDO INSTRUÇÃO E DADOS -----
rstCPU <= '0' after 2 ns; -- release the processor to execute
wait for 4 ns; -- To activate the RST CPU signal
wait until rst = '1'; -- to Hold again!
end process;
end cpu_tb;
| mit | e79b6a7e0f3b24e95b1865cab40dfc9d | 0.485898 | 3.828687 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/uart_rx.vhd | 3 | 2,290 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_RX is
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
CE_16 : in std_logic; -- 16 times baud rate
SER_IN : in std_logic; -- Serial input line
DATA : out std_logic_vector(7 downto 0);
DATA_FLAG : out std_logic -- toggle on every byte received
);
end UART_RX;
architecture RX_UART_arch of UART_RX is
signal POSITION : std_logic_vector(7 downto 0); -- sample position
signal BUF : std_logic_vector(9 downto 0);
signal LDATA_FLAG : std_logic;
signal SER_IN1 : std_logic; -- double clock the input
signal SER_HOT : std_logic; -- double clock the input
begin
-- double clock the input data...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
SER_IN1 <= '1';
SER_HOT <= '1';
else
SER_IN1 <= SER_IN;
SER_HOT <= SER_IN1;
end if;
end if;
end process;
DATA_FLAG <= LDATA_FLAG;
process(CLK_I, POSITION)
variable START_BIT : boolean;
variable STOP_BIT : boolean;
variable STOP_POS : boolean;
begin
START_BIT := POSITION(7 downto 4) = X"0";
STOP_BIT := POSITION(7 downto 4) = X"9";
STOP_POS := STOP_BIT and POSITION(3 downto 2) = "11"; -- 3/4 of stop bit
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
LDATA_FLAG <= '0';
POSITION <= X"00"; -- idle
BUF <= "1111111111";
DATA <= "00000000";
elsif (CE_16 = '1') then
if (POSITION = X"00") then -- uart idle
BUF <= "1111111111";
if (SER_HOT = '0') then -- start bit received
POSITION <= X"01";
end if;
else
POSITION <= POSITION + X"01";
if (POSITION(3 downto 0) = "0111") then -- 1/2 of the bit
BUF <= SER_HOT & BUF(9 downto 1); -- sample data
-- validate start bit
--
if (START_BIT and SER_HOT = '1') then -- inside start bit
POSITION <= X"00";
end if;
if (STOP_BIT) then -- inside stop bit
DATA <= BUF(9 downto 2);
end if;
elsif (STOP_POS) then -- 3/4 of stop bit
LDATA_FLAG <= LDATA_FLAG xor (BUF(9) and not BUF(0));
POSITION <= X"00";
end if;
end if;
end if;
end if;
end process;
end RX_UART_arch;
| mit | 187e74d8d99ee6ab054972a9f8c6a637 | 0.567686 | 2.820197 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/midi/track_decoder.vhd | 1 | 12,283 | library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.midi_pkg.all;
entity track_decoder is
generic(
max_read_bytes : integer
);
port(
ctrl : in ctrl_t;
midi_pulses : in midi_pulse_arr;
midi_pulse_acks : out midi_pulse_arr;
playing_en : in std_logic;
chunk_data : in chunk_data_t_arr;
num_chunks : in integer range 0 to max_num_tracks - 1;
-- ram read interface
read_start_addr : out unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0) := (others => '0');
read_num_bytes : out integer range 0 to max_read_bytes;
read_en : out std_logic;
read_busy : in std_logic;
midi_ram_out : in std_logic_vector((max_read_bytes * 8) - 1 downto 0);
midi_nos : out midi_note_arr_t
);
end;
architecture rtl of track_decoder is
constant read_addr_length : integer := integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1;
type internals_t is record
first_event : std_logic;
read_start_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
status : std_logic_vector(7 downto 0);
last_byte_was_status : std_logic;
unknown_midi_event : std_logic;
midi_no : midi_note_t;
volume : unsigned(7 downto 0);
delta_counter : unsigned(27 downto 0);
end record;
type internals_t_arr is array(1 to max_num_tracks - 1) of internals_t;
signal internals : internals_t_arr;
signal current_internal : internals_t;
type state_t is (
wait_en,
init_read_addrs_1,
init_read_addrs_2,
read_variable_length_1,
read_variable_length_2,
read_variable_length_3,
apply_delta_time,
wait_delta_time_and_cede_control,
wait_delta_time_and_cede_control_delay,
increment_current_internal_1,
increment_current_internal_2,
read_status_1,
read_status_2,
read_status_3,
dispatch_event,
dispatch_meta_1,
dispatch_meta_2,
skip_over_meta_event_1,
skip_over_meta_event_2,
read_note_on_1,
read_note_on_2,
read_note_on_3,
read_note_on_4,
done,
error_state
);
signal state : state_t;
signal return_state : state_t;
signal read_num_bytes_int : integer range 0 to max_read_bytes;
signal variable_length : unsigned(27 downto 0);
signal current_track : integer range 1 to max_num_tracks - 1;
signal read_busy_d1 : std_logic;
-----------------------------------------------------------------------------
-- Enumeration of known events
constant meta_event : std_logic_vector(7 downto 0) := x"FF";
constant note_on_event : std_logic_vector(3 downto 0) := x"9";
constant end_of_track : std_logic_vector(7 downto 0) := x"2F";
constant track_name : std_logic_vector(7 downto 0) := x"03";
constant prefix_port : std_logic_vector(7 downto 0) := x"21";
begin
delay_read_busy : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_busy_d1 <= read_busy;
end if;
end process;
fsm : process(ctrl.clk)
procedure increment_current_track is
begin
if current_track = num_chunks then
current_track <= 1;
else
current_track <= current_track + 1;
end if;
end;
impure function ram_read_finished return boolean is
begin
return read_busy = '0' and read_busy_d1 = '1';
end;
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
internals <= (
others => (
first_event => '1',
read_start_addr => (others => '0'),
status => (others => '0'),
last_byte_was_status => '0',
unknown_midi_event => '0',
midi_no => midi_note_t'low,
volume => (others => '0'),
delta_counter => (others => '0')
));
current_internal <= (
first_event => '1',
read_start_addr => (others => '0'),
status => (others => '0'),
last_byte_was_status => '0',
unknown_midi_event => '0',
midi_no => midi_note_t'low,
volume => (others => '0'),
delta_counter => (others => '0')
);
state <= wait_en;
return_state <= error_state;
variable_length <= (others => '0');
read_en <= '0';
current_track <= 1;
for i in 1 to max_num_tracks - 1 loop
midi_pulse_acks(i) <= '0';
end loop;
else
case state is
when wait_en =>
if playing_en = '1' then
state <= init_read_addrs_1;
end if;
when init_read_addrs_1 =>
for i in internals'range loop
internals(i).read_start_addr <= chunk_data(i).base_addr + 8;
end loop;
state <= init_read_addrs_2;
when init_read_addrs_2 =>
current_internal <= internals(current_track);
return_state <= apply_delta_time;
state <= read_variable_length_1;
when read_variable_length_1 =>
variable_length <= (others => '0');
state <= read_variable_length_2;
when read_variable_length_2 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= read_variable_length_3;
when read_variable_length_3 =>
read_en <= '0';
if ram_read_finished then
variable_length <= variable_length(variable_length'left - 7 downto 0) & unsigned(midi_ram_out(6 downto 0));
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
if midi_ram_out(7) = '1' then
state <= read_variable_length_2;
else
state <= return_state;
end if;
end if;
when apply_delta_time =>
current_internal.delta_counter <= variable_length;
state <= wait_delta_time_and_cede_control;
when wait_delta_time_and_cede_control =>
midi_pulse_acks(current_track) <= '0';
if current_internal.delta_counter = 0 then
state <= read_status_1;
elsif midi_pulses(current_track) = '1' then
current_internal.delta_counter <= current_internal.delta_counter - 1;
midi_pulse_acks(current_track) <= '1';
state <= wait_delta_time_and_cede_control_delay;
else
-- Now we are switching midi track, so we must put the current
-- track back in storage and get another one out.
internals(current_track) <= current_internal;
internals(current_track).first_event <= '0';
state <= increment_current_internal_1;
increment_current_track;
end if;
-- This state prevents the delta counters from accidentally double
-- decrementing.
when wait_delta_time_and_cede_control_delay =>
state <= wait_delta_time_and_cede_control;
when increment_current_internal_1 =>
current_internal <= internals(current_track);
state <= increment_current_internal_2;
when increment_current_internal_2 =>
if current_internal.first_event = '1' then
state <= read_variable_length_1;
return_state <= apply_delta_time;
else
state <= wait_delta_time_and_cede_control;
end if;
when read_status_1 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= read_status_2;
when read_status_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
--here we implement the running status
if midi_ram_out(7) = '1' then
current_internal.status <= midi_ram_out(7 downto 0);
current_internal.last_byte_was_status <= '1';
else
current_internal.last_byte_was_status <= '0';
end if;
state <= dispatch_event;
end if;
-- If last_byte_was_status = '1', then the last byte we read from
-- ram was a data byte, If last_byte_was_status = '0', then that
-- data byte was read and the pointer is looking at the next data
-- byte.
--
-- To remove confusion, in this state, we subtract 1 from the ram
-- read pointer to unify that situation and make sure that the read
-- pointer is at the first data byte.
when dispatch_event =>
if current_internal.last_byte_was_status = '0' then
current_internal.read_start_addr <= current_internal.read_start_addr - 1;
end if;
if current_internal.status = meta_event then
state <= dispatch_meta_1;
elsif current_internal.status(7 downto 4) = note_on_event then
state <= read_note_on_1;
else
current_internal.unknown_midi_event <= '1';
state <= error_state;
end if;
when dispatch_meta_1 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= dispatch_meta_2;
when dispatch_meta_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
if midi_ram_out(7 downto 0) = end_of_track then
state <= done;
elsif midi_ram_out(7 downto 0) = track_name or
midi_ram_out(7 downto 0) = prefix_port then
state <= skip_over_meta_event_1;
else
state <= error_state;
end if;
end if;
when skip_over_meta_event_1 =>
state <= read_variable_length_1;
return_state <= skip_over_meta_event_2;
when skip_over_meta_event_2 =>
current_internal.read_start_addr <= current_internal.read_start_addr +
resize(variable_length, read_addr_length);
state <= read_variable_length_1;
return_state <= apply_delta_time;
when read_note_on_1 =>
read_en <= '1';
read_num_bytes_int <= 2;
state <= read_note_on_2;
when read_note_on_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
current_internal.midi_no <= to_integer(unsigned(midi_ram_out(15 downto 8)));
midi_nos(current_track - 1) <= to_integer(unsigned(midi_ram_out(15 downto 8)));
current_internal.volume <= unsigned(midi_ram_out(7 downto 0));
state <= read_variable_length_1;
return_state <= apply_delta_time;
end if;
when done =>
increment_current_track;
null;
when error_state =>
null;
when others =>
null;
end case;
end if;
end if;
end process;
-- mux the read address output
read_start_addr <= current_internal.read_start_addr;
read_num_bytes <= read_num_bytes_int;
end architecture;
| bsd-2-clause | 4ef449320a0bb082c65b36dc34f244ea | 0.518766 | 3.905564 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/uart_rx.vhd | 1 | 2,286 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_RX is
PORT( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : in std_logic; -- 16 times baud rate
SER_IN : in std_logic; -- Serial input line
DATA : out std_logic_vector(7 downto 0);
DATA_FLAG : out std_logic -- toggle on every byte received
);
end UART_RX;
architecture RX_UART_arch of UART_RX is
signal POSITION : std_logic_vector(7 downto 0); -- sample position
signal BUF : std_logic_vector(9 downto 0);
signal LDATA_FLAG : std_logic;
signal SER_IN1 : std_logic; -- double clock the input
signal SER_HOT : std_logic; -- double clock the input
begin
-- double clock the input data...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
SER_IN1 <= '1';
SER_HOT <= '1';
else
SER_IN1 <= SER_IN;
SER_HOT <= SER_IN1;
end if;
end if;
end process;
DATA_FLAG <= LDATA_FLAG;
process(CLK_I, POSITION)
variable START_BIT : boolean;
variable STOP_BIT : boolean;
variable STOP_POS : boolean;
begin
START_BIT := POSITION(7 downto 4) = X"0";
STOP_BIT := POSITION(7 downto 4) = X"9";
STOP_POS := STOP_BIT and POSITION(3 downto 2) = "11"; -- 3/4 of stop bit
if (rising_edge(CLK_I)) then
if (CLR = '1') then
LDATA_FLAG <= '0';
POSITION <= X"00"; -- idle
BUF <= "1111111111";
DATA <= "00000000";
elsif (CE_16 = '1') then
if (POSITION = X"00") then -- uart idle
BUF <= "1111111111";
if (SER_HOT = '0') then -- start bit received
POSITION <= X"01";
end if;
else
POSITION <= POSITION + X"01";
if (POSITION(3 downto 0) = "0111") then -- 1/2 of the bit
BUF <= SER_HOT & BUF(9 downto 1); -- sample data
-- validate start bit
--
if (START_BIT and SER_HOT = '1') then -- inside start bit
POSITION <= X"00";
end if;
if (STOP_BIT) then -- inside stop bit
DATA <= BUF(9 downto 2);
end if;
elsif (STOP_POS) then -- 3/4 of stop bit
LDATA_FLAG <= LDATA_FLAG xor (BUF(9) and not BUF(0));
POSITION <= X"00";
end if;
end if;
end if;
end if;
end process;
end RX_UART_arch;
| mit | caca8b78e41bd7ac0b19957d563c2a9d | 0.567367 | 2.836228 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_32_32.vhd | 1 | 57,406 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_32_32.vhd
-- /___/ /\ Timestamp: Wed Jul 16 13:57:38 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_32.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_32_32
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_32_32 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end fifo_generator_32_32;
architecture STRUCTURE of fifo_generator_32_32 is
signal N0 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_66 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_70 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_72 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_75 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44;
XST_GND : GND
port map (
G => N0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_72,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_72
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_66
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_75
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_70,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_74
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_65,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_70
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_71,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_73,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_75,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_64,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_66,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => N22
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I4 => N22,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb82 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93 : LUT6
generic map(
INIT => X"FFFFFFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000142 : LUT6
generic map(
INIT => X"D4C4C4C4DCCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182 : LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000232 : LUT6
generic map(
INIT => X"EEAAECA8AAAAA8A8"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb132 : LUT6
generic map(
INIT => X"FF44FF0444440404"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_63,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2 : LUT4
generic map(
INIT => X"0C04"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP :
RAMB18SDP
generic map(
DO_REG => 0,
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
SRVAL => X"000000000"
)
port map (
RDCLK => clk,
WRCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
REGCE => N0,
SSR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDADDR(8) => N0,
RDADDR(7) => N0,
RDADDR(6) => N0,
RDADDR(5) => N0,
RDADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
WRADDR(8) => N0,
WRADDR(7) => N0,
WRADDR(6) => N0,
WRADDR(5) => N0,
WRADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED
,
WE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | e48098fa22618ca568d9d0d2549532be | 0.667944 | 2.731668 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_range.vhd | 1 | 1,268 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_range is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
min : natural := 0;
max : natural := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_range;
| mit | 5fb093486f195b88e991d73618dce758 | 0.537855 | 3.464481 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/bin_to_7segment.vhd | 1 | 3,865 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bin_to_7segment is
Port( CLK_I : in std_logic;
T2 : in std_logic;
PC : in std_logic_vector(15 downto 0);
SEG1 : out std_logic_vector(7 downto 1);
SEG2 : out std_logic_vector(7 downto 0));
end bin_to_7segment;
architecture Behavioral of bin_to_7segment is
-- +------- middle upper
-- |+------- right upper
-- ||+------ right lower
-- |||+----- middle lower
-- ||||+---- left lower
-- |||||+--- left upper
-- ||||||+-- middle middle
-- |||||||
constant LEDV_0 : std_logic_vector(6 downto 0):= "1111110";-- 0
constant LEDV_1 : std_logic_vector(6 downto 0):= "0110000";-- 1
constant LEDV_2 : std_logic_vector(6 downto 0):= "1101101";-- 2
constant LEDV_3 : std_logic_vector(6 downto 0):= "1111001";-- 3
constant LEDV_4 : std_logic_vector(6 downto 0):= "0110011";-- 4
constant LEDV_5 : std_logic_vector(6 downto 0):= "1011011";-- 5
constant LEDV_6 : std_logic_vector(6 downto 0):= "1011111";-- 6
constant LEDV_7 : std_logic_vector(6 downto 0):= "1110000";-- 7
constant LEDV_8 : std_logic_vector(6 downto 0):= "1111111";-- 8
constant LEDV_9 : std_logic_vector(6 downto 0):= "1111011";-- 9
constant LEDV_A : std_logic_vector(6 downto 0):= "1110111";-- A
constant LEDV_b : std_logic_vector(6 downto 0):= "0011111";-- b
constant LEDV_C : std_logic_vector(6 downto 0):= "1001110";-- C
constant LEDV_d : std_logic_vector(6 downto 0):= "0111101";-- d
constant LEDV_E : std_logic_vector(6 downto 0):= "1001111";-- E
constant LEDV_F : std_logic_vector(6 downto 0):= "1000111";-- F
signal LED_CNT : std_logic_vector(24 downto 0);
signal LED_VAL : std_logic_vector(15 downto 0);
begin
process(CLK_I)
variable LED4H, LED4L : std_logic_vector(3 downto 0);
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (LED_CNT(24) = '0') then
LED4H := LED_VAL( 7 downto 4);
LED4L := LED_VAL( 3 downto 0);
else
LED4H := LED_VAL(15 downto 12);
LED4L := LED_VAL(11 downto 8);
end if;
if (LED_CNT = 0) then LED_VAL <= PC; end if;
LED_CNT <= LED_CNT + 1;
case LED4H is
when X"0" => SEG1 <= LEDV_0;
when X"1" => SEG1 <= LEDV_1;
when X"2" => SEG1 <= LEDV_2;
when X"3" => SEG1 <= LEDV_3;
when X"4" => SEG1 <= LEDV_4;
when X"5" => SEG1 <= LEDV_5;
when X"6" => SEG1 <= LEDV_6;
when X"7" => SEG1 <= LEDV_7;
when X"8" => SEG1 <= LEDV_8;
when X"9" => SEG1 <= LEDV_9;
when X"A" => SEG1 <= LEDV_A;
when X"B" => SEG1 <= LEDV_b;
when X"C" => SEG1 <= LEDV_c;
when X"D" => SEG1 <= LEDV_d;
when X"E" => SEG1 <= LEDV_E;
when others => SEG1 <= LEDV_F;
end case;
case LED4L is
when X"0" => SEG2(7 downto 1) <= LEDV_0;
when X"1" => SEG2(7 downto 1) <= LEDV_1;
when X"2" => SEG2(7 downto 1) <= LEDV_2;
when X"3" => SEG2(7 downto 1) <= LEDV_3;
when X"4" => SEG2(7 downto 1) <= LEDV_4;
when X"5" => SEG2(7 downto 1) <= LEDV_5;
when X"6" => SEG2(7 downto 1) <= LEDV_6;
when X"7" => SEG2(7 downto 1) <= LEDV_7;
when X"8" => SEG2(7 downto 1) <= LEDV_8;
when X"9" => SEG2(7 downto 1) <= LEDV_9;
when X"A" => SEG2(7 downto 1) <= LEDV_A;
when X"B" => SEG2(7 downto 1) <= LEDV_b;
when X"C" => SEG2(7 downto 1) <= LEDV_c;
when X"D" => SEG2(7 downto 1) <= LEDV_d;
when X"E" => SEG2(7 downto 1) <= LEDV_E;
when others => SEG2(7 downto 1) <= LEDV_F;
end case;
SEG2(0) <= LED_CNT(24);
end if;
end if;
end process;
end Behavioral;
| mit | 8074458c44ab6c4bfed5f74b717fd205 | 0.561708 | 2.542763 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/three_cycle_mult.vhd | 1 | 1,828 | --
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
| mit | a79abcb7f7b58d2ad6aed7c36747c9dc | 0.557987 | 3.508637 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/sinewave/many_sines.vhd | 1 | 4,909 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
-- Used only for midi_note_t and midi_note_arr_t
use virtual_button_lib.midi_pkg.all;
-- Used for sine_addr_max
use virtual_button_lib.sine_lut_pkg.all;
entity many_sines is
port(
ctrl : in ctrl_t;
midi_nos : in midi_note_arr_t;
pcm_out : out signed(15 downto 0);
new_pcm_out : out std_logic
);
end;
architecture rtl of many_sines is
type sine_rom_read_address_arr_t is array(0 to num_sines - 1) of integer range 0 to sine_addr_max;
type sine_rom_read_out_arr_t is array(0 to num_sines - 1) of signed(15 downto 0);
type strides_arr_t is array(0 to num_sines - 1) of integer range 0 to calc_midi_note_strides(midi_note_t'high);
type sine_driver_counter_arr_t is array(0 to num_sines - 1) of unsigned (midi_counter_width - 1 downto 0);
signal sine_rom_read_addresses : sine_rom_read_address_arr_t;
signal sine_rom_read_outs : sine_rom_read_out_arr_t;
signal strides : strides_arr_t;
signal sine_driver_counters : sine_driver_counter_arr_t := (others => (others => '0'));
constant stride_lut : stride_arr_t := calc_midi_note_strides;
-- These signals delay the current sine to allow sine_rom_read_out to be read
-- into the correct internals.
signal current_sine, current_sine_d1, current_sine_d2 : integer range 0 to num_sines - 1;
signal read_address : integer range 0 to sine_addr_max;
signal read_out : signed(15 downto 0);
-- Signals for generating the audio sampling frequency
constant audio_freq_counter_max : integer := sample_period / clk_period;
signal audio_freq_counter : integer range 0 to audio_freq_counter_max;
signal audio_freq_counter_done : std_logic;
-- stride signals
signal stride_read_addr : midi_note_t;
begin
sine_counter_runners : for j in 0 to num_sines - 1 generate
sine_driver : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
sine_driver_counters(j) <= (others => '0');
elsif audio_freq_counter_done = '1' then
sine_driver_counters(j) <= sine_driver_counters(j) + strides(j);
end if;
end if;
end process;
-- todo Make this prettier. Also I realised that sine_rom_read_address does
-- not need its own register. It is really just a truncation of sine_rom_read_address.
--
-- Note that the width of sine_driver counter is determined by the need to
-- maintain a correct output frequency granularity. This line removes the
-- bits which are not necessary for an address lookup.
sine_rom_read_addresses(j) <=
to_integer(sine_driver_counters(j)) / (2**(midi_counter_width - integer(log2(real(sine_addr_max)))));
end generate;
-- A single lookup table for sinewave generators.
sine_rom_1 : entity virtual_button_lib.sine_rom
port map (
ctrl => ctrl,
read_address_d0 => read_address,
read_out_d1 => read_out
);
-- A round robin multiplexer.
-- Cycles once per clock
sine_lookup_mux : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if current_sine = num_sines - 1 then
current_sine <= 0;
else
current_sine <= current_sine + 1;
end if;
current_sine_d1 <= current_sine;
read_address <= sine_rom_read_addresses(current_sine);
sine_rom_read_outs(current_sine_d1) <= read_out;
end if;
end process;
stride_lookup_mux : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
stride_read_addr <= midi_note_t'low;
else
stride_read_addr <= midi_nos(current_sine);
strides(current_sine_d1) <= stride_lut(stride_read_addr);
end if;
end if;
end process;
-- This is just a 44.1khz strobe.
count_audio_freq : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if audio_freq_counter >= audio_freq_counter_max then
audio_freq_counter <= 0;
audio_freq_counter_done <= '1';
else
audio_freq_counter <= audio_freq_counter + 1;
audio_freq_counter_done <= '0';
end if;
end if;
end process;
-- todo ugly will this synthesizable?
gen_pcm_out : process(ctrl.clk)
variable pcm_out_int : signed(15 + num_sines - 1 downto 0);
begin
if rising_edge(ctrl.clk) then
pcm_out_int := to_signed(0, pcm_out_int'length);
for i in 0 to num_sines - 1 loop
pcm_out_int := resize(sine_rom_read_outs(i), pcm_out_int'length) + pcm_out_int;
pcm_out <= pcm_out_int(pcm_out_int'left downto pcm_out_int'left - 15);
end loop;
end if;
end process;
new_pcm_out <= audio_freq_counter_done;
end;
| bsd-2-clause | 90a0e79e2753d68ac1fc0d738678e55a | 0.645142 | 3.281417 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/std_ovl.vhd | 1 | 10,812 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
package std_ovl is
-- subtypes for common generics
subtype ovl_severity_level is integer range -1 to 3;
subtype ovl_severity_level_natural is ovl_severity_level range 0 to ovl_severity_level'high;
subtype ovl_property_type is integer range -1 to 4;
subtype ovl_property_type_natural is ovl_property_type range 0 to ovl_property_type'high;
subtype ovl_coverage_level is integer range -1 to 15;
subtype ovl_coverage_level_natural is ovl_coverage_level range 0 to ovl_coverage_level'high;
subtype ovl_active_edges is integer range -1 to 3;
subtype ovl_active_edges_natural is ovl_active_edges range 0 to ovl_active_edges'high;
subtype ovl_reset_polarity is integer range -1 to 1;
subtype ovl_reset_polarity_natural is ovl_reset_polarity range 0 to ovl_reset_polarity'high;
subtype ovl_gating_type is integer range -1 to 2;
subtype ovl_gating_type_natural is ovl_gating_type range 0 to ovl_gating_type'high;
-- subtypes for checker specific generics
subtype ovl_necessary_condition is integer range 0 to 2;
subtype ovl_action_on_new_start is integer range 0 to 2;
subtype ovl_inactive is integer range 0 to 2;
subtype ovl_positive_2 is integer range 2 to integer'high;
subtype ovl_chk_overlap is integer range 0 to 1;
-- subtypes for control constants
subtype ovl_ctrl is integer range 0 to 1;
subtype ovl_msg_default_type is string(1 to 50);
-- user modifiable library control items
type ovl_ctrl_record is record
-- generate statement controls
xcheck_ctrl : ovl_ctrl;
implicit_xcheck_ctrl : ovl_ctrl;
init_msg_ctrl : ovl_ctrl;
init_count_ctrl : ovl_ctrl;
assert_ctrl : ovl_ctrl;
cover_ctrl : ovl_ctrl;
global_reset_ctrl : ovl_ctrl;
finish_ctrl : ovl_ctrl;
gating_ctrl : ovl_ctrl;
-- user configurable library constants
max_report_error : natural;
max_report_cover_point : natural;
runtime_after_fatal : string(1 to 10);
-- default values for common generics
severity_level_default : ovl_severity_level_natural;
property_type_default : ovl_property_type_natural;
msg_default : ovl_msg_default_type;
coverage_level_default : ovl_coverage_level_natural;
clock_edge_default : ovl_active_edges_natural;
reset_polarity_default : ovl_reset_polarity_natural;
gating_type_default : ovl_gating_type_natural;
end record ovl_ctrl_record;
-- global signals
signal ovl_global_reset_signal : std_logic;
signal ovl_end_of_simulation_signal : std_logic := '0';
-- global variable
shared variable ovl_init_count : natural := 0;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Hard-coded library constants --
-- NOTE: These constants must not be changed by users. Users can configure --
-- the library using the ovl_ctrl_record. Please see the OVL LRM for --
-- details of how to do this. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
constant OVL_VERSION : string := "V2.3";
-- This constant may be changed in future releases of the library or by EDA vendors.
constant OVL_FIRE_WIDTH : natural := 3;
constant OVL_NOT_SET : integer := -1;
-- generate statement control constants
constant OVL_ON : ovl_ctrl := 1;
constant OVL_OFF : ovl_ctrl := 0;
-- fire bit selection constants
constant OVL_FIRE_2STATE : integer := 0;
constant OVL_FIRE_XCHECK : integer := 1;
constant OVL_FIRE_COVER : integer := 2;
-- severity level
constant OVL_SEVERITY_LEVEL_NOT_SET : ovl_severity_level := OVL_NOT_SET;
constant OVL_FATAL : ovl_severity_level := 0;
constant OVL_ERROR : ovl_severity_level := 1;
constant OVL_WARNING : ovl_severity_level := 2;
constant OVL_INFO : ovl_severity_level := 3;
-- coverage levels
constant OVL_COVERAGE_LEVEL_NOT_SET : ovl_coverage_level := OVL_NOT_SET;
constant OVL_COVER_NONE : ovl_coverage_level := 0;
constant OVL_COVER_SANITY : ovl_coverage_level := 1;
constant OVL_COVER_BASIC : ovl_coverage_level := 2;
constant OVL_COVER_CORNER : ovl_coverage_level := 4;
constant OVL_COVER_STATISTIC : ovl_coverage_level := 8;
constant OVL_COVER_ALL : ovl_coverage_level := 15;
-- property type
constant OVL_PROPERTY_TYPE_NOT_SET : ovl_property_type := OVL_NOT_SET;
constant OVL_ASSERT : ovl_property_type := 0;
constant OVL_ASSUME : ovl_property_type := 1;
constant OVL_IGNORE : ovl_property_type := 2;
constant OVL_ASSERT_2STATE : ovl_property_type := 3;
constant OVL_ASSUME_2STATE : ovl_property_type := 4;
-- active edges
constant OVL_ACTIVE_EDGES_NOT_SET : ovl_active_edges := OVL_NOT_SET;
constant OVL_NOEDGE : ovl_active_edges := 0;
constant OVL_POSEDGE : ovl_active_edges := 1;
constant OVL_NEGEDGE : ovl_active_edges := 2;
constant OVL_ANYEDGE : ovl_active_edges := 3;
-- necessary condition
constant OVL_TRIGGER_ON_MOST_PIPE : ovl_necessary_condition := 0;
constant OVL_TRIGGER_ON_FIRST_PIPE : ovl_necessary_condition := 1;
constant OVL_TRIGGER_ON_FIRST_NOPIPE : ovl_necessary_condition := 2;
-- action on new start
constant OVL_IGNORE_NEW_START : ovl_action_on_new_start := 0;
constant OVL_RESET_ON_NEW_START : ovl_action_on_new_start := 1;
constant OVL_ERROR_ON_NEW_START : ovl_action_on_new_start := 2;
-- inactive levels
constant OVL_ALL_ZEROS : ovl_inactive := 0;
constant OVL_ALL_ONES : ovl_inactive := 1;
constant OVL_ONE_COLD : ovl_inactive := 2;
-- reset polarity
constant OVL_RESET_POLARITY_NOT_SET : ovl_reset_polarity := OVL_NOT_SET;
constant OVL_ACTIVE_LOW : ovl_reset_polarity := 0;
constant OVL_ACTIVE_HIGH : ovl_reset_polarity := 1;
-- gating type
constant OVL_GATING_TYPE_NOT_SET : ovl_gating_type := OVL_NOT_SET;
constant OVL_GATE_NONE : ovl_gating_type := 0;
constant OVL_GATE_CLOCK : ovl_gating_type := 1;
constant OVL_GATE_RESET : ovl_gating_type := 2;
-- ovl_next check_overlapping values
constant OVL_CHK_OVERLAP_OFF : ovl_chk_overlap := 1;
constant OVL_CHK_OVERLAP_ON : ovl_chk_overlap := 0;
-- checker xcheck type
constant OVL_IMPLICIT_XCHECK : boolean := false;
constant OVL_EXPLICIT_XCHECK : boolean := true;
-- common default values
constant OVL_SEVERITY_DEFAULT : ovl_severity_level := OVL_ERROR;
constant OVL_PROPERTY_DEFAULT : ovl_property_type := OVL_ASSERT;
constant OVL_MSG_NUL : string(10 to ovl_msg_default_type'high) := (others => NUL);
constant OVL_MSG_DEFAULT : ovl_msg_default_type := "VIOLATION" & OVL_MSG_NUL;
constant OVL_MSG_NOT_SET : string := "";
constant OVL_COVER_DEFAULT : ovl_coverage_level := OVL_COVER_BASIC;
constant OVL_CLOCK_EDGE_DEFAULT : ovl_active_edges := OVL_POSEDGE;
constant OVL_RESET_POLARITY_DEFAULT : ovl_reset_polarity := OVL_ACTIVE_LOW;
constant OVL_GATING_TYPE_DEFAULT : ovl_gating_type := OVL_GATE_CLOCK;
-- checker specific default values
constant OVL_NECESSARY_CONDITION_DEFAULT : ovl_necessary_condition := OVL_TRIGGER_ON_MOST_PIPE;
constant OVL_ACTION_ON_NEW_START_DEFAULT : ovl_action_on_new_start := OVL_IGNORE_NEW_START;
constant OVL_INACTIVE_DEFAULT : ovl_inactive := OVL_ONE_COLD;
-- default library configuration
constant OVL_CTRL_DEFAULTS : ovl_ctrl_record :=
(
-- generate statement controls
xcheck_ctrl => OVL_ON,
implicit_xcheck_ctrl => OVL_ON,
init_msg_ctrl => OVL_OFF,
init_count_ctrl => OVL_OFF,
assert_ctrl => OVL_ON,
cover_ctrl => OVL_OFF,
global_reset_ctrl => OVL_OFF,
finish_ctrl => OVL_ON,
gating_ctrl => OVL_ON,
-- user configurable library constants
max_report_error => 15,
max_report_cover_point => 15,
runtime_after_fatal => "100 ns ",
-- default values for common generics
severity_level_default => OVL_SEVERITY_DEFAULT,
property_type_default => OVL_PROPERTY_DEFAULT,
msg_default => OVL_MSG_DEFAULT,
coverage_level_default => OVL_COVER_DEFAULT,
clock_edge_default => OVL_CLOCK_EDGE_DEFAULT,
reset_polarity_default => OVL_RESET_POLARITY_DEFAULT,
gating_type_default => OVL_GATING_TYPE_DEFAULT
);
end package std_ovl;
| mit | 666553a4e5ec79c745fce355b4ddf9fd | 0.524417 | 4.020826 | false | false | false | false |
RafaelCatrou/docker_ghdl | src/ghdl_check1/a_testbench.vhd | 1 | 2,767 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
library lib;
use lib.all;
entity a_testbench is
end entity a_testbench;
architecture bench of a_testbench is
-- Component to test
component a_entity is
port (
clk : in std_logic;
din_enable : in std_logic;
din_value : in unsigned(15 downto 0);
dout_enable : out std_logic;
dout_value : out unsigned(15 downto 0)
);
end component a_entity;
signal clk : std_logic;
signal din_enable : std_logic;
signal din_value : unsigned(15 downto 0);
signal dout1_enable : std_logic;
signal dout1_value : unsigned(15 downto 0);
signal a_dout2_enable : std_logic;
signal a_dout2_value : unsigned(15 downto 0);
signal b_dout2_enable : std_logic;
signal b_dout2_value : unsigned(15 downto 0);
-- bench tools
constant CLOCK_HALF_PERIOD : time := 5 ns;
begin
a_instance_1 : a_entity
port map (
clk => clk,
din_enable => din_enable,
din_value => din_value,
dout_enable => dout1_enable,
dout_value => dout1_value
);
a_instance_2 : a_entity
port map (
clk => clk,
din_enable => dout1_enable,
din_value => dout1_value,
dout_enable => a_dout2_enable,
dout_value => a_dout2_value
);
--b_instance_1 : entity lib.b(b_archi2)
b_instance_1 : configuration lib.b_config
port map (
clk => clk,
din_enable => dout1_enable,
din_value => dout1_value,
dout_enable => b_dout2_enable,
dout_value => b_dout2_value
);
proc_clk : process
begin
clk <= '0';
wait for CLOCK_HALF_PERIOD;
clk <= '1';
wait for CLOCK_HALF_PERIOD;
end process proc_clk;
proc_upstream : process
begin
din_enable <= '0';
din_value <= (others => '0');
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
-- feed
for i in 0 to 3 loop
din_enable <= '1';
din_value <= din_value +1;
wait until rising_edge(clk);
din_enable <= '0';
wait until rising_edge(clk);
end loop;
wait;
end process proc_upstream;
proc_downstream : process(clk)
begin
if rising_edge(clk) then
if a_dout2_enable = '1' then
report string'("(A) dout2_value = ") & integer'image(to_integer(a_dout2_value));
end if;
if b_dout2_enable = '1' then
report string'("(B) dout2_value = ") & integer'image(to_integer(b_dout2_value));
end if;
end if;
end process proc_downstream;
proc_end_of_simulation : process
begin
wait for 1 us;
report "End of simulation";
finish(0);
wait;
end process proc_end_of_simulation;
end bench;
| apache-2.0 | e0ac954e3181082893e708e085d18721 | 0.594507 | 3.282325 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/strobe_to_square.vhd | 1 | 587 | library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
entity strobe_to_square is
port(
ctrl : in ctrl_t;
strobe : in std_logic;
square : out std_logic
);
end;
architecture rtl of strobe_to_square is
signal square_sig : std_logic;
begin
go : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
square_sig <= '0';
elsif strobe = '1' then
square_sig <= not square_sig;
end if;
end if;
end process go;
square <= square_sig;
end;
| bsd-2-clause | 231eac9755f4d4a31ba8ff0c0a499e0a | 0.625213 | 3.139037 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Advanced/test_bcd_display.vhd | 1 | 1,470 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY test_bcd_display IS
END test_bcd_display;
ARCHITECTURE behavior OF test_bcd_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_display
PORT(
clk : in std_logic;
masterReset : in std_logic;
byte_in : in STD_LOGIC_VECTOR(7 downto 0);
bcd_val : out STD_LOGIC_VECTOR(11 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal masterReset : std_logic := '0';
signal byte_in : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal bcd_val : std_logic_vector(11 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_display PORT MAP (
clk => clk,
masterReset => masterReset,
byte_in => byte_in,
bcd_val => bcd_val
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process (masterReset, clk) begin
if (masterReset = '1') then
byte_in <= (others => '0');
elsif (clk'event and clk = '1') then
byte_in <= byte_in + '1';
end if;
end process;
END;
| apache-2.0 | cc7fc30ac41c573cea618626684e81a8 | 0.578231 | 3.450704 | false | true | false | false |
willtmwu/vhdlExamples | Project/SPI_ctrlr_test.vhd | 1 | 5,414 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: SPI_ctrlr_test.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Testing NRF state transitions
------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SPI_ctrlr_test IS
END SPI_ctrlr_test;
ARCHITECTURE behavior OF SPI_ctrlr_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SPI_ctrlr
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
m_en : IN std_logic;
m_ready : OUT std_logic;
sTransmissionLines : in std_logic_vector(2 downto 0);
send_now : IN std_logic;
send_message : IN std_logic_vector(55 downto 0);
send_active : OUT std_logic;
recv_dtr : OUT std_logic;
recv_message : OUT std_logic_vector(55 downto 0);
recv_active : OUT std_logic;
hamming_err : IN std_logic_vector(7 downto 0);
IRQ : in STD_LOGIC;
CE : OUT std_logic;
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic;
LED_SPI : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal masterReset : std_logic := '1';
signal m_en : std_logic := '0';
signal send_now : std_logic := '0';
signal send_message : std_logic_vector(55 downto 0) := (others => '0');
signal hamming_err : std_logic_vector(7 downto 0) := (others => '0');
signal MISO : std_logic := '0';
signal IRQ : std_logic := '1';
signal sTransmissionLines : std_logic_vector(2 downto 0) := "010";
--Outputs
signal m_ready : std_logic;
signal send_active : std_logic;
signal recv_dtr : std_logic;
signal recv_message : std_logic_vector(55 downto 0);
signal recv_active : std_logic;
signal CE : std_logic;
signal CS : std_logic;
signal SCLK : std_logic;
signal MOSI : std_logic;
signal LED_SPI : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
--Procedure should mimic NRF, will need to clock out
procedure SPI_MISO (
byte_in : in std_logic_vector(7 downto 0) ;
signal MISO : out std_logic
) is
begin
for i in 7 downto 0 loop
MISO <= byte_in(i);
wait until falling_edge(SCLK);
end loop;
end SPI_MISO;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SPI_ctrlr PORT MAP (
clk => clk,
masterReset => masterReset,
m_en => m_en,
m_ready => m_ready,
sTransmissionLines => sTransmissionLines,
send_now => send_now,
send_message => send_message,
send_active => send_active,
recv_dtr => recv_dtr,
recv_message => recv_message,
recv_active => recv_active,
hamming_err => hamming_err,
IRQ => IRQ,
CE => CE,
CS => CS,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
LED_SPI => LED_SPI
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process
begin
wait for clk_period*10;
masterReset <= '0';
m_en <= '1';
wait until M_ready = '1';
-- Module Intialised and Send
wait for clk_period*10;
wait until rising_edge(clk);
send_now <= '1';
send_message(55 downto 40) <= "1111000010100011";
wait until rising_edge(clk);
send_now <= '0';
wait until send_active = '0';
wait for clk_period*100;
-- Test Interrupt Reading
IRQ <= '0';
wait until rising_edge(clk);
IRQ <= '1';
wait until recv_active = '1';
SPI_MISO("11111101", MISO);
SPI_MISO("11000001", MISO);
wait until falling_edge(SCLK);
-- Send Through a message, In Hex, start wit basic location
SPI_MISO(x"FF", MISO); -- REG
SPI_MISO(x"00", MISO); -- 0
SPI_MISO(x"2B", MISO); -- 1
SPI_MISO(x"8E", MISO); -- 2
SPI_MISO(x"71", MISO); -- 3
SPI_MISO(x"6C", MISO); -- 4
SPI_MISO(x"5A", MISO); -- 5
SPI_MISO(x"47", MISO); -- 6
SPI_MISO(x"36", MISO); -- 7
SPI_MISO(x"2B", MISO); -- 8
SPI_MISO(x"1D", MISO); -- 9
SPI_MISO(x"2A", MISO); -- 10
SPI_MISO(x"47", MISO); -- 11
SPI_MISO(x"1D", MISO); -- 12
SPI_MISO(x"93", MISO); -- 13
SPI_MISO(x"2B", MISO); -- 14
SPI_MISO(x"36", MISO); -- 15
SPI_MISO(x"8E", MISO); -- 16
SPI_MISO(x"5A", MISO); -- 17
SPI_MISO(x"00", MISO); -- 18
SPI_MISO(x"00", MISO); -- 19
SPI_MISO(x"6C", MISO); -- 20
SPI_MISO(x"00", MISO); -- 21
SPI_MISO(x"5A", MISO); -- 22
SPI_MISO(x"00", MISO); -- 23
SPI_MISO(x"47", MISO); -- 24
SPI_MISO(x"00", MISO); -- 25
SPI_MISO(x"36", MISO); -- 26
SPI_MISO(x"00", MISO); -- 27
SPI_MISO(x"2B", MISO); -- 28
SPI_MISO(x"00", MISO); -- 29
SPI_MISO(x"1D", MISO); -- 30
SPI_MISO(x"00", MISO); -- 31
wait for clk_period*30000;
wait;
end process;
END;
| apache-2.0 | 90171cf6ac927c93f383c0fac6edaa07 | 0.534171 | 3.072645 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Medium/bcd_1_adder.vhd | 2 | 867 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bcd_1_adder is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
C_IN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
C_OUT: out STD_LOGIC
);
end bcd_1_adder;
--algorithm
-- If A + B <= 9 then -- assume both A and B are valid BCD numbers
-- RESULT = A + B ;
-- CARRY = 0 ;
-- else
-- RESULT = A + B + 6 ;
-- CARRY = 1;
-- end if ;
architecture bcd_1_adder_arch of bcd_1_adder is
begin
--BCD adder logic
process (A,B,C_IN) begin
if ( ('0'&A) + ('0'&B) + C_IN <= 9 ) then
SUM <= (A + B + C_IN);
C_OUT <= '0';
else
SUM <= (A + B + C_IN + 6);
C_OUT <= '1';
end if;
end process;
end bcd_1_adder_arch;
| apache-2.0 | a5ecdd7d3349f2334576b3c1cfd6cbb2 | 0.529412 | 2.651376 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/MAC4/MAC4.vhd | 1 | 1,801 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MAC4 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (7 downto 0));
end MAC4;
architecture MAC4_arch of MAC4 is
component HA
port(A,B: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
component HAM
port(X,Y,B: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
component FA
port(A,B,Cin: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
component FAM
port(X,Y,B,Cin: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
signal S0,S1,S2,S3,S4,C1,C2,C3,C4 : STD_LOGIC_VECTOR(3 downto 0);
begin
S0(0) <= A(0) AND B(0);
S0(1) <= A(1) AND B(0);
S0(2) <= A(2) AND B(0);
S0(3) <= A(3) AND B(0);
HAM10: HAM port map(A(0),B(1),S0(1),S1(0),C1(0));
HAM11: HAM port map(A(1),B(1),S0(2),S1(1),C1(1));
HAM12: HAM port map(A(2),B(1),S0(3),S1(2),C1(2));
HAM13: HAM port map(A(3),B(1),'0',S1(3),C1(3));
FAM20: FAM port map(A(0),B(2),S1(1),C1(0),S2(0),C2(0));
FAM21: FAM port map(A(1),B(2),S1(2),C1(1),S2(1),C2(1));
FAM22: FAM port map(A(2),B(2),S1(3),C1(2),S2(2),C2(2));
HAM23: HAM port map(A(3),B(2),C1(3),S2(3),C2(3));
FAM30: FAM port map(A(0),B(3),S2(1),C2(0),S3(0),C3(0));
FAM31: FAM port map(A(1),B(3),S2(2),C2(1),S3(1),C3(1));
FAM32: FAM port map(A(2),B(3),S2(3),C2(2),S3(2),C3(2));
HAM33: HAM port map(A(3),B(3),C2(3),S3(3),C3(3));
HA40: HA port map(S3(1),C3(0),S4(0),C4(0));
FA41: FA port map(S3(2),C3(1),C4(0),S4(1),C4(1));
FA42: FA port map(S3(3),C3(2),C4(1),S4(2),C4(2));
HA44: HA port map(C3(3),C4(2),S4(3),open);
Z(0)<=S0(0);
Z(1)<=S1(0);
Z(2)<=S2(0);
Z(3)<=S3(0);
Z(4)<=S4(0);
Z(5)<=S4(1);
Z(6)<=S4(2);
Z(7)<=S4(3);
end MAC4_arch;
| mit | a5463a8c1ebe422969fd2c2f71907492 | 0.556913 | 1.876042 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_1_s512.vhd | 1 | 136,365 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_1_s512.vhd
-- /___/ /\ Timestamp: Mon Aug 18 13:51:53 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_1_s512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_1_s512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
din : in STD_LOGIC_VECTOR ( 0 downto 0 )
);
end fifo_generator_1_s512;
architecture STRUCTURE of fifo_generator_1_s512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1_143 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i_167 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i_202 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6_203 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7_204 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71_205 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8_206 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_mem : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_244 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_248 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_250 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_251 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_253 : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_15_sms_gram_gsms_0_gv5_srl32_Q31_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect : STD_LOGIC_VECTOR ( 14 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i;
empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i_167;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1_143;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i_202;
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_250,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_250
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_244
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_253
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_248,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_251
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_251,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_248
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_sm1_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => din(0),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(0),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(0),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_1_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(0),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(1),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(1),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_2_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(1),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(2),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(2),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_3_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(2),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(3),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(3),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_4_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(3),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(4),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(4),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_5_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(4),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(5),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_6_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(5),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(6),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(6),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_7_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(6),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(7),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(7),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_8_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(7),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(8),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(8),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_9_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(8),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(9),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(9),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_10_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(9),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(10),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(10),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_11_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(10),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(11),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(11),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_12_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(11),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(12),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(12),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_13_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(12),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(13),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(13),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_14_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(13),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(14),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(14),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_15_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(14),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(15),
Q31 => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_15_sms_gram_gsms_0_gv5_srl32_Q31_UNCONNECTED,
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(7),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(5),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6_203
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7_204
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(15),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(12),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(13),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(14),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71_205
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(11),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(8),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(9),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(10),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8_206
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(0),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_mem,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i_202
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i_167
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_3,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_8 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(8),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_7 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(7),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_6 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(6),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_5 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(5),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_4 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(4),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_3 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(3),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_2 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(2),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1_143
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_244,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_0_and00001 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"080CAEAE080C0C0C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp2,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_RD_PNTR_8_1 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71_205,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7_204,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6_203,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8_206,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_mem
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb1 : LUT6
generic map(
INIT => X"AEFF8CCC8CCC8CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp0,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp1,
I5 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Mxor_cntr_en_Result1 : LUT4
generic map(
INIT => X"6530"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
I2 => wr_en,
I3 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(4)
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 09529b2430b860ac37fba96cb11a50e9 | 0.676897 | 2.424094 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_never_unknown.vhd | 1 | 1,223 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never_unknown is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
qualifier : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never_unknown;
| mit | f59c3974b0bcfc9eaf644d3c18f864dc | 0.566639 | 3.35989 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Advanced/bcd_display.vhd | 1 | 1,554 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bcd_display is
Port ( clk : in std_logic;
masterReset : in std_logic;
byte_in : in STD_LOGIC_VECTOR(7 downto 0);
bcd_val : out STD_LOGIC_VECTOR(11 downto 0)
);
end bcd_display;
architecture Behavioral of bcd_display is begin
process ( masterReset, clk, byte_in )
variable byte_src : std_logic_vector (4 downto 0) ;
variable bcd_out : std_logic_vector (11 downto 0) ;
begin
if(masterReset = '1') then
byte_src := (others => '0');
bcd_out := (others => '0');
bcd_val <= (others => '0');
elsif(clk'event and clk='1') then
bcd_out := (others => '0');
bcd_out(2 downto 0) := byte_in(7 downto 5);
byte_src := byte_in(4 downto 0);
for i in byte_src'range loop
if bcd_out(3 downto 0) > "0100" then
bcd_out(3 downto 0) := bcd_out(3 downto 0) + "0011";
end if ;
if bcd_out(7 downto 4) > "0100" then
bcd_out(7 downto 4) := bcd_out(7 downto 4) + "0011";
end if ;
-- No roll over for hundred digit
bcd_out := bcd_out(10 downto 0) & byte_src(byte_src'left) ;
byte_src := byte_src(byte_src'left - 1 downto byte_src'right) & '0' ;
end loop ;
bcd_val <= bcd_out + '1';
end if;
end process ;
end Behavioral;
--Reference: http://stackoverflow.com/questions/23871792/convert-8bit-binary-number-to-bcd-in-vhdl | apache-2.0 | 25af90328cd37798b068990c6d25a88e | 0.569498 | 3.053045 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/DUT/single_cycle_add_and_xor.vhd | 1 | 3,229 | -- *******************************************************************
-- Copyright 2008 Ray Salemi
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000") and (done_aax_int = '0') and (reset_n = '1')) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
| mit | 5510b84dca883538a014e4657560697e | 0.506658 | 3.981504 | false | false | false | false |
zambreno/RCL | parallelCyGraph/vhdl/cygraph.vhd | 1 | 45,291 | library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
-- use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity cygraph is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- ae-to-ae signals
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
nxtae_rx_data : in std_logic_vector(31 downto 0);
nxtae_rx_vld : in std_logic;
prvae_rx_data : in std_logic_vector(31 downto 0);
prvae_rx_vld : in std_logic;
nxtae_tx_data : out std_logic_vector(31 downto 0);
nxtae_tx_vld : out std_logic;
prvae_tx_data : out std_logic_vector(31 downto 0);
prvae_tx_vld : out std_logic;
-- Graph Parameters
n_in : in std_logic_vector(63 downto 0); -- Number of nodes in graph
non_zeros_in : in std_logic_vector(63 downto 0); -- Number of non-zero edges
current_level_in : in std_logic_vector(63 downto 0); -- Current level of traversal
cq_count_in : in std_logic_vector(63 downto 0); -- How many nodes to traverse in the current level
nq_count_out : out std_logic_vector(63 downto 0); -- How many nodes to traverse in the next level
-- Input Graph Pointers (Represented in Custom CSR)
graphData_in : in std_logic_vector(63 downto 0);
graphInfo_in : in std_logic_vector(63 downto 0);
-- Queue pointers
queue1_address_in : in std_logic_vector(63 downto 0);
queue2_address_in : in std_logic_vector(63 downto 0);
-- MC0 port signals
mc0_req_ld : out std_logic;
mc0_req_st : out std_logic;
mc0_req_size : out std_logic_vector(1 downto 0);
mc0_req_vaddr : out std_logic_vector(47 downto 0);
mc0_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc0_req_flush : out std_logic;
mc0_rd_rq_stall : in std_logic;
mc0_wr_rq_stall : in std_logic;
mc0_rsp_push : in std_logic;
mc0_rsp_stall : out std_logic;
mc0_rsp_data : in std_logic_vector(63 downto 0);
mc0_rsp_rdctl : in std_logic_vector(31 downto 0);
mc0_rsp_flush_cmplt : in std_logic;
-- MC1 port signals
mc1_req_ld : out std_logic;
mc1_req_st : out std_logic;
mc1_req_size : out std_logic_vector(1 downto 0);
mc1_req_vaddr : out std_logic_vector(47 downto 0);
mc1_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc1_req_flush : out std_logic;
mc1_rd_rq_stall : in std_logic;
mc1_wr_rq_stall : in std_logic;
mc1_rsp_push : in std_logic;
mc1_rsp_stall : out std_logic;
mc1_rsp_data : in std_logic_vector(63 downto 0);
mc1_rsp_rdctl : in std_logic_vector(31 downto 0);
mc1_rsp_flush_cmplt : in std_logic;
-- MC2 port signals
mc2_req_ld : out std_logic;
mc2_req_st : out std_logic;
mc2_req_size : out std_logic_vector(1 downto 0);
mc2_req_vaddr : out std_logic_vector(47 downto 0);
mc2_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc2_req_flush : out std_logic;
mc2_rd_rq_stall : in std_logic;
mc2_wr_rq_stall : in std_logic;
mc2_rsp_push : in std_logic;
mc2_rsp_stall : out std_logic;
mc2_rsp_data : in std_logic_vector(63 downto 0);
mc2_rsp_rdctl : in std_logic_vector(31 downto 0);
mc2_rsp_flush_cmplt : in std_logic;
-- MC3 port signals
mc3_req_ld : out std_logic;
mc3_req_st : out std_logic;
mc3_req_size : out std_logic_vector(1 downto 0);
mc3_req_vaddr : out std_logic_vector(47 downto 0);
mc3_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc3_req_flush : out std_logic;
mc3_rd_rq_stall : in std_logic;
mc3_wr_rq_stall : in std_logic;
mc3_rsp_push : in std_logic;
mc3_rsp_stall : out std_logic;
mc3_rsp_data : in std_logic_vector(63 downto 0);
mc3_rsp_rdctl : in std_logic_vector(31 downto 0);
mc3_rsp_flush_cmplt : in std_logic;
-- MC4 port signals
mc4_req_ld : out std_logic;
mc4_req_st : out std_logic;
mc4_req_size : out std_logic_vector(1 downto 0);
mc4_req_vaddr : out std_logic_vector(47 downto 0);
mc4_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc4_req_flush : out std_logic;
mc4_rd_rq_stall : in std_logic;
mc4_wr_rq_stall : in std_logic;
mc4_rsp_push : in std_logic;
mc4_rsp_stall : out std_logic;
mc4_rsp_data : in std_logic_vector(63 downto 0);
mc4_rsp_rdctl : in std_logic_vector(31 downto 0);
mc4_rsp_flush_cmplt : in std_logic;
-- MC5 port signals
mc5_req_ld : out std_logic;
mc5_req_st : out std_logic;
mc5_req_size : out std_logic_vector(1 downto 0);
mc5_req_vaddr : out std_logic_vector(47 downto 0);
mc5_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc5_req_flush : out std_logic;
mc5_rd_rq_stall : in std_logic;
mc5_wr_rq_stall : in std_logic;
mc5_rsp_push : in std_logic;
mc5_rsp_stall : out std_logic;
mc5_rsp_data : in std_logic_vector(63 downto 0);
mc5_rsp_rdctl : in std_logic_vector(31 downto 0);
mc5_rsp_flush_cmplt : in std_logic;
-- MC6 port signals
mc6_req_ld : out std_logic;
mc6_req_st : out std_logic;
mc6_req_size : out std_logic_vector(1 downto 0);
mc6_req_vaddr : out std_logic_vector(47 downto 0);
mc6_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc6_req_flush : out std_logic;
mc6_rd_rq_stall : in std_logic;
mc6_wr_rq_stall : in std_logic;
mc6_rsp_push : in std_logic;
mc6_rsp_stall : out std_logic;
mc6_rsp_data : in std_logic_vector(63 downto 0);
mc6_rsp_rdctl : in std_logic_vector(31 downto 0);
mc6_rsp_flush_cmplt : in std_logic;
-- MC7 port signals
mc7_req_ld : out std_logic;
mc7_req_st : out std_logic;
mc7_req_size : out std_logic_vector(1 downto 0);
mc7_req_vaddr : out std_logic_vector(47 downto 0);
mc7_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc7_req_flush : out std_logic;
mc7_rd_rq_stall : in std_logic;
mc7_wr_rq_stall : in std_logic;
mc7_rsp_push : in std_logic;
mc7_rsp_stall : out std_logic;
mc7_rsp_data : in std_logic_vector(63 downto 0);
mc7_rsp_rdctl : in std_logic_vector(31 downto 0);
mc7_rsp_flush_cmplt : in std_logic;
-- MC8 port signals
mc8_req_ld : out std_logic;
mc8_req_st : out std_logic;
mc8_req_size : out std_logic_vector(1 downto 0);
mc8_req_vaddr : out std_logic_vector(47 downto 0);
mc8_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc8_req_flush : out std_logic;
mc8_rd_rq_stall : in std_logic;
mc8_wr_rq_stall : in std_logic;
mc8_rsp_push : in std_logic;
mc8_rsp_stall : out std_logic;
mc8_rsp_data : in std_logic_vector(63 downto 0);
mc8_rsp_rdctl : in std_logic_vector(31 downto 0);
mc8_rsp_flush_cmplt : in std_logic;
-- MC9 port signals
mc9_req_ld : out std_logic;
mc9_req_st : out std_logic;
mc9_req_size : out std_logic_vector(1 downto 0);
mc9_req_vaddr : out std_logic_vector(47 downto 0);
mc9_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc9_req_flush : out std_logic;
mc9_rd_rq_stall : in std_logic;
mc9_wr_rq_stall : in std_logic;
mc9_rsp_push : in std_logic;
mc9_rsp_stall : out std_logic;
mc9_rsp_data : in std_logic_vector(63 downto 0);
mc9_rsp_rdctl : in std_logic_vector(31 downto 0);
mc9_rsp_flush_cmplt : in std_logic;
-- MC10 port signals
mc10_req_ld : out std_logic;
mc10_req_st : out std_logic;
mc10_req_size : out std_logic_vector(1 downto 0);
mc10_req_vaddr : out std_logic_vector(47 downto 0);
mc10_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc10_req_flush : out std_logic;
mc10_rd_rq_stall : in std_logic;
mc10_wr_rq_stall : in std_logic;
mc10_rsp_push : in std_logic;
mc10_rsp_stall : out std_logic;
mc10_rsp_data : in std_logic_vector(63 downto 0);
mc10_rsp_rdctl : in std_logic_vector(31 downto 0);
mc10_rsp_flush_cmplt: in std_logic;
-- MC11 port signals
mc11_req_ld : out std_logic;
mc11_req_st : out std_logic;
mc11_req_size : out std_logic_vector(1 downto 0);
mc11_req_vaddr : out std_logic_vector(47 downto 0);
mc11_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc11_req_flush : out std_logic;
mc11_rd_rq_stall : in std_logic;
mc11_wr_rq_stall : in std_logic;
mc11_rsp_push : in std_logic;
mc11_rsp_stall : out std_logic;
mc11_rsp_data : in std_logic_vector(63 downto 0);
mc11_rsp_rdctl : in std_logic_vector(31 downto 0);
mc11_rsp_flush_cmplt: in std_logic;
-- MC12 port signals
mc12_req_ld : out std_logic;
mc12_req_st : out std_logic;
mc12_req_size : out std_logic_vector(1 downto 0);
mc12_req_vaddr : out std_logic_vector(47 downto 0);
mc12_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc12_req_flush : out std_logic;
mc12_rd_rq_stall : in std_logic;
mc12_wr_rq_stall : in std_logic;
mc12_rsp_push : in std_logic;
mc12_rsp_stall : out std_logic;
mc12_rsp_data : in std_logic_vector(63 downto 0);
mc12_rsp_rdctl : in std_logic_vector(31 downto 0);
mc12_rsp_flush_cmplt: in std_logic;
-- MC13 port signals
mc13_req_ld : out std_logic;
mc13_req_st : out std_logic;
mc13_req_size : out std_logic_vector(1 downto 0);
mc13_req_vaddr : out std_logic_vector(47 downto 0);
mc13_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc13_req_flush : out std_logic;
mc13_rd_rq_stall : in std_logic;
mc13_wr_rq_stall : in std_logic;
mc13_rsp_push : in std_logic;
mc13_rsp_stall : out std_logic;
mc13_rsp_data : in std_logic_vector(63 downto 0);
mc13_rsp_rdctl : in std_logic_vector(31 downto 0);
mc13_rsp_flush_cmplt: in std_logic;
-- MC14 port signals
mc14_req_ld : out std_logic;
mc14_req_st : out std_logic;
mc14_req_size : out std_logic_vector(1 downto 0);
mc14_req_vaddr : out std_logic_vector(47 downto 0);
mc14_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc14_req_flush : out std_logic;
mc14_rd_rq_stall : in std_logic;
mc14_wr_rq_stall : in std_logic;
mc14_rsp_push : in std_logic;
mc14_rsp_stall : out std_logic;
mc14_rsp_data : in std_logic_vector(63 downto 0);
mc14_rsp_rdctl : in std_logic_vector(31 downto 0);
mc14_rsp_flush_cmplt: in std_logic;
-- MC15 port signals
mc15_req_ld : out std_logic;
mc15_req_st : out std_logic;
mc15_req_size : out std_logic_vector(1 downto 0);
mc15_req_vaddr : out std_logic_vector(47 downto 0);
mc15_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc15_req_flush : out std_logic;
mc15_rd_rq_stall : in std_logic;
mc15_wr_rq_stall : in std_logic;
mc15_rsp_push : in std_logic;
mc15_rsp_stall : out std_logic;
mc15_rsp_data : in std_logic_vector(63 downto 0);
mc15_rsp_rdctl : in std_logic_vector(31 downto 0);
mc15_rsp_flush_cmplt: in std_logic
);
end entity;
architecture arch of cygraph is
component cygraph_kernel is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
current_level : in unsigned(31 downto 0); -- Current Level
cq_count : in unsigned(31 downto 0); -- Number of nodes to visit in the current level
-- kernels communication signals
kernel_tx_done : out std_logic; -- 0 kernel done, 1 kernel working
kernel_tx_vld : out std_logic;
kernel_tx_count : out unsigned(31 downto 0);
kernel_rx_done : in std_logic; -- 0 previous kernel done, 1 previous kernel working
kernel_rx_vld : in std_logic;
kernel_rx_count : in unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphData : in std_logic_vector(63 downto 0);
graphInfo : in std_logic_vector(63 downto 0);
-- Queue pointers
cq_address : in std_logic_vector(63 downto 0);
nq_address : in std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end component;
-- Input signals
signal n : std_logic_vector(63 downto 0); -- Number of nodes in graph
signal non_zeros : std_logic_vector(63 downto 0); -- Number of non-zero edges
signal graphData : std_logic_vector(63 downto 0);
signal graphInfo : std_logic_vector(63 downto 0);
signal queue1_address : std_logic_vector(63 downto 0);
signal queue2_address : std_logic_vector(63 downto 0);
-- Master Process Signals
signal kernels_count : unsigned(7 downto 0) := x"40"; -- 64 kernels
signal current_level : unsigned(31 downto 0);
signal cq_count : unsigned(31 downto 0);
type state is (st_idle, st_start, st_wait, st_busy, st_flush, st_done);
signal cygraph_state : state;
-- Kernels control signals
signal kernel_enable : std_logic_vector(15 downto 0);
signal kernel_done : std_logic_vector(15 downto 0);
signal kernel_busy : std_logic_vector(15 downto 0);
signal mc_flushed : std_logic_vector(15 downto 0);
signal cq_address : std_logic_vector(63 downto 0);
signal nq_address : std_logic_vector(63 downto 0);
-- Kernel-to-kernel communication signals
type unsigned32 is array (0 to 15) of unsigned(31 downto 0);
signal kernel_tx_done : std_logic_vector(15 downto 0);
signal kernel_tx_vld : std_logic_vector(15 downto 0);
signal kernel_tx_count : unsigned32;
signal master_tx_done : std_logic;
signal master_tx_vld : std_logic;
signal master_tx_count : unsigned(31 downto 0);
signal k2k_start : std_logic;
signal k0_rx_vld : std_logic;
signal nxtae_done : std_logic;
signal nxtae_count : std_logic_vector(31 downto 0);
signal done_sent_bw : std_logic;
signal done_sent_fw : std_logic;
begin
-- CyGraph Kernel 0
k0 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(0),
busy => kernel_busy(0),
done => kernel_done(0),
-- Kernel Parameters
kernel_id => x"00",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(0),
kernel_tx_vld => kernel_tx_vld(0),
kernel_tx_count => kernel_tx_count(0),
kernel_rx_done => master_tx_done,
kernel_rx_vld => k0_rx_vld, -- was master_tx_vld
kernel_rx_count => master_tx_count,
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC0 request port signals
mc_req_ld => mc0_req_ld,
mc_req_st => mc0_req_st,
mc_req_size => mc0_req_size,
mc_req_vaddr => mc0_req_vaddr,
mc_req_wrd_rdctl => mc0_req_wrd_rdctl,
mc_rd_rq_stall => mc0_rd_rq_stall,
mc_wr_rq_stall => mc0_wr_rq_stall,
-- MC0 response port signals
mc_rsp_push => mc0_rsp_push,
mc_rsp_stall => mc0_rsp_stall,
mc_rsp_data => mc0_rsp_data,
mc_rsp_rdctl => mc0_rsp_rdctl
);
-- CyGraph Kernel 1
k1 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(1),
busy => kernel_busy(1),
done => kernel_done(1),
-- Kernel Parameters
kernel_id => x"01",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(1),
kernel_tx_vld => kernel_tx_vld(1),
kernel_tx_count => kernel_tx_count(1),
kernel_rx_done => kernel_tx_done(0),
kernel_rx_vld => kernel_tx_vld(0),
kernel_rx_count => kernel_tx_count(0),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC1 request port signals
mc_req_ld => mc1_req_ld,
mc_req_st => mc1_req_st,
mc_req_size => mc1_req_size,
mc_req_vaddr => mc1_req_vaddr,
mc_req_wrd_rdctl => mc1_req_wrd_rdctl,
mc_rd_rq_stall => mc1_rd_rq_stall,
mc_wr_rq_stall => mc1_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc1_rsp_push,
mc_rsp_stall => mc1_rsp_stall,
mc_rsp_data => mc1_rsp_data,
mc_rsp_rdctl => mc1_rsp_rdctl
);
-- CyGraph Kernel 2
k2 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(2),
busy => kernel_busy(2),
done => kernel_done(2),
-- Kernel Parameters
kernel_id => x"02",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(2),
kernel_tx_vld => kernel_tx_vld(2),
kernel_tx_count => kernel_tx_count(2),
kernel_rx_done => kernel_tx_done(1),
kernel_rx_vld => kernel_tx_vld(1),
kernel_rx_count => kernel_tx_count(1),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC2 request port signals
mc_req_ld => mc2_req_ld,
mc_req_st => mc2_req_st,
mc_req_size => mc2_req_size,
mc_req_vaddr => mc2_req_vaddr,
mc_req_wrd_rdctl => mc2_req_wrd_rdctl,
mc_rd_rq_stall => mc2_rd_rq_stall,
mc_wr_rq_stall => mc2_wr_rq_stall,
-- MC2 response port signals
mc_rsp_push => mc2_rsp_push,
mc_rsp_stall => mc2_rsp_stall,
mc_rsp_data => mc2_rsp_data,
mc_rsp_rdctl => mc2_rsp_rdctl
);
-- CyGraph Kernel 3
k3 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(3),
busy => kernel_busy(3),
done => kernel_done(3),
-- Kernel Parameters
kernel_id => x"03",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(3),
kernel_tx_vld => kernel_tx_vld(3),
kernel_tx_count => kernel_tx_count(3),
kernel_rx_done => kernel_tx_done(2),
kernel_rx_vld => kernel_tx_vld(2),
kernel_rx_count => kernel_tx_count(2),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC3 request port signals
mc_req_ld => mc3_req_ld,
mc_req_st => mc3_req_st,
mc_req_size => mc3_req_size,
mc_req_vaddr => mc3_req_vaddr,
mc_req_wrd_rdctl => mc3_req_wrd_rdctl,
mc_rd_rq_stall => mc3_rd_rq_stall,
mc_wr_rq_stall => mc3_wr_rq_stall,
-- MC3 response port signals
mc_rsp_push => mc3_rsp_push,
mc_rsp_stall => mc3_rsp_stall,
mc_rsp_data => mc3_rsp_data,
mc_rsp_rdctl => mc3_rsp_rdctl
);
-- CyGraph Kernel 4
k4 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(4),
busy => kernel_busy(4),
done => kernel_done(4),
-- Kernel Parameters
kernel_id => x"04",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(4),
kernel_tx_vld => kernel_tx_vld(4),
kernel_tx_count => kernel_tx_count(4),
kernel_rx_done => kernel_tx_done(3),
kernel_rx_vld => kernel_tx_vld(3),
kernel_rx_count => kernel_tx_count(3),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC4 request port signals
mc_req_ld => mc4_req_ld,
mc_req_st => mc4_req_st,
mc_req_size => mc4_req_size,
mc_req_vaddr => mc4_req_vaddr,
mc_req_wrd_rdctl => mc4_req_wrd_rdctl,
mc_rd_rq_stall => mc4_rd_rq_stall,
mc_wr_rq_stall => mc4_wr_rq_stall,
-- MC4 response port signals
mc_rsp_push => mc4_rsp_push,
mc_rsp_stall => mc4_rsp_stall,
mc_rsp_data => mc4_rsp_data,
mc_rsp_rdctl => mc4_rsp_rdctl
);
-- CyGraph Kernel 5
k5 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(5),
busy => kernel_busy(5),
done => kernel_done(5),
-- Kernel Parameters
kernel_id => x"05",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(5),
kernel_tx_vld => kernel_tx_vld(5),
kernel_tx_count => kernel_tx_count(5),
kernel_rx_done => kernel_tx_done(4),
kernel_rx_vld => kernel_tx_vld(4),
kernel_rx_count => kernel_tx_count(4),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC1 request port signals
mc_req_ld => mc5_req_ld,
mc_req_st => mc5_req_st,
mc_req_size => mc5_req_size,
mc_req_vaddr => mc5_req_vaddr,
mc_req_wrd_rdctl => mc5_req_wrd_rdctl,
mc_rd_rq_stall => mc5_rd_rq_stall,
mc_wr_rq_stall => mc5_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc5_rsp_push,
mc_rsp_stall => mc5_rsp_stall,
mc_rsp_data => mc5_rsp_data,
mc_rsp_rdctl => mc5_rsp_rdctl
);
-- CyGraph Kernel 6
k6 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(6),
busy => kernel_busy(6),
done => kernel_done(6),
-- Kernel Parameters
kernel_id => x"06",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(6),
kernel_tx_vld => kernel_tx_vld(6),
kernel_tx_count => kernel_tx_count(6),
kernel_rx_done => kernel_tx_done(5),
kernel_rx_vld => kernel_tx_vld(5),
kernel_rx_count => kernel_tx_count(5),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC6 request port signals
mc_req_ld => mc6_req_ld,
mc_req_st => mc6_req_st,
mc_req_size => mc6_req_size,
mc_req_vaddr => mc6_req_vaddr,
mc_req_wrd_rdctl => mc6_req_wrd_rdctl,
mc_rd_rq_stall => mc6_rd_rq_stall,
mc_wr_rq_stall => mc6_wr_rq_stall,
-- MC6 response port signals
mc_rsp_push => mc6_rsp_push,
mc_rsp_stall => mc6_rsp_stall,
mc_rsp_data => mc6_rsp_data,
mc_rsp_rdctl => mc6_rsp_rdctl
);
-- CyGraph Kernel 7
k7 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(7),
busy => kernel_busy(7),
done => kernel_done(7),
-- Kernel Parameters
kernel_id => x"07",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(7),
kernel_tx_vld => kernel_tx_vld(7),
kernel_tx_count => kernel_tx_count(7),
kernel_rx_done => kernel_tx_done(6),
kernel_rx_vld => kernel_tx_vld(6),
kernel_rx_count => kernel_tx_count(6),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC7 request port signals
mc_req_ld => mc7_req_ld,
mc_req_st => mc7_req_st,
mc_req_size => mc7_req_size,
mc_req_vaddr => mc7_req_vaddr,
mc_req_wrd_rdctl => mc7_req_wrd_rdctl,
mc_rd_rq_stall => mc7_rd_rq_stall,
mc_wr_rq_stall => mc7_wr_rq_stall,
-- MC7 response port signals
mc_rsp_push => mc7_rsp_push,
mc_rsp_stall => mc7_rsp_stall,
mc_rsp_data => mc7_rsp_data,
mc_rsp_rdctl => mc7_rsp_rdctl
);
-- CyGraph Kernel 8
k8 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(8),
busy => kernel_busy(8),
done => kernel_done(8),
-- Kernel Parameters
kernel_id => x"08",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(8),
kernel_tx_vld => kernel_tx_vld(8),
kernel_tx_count => kernel_tx_count(8),
kernel_rx_done => kernel_tx_done(7),
kernel_rx_vld => kernel_tx_vld(7),
kernel_rx_count => kernel_tx_count(7),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC8 request port signals
mc_req_ld => mc8_req_ld,
mc_req_st => mc8_req_st,
mc_req_size => mc8_req_size,
mc_req_vaddr => mc8_req_vaddr,
mc_req_wrd_rdctl => mc8_req_wrd_rdctl,
mc_rd_rq_stall => mc8_rd_rq_stall,
mc_wr_rq_stall => mc8_wr_rq_stall,
-- MC8 response port signals
mc_rsp_push => mc8_rsp_push,
mc_rsp_stall => mc8_rsp_stall,
mc_rsp_data => mc8_rsp_data,
mc_rsp_rdctl => mc8_rsp_rdctl
);
-- CyGraph Kernel 9
k9 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(9),
busy => kernel_busy(9),
done => kernel_done(9),
-- Kernel Parameters
kernel_id => x"09",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(9),
kernel_tx_vld => kernel_tx_vld(9),
kernel_tx_count => kernel_tx_count(9),
kernel_rx_done => kernel_tx_done(8),
kernel_rx_vld => kernel_tx_vld(8),
kernel_rx_count => kernel_tx_count(8),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC9 request port signals
mc_req_ld => mc9_req_ld,
mc_req_st => mc9_req_st,
mc_req_size => mc9_req_size,
mc_req_vaddr => mc9_req_vaddr,
mc_req_wrd_rdctl => mc9_req_wrd_rdctl,
mc_rd_rq_stall => mc9_rd_rq_stall,
mc_wr_rq_stall => mc9_wr_rq_stall,
-- MC9 response port signals
mc_rsp_push => mc9_rsp_push,
mc_rsp_stall => mc9_rsp_stall,
mc_rsp_data => mc9_rsp_data,
mc_rsp_rdctl => mc9_rsp_rdctl
);
-- CyGraph Kernel 10
k10 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(10),
busy => kernel_busy(10),
done => kernel_done(10),
-- Kernel Parameters
kernel_id => x"0A",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(10),
kernel_tx_vld => kernel_tx_vld(10),
kernel_tx_count => kernel_tx_count(10),
kernel_rx_done => kernel_tx_done(9),
kernel_rx_vld => kernel_tx_vld(9),
kernel_rx_count => kernel_tx_count(9),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC10 request port signals
mc_req_ld => mc10_req_ld,
mc_req_st => mc10_req_st,
mc_req_size => mc10_req_size,
mc_req_vaddr => mc10_req_vaddr,
mc_req_wrd_rdctl => mc10_req_wrd_rdctl,
mc_rd_rq_stall => mc10_rd_rq_stall,
mc_wr_rq_stall => mc10_wr_rq_stall,
-- MC10 response port signals
mc_rsp_push => mc10_rsp_push,
mc_rsp_stall => mc10_rsp_stall,
mc_rsp_data => mc10_rsp_data,
mc_rsp_rdctl => mc10_rsp_rdctl
);
-- CyGraph Kernel 11
k11 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(11),
busy => kernel_busy(11),
done => kernel_done(11),
-- Kernel Parameters
kernel_id => x"0B",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(11),
kernel_tx_vld => kernel_tx_vld(11),
kernel_tx_count => kernel_tx_count(11),
kernel_rx_done => kernel_tx_done(10),
kernel_rx_vld => kernel_tx_vld(10),
kernel_rx_count => kernel_tx_count(10),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC11 request port signals
mc_req_ld => mc11_req_ld,
mc_req_st => mc11_req_st,
mc_req_size => mc11_req_size,
mc_req_vaddr => mc11_req_vaddr,
mc_req_wrd_rdctl => mc11_req_wrd_rdctl,
mc_rd_rq_stall => mc11_rd_rq_stall,
mc_wr_rq_stall => mc11_wr_rq_stall,
-- MC11 response port signals
mc_rsp_push => mc11_rsp_push,
mc_rsp_stall => mc11_rsp_stall,
mc_rsp_data => mc11_rsp_data,
mc_rsp_rdctl => mc11_rsp_rdctl
);
-- CyGraph Kernel 12
k12 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(12),
busy => kernel_busy(12),
done => kernel_done(12),
-- Kernel Parameters
kernel_id => x"0C",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(12),
kernel_tx_vld => kernel_tx_vld(12),
kernel_tx_count => kernel_tx_count(12),
kernel_rx_done => kernel_tx_done(11),
kernel_rx_vld => kernel_tx_vld(11),
kernel_rx_count => kernel_tx_count(11),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC12 request port signals
mc_req_ld => mc12_req_ld,
mc_req_st => mc12_req_st,
mc_req_size => mc12_req_size,
mc_req_vaddr => mc12_req_vaddr,
mc_req_wrd_rdctl => mc12_req_wrd_rdctl,
mc_rd_rq_stall => mc12_rd_rq_stall,
mc_wr_rq_stall => mc12_wr_rq_stall,
-- MC12 response port signals
mc_rsp_push => mc12_rsp_push,
mc_rsp_stall => mc12_rsp_stall,
mc_rsp_data => mc12_rsp_data,
mc_rsp_rdctl => mc12_rsp_rdctl
);
-- CyGraph Kernel 13
k13 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(13),
busy => kernel_busy(13),
done => kernel_done(13),
-- Kernel Parameters
kernel_id => x"0D",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(13),
kernel_tx_vld => kernel_tx_vld(13),
kernel_tx_count => kernel_tx_count(13),
kernel_rx_done => kernel_tx_done(12),
kernel_rx_vld => kernel_tx_vld(12),
kernel_rx_count => kernel_tx_count(12),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC13 request port signals
mc_req_ld => mc13_req_ld,
mc_req_st => mc13_req_st,
mc_req_size => mc13_req_size,
mc_req_vaddr => mc13_req_vaddr,
mc_req_wrd_rdctl => mc13_req_wrd_rdctl,
mc_rd_rq_stall => mc13_rd_rq_stall,
mc_wr_rq_stall => mc13_wr_rq_stall,
-- MC13 response port signals
mc_rsp_push => mc13_rsp_push,
mc_rsp_stall => mc13_rsp_stall,
mc_rsp_data => mc13_rsp_data,
mc_rsp_rdctl => mc13_rsp_rdctl
);
-- CyGraph Kernel 14
k14 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(14),
busy => kernel_busy(14),
done => kernel_done(14),
-- Kernel Parameters
kernel_id => x"0E",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(14),
kernel_tx_vld => kernel_tx_vld(14),
kernel_tx_count => kernel_tx_count(14),
kernel_rx_done => kernel_tx_done(13),
kernel_rx_vld => kernel_tx_vld(13),
kernel_rx_count => kernel_tx_count(13),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC14 request port signals
mc_req_ld => mc14_req_ld,
mc_req_st => mc14_req_st,
mc_req_size => mc14_req_size,
mc_req_vaddr => mc14_req_vaddr,
mc_req_wrd_rdctl => mc14_req_wrd_rdctl,
mc_rd_rq_stall => mc14_rd_rq_stall,
mc_wr_rq_stall => mc14_wr_rq_stall,
-- MC14 response port signals
mc_rsp_push => mc14_rsp_push,
mc_rsp_stall => mc14_rsp_stall,
mc_rsp_data => mc14_rsp_data,
mc_rsp_rdctl => mc14_rsp_rdctl
);
-- CyGraph Kernel 15
k15 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernel_enable(15),
busy => kernel_busy(15),
done => kernel_done(15),
-- Kernel Parameters
kernel_id => x"0F",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(15),
kernel_tx_vld => kernel_tx_vld(15),
kernel_tx_count => kernel_tx_count(15),
kernel_rx_done => kernel_tx_done(14),
kernel_rx_vld => kernel_tx_vld(14),
kernel_rx_count => kernel_tx_count(14),
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
graphInfo => graphInfo,
-- Queue pointers
cq_address => cq_address,
nq_address => nq_address,
-- MC15 request port signals
mc_req_ld => mc15_req_ld,
mc_req_st => mc15_req_st,
mc_req_size => mc15_req_size,
mc_req_vaddr => mc15_req_vaddr,
mc_req_wrd_rdctl => mc15_req_wrd_rdctl,
mc_rd_rq_stall => mc15_rd_rq_stall,
mc_wr_rq_stall => mc15_wr_rq_stall,
-- MC15 response port signals
mc_rsp_push => mc15_rsp_push,
mc_rsp_stall => mc15_rsp_stall,
mc_rsp_data => mc15_rsp_data,
mc_rsp_rdctl => mc15_rsp_rdctl
);
-- master_tx_done <= '1';
-- master_tx_done <= '1' when ae_id = "00" else prvae_rx_data(31) when prvae_rx_vld = '1' else master_tx_done;
-- master_tx_count <= (others => '0') when cygraph_state = st_start and ae_id = "00" else
-- (others => '0') when enable = '1' else
-- ('0' & unsigned(prvae_rx_data(30 downto 0))) when prvae_rx_vld = '1' else master_tx_count;
-- k0_rx_vld <= master_tx_vld when ae_id = "00" else prvae_rx_vld;
prvae_tx_vld <= '0';
prvae_tx_data <= (others => '0');
ae_ae : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
prvae_tx_vld <= '0';
prvae_tx_data <= (others => '0');
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
nxtae_done <= '0';
master_tx_done <= '0';
master_tx_count <= (others => '0');
done_sent_bw <= '0';
done_sent_fw <= '0';
nq_count_out <= (others => '0');
k0_rx_vld <= '0';
else
-- Control done_sent_fw
if (cygraph_state = st_start or enable = '1') then
done_sent_fw <= '0';
nq_count_out <= (others => '0');
elsif (prvae_rx_vld = '1' and prvae_rx_data(31) = '1') then
done_sent_fw <= '1';
nq_count_out <= x"00000000" & '0' & std_logic_vector(prvae_rx_data(30 downto 0));
end if;
-- Control nxtae_tx_vld, nxtae_tx_data
if (cygraph_state = st_start or enable = '1' or (ae_id = "00" and done_sent_fw = '1')) then
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
else
nxtae_tx_vld <= kernel_tx_vld(15);
nxtae_tx_data <= kernel_tx_done(15) & std_logic_vector(resize(kernel_tx_count(15), 31));
end if;
-- Control master_tx_count
if ((cygraph_state = st_start and ae_id = "00") or enable = '1') then
master_tx_count <= (others => '0');
elsif (prvae_rx_vld = '1') then
master_tx_count <= ('0' & unsigned(prvae_rx_data(30 downto 0)));
end if;
-- Control master_tx_done, k0_rx_vld, master_tx_count
if (cygraph_state = st_start or enable = '1') then
master_tx_done <= '0';
k0_rx_vld <= '0';
else
if (ae_id = "00" and done_sent_fw = '1') then
master_tx_done <= '0';
k0_rx_vld <= '0';
elsif (ae_id = "00") then
master_tx_done <= '1';
k0_rx_vld <= master_tx_vld;
elsif (prvae_rx_vld = '1') then
master_tx_done <= prvae_rx_data(31);
k0_rx_vld <= '1';
else
master_tx_done <= master_tx_done;
k0_rx_vld <= '0';
end if;
end if;
-- Control nxtae_done, nxtae_count
if (cygraph_state = st_start or enable = '1') then
nxtae_done <= '0';
nxtae_count <= (others => '0');
else
if (ae_id = "11") then
nxtae_done <= kernel_tx_done(15);
nxtae_count <= std_logic_vector(kernel_tx_count(15));
elsif (nxtae_rx_vld = '1') then
nxtae_done <= '1';
nxtae_count <= nxtae_rx_data;
end if;
end if;
-- -- Control prvae_tx_vld, prvae_tx_data
-- if (cygraph_state = st_start) then
-- prvae_tx_vld <= '0';
-- prvae_tx_data <= (others => '0');
-- done_sent_bw <= '0';
-- elsif (kernel_tx_done(15) = '1' and done_sent_bw = '0' and nxtae_done = '1') then
-- prvae_tx_vld <= '1';
-- prvae_tx_data <= nxtae_count;
-- done_sent_bw <= '1';
-- else
-- prvae_tx_vld <= '0';
-- end if;
end if;
end if;
end process; -- ae_ae
master : process(clk, rst)
begin
if rising_edge(clk) then
if (rst = '1') then
busy <= '0';
done <= '0';
cygraph_state <= st_idle;
kernel_enable <= (others => '0');
queue1_address <= (others => '0');
queue2_address <= (others => '0');
cq_address <= (others => '0');
nq_address <= (others => '0');
-- reset data
n <= (others => '0');
non_zeros <= (others => '0');
graphData <= (others => '0');
graphInfo <= (others => '0');
cq_count <= (others => '0');
current_level <= (others => '0');
-- reset flush
mc_flushed <= (others => '0');
mc0_req_flush <= '0';
mc1_req_flush <= '0';
mc2_req_flush <= '0';
mc3_req_flush <= '0';
mc4_req_flush <= '0';
mc5_req_flush <= '0';
mc6_req_flush <= '0';
mc7_req_flush <= '0';
mc8_req_flush <= '0';
mc9_req_flush <= '0';
mc10_req_flush <= '0';
mc11_req_flush <= '0';
mc12_req_flush <= '0';
mc13_req_flush <= '0';
mc14_req_flush <= '0';
mc15_req_flush <= '0';
else
case (cygraph_state) is
when st_idle =>
done <= '0';
-- reset flush
mc_flushed <= (others => '0');
mc0_req_flush <= '0';
mc1_req_flush <= '0';
mc2_req_flush <= '0';
mc3_req_flush <= '0';
mc4_req_flush <= '0';
mc5_req_flush <= '0';
mc6_req_flush <= '0';
mc7_req_flush <= '0';
mc8_req_flush <= '0';
mc9_req_flush <= '0';
mc10_req_flush <= '0';
mc11_req_flush <= '0';
mc12_req_flush <= '0';
mc13_req_flush <= '0';
mc14_req_flush <= '0';
mc15_req_flush <= '0';
if (enable = '1') then
busy <= '1';
n <= n_in;
non_zeros <= non_zeros_in;
graphData <= graphData_in;
graphInfo <= graphInfo_in;
queue1_address <= queue1_address_in;
queue2_address <= queue2_address_in;
current_level <= unsigned(current_level_in(31 downto 0));
cq_count <= unsigned(cq_count_in(31 downto 0));
kernel_enable <= x"FFFF"; -- set enable early, to allow k2k process in kernel to work
cygraph_state <= st_start;
else
busy <= '0';
kernel_enable <= x"0000";
cygraph_state <= st_idle;
end if ;
when st_start =>
if (kernel_busy = x"0000") then
kernel_enable <= x"FFFF";
cq_address <= queue1_address;
nq_address <= queue2_address;
cygraph_state <= st_wait;
else
cygraph_state <= st_start;
end if;
when st_wait =>
kernel_enable <= x"0000";
cygraph_state <= st_busy;
-- Wait ffor a level to be done
when st_busy =>
-- if (prvae_rx_vld = '1') then
-- nq_count_out <= x"00000000" & '0' & std_logic_vector(prvae_rx_data(30 downto 0));
-- end if;
if (kernel_busy = x"0000" and kernel_tx_done = x"FFFF" and (ae_id /= "00" or (ae_id = "00" and done_sent_fw = '1'))) then
-- if (kernel_busy = x"0000" and kernel_tx_done(15) = '1') then
-- if (kernel_busy = x"0000" and kernel_tx_done(15) = '1' and nxtae_done = '1') then
-- level is done
-- nq_count_out <= x"00000000" & nxtae_count;
mc_flushed <= (others => '0');
mc0_req_flush <= '1';
mc1_req_flush <= '1';
mc2_req_flush <= '1';
mc3_req_flush <= '1';
mc4_req_flush <= '1';
mc5_req_flush <= '1';
mc6_req_flush <= '1';
mc7_req_flush <= '1';
mc8_req_flush <= '1';
mc9_req_flush <= '1';
mc10_req_flush <= '1';
mc11_req_flush <= '1';
mc12_req_flush <= '1';
mc13_req_flush <= '1';
mc14_req_flush <= '1';
mc15_req_flush <= '1';
cygraph_state <= st_flush;
else
cygraph_state <= st_busy;
end if;
-- wait for flush to complete
when st_flush =>
mc0_req_flush <= '0';
mc1_req_flush <= '0';
mc2_req_flush <= '0';
mc3_req_flush <= '0';
mc4_req_flush <= '0';
mc5_req_flush <= '0';
mc6_req_flush <= '0';
mc7_req_flush <= '0';
mc8_req_flush <= '0';
mc9_req_flush <= '0';
mc10_req_flush <= '0';
mc11_req_flush <= '0';
mc12_req_flush <= '0';
mc13_req_flush <= '0';
mc14_req_flush <= '0';
mc15_req_flush <= '0';
if (mc0_rsp_flush_cmplt = '1') then
mc_flushed(0) <= '1';
end if;
if (mc1_rsp_flush_cmplt = '1') then
mc_flushed(1) <= '1';
end if;
if (mc2_rsp_flush_cmplt = '1') then
mc_flushed(2) <= '1';
end if;
if (mc3_rsp_flush_cmplt = '1') then
mc_flushed(3) <= '1';
end if;
if (mc4_rsp_flush_cmplt = '1') then
mc_flushed(4) <= '1';
end if;
if (mc5_rsp_flush_cmplt = '1') then
mc_flushed(5) <= '1';
end if;
if (mc6_rsp_flush_cmplt = '1') then
mc_flushed(6) <= '1';
end if;
if (mc7_rsp_flush_cmplt = '1') then
mc_flushed(7) <= '1';
end if;
if (mc8_rsp_flush_cmplt = '1') then
mc_flushed(8) <= '1';
end if;
if (mc9_rsp_flush_cmplt = '1') then
mc_flushed(9) <= '1';
end if;
if (mc10_rsp_flush_cmplt = '1') then
mc_flushed(10) <= '1';
end if;
if (mc11_rsp_flush_cmplt = '1') then
mc_flushed(11) <= '1';
end if;
if (mc12_rsp_flush_cmplt = '1') then
mc_flushed(12) <= '1';
end if;
if (mc13_rsp_flush_cmplt = '1') then
mc_flushed(13) <= '1';
end if;
if (mc14_rsp_flush_cmplt = '1') then
mc_flushed(14) <= '1';
end if;
if (mc15_rsp_flush_cmplt = '1') then
mc_flushed(15) <= '1';
end if;
if (mc_flushed = x"FFFF") then -- Just check the first flush_cmplt
cygraph_state <= st_done;
else
cygraph_state <= st_flush;
end if;
-- Cygraph is done
when st_done =>
done <= '1';
busy <= '0';
cygraph_state <= st_idle;
when others =>
cygraph_state <= st_idle;
end case;
end if; -- end if rst
end if; -- end if clk
end process; -- master
-- Kernel-to-kenrel process
--- Start and control the kernel_tx_vld signals
k2k : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
k2k_start <= '0';
master_tx_vld <= '0';
else
-- If kernel idle, reset signals
if (cygraph_state = st_start or enable = '1') then
-- if (cygraph_state = st_idle) then
k2k_start <= '0';
master_tx_vld <= '0';
-- elsif (cygraph_state = st_busy) then
else
-- If the start of the level, issue a vld signal
if (k2k_start = '0') then
master_tx_vld <= '1';
k2k_start <= '1';
else
-- if valid signal, pass it to next kernel in the ring
-- if (kernel_tx_vld(15) = '1') then
if (prvae_rx_vld = '1') then
master_tx_vld <= '1';
else
master_tx_vld <= '0';
end if;
end if;
-- else
-- k2k_start <= '0';
-- master_tx_vld <= '0';
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- Kernel-to-kernel communication
end architecture; | apache-2.0 | c0ae2fc0a3b187a4b67f3da726d0a8c0 | 0.603144 | 2.401941 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/data_core.vhd | 1 | 4,855 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity data_core is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
-- data in signals
IMM : in std_logic_vector(15 downto 0); -- immediate data
M_RDAT : in std_logic_vector( 7 downto 0); -- memory data
-- memory control signals
ADR : out std_logic_vector(15 downto 0);
MQ : out std_logic_vector( 7 downto 0);
-- input/output
IO_RDAT: in std_logic_vector( 7 downto 0);
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end data_core;
architecture Behavioral of data_core is
function b8(A : std_logic) return std_logic_vector is
begin
return A & A & A & A & A & A & A & A;
end;
COMPONENT alu8
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
CLR : in std_logic;
ALU_OP : IN std_logic_vector( 4 downto 0);
XX : IN std_logic_vector(15 downto 0);
YY : IN std_logic_vector(15 downto 0);
ZZ : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT select_yy
PORT( SY : IN std_logic_vector( 3 downto 0);
IMM : IN std_logic_vector(15 downto 0);
QUICK : IN std_logic_vector( 3 downto 0);
M_RDAT : IN std_logic_vector( 7 downto 0);
IO_RDAT : IN std_logic_vector( 7 downto 0);
RR : IN std_logic_vector(15 downto 0);
YY : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
-- cpu registers
--
signal RR : std_logic_vector(15 downto 0);
signal LL : std_logic_vector(15 downto 0);
signal SP : std_logic_vector(15 downto 0);
-- internal buses
--
signal XX : std_logic_vector(15 downto 0);
signal YY : std_logic_vector(15 downto 0);
signal ZZ : std_logic_vector(15 downto 0);
signal ADR_X : std_logic_vector(15 downto 0);
signal ADR_Z : std_logic_vector(15 downto 0);
signal ADR_YZ : std_logic_vector(15 downto 0);
signal ADR_XYZ : std_logic_vector(15 downto 0);
begin
alu_8: alu8
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
CLR => CLR,
ALU_OP => OP,
XX => XX,
YY => YY,
ZZ => ZZ
);
selyy: select_yy
PORT MAP( SY => SY,
IMM => IMM,
QUICK => QU,
M_RDAT => M_RDAT,
IO_RDAT => IO_RDAT,
RR => RR,
YY => YY
);
ADR <= ADR_XYZ;
MQ <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);
Q_RR <= RR;
Q_LL <= LL;
Q_SP <= SP;
-- memory address
--
sel_ax: process(SA(4 downto 3), IMM)
variable SAX : std_logic_vector(4 downto 3);
begin
SAX := SA(4 downto 3);
case SAX is
when SA_43_I16 => ADR_X <= IMM;
when SA_43_I8S => ADR_X <= b8(IMM(7)) & IMM(7 downto 0);
when others => ADR_X <= b8(SA(3)) & b8(SA(3));
end case;
end process;
sel_az: process(SA(2 downto 1), LL, RR, SP)
variable SAZ : std_logic_vector(2 downto 1);
begin
SAZ := SA(2 downto 1);
case SAZ is
when SA_21_0 => ADR_Z <= X"0000";
when SA_21_LL => ADR_Z <= LL;
when SA_21_RR => ADR_Z <= RR;
when others => ADR_Z <= SP;
end case;
end process;
sel_ayz: process(SA(0), ADR_Z)
begin
ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));
end process;
sel_axyz: process(ADR_X, ADR_YZ)
begin
ADR_XYZ <= ADR_X + ADR_YZ;
end process;
sel_xx: process(SX, LL, RR, SP, PC)
begin
case SX is
when SX_LL => XX <= LL;
when SX_RR => XX <= RR;
when SX_SP => XX <= SP;
when others => XX <= PC;
end case;
end process;
regs: process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
RR <= X"0000";
LL <= X"0000";
SP <= X"0000";
elsif (CE = '1') then
if (WE_RR = '1') then RR <= ZZ; end if;
if (WE_LL = '1') then LL <= ZZ; end if;
case WE_SP is
when SP_INC => SP <= ADR_YZ;
when SP_LOAD => SP <= ADR_XYZ;
when SP_NOP => null;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 232ccd608d3a798e5b526436d421152c | 0.567662 | 2.552576 | false | false | false | false |
SDRG-UCT/RHINO_CALF | gpmc-io/gpmc_blinky.vhd | 1 | 6,661 | --Alan Langman, 2011
--modified by Gordon Inggs, 2015
--https://github.com/brandonhamilton/rhino/tree/master/examples/gpmc_test
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; -- not a standard library
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
------------------------------------------------------------------------------------
-- Declare input and output pins for gpmc_blinky
------------------------------------------------------------------------------------
entity gpmc_blinky is
port
(
-- FPGA-processor interface pins
gpmc_a : in std_logic_vector(10 downto 1);
gpmc_d : inout std_logic_vector(15 downto 0);
gpmc_clk_i : in std_logic;
gpmc_n_cs : in std_logic_vector(6 downto 0);
gpmc_n_we : in std_logic;
gpmc_n_oe : in std_logic;
gpmc_n_adv_ale : in std_logic;
gpmc_n_wp : in std_logic;
gpmc_busy_0 : out std_logic;
gpmc_busy_1 : out std_logic;
-- LED and CLOCK pins
led : out std_logic_vector(7 downto 0);
sys_clk_P : in std_logic;
sys_clk_N : in std_logic
);
end gpmc_blinky;
------------------------------------------------------------------------------------
-- Architecture of rhino_proc_intrfc_top
------------------------------------------------------------------------------------
architecture rtl of gpmc_blinky is
------------------------------------------------------------------------------------
-- Declare types
------------------------------------------------------------------------------------
type ram_type is array (63 downto 0) of std_logic_vector(15 downto 0);
type word32_type is array (1 downto 0) of std_logic_vector(15 downto 0);
type word64_type is array (3 downto 0) of std_logic_vector(15 downto 0);
------------------------------------------------------------------------------------
-- Declare signals
------------------------------------------------------------------------------------
-- Define signals for the gpmc bus
signal gpmc_clk_i_b : std_logic; --buffered gpmc_clk_i
signal gpmc_address : std_logic_vector(25 downto 0):=(others => '0'); -- Full de-multiplexed address bus (ref. 16 bits)
signal gpmc_data_o : std_logic_vector(15 downto 0):="0000000000000000"; -- Register for output bus value
signal gpmc_data_i : std_logic_vector(15 downto 0):="0000000000000000"; -- Register for input bus value
--Other signals
signal heartbeat : std_logic;
signal dcm_locked : std_logic;
signal rd_cs_en : std_logic:='0';
signal we_cs_en : std_logic:='0';
--Clocks
signal sys_clk_100MHz : std_logic;
-- Debug signals
constant VERSION : std_logic_vector(7 downto 0) := "00000001"; --0x01 (1)
constant ID : std_logic_vector(7 downto 0) := "01010001"; --0x51 (81)
signal reg_bank: ram_type;
signal led_reg : std_logic_vector(15 downto 0) := "1010101001010101";
signal word32_reg: word32_type := ("0101010101010101","0101010101010101");
-- ALIASES
-- Support 64 memory banks, each with a maximum of 2MW
ALIAS reg_bank_address: std_logic_vector(3 downto 0) IS gpmc_address(25 downto 22);
-- Currently each register is 64 x 16
ALIAS reg_file_address: std_logic_vector(5 downto 0) IS gpmc_address(5 downto 0);
--==========================
begin --architecture RTL
--==========================
------------------------------------------------------------------------------------
-- Instantiate input buffer for FPGA_PROC_BUS_CLK
------------------------------------------------------------------------------------
IBUFG_gpmc_clk_i : IBUFG
generic map
(
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "DEFAULT"
)
port map
(
I => gpmc_clk_i,
O => gpmc_clk_i_b
);
------------------------------------------------------------------------------------
-- Instantiate differential input clockl buffer, for 100MHz clock (for UART)
-----------------------------------------------------------------------------------
IBUFGDS_sys_clk: IBUFGDS
generic map
(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE
)
port map
(
I => sys_clk_P,
IB => sys_clk_N,
O => sys_clk_100MHz
);
------------------------------------------------------------------------------------
-- Misc signal wiring
------------------------------------------------------------------------------------
-- Map important processor bus pins to GPIO header
led <= led_reg(7 downto 0);
-- Set other outputs low
gpmc_busy_0 <= '0';
gpmc_busy_1 <= '0';
-----------------------------------------------------------------------------------
-- Register File: Read
------------------------------------------------------------------------------------
process (gpmc_clk_i_b,gpmc_n_cs,gpmc_n_oe,gpmc_n_we,gpmc_n_adv_ale,gpmc_d,gpmc_a)
begin
if (gpmc_n_cs /= "1111111") then -- CS 1
if gpmc_clk_i_b'event and gpmc_clk_i_b = '1' then
--First cycle of the bus transaction record the address
if (gpmc_n_adv_ale = '0') then
gpmc_address <= gpmc_a & gpmc_d; -- Address of 16 bit word
--Second cycle of the bus is read or write
--Check for read
elsif (gpmc_n_oe = '0') then
case conv_integer(reg_bank_address) is
when 0 => gpmc_data_o <= ID & VERSION;
when 2 => gpmc_data_o <= word32_reg(conv_integer(reg_file_address));
when 3 => gpmc_data_o <= reg_bank(conv_integer(reg_file_address));
when others => gpmc_data_o <= (others => '0');
end case;
--Check for write
elsif (gpmc_n_we = '0') then
case conv_integer(reg_bank_address) is
when 1 => led_reg <= gpmc_data_i;
when 2 => word32_reg(conv_integer(reg_file_address)) <= gpmc_data_i;
when 3 => reg_bank(conv_integer(reg_file_address)) <= gpmc_data_i;
when others => null;
end case;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------
-- Manage the tri-state bus
---------------------------------------------------------------------------------
gpmc_d <= gpmc_data_o when (gpmc_n_oe = '0') else (others => 'Z');
gpmc_data_i <= gpmc_d;
end rtl;
| gpl-3.0 | 51d37a7ae6e702b6dcb9f79485b4e0a3 | 0.473953 | 3.955463 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_implication.vhd | 1 | 1,343 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_implication is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
antecedent_expr : in std_logic;
consequent_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_implication;
| mit | f926c8e559c112f10bbc4416affddca0 | 0.498138 | 3.859195 | false | false | false | false |
jaruiz/light8080 | src/vhdl/testbench/txt_util.vhdl | 1 | 14,577 | -- No license information available, assumed to be in public domain.
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| lgpl-2.1 | 59d031745b7d5aa4b7cff784cc836d16 | 0.474583 | 3.821972 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/uart_tx.vhd | 3 | 1,725 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
PORT( CLK_I : in std_logic;
RST_I : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : in std_logic; -- toggle to send data
SER_OUT : out std_logic; -- Serial output line
DATA_FLAGQ : out std_logic -- Transmitting Flag
);
end UART_TX;
architecture TX_UART_arch of UART_TX is
signal BUF : std_logic_vector(7 downto 0);
signal TODO : integer range 0 to 9; -- bits to send
signal FLAGQ : std_logic;
signal CE_1 : std_logic;
signal C16 : std_logic_vector(3 downto 0);
begin
DATA_FLAGQ <= FLAGQ;
-- generate a CE_1 every 16 CE_16...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
CE_1 <= '0';
if (RST_I = '1') then
C16 <= "0000";
elsif (CE_16 = '1') then
if (C16 = "1111") then
CE_1 <= '1';
end if;
C16 <= C16 + "0001";
end if;
end if;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
SER_OUT <= '1';
BUF <= "11111111";
TODO <= 0;
FLAGQ <= DATA_FLAG; -- idle
elsif (CE_1 = '1') then
if (TODO > 0) then -- transmitting
SER_OUT <= BUF(0); -- next bit
BUF <= '1' & BUF(7 downto 1);
if (TODO = 1) then
FLAGQ <= DATA_FLAG;
end if;
TODO <= TODO - 1;
elsif (FLAGQ /= DATA_FLAG) then -- new byte
SER_OUT <= '0'; -- start bit
TODO <= 9;
BUF <= DATA;
end if;
end if;
end if;
end process;
end TX_UART_arch;
| mit | b692534df262527c1305e38279784bec | 0.526377 | 2.674419 | false | false | false | false |
jmgc/myhdl-numeric | example/manual/FramerCtrl.vhd | 6 | 2,076 | -- File: FramerCtrl.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
package pck_FramerCtrl is
type t_enum_t_State_1 is (
SEARCH,
CONFIRM,
SYNC
);
attribute enum_encoding of t_enum_t_State_1: type is "001 010 100";
end package pck_FramerCtrl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
use work.pck_FramerCtrl.all;
entity FramerCtrl is
port (
SOF: out std_logic;
state: inout t_enum_t_State_1;
syncFlag: in std_logic;
clk: in std_logic;
reset_n: in std_logic
);
end entity FramerCtrl;
-- Framing control FSM.
--
-- SOF -- start-of-frame output bit
-- state -- FramerState output
-- syncFlag -- sync pattern found indication input
-- clk -- clock input
-- reset_n -- active low reset
architecture MyHDL of FramerCtrl is
signal index: unsigned(7 downto 0);
begin
FRAMERCTRL_FSM: process (clk, reset_n) is
begin
if (reset_n = '0') then
SOF <= '0';
index <= "00000000";
state <= SEARCH;
elsif rising_edge(clk) then
index <= ((index + 1) mod 8);
SOF <= '0';
case state is
when SEARCH =>
index <= "00000001";
if bool(syncFlag) then
state <= CONFIRM;
end if;
when CONFIRM =>
if (index = 0) then
if bool(syncFlag) then
state <= SYNC;
else
state <= SEARCH;
end if;
end if;
when SYNC =>
if (index = 0) then
if (not bool(syncFlag)) then
state <= SEARCH;
end if;
end if;
SOF <= stdl(signed(resize(index, 9)) = (8 - 1));
when others =>
assert False report "End of Simulation" severity Failure;
end case;
end if;
end process FRAMERCTRL_FSM;
end architecture MyHDL;
| lgpl-2.1 | 5fe07d1054c81879d4ba4ebd2499e1a8 | 0.523121 | 3.858736 | false | false | false | false |
zambreno/RCL | parallelCyGraph/vhdl/cygraph_kernel.vhd | 1 | 28,386 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- CyGraph Kernel
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity cygraph_kernel is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
current_level : in unsigned(31 downto 0); -- Current Level
cq_count : in unsigned(31 downto 0); -- Number of nodes to visit in the current level
-- kernels communication signals
kernel_tx_done : out std_logic; -- 0 kernel done, 1 kernel working
kernel_tx_vld : out std_logic;
kernel_tx_count : out unsigned(31 downto 0);
kernel_rx_done : in std_logic; -- 0 previous kernel done, 1 previous kernel working
kernel_rx_vld : in std_logic;
kernel_rx_count : in unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphData : in std_logic_vector(63 downto 0);
graphInfo : in std_logic_vector(63 downto 0);
-- Queue pointers
cq_address : in std_logic_vector(63 downto 0);
nq_address : in std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end cygraph_kernel;
architecture Behavioral of cygraph_kernel is
component master is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic;
done : out std_logic;
started : out std_logic;
-- kernels communication signals
current_level : in unsigned(31 downto 0); -- Current Level
kernel_rx_vld : in std_logic;
wr_offset : in unsigned(31 downto 0);
wr_reserved_space : in unsigned(31 downto 0);
wr_used_space : out unsigned(31 downto 0);
-- Queue pointers
nq_address : in std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- Process 1 signals
p1_req_q_rd_enb : out std_logic;
p1_req_q_dout : in std_logic_vector(63 downto 0);
p1_req_q_valid : in std_logic;
p1_req_q_empty : in std_logic;
-- Process 2 signals
p2_req_q_rd_enb : out std_logic;
p2_req_q_dout : in std_logic_vector(63 downto 0);
p2_req_q_valid : in std_logic;
p2_req_q_empty : in std_logic;
-- Process 3 signals
p3_req_q_rd_enb : out std_logic;
p3_req_q_dout : in std_logic_vector(63 downto 0);
p3_req_q_valid : in std_logic;
p3_req_q_empty : in std_logic;
-- Process 4 signals
p4_done : in std_logic;
p4_addr_q_rd_enb : out std_logic;
p4_addr_q_dout : in std_logic_vector(63 downto 0);
p4_addr_q_valid : in std_logic;
p4_addr_q_empty : in std_logic;
p4_info_q_rd_enb : out std_logic;
p4_info_q_dout : in std_logic_vector(63 downto 0);
p4_info_q_valid : in std_logic;
p4_info_q_empty : in std_logic
);
end component;
component process1 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0);
ae_id : in std_logic_vector(1 downto 0);
kernels_count : in unsigned(7 downto 0);
cq_count : in unsigned(31 downto 0);
-- Queue pointers
cq_address : in std_logic_vector(63 downto 0);
-- Process 1 signals
p1_done : out std_logic;
p1_count : out unsigned(31 downto 0);
-- Process 1 req queue signals
p1_req_q_almost_full : in std_logic;
p1_req_q_wr_en : out std_logic;
p1_req_q_din : out std_logic_vector(63 downto 0);
p1_req_q_full : in std_logic
);
end component;
component process2
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 2 information
p2_done : out std_logic;
p2_busy : out std_logic;
p2_count_1 : out unsigned(31 downto 0);
p2_count_2 : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphData : in std_logic_vector(63 downto 0);
-- Process 1 information
p1_done : in std_logic;
p1_count : in unsigned(31 downto 0);
-- Process 1 response queue signals
p1_rsp_q_rd_en : in std_logic;
p1_rsp_q_rd_enb : out std_logic;
p1_rsp_q_dout : in std_logic_vector(63 downto 0);
p1_rsp_q_valid : in std_logic;
p1_rsp_q_empty : in std_logic;
-- Process 2 request queue signals
p2_req_q_almost_full : in std_logic;
p2_req_q_wr_en : out std_logic;
p2_req_q_din : out std_logic_vector(63 downto 0)
);
end component;
component process3
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 3 signals
p3_done : out std_logic;
p3_count : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count_2 : in unsigned(31 downto 0);
-- Process 3 req queue signals
p3_req_q_almost_full : in std_logic;
p3_req_q_wr_en : out std_logic;
p3_req_q_din : out std_logic_vector(63 downto 0);
p3_req_q_full : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end component;
component fifo_generator_32_512 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
component fifo_generator_64_512 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
-- type addr_array is array (0 to 7) of std_logic_vector(63 downto 0);
signal k_rst : std_logic;
-- Master process signals
signal started : std_logic;
signal wr_offset : unsigned(31 downto 0); -- Next queue write offset (get it from previous kernel)
signal wr_demand_count : unsigned(31 downto 0); -- Space that kernel needs to reserve to write to next queue
signal wr_reserved_space : unsigned(31 downto 0); -- What I already reserved previously
signal wr_used_space : unsigned(31 downto 0); -- What I consumed from the reserved space
signal out_done : std_logic;
-- registers for output
signal out_kernel_tx_vld : std_logic;
-- Process 1 signals
signal p1_done : std_logic;
signal p1_count : unsigned(31 downto 0);
signal p1_offset : unsigned(31 downto 0);
signal p1_req_q_almost_full : std_logic;
signal p1_req_q_wr_en : std_logic;
signal p1_req_q_rd_enb : std_logic;
signal p1_req_q_rd_en : std_logic;
signal p1_req_q_din : std_logic_vector(63 downto 0);
signal p1_req_q_dout : std_logic_vector(63 downto 0);
signal p1_req_q_valid : std_logic;
signal p1_req_q_full : std_logic;
signal p1_req_q_empty : std_logic;
signal p1_rsp_q_almost_full : std_logic;
signal p1_rsp_q_wr_en : std_logic;
signal p1_rsp_q_rd_enb : std_logic;
signal p1_rsp_q_rd_en : std_logic;
signal p1_rsp_q_din : std_logic_vector(63 downto 0);
signal p1_rsp_q_dout : std_logic_vector(63 downto 0);
signal p1_rsp_q_valid : std_logic;
signal p1_rsp_q_full : std_logic;
signal p1_rsp_q_empty : std_logic;
-- Process 2 signals
signal p2_done : std_logic;
signal p2_busy : std_logic;
signal p2_count_1 : unsigned(31 downto 0);
signal p2_count_2 : unsigned(31 downto 0);
signal p2_req_q_almost_full : std_logic;
signal p2_req_q_wr_en : std_logic;
signal p2_req_q_rd_enb : std_logic;
signal p2_req_q_rd_en : std_logic;
signal p2_req_q_din : std_logic_vector(63 downto 0);
signal p2_req_q_dout : std_logic_vector(63 downto 0);
signal p2_req_q_valid : std_logic;
signal p2_req_q_full : std_logic;
signal p2_req_q_empty : std_logic;
signal p2_rsp_q_almost_full : std_logic;
signal p2_rsp_q_wr_en : std_logic;
signal p2_rsp_q_rd_enb : std_logic;
signal p2_rsp_q_rd_en : std_logic;
signal p2_rsp_q_din : std_logic_vector(31 downto 0);
signal p2_rsp_q_dout : std_logic_vector(31 downto 0);
signal p2_rsp_q_valid : std_logic;
signal p2_rsp_q_full : std_logic;
signal p2_rsp_q_empty : std_logic;
-- Process 3 signals
signal p3_done : std_logic;
signal p3_count : unsigned(31 downto 0);
signal p3_req_q_almost_full : std_logic;
signal p3_req_q_wr_en : std_logic;
signal p3_req_q_rd_enb : std_logic;
signal p3_req_q_rd_en : std_logic;
signal p3_req_q_din : std_logic_vector(63 downto 0);
signal p3_req_q_dout : std_logic_vector(63 downto 0);
signal p3_req_q_valid : std_logic;
signal p3_req_q_full : std_logic;
signal p3_req_q_empty : std_logic;
signal p3_rsp_q_almost_full : std_logic;
signal p3_rsp_q_wr_en : std_logic;
signal p3_rsp_q_rd_enb : std_logic;
signal p3_rsp_q_rd_en : std_logic;
signal p3_rsp_q_din : std_logic_vector(63 downto 0);
signal p3_rsp_q_dout : std_logic_vector(63 downto 0);
signal p3_rsp_q_valid : std_logic;
signal p3_rsp_q_full : std_logic;
signal p3_rsp_q_empty : std_logic;
-- Process 4 signals
signal p4_done : std_logic;
signal p4_count : unsigned(31 downto 0);
signal p4_state : unsigned(1 downto 0);
signal p4_addr_q_almost_full : std_logic;
signal p4_addr_q_wr_en : std_logic;
signal p4_addr_q_rd_enb : std_logic;
signal p4_addr_q_rd_en : std_logic;
signal p4_addr_q_din : std_logic_vector(63 downto 0);
signal p4_addr_q_dout : std_logic_vector(63 downto 0);
signal p4_addr_q_valid : std_logic;
signal p4_addr_q_full : std_logic;
signal p4_addr_q_empty : std_logic;
signal p4_info_q_almost_full : std_logic;
signal p4_info_q_wr_en : std_logic;
signal p4_info_q_rd_enb : std_logic;
signal p4_info_q_rd_en : std_logic;
signal p4_info_q_din : std_logic_vector(63 downto 0);
signal p4_info_q_dout : std_logic_vector(63 downto 0);
signal p4_info_q_valid : std_logic;
signal p4_info_q_full : std_logic;
signal p4_info_q_empty : std_logic;
begin
-- Output signals
done <= out_done;
kernel_tx_vld <= out_kernel_tx_vld; -- when out_done = '0' else kernel_rx_vld;
-- mask rd enable signals with empty signals
p1_req_q_rd_en <= p1_req_q_rd_enb and not p1_req_q_empty;
-- p1_rsp_q_rd_en <= p1_rsp_q_rd_enb and not p1_rsp_q_empty;
p1_rsp_q_rd_en <= p1_rsp_q_rd_enb and not p1_rsp_q_empty and not p2_busy; -- TEST
-- p2_req_q_rd_en <= p2_req_q_rd_enb and not p2_req_q_empty and not p2_busy; -- WERID!! WHY I NEED THE BUSY SIGNAL??
p2_req_q_rd_en <= p2_req_q_rd_enb and not p2_req_q_empty;
p2_rsp_q_rd_en <= p2_rsp_q_rd_enb and not p2_rsp_q_empty and not p3_rsp_q_empty;
p3_req_q_rd_en <= p3_req_q_rd_enb and not p3_req_q_empty;
p3_rsp_q_rd_en <= p3_rsp_q_rd_enb and not p2_rsp_q_empty and not p3_rsp_q_empty;
p4_addr_q_rd_en <= p4_addr_q_rd_enb and not p4_addr_q_empty;
p4_info_q_rd_en <= p4_info_q_rd_enb and not p4_info_q_empty;
p0: master
port map (
-- control signals
clk => clk,
rst => k_rst,
enable => enable,
busy => busy,
done => out_done,
started => started,
-- kernels communication signals
current_level => current_level,
kernel_rx_vld => kernel_rx_vld,
wr_offset => wr_offset,
wr_reserved_space => wr_reserved_space,
wr_used_space => wr_used_space,
-- Queue pointers
nq_address => nq_address,
-- MC request port signals
mc_req_ld => mc_req_ld,
mc_req_st => mc_req_st,
mc_req_size => mc_req_size,
mc_req_vaddr => mc_req_vaddr,
mc_req_wrd_rdctl => mc_req_wrd_rdctl,
mc_rd_rq_stall => mc_rd_rq_stall,
mc_wr_rq_stall => mc_wr_rq_stall,
-- Process 1 signals
p1_req_q_rd_enb => p1_req_q_rd_enb,
p1_req_q_dout => p1_req_q_dout,
p1_req_q_valid => p1_req_q_valid,
p1_req_q_empty => p1_req_q_empty,
-- Process 2 signals
p2_req_q_rd_enb => p2_req_q_rd_enb,
p2_req_q_dout => p2_req_q_dout,
p2_req_q_valid => p2_req_q_valid,
p2_req_q_empty => p2_req_q_empty,
-- Process 3 signals
p3_req_q_rd_enb => p3_req_q_rd_enb,
p3_req_q_dout => p3_req_q_dout,
p3_req_q_valid => p3_req_q_valid,
p3_req_q_empty => p3_req_q_empty,
-- Process 4 signals
p4_done => p4_done,
p4_addr_q_rd_enb => p4_addr_q_rd_enb,
p4_addr_q_dout => p4_addr_q_dout,
p4_addr_q_valid => p4_addr_q_valid,
p4_addr_q_empty => p4_addr_q_empty,
p4_info_q_rd_enb => p4_info_q_rd_enb,
p4_info_q_dout => p4_info_q_dout,
p4_info_q_valid => p4_info_q_valid,
p4_info_q_empty => p4_info_q_empty
);
p1: process1
port map (
-- control signals
clk => clk,
rst => k_rst,
started => started,
-- Kernel Parameters
kernel_id => kernel_id,
ae_id => ae_id,
kernels_count => kernels_count,
cq_count => cq_count,
-- Queue pointers
cq_address => cq_address,
-- Process 1 signals
p1_done => p1_done,
p1_count => p1_count,
-- Process 1 req queue signals
p1_req_q_almost_full => p1_req_q_almost_full,
p1_req_q_wr_en => p1_req_q_wr_en,
p1_req_q_din => p1_req_q_din,
p1_req_q_full => p1_req_q_full
);
p2: process2
port map (
-- control signals
clk => clk,
rst => k_rst,
started => started,
-- Process 2 information
p2_done => p2_done,
p2_busy => p2_busy,
p2_count_1 => p2_count_1,
p2_count_2 => p2_count_2,
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
-- Process 1 information
p1_done => p1_done,
p1_count => p1_count,
-- Process 1 response queue signals
p1_rsp_q_rd_en => p1_rsp_q_rd_en,
p1_rsp_q_rd_enb => p1_rsp_q_rd_enb,
p1_rsp_q_dout => p1_rsp_q_dout,
p1_rsp_q_valid => p1_rsp_q_valid,
p1_rsp_q_empty => p1_rsp_q_empty,
-- Process 2 request queue signals
p2_req_q_almost_full => p2_req_q_almost_full,
p2_req_q_wr_en => p2_req_q_wr_en,
p2_req_q_din => p2_req_q_din
);
p3: process3
port map (
-- control signals
clk => clk,
rst => k_rst,
started => started,
-- Process 3 signals
p3_done => p3_done,
p3_count => p3_count,
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo => graphInfo,
-- Process 2 information
p2_done => p2_done,
p2_count_2 => p2_count_2,
-- Process 3 req queue signals
p3_req_q_almost_full => p3_req_q_almost_full,
p3_req_q_wr_en => p3_req_q_wr_en,
p3_req_q_din => p3_req_q_din,
p3_req_q_full => p3_req_q_full,
-- MC response port signals
mc_rsp_push => mc_rsp_push,
mc_rsp_data => mc_rsp_data,
mc_rsp_rdctl => mc_rsp_rdctl
);
-- Process 1 request queue
p1_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p1_req_q_almost_full,
wr_en => p1_req_q_wr_en,
rd_en => p1_req_q_rd_enb,
din => p1_req_q_din,
dout => p1_req_q_dout,
full => p1_req_q_full,
empty => p1_req_q_empty,
valid => p1_req_q_valid
);
-- process 1 respond queue
p1_rsp_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p1_rsp_q_almost_full,
wr_en => p1_rsp_q_wr_en,
rd_en => p1_rsp_q_rd_en,
din => p1_rsp_q_din,
dout => p1_rsp_q_dout,
full => p1_rsp_q_full,
empty => p1_rsp_q_empty,
valid => p1_rsp_q_valid
);
-- process 2 request queue
p2_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_req_q_almost_full,
wr_en => p2_req_q_wr_en,
rd_en => p2_req_q_rd_en,
din => p2_req_q_din,
dout => p2_req_q_dout,
full => p2_req_q_full,
empty => p2_req_q_empty,
valid => p2_req_q_valid
);
-- process 2 respond queue
p2_rsp_q : fifo_generator_32_512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_rsp_q_almost_full,
wr_en => p2_rsp_q_wr_en,
rd_en => p2_rsp_q_rd_en,
din => p2_rsp_q_din,
dout => p2_rsp_q_dout,
full => p2_rsp_q_full,
empty => p2_rsp_q_empty,
valid => p2_rsp_q_valid
);
-- process 3 request queue
p3_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p3_req_q_almost_full,
wr_en => p3_req_q_wr_en,
rd_en => p3_req_q_rd_en,
din => p3_req_q_din,
dout => p3_req_q_dout,
full => p3_req_q_full,
empty => p3_req_q_empty,
valid => p3_req_q_valid
);
-- process 3 respond queue
p3_rsp_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p3_rsp_q_almost_full,
wr_en => p3_rsp_q_wr_en,
rd_en => p3_rsp_q_rd_en,
din => p3_rsp_q_din,
dout => p3_rsp_q_dout,
full => p3_rsp_q_full,
empty => p3_rsp_q_empty,
valid => p3_rsp_q_valid
);
-- process 4 address queue
p4_addr_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p4_addr_q_almost_full,
wr_en => p4_addr_q_wr_en,
rd_en => p4_addr_q_rd_en,
din => p4_addr_q_din,
dout => p4_addr_q_dout,
full => p4_addr_q_full,
empty => p4_addr_q_empty,
valid => p4_addr_q_valid
);
-- process 4 information queue (custom csr)
p4_info_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p4_info_q_almost_full,
wr_en => p4_info_q_wr_en,
rd_en => p4_info_q_rd_en,
din => p4_info_q_din,
dout => p4_info_q_dout,
full => p4_info_q_full,
empty => p4_info_q_empty,
valid => p4_info_q_valid
);
-- Kernel-to-kenrel process
-- Get the previous kernel reserved count, reserve yours and send it to the next kernel
k2k : process (clk, rst, k_rst)
begin
if (rising_edge(clk)) then
k_rst <= rst;
if (k_rst = '1') then
out_kernel_tx_vld <= '0';
kernel_tx_count <= (others => '0');
kernel_tx_done <= '0';
wr_demand_count <= (others => '0');
wr_reserved_space <= (others => '0');
wr_offset <= (others => '0');
else
-- If kernel busy
--- Incrmenet demand count when something is pushed to p4 queues
--- Wait for valid signal from previous kernel, and reserve space
--- Send done signal if done
if (enable = '1') then
out_kernel_tx_vld <= '0';
kernel_tx_count <= (others => '0');
kernel_tx_done <= '0';
wr_demand_count <= (others => '0');
wr_reserved_space <= (others => '0');
wr_offset <= (others => '0');
else
-- Inrease demand count whenever new item is pushed to p4 queues
if (p4_info_q_wr_en = '1') then
wr_demand_count <= wr_demand_count + 1;
end if;
-- if reserved space are consumed, request more ------------------------------------ FIX THAT
if (wr_used_space = wr_reserved_space and kernel_rx_vld = '1') then
out_kernel_tx_vld <= '1';
kernel_tx_count <= kernel_rx_count + wr_demand_count - wr_reserved_space;
wr_reserved_space <= wr_demand_count;
wr_offset <= kernel_rx_count;
-- elsif (wr_used_space < wr_reserved_space and kernel_rx_vld = '1') then
elsif (kernel_rx_vld = '1') then
out_kernel_tx_vld <= '1';
kernel_tx_count <= kernel_rx_count;
else
out_kernel_tx_vld <= '0';
end if;
-- if previous kernel is done and this kernel is done, assert kernel_tx_done
if (kernel_rx_done = '1' and out_done = '1') then
kernel_tx_done <= '1';
else
kernel_tx_done <= '0';
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- Kernel-to-kernel communication
p4 : process (clk, k_rst)
begin
if (rising_edge(clk)) then
if (k_rst = '1') then
p4_done <= '0';
p4_count <= (others => '0');
p4_state <= "00";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
else
if (started = '0') then
p4_done <= '0';
p4_count <= (others => '0');
p4_state <= "00";
-- set queues signals to default
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
elsif (started = '1') then
case (p4_state) is
-- Nothing was popped from queues before
when "00" =>
if (p2_rsp_q_empty = '0' and p3_rsp_q_empty = '0' and p4_info_q_almost_full = '0' and p4_addr_q_almost_full = '0') then
p2_rsp_q_rd_enb <= '1';
p3_rsp_q_rd_enb <= '1';
p4_count <= p4_count + 1;
p4_state <= "01";
-- set queues signals to default
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
else
p4_state <= "00";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end if;
-- Neighbor info is popped from p3_rsp and p2_rsp
when "01" =>
if (p3_rsp_q_valid = '1' and p2_rsp_q_valid = '1') then
-- if not visited, push address and csr to p4 queue
if (p3_rsp_q_dout(0) = '0') then
p4_addr_q_wr_en <= '1';
p4_addr_q_din <= std_logic_vector(resize(8 * unsigned(p2_rsp_q_dout) + unsigned(graphInfo), 64));
if (unsigned(p3_rsp_q_dout(31 downto 1)) > 0) then
p4_info_q_wr_en <= '1';
p4_info_q_din <= p3_rsp_q_dout;
else
p4_info_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
end if;
else
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end if;
-- If there is more, pop them
if (p2_rsp_q_empty = '0' and p3_rsp_q_empty = '0' and p4_info_q_almost_full = '0' and p4_addr_q_almost_full = '0') then
p4_state <= "01";
p2_rsp_q_rd_enb <= '1';
p3_rsp_q_rd_enb <= '1';
p4_count <= p4_count + 1;
else
p4_state <= "00";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
end if;
-- nothing popped yet, keep waiting
else
-- set queues signals to default
p4_state <= "01";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end if;
when others =>
p4_state <= "00";
-- set queues signals to default
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end case;
-- Process 4 is done if process 3 is done and p3_count = p4_count = p2_count_2
if p3_done = '1' and p4_count >= p2_count_2 and p4_count >= p3_count and p2_rsp_q_empty = '1' and p4_state = "00" then
p4_done <= '1';
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 4
-- I DON'T NEED THIS PROCESS .. could be distributed among different processes
-- MC Response decoder process
mc_rsp_decoder : process(clk, k_rst)
begin
if rising_edge(clk) then
if (k_rst = '1') then
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
mc_rsp_stall <= '0';
else
if (started = '0') then
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
mc_rsp_stall <= '0';
elsif (started = '1') then
if (mc_rsp_push = '1') then
-- Get process 1 response
if (mc_rsp_rdctl(7 downto 0) = x"01") then
-- push results to p1 response queue
p1_rsp_q_wr_en <= '1';
p1_rsp_q_din <= mc_rsp_data;
-- reset others
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
-- Get process 2 response
elsif (mc_rsp_rdctl(7 downto 0) = x"02") then
-- push results to p2 response queue
p2_rsp_q_wr_en <= '1';
p2_rsp_q_din <= mc_rsp_data(31 downto 0);
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
-- Get process 3 response
elsif (mc_rsp_rdctl(7 downto 0) = x"03") then
-- push results to p3 response queue
p3_rsp_q_wr_en <= '1';
p3_rsp_q_din <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
else
-- set p1 response qeueue signals to defaults
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
-- set p2 response qeueue signals to defaults
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
-- set p3 response qeueue signals to defaults
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
end if;
else
-- set p1 response qeueue signals to defaults
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
-- set p2 response qeueue signals to defaults
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
-- set p3 response qeueue signals to defaults
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
end if;
-- Control mc_rsp_stall signal
if (p1_rsp_q_almost_full = '1' or p2_rsp_q_almost_full = '1' or p3_rsp_q_almost_full = '1'
or p3_req_q_almost_full = '1' or p4_info_q_almost_full = '1' or p4_addr_q_almost_full = '1') then
mc_rsp_stall <= '1';
else
mc_rsp_stall <= '0';
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- end process rsp decoder
end Behavioral;
| apache-2.0 | 71ff3b539827c56dc8147ba2d44743b3 | 0.567392 | 2.425532 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/DPU_matrix_multiplication/DPU_matrix_multiplication.vhd | 1 | 1,851 | library ieee;
use ieee.std_logic_1164.all;
entity DPU_matrix_multiplication is
Port ( Ain : in STD_LOGIC_VECTOR (3 downto 0);
Bin : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
clear: in STD_LOGIC;
Aout : out STD_LOGIC_VECTOR (3 downto 0);
Bout : out STD_LOGIC_VECTOR (3 downto 0);
Result : out STD_LOGIC_VECTOR (9 downto 0));
end DPU_matrix_multiplication;
architecture DPU_matrix_multiplication_arch of DPU_matrix_multiplication is
component PIPO4
port( Rin: in STD_LOGIC_VECTOR (3 downto 0);
CLK,Preset,Clear: in STD_LOGIC;
Rout : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component MAC4
port( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component FA10
port( A : in STD_LOGIC_VECTOR (9 downto 0);
B : in STD_LOGIC_VECTOR (9 downto 0);
Sout : out STD_LOGIC_VECTOR (9 downto 0);
Cout : out STD_LOGIC);
end component;
component PIPO10
port( Rin: in STD_LOGIC_VECTOR (9 downto 0);
CLK,Preset,Clear: in STD_LOGIC;
Rout : out STD_LOGIC_VECTOR (9 downto 0));
end component;
signal S1,S2: STD_LOGIC_VECTOR (3 downto 0);
signal S3: STD_LOGIC_VECTOR (7 downto 0);
signal S4,S5,S6: STD_LOGIC_VECTOR (9 downto 0);
begin
R0: PIPO4 port map(Ain,CLK,'1',clear,S1);
R1: PIPO4 port map(Bin,CLK,'1',clear,S2);
MAC: MAC4 port map(S1,S2,S3);
S4(0)<=S3(0);
S4(1)<=S3(1);
S4(2)<=S3(2);
S4(3)<=S3(3);
S4(4)<=S3(4);
S4(5)<=S3(5);
S4(6)<=S3(6);
S4(7)<=S3(7);
S4(8)<='0';
S4(9)<='0';
FA: FA10 port map(S4,S5,S6,open);
R2: PIPO10 port map(S6,CLK,'1',clear,S5);
Aout <= S1;
Bout <= S2;
Result <= S5;
end DPU_matrix_multiplication_arch;
| mit | 70f9d956ab99db8c81db1c00dd251c15 | 0.601837 | 2.670996 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_never_unknown_async.vhd | 1 | 1,153 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never_unknown_async is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never_unknown_async;
| mit | dc9a1a4d9e323975bbcce4a5588bdde2 | 0.580225 | 3.313218 | false | false | false | false |
willtmwu/vhdlExamples | Finite State Machines/test_fsm_prac4.vhd | 1 | 2,281 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_fsm_prac4 IS
END test_fsm_prac4;
ARCHITECTURE behavior OF test_fsm_prac4 IS
COMPONENT fsm_prac4
PORT(
X : IN std_logic;
RESET : IN std_logic;
clk100mhz : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
signal X : std_logic := '0';
signal RESET : std_logic := '0';
signal clk100mhz : std_logic := '0';
signal Z : std_logic;
signal check_data_line : std_logic_vector (15 downto 0) := "0110110100011100";
signal check_data_match : std_logic_vector (15 downto 0) := "0000011011000000";
signal check_state_trans : std_logic_vector (19 downto 0) := "11010011101100011010";
constant clk100mhz_period : time := 10 ns;
signal full_check_state : std_logic_vector(31 downto 0) := (others => '0');
subtype counter_bit_int is integer range 0 to 31;
BEGIN
full_check_state(31 downto 16) <= check_data_line;
full_check_state(15 downto 0) <= check_data_match;
uut: fsm_prac4 PORT MAP (
X => X,
RESET => RESET,
clk100mhz => clk100mhz,
Z => Z
);
-- Clock process definitions
clk100mhz_process :process
begin
clk100mhz <= '0';
wait for clk100mhz_period/2;
clk100mhz <= '1';
wait for clk100mhz_period/2;
end process;
RESET <= '1';
-- Stimulus process
stim_proc: process
begin
RESET <= '0' ;
wait for clk100mhz_period*10;
RESET <= '1' ;
wait for clk100mhz_period*10;
FOR I in 19 downto 0 loop
wait until clk100mhz'event;
if clk100mhz = '1' then
X <= check_state_trans(I);
end if;
--assert ( Z = check_data_match(I) ) report "MATCH ERROR" severity error;
END loop;
wait until clk100mhz'event and clk100mhz = '1';
wait for clk100mhz_period*10;
wait;
end process;
-- tester : process (clk100mHz)
-- variable counter : counter_bit_int := 0;
-- begin
-- --wait until submitButton'event and submitButton = '1' ;
-- if (clk100mhz'event and clk100mhz = '1') then
-- if (counter >= 0) then
-- X <= full_check_state(counter);
-- counter := counter - 1;
-- else
-- counter := 31;
-- end if;
-- end if;
-- end process;
END;
| apache-2.0 | 4d7c74ef4e9b5407c1c79e94c37ce53d | 0.594915 | 3.086604 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/cpu.vhd | 1 | 5,755 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_pack.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity cpu16 is
PORT( CLK_I : in STD_LOGIC;
T2 : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR( 7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
XM_WE : out STD_LOGIC;
XM_CE : out STD_LOGIC
);
end cpu16;
architecture behavioral of cpu16 is
COMPONENT bin_to_7segment
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
SEG1 : OUT std_logic_vector(7 downto 1);
SEG2 : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT cpu_engine
PORT( CLK_I : in std_logic;
T2 : out std_logic;
CLR : in std_logic;
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- input/output
INT : in std_logic;
IO_ADR : out std_logic_vector(7 downto 0);
IO_RD : out std_logic;
IO_WR : out std_logic;
IO_RDAT : in std_logic_vector( 7 downto 0);
-- memory
XM_ADR : out std_logic_vector(15 downto 0);
XM_RDAT : in std_logic_vector( 7 downto 0);
XM_WDAT : out std_logic_vector( 7 downto 0);
XM_WE : out std_logic;
XM_CE : out std_logic;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0);
HALT : out std_logic
);
END COMPONENT;
COMPONENT input_output
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : OUT std_logic;
TEMP_SPO : IN std_logic;
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic;
SER_IN : IN std_logic;
SER_OUT : OUT std_logic;
SWITCH : IN std_logic_vector(9 downto 0);
LED : OUT std_logic_vector(7 downto 0);
IO_RD : IN std_logic;
IO_WR : IN std_logic;
IO_ADR : IN std_logic_vector(7 downto 0);
IO_WDAT : IN std_logic_vector(7 downto 0);
IO_RDAT : OUT std_logic_vector(7 downto 0);
INT : OUT std_logic;
HALT : in std_logic
);
END COMPONENT;
signal CLR : std_logic;
signal LT2 : std_logic;
signal ADR : std_logic_vector(15 downto 0);
signal HALT : std_logic;
signal INT : std_logic;
signal IO_RD : std_logic;
signal IO_WR : std_logic;
signal IO_ADR : std_logic_vector( 7 downto 0);
signal IO_RDAT : std_logic_vector( 7 downto 0);
signal IOM_WDAT : std_logic_vector( 7 downto 0);
signal PC : std_logic_vector(15 downto 0);
signal Q_C_SX : std_logic_vector(1 downto 0);
signal Q_C_SY : std_logic_vector(3 downto 0);
signal Q_C_OP : std_logic_vector(4 downto 0);
signal Q_C_SA : std_logic_vector(4 downto 0);
signal Q_C_SMQ : std_logic;
signal Q_C_WE_RR : std_logic;
signal Q_C_WE_LL : std_logic;
signal Q_C_WE_SP : SP_OP;
signal Q_C_RR : std_logic_vector(15 downto 0);
signal Q_C_LL : std_logic_vector(15 downto 0);
signal Q_C_SP : std_logic_vector(15 downto 0);
signal Q_C_OPC : std_logic_vector( 7 downto 0);
signal Q_C_CAT : op_category;
signal Q_C_IMM : std_logic_vector(15 downto 0);
signal Q_C_CYC : cycle;
begin
T2 <= LT2;
SEG1(0) <= HALT;
XM_ADR <= ADR;
XM_WDAT <= IOM_WDAT;
seg7: bin_to_7segment
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
PC => PC,
SEG1 => SEG1(7 downto 1),
SEG2 => SEG2
);
eng: cpu_engine
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR, -- SW-1 (RESET)
Q_PC => PC,
Q_OPC => Q_C_OPC,
Q_CAT => Q_C_CAT,
Q_IMM => Q_C_IMM,
Q_CYC => Q_C_CYC,
INT => INT,
IO_ADR => IO_ADR,
IO_RD => IO_RD,
IO_WR => IO_WR,
IO_RDAT => IO_RDAT,
XM_ADR => ADR,
XM_RDAT => XM_RDAT,
XM_WDAT => IOM_WDAT,
XM_WE => XM_WE,
XM_CE => XM_CE,
Q_SX => Q_C_SX,
Q_SY => Q_C_SY,
Q_OP => Q_C_OP,
Q_SA => Q_C_SA,
Q_SMQ => Q_C_SMQ,
Q_WE_RR => Q_C_WE_RR,
Q_WE_LL => Q_C_WE_LL,
Q_WE_SP => Q_C_WE_SP,
Q_RR => Q_C_RR,
Q_LL => Q_C_LL,
Q_SP => Q_C_SP,
HALT => HALT
);
io: input_output
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
SER_IN => SER_IN,
SER_OUT => SER_OUT,
SWITCH => SWITCH,
LED => LED,
IO_RD => IO_RD,
IO_WR => IO_WR,
IO_ADR => IO_ADR,
IO_RDAT => IO_RDAT,
IO_WDAT => IOM_WDAT,
INT => INT,
HALT => HALT
);
end behavioral;
| mit | b0971668fafc0a577b816817d060a492 | 0.535708 | 2.506533 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/spi/spi_tx.vhd | 1 | 5,342 | library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
entity spi_tx is
generic (
cpol : integer;
cpha : integer
);
port(
ctrl : in ctrl_t;
-- spi interface
cs_n : in std_logic;
sclk : in std_logic;
miso : out std_logic;
-- internal interface
data : in std_logic_vector(spi_word_length - 1 downto 0);
latched_data : out std_logic_vector(spi_word_length - 1 downto 0);
data_fully_latched : out std_logic
);
end;
architecture rtl of spi_tx is
----------------------------------------------------------------------------------------------------
-- Prevent metastability.
----------------------------------------------------------------------------------------------------
signal sclk_d1, sclk_d2 : std_logic;
signal cs_n_d1, cs_n_d2 : std_logic;
signal mosi_d1, mosi_d2 : std_logic;
signal ungated_miso : std_logic;
signal bit_index : integer range 0 to spi_word_length;
type state_t is (disabled, transmitting);
-- Note the subtraction of 2 is correct. See the comment in process transmit.
signal time_to_transmit : std_logic;
constant bit_index_reset : integer := 0;
signal latched_data_int : std_logic_vector(spi_word_length - 1 downto 0);
signal data_fully_latched_int : std_logic;
signal data_tentatively_latched : std_logic;
signal has_been_fully_latched : std_logic;
begin
prevent_metastability : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
sclk_d1 <= sclk;
sclk_d2 <= sclk_d1;
cs_n_d1 <= cs_n;
cs_n_d2 <= cs_n_d1;
end if;
end process prevent_metastability;
generate_time_to_transmit : process(sclk_d2, sclk_d1, cs_n_d2, cs_n_d1) is
variable time_to_transmit_bool : boolean;
begin
if cpol = 0 and cpha = 0 then
time_to_transmit_bool := (sclk_d2 = '1' and sclk_d1 = '0') or
--special case for transmitting first bit on
--fedge of chipselect
(cs_n_d2 = '1' and cs_n_d1 = '0');
elsif cpol = 0 and cpha = 1 then
time_to_transmit_bool := (sclk_d2 = '0' and sclk_d1 = '1') or
(cs_n_d2 = '1' and cs_n_d1 = '0');
elsif cpol = 1 and cpha = 0 then
time_to_transmit_bool := (sclk_d2 = '0' and sclk_d1 = '1');
else
time_to_transmit_bool := (sclk_d2 = '1' and sclk_d1 = '0');
end if;
if time_to_transmit_bool then
time_to_transmit <= '1';
else
time_to_transmit <= '0';
end if;
end process;
generate_latch : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
latched_data_int <= (others => '0');
else
if (cs_n_d2 = '1' and cs_n_d1 = '0' and has_been_fully_latched = '1') or
(time_to_transmit = '1' and
has_been_fully_latched = '1' and bit_index = 0)then
latched_data_int <= data;
data_tentatively_latched <= '1';
else
data_tentatively_latched <= '0';
end if;
end if;
end if;
end process;
select_next_bit : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
-- bit_index_reset is one greater than the number of bits in
-- latched_data, and would thus fail to index. Do not read latched_data
-- if this is the case.
ungated_miso <= latched_data_int(bit_index);
end if;
end process;
calc_bit_and_byte_index : process(ctrl.clk) is
procedure reset_indices is
begin
bit_index <= 0;
end;
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
reset_indices;
else
if cs_n_d1 = '1' then
reset_indices;
-- This is the initial bit of a byte. Send the first bit of the data in
-- the data port and latch the rest of it.
elsif time_to_transmit = '1' then
if bit_index = 0 then
bit_index <= 7;
else
bit_index <= bit_index - 1;
end if;
end if;
end if;
end if;
end process;
gate_miso : process (cs_n, cs_n_d1, ungated_miso)
begin
if cs_n = '1' or cs_n_d1 = '1' then
miso <= 'Z';
else
miso <= ungated_miso;
end if;
end process;
--This process exists to get around problems where the fpga attempted to send
--the next byte during the back porch. Since the back porch isn't actually
--the start of a new byte, that byte never got sent.
gen_second_bit_sent : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
data_fully_latched_int <= '0';
else
if bit_index < 5 and bit_index /= 0 then
data_fully_latched_int <= '1';
else
data_fully_latched_int <= '0';
end if;
if data_fully_latched_int = '1' then
has_been_fully_latched <= '1';
elsif data_tentatively_latched = '1' then
has_been_fully_latched <= '0';
end if;
end if;
end if;
end process;
data_fully_latched <= data_fully_latched_int;
latched_data <= latched_data_int;
end;
| bsd-2-clause | 5258544e9b3f074318883ba4b8a2aa07 | 0.547548 | 3.468831 | false | false | false | false |
willtmwu/vhdlExamples | Finite State Machines/fsm_prac4.vhd | 1 | 2,324 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fsm_prac4 IS
PORT ( X : IN STD_LOGIC;
RESET : IN STD_LOGIC;
clk100mhz : IN STD_LOGIC;
Z : OUT STD_LOGIC;
DEBUG_CHECK : OUT STD_LOGIC_VECTOR (3 downto 0);
DEBUG_OUT : OUT STD_LOGIC_VECTOR (3 downto 0));
END fsm_prac4;
ARCHITECTURE Behavioral OF fsm_prac4 IS
TYPE State_check_type IS (B,C,D,E,F);
--ATTRIBUTE ENUM_ENCODING of State_check_type: type is "000 010 100 110"
attribute enum_encoding : string;
attribute enum_encoding of State_check_type : type is "gray";
TYPE State_out_type IS (L,M,N);
Signal state_check : State_check_type := B;
Signal state_out : State_out_type := L;
Signal S : std_logic;
BEGIN
PROCESS(RESET, clk100mhz)
BEGIN
IF (RESET = '0') THEN
state_check <= B;
ELSIF (clk100mhz'EVENT AND clk100mhz = '1') THEN
CASE state_check IS
WHEN B =>
IF X = '1' THEN
state_check <= C;
ELSE
state_check <= B;
END IF;
DEBUG_CHECK <= "0000";
WHEN C =>
IF X = '1' THEN
state_check <= D;
ELSE
state_check <= B;
END IF;
DEBUG_CHECK <= "0001";
WHEN D =>
IF X = '0' THEN
state_check <= E;
ELSE
state_check <= B;
END IF;
DEBUG_CHECK <= "0010";
WHEN E =>
IF X = '1' THEN
state_check <= F;
ELSE
state_check <= B;
END IF;
DEBUG_CHECK <= "0011";
WHEN F =>
IF X = '1' THEN
state_check <= D;
ELSE
state_check <= B;
END IF;
DEBUG_CHECK <= "0100";
END CASE;
END IF;
END PROCESS;
S <= '1' WHEN (state_check = E AND X = '1') ELSE '0';
PROCESS (RESET, clk100mhz)
BEGIN
IF RESET = '0' THEN
state_out <= L;
ELSIF (clk100mhz'EVENT AND clk100mhz = '1') THEN
CASE state_out IS
WHEN L =>
IF S = '1' THEN
state_out <= M;
ELSE
state_out <= L;
END IF;
DEBUG_OUT <= "0000";
WHEN M =>
state_out <= N;
DEBUG_OUT <= "0001";
WHEN N =>
state_out <= L;
DEBUG_OUT <= "0010";
END CASE;
END IF;
END PROCESS;
Z <= '1' WHEN (state_out = M OR state_out = N) ELSE '0';
END Behavioral;
| apache-2.0 | 42b19b62bc59bd3661b59301f6c98153 | 0.509036 | 3.002584 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/spi/circular_queue_tb/circular_queue_tb.vhd | 1 | 4,734 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity circular_queue_tb is
end;
architecture behavioural of circular_queue_tb is
constant queue_depth : integer := 2;
signal ctrl : ctrl_t;
signal enqueue : std_logic := '0';
signal dequeue : std_logic := '0';
signal write_in_data : std_logic_vector(7 downto 0) := (others => '0');
signal read_out_data : std_logic_vector(7 downto 0);
signal empty : std_logic;
signal full : std_logic;
signal contents_count : natural range 0 to queue_depth + 1;
begin
circular_queue_1 : entity work.circular_queue
generic map (
queue_depth => queue_depth,
queue_width => 8
)
port map (
ctrl => ctrl,
enqueue => enqueue,
dequeue => dequeue,
write_in_data => write_in_data,
read_out_data => read_out_data,
empty => empty,
full => full,
contents_count => contents_count);
-- Clock process definitions
clk_process : process
begin
ctrl.clk <= '0';
wait for clk_period/2;
ctrl.clk <= '1';
wait for clk_period/2;
end process;
stim_proc : process
procedure write_item(value : in integer) is
begin
write_in_data <= std_logic_vector(to_unsigned(value, 8));
wait until falling_edge(ctrl.clk);
enqueue <= '1';
wait until falling_edge(ctrl.clk);
enqueue <= '0';
wait until falling_edge(ctrl.clk);
end;
procedure dequeue_item is
begin
dequeue <= '1';
wait until falling_edge(ctrl.clk);
dequeue <= '0';
wait until falling_edge(ctrl.clk);
end;
begin
ctrl.reset_n <= '0';
wait for 1 ms;
-- Check reset values
assert empty = '1' report "empty reset value fail";
assert full = '0' report "full reset value fail";
assert contents_count = 0 report "contents_count reset value fail";
ctrl.reset_n <= '1';
wait for 1 us;
-- Check empty and full when there is no data.
assert empty = '1' report "empty fail after reset deassert";
assert full = '0' report "full fail after reset deassert";
assert contents_count = 0 report "contents_count fail after reset deassert";
-- Now add an item. Check that the queue is neither empty nor full.
-- Also check that read_out_data is showing the same item.
write_item(1);
assert empty = '0' report "empty fail after single item added";
assert full = '0' report "full fail after single item added";
assert read_out_data = write_in_data report "read_out_data is not equal to write_in_data after first item added";
assert contents_count = 1 report "contents_count fail after single item added";
-- Add another item. Check that full is asserted and that read_out_data has
-- not changed this time.
write_item(2);
assert empty = '0' report "empty fail when fifo should be full";
assert full = '1' report "full fail when fifo is full";
assert read_out_data = std_logic_vector(to_unsigned(1, 8));
assert contents_count = 2 report "contents_count fail when fifo is full";
-- Now to check that nothing happens, attempt to write a third value. the
-- first item will be dequeued and we will check that the third value is
-- not beign displayed.
write_item(3);
assert empty = '0' report "empty fail after writing to full queue";
assert full = '1' report "full fail after writing to full queue";
assert contents_count = 2 report "contents_count fail after writing to full queue";
dequeue_item;
assert empty = '0' report "empty fail after dequeueing full queue";
assert full = '0' report "full fail after dequeueing full queue";
assert read_out_data = std_logic_vector(to_unsigned(2, 8));
assert contents_count = 1 report "contents_count fail after dequeueing full queue";
-- Now dequeue the final item. Check that the queue is empty again.
dequeue_item;
assert empty = '1' report "empty fail after emptying the queue";
assert full = '0' report "full fail after emptying the queue";
assert contents_count = 0 report "contents_count fail after emptying the queueue";
-- Check that empty and full do not change when dequeueing an empty queue
dequeue_item;
assert empty = '1' report "empty fail after dequeueing an empty queue";
assert full = '0' report "full fail after dequeueing an empty queue";
assert contents_count = 0 report "contents_count fail after dequeueing and empty queue";
assert false severity failure;
wait;
end process;
end;
| bsd-2-clause | 8616e9c95e5332d721f16c4b3b7c1a20 | 0.653147 | 3.883511 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/alu8.vhd | 1 | 7,815 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity alu8 is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
ALU_OP : in std_logic_vector( 4 downto 0);
XX : in std_logic_vector(15 downto 0);
YY : in std_logic_vector(15 downto 0);
ZZ : out std_logic_vector(15 downto 0)
);
end alu8;
architecture Behavioral of alu8 is
function sh_mask(Y : unsigned(3 downto 0);
YMAX : unsigned(3 downto 0);
LR : std_logic;
FILL : std_logic;
X : std_logic) return std_logic is
begin
if (YMAX >= Y) then -- Y small
if (LR = '1') then return X; -- LSL
else return FILL; -- LSR
end if;
else -- Y big
if (LR = '1') then return FILL; -- LSL
else return X; -- ASR/LSR
end if;
end if;
end;
function b8(A : std_logic) return std_logic_vector is
begin
return A & A & A & A & A & A & A & A;
end;
function b16(A : std_logic) return std_logic_vector is
begin
return b8(A) & b8(A);
end;
function aoxn(A : std_logic_vector(3 downto 0)) return std_logic is
begin
case A is
-- and
when "0000" => return '0';
when "0001" => return '0';
when "0010" => return '0';
when "0011" => return '1';
-- or
when "0100" => return '0';
when "0101" => return '1';
when "0110" => return '1';
when "0111" => return '1';
-- xor
when "1000" => return '0';
when "1001" => return '1';
when "1010" => return '1';
when "1011" => return '0';
-- not Y
when "1100" => return '1';
when "1101" => return '0';
when "1110" => return '1';
when others => return '0';
end case;
end;
signal MD_OR : std_logic_vector(15 downto 0); -- Multiplicator/Divisor
signal PROD_REM : std_logic_vector(31 downto 0);
signal MD_OP : std_logic; -- operation D/M, S/U
signal QP_NEG : std_logic; -- product / quotient negative
signal RM_NEG : std_logic; -- remainder negative
begin
alumux: process(ALU_OP, MD_OP, XX, YY, QP_NEG, RM_NEG, PROD_REM)
variable MASKED_X : std_logic_vector(15 downto 0);
variable SCNT : unsigned(3 downto 0);
variable SFILL : std_logic;
variable ROL1 : std_logic_vector(15 downto 0);
variable ROL2 : std_logic_vector(15 downto 0);
variable ROL4 : std_logic_vector(15 downto 0);
variable ROL8 : std_logic_vector(15 downto 0);
variable X_GE_Y : std_logic; -- signed X >= Y
variable X_HS_Y : std_logic; -- unsigned X >= Y
variable X_HSGE_Y : std_logic; -- any X >= Y
variable X_EQ_Y : std_logic; -- signed X == Y
variable X_CMP_Y : std_logic;
begin
MASKED_X := XX and b16(ALU_OP(0));
SFILL := ALU_OP(0) and XX(15);
if (ALU_OP(1) = '1') then -- LSL
SCNT := UNSIGNED(YY(3 downto 0));
else -- LSR / ASR
SCNT := "0000" - UNSIGNED(YY(3 downto 0));
end if;
if (SCNT(0) = '0') then ROL1 := XX;
else ROL1 := XX(14 downto 0) & XX(15);
end if;
if (SCNT(1) = '0') then ROL2 := ROL1;
else ROL2 := ROL1(13 downto 0) & ROL1(15 downto 14);
end if;
if (SCNT(2) = '0') then ROL4 := ROL2;
else ROL4 := ROL2(11 downto 0) & ROL2(15 downto 12);
end if;
if (SCNT(3) = '0') then ROL8 := ROL4;
else ROL8 := ROL4(7 downto 0) & ROL4(15 downto 8);
end if;
if (XX = YY) then X_EQ_Y := '1';
else X_EQ_Y := '0';
end if;
if (UNSIGNED(XX) >= UNSIGNED(YY)) then X_HSGE_Y := '1';
else X_HSGE_Y := '0';
end if;
if (XX(15) /= YY(15)) then -- different sign/high bit
X_HS_Y := XX(15); -- X ia bigger iff high bit set
X_GE_Y := YY(15); -- X is bigger iff Y negative
else -- same sign/high bit: GE == HS
X_HS_Y := X_HSGE_Y;
X_GE_Y := X_HSGE_Y;
end if;
case ALU_OP is
when ALU_X_HS_Y => X_CMP_Y := X_HS_Y;
when ALU_X_LO_Y => X_CMP_Y := not X_HS_Y;
when ALU_X_HI_Y => X_CMP_Y := X_HS_Y and not X_EQ_Y;
when ALU_X_LS_Y => X_CMP_Y := not (X_HS_Y and not X_EQ_Y);
when ALU_X_GE_Y => X_CMP_Y := X_GE_Y;
when ALU_X_LT_Y => X_CMP_Y := not X_GE_Y;
when ALU_X_GT_Y => X_CMP_Y := X_GE_Y and not X_EQ_Y;
when ALU_X_LE_Y => X_CMP_Y := not (X_GE_Y and not X_EQ_Y);
when ALU_X_EQ_Y => X_CMP_Y := X_EQ_Y;
when others => X_CMP_Y := not X_EQ_Y;
end case;
ZZ <= X"0000";
case ALU_OP is
when ALU_X_HS_Y | ALU_X_LO_Y | ALU_X_HI_Y | ALU_X_LS_Y |
ALU_X_GE_Y | ALU_X_LT_Y | ALU_X_GT_Y | ALU_X_LE_Y |
ALU_X_EQ_Y | ALU_X_NE_Y =>
ZZ <= b16(X_CMP_Y);
when ALU_NEG_Y | ALU_X_SUB_Y =>
ZZ <= MASKED_X - YY;
when ALU_MOVE_Y | ALU_X_ADD_Y =>
ZZ <= MASKED_X + YY;
when ALU_X_AND_Y | ALU_X_OR_Y | ALU_X_XOR_Y | ALU_NOT_Y =>
for i in 0 to 15 loop
ZZ(i) <= aoxn(ALU_OP(1 downto 0) & XX(i) & YY(i));
end loop;
when ALU_X_LSR_Y | ALU_X_ASR_Y | ALU_X_LSL_Y =>
for i in 0 to 15 loop
ZZ(i) <= sh_mask(SCNT, CONV_UNSIGNED(i, 4),
ALU_OP(1), SFILL, ROL8(i));
end loop;
when ALU_X_MIX_Y =>
ZZ(15 downto 8) <= YY(7 downto 0);
ZZ( 7 downto 0) <= XX(7 downto 0);
when ALU_MUL_IU | ALU_MUL_IS |
ALU_DIV_IU | ALU_DIV_IS | ALU_MD_STP => -- mult/div ini/step
ZZ <= PROD_REM(15 downto 0);
when ALU_MD_FIN => -- mult/div
if (QP_NEG = '0') then ZZ <= PROD_REM(15 downto 0);
else ZZ <= X"0000" - PROD_REM(15 downto 0);
end if;
when others => -- modulo
if (RM_NEG = '0') then ZZ <= PROD_REM(31 downto 16);
else ZZ <= X"0000" - PROD_REM(31 downto 16);
end if;
end case;
end process;
muldiv: process(CLK_I)
variable POS_YY : std_logic_vector(15 downto 0);
variable POS_XX : std_logic_vector(15 downto 0);
variable DIFF : std_logic_vector(16 downto 0);
variable SUM : std_logic_vector(16 downto 0);
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
PROD_REM <= X"00000000"; -- product/remainder
MD_OR <= X"0000"; -- multiplicator/divisor
MD_OP <= '0'; -- mult(0)/div(1)
QP_NEG <= '0'; -- quotient/product negative
RM_NEG <= '0'; -- remainder negative
elsif (CE = '1') then
SUM := ('0' & PROD_REM(31 downto 16)) + ('0' & MD_OR);
DIFF := ('0' & PROD_REM(30 downto 15)) - ('0' & MD_OR);
if (XX(15) = '0') then POS_XX := XX;
else POS_XX := X"0000" - XX;
end if;
if (YY(15) = '0') then POS_YY := YY;
else POS_YY := X"0000" - YY;
end if;
case ALU_OP is
when ALU_MUL_IU | ALU_MUL_IS | ALU_DIV_IU | ALU_DIV_IS =>
MD_OP <= ALU_OP(1); -- div / mult
MD_OR <= POS_YY; -- multiplicator/divisor
QP_NEG <= ALU_OP(0) and (XX(15) xor YY(15));
RM_NEG <= ALU_OP(0) and XX(15);
PROD_REM <= X"0000" & POS_XX;
when ALU_MD_STP =>
if (MD_OP = '0') then -- multiplication step
PROD_REM(15 downto 0) <= PROD_REM(16 downto 1);
if (PROD_REM(0) = '0') then
PROD_REM(31 downto 15) <=
'0' & PROD_REM(31 downto 16);
else
PROD_REM(31 downto 15) <= SUM;
end if;
else -- division step
if (DIFF(16) = '1') then -- carry: small remainder
PROD_REM(31 downto 16) <= PROD_REM(30 downto 15);
else
PROD_REM(31 downto 16) <= DIFF(15 downto 0);
end if;
PROD_REM(15 downto 1) <= PROD_REM(14 downto 0);
PROD_REM(0) <= not DIFF(16);
end if;
when others =>
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | aa30c4a90aaa070cf78baca713b54495 | 0.540243 | 2.469975 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/opcode_decoder.vhd | 2 | 33,474 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_decoder is
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : IN std_logic_vector(7 downto 0);
OP_CYC : IN cycle; -- current cycle (M1, M2, ...)
INT : IN std_logic; -- interrupt
RRZ : IN std_logic; -- RR is zero
OP_CAT : OUT op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic; -- last M cycle of an opcode
HLT : out std_logic
);
end opcode_decoder;
architecture Behavioral of opcode_decoder is
function pc(A : std_logic;
OP : std_logic_vector(2 downto 0)) return std_logic_vector is
begin
if (A = '1') then return OP;
else return PC_NEXT;
end if;
end;
function hadr( A : std_logic;
ADR : std_logic_vector(4 downto 0)) return std_logic_vector is
begin
return ADR(4 downto 1) & A;
end;
function mix(A : std_logic) return std_logic_vector is
begin
if (A = '1') then return ALU_X_MIX_Y;
else return ALU_MOVE_Y;
end if;
end;
function sp(A : std_logic;
OP : SP_OP) return SP_OP is
begin
if (A = '1') then return OP;
else return SP_NOP;
end if;
end;
signal LAST : cycle;
signal ENABLE_INT : std_logic;
signal DISABLE_INT : std_logic;
signal DISABLE_CNT : std_logic_vector(3 downto 0);
signal HALT_REQ : std_logic;
signal UNHALT_REQ : std_logic;
signal HALTED : std_logic;
signal INT_M1 : std_logic;
signal INT_M2 : std_logic;
begin
LAST_M <= '1' when (OP_CYC = LAST) else '0';
HLT <= HALTED; -- show when CPU is halted
-- HLT <= '1' when DISABLE_CNT = 0 else '0'; -- show when ints enabled
process(CLK_I, CLR)
begin
if (CLR = '1') then
DISABLE_CNT <= "0001"; -- 1 x disabled
INT_M2 <= '0';
HALTED <= '0';
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
if (DISABLE_INT = '1') then
DISABLE_CNT <= DISABLE_CNT + 1;
elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
DISABLE_CNT <= DISABLE_CNT - 1;
end if;
if (UNHALT_REQ = '1') then
HALTED <= '0';
elsif (HALT_REQ = '1') then
HALTED <= '1';
end if;
INT_M2 <= INT_M1;
end if;
end process;
process(OPCODE, OP_CYC, INT, RRZ, INT_M2, DISABLE_CNT, HALTED)
variable IS_M1 : std_logic;
variable IS_M2, IS_M1_M2 : std_logic;
variable IS_M3, IS_M2_M3 : std_logic;
variable IS_M4, IS_M3_M4 : std_logic;
variable IS_M5 : std_logic;
begin
if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if;
if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if;
if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if;
if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if;
if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if;
IS_M1_M2 := IS_M1 or IS_M2;
IS_M2_M3 := IS_M2 or IS_M3;
IS_M3_M4 := IS_M3 or IS_M4;
-- default: NOP
--
OP_CAT <= undef;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_OP <= "00000";
D_SA <= "00000";
D_SMQ <= '0';
D_WE_RR <= '0';
D_WE_LL <= '0';
D_WE_SP <= SP_NOP;
D_WE_O <= '0';
D_RD_O <= '0';
D_LOCK <= '0';
D_IO <= '0';
PC_OP <= PC_NEXT;
LAST <= M1; -- default: single cycle opcode (M1 only)
ENABLE_INT <= '0';
DISABLE_INT <= '0';
HALT_REQ <= '0';
UNHALT_REQ <= '0';
INT_M1 <= '0';
if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or
or INT_M2 = '1' ) then -- continue INT
OP_CAT <= INTR;
LAST <= M2;
INT_M1 <= IS_M1;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY0; -- PC + 0 (current PC)
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_INT);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
DISABLE_INT <= IS_M1;
UNHALT_REQ <= '1';
elsif (HALTED = '1') then
OP_CAT <= HALT_WAIT;
LAST <= M2;
PC_OP <= PC_WAIT;
elsif (OPCODE(7) = '1') then
case OPCODE(6 downto 4) is
when "010" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "011" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "100" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1;
when "101" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1; -- !! RR
when "110" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UQ;
D_WE_LL <= IS_M1;
when "111" =>
case OPCODE(3 downto 0) is
when "0100" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0101" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "0110" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0111" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1000" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "1001" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1010" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3; -- SEQ sets RR !
when "1011" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2; -- SEQ sets RR !
when "1100" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_LL <= IS_M3;
when "1101" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_LL <= IS_M2;
when others => -- undefined
end case;
when others => -- undefined
end case;
else
case OPCODE(6 downto 0) is
-- 00000000000000000000000000000000000000000000000000000000000000000000
when "0000000" =>
OP_CAT <= HALT;
HALT_REQ <= '1';
PC_OP <= PC_WAIT;
when "0000001" =>
OP_CAT <= NOP;
when "0000010" =>
OP_CAT <= JMP_i;
LAST <= M3;
PC_OP <= pc(IS_M2, PC_JMP);
when "0000011" =>
OP_CAT <= JMP_RRNZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and not RRZ, PC_JMP);
when "0000100" =>
OP_CAT <= JMP_RRZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and RRZ, PC_JMP);
when "0000101" =>
OP_CAT <= CALL_i;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY3; -- PC + 3
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M2, PC_JMP);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000110" =>
OP_CAT <= CALL_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY1; -- PC + 1
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_JPRR);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000111" | "1111000" =>
if (OPCODE(0) = '1') then
OP_CAT <= RET;
else
OP_CAT <= RETI;
ENABLE_INT <= IS_M1;
end if;
LAST <= M5;
D_SA <= ADR_SPi; -- read address: (SP)+
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
case OP_CYC is
when M1 => PC_OP <= PC_WAIT;
when M2 => PC_OP <= PC_WAIT;
when M3 => PC_OP <= PC_RETL;
when M4 => PC_OP <= PC_RETH;
when others =>
end case;
when "0001000" =>
OP_CAT <= MOVE_SPi_RR;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
LAST <= M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_RR <= IS_M2_M3;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_OP <= mix(IS_M3);
when "0001001" =>
OP_CAT <= MOVE_SPi_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
when "0001010" =>
OP_CAT <= MOVE_SPi_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_RR <= IS_M2;
when "0001011" =>
OP_CAT <= MOVE_SPi_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_WE_LL <= IS_M2_M3;
D_OP <= mix(IS_M3);
when "0001100" =>
OP_CAT <= MOVE_SPi_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001101" =>
OP_CAT <= MOVE_SPi_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001110" =>
OP_CAT <= MOVE_RR_dSP;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
D_SMQ <= IS_M1;
when "0001111" =>
OP_CAT <= MOVE_R_dSP;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_WE_SP <= SP_LOAD;
-- 11111111111111111111111111111111111111111111111111111111111111111111
when "0010000" =>
OP_CAT <= AND_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010001" =>
OP_CAT <= AND_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010010" =>
OP_CAT <= OR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010011" =>
OP_CAT <= OR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010100" =>
OP_CAT <= XOR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010101" =>
OP_CAT <= XOR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010110" =>
OP_CAT <= SEQ_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010111" =>
OP_CAT <= SEQ_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011000" =>
OP_CAT <= SNE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011001" =>
OP_CAT <= SNE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011010" =>
OP_CAT <= SGE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011011" =>
OP_CAT <= SGE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011100" =>
OP_CAT <= SGT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011101" =>
OP_CAT <= SGT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011110" =>
OP_CAT <= SLE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011111" =>
OP_CAT <= SLE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
-- 22222222222222222222222222222222222222222222222222222222222222222222
when "0100000" =>
OP_CAT <= SLT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100001" =>
OP_CAT <= SLT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0100010" =>
OP_CAT <= SHS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100011" =>
OP_CAT <= SHS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100100" =>
OP_CAT <= SHI_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100101" =>
OP_CAT <= SHI_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100110" =>
OP_CAT <= SLS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100111" =>
OP_CAT <= SLS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101000" =>
OP_CAT <= SLO_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0101001" =>
OP_CAT <= SLO_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101010" =>
OP_CAT <= ADD_SP_I;
LAST <= M3; -- wait for ##
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_16SP_L;
D_WE_SP <= sp(IS_M2, SP_LOAD);
when "0101011" =>
OP_CAT <= ADD_SP_I;
LAST <= M2; -- wait for #
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_8SP_L;
D_WE_SP <= sp(IS_M1, SP_LOAD);
when "0101100" =>
OP_CAT <= CLRW_dSP;
LAST <= M2;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_LOCK <= IS_M1;
D_WE_SP <= SP_LOAD;
PC_OP <= pc(IS_M1, PC_WAIT);
when "0101101" =>
OP_CAT <= CLRB_dSP;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1;
D_WE_SP <= SP_LOAD;
when "0101110" =>
OP_CAT <= IN_ci_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_IO;
D_RD_O <= IS_M1;
D_IO <= IS_M1;
D_WE_RR <= IS_M2;
when "0101111" =>
OP_CAT <= OUT_R_ci;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_IO;
D_WE_O <= IS_M1;
D_IO <= IS_M1;
-- 33333333333333333333333333333333333333333333333333333333333333333333
when "0110000" =>
OP_CAT <= AND_LL_RR;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110001" =>
OP_CAT <= OR_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110010" =>
OP_CAT <= XOR_LL_RR;
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110011" =>
OP_CAT <= SEQ_LL_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110100" =>
OP_CAT <= SNE_LL_RR;
D_OP <= ALU_X_NE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110101" =>
OP_CAT <= SGE_LL_RR;
D_OP <= ALU_X_GE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110110" =>
OP_CAT <= SGT_LL_RR;
D_OP <= ALU_X_GT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110111" =>
OP_CAT <= SLE_LL_RR;
D_OP <= ALU_X_LE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111000" =>
OP_CAT <= SLT_LL_RR;
D_OP <= ALU_X_LT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111001" =>
OP_CAT <= SHS_LL_RR;
D_OP <= ALU_X_HS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111010" =>
OP_CAT <= SHI_LL_RR;
D_OP <= ALU_X_HI_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111011" =>
OP_CAT <= SLS_LL_RR;
D_OP <= ALU_X_LS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111100" =>
OP_CAT <= SLO_LL_RR;
D_OP <= ALU_X_LO_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111101" =>
OP_CAT <= LNOT_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "0111110" =>
OP_CAT <= NEG_RR;
D_OP <= ALU_NEG_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111111" =>
OP_CAT <= NOT_RR;
D_OP <= ALU_NOT_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
-- 44444444444444444444444444444444444444444444444444444444444444444444
when "1000000" =>
OP_CAT <= MOVE_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "1000001" =>
OP_CAT <= MOVE_LL_cRR;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000010" =>
OP_CAT <= MOVE_L_cRR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= ADR_cRR_L;
D_WE_O <= IS_M1;
when "1000011" =>
OP_CAT <= MOVE_RR_LL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_LL <= IS_M1;
when "1000100" =>
OP_CAT <= MOVE_RR_cLL;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cLL_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000101" =>
OP_CAT <= MOVE_R_cLL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_cLL_L;
D_WE_O <= IS_M1;
when "1000110" =>
OP_CAT <= MOVE_cRR_RR;
LAST <= M3;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_WE_RR <= not IS_M1; -- M2 or M3
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
when "1000111" =>
OP_CAT <= MOVE_cRR_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001000" =>
OP_CAT <= MOVE_cRR_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001001" =>
OP_CAT <= MOVE_ci_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
when "1001010" =>
OP_CAT <= MOVE_ci_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001011" =>
OP_CAT <= MOVE_ci_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001100" =>
OP_CAT <= MOVE_ci_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1001101" =>
OP_CAT <= MOVE_ci_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001110" =>
OP_CAT <= MOVE_ci_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001111" =>
OP_CAT <= MOVE_RR_SP;
D_SA <= ADR_cRR_L;
D_WE_SP <= SP_LOAD;
-- 55555555555555555555555555555555555555555555555555555555555555555555
when "1010000" =>
-- spare
when "1010001" =>
-- spare
when "1010010" =>
OP_CAT <= LSL_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010011" =>
OP_CAT <= ASR_RR_i;
LAST <= M2;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010100" =>
OP_CAT <= LSR_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010101" =>
OP_CAT <= LSL_LL_RR;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010110" =>
OP_CAT <= ASR_LL_RR;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010111" =>
OP_CAT <= LSR_LL_RR;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011000" =>
OP_CAT <= ADD_LL_RR;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011001" =>
OP_CAT <= SUB_LL_RR;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011010" =>
OP_CAT <= MOVE_RR_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011011" =>
OP_CAT <= MOVE_R_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_cI16_L;
D_WE_O <= IS_M2;
when "1011100" => -- long offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011101" => -- short offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1011110" => -- long offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_16SP_L;
D_WE_O <= IS_M2;
D_OP <= ALU_X_OR_Y;
when "1011111" => -- short offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_8SP_L;
D_WE_O <= IS_M1;
D_OP <= ALU_X_OR_Y;
-- 66666666666666666666666666666666666666666666666666666666666666666666
when "1100000" => -- long offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M3_M4);
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_RR <= IS_M3_M4;
when "1100001" => -- short offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_RR <= IS_M2_M3;
when "1100010" => -- long offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100011" => -- short offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100100" => -- long offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100101" => -- short offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100110" => -- long offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_8SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1100111" => -- short offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_LL <= IS_M2_M3;
when "1101000" => -- long offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101001" => -- short offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101010" => -- long offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101011" => -- short offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101100" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "1101101" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1101110" =>
OP_CAT <= MOVE_dRR_dLL;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_dRR;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
when "1101111" =>
OP_CAT <= MOVE_RRi_LLi;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_RRi;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
-- 77777777777777777777777777777777777777777777777777777777777777777777
when "1110000" =>
OP_CAT <= MUL_IS;
D_OP <= ALU_MUL_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110001" =>
OP_CAT <= MUL_IU;
D_OP <= ALU_MUL_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110010" =>
OP_CAT <= DIV_IS;
D_OP <= ALU_DIV_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110011" =>
OP_CAT <= DIV_IU;
D_OP <= ALU_DIV_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110100" =>
OP_CAT <= MD_STEP;
D_OP <= ALU_MD_STP;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110101" =>
OP_CAT <= MD_FIN;
D_OP <= ALU_MD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110110" =>
OP_CAT <= MOD_FIN;
D_OP <= ALU_MOD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110111" =>
OP_CAT <= EI;
ENABLE_INT <= IS_M1;
when "1111001" =>
OP_CAT <= DI;
DISABLE_INT <= IS_M1;
-- undefined --------------------------------------------------------
when others =>
end case;
end if;
end process;
end Behavioral;
| mit | fe9c281200a2c8f2f96d9f0929d4398d | 0.422686 | 2.217849 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/std_ovl_components.vhd | 1 | 12,949 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
package std_ovl_components is
------------------------------------------------------------------------------
-- ovl_always
------------------------------------------------------------------------------
component ovl_always
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_always;
------------------------------------------------------------------------------
-- ovl_never
------------------------------------------------------------------------------
component ovl_never
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_never;
------------------------------------------------------------------------------
-- ovl_next
------------------------------------------------------------------------------
component ovl_next
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : positive := 1;
check_overlapping : ovl_chk_overlap := OVL_CHK_OVERLAP_OFF;
check_missing_start : ovl_ctrl := OVL_OFF;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
start_event : in std_logic;
test_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_next;
------------------------------------------------------------------------------
-- ovl_cycle_sequence
------------------------------------------------------------------------------
component ovl_cycle_sequence
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : ovl_positive_2 := 2;
necessary_condition : ovl_necessary_condition := OVL_TRIGGER_ON_MOST_PIPE;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
event_sequence : in std_logic_vector(num_cks - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_cycle_sequence;
------------------------------------------------------------------------------
-- ovl_zero_one_hot
------------------------------------------------------------------------------
component ovl_zero_one_hot
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_zero_one_hot;
------------------------------------------------------------------------------
-- ovl_range
------------------------------------------------------------------------------
component ovl_range
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
min : natural := 0;
max : natural := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_range;
------------------------------------------------------------------------------
-- ovl_one_hot
------------------------------------------------------------------------------
component ovl_one_hot
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_one_hot;
------------------------------------------------------------------------------
-- ovl_never_unknown
------------------------------------------------------------------------------
component ovl_never_unknown
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
qualifier : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_never_unknown;
------------------------------------------------------------------------------
-- ovl_never_unknown_async
------------------------------------------------------------------------------
component ovl_never_unknown_async
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_never_unknown_async;
------------------------------------------------------------------------------
-- ovl_implication
------------------------------------------------------------------------------
component ovl_implication
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
antecedent_expr : in std_logic;
consequent_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_implication;
end package std_ovl_components;
| mit | b9d0087152e6052a303abed3f3b2e213 | 0.446289 | 4.03773 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/sinewave/sine_rom.vhd | 1 | 3,973 | -- Returns the sine of a value from 0 to 1 (scaled as - to sine_addr_max)
--
-- The lookup table actually stores the first quarter of each sine wave, so
-- this entity transforms the stored first quarter to be able to calculate the
-- sine of any quarter of the wave. The following graph shoes the relation
-- between inputs to the entity (x axis) and outputs from the module (y axis)
--
-- y=1.0
-- | -------------
-- | / \
-- | / \
-- | / \
-- |/ \
-- |--------------------------------------------
-- | \ /
-- | \ /
-- | \ /
-- | \-------------/
-- |<---a---->|<---b---->|<---c---->|<---d---->|
-- x=0 0.25 0.5 0.75 1
-- y=-1
--
-- In Section a, the output value is directly read from the LUT.
-- In Section b, the output value is directly read but the LUT is indexed by 0.25-x
-- In Section c, the LUT output is negates and the LUT is indexed by x-0.5
-- In Section d, the LUT output is negates and the LUT is indexed by 0.75-x
--
-- The implementation is gently pipelined.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.sine_lut_pkg.all;
use virtual_button_lib.utils.all;
entity sine_rom is
port(
ctrl : in ctrl_t;
read_address_d0 : in integer range 0 to sine_addr_max;
read_out_d1 : out signed(15 downto 0)
);
end;
architecture rtl of sine_rom is
signal sine_rom : sine_lut_arr := calc_sine_lut;
attribute ram_style : string;
attribute ram_style of sine_rom : signal is "block";
constant address_width : integer := integer(ceil(log2(real(sine_addr_max))));
signal read_address_d1 : integer range 0 to sine_addr_max;
signal read_address_int_d0 : integer range 0 to sine_lut_bram_depth - 1;
signal negative_read_out_int_d1 : signed(lut_width - 1 downto 0);
signal read_out_int_d1 : signed(lut_width - 1 downto 0);
type modes is (normal_inc, normal_dec, inv_inc, inv_dec);
--signal mode : modes;
function calc_mode(read_address : in integer range 0 to sine_addr_max) return modes is
begin
if read_address < sine_lut_bram_depth then
return normal_inc;
elsif read_address < 2 * sine_lut_bram_depth then
return normal_dec;
elsif read_address < 3 * sine_lut_bram_depth then
return inv_inc;
else
return inv_dec;
end if;
end;
begin
negative_read_out_int_d1 <= -read_out_int_d1;
delay_read_address : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_address_d1 <= read_address_d0;
end if;
end process;
ram_proc : process (read_address_d0) is
--variable mode : modes;
begin
--if rising_edge(ctrl.clk) then
if calc_mode(read_address_d0) = normal_inc then
read_address_int_d0 <= read_address_d0;
elsif calc_mode(read_address_d0) = normal_dec then
read_address_int_d0 <= (sine_lut_bram_depth * 2) - 1 - read_address_d0;
elsif calc_mode(read_address_d0) = inv_inc then
read_address_int_d0 <= read_address_d0 - (2 * sine_lut_bram_depth);
else
read_address_int_d0 <= (sine_lut_bram_depth * 4) - 1 - read_address_d0;
end if;
--end if;
end process;
ram_read_proc : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_out_int_d1 <= sine_rom(read_address_int_d0);
end if;
end process;
assign_outputs : process(read_address_d1, read_out_int_d1, negative_read_out_int_d1)
variable mode : modes;
begin
mode := calc_mode(read_address_d1);
if mode = normal_inc or mode = normal_dec then
read_out_d1 <= read_out_int_d1;
else
read_out_d1 <= negative_read_out_int_d1;
end if;
end process;
end;
| bsd-2-clause | 00709451a981ed48ee06155cbdceec5d | 0.592248 | 3.230081 | false | false | false | false |
SDRG-UCT/RHINO_CALF | ethernet-io/UDP_1GbE_if.vhd | 1 | 10,234 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:01 04/27/2015
-- Design Name:
-- Module Name: UDP_1Gbe_Core - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity UDP_1GbE_if is
port(
GIGE_COL : in std_logic;
GIGE_CRS : in std_logic;
GIGE_MDC : out std_logic;
GIGE_MDIO : inout std_logic;
GIGE_TX_CLK : in std_logic;
GIGE_nRESET : out std_logic;
GIGE_RXD : in std_logic_vector( 7 downto 0 );
GIGE_RX_CLK : in std_logic;
GIGE_RX_DV : in std_logic;
GIGE_RX_ER : in std_logic;
GIGE_TXD : out std_logic_vector( 7 downto 0 );
GIGE_GTX_CLK : out std_logic;
GIGE_TX_EN : out std_logic;
GIGE_TX_ER : out std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst_i : in std_logic
);
end UDP_1GbE_if;
architecture Behavioral of UDP_1GbE_if is
---------------------------------------------------------------------------
-- Signal declaration section
---------------------------------------------------------------------------
attribute S: string;
attribute keep : string;
attribute S of GIGE_RXD : signal is "TRUE";
attribute S of GIGE_RX_DV : signal is "TRUE";
attribute S of GIGE_RX_ER : signal is "TRUE";
-- define constants
constant UDP_TX_DATA_BYTE_LENGTH : integer := 128;
constant UDP_RX_DATA_BYTE_LENGTH : integer := 37;
constant TX_DELAY : integer := 10;
-- system control
signal clk_125mhz : std_logic;
signal clk_100mhz : std_logic;
signal clk_25mhz : std_logic;
signal clk_6_25mhz : std_logic;
signal clk_3_125mhz : std_logic;
signal reset : std_logic;
-- MAC signals
signal udp_tx_pkt_data : std_logic_vector (8 * UDP_TX_DATA_BYTE_LENGTH - 1 downto 0);
signal udp_tx_pkt_vld : std_logic;
signal udp_tx_pkt_sent : std_logic;
signal udp_tx_pkt_vld_r : std_logic;
signal udp_tx_rdy : std_logic;
signal udp_rx_pkt_data : std_logic_vector(8 * UDP_RX_DATA_BYTE_LENGTH - 1 downto 0);
signal udp_rx_pkt_data_r: std_logic_vector(8 * UDP_RX_DATA_BYTE_LENGTH - 1 downto 0);
signal udp_rx_pkt_req : std_logic;
signal udp_rx_rdy : std_logic;
signal udp_rx_rdy_r : std_logic;
signal dst_mac_addr : std_logic_vector(47 downto 0);
signal tx_state : std_logic_vector(2 downto 0) := "000";
signal rx_state : std_logic_vector(2 downto 0) := "000";
signal locked : std_logic;
signal mac_init_done : std_logic;
signal GIGE_GTX_CLK_r : std_logic;
signal GIGE_MDC_r : std_logic;
signal tx_delay_cnt : integer := 0;
---------------------------------------------------------------------------
-- Component declaration section
---------------------------------------------------------------------------
component UDP_1GbE is
generic(
UDP_TX_DATA_BYTE_LENGTH : natural := 1;
UDP_RX_DATA_BYTE_LENGTH : natural:= 1
);
port(
-- user logic interface
own_ip_addr : in std_logic_vector (31 downto 0);
own_mac_addr : in std_logic_vector (47 downto 0);
dst_ip_addr : in std_logic_vector (31 downto 0);
dst_mac_addr : out std_logic_vector(47 downto 0);
udp_src_port : in std_logic_vector (15 downto 0);
udp_dst_port : in std_logic_vector (15 downto 0);
udp_tx_pkt_data : in std_logic_vector (8 * UDP_TX_DATA_BYTE_LENGTH - 1 downto 0);
udp_tx_pkt_vld : in std_logic;
udp_tx_rdy : out std_logic;
udp_rx_pkt_data : out std_logic_vector(8 * UDP_RX_DATA_BYTE_LENGTH - 1 downto 0);
udp_rx_pkt_req : in std_logic;
udp_rx_rdy : out std_logic;
mac_init_done : out std_logic;
udp_tx_clk_66mhz : out std_logic;
-- MAC interface
GIGE_COL : in std_logic;
GIGE_CRS : in std_logic;
GIGE_MDC : out std_logic;
GIGE_MDIO : inout std_logic;
GIGE_TX_CLK : in std_logic;
GIGE_nRESET : out std_logic;
GIGE_RXD : in std_logic_vector( 7 downto 0 );
GIGE_RX_CLK : in std_logic;
GIGE_RX_DV : in std_logic;
GIGE_RX_ER : in std_logic;
GIGE_TXD : out std_logic_vector( 7 downto 0 );
GIGE_GTX_CLK : out std_logic;
GIGE_TX_EN : out std_logic;
GIGE_TX_ER : out std_logic;
-- system control
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst_i : in std_logic;
debug : out std_logic_vector(2 downto 0)
);
end component UDP_1GbE;
---------------------------------------------------------------------------
-- DUBUGGING SECTION
---------------------------------------------------------------------------
component icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
component ila0
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(299 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
component ila1
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
signal control0 : std_logic_vector(35 downto 0);
signal control1 : std_logic_vector(35 downto 0);
signal ila_data0 : std_logic_vector(299 downto 0);
signal ila_data1 : std_logic_vector(63 downto 0);
signal trig0 : std_logic_vector(7 downto 0);
signal trig1 : std_logic_vector(7 downto 0);
---------------------------------------------------------------------------
-- END OF DUBUGGING SECTION
---------------------------------------------------------------------------
begin
UDP_1GbE_inst : UDP_1GbE
generic map(
UDP_TX_DATA_BYTE_LENGTH => UDP_TX_DATA_BYTE_LENGTH,
UDP_RX_DATA_BYTE_LENGTH => UDP_RX_DATA_BYTE_LENGTH
)
port map(
-- user logic interface
own_ip_addr => x"c0a80003",
own_mac_addr => x"0024ba7d1d70",
dst_ip_addr => x"c0a80001",
dst_mac_addr => dst_mac_addr,
udp_src_port => x"26CA", --9930
udp_dst_port => x"26CA",
udp_tx_pkt_data => udp_tx_pkt_data,
udp_tx_pkt_vld => udp_tx_pkt_vld,
udp_tx_rdy => udp_tx_rdy,
udp_rx_pkt_data => udp_rx_pkt_data,
udp_rx_pkt_req => udp_rx_pkt_req,
udp_rx_rdy => udp_rx_rdy,
mac_init_done => mac_init_done,
udp_tx_clk_66mhz => clk_100mhz,
-- MAC interface
GIGE_COL => GIGE_COL,
GIGE_CRS => GIGE_CRS,
GIGE_MDC => GIGE_MDC,
GIGE_MDIO => GIGE_MDIO,
GIGE_TX_CLK => GIGE_TX_CLK,
GIGE_nRESET => GIGE_nRESET,
GIGE_RXD => GIGE_RXD,
GIGE_RX_CLK => GIGE_RX_CLK,
GIGE_RX_DV => GIGE_RX_DV,
GIGE_RX_ER => GIGE_RX_ER,
GIGE_TXD => GIGE_TXD,
GIGE_GTX_CLK => GIGE_GTX_CLK,
GIGE_TX_EN => GIGE_TX_EN,
GIGE_TX_ER => GIGE_TX_ER,
-- system control
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst_i => sys_rst_i
);
-----------------------------------------------------------------------
-- UDP TRANSMISSION SECTION
-----------------------------------------------------------------------
tx_proc : process(sys_rst_i,clk_100mhz)
begin
if(sys_rst_i = '1') then
elsif(rising_edge(clk_100mhz)) then
case tx_state is
when "000" =>
tx_delay_cnt <= 0;
if(udp_tx_rdy = '1') then
tx_state <= "001";
end if;
when "001" =>
if(udp_tx_rdy = '1') then
if(tx_delay_cnt = TX_DELAY) then
tx_delay_cnt <= 0;
udp_tx_pkt_vld_r <= '0';--'1';
udp_tx_pkt_data <= x"4833657a4769385670795139574134754e6563334e794d57685a4f5a346872697656315869796a71366a51463437525241333034734a72486567726f4d6f6c34486a4b4467696f484f6f67486d3073364b505348305a734f6a464a4b554d4e44775071416f526e4266366d50544c736c51736c78596b36335a584375666b3535";
else
udp_tx_pkt_vld_r <= '0';
tx_delay_cnt <= tx_delay_cnt + 1;
end if;
else
tx_state <= "000";
end if;
when others =>
null;
end case;
end if;
end process;
udp_tx_pkt_vld <= udp_tx_pkt_vld_r;
-----------------------------------------------------------------------
-- UDP RECEPTION SECTION
-----------------------------------------------------------------------
rx_proc : process(sys_rst_i,clk_100mhz)
begin
if(sys_rst_i = '1') then
elsif(rising_edge(clk_100mhz)) then
case rx_state is
when "000" =>
udp_rx_pkt_req <= '1';
udp_rx_rdy_r <= udp_rx_rdy;
rx_state <= "001";
when "001" =>
if(udp_rx_rdy = '1') then
udp_rx_pkt_data_r <= udp_rx_pkt_data;
udp_rx_rdy_r <= udp_rx_rdy;
rx_state <= "010";
end if;
when "010" =>
udp_rx_pkt_data_r <= (others => '0');
rx_state <= "000";
udp_rx_rdy_r <= udp_rx_rdy;
when others =>
null;
end case;
end if;
end process;
-----------------------------------------------------------------------
-- DEBUGGING SECTION
-----------------------------------------------------------------------
-- icon_inst : icon
-- port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1);
-- ila0_inst : ila0
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_100mhz,
-- DATA => ila_data0,
-- TRIG0 => TRIG0);
-- ila1_inst : ila1
-- port map (
-- CONTROL => CONTROL1,
-- CLK => clk_125mhz,
-- DATA => ila_data1,
-- TRIG0 => TRIG1);
-- ila_data0(0) <= udp_rx_rdy_r;
-- ila_data0(1) <= udp_rx_pkt_req;
-- ila_data0(297 downto 2) <= udp_rx_pkt_data_r;
-- trig0(0) <= udp_rx_rdy;
end Behavioral;
| gpl-3.0 | 34845d31ff80dfa70fb9f8dad932f863 | 0.530291 | 2.893412 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/scc_process2.vhd | 1 | 3,278 | -- Author: Osama G. Attia
-- email: ogamal [at] iastate dot edu
-- Create Date: 16:57:25 06/23/2014
-- Module Name: scc_process2 - Behavioral
-- Description: Request rInfo[id] and SCC[id]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity scc_process2 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- Process 2 information
p2_done : out std_logic;
p2_count : out unsigned(63 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
rgraph_info : in std_logic_vector(63 downto 0);
scc_results : in std_logic_vector(63 downto 0);
-- Process 2 information
p1_done : in std_logic;
p1_count : in unsigned(63 downto 0);
-- Process 2 SCC req queue signals
p2_scc_req_almost_full : in std_logic;
p2_scc_req_wr_en : out std_logic;
p2_scc_req_din : out std_logic_vector(63 downto 0);
-- Process 2 rInfo req queue signals
p2_rInfo_req_almost_full : in std_logic;
p2_rInfo_req_wr_en : out std_logic;
p2_rInfo_req_din : out std_logic_vector(63 downto 0);
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end scc_process2;
architecture Behavioral of scc_process2 is
signal count : unsigned (63 downto 0);
begin
p2_count <= count;
p2 : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p2_done <= '0';
count <= (others => '0');
p2_scc_req_wr_en <= '0';
p2_scc_req_din <= (others => '0');
p2_rInfo_req_wr_en <= '0';
p2_rInfo_req_din <= (others => '0');
else
if (enable = '1') then
-- Got process 1 response
if (p2_scc_req_almost_full = '0' and p2_rInfo_req_almost_full = '0' and mc_rsp_push = '1' and mc_rsp_rdctl(7 downto 0) = x"01") then
-- request scc[ID]
p2_scc_req_wr_en <= '1';
p2_scc_req_din <= std_logic_vector(resize(8 * unsigned(mc_rsp_data) + unsigned(scc_results), 64));
-- request rInfo[ID]
p2_rInfo_req_wr_en <= '1';
p2_rInfo_req_din <= std_logic_vector(resize(8 * unsigned(mc_rsp_data) + unsigned(rgraph_info), 64));
-- increment counter
count <= count + 1;
else
p2_scc_req_wr_en <= '0';
p2_scc_req_din <= (others => '0');
p2_rInfo_req_wr_en <= '0';
p2_rInfo_req_din <= (others => '0');
end if;
-- Process 2 is done if process 1 is done and count = p1_count
if (p1_done = '1' and count = p1_count) then
p2_done <= '1';
end if;
else
p2_done <= '0';
count <= (others => '0');
p2_scc_req_wr_en <= '0';
p2_scc_req_din <= (others => '0');
p2_rInfo_req_wr_en <= '0';
p2_rInfo_req_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 2
end Behavioral;
| apache-2.0 | fc2de4fb1034dfe76295bdbd575cefb1 | 0.542404 | 2.820998 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/uart/uart_tx.vhd | 1 | 3,521 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.uart_constants.all;
entity uart_tx is
port(
ctrl : in ctrl_t;
send : in std_logic;
data : in std_logic_vector (7 downto 0);
ready : out std_logic;
uart_tx : out std_logic
);
end entity;
architecture rtl of uart_tx is
type uart_tx_state_t is (uart_ready, uart_zero_counter, uart_transmit);
signal state : uart_tx_state_t;
signal uart_data : std_logic_vector (9 downto 0);
constant bit_time : time := 1.0 sec / baud_rate;
constant bit_time_clocks : integer := calc_delay_clocks(clk_period, bit_time);
signal tx_count : integer range 0 to bit_time_clocks;
signal tx_count_done : std_logic;
constant max_bit_index : integer := 9;
signal bit_index : integer range 0 to max_bit_index;
begin
uart_fsm_nextstate : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
state <= uart_ready;
else
case state is
when uart_ready =>
if send = '1' then
state <= uart_transmit;
end if;
when uart_transmit =>
if tx_count_done = '1' then
if bit_index = max_bit_index then
state <= uart_ready;
else
state <= uart_zero_counter;
end if;
end if;
when uart_zero_counter =>
state <= uart_transmit;
when others =>
state <= uart_ready;
end case;
end if;
end if;
end process;
tx_counter_ctrl : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
tx_count_done <= '0';
tx_count <= 0;
else
tx_count_done <= '0';
if state = uart_zero_counter or state = uart_ready then
tx_count <= 0;
else
if tx_count < bit_time_clocks then
tx_count <= tx_count + 1;
else
tx_count_done <= '1';
end if;
end if;
end if;
end if;
end process;
bit_index_ctrl : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
bit_index <= 0;
else
if state = uart_ready then
bit_index <= 0;
elsif state = uart_zero_counter then
bit_index <= bit_index + 1;
end if;
end if;
end if;
end process;
uart_data_latch : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
uart_data <= (9 => '1', -- Rely on optimization to not assign an ff to bit 9
others => '0'); -- or bit 0
else
if state = uart_ready then
-- stop bit, data bit, start bit
uart_data <= '1' & data & '0';
end if;
end if;
end if;
end process;
tx_bit_ctrl : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
uart_tx <= '1';
else
--There is latching behaviour for when the state is zero_counter
if state = uart_ready then
uart_tx <= '1';
elsif state = uart_transmit then
uart_tx <= uart_data(bit_index);
end if;
end if;
end if;
end process;
ready <= '1' when state = uart_ready else '0';
end architecture;
| bsd-2-clause | 8a0d1ac691bd9737326c36c6ddc38f91 | 0.540187 | 3.603889 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/legacy/std_ovl.vhd | 1 | 18,799 | -- Accellera Standard V2.3 Open Verification Library (OVL)
-- Accellera Copyright (c) 2005-2008. All rights reserved.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE std_ovl IS
constant OVL_STD_DEFINES_H : boolean := true;
constant OVL_VERSION : string := "V2.3";
-- active edges
constant OVL_NOEDGE : integer := 0;
constant OVL_POSEDGE : integer := 1;
constant OVL_NEGEDGE : integer := 2;
constant OVL_ANYEDGE : integer := 3;
-- severity level
constant OVL_FATAL : integer := 0;
constant OVL_ERROR : integer := 1;
constant OVL_WARNING : integer := 2;
constant OVL_INFO : integer := 3;
-- coverage levels
constant OVL_COVER_NONE : integer := 0;
constant OVL_COVER_SANITY : integer := 1;
constant OVL_COVER_BASIC : integer := 2;
constant OVL_COVER_CORNER : integer := 4;
constant OVL_COVER_STATISTIC : integer := 8;
constant OVL_COVER_ALL : integer := 15;
-- property type
constant OVL_ASSERT : integer := 0;
constant OVL_ASSUME : integer := 1;
constant OVL_IGNORE : integer := 2;
-- necessary condition
constant OVL_TRIGGER_ON_MOST_PIPE : integer := 0;
constant OVL_TRIGGER_ON_FIRST_PIPE : integer := 1;
constant OVL_TRIGGER_ON_FIRST_NOPIPE : integer := 2;
-- action on new start
constant OVL_IGNORE_NEW_START : integer := 0;
constant OVL_RESET_ON_NEW_START : integer := 1;
constant OVL_ERROR_ON_NEW_START : integer := 2;
-- inactive levels
constant OVL_ALL_ZEROS : integer := 0;
constant OVL_ALL_ONES : integer := 1;
constant OVL_ONE_COLD : integer := 2;
-- Global reset
signal OVL_GLOBAL_RESET : boolean := false;
signal OVL_RESET_SIGNAL : std_ulogic;
-- End of simulation
signal OVL_END_OF_SIMULATION : std_ulogic := '0';
component assert_always
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_always_on_edge
generic (
severity_level : integer := OVL_ERROR;
edge_type : integer := OVL_NOEDGE;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
sampling_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_change
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
num_cks : integer := 1;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_cycle_sequence
generic (
severity_level : integer := OVL_ERROR;
num_cks : integer := 2;
necessary_condition : integer := OVL_TRIGGER_ON_MOST_PIPE;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
event_sequence : in std_ulogic_vector(num_cks-1 downto 0)
);
end component;
component assert_decrement
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
value : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_delta
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 1;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_even_parity
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_fifo_index
generic (
severity_level : integer := OVL_ERROR;
depth : integer := 1;
push_width : integer := 1;
pop_width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL;
simultaneous_push_pop : integer := 1
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
push : in std_ulogic_vector(push_width-1 downto 0);
pop : in std_ulogic_vector(pop_width-1 downto 0)
);
end component;
component assert_frame
generic (
severity_level : integer := OVL_ERROR;
min_cks : integer := 0;
max_cks : integer := 0;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_handshake
generic (
severity_level : integer := OVL_ERROR;
min_ack_cycle : integer := 0;
max_ack_cycle : integer := 0;
req_drop : integer := 0;
deassert_count : integer := 0;
max_ack_length : integer := 0;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
req : in std_ulogic;
ack : in std_ulogic
);
end component;
component assert_implication
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
antecedent_expr : in std_ulogic;
consequent_expr : in std_ulogic
);
end component;
component assert_increment
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
value : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_never
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_never_unknown
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
qualifier : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_never_unknown_async
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_next
generic (
severity_level : integer := OVL_ERROR;
num_cks : integer := 1;
check_overlapping : integer := 1;
check_missing_start : integer := 0;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_no_overflow
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 0;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_no_transition
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
start_state : in std_ulogic_vector(width-1 downto 0);
next_state : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_no_underflow
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 0;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_odd_parity
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_one_cold
generic (
severity_level : integer := OVL_ERROR;
width : integer := 32;
inactive : integer := OVL_ONE_COLD;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_one_hot
generic (
severity_level : integer := OVL_ERROR;
width : integer := 32;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_proposition
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_quiescent_state
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
state_expr : in std_ulogic_vector(width-1 downto 0);
check_value : in std_ulogic_vector(width-1 downto 0);
sample_event : in std_ulogic
);
end component;
component assert_range
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
min : integer := 1;
max : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_time
generic (
severity_level : integer := OVL_ERROR;
num_cks : integer := 1;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_transition
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
start_state : in std_ulogic_vector(width-1 downto 0);
next_state : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_unchange
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
num_cks : integer := 1;
action_on_new_start : integer := OVL_IGNORE_NEW_START;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
component assert_width
generic (
severity_level : integer := OVL_ERROR;
min_cks : integer := 1;
max_cks : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic
);
end component;
component assert_win_change
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
end_event : in std_ulogic
);
end component;
component assert_win_unchange
generic (
severity_level : integer := OVL_ERROR;
width : integer := 1;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0);
end_event : in std_ulogic
);
end component;
component assert_window
generic (
severity_level : integer := OVL_ERROR;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic;
end_event : in std_ulogic
);
end component;
component assert_zero_one_hot
generic (
severity_level : integer := OVL_ERROR;
width : integer := 32;
property_type : integer := OVL_ASSERT;
msg : string := "VIOLATION";
coverage_level : integer := OVL_COVER_ALL
);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
test_expr : in std_ulogic_vector(width-1 downto 0)
);
end component;
END std_ovl;
| mit | 83e0ae3e40c6563a3345660d750536b9 | 0.519443 | 3.842019 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_1_d512.vhd | 1 | 103,184 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_1_d512.vhd
-- /___/ /\ Timestamp: Mon Aug 18 13:21:56 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_d512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_1_d512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_1_d512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
din : in STD_LOGIC_VECTOR ( 0 downto 0 )
);
end fifo_generator_1_d512;
architecture STRUCTURE of fifo_generator_1_d512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N13 : STD_LOGIC;
signal N7 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_6 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_47 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_109 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_126 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM_index0001 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_170 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_174 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_176 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_179 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal write_ctrl_187 : STD_LOGIC;
signal write_ctrl1_188 : STD_LOGIC;
signal write_ctrl2_189 : STD_LOGIC;
signal write_ctrl3_190 : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_6;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_109;
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM_index0001,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_6
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl2_189,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED,
DPO => N11,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl_187,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED,
DPO => N7,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl1_188,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED,
DPO => N9,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4 : RAM128X1D
port map (
WCLK => clk,
D => din(0),
WE => write_ctrl3_190,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED,
DPO => N13,
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_176,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_176
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_170
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_179
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_174,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_178
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_169,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_174
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_47,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_126,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_109
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_175,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_179,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_177,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_170,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_168,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
inst_LPM_MUX31 : LUT6
generic map(
INIT => X"EFE5EAE04F454A40"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
I1 => N9,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I3 => N11,
I4 => N7,
I5 => N13,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM_index0001
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or00001 : LUT6
generic map(
INIT => X"FA32F030FAF2F0F0"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_28,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"2F0222022F222222"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_45
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_39
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_35
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_124
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_122
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_120
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_118
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_116
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_114
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_112
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_47
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_126
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_167,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
write_ctrl : LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
O => write_ctrl_187
);
write_ctrl1 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
O => write_ctrl1_188
);
write_ctrl2 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
O => write_ctrl2_189
);
write_ctrl3 : LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_108,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
O => write_ctrl3_190
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0)
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 347731e9091e9d2d701c07da2546cd32 | 0.665898 | 2.445988 | false | false | false | false |
willtmwu/vhdlExamples | Moving Averager/datapath_averager.vhd | 1 | 10,607 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity datapath_averager is
Port ( mem_addr : in STD_LOGIC_VECTOR(5 downto 0);
window_val : in STD_LOGIC_VECTOR(1 downto 0);
overflow : out STD_LOGIC;
clk : in STD_LOGIC;
masterReset : in STD_LOGIC;
input_val : out std_logic_vector (7 downto 0);
average_val : out STD_LOGIC_VECTOR(7 downto 0));
end datapath_averager;
architecture Behavioral of datapath_averager is
type DATA_MEM is array (0 to 63) of integer range 0 to 255;
signal V : DATA_MEM := ( 12, 23, 222, 12, 231, 42, 56, 121, 78, 76,
23, 119, 12, 45, 55, 100, 21, 3, 96, 34,
67, 1, 1, 54, 133, 55, 0, 5, 88, 64,
88, 123, 123, 24, 133, 99, 25, 44, 98, 66,
200, 255, 20, 45, 255, 255, 255, 255, 255, 54,
1, 251, 49, 234, 77, 23, 33, 94, 66, 88,
222, 12, 73, 75 );
type DATA_BUFF is array (0 to 15) of integer range 0 to 255;
signal window : integer range 0 to 16 := 4;
signal fetch_addr : integer range 0 to 64 := 0;
signal layered_division : integer range 0 to 4 := 2;
signal average_buff : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
with window_val select
window <= 4 when "01",
8 when "10",
16 when "11",
4 when others;
with window_val select
layered_division <= 2 when "01",
3 when "10",
4 when "11",
2 when others;
fetch_addr <= conv_integer( IEEE.std_logic_arith.unsigned(mem_addr) );
--average_val <= average_buff;
process (clk, masterReset)
variable buffer_counter : integer range 0 to 16 := 0;
variable sum : integer range 0 to 511 := 0;
variable window_buffer : DATA_BUFF := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
variable temp : std_logic_vector( 8 downto 0);
variable layered_buffer : DATA_BUFF := ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
variable limit : integer range 0 to 4 := 0;
begin
if (masterReset = '1') then
window_buffer := (0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
layered_buffer := (0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
buffer_counter := 0;
sum := 0;
elsif (clk'event and clk = '1') then
window_buffer(buffer_counter) := V(fetch_addr);
input_val <= std_logic_vector(IEEE.numeric_std.to_unsigned(window_buffer(buffer_counter), 8));
--layered_buffer := window_buffer;
layered_buffer(0) := window_buffer(0);
layered_buffer(1) := window_buffer(1);
layered_buffer(2) := window_buffer(2);
layered_buffer(3) := window_buffer(3);
layered_buffer(4) := window_buffer(4);
layered_buffer(5) := window_buffer(5);
layered_buffer(6) := window_buffer(6);
layered_buffer(7) := window_buffer(7);
layered_buffer(8) := window_buffer(8);
layered_buffer(9) := window_buffer(9);
layered_buffer(10) := window_buffer(10);
layered_buffer(11) := window_buffer(11);
layered_buffer(12) := window_buffer(12);
layered_buffer(13) := window_buffer(13);
layered_buffer(14) := window_buffer(14);
layered_buffer(15) := window_buffer(15);
--Test
-- limit := (layered_division-1);
-- for I in 0 to 4 loop
-- if (limit >= 0) then
-- layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
-- layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
-- layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
-- layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
-- layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
-- layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
-- layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
-- layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
-- end if;
-- limit := limit - 1;
-- end loop;
if (window_val = "01") then
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
elsif (window_val = "10") then
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
elsif (window_val = "11") then
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
layered_buffer(0) := ( (layered_buffer(0) + layered_buffer(1)) /2 );
layered_buffer(1) := ( (layered_buffer(2) + layered_buffer(3)) /2 );
layered_buffer(2) := ( (layered_buffer(4) + layered_buffer(5)) /2 );
layered_buffer(3) := ( (layered_buffer(6) + layered_buffer(7)) /2 );
layered_buffer(4) := ( (layered_buffer(8) + layered_buffer(9)) /2 );
layered_buffer(5) := ( (layered_buffer(10) + layered_buffer(11)) /2 );
layered_buffer(6) := ( (layered_buffer(12) + layered_buffer(13)) /2 );
layered_buffer(7) := ( (layered_buffer(14) + layered_buffer(15)) /2 );
end if;
sum := layered_buffer(0);
--buffer_counter := 0;
buffer_counter := buffer_counter + 1;
--buffer_counter := buffer_counter mod window;
if (buffer_counter >= window) then
buffer_counter := buffer_counter - window;
end if;
temp := std_logic_vector(IEEE.numeric_std.to_unsigned(sum,9));
average_val <= temp (7 downto 0);
--overflow <= temp(8);
if ( sum = 255 ) then
overflow <= '1';
else
overflow <= '0';
end if;
end if;
end process;
--overflow <= '1' when ( average_val = "111111") else '0';
end Behavioral;
| apache-2.0 | 3120a615fdf532fc8fa59a399378e254 | 0.554445 | 2.611918 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/cygraph_master.vhd | 1 | 21,197 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Control workflow
-- Requests Multiplexer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity master is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic;
done : out std_logic;
started : out std_logic;
-- kernels communication signals
current_level : in unsigned(31 downto 0); -- Current Level
kernel_rx_vld : in std_logic;
wr_offset : in unsigned(31 downto 0);
wr_reserved_space : in unsigned(31 downto 0);
wr_used_space : out unsigned(31 downto 0);
-- Memory pointers
graphInfo : in std_logic_vector(63 downto 0);
nq_address : in std_logic_vector(63 downto 0);
reach_queue : in std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC flush signals
mc_req_flush : out std_logic;
mc_rsp_flush_cmplt : in std_logic;
-- Process 1 signals
p1_req_q_rd_enb : out std_logic;
p1_req_q_dout : in std_logic_vector(63 downto 0);
p1_req_q_valid : in std_logic;
p1_req_q_empty : in std_logic;
-- Process 2 signals
p2_req_q_rd_enb : out std_logic;
p2_req_q_dout : in std_logic_vector(63 downto 0);
p2_req_q_valid : in std_logic;
p2_req_q_empty : in std_logic;
-- Process 3 signals
p3_req_q_rd_enb : out std_logic;
p3_req_q_dout : in std_logic_vector(63 downto 0);
p3_req_q_valid : in std_logic;
p3_req_q_empty : in std_logic;
-- Process 4 signals
p4_done : in std_logic;
p4_addr_q_rd_enb : out std_logic;
p4_addr_q_dout : in std_logic_vector(63 downto 0);
p4_addr_q_valid : in std_logic;
p4_addr_q_empty : in std_logic;
p4_info_q_rd_enb : out std_logic;
p4_info_q_dout : in std_logic_vector(63 downto 0);
p4_info_q_valid : in std_logic;
p4_info_q_empty : in std_logic
);
end entity; -- Master process
architecture arch of master is
type state_type is (st_idle, st_busy, st_flush, st_done);
signal state : state_type;
type muxstatetype is (mx_start, mx_stall, mx_p1, mx_p2, mx_p3, mx_p4, mx_p5, mx_p6);
signal mux_state : muxstatetype;
signal saved_state : std_logic_vector(7 downto 0);
signal saved_addr : std_logic_vector(63 downto 0);
signal saved_data : std_logic_vector(63 downto 0);
signal used_space : unsigned(31 downto 0); -- What I consumed from the reserved space
signal local_offset : unsigned(31 downto 0);
signal pause_p4 : std_logic;
signal done_count : integer range 0 to 3;
-- debug signals
signal p2_req_count_debug : unsigned(31 downto 0);
begin
started <= '1' when state = st_busy else '0';
wr_used_space <= used_space;
-- Requests Multiplexer
-- Read from the processes' request queues with the specific tag
Master : process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
state <= st_idle;
busy <= '0';
done <= '0';
done_count <= 0;
-- reset master process control signals
pause_p4 <= '0';
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
used_space <= (others => '0');
local_offset <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
mc_req_flush <= '0';
-- reset queues read enable signals
p4_info_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
else
-- Kernel go idle
--- Reset signals
--- Wait for enable signal
if (state = st_idle) then
busy <= '0';
done_count <= 0;
-- reset master process control signals
pause_p4 <= '0';
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
used_space <= (others => '0');
local_offset <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
mc_req_flush <= '0';
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
-- If got enable signal, go busy
if (enable = '1') then
busy <= '1';
done <= '0';
done_count <= 0;
state <= st_busy;
else
busy <= '0';
state <= st_idle;
end if ;
-- Go Busy:
--- MULTIPLEX requests to memory controller
--- Set done signal if everything is done
elsif (state = st_busy) then
-- is memory controller asserting rd/wr stall?
if (mc_rd_rq_stall = '1' or mc_wr_rq_stall = '1') then
-- save addr/data
if (p1_req_q_valid = '1') then
saved_state <= x"01";
saved_addr <= p1_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p2_req_q_valid = '1') then
saved_state <= x"02";
saved_addr <= p2_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_req_q_valid = '1') then
saved_state <= x"03";
saved_addr <= p3_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p4_info_q_valid = '1' and p4_addr_q_valid = '1') then
-- Push CSR to NQ
saved_state <= x"04";
saved_data <= p4_info_q_dout;
saved_addr <= p4_addr_q_dout;
mux_state <= mx_stall;
elsif (mux_state = mx_p5) then
-- Vist node by setting CSR to current level
saved_state <= x"05";
saved_addr <= saved_addr;
saved_data <= saved_data;
mux_state <= mx_stall;
elsif (mux_state = mx_p6) then
-- Push node to reachQueue
saved_state <= x"06";
saved_addr <= saved_addr;
saved_data <= saved_data;
mux_state <= mx_stall;
else
saved_state <= saved_state;
saved_addr <= saved_addr;
saved_data <= saved_data;
mux_state <= mux_state;
end if;
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
-- If not a memory controller rd/wr stall
elsif (mc_rd_rq_stall = '0' and mc_wr_rq_stall = '0') then
if (mux_state = mx_stall) then
-- Issue a request, if comming from a stall
if (saved_state = x"01") then
-- Request from current queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"02") then
-- Request neighbors (IDs of 32-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "10";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"03") then
-- Request neighbors informations (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"04") then
-- Push CSR to Next Queue
if (used_space < wr_reserved_space and wr_reserved_space > 0) then
-- Write node CSR to next queue
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(unsigned(nq_address) + (wr_offset + local_offset) * 8, 48));
mc_req_wrd_rdctl <= saved_data;
-- reset saved state
saved_state <= x"05";
saved_addr <= saved_addr;
saved_data <= saved_data;
else
-- Reset MC
mc_req_ld <= '0';
mc_req_st <= '0';
-- keep state
saved_state <= saved_state;
saved_addr <= saved_addr;
saved_data <= saved_data;
end if;
elsif (saved_state = x"05") then
-- Visit node by setting CSR (current_level & 1)
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(8 * unsigned(saved_addr) + unsigned(graphInfo), 48)); -- CHECK HERE
mc_req_wrd_rdctl <= saved_data(63 downto 1) & '1';
-- reset saved state
saved_state <= x"06";
saved_addr <= saved_addr;
saved_data <= saved_data;
elsif (saved_state = x"06") then
-- Push node id to reachQueue
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(unsigned(reach_queue) + (wr_offset + local_offset) * 8, 48)); -- CHECK HERE
mc_req_wrd_rdctl <= saved_addr; -- Node ID -- CHECK HERE;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if;
elsif (mux_state = mx_p1 and p1_req_q_valid = '1') then
-- TODO: fix that to replace the whole code of process 1
-- Request from current queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p1_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"01";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p2 and p2_req_q_valid = '1') then
-- Request neighbors (IDs of 32-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "10";
mc_req_vaddr <= p2_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"02";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p3 and p3_req_q_valid = '1') then
-- Request neighbors informations (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p3_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"03";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p4 and p4_info_q_valid = '1' and p4_addr_q_valid = '1') then
if (used_space < wr_reserved_space and wr_reserved_space > 0) then
-- Write node CSR to next queue
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(unsigned(nq_address) + (wr_offset + local_offset) * 8, 48));
mc_req_wrd_rdctl <= p4_info_q_dout;
-- reset saved state
saved_state <= x"05";
saved_addr <= p4_addr_q_dout;
saved_data <= p4_info_q_dout;
else
-- Reset MC
mc_req_ld <= '0';
mc_req_st <= '0';
-- keep state
saved_state <= x"04";
saved_addr <= p4_addr_q_dout;
saved_data <= p4_info_q_dout;
end if;
elsif (mux_state = mx_p5) then
-- Write new CSR (current_level & 1)
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(8 * unsigned(saved_addr) + unsigned(graphInfo), 48));
mc_req_wrd_rdctl <= saved_data(63 downto 1) & '1';
-- Save information for next write request
saved_state <= x"06";
saved_addr <= saved_addr;
saved_data <= saved_data;
elsif (mux_state = mx_p6) then
-- Push node ID to reachQueue
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(unsigned(reach_queue) + (wr_offset + local_offset) * 8, 48)); -- CHECK HERE
mc_req_wrd_rdctl <= saved_addr; -- Node ID -- CHECK HERE;
-- Save information for next write request
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if; -- End mux states execution
-- Pop from queue if mux is ready
if (((mux_state = mx_start)
or (mux_state = mx_stall and saved_state /= x"04" and saved_state /= x"05")
or (mux_state = mx_p1 and p1_req_q_valid = '1')
or (mux_state = mx_p2 and p2_req_q_valid = '1')
or (mux_state = mx_p3 and p3_req_q_valid = '1')
or (mux_state = mx_p6)) and mux_state /= mx_p4) then
if (p4_addr_q_empty = '0' and p4_info_q_empty = '0' and wr_reserved_space > 0 and used_space < wr_reserved_space) then
-- If process 4 info/addr queues are not empty, make a write request
p4_addr_q_rd_enb <= '1';
p4_info_q_rd_enb <= '1';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
mux_state <= mx_p4;
elsif (p3_req_q_empty = '0') then
-- If process 3 queue isn't empty, make a read request
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '1';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
mux_state <= mx_p3;
elsif (p2_req_q_empty = '0') then
-- If process 2 queue isn't empty, make a read request
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '1';
p1_req_q_rd_enb <= '0';
mux_state <= mx_p2;
elsif (p1_req_q_empty = '0') then -- TODO: fix that to replace the whole code of process 1
-- If process 1 queue isn't empty, make a read request
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '1';
mux_state <= mx_p1;
else
-- reset
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
mux_state <= mx_start;
end if;
else
if (mux_state = mx_p4 and p4_info_q_valid = '1' and p4_addr_q_valid = '1') then
if (used_space >= wr_reserved_space or wr_reserved_space = 0) then
mux_state <= mx_stall;
else
mux_state <= mx_p5;
end if;
elsif (mux_state = mx_stall and saved_state = x"04") then
if (used_space >= wr_reserved_space or wr_reserved_space = 0) then
mux_state <= mx_stall;
else
mux_state <= mx_p5;
end if;
elsif (mux_state = mx_p5) then
mux_state <= mx_p6;
elsif (mux_state = mx_stall and saved_state = x"05") then
mux_state <= mx_p6;
else
mux_state <= mux_state;
end if;
-- reset
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
end if; -- end if mux green light!
else
-- weird case, memory controller not ready yet
mux_state <= mux_state;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
end if; -- end check for rd/wr stall
-- Update the used space count ---------------------------------------- CHECK THIS LOGIC HERE
if (used_space >= wr_reserved_space and kernel_rx_vld = '1') then
local_offset <= (others => '0');
--elsif (mc_rd_rq_stall = '0' and mc_wr_rq_stall = '0' and used_space < wr_reserved_space and wr_reserved_space > 0
--and ((mux_state = mx_stall and saved_state = x"04") or (mux_state = mx_p4 and p4_info_q_valid = '1' and p4_addr_q_valid = '1'))) then
elsif (mc_rd_rq_stall = '0' and mc_wr_rq_stall = '0' and (mux_state = mx_p6 or (mux_state = mx_stall and saved_state = x"06"))) then -- CHECK later
used_space <= used_space + 1;
local_offset <= local_offset + 1;
end if;
----- TODO #####
-- if all processes are done and queues ar eempty go done
if (p4_done = '1' and p4_addr_q_empty = '1' and p4_info_q_empty = '1' and p1_req_q_empty = '1'
and p2_req_q_empty = '1' and p3_req_q_empty = '1' and done_count < 3) then
state <= st_busy;
done_count <= done_count + 1;
mc_req_flush <= '0';
elsif (p4_done = '1' and done_count = 3) then
state <= st_flush;
done_count <= 0;
mc_req_flush <= '1';
else
state <= st_busy;
done_count <= 0;
mc_req_flush <= '0';
end if;
if (p2_req_q_valid = '1') then
p2_req_count_debug <= p2_req_count_debug + 1;
end if;
-- flush memory controller
elsif (state = st_flush) then
mc_req_flush <= '0';
if (mc_rsp_flush_cmplt = '1') then
state <= st_done;
end if;
-- Kernel is done with its part of the level
elsif (state = st_done) then
-- set done signal one and go idle
state <= st_idle;
busy <= '0';
done <= '1';
done_count <= 0;
-- reset saved state
pause_p4 <= '0';
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
used_space <= (others => '0');
local_offset <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
mc_req_flush <= '0';
-- reset queues read enable signals
p4_info_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
else
state <= st_idle;
end if; -- end if state
end if; -- end if rst
end if; -- end if clk
end process; -- Master
end architecture ; -- arch | apache-2.0 | f4956324ed8b4fc702dd29bf01cbaf60 | 0.510072 | 2.679434 | false | false | false | false |
willtmwu/vhdlExamples | Basic Logic/and2orgatemixed.vhd | 1 | 1,874 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY and2or IS
PORT(
in1,in2,in3,in4 : IN std_logic;
outandor, outandor_flow, outandor_beh : OUT std_logic
);
END and2or ;
ARCHITECTURE mixed OF and2or IS
COMPONENT and2gate
PORT(
in1 : IN std_logic;
in2 : IN std_logic;
outand : OUT std_logic
);
END COMPONENT;
COMPONENT or2gate
PORT(
in1 : IN std_logic;
in2 : IN std_logic;
outor : OUT std_logic
);
END COMPONENT;
-- need wires to connect outputs of AND gates to OR gate
SIGNAL in1or : std_logic ;
SIGNAL in2or : std_logic ;
BEGIN
--THIS IS STRUCTURAL; g1,g2,g3 form a netlist
g1: and2gate PORT MAP(
in1 => in1, --careful !! it means that in1 of g1 is connected to in1 of Entity and2or
in2 => in2, --careful !! it means that in1 of g1 is connected to in1 of Entity and2or
outand => in1or -- connected to 'wire' in1or
);
-- another (simpler) way to instantiate (port mapping by position)
g2: and2gate PORT MAP(in3, in4, in2or) ;
g3: or2gate PORT MAP(in1or, in2or, outandor) ; -- inputs wired to outputs of ANDs, otput directly to the Entity
--THIS IS SIGNAL FLOW
-- now there is a behavioural description of the same functionality, it is not in a process, and is called signal flow style
outandor_flow <= (in1 AND in2) OR (in3 AND in4) ;
--THIS IS BEHAVIOURAL/PROCESS
-- read more in your textbook
p1: PROCESS(in1,in2,in3,in4)
BEGIN
outandor_beh <= (in1 AND in2) OR (in3 AND in4);
END PROCESS ;
-- notice how much simpler it is to describe circuits in behavioural/data flow !
-- All three: signal flow, structural, and behavioural(processes) can be freely mixed.
END;
| apache-2.0 | 849b4254948fc8bbfb896e3680a356bb | 0.636073 | 3.112957 | false | false | false | false |
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II | ProgramaVHDL/MIPS-MC_SingleEdge_tb.vhd | 1 | 19,343 | -------------------------------------------------------------------------
--
-- 32 bits PROCESSOR TESTBENCH LITTLE ENDIAN 13/october/2004
--
-- It must be observed that the processor is hold in reset
-- (rstCPU <= '1') at the start of simulation, being activated
-- (rstCPU <= '0') just after the end of the object file reading be the
-- testbench.
--
-- This testbench employs two memories, implying a HARVARD organization
--
-- Changes:
-- 16/05/2012 (Ney Calazans)
-- - Corrected bug in memory filling during reset. The instruction
-- memory fill process, makes the processor produce "ce" signals to
-- memory which ended up by filling data memory with rubbish at
-- the same time. To solve this, the first line of the data memory
-- Dce control signal generation was changed from
-- -- ce='1' or go_d='1' to
-- -- (ce='1' and rstCPU/='1') or go_d='1'
-- - Also, there was a problem with the data memory write operation in
-- monocycle MIPS implementations: when multiple SW instructions
-- were issued one after the other, the write operation was executed
-- in two sets of memory positions at once after the first SW. To
-- solve this the data signal was removed from the memory write
-- process sensitivity list.
-- 10/10/2015 (Ney Calazans)
-- - Signal bw from memory set to '1', since the CPU
-- does not generate it anymore.
-- 28/10/2016 (Ney Calazans)
-- - Also, regX defs were changed to wiresX, to improve
-- code readability.
-- 02/06/2017 (Ney Calazans) - bugfix
-- - tmp_address changed to int_address in the memory definition
-- -IN the definition of the memory read/write processes,
-- CONV_INTEGER(low_address+3)<=MEMORY_SIZE was changed to
-- CONV_INTEGER(low_address)<=MEMORY_SIZE-3
-- This avoids an error that freezes the simulation when the
-- ALU contains a large number (>65533) in its output
-- immediately before an LW or SW instruction.
-------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use std.textio.all;
package aux_functions is
subtype wires32 is std_logic_vector(31 downto 0);
subtype wires16 is std_logic_vector(15 downto 0);
subtype wires8 is std_logic_vector( 7 downto 0);
subtype wires4 is std_logic_vector( 3 downto 0);
-- definio do tipo 'memory', que ser utilizado para as memrias de dados/instrues
constant MEMORY_SIZE : integer := 2048;
type memory is array (0 to MEMORY_SIZE) of wires8;
constant TAM_LINHA : integer := 200;
function CONV_VECTOR( letra : string(1 to TAM_LINHA); pos: integer ) return std_logic_vector;
procedure readFileLine(file in_file: TEXT; outStrLine: out string);
end aux_functions;
package body aux_functions is
--
-- converte um caracter de uma dada linha em um std_logic_vector
--
function CONV_VECTOR( letra:string(1 to TAM_LINHA); pos: integer ) return std_logic_vector is
variable bin: wires4;
begin
case (letra(pos)) is
when '0' => bin := "0000";
when '1' => bin := "0001";
when '2' => bin := "0010";
when '3' => bin := "0011";
when '4' => bin := "0100";
when '5' => bin := "0101";
when '6' => bin := "0110";
when '7' => bin := "0111";
when '8' => bin := "1000";
when '9' => bin := "1001";
when 'A' | 'a' => bin := "1010";
when 'B' | 'b' => bin := "1011";
when 'C' | 'c' => bin := "1100";
when 'D' | 'd' => bin := "1101";
when 'E' | 'e' => bin := "1110";
when 'F' | 'f' => bin := "1111";
when others => bin := "0000";
end case;
return bin;
end CONV_VECTOR;
procedure readFileLine(file in_file: TEXT;
outStrLine: out string) is
variable localLine: line;
variable localChar: character;
variable isString: boolean;
begin
readline(in_file, localLine);
for i in outStrLine'range loop
outStrLine(i) := ' ';
end loop;
for i in outStrLine'range loop
read(localLine, localChar, isString);
outStrLine(i) := localChar;
if not isString then -- found end of line
exit;
end if;
end loop;
end readFileLine;
end aux_functions;
--------------------------------------------------------------------------
-- Module implementing a behavioral model of an ASYNCHRONOUS INTERFACE RAM
--------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use std.textio.all;
use work.aux_functions.all;
entity RAM_mem is
generic( START_ADDRESS: wires32 := (others=>'0') );
port( ce_n, we_n, oe_n, bw: in std_logic; address: in wires32; data: inout wires32);
end RAM_mem;
architecture RAM_mem of RAM_mem is
signal RAM : memory;
signal tmp_address: wires32;
alias low_address: wires16 is tmp_address(15 downto 0); -- baixa para 16 bits devido ao CONV_INTEGER --
begin
tmp_address <= address - START_ADDRESS; -- offset do endereamento --
-- writes in memory ASYNCHRONOUSLY -- LITTLE ENDIAN -------------------
process(ce_n, we_n, low_address) -- Modification in 16/05/2012 for monocycle processors only,
begin
if ce_n='0' and we_n='0' then
if CONV_INTEGER(low_address)>=0 and CONV_INTEGER(low_address)<=MEMORY_SIZE-3 then
if bw='1' then
RAM(CONV_INTEGER(low_address+3)) <= data(31 downto 24);
RAM(CONV_INTEGER(low_address+2)) <= data(23 downto 16);
RAM(CONV_INTEGER(low_address+1)) <= data(15 downto 8);
end if;
RAM(CONV_INTEGER(low_address )) <= data( 7 downto 0);
end if;
end if;
end process;
-- read from memory
process(ce_n, oe_n, low_address)
begin
if ce_n='0' and oe_n='0' and
CONV_INTEGER(low_address)>=0 and CONV_INTEGER(low_address)<=MEMORY_SIZE-3 then
data(31 downto 24) <= RAM(CONV_INTEGER(low_address+3));
data(23 downto 16) <= RAM(CONV_INTEGER(low_address+2));
data(15 downto 8) <= RAM(CONV_INTEGER(low_address+1));
data( 7 downto 0) <= RAM(CONV_INTEGER(low_address ));
else
data(31 downto 24) <= (others=>'Z');
data(23 downto 16) <= (others=>'Z');
data(15 downto 8) <= (others=>'Z');
data( 7 downto 0) <= (others=>'Z');
end if;
end process;
end RAM_mem;
-------------------------------------------------------------------------
-----------------------------------------
-- Autores: Vinicius Cerutti e Yuri Bittencourt
-- Disciplina: Organização e arquitetura de Computadores II
-- T1 - Comunicação Serial Periférico-Processador
-- Parte do Periferico
-----------------------------------------
-- peripheral module
-- periferico trabalha na velocidade de 115200 bits por segundo
-------------------------------------------------------------------------
Library ieee;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_arith.All;
Use IEEE.std_logic_unsigned.All;
Entity periferico Is
Port (
clock : In std_logic;
reset : In std_logic;
rxd : In std_logic;
txd : Out std_logic
);
End periferico;
Architecture periferico Of periferico Is
Type State_type Is (a, c, d, e,f);
Signal State : State_type;
Signal dadoSync : std_logic_vector(10 Downto 0);
Signal result : std_logic_vector(9 Downto 0);
Type data_memInf Is Array(0 To 1) Of std_logic_vector(7 Downto 0);
Signal memInf : data_memInf := (Others => (Others => '0'));
Signal contBitsReceiver, contBitsSend : std_logic_vector (7 Downto 0);
Signal contVetor : std_logic_vector (7 Downto 0);
signal enviar_dado_sinc : std_logic := '1';
Begin
Process (reset, clock,rxd)
Begin
If (reset = '1') Then
result <= "0000000000";
dadoSync <= "00000000000";
contBitsSend <= "00000000";
contBitsReceiver <= "00000000";
contVetor<=x"00";
Elsif (clock'EVENT And clock = '1') Then
Case State Is
When a =>
-- envia dado 0x55 para sicronizacao com a interface serial
if(enviar_dado_sinc = '1') Then
contBitsSend <= x"0A";
dadoSync <= "10101010101";
State <= f;
-- os dois dados estao recebidos logo devem ser somados e
-- madandos para o periferico
elsif (contVetor = x"02") then
contBitsSend <= x"00";
result(8 Downto 1) <= memInf(0)(7 Downto 0) + memInf(1)(7 Downto 0);
result(9) <= '1';
State <= e;
-- se ainda nao recebeu os dois valores para realizar a soma
elsif (contVetor /= x"02") Then
contBitsReceiver <= x"08";
-- verifica se o primeiro bit é start bit
If (rxd = '0') Then
State <= c;
else State<=a;
End if;
end if;
-- estado que realiza o recebimento dos bits da interface serial
When c =>
If (contBitsReceiver > 1) Then
memInf(CONV_INTEGER(contVetor)) <= rxd & memInf(CONV_INTEGER(contVetor))(7 Downto 1);
contBitsReceiver <= contBitsReceiver - x"01";
State <= c;
Else
memInf(CONV_INTEGER(contVetor)) <= rxd & memInf(CONV_INTEGER(contVetor))(7 Downto 1);
contBitsReceiver <= contBitsReceiver - x"01";
State <= d;
End If;
-- estado que verifica se existe o stop bit
When d =>
If (rxd /= '0') Then
contVetor <= contVetor + x"01";
State <= a;
Else
State <= d;
End If;
-- estado para enviar os dados do periferico para
-- interface serial
When e =>
If (contBitsSend <= x"08") Then
txd <= result(CONV_INTEGER(contBitsSend));
contBitsSend <= contBitsSend + x"01";
State <= e;
Else
txd <= result(CONV_INTEGER(contBitsSend));
contVetor <= x"00";
State <= a;
end if;
-- estado para enviar o dado de sicronizacao(0x55) para
-- a interface serial
When f =>
if(enviar_dado_sinc ='1') Then
enviar_dado_sinc <='0';
End If;
If (contBitsSend >= x"01") Then
txd <= dadoSync(CONV_INTEGER(contBitsSend));
contBitsSend <= contBitsSend - x"01";
State <= f;
Else
txd <= dadoSync(CONV_INTEGER(contBitsSend));
State <= a;
end if;
When Others =>
State <= a;
End Case;
End If;
End Process;
End periferico;
-------------------------------------------------------------------------
-- CPU PROCESSOR SIMULATION TESTBENCH
-------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use STD.TEXTIO.all;
use work.aux_functions.all;
entity CPU_tb is
end CPU_tb;
architecture cpu_tb of cpu_tb is
signal Dadress, Ddata, Iadress, Idata,
i_cpu_address, d_cpu_address, data_cpu, tb_add, tb_data : wires32 := (others => '0' );
signal Dce_n, Dwe_n, Doe_n, Ice_n, Iwe_n, Ioe_n, ck, rst, rstCPU,
go_i, go_d, ce, rw, bw: std_logic;
signal mem_ce : std_logic;
signal tx_data,rx_data: std_logic_vector (7 downto 0);
signal tx_av,rx_busy, rx_start: std_logic;
signal rxd,txd,clkPeriferico: std_logic;
file ARQ : TEXT open READ_MODE is "textMips2.txt";
begin
Logica_cola: entity work.FsmLogicaCola
port map (ce => Dce_n,address=>Dadress, mem_ce=>mem_ce, rw=>rw, clock=>ck, reset=>rstCPU, tx_data=>tx_data,
rx_data=>rx_data, tx_av=> tx_av, rx_busy=>rx_busy,rx_start=>rx_start, data => Ddata);
Interface_Serial: entity work.serialinterface
port map (clock=>ck,reset=>rstCPU,rxd=>rxd,txd=>txd,rx_data=>rx_data,rx_start=>rx_start,
rx_busy => rx_busy,tx_data=>tx_data,tx_av=>tx_av
);
perifericoMap: entity work.periferico
port map(clock => clkPeriferico,reset=>rstCPU,rxd=>rxd,txd=>txd);
Data_mem: entity work.RAM_mem
generic map( START_ADDRESS => x"10010000" )
port map (ce_n=>mem_ce, we_n=>Dwe_n, oe_n=>Doe_n, bw=>bw, address=>Dadress, data=>Ddata);
Instr_mem: entity work.RAM_mem
generic map( START_ADDRESS => x"00400000" )
port map (ce_n=>Ice_n, we_n=>Iwe_n, oe_n=>Ioe_n, bw=>'1', address=>Iadress, data=>Idata);
-- data memory signals --------------------------------------------------------
Dce_n <= '0' when (ce='1' and rstCPU/='1') or go_d='1' else '1'; -- Bug corrected here in 16/05/2012
Doe_n <= '0' when (ce='1' and rw='1') else '1';
Dwe_n <= '0' when (ce='1' and rw='0') or go_d='1' else '1';
Dadress <= tb_add when rstCPU='1' else d_cpu_address;
Ddata <= tb_data when rstCPU='1' else data_cpu when (ce='1' and rw='0') else (others=>'Z');
data_cpu <= Ddata when (ce='1' and rw='1') else (others=>'Z');
-- instructions memory signals --------------------------------------------------------
Ice_n <= '0';
Ioe_n <= '1' when rstCPU='1' else '0'; -- impede leitura enquanto est escrevendo
Iwe_n <= '0' when go_i='1' else '1'; -- escrita durante a leitura do arquivo
Iadress <= tb_add when rstCPU='1' else i_cpu_address;
Idata <= tb_data when rstCPU='1' else (others => 'Z');
cpu: entity work.MIPS_MCS port map(
clock=>ck, reset=>rstCPU,
i_address => i_cpu_address,
instruction => Idata,
ce=>ce, rw=>rw, bw=>bw,
d_address => d_cpu_address,
data => data_cpu
);
rst <='1', '0' after 15 ns; -- generates the reset signal
process -- generates the clock signal
begin
ck <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process -- generates the clock signal for peripheral
begin
clkPeriferico <= '1', '0' after 4.34 us;
wait for 8.68 us;
end process;
----------------------------------------------------------------------------
-- this process loads the instruction memory and the data memory during reset
--
--
-- O PROCESSO ABAIXO UMA PARSER PARA LER CDIGO GERADO PELO SPIM NO
-- SEGUINTE FORMATO:
--
-- Text Segment
-- [0x00400000] 0x3c011001 lui $1, 4097 [d2] ; 16: la $t0, d2
-- [0x00400004] 0x34280004 ori $8, $1, 4 [d2]
-- [0x00400008] 0x8d080000 lw $8, 0($8) ; 17: lw $t0,0($t0)
-- .....
-- [0x00400048] 0x0810000f j 0x0040003c [loop] ; 30: j loop
-- [0x0040004c] 0x01284821 addu $9, $9, $8 ; 32: addu $t1, $t1, $t0
-- [0x00400050] 0x08100014 j 0x00400050 [x] ; 34: j x
-- Data Segment
-- [0x10010000] 0x0000faaa 0x00000083 0x00000000 0x00000000
--
----------------------------------------------------------------------------
process
variable ARQ_LINE : LINE;
variable line_arq : string(1 to TAM_LINHA);
variable code : boolean;
variable i, address_flag : integer;
begin
go_i <= '0';
go_d <= '0';
rstCPU <= '1'; -- hold the processor during file reading
code:=true; -- default value of code is 1 (CODE)
wait until rst = '1';
while NOT (endfile(ARQ)) loop -- INCIO DA LEITURA DO ARQUIVO CONTENDO INSTRUO E DADOS -----
--readline(ARQ, ARQ_LINE);
--read(ARQ_LINE, line_arq(1 to ARQ_LINE'length) );
readFileLine(ARQ, line_arq);
if line_arq(1 to 12)="Text Segment" then
code:=true; -- code
elsif line_arq(1 to 12)="Data Segment" then
code:=false; -- data
else
i := 1; -- LEITORA DE LINHA - analizar o loop abaixo para compreender
address_flag := 0; -- para INSTRUO um para (end,inst)
-- para DADO aceita (end, dado 0, dado 1, dado 2 ....)
loop
if line_arq(i) = '0' and line_arq(i+1) = 'x' then -- encontrou indicao de nmero hexa: '0x'
i := i + 2;
if address_flag=0 then
for w in 0 to 7 loop
tb_add( (31-w*4) downto (32-(w+1)*4)) <= CONV_VECTOR(line_arq,i+w);
end loop;
i := i + 8;
address_flag := 1;
else
for w in 0 to 7 loop
tb_data( (31-w*4) downto (32-(w+1)*4)) <= CONV_VECTOR(line_arq,i+w);
end loop;
i := i + 8;
wait for 0.1 ns;
if code=true then go_i <= '1'; -- the go_i signal enables instruction memory writing
else go_d <= '1'; -- the go_d signal enables data memory writing
end if;
wait for 0.1 ns;
tb_add <= tb_add + 4; -- *great!* consigo ler mais de uma word por linha!
go_i <= '0';
go_d <= '0';
address_flag := 2; -- sinaliza que j leu o contedo do endereo;
end if;
end if;
i := i + 1;
-- sai da linha quando chegou no seu final OU j leu par(endereo, instruo) no caso de cdigo
exit when i=TAM_LINHA or (code=true and address_flag=2);
end loop;
end if;
end loop; -- FINAL DA LEITURA DO ARQUIVO CONTENDO INSTRUO E DADOS -----
rstCPU <= '0' after 2 ns; -- release the processor to execute
wait for 4 ns; -- To activate the RST CPU signal
wait until rst = '1'; -- to Hold again!
end process;
end cpu_tb;
| mit | cbd18c320d6036677c504df2c05c10ce | 0.49894 | 3.822297 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/opcode_fetch.vhd | 2 | 1,428 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
architecture Behavioral of opcode_fetch is
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
begin
PC <= LPC;
process(CLK_I, CLR)
begin
if (CLR = '1') then
LPC <= X"0000";
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end process;
end Behavioral;
| mit | 8a6cdc0a9478093019ff46bf7db0acab | 0.615546 | 2.767442 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/input_output.vhd | 3 | 5,695 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity input_output is
PORT ( CLK_I : in std_logic;
ADR_I : in std_logic_vector( 7 downto 0);
CYC_I : in std_logic;
STB_I : in std_logic;
ACK_O : out std_logic;
RST_O : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
HALT : in STD_LOGIC;
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
-- temperature
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- input/output
IO : in std_logic;
WE_I : in std_logic;
IO_RDAT : out std_logic_vector( 7 downto 0);
IO_WDAT : in std_logic_vector( 7 downto 0);
INT : out STD_LOGIC
);
end input_output;
architecture Behavioral of input_output is
COMPONENT temperature
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
TEMP_SPO : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic
);
END COMPONENT;
COMPONENT uart_baudgen
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
RD : IN std_logic;
WR : IN std_logic;
TX_DATA : IN std_logic_vector(7 downto 0);
RX_SERIN : IN std_logic;
TX_SEROUT : OUT std_logic;
RX_DATA : OUT std_logic_vector(7 downto 0);
RX_READY : OUT std_logic;
TX_BUSY : OUT std_logic
);
END COMPONENT;
signal IO_RD_SERIAL : std_logic;
signal IO_WR_SERIAL : std_logic;
signal RX_READY : std_logic;
signal TX_BUSY : std_logic;
signal RX_DATA : std_logic_vector(7 downto 0);
signal TEMP_DO : std_logic_vector(7 downto 0);
signal SERDAT : std_logic;
signal LCLR : std_logic;
signal C1_N, C2_N : std_logic; -- switch debounce, active low
signal RX_INT_ENABLED : std_logic;
signal TX_INT_ENABLED : std_logic;
signal TIM_INT_ENABLED : std_logic;
signal TIMER_INT : std_logic;
signal TIMER : std_logic_vector(15 downto 0);
signal CLK_COUNT : std_logic_vector(16 downto 0);
signal CLK_COUNT_EN : std_logic;
signal CLK_HALT_MSK : std_logic;
signal CLK_HALT_VAL : std_logic;
begin
tempr: temperature
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
DATA_OUT => TEMP_DO,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
uart: uart_baudgen
PORT MAP( CLK_I => CLK_I,
RST_I => LCLR,
RD => IO_RD_SERIAL,
WR => IO_WR_SERIAL,
TX_DATA => IO_WDAT,
TX_SEROUT => SER_OUT,
RX_SERIN => SER_IN,
RX_DATA => RX_DATA,
RX_READY => RX_READY,
TX_BUSY => TX_BUSY
);
RST_O <= LCLR;
INT <= (RX_INT_ENABLED and RX_READY)
or (TX_INT_ENABLED and not TX_BUSY)
or (TIM_INT_ENABLED and TIMER_INT);
SERDAT <= (IO and CYC_I) when (ADR_I = X"00") else '0';
IO_RD_SERIAL <= SERDAT and not WE_I;
IO_WR_SERIAL <= SERDAT and WE_I;
ACK_O <= STB_I;
-- IO read process
--
process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
RX_INT_ENABLED, RX_READY, TEMP_DO, SWITCH, CLK_COUNT)
begin
case ADR_I is
when X"00" => IO_RDAT <= RX_DATA;
when X"01" => IO_RDAT <= '0'
& (TIM_INT_ENABLED and TIMER_INT)
& (TX_INT_ENABLED and not TX_BUSY)
& (RX_INT_ENABLED and RX_READY)
& '0'
& TIMER_INT
& TX_BUSY
& RX_READY;
when X"02" => IO_RDAT <= TEMP_DO;
when X"03" => IO_RDAT <= SWITCH(7 downto 0);
when X"05" => IO_RDAT <= CLK_COUNT(8 downto 1);
when others => IO_RDAT <= CLK_COUNT(16 downto 9);
end case;
end process;
-- IO write and timer process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LCLR = '1') then
LED <= X"00";
RX_INT_ENABLED <= '0';
TX_INT_ENABLED <= '0';
TIM_INT_ENABLED <= '0';
TIMER_INT <= '0';
TIMER <= X"0000";
else
if (IO = '1' and CYC_I = '1' and WE_I = '1') then
case ADR_I is
when X"00" => -- handled by uart
when X"01" => -- handled by uart
when X"02" => LED <= IO_WDAT;
when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
TX_INT_ENABLED <= IO_WDAT(1);
TIM_INT_ENABLED <= IO_WDAT(2);
when X"04" => TIMER_INT <= '0';
when X"05" => CLK_COUNT_EN <= '1';
CLK_COUNT <= '0' & X"0000";
CLK_HALT_VAL <= IO_WDAT(0);
CLK_HALT_MSK <= IO_WDAT(1);
when X"06" => CLK_COUNT_EN <= '0';
when others =>
end case;
end if;
if (TIMER = 39999) then -- 1 ms at 40 MHz
TIMER_INT <= '1';
TIMER <= X"0000";
else
TIMER <= TIMER + 1;
end if;
if (CLK_COUNT_EN = '1' and
(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
CLK_COUNT <= CLK_COUNT + 1;
end if;
end if;
end if;
end process;
-- reset debounce process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
-- switch debounce
if (SWITCH(8) = '1' or SWITCH(9) = '1') then
LCLR <= '1';
C2_N <= '0';
C1_N <= '0';
else
LCLR <= not C2_N;
C2_N <= C1_N;
C1_N <= '1';
end if;
end if;
end process;
end Behavioral;
| mit | 58268a4f4d5be59684dcc88033584050 | 0.545215 | 2.634135 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Simple/hardware_interface.vhd | 1 | 3,915 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component bcd_2_adder port (
Carry_in : in std_logic;
Carry_out : out std_logic;
Adig0: in STD_LOGIC_VECTOR (3 downto 0);
Adig1: in STD_LOGIC_VECTOR (3 downto 0);
Bdig0: in STD_LOGIC_VECTOR (3 downto 0);
Bdig1: in STD_LOGIC_VECTOR (3 downto 0);
Sdig0: out STD_LOGIC_VECTOR (3 downto 0);
Sdig1: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal clockScalers : std_logic_vector (26 downto 0);
signal masterReset : std_logic;
signal displayKey : std_logic_vector(15 downto 0);
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal buttonA : std_logic;
signal buttonB : std_logic;
signal inA0 : std_logic_vector(3 downto 0);
signal inA1 : std_logic_vector(3 downto 0);
signal inB0 : std_logic_vector(3 downto 0);
signal inB1 : std_logic_vector(3 downto 0);
signal carry_bit : std_logic;
signal mode_selector : std_logic_vector(1 downto 0);
BEGIN
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : bcd_2_adder port map (carry_bit, digit7(0), inA0, inA1, inB0, inB1, digit5, digit6);
LEDs (15 downto 0) <= clockScalers(26 downto 11);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
buttonA <= pushButtons(0);
buttonB <= pushButtons(1);
masterReset <= pushButtons(2);
mode_selector <= slideSwitches(15 downto 14);
carry_bit <= slideSwitches(13);
inA0 <= slideSwitches (3 downto 0) when (buttonA'event and buttonA = '1');
inA1 <= slideSwitches (7 downto 4) when (buttonA'event and buttonA = '1');
inB0 <= slideSwitches (3 downto 0) when (buttonB'event and buttonB = '1');
inB1 <= slideSwitches (7 downto 4) when (buttonB'event and buttonB = '1');
displayKey(3 downto 0) <= inA0;
displayKey(7 downto 4) <= inA1;
displayKey(11 downto 8) <= inB0;
displayKey(15 downto 12) <= inB1;
with mode_selector select
logic_analyzer(3 downto 0) <= inA0 when "01",
inB0 when "10",
digit5 when "11";
with mode_selector select
logic_analyzer(7 downto 4) <= inA1 when "01",
inB1 when "10",
digit6 when "11";
end Behavioral;
| apache-2.0 | 40c1012cb2fc50a96ac94de2e53848d8 | 0.659515 | 2.963664 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/std_ovl_clock_gating.vhd | 1 | 3,099 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
entity std_ovl_clock_gating is
generic (
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
enable : in std_logic;
clk : out std_logic
);
end entity std_ovl_clock_gating;
architecture rtl of std_ovl_clock_gating is
constant clock_edge_ctrl : ovl_active_edges_natural :=
ovl_get_ctrl_val(clock_edge, controls.clock_edge_default);
constant gating_type_ctrl : ovl_gating_type_natural :=
ovl_get_ctrl_val(gating_type, controls.gating_type_default);
begin
ovl_on_gen : if ((controls.assert_ctrl = OVL_ON) or (controls.cover_ctrl = OVL_ON)) generate
----------------------------------------------------------------------------
-- Gated clock --
----------------------------------------------------------------------------
ovl_gating_on_gen : if ((controls.gating_ctrl = OVL_ON) and (gating_type_ctrl = OVL_GATE_CLOCK)) generate
-- non-inverted clock
ovl_noninv_clk_gen : if (clock_edge_ctrl = OVL_POSEDGE) generate
ovl_clock_gating_p : process (clock, enable)
variable clken : std_logic;
begin
if (clock = '0') then
clken := enable;
end if;
clk <= clock and clken;
end process ovl_clock_gating_p;
end generate ovl_noninv_clk_gen;
-- inverted clock
ovl_inv_clk_gen : if (clock_edge_ctrl /= OVL_POSEDGE) generate
ovl_clock_gating_p : process (clock, enable)
variable clken : std_logic;
begin
if (clock = '0') then
clken := enable;
end if;
clk <= not (clock and clken);
end process ovl_clock_gating_p;
end generate ovl_inv_clk_gen;
end generate ovl_gating_on_gen;
----------------------------------------------------------------------------
-- Non-gated clock --
----------------------------------------------------------------------------
ovl_gating_off_gen : if ((controls.gating_ctrl = OVL_OFF) or (gating_type_ctrl /= OVL_GATE_CLOCK)) generate
-- non-inverted clock
ovl_noninv_clk_gen : if (clock_edge_ctrl = OVL_POSEDGE) generate
clk <= clock;
end generate ovl_noninv_clk_gen;
-- inverted clock
ovl_inv_clk_gen : if (clock_edge_ctrl /= OVL_POSEDGE) generate
clk <= not clock;
end generate ovl_inv_clk_gen;
end generate ovl_gating_off_gen;
end generate ovl_on_gen;
ovl_off_gen : if ((controls.assert_ctrl = OVL_OFF) and (controls.cover_ctrl = OVL_OFF)) generate
clk <= '0';
end generate ovl_off_gen;
end architecture rtl;
| mit | 6b87dab7a085734c48bdc7749bf912ad | 0.530816 | 3.738239 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Advanced/pwm.vhd | 1 | 1,756 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY pwm IS
GENERIC(
sys_clk : INTEGER := 100_000_000;
pwm_freq : INTEGER := 50);
PORT(
clk : IN STD_LOGIC;
masterReset : IN STD_LOGIC;
en : IN STD_LOGIC;
duty : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pwm_out : OUT STD_LOGIC);
END pwm;
ARCHITECTURE logic OF pwm IS
CONSTANT period : INTEGER := sys_clk/pwm_freq;
SIGNAL count : INTEGER RANGE 0 TO period - 1 := 0;
SIGNAL duty_cycle : INTEGER RANGE 0 TO period - 1 := 0;
BEGIN
PROCESS(clk, masterReset)
BEGIN
IF(masterReset = '1') THEN
count <= 0;
pwm_out <= '1';
ELSIF(clk'EVENT AND clk = '1') THEN
IF(en = '1') THEN
duty_cycle <= (conv_integer(duty) * period) / ((2**8) - 1);
ELSE
IF(count = period - 1) THEN
count <= 0;
pwm_out <= '1';
ELSE
count <= count + 1;
END IF;
IF(count < duty_cycle) THEN
pwm_out <= '1';
ELSIF(count >= duty_cycle) THEN
pwm_out <= '0';
END IF;
END IF;
END IF;
END PROCESS;
END logic;
| apache-2.0 | d4750a749bfcb845da1a64ee44268634 | 0.352506 | 4.745946 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/cpu_engine.vhd | 1 | 12,371 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_engine is
PORT( -- WISHBONE interface
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0);
DAT_O : out std_logic_vector( 7 downto 0);
RST_I : in std_logic;
ACK_I : in std_logic;
ADR_O : out std_logic_vector(15 downto 0);
CYC_O : out std_logic;
STB_O : out std_logic;
TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
WE_O : out std_logic;
INT : in std_logic;
HALT : out std_logic;
-- debug signals
--
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end cpu_engine;
architecture Behavioral of cpu_engine is
-- Unfortunately, the on-chip memory needs a clock to read data.
-- Therefore we cannot make it wishbone compliant without a speed penalty.
-- We avoid this problem by making the on-chip memory part of the CPU.
-- However, as a consequence, you cannot DMA to the on-chip memory.
--
-- The on-chip memory is 8K, so that you can run a test SoC without external
-- memory. For bigger applications, you should use external ROM and RAM and
-- remove the internal memory entirely (setting EXTERN accordingly).
--
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
OP_CAT : out op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
ADR : out std_logic_vector(15 downto 0); -- memory/IO address
MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
-- global signals
signal CE : std_logic;
signal T2 : std_logic;
-- memory signals
signal WDAT : std_logic_vector(7 downto 0);
signal RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_RD_O : std_logic;
signal D_WE_O : std_logic;
signal D_LOCK : std_logic; -- first cycle
signal LM_WE : std_logic;
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
signal C_MQ : std_logic_vector(7 downto 0);
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal XM_RDAT : std_logic_vector(7 downto 0);
signal C_IO : std_logic;
signal C_RD_O : std_logic;
signal C_WE_O : std_logic;
-- signals to remember, whether the previous read cycle
-- addressed internal memory or external memory
--
signal OPCS : std_logic; -- '1' if opcode from external memory
signal RDATS : std_logic; -- '1' if data from external memory
signal EXTERN : std_logic; -- '1' if opcode or data from external memory
begin
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
-- read in T1
PC => M_PC,
OPC => LM_OPC,
-- read or written in T2
ADR => ADR,
WR => LM_WE,
WDAT => WDAT,
RDAT => LM_RDAT
);
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => RDAT,
PC => M_PC
);
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_SP => D_WE_SP,
D_RD_O => D_RD_O,
D_WE_O => D_WE_O,
D_LOCK => D_LOCK,
D_IO => D_IO,
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
IMM => C_IMM,
RDAT => RDAT,
ADR => ADR,
MQ => WDAT,
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
CE <= ACK_I or not EXTERN;
TGA_O(0) <= T2 and C_IO;
WE_O <= T2 and C_WE_O;
STB_O <= EXTERN;
CYC_O <= EXTERN;
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
-- write enable/select signal (debug)
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
DAT_O <= WDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then T2 <= '0';
else T2 <= not T2;
end if;
end if;
end process;
process(T2, M_PC, ADR, C_IO)
begin
if (T2 = '0') then -- opcode fetch
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
-- B EXTERN <= '1'; -- no internal memory
else -- data or I/O
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
-- B EXTERN <= ('1' or -- no internal memory
C_IO) and (C_RD_O or C_WE_O);
end if;
end process;
-- remember whether access is to internal or to external (incl I/O) memory.
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
OPCS <= EXTERN;
XM_OPC <= DAT_I;
else
RDATS <= EXTERN;
XM_RDAT <= DAT_I;
end if;
end if;
end process;
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
ADR_O <= M_PC when (T2 = '0') else ADR;
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_IMM <= X"FFFF";
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
C_IO <= '0';
C_RD_O <= '0';
C_WE_O <= '0';
LM_WE <= '0';
elsif (CE = '1' and T2 = '1') then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
C_IO <= D_IO;
C_RD_O <= D_RD_O;
C_WE_O <= D_WE_O;
LM_WE <= D_WE_O and not D_IO;
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode...
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 78db17e4323fc375f5b6efa9f9df6261 | 0.547733 | 2.4668 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/top_tb.vhd | 1 | 6,695 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.uart_constants.all;
use virtual_button_lib.uart_functions.all;
use virtual_button_lib.button_pkg.all;
entity top_tb is
end;
architecture behavioural of top_tb is
signal clk_50mhz : std_logic;
-- board switches
signal pb_0 : std_logic := '0';
signal pb_1 : std_logic := '0';
signal sw_0 : std_logic := '1';
signal sw_1 : std_logic := '0';
-- board leds
signal led_0 : std_logic;
signal led_1 : std_logic := '1';
-- uart signals
signal pi_to_fpga_pin : std_logic;
signal fpga_to_pi_pin : std_logic;
-- spi signals
signal sclk : std_logic;
signal cs_n : std_logic;
signal mosi : std_logic;
signal miso : std_logic;
signal light_square_data : std_logic;
-- mock spi master signals
signal ready : boolean := false;
signal send : boolean := false;
signal master_data : std_logic_vector(spi_word_length - 1 downto 0) := (others => '0');
signal force_cs_low : boolean := false;
signal mcu_to_fpga_data : std_logic_vector(spi_word_length - 1 downto 0);
signal tb_ctrl : ctrl_t;
signal tb_rx_wip : std_logic_vector(7 downto 0);
signal tb_rx : std_logic_vector(7 downto 0);
signal new_tb_rx : std_logic;
signal next_time_sig : time;
signal next_enable_sig, next_clock_sig, next_mosi_sig : character;
signal remaining_bytes : integer := 0;
signal current_rx : std_logic_vector(7 downto 0);
signal last_rx : std_logic_vector(7 downto 0);
begin
top_1 : entity virtual_button_lib.top
port map (
clk_50mhz => clk_50mhz,
pb_0 => pb_0,
pb_1 => pb_1,
sw_0 => sw_0,
sw_1 => sw_1,
led_0 => led_0,
led_1 => led_1,
pi_to_fpga_pin => pi_to_fpga_pin,
fpga_to_pi_pin => fpga_to_pi_pin,
sclk => sclk,
cs_n => cs_n,
mosi => mosi,
miso => miso,
light_square_data => light_square_data);
tb_ctrl.clk <= clk_50mhz;
tb_ctrl.reset_n <= '1';
spi_rx_1 : entity virtual_button_lib.spi_rx
generic map (
cpol => 0,
cpha => 0)
port map (
ctrl => tb_ctrl,
sclk => sclk,
cs_n => cs_n,
mosi => miso,
data => tb_rx_wip,
new_data => new_tb_rx);
update_tb_rx : process(new_tb_rx) is
begin
if rising_edge(new_tb_rx) then
tb_rx <= tb_rx_wip;
end if;
end process;
--mock_spi_master_1 : entity virtual_button_lib.mock_spi_master
-- port map (
-- frequency => 5_000_000,
-- cpol => 0,
-- cpha => 0,
-- send => send,
-- force_cs_low => force_cs_low,
-- ready => ready,
-- data => master_data,
-- cs_n => cs_n,
-- sclk => sclk,
-- mosi => mosi);
-- Clock process definitions
clk_process : process
constant clk_period_50 : time := 1 sec / 50_000_000;
begin
loop
clk_50mhz <= '0';
wait for clk_period_50/2;
clk_50mhz <= '1';
wait for clk_period_50/2;
end loop;
end process;
-- Stimulus process
stim_proc : process
begin
sw_0 <= '0';
wait for 1 us;
sw_0 <= '1';
wait;
end process;
uart_things : process is
begin
uart_send(std_logic_vector(to_unsigned(character'pos('e'), 8)), 9600, pi_to_fpga_pin);
wait;
end process;
decode_tb_rx : process(new_tb_rx) is
begin
if rising_edge(new_tb_rx) then
if remaining_bytes = 0 then
remaining_bytes <= to_integer(unsigned(tb_rx));
else
remaining_bytes <= remaining_bytes - 1;
if last_rx = tb_rx and to_integer(signed(tb_rx)) /= 127 and to_integer(signed(tb_rx)) /= -128 then
--report "last_rx and tb_rx are the same" & integer'image(to_integer(signed(tb_rx))) severity failure;
end if;
last_rx <= current_rx;
current_rx <= tb_rx;
end if;
end if;
end process;
mcu_send_proc : process is
file time_file : text;
file clock_file : text;
file enable_file : text;
file mosi_file : text;
variable time_line, clock_line, enable_line, mosi_line : line;
variable next_time : time;
variable next_clock, next_enable, next_mosi : character;
variable success : boolean;
variable current_loop_start : time := 0 sec;
begin
wait for 1 ms;
loop
file_open(time_file, "tb/time.txt", read_mode);
file_open(clock_file, "tb/CLOCK.txt", read_mode);
file_open(enable_file, "tb/ENABLE.txt", read_mode);
file_open(mosi_file, "tb/MOSI.txt", read_mode);
while not endfile(time_file) loop
readline(time_file, time_line);
read(time_line, next_time, success);
if not success then
report "invalid time" severity error;
end if;
next_time_sig <= next_time;
readline(clock_file, clock_line);
read(clock_line, next_clock, success);
if not success then
report "invalid clock" severity error;
end if;
next_clock_sig <= next_clock;
readline(enable_file, enable_line);
read(enable_line, next_enable, success);
if not success then
report "invalid enable" severity error;
end if;
next_enable_sig <= next_enable;
readline(mosi_file, mosi_line);
read(mosi_line, next_mosi, success);
if not success then
report "invalid enable" severity error;
end if;
next_mosi_sig <= next_mosi;
if now < (next_time + current_loop_start) then
wait for (next_time + current_loop_start) - now;
end if;
if next_clock = '1' then
sclk <= '1';
else
sclk <= '0';
end if;
if next_enable = '1' then
cs_n <= '1';
else
cs_n <= '0';
end if;
if next_mosi = '1' then
mosi <= '1';
else
mosi <= '0';
end if;
end loop;
file_close(time_file);
file_close(clock_file);
file_close(enable_file);
file_close(mosi_file);
current_loop_start := now;
end loop;
wait;
end process;
end;
| bsd-2-clause | 3f32c7824cd3e554400c8c572b93d516 | 0.535624 | 3.438624 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod01_sv_for_vhdlers/SystemVerilog_for_VHDL_Engineers_Primer/primer_examples/processes/vhdl_adder.vhd | 2 | 949 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY adder IS
PORT(
A : IN std_logic_vector ( 7 DOWNTO 0 );
B : IN std_logic_vector ( 7 DOWNTO 0 );
clk : IN std_logic;
rst_n : IN std_logic;
carry : OUT std_logic;
sum : OUT std_logic_vector ( 7 DOWNTO 0 )
);
END adder ;
ARCHITECTURE rtl OF adder IS
signal sum_int : std_logic_vector (8 downto 0);
signal A8 : std_logic_vector (8 downto 0);
signal B8 : std_logic_vector (8 downto 0);
BEGIN
A8 <= "0" & A;
B8 <= "0" & B;
sum_int <= A8 + B8;
adder: process (clk, rst_n)
begin
if rst_n = '0' then
carry <= '0';
sum <= "00000000";
elsif clk'event and clk = '1' then
carry <= sum_int(8);
sum <= sum_int(7 downto 0);
end if;
end process adder;
END ARCHITECTURE rtl;
| mit | a0deb3f1ab894dbdba8a0ac7f957b900 | 0.539515 | 3.101307 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/midi_ram_tb/midi_ram_tb.vhd | 1 | 2,494 | --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity midi_ram_tb is
end;
architecture tb of midi_ram_tb is
constant max_read_bytes : integer := 3;
signal ctrl : ctrl_t;
signal enqueue : std_logic;
signal write_in_data : std_logic_vector(8 - 1 downto 0);
signal empty : std_logic;
signal full : std_logic;
signal contents_count : natural range 0 to midi_file_rx_bram_depth;
signal read_start_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal read_num_bytes : integer range 0 to max_read_bytes;
signal read_en : std_logic;
signal read_busy : std_logic;
signal midi_ram_out : std_logic_vector((max_read_bytes * 8) - 1 downto 0);
begin
midi_ram_top_1 : entity virtual_button_lib.midi_ram_top
generic map (
max_read_bytes => max_read_bytes,
queue_width => 8
)
port map (
ctrl => ctrl,
enqueue => enqueue,
write_in_data => write_in_data,
empty => empty,
full => full,
contents_count => contents_count,
read_start_addr => read_start_addr,
read_num_bytes => read_num_bytes,
read_en => read_en,
read_busy => read_busy,
midi_ram_out => midi_ram_out);
-- Clock process definitions
clk_process : process
begin
ctrl.clk <= '0';
wait for clk_period/2;
ctrl.clk <= '1';
wait for clk_period/2;
end process;
stim_proc : process
begin
ctrl.reset_n <= '0';
enqueue <= '0';
write_in_data <= (others => '0');
read_start_addr <= (others => '0');
read_num_bytes <= 0;
read_en <= '0';
wait for 1 us;
ctrl.reset_n <= '1';
-- Add some_items
for i in 1 to 100 loop
wait until falling_edge(ctrl.clk);
enqueue <= '1';
write_in_data <= std_logic_vector(to_unsigned(i, 8));
end loop;
enqueue <= '0';
-- now see if dequeueing works.
wait until falling_edge(ctrl.clk);
read_start_addr <= to_unsigned(0, integer(ceil(log2(real(midi_file_rx_bram_depth)))));
read_num_bytes <= 3;
read_en <= '1';
wait until falling_edge(ctrl.clk);
read_en <= '0';
wait until falling_edge(read_busy);
wait;
end process;
end;
| bsd-2-clause | e3a36c0019bb33333d27f2dec8626ded | 0.576985 | 3.268676 | false | false | false | false |
SDRG-UCT/RHINO_CALF | fmc150-io/fmc150_if.vhd | 1 | 37,417 |
----------------------------------------------------------------------------
-- Title : Interfacing RHINO with 4DSP-FMC150
----------------------------------------------------------------------------
-- Project : RHINO SDR Processing Blocks
----------------------------------------------------------------------------
--
-- Author : Lekhobola Tsoeunyane
-- Company : University Of Cape Town
-- Email : [email protected]
----------------------------------------------------------------------------
-- Revisions :
----------------------------------------------------------------------------
-- Features
-- 1) SPI configuration of ADS62P49, DAC3283, CDCE72010, ADS4249 and AMC7823
-- 2) LVDS interface to ADS62P49 and DAC3283
-- 2) ADS62P49 auto-calibration
--
-----------------------------------------------------------------------------
-- Library declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Entity declaration
------------------------------------------------------------------------------
entity fmc150_if is
port (
--RHINO Resources
sysrst : in std_logic;
clk_100MHz : in std_logic;
mmcm_locked : in std_logic;
clk_61_44MHz : in std_logic;
clk_122_88MHz : in std_logic;
mmcm_adac_locked : in std_logic;
dac_fpga_clk : out std_logic;
-------------- user design interface -----------------------
-- ADC
adc_cha_dout : out std_logic_vector(13 downto 0);
adc_chb_dout : out std_logic_vector(13 downto 0);
-- DAC
dac_chc_din : in std_logic_vector(15 downto 0);
dac_chd_din : in std_logic_vector(15 downto 0);
calibration_ok : out std_logic;
-------------- physical external interface -----------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
clk_ab_p : in std_logic;
clk_ab_n : in std_logic;
cha_p : in std_logic_vector(6 downto 0);
cha_n : in std_logic_vector(6 downto 0);
chb_p : in std_logic_vector(6 downto 0);
chb_n : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga : in std_logic;
ext_trigger : in std_logic;
--Serial Peripheral Interface (SPI)
spi_sclk : out std_logic; -- Shared SPI clock line
spi_sdata : out std_logic; -- Shared SPI sata line
-- ADC specific signals
adc_n_en : out std_logic; -- SPI chip select
adc_sdo : in std_logic; -- SPI data out
adc_reset : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en : out std_logic; -- SPI chip select
cdce_sdo : in std_logic; -- SPI data out
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
-- DAC specific signals
dac_n_en : out std_logic; -- SPI chip select
dac_sdo : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en : out std_logic; -- SPI chip select
mon_sdo : in std_logic; -- SPI data out
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
--FMC Present status
nfmc0_prsnt : in std_logic
-- debug signals
);
end fmc150_if;
architecture rtl of fmc150_if is
----------------------------------------------------------------------------------------------------
-- Constant declaration
----------------------------------------------------------------------------------------------------
constant CLK_IDELAY : integer := 0; -- Initial number of delay taps on ADC clock input
constant CHA_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port A -- error-free capture range measured between 20 ... 30
constant CHB_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port B -- error-free capture range measured between 20 ... 30
constant MAX_PATTERN_CNT : integer := 600;--16383; -- value of 15000 = approx 1 sec for ramp of length 2^14 samples @ 245.76 MSPS
-- Define the phase increment word for the DDC and DUC blocks (aka NCO)
-- dec2bin(round(Fc/Fs*2^28)), where Fc = -12 MHz, Fs = 61.44 MHz
--constant FREQ_DEFAULT : std_logic_vector(27 downto 0) := x"CE00000";
constant FREQ_DEFAULT : std_logic_vector(27 downto 0) := x"3200000";
component mmcm_adac
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component MMCM
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component fmc150_spi_ctrl is
port (
init_done : out std_logic;
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
rst : in std_logic;
clk : in std_logic;
external_clock : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic
);
end component fmc150_spi_ctrl;
component dac3283_serializer is
port(
--System Control Inputs
RST_I : in STD_LOGIC;
--Signal Channel Inputs
DAC_CLK_O : out STD_LOGIC;
DAC_CLK_DIV4_O : out STD_LOGIC;
DAC_READY : out STD_LOGIC;
CH_C_I : in STD_LOGIC_VECTOR(15 downto 0);
CH_D_I : in STD_LOGIC_VECTOR(15 downto 0);
-- DAC interface
FMC150_CLK : in STD_LOGIC;
DAC_DCLK_P : out STD_LOGIC;
DAC_DCLK_N : out STD_LOGIC;
DAC_DATA_P : out STD_LOGIC_VECTOR(7 downto 0);
DAC_DATA_N : out STD_LOGIC_VECTOR(7 downto 0);
FRAME_P : out STD_LOGIC;
FRAME_N : out STD_LOGIC;
-- Testing
IO_TEST_EN : in STD_LOGIC
);
end component dac3283_serializer;
component ADC_auto_calibration is
generic (
MAX_PATTERN_CNT : integer := 1000; -- value of 15000 = approx 1 sec for ramp of length 2^14 samples @ 245.76 MSPS
INIT_IDELAY : integer -- Initial number of delay taps on ADC data port
);
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ADC_calibration_start : in STD_LOGIC;
ADC_data : in STD_LOGIC_VECTOR (13 downto 0);
re_mux_polarity : out STD_LOGIC;
trace_edge : out STD_LOGIC;
ADC_calibration_state : out STD_LOGIC_VECTOR(2 downto 0);
iDelay_cnt : out STD_LOGIC_VECTOR (4 downto 0);
iDelay_inc_en : out std_logic;
ADC_calibration_done : out BOOLEAN;
ADC_calibration_good : out STD_LOGIC);
end component;
----------------------------------------------------------------------------------------------------
-- Debugging Components and Signals
----------------------------------------------------------------------------------------------------
component icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
component ila0
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
component ila1
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
component vio
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
ASYNC_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal CONTROL1 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal CONTROL2 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal ila_data0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal ila_data1 : STD_LOGIC_VECTOR(127 DOWNTO 0);
signal trig0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal trig1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal vio_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Signal declaration
----------------------------------------------------------------------------------------------------
--signal clk_100Mhz : std_logic;
--signal clk_200Mhz : std_logic;
--signal mmcm_locked : std_logic;
signal arst : std_logic := '0';
signal rst : std_logic;
signal rst_duc_ddc : std_logic;
signal clk_ab_l : std_logic;
signal clk_ab_dly : std_logic;
signal clk_ab_i : std_logic;
signal cha_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal cha_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal cha_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal chb_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal chb_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal chb_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_dout_i : std_logic_vector(13 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_dout_q : std_logic_vector(13 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_vout : std_logic;
signal freq : std_logic_vector(27 downto 0);
signal cmplx_aresetn_duc : std_logic;
signal dds_reset_duc : std_logic;
signal cmplx_aresetn_ddc : std_logic;
signal dds_reset_ddc : std_logic;
signal signal_ce : std_logic;
signal signal_ce_prev : std_logic;
signal signal_vout : std_logic;
signal imp_dout_i : std_logic_vector(15 downto 0);
signal imp_dout_q : std_logic_vector(15 downto 0);
signal delay_update : std_logic;
signal clk_cntvaluein : std_logic_vector(4 downto 0);
signal cha_cntvaluein : std_logic_vector(4 downto 0);
signal chb_cntvaluein : std_logic_vector(4 downto 0);
signal clk_cntvalueout : std_logic_vector(4 downto 0);
type cha_cntvalueout_array is array(cha_p'length-1 downto 0) of std_logic_vector(4 downto 0);
signal cha_cntvalueout : cha_cntvalueout_array;
type chb_cntvalueout_array is array(chb_p'length-1 downto 0) of std_logic_vector(4 downto 0);
signal chb_cntvalueout : chb_cntvalueout_array;
signal rd_n_wr : std_logic;
signal addr : std_logic_vector(15 downto 0);
signal idata : std_logic_vector(31 downto 0);
signal odata : std_logic_vector(31 downto 0);
signal busy : std_logic;
signal cdce72010_valid : std_logic;
signal ads62p49_valid : std_logic;
signal dac3283_valid : std_logic;
signal amc7823_valid : std_logic;
--signal clk_66MHz : std_logic;
--signal clk_61_44MHz : std_logic;
signal clk_61_44MHz_n : std_logic;
--signal clk_122_88MHz : std_logic;
--signal clk_368_64MHz : std_logic;
--signal mmcm_adac_locked : std_logic;
signal dac_din_i : std_logic_vector(15 downto 0);
signal dac_din_q : std_logic_vector(15 downto 0);
signal frame : std_logic;
signal io_rst : std_logic;
signal dac_dclk_prebuf : std_logic;
signal dac_data_prebuf : std_logic_vector(7 downto 0);
signal dac_frame_prebuf : std_logic;
signal digital_mode : std_logic;
signal external_clock : std_logic := '0';
signal ADC_cha_calibration_start : std_logic;
signal ADC_chb_calibration_start : std_logic;
signal ADC_cha_calibration_done : boolean;
signal ADC_cha_calibration_done_r : boolean;
signal ADC_cha_calibration_done_rr : boolean;
signal ADC_chb_calibration_done : boolean;
signal ADC_chb_calibration_done_r : boolean;
signal ADC_chb_calibration_done_rr : boolean;
signal ADC_chb_calibration_test_pattern_mode_command_sent : boolean;
signal ADC_cha_calibration_test_pattern_mode_command_sent : boolean;
signal ADC_chb_normal_mode_command_sent : boolean;
signal ADC_cha_normal_mode_command_sent : boolean;
signal ADC_chb_trace_edge : std_logic;
signal ADC_cha_trace_edge : std_logic;
signal ADC_chb_calibration_state : std_logic_vector(2 downto 0);
signal ADC_cha_calibration_state : std_logic_vector(2 downto 0);
signal ADC_chb_calibration_good : std_logic;
signal ADC_cha_calibration_good : std_logic;
signal ADC_calibration_good : std_logic;
signal ADC_chb_ready : boolean;
signal ADC_cha_ready : boolean;
signal ADC_ready : boolean;
signal cha_cntvaluein_update : std_logic_vector(4 downto 0);
signal clk_cntvaluein_update : std_logic_vector(4 downto 0);
signal fmc150_spi_ctrl_done : std_logic;
signal fmc150_spi_ctrl_done_r : std_logic;
signal sysclk : std_logic;
signal busy_reg : std_logic;
signal cha_cntvaluein_update_61_44MHz : std_logic_vector(4 downto 0);
signal cha_cntvaluein_update_100MHz : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update_vio : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update_61_44MHz : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update_100MHz : std_logic_vector(4 downto 0);
signal adc_dout_i_prev : std_logic_vector(13 downto 0);
signal adc_dout_61_44_MSPS_valid : std_logic;
signal clk_61_44MHz_count : std_logic;
signal adc_cha_re_mux_polarity : std_logic := '1'; -- initial state '1' is contrary to actual default behaviour in hardware, but desired for simulation to verify correctness of state machine
signal adc_chb_re_mux_polarity : std_logic := '1'; -- initial state '1' is contrary to actual default behaviour in hardware, but desired for simulation to verify correctness of state machine
signal sclk : std_logic;
signal sclk_n : std_logic;
signal ce_a : std_logic := '0';
signal ce_b : std_logic := '0';
signal cha_inc_update : std_logic;
signal cha_inc_update_100MHz : std_logic;
signal cha_inc_update_61_44MHz : std_logic;
signal cha_incin : std_logic;
signal chb_inc_update : std_logic;
signal chb_inc_update_100MHz : std_logic;
signal chb_inc_update_61_44MHz : std_logic;
signal chb_incin : std_logic;
signal dac_ready : std_logic;
signal txen : std_logic := '0';
signal dac_cnt : std_logic_vector(13 downto 0) := (others => '0');
--signal dac_sample_clk : std_logic;
signal ftw : std_logic_vector(31 downto 0);
----------------------------------------------------------------------------------------------------
-- Begin
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
-- Perform ADC auto calibration
----------------------------------------------------------------------------------
routing_to_SPI: process (arst, clk_100Mhz)
begin
if (arst = '1') then
busy_reg <= '0';
cdce72010_valid <= '0';
ads62p49_valid <= '0';
dac3283_valid <= '0';
amc7823_valid <= '0';
cha_cntvaluein_update_100MHz <= conv_std_logic_vector(CHA_IDELAY, 5);
cha_cntvaluein_update <= conv_std_logic_vector(CHA_IDELAY, 5);
chb_cntvaluein_update_100MHz <= conv_std_logic_vector(CHB_IDELAY, 5);
chb_cntvaluein_update <= conv_std_logic_vector(CHB_IDELAY, 5);
clk_cntvaluein_update <= conv_std_logic_vector(CLK_IDELAY, 5);
ADC_chb_calibration_done_r <= FALSE;
ADC_chb_calibration_done_rr <= FALSE;
ADC_cha_calibration_done_r <= FALSE;
ADC_cha_calibration_done_rr <= FALSE;
ADC_chb_calibration_test_pattern_mode_command_sent <= FALSE;
ADC_cha_calibration_test_pattern_mode_command_sent <= FALSE;
ADC_chb_normal_mode_command_sent <= FALSE;
ADC_cha_normal_mode_command_sent <= FALSE;
ADC_chb_calibration_start <= '0';
ADC_cha_calibration_start <= '0';
fmc150_spi_ctrl_done_r <= '0';
ADC_cha_ready <= FALSE;
ADC_chb_ready <= FALSE;
ADC_ready <= FALSE;
elsif (rising_edge(clk_100Mhz)) then
busy_reg <= busy;
fmc150_spi_ctrl_done_r <= fmc150_spi_ctrl_done;
ADC_chb_calibration_done_r <= ADC_chb_calibration_done; -- double-register to cross from clock domain of 'ADC_auto_calibration'
ADC_chb_calibration_done_rr <= ADC_chb_calibration_done_r; -- where 'ADC_chb_calibration_done' is set
ADC_chb_calibration_done_rr <= TRUE;
ADC_cha_calibration_done_r <= ADC_cha_calibration_done;
ADC_cha_calibration_done_rr <= ADC_cha_calibration_done_r;
-------------------Debugging-------------
--ADC_chb_ready <= TRUE;
-------------------Debugging-------------
if not ADC_chb_ready then
chb_cntvaluein_update_100MHz <= chb_cntvaluein_update_61_44MHz;
chb_cntvaluein_update <= chb_cntvaluein_update_100MHz;
chb_inc_update_100MHz <= chb_inc_update_61_44MHz;
chb_inc_update <= chb_inc_update_100MHz;
if not ADC_chb_calibration_done_rr then
if not ADC_chb_calibration_test_pattern_mode_command_sent then
if (fmc150_spi_ctrl_done = '1' and fmc150_spi_ctrl_done_r = '0') then -- rising edge of 'fmc150_spi_ctrl_done' indicates reset-time
-- initialization of FMC150 SPI devices has completed
addr <= x"0075";
idata <= x"00000004"; -- send SPI command to ads62p49 for test-mode / ramp pattern on Ch B
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_chb_calibration_test_pattern_mode_command_sent <= TRUE;
else
ads62p49_valid <= ads62p49_valid;
ADC_chb_calibration_test_pattern_mode_command_sent <= FALSE;
end if;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 for test-mode
ADC_chb_calibration_start <= '1'; -- ... ADC auto-calibration state-machine 'ADC_auto_calibration' is awaiting this event to start
else
ADC_chb_calibration_start <= '0';
end if;
end if;
else
if not ADC_chb_normal_mode_command_sent then
addr <= x"0075";
idata <= x"00000000"; -- send SPI command to ads62p49 for normal capture mode
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_chb_normal_mode_command_sent <= TRUE;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 to resume normal capture mode after ADC calibration sequence
ADC_chb_ready <= TRUE; -- ADC auto-calibration is done and ADS62P49 is now in normal capture mode ... allow RX FIFO to read
else
ADC_chb_ready <= FALSE;
end if;
end if;
end if;
elsif not ADC_cha_ready then
cha_cntvaluein_update_100MHz <= cha_cntvaluein_update_61_44MHz;
cha_cntvaluein_update <= cha_cntvaluein_update_100MHz;
cha_inc_update_100MHz <= cha_inc_update_61_44MHz;
cha_inc_update <= cha_inc_update_100MHz;
if not ADC_cha_calibration_done_rr then
if not ADC_cha_calibration_test_pattern_mode_command_sent then
addr <= x"0062";
idata <= x"00000004"; -- send SPI command to ads62p49 for test-mode / ramp pattern on Ch A
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_cha_calibration_test_pattern_mode_command_sent <= TRUE;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 for test-mode
ADC_cha_calibration_start <= '1'; -- ... ADC auto-calibration state-machine 'ADC_auto_calibration' is awaiting this event to start
else
ADC_cha_calibration_start <= '0';
end if;
end if;
else
if not ADC_cha_normal_mode_command_sent then
addr <= x"0062";
idata <= x"00000000"; -- send SPI command to ads62p49 for normal capture mode
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_cha_normal_mode_command_sent <= TRUE;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 to resume normal capture mode after ADC calibration sequence
ADC_cha_ready <= TRUE; -- ADC auto-calibration is done and ADS62P49 is now in normal capture mode
ADC_ready <= TRUE; -- allow RX FIFO to read
else
ADC_cha_ready <= FALSE;
ADC_ready <= FALSE;
end if;
end if;
end if;
end if;
end if;
end process routing_to_SPI;
calibration_ok <= '1' when ADC_cha_calibration_done_r and ADC_chb_calibration_done_r else
'0';
----------------------------------------------------------------------------------
-- Update iDelay values for incoming ADC data, clock
----------------------------------------------------------------------------------
iDelay_update: process (arst, clk_100Mhz)
begin
if (arst = '1') then
delay_update <= '1';
clk_cntvaluein <= conv_std_logic_vector(CLK_IDELAY, 5);
cha_cntvaluein <= conv_std_logic_vector(CHA_IDELAY, 5);
chb_cntvaluein <= conv_std_logic_vector(CHB_IDELAY, 5);
cha_incin <= '0';
chb_incin <= '0';
elsif (rising_edge(clk_100Mhz)) then
-- Generate an delay_update pulse in case one of the cntvaluein values has changed
if (cha_cntvaluein /= cha_cntvaluein_update) then
delay_update <= '1';
clk_cntvaluein <= clk_cntvaluein;
chb_cntvaluein <= chb_cntvaluein;
cha_cntvaluein <= cha_cntvaluein_update;
chb_incin <= '0';
cha_incin <= cha_inc_update;
elsif (chb_cntvaluein /= chb_cntvaluein_update) then
delay_update <= '1';
clk_cntvaluein <= clk_cntvaluein;
chb_cntvaluein <= chb_cntvaluein_update;
cha_cntvaluein <= cha_cntvaluein;
chb_incin <= chb_inc_update;
cha_incin <= '0';
elsif (clk_cntvaluein /= clk_cntvaluein_update) then
delay_update <= '1';
clk_cntvaluein <= clk_cntvaluein_update;
chb_cntvaluein <= chb_cntvaluein;
cha_cntvaluein <= cha_cntvaluein;
chb_incin <= '0';
cha_incin <= '0';
else
delay_update <= '0';
clk_cntvaluein <= clk_cntvaluein;
chb_cntvaluein <= chb_cntvaluein;
cha_cntvaluein <= cha_cntvaluein;
chb_incin <= '0';
cha_incin <= '0';
end if;
end if;
end process iDelay_update;
----------------------------------------------------------------------------------
-- ADC calibration Channel B
----------------------------------------------------------------------------------
ADC_auto_calibration_chB: ADC_auto_calibration
generic map(
MAX_PATTERN_CNT => MAX_PATTERN_CNT,
INIT_IDELAY => CHB_IDELAY
)
Port map(
reset => arst,
clk => clk_61_44Mhz,
ADC_calibration_start => ADC_chb_calibration_start,
ADC_data => adc_dout_q,
re_mux_polarity => adc_chb_re_mux_polarity,
trace_edge => ADC_chb_trace_edge,
ADC_calibration_state => ADC_chb_calibration_state,
iDelay_cnt => chb_cntvaluein_update_61_44MHz,
iDelay_inc_en => chb_inc_update_61_44MHz,
ADC_calibration_done => ADC_chb_calibration_done,
ADC_calibration_good => ADC_chb_calibration_good);
----------------------------------------------------------------------------------
-- ADC calibration Channel A
----------------------------------------------------------------------------------
ADC_auto_calibration_chA: ADC_auto_calibration
generic map(
MAX_PATTERN_CNT => MAX_PATTERN_CNT,
INIT_IDELAY => CHA_IDELAY
)
Port map(
reset => arst,
clk => clk_61_44Mhz,
ADC_calibration_start => ADC_cha_calibration_start,
ADC_data => adc_dout_i,
re_mux_polarity => adc_cha_re_mux_polarity,
trace_edge => ADC_cha_trace_edge,
ADC_calibration_state => ADC_cha_calibration_state,
iDelay_cnt => cha_cntvaluein_update_61_44MHz,
iDelay_inc_en => cha_inc_update_61_44MHz,
ADC_calibration_done => ADC_cha_calibration_done,
ADC_calibration_good => ADC_cha_calibration_good);
ADC_calibration_good <= ADC_chb_calibration_good AND ADC_cha_calibration_good;
----------------------------------------------------------------------------------------------------
-- IDELAY Control
----------------------------------------------------------------------------------------------------
ce_a <= cha_incin;
ce_b <= chb_incin;
arst <= vio_data(0) or not mmcm_locked;
--arst <= vio_data(0);
clk_61_44MHz_n <= not clk_61_44MHz;
----------------------------------------------------------------------------------------------------
-- Reset sequence
----------------------------------------------------------------------------------------------------
process (mmcm_adac_locked, clk_61_44MHz)
variable cnt : integer range 0 to 1023 := 0;
begin
if (mmcm_adac_locked = '0') then
rst <= '1';
io_rst <= '0';
frame <= '0';
txenable <= '0';
elsif (rising_edge(clk_61_44MHz)) then
-- Finally the TX enable for the DAC can by pulled high.
-- DDC and DUC are kept in reset state for a while...
if (cnt < 1023) then
cnt := cnt + 1;
rst <= '1';
else
cnt := cnt;
rst <= '0';
end if;
-- The OSERDES blocks are synchronously reset for one clock cycle...
if (cnt = 255) then
io_rst <= '1';
else
io_rst <= '0';
end if;
if (cnt = 1023) then
txenable <= '1';
txen <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Channel A data from ADC
----------------------------------------------------------------------------------------------------
adc_data_a: for i in 0 to 6 generate
-- Differantial input buffer with termination (LVDS)
ibufds_inst : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => cha_p(i),
ib => cha_n(i),
o => cha_ddr(i)
);
-- Input delay
iodelay_inst : iodelay2
generic map (
DATA_RATE => "DDR",
IDELAY_VALUE => CHA_IDELAY,
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
COUNTER_WRAPAROUND => "STAY_AT_LIMIT",
DELAY_SRC => "IDATAIN",
SERDES_MODE => "NONE",
SIM_TAPDELAY_VALUE => 75
)
port map (
idatain => cha_ddr(i),
dataout => cha_ddr_dly(i),
t => '1',
odatain => '0',
ioclk0 => clk_61_44MHz,
ioclk1 => clk_61_44MHz_n,
clk => clk_61_44MHz,
cal => '0',
inc => cha_incin,
ce => ce_a,
busy => open,
rst => sysrst
);
-- DDR to SDR
iddr_inst_cha : IDDR2
generic map (
-- DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
DDR_ALIGNMENT => "NONE",
INIT_Q0 => '0',
INIT_Q1 => '0',
SRTYPE => "SYNC")
port map (
q0 => cha_sdr(2*i),
q1 => cha_sdr(2*i+1),
c0 => clk_61_44MHz,
c1 => clk_61_44MHz_n,
ce => '1',
d => cha_ddr_dly(i), --cha_ddr_dly
r => sysrst,
s => '0'
);
end generate;
----------------------------------------------------------------------------------------------------
-- Channel B data from ADC
----------------------------------------------------------------------------------------------------
adc_data_b: for i in 0 to 6 generate
-- Differantial input buffer with termination (LVDS)
ibufds_inst : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => chb_p(i),
ib => chb_n(i),
o => chb_ddr(i)
);
-- Input delay
iodelay_inst : iodelay2
generic map (
DATA_RATE => "DDR",
IDELAY_VALUE => CHB_IDELAY,
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
COUNTER_WRAPAROUND => "STAY_AT_LIMIT",
DELAY_SRC => "IDATAIN",
SERDES_MODE => "NONE",
SIM_TAPDELAY_VALUE => 75
)
port map (
idatain => chb_ddr(i),
dataout => chb_ddr_dly(i),
t => '1',
odatain => '0',
ioclk0 => clk_61_44MHz,
ioclk1 => clk_61_44MHz_n,
clk => clk_61_44MHz,
cal => '0',
inc => chb_incin,
ce => ce_b,
busy => open,
rst => sysrst
);
-- DDR to SDR
iddr_inst_chb : IDDR2
generic map (
-- DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
DDR_ALIGNMENT => "NONE",
INIT_Q0 => '0',
INIT_Q1 => '0',
SRTYPE => "SYNC")
port map (
q0 => chb_sdr(2*i),
q1 => chb_sdr(2*i+1),
c0 => clk_61_44MHz,
c1 => clk_61_44MHz_n,
ce => '1',
d => chb_ddr_dly(i), --chb_ddr_dly
r => sysrst,
s => '0'
);
end generate;
----------------------------------------------------------------------------------------------------
-- Ouput 16-bit digital samples
----------------------------------------------------------------------------------------------------
process (clk_61_44MHz)
begin
if (rising_edge(clk_61_44MHz)) then
adc_cha_dout <= cha_sdr;
adc_chb_dout <= chb_sdr;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Output MUX - Select data connected to the physical DAC interface
----------------------------------------------------------------------------------------------------
process (clk_61_44MHz)
begin
if (rising_edge(clk_61_44MHz)) then
dac_cnt <= dac_cnt + 1024;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Output serdes and LVDS buffer for DAC clock
----------------------------------------------------------------------------------------------------
dac : dac3283_serializer
port map(
RST_I => sysrst,
DAC_CLK_O => dac_fpga_clk,
DAC_CLK_DIV4_O => open,
DAC_READY => dac_ready,
CH_C_I => dac_chc_din,
CH_D_I => dac_chd_din,
FMC150_CLK => clk_to_fpga,
DAC_DCLK_P => dac_dclk_p,
DAC_DCLK_N => dac_dclk_n,
DAC_DATA_P => dac_data_p,
DAC_DATA_N => dac_data_n,
FRAME_P => dac_frame_p,
FRAME_N => dac_frame_n,
IO_TEST_EN => '0'
);
----------------------------------------------------------------------------------------------------
-- Configuring the FMC150 card
----------------------------------------------------------------------------------------------------
-- the fmc150_spi_ctrl component configures the devices on the FMC150 card through the Serial
-- Peripheral Interfaces (SPI) and some additional direct control signals.
----------------------------------------------------------------------------------------------------
fmc150_spi_ctrl_inst : fmc150_spi_ctrl
port map (
init_done => fmc150_spi_ctrl_done,
rd_n_wr => rd_n_wr,
addr => addr,
idata => idata,
odata => odata,
busy => busy,
cdce72010_valid => cdce72010_valid,
ads62p49_valid => ads62p49_valid,
dac3283_valid => dac3283_valid,
amc7823_valid => amc7823_valid,
rst => arst,
clk => clk_100MHz,
external_clock => external_clock,
spi_sclk => sclk,
spi_sdata => spi_sdata,
adc_n_en => adc_n_en,
adc_sdo => adc_sdo,
adc_reset => adc_reset,
cdce_n_en => cdce_n_en,
cdce_sdo => cdce_sdo,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => ref_en,
pll_status => pll_status,
dac_n_en => dac_n_en,
dac_sdo => dac_sdo,
mon_n_en => mon_n_en,
mon_sdo => mon_sdo,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
prsnt_m2c_l => nfmc0_prsnt
);
-- ODDR2 is needed instead of the following
-- and limiting in Spartan 6
txclk_ODDR2_inst : ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => spi_sclk, -- 1-bit DDR output data
C0 => sclk, -- clock is your signal from PLL
C1 => sclk_n, -- n
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => sysrst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
sclk_n <= not sclk;
-------------------------------------------END------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Debugging Section
----------------------------------------------------------------------------------------------------
-- ila_data0(0) <= fmc150_spi_ctrl_done;
-- ila_data0(1) <= external_clock;
-- ila_data0(2) <= busy;
-- ila_data0(3) <= mmcm_adac_locked;
-- ila_data0(4) <= mmcm_locked;
-- ila_data0(5) <= pll_status;
-- ila_data0(6) <= '1' when ADC_cha_ready = TRUE else '0';
-- ila_data0(7) <= '1' when ADC_chb_ready = TRUE else '0';
-- ila_data0(8) <= txen;
-- ila_data1(13 downto 0) <= adc_dout_i;
-- ila_data1(27 downto 14)<= adc_dout_q;
-- ila_data1(41 downto 28) <= dac_cnt;
-- ila_data1(44 downto 42) <= ADC_chb_calibration_state;
-- ila_data1(49 downto 45) <= cha_cntvaluein;
-- ila_data1(50) <= ADC_calibration_good;
--trig0(0) <= busy;--cmd_state(3 downto 0);--busy;--init_done;
-- trig1(2 downto 0) <= ADC_chb_calibration_state;
------ instantiate chipscope components -------
-- icon_inst : icon
-- port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1,
-- CONTROL2 => CONTROL2
-- );
-- ila_data0_inst : ila0
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_100MHz,--clk_245_76MHz,
-- DATA => ila_data0,
-- TRIG0 => TRIG0);
-- ila_data1_inst : ila1
-- port map (
-- CONTROL => CONTROL2,
-- CLK => clk_61_44MHz,
-- DATA => ila_data1,
-- TRIG0 => TRIG1);
-- vio_inst : vio
-- port map (
-- CONTROL => CONTROL1,
-- ASYNC_OUT => vio_data);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end rtl;
| gpl-3.0 | 1fe6eca847bbe00bb736251c45c6e5b0 | 0.519149 | 3.515974 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_cycle_sequence.vhd | 1 | 1,308 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_cycle_sequence is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : ovl_positive_2 := 2;
necessary_condition : ovl_necessary_condition := OVL_TRIGGER_ON_MOST_PIPE;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
event_sequence : in std_logic_vector(num_cks - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_cycle_sequence;
| mit | 50043e96d6e7ac6eaf06ff44c4f2b2b2 | 0.570336 | 3.379845 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Medium/bcd_counter.vhd | 1 | 1,758 | --Continuously count every clk tick while enable is active
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_counter is
port ( rst : in std_logic;
en : in std_logic;
-- 2 BCD Digits
bcd_out : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end bcd_counter;
architecture Behavioral of bcd_counter is
COMPONENT bcd_2_adder port (
Carry_in : in std_logic;
Carry_out : out std_logic;
Adig0: in STD_LOGIC_VECTOR (3 downto 0);
Adig1: in STD_LOGIC_VECTOR (3 downto 0);
Bdig0: in STD_LOGIC_VECTOR (3 downto 0);
Bdig1: in STD_LOGIC_VECTOR (3 downto 0);
Sdig0: out STD_LOGIC_VECTOR (3 downto 0);
Sdig1: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
--Inputs
signal digit_A : std_logic_vector (7 downto 0) := (others => '0');
signal digit_B : std_logic_vector (7 downto 0) := (others => '0');
signal carry_in : std_logic := '0';
--Outputs
signal carry_out : std_logic;
signal sum : std_logic_vector (7 downto 0);
--signal counter : std_logic_vector (7 downto 0) := (others => '0');
begin
m1: bcd_2_adder port map( carry_in, carry_out,
digit_A(3 downto 0), digit_A(7 downto 4),
digit_B(3 downto 0), digit_B(7 downto 4),
sum(3 downto 0) , sum(7 downto 4) );
bcd_out <= sum;
process (clk, rst, en) begin
if (rst = '1') then
--counter <= (others => '0');
digit_A <= (others => '0');
carry_in <= '0';
digit_B(0) <= '0';
elsif (clk'event and clk = '1') then
digit_A <= sum;
carry_in <= carry_out;
if (en = '1') then
digit_B(0) <= '1';
else
digit_B(0) <= '0';
--digit_B <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| apache-2.0 | 29d91c1b282bd9e824df2056f95ceb71 | 0.574516 | 2.781646 | false | false | false | false |
jmgc/myhdl-numeric | vhdl/fixed_pkg_c.vhdl | 1 | 303,533 | -- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.math_utility_pkg.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 1.17 $
-- Date : $Date: 2007-05-31 14:52:33-04 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the length
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- Conversion from sfixed to ufixed (performs an "abs" function)
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_suv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_suv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_suv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_suv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_suv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_suv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 1.17 $
-- Date : $Date: 2007-05-31 14:52:33-04 $
--
-- Created for VHDL-200X-ft, David Bishop ([email protected])
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_suv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_suv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_suv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_suv;
function to_suv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_suv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_suv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_suv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_suv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) and to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) or to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) nand to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) nor to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) xor to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) xnor to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_suv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) and to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) or to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) nand to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) nor to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) xor to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_suv(L) xnor to_suv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_suv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_suv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_suv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_suv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_suv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_suv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_suv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_suv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_suv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_suv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_suv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_suv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_suv(L), to_suv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_suv(L), to_suv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_suv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_suv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_suv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_suv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_suv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_suv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_suv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_suv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_suv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_suv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_suv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_suv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_suv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s(1 to (sindx-1)), justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s(1 to (sindx - 1)), justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low > 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low > 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low > 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -1));
end if;
else
slv := to_suv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low > 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_suv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low > 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_suv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low > 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_suv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
| lgpl-2.1 | 43e83207f38d1ec89444ecc15e99e693 | 0.568271 | 3.978152 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/DUT/three_cycle_mult.vhd | 1 | 2,574 | -- *******************************************************************
-- Copyright 2008 Ray Salemi
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ********************************************************************
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
| mit | c40b10028c18746e2f00fc7fba5de2ef | 0.566434 | 3.802068 | false | false | false | false |
willtmwu/vhdlExamples | Project/top_controller_test.vhd | 1 | 10,594 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: top_controller_test.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Testing the RAM loading and full packet sending
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
LIBRARY work;
use work.project_nrf_subprogV2.all;
ENTITY top_controller_test IS
END top_controller_test;
ARCHITECTURE behavior OF top_controller_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_controller
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
bSend : IN std_logic;
bModeChange : IN std_logic;
bEnterData : IN std_logic;
bCount : IN std_logic;
sTransmission : IN std_logic_vector(2 downto 0);
sHighSpeed : IN std_logic;
displayLower : OUT std_logic_vector(15 downto 0);
displayUpper : OUT std_logic_vector(15 downto 0);
data_nib : IN std_logic_vector(3 downto 0);
hamming_err : IN std_logic_vector(7 downto 0);
IRQ : IN std_logic;
CE : OUT std_logic;
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic;
LED_SPI : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal masterReset : std_logic := '1';
signal bSend : std_logic := '0';
signal bModeChange : std_logic := '0';
signal bEnterData : std_logic := '0';
signal bCount : std_logic := '0';
signal sTransmission : std_logic_vector(2 downto 0) := (others => '0');
signal sHighSpeed : std_logic := '1';
signal data_nib : std_logic_vector(3 downto 0) := (others => '0');
signal hamming_err : std_logic_vector(7 downto 0) := (others => '0');
signal IRQ : std_logic := '1';
signal MISO : std_logic := '0';
--Outputs
signal displayLower : std_logic_vector(15 downto 0);
signal displayUpper : std_logic_vector(15 downto 0);
signal CE : std_logic;
signal CS : std_logic;
signal SCLK : std_logic;
signal MOSI : std_logic;
signal LED_SPI : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
procedure ENTER_NIB (
nib : in std_logic_vector(3 downto 0) ;
signal bEnterData : out std_logic;
signal data_nib : out std_logic_vector(3 downto 0)
) is
begin
wait until rising_edge(clk);
bEnterData <= '0';
wait until rising_edge(clk);
data_nib <= nib;
bEnterData <= '1';
wait until rising_edge(clk);
bEnterData <= '0';
wait until rising_edge(clk);
end ENTER_NIB;
procedure BUTTON_PULSE (
signal button : out std_logic
) is
begin
wait until rising_edge(clk);
button <= '0';
wait until rising_edge(clk);
button <= '1';
wait until rising_edge(clk);
button <= '0';
wait until rising_edge(clk);
end BUTTON_PULSE;
procedure FILL_RAM (
signal bEnterData : out std_logic;
signal bCount : out std_logic;
signal data_nib: out std_logic_vector( 3 downto 0)
) is
begin
for i in 0 to 31 loop
for j in 0 to 1 loop
if(j=0) then
ENTER_NIB(to_BCD(std_logic_vector(IEEE.numeric_std.to_unsigned(i, 5)))(3 downto 0), bEnterData,data_nib);
else
ENTER_NIB(to_BCD(std_logic_vector(IEEE.numeric_std.to_unsigned(i, 5)))(7 downto 4), bEnterData,data_nib);
end if;
end loop;
BUTTON_PULSE(bCount);
end loop;
end FILL_RAM;
procedure SPI_MISO (
byte_in : in std_logic_vector(7 downto 0) ;
signal MISO : out std_logic
) is
begin
for i in 7 downto 0 loop
MISO <= byte_in(i);
wait until falling_edge(SCLK);
end loop;
end SPI_MISO;
procedure NRF_MESSAGE (
byte_0 : in std_logic_vector(7 downto 0) ;
byte_1 : in std_logic_vector(7 downto 0) ;
byte_2 : in std_logic_vector(7 downto 0) ;
byte_3 : in std_logic_vector(7 downto 0) ;
byte_4 : in std_logic_vector(7 downto 0) ;
byte_5 : in std_logic_vector(7 downto 0) ;
byte_6 : in std_logic_vector(7 downto 0) ;
byte_7 : in std_logic_vector(7 downto 0) ;
byte_8 : in std_logic_vector(7 downto 0) ;
byte_9 : in std_logic_vector(7 downto 0) ;
byte_10 : in std_logic_vector(7 downto 0) ;
byte_11 : in std_logic_vector(7 downto 0) ;
byte_12 : in std_logic_vector(7 downto 0) ;
byte_13 : in std_logic_vector(7 downto 0) ;
signal MISO : out std_logic;
signal IRQ : out std_logic;
signal CS : in std_logic
) is
begin
-- Message Arrival, Ensure IRQ is active high
wait until rising_edge(clk);
IRQ <= '0';
wait until rising_edge(clk);
IRQ <= '1';
SPI_MISO("11111101", MISO);
SPI_MISO("11000001", MISO);
wait until falling_edge(SCLK);
-- Send Through a message, In Hex, start wit basic location
SPI_MISO(x"FF", MISO); -- REG
-- Packet Type
SPI_MISO(x"00", MISO); -- 0
SPI_MISO(x"2B", MISO); -- 1
-- ADDR
SPI_MISO(x"8E", MISO); -- 2
SPI_MISO(x"71", MISO); -- 3
SPI_MISO(x"6C", MISO); -- 4
SPI_MISO(x"5A", MISO); -- 5
SPI_MISO(x"47", MISO); -- 6
SPI_MISO(x"36", MISO); -- 7
SPI_MISO(x"2B", MISO); -- 8
SPI_MISO(x"1D", MISO); -- 9
-- ADDR
SPI_MISO(x"2A", MISO); -- 10
SPI_MISO(x"47", MISO); -- 11
SPI_MISO(x"1D", MISO); -- 12
SPI_MISO(x"93", MISO); -- 13
SPI_MISO(x"2B", MISO); -- 14
SPI_MISO(x"36", MISO); -- 15
SPI_MISO(x"8E", MISO); -- 16
SPI_MISO(x"5A", MISO); -- 17
-- Message
SPI_MISO(Byte_13, MISO); -- 18
SPI_MISO(Byte_12, MISO); -- 19
SPI_MISO(Byte_11, MISO); -- 20
SPI_MISO(Byte_10, MISO); -- 21
SPI_MISO(Byte_9, MISO); -- 22
SPI_MISO(Byte_8, MISO); -- 23
SPI_MISO(Byte_7, MISO); -- 24
SPI_MISO(Byte_6, MISO); -- 25
SPI_MISO(Byte_5, MISO); -- 26
SPI_MISO(Byte_4, MISO); -- 27
SPI_MISO(Byte_3, MISO); -- 28
SPI_MISO(Byte_2, MISO); -- 29
SPI_MISO(Byte_1, MISO); -- 30
SPI_MISO(Byte_0, MISO); -- 31
wait until rising_edge(clk);
wait for clk_period*1000;
wait until rising_edge(clk);
end NRF_MESSAGE;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_controller PORT MAP (
clk => clk,
masterReset => masterReset,
bSend => bSend,
bModeChange => bModeChange,
bEnterData => bEnterData,
bCount => bCount,
sTransmission => sTransmission,
sHighSpeed => sHighSpeed,
displayLower => displayLower,
displayUpper => displayUpper,
data_nib => data_nib,
hamming_err => hamming_err,
IRQ => IRQ,
CE => CE,
CS => CS,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
LED_SPI => LED_SPI
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period*10;
masterReset <= '0';
wait for 10_000_200ns;
wait until rising_edge(clk);
wait for clk_period*10;
FILL_RAM(bEnterData, bCount, data_nib);
wait for clk_period*10;
BUTTON_PULSE(bSend);
wait for 55_850_000ns;
-- NRF_MESSAGE (
-- x"B8", -- Byte 0
-- x"A5", -- Byte 1
-- x"93", -- Byte 2
-- x"8E", -- Byte 3
-- x"71", -- Byte 4
-- x"6C", -- Byte 5
-- x"5A", -- Byte 6
-- x"47", -- Byte 7
-- x"36", -- Byte 8
-- x"2B", -- Byte 9
-- x"1D", -- Byte 10
-- x"00", -- Byte 11
-- x"00", -- Byte 12
-- x"FF", -- Byte 13
-- MISO,IRQ,CS
-- );
-- FF 0 0 1D 0 2B 0 36 0 47 0 5A 0 6C
-- NRF_MESSAGE (
-- x"6C", -- Byte 0
-- x"00", -- Byte 1
-- x"5A", -- Byte 2
-- x"00", -- Byte 3
-- x"47", -- Byte 4
-- x"00", -- Byte 5
-- x"36", -- Byte 6
-- x"00", -- Byte 7
-- x"2B", -- Byte 8
-- x"00", -- Byte 9
-- x"1D", -- Byte 10
-- x"00", -- Byte 11
-- x"00", -- Byte 12
-- x"FF", -- Byte 13
-- MISO,IRQ,CS
-- );
--
-- -- FF 1D 0 71 0 8E 0 93 1D 0 1D 1D 1D 2B
-- NRF_MESSAGE (
-- x"2B", -- Byte 0
-- x"1D", -- Byte 1
-- x"1D", -- Byte 2
-- x"1D", -- Byte 3
-- x"00", -- Byte 4
-- x"1D", -- Byte 5
-- x"93", -- Byte 6
-- x"00", -- Byte 7
-- x"8E", -- Byte 8
-- x"00", -- Byte 9
-- x"71", -- Byte 10
-- x"00", -- Byte 11
-- x"1D", -- Byte 12
-- x"FF", -- Byte 13
-- MISO,IRQ,CS
-- );
--
-- -- FF 2B 1D 36 1D 47 1D 5A 1D 6C 1D 71 1D 8E
-- NRF_MESSAGE (
-- x"8E", -- Byte 0
-- x"1D", -- Byte 1
-- x"71", -- Byte 2
-- x"1D", -- Byte 3
-- x"6C", -- Byte 4
-- x"1D", -- Byte 5
-- x"5A", -- Byte 6
-- x"1D", -- Byte 7
-- x"47", -- Byte 8
-- x"1D", -- Byte 9
-- x"36", -- Byte 10
-- x"1D", -- Byte 11
-- x"2B", -- Byte 12
-- x"FF", -- Byte 13
-- MISO,IRQ,CS
-- );
--
-- -- FF 36 1D 93 2B 0 2B 1D 2B 2B 2B 36 2B 47
-- NRF_MESSAGE (
-- x"47", -- Byte 0
-- x"2B", -- Byte 1
-- x"36", -- Byte 2
-- x"2B", -- Byte 3
-- x"2B", -- Byte 4
-- x"2B", -- Byte 5
-- x"1D", -- Byte 6
-- x"2B", -- Byte 7
-- x"00", -- Byte 8
-- x"2B", -- Byte 9
-- x"93", -- Byte 10
-- x"1D", -- Byte 11
-- x"36", -- Byte 12
-- x"FF", -- Byte 13
-- MISO,IRQ,CS
-- );
--
-- -- FF 47 2B 5A 2B 6C 2B 71 2B 8E 2B 93 36 0
-- NRF_MESSAGE (
-- x"00", -- Byte 0
-- x"36", -- Byte 1
-- x"93", -- Byte 2
-- x"2B", -- Byte 3
-- x"8E", -- Byte 4
-- x"2B", -- Byte 5
-- x"71", -- Byte 6
-- x"2B", -- Byte 7
-- x"6C", -- Byte 8
-- x"2B", -- Byte 9
-- x"5A", -- Byte 10
-- x"2B", -- Byte 11
-- x"47", -- Byte 12
-- x"FF", -- Byte 13
-- MISO,IRQ,CS
-- );
-- FF 5A 36 1D 36 2B 0 1D 0 2B 0 36 0 47
NRF_MESSAGE (
x"47", -- Byte 0
x"00", -- Byte 1
x"36", -- Byte 2
x"00", -- Byte 3
x"2B", -- Byte 4
x"00", -- Byte 5
x"1D", -- Byte 6
x"00", -- Byte 7
x"2B", -- Byte 8
x"36", -- Byte 9
x"1D", -- Byte 10
x"36", -- Byte 11
x"5A", -- Byte 12
x"FF", -- Byte 13
MISO,IRQ,CS
);
wait;
end process;
END;
| apache-2.0 | e770a7d3a7a9c7fbec38838713bfe220 | 0.520861 | 2.589587 | false | false | false | false |
scarter93/RSA-Encryption | modular_exponentiation_tb.vhd | 1 | 2,984 | -- Entity name: modular_exponentiation_tb
-- Author: Luis Gallet, Jacob Barnett
-- Contact: [email protected], [email protected]
-- Date: April 12, 2016
-- Description:
-- Testbench for modular_exponentiation.vhd and mod_exp_comparison.vhd
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity modular_exponentiation_tb is
end entity;
architecture test of modular_exponentiation_tb is
component mod_exp_comparison is
generic(
WIDTH_IN : integer := 64
);
port( N : in unsigned(WIDTH_IN-1 downto 0); --Number
Exp : in unsigned(WIDTH_IN-1 downto 0); --Exponent
M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0) --Output
);
end component;
CONSTANT WIDTH_IN : integer := 64;
CONSTANT clk_period : time := 1 ns;
Signal M_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
Signal N_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
Signal Exp_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal latch_in : std_logic := '0';
Signal clk : std_logic := '0';
Signal reset_t : std_logic := '0';
Signal C_out : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
Begin
-- device under test
dut: mod_exp_comparison
generic map(WIDTH_IN => WIDTH_IN)
PORT MAP( N => N_in,
Exp => Exp_in,
M => M_in,
clk => clk,
reset => reset_t,
C => C_out
);
-- process for clock
clk_process : Process
Begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_process: process
Begin
reset_t <= '1';
wait for 1 * clk_period;
reset_t <= '0';
wait for 1 * clk_period;
REPORT "Begin test case for base=9014435050856796582, exp=65537, mod=10976230439201618177";
REPORT "Expected output is 10386396763144533567, 1001000000100011111001001101001110011011011111110011011000111111";
N_in <= "0111110100011001101101001110101100010001001001100101000110100110";
Exp_in <= "0000000000000000000000000000000000000000000000010000000000000001";
M_in <= "1001100001010011011001110110111000001101011100010011100100000001";
wait for 8513 * clk_period;
ASSERT(C_out = "1001000000100011111001001101001110011011011111110011011000111111") REPORT "test failed" SEVERITY NOTE;
REPORT "Begin test case for base=10386396763144533567, exp=6302493663540011453, mod=10976230439201618177";
REPORT "Expected output is 9014435050856796582, 0111110100011001101101001110101100010001001001100101000110100110";
N_in <= "1001000000100011111001001101001110011011011111110011011000111111";
Exp_in <= "0101011101110110111101001001100001001110011100111110000110111101";
M_in <= "1001100001010011011001110110111000001101011100010011100100000001";
wait for 8513 * clk_period;
ASSERT(C_out = "0111110100011001101101001110101100010001001001100101000110100110") REPORT "test failed" SEVERITY NOTE;
wait;
end process;
end;
| mit | 9cb8315ac24e05e698106f33343e7198 | 0.732909 | 3.174468 | false | true | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/DPU_matrix_multiplication/netgen/par/DPU_matrix_multiplication_timesim.vhd | 1 | 52,935 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: DPU_matrix_multiplication_timesim.vhd
-- /___/ /\ Timestamp: Mon Feb 22 00:04:32 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -s 4 -pcf DPU_matrix_multiplication.pcf -rpw 100 -tpw 0 -ar Structure -tm DPU_matrix_multiplication -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim DPU_matrix_multiplication.ncd DPU_matrix_multiplication_timesim.vhd
-- Device : 3s400tq144-4 (PRODUCTION 1.39 2013-10-13)
-- Input file : DPU_matrix_multiplication.ncd
-- Output file : E:\Works\GitHub\Systolic-Processor-On-FPGA\ISE Design Files\DPU_matrix_multiplication\netgen\par\DPU_matrix_multiplication_timesim.vhd
-- # of Entities : 1
-- Design Name : DPU_matrix_multiplication
-- Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity DPU_matrix_multiplication is
port (
CLK : in STD_LOGIC := 'X';
Result : out STD_LOGIC_VECTOR ( 9 downto 0 );
Bout : out STD_LOGIC_VECTOR ( 3 downto 0 );
Aout : out STD_LOGIC_VECTOR ( 3 downto 0 );
Ain : in STD_LOGIC_VECTOR ( 3 downto 0 );
Bin : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end DPU_matrix_multiplication;
architecture Structure of DPU_matrix_multiplication is
signal CLK_BUFGP : STD_LOGIC;
signal Ain_1_IBUF_376 : STD_LOGIC;
signal R2_DFF2_Q_377 : STD_LOGIC;
signal Ain_2_IBUF_378 : STD_LOGIC;
signal R2_DFF3_Q_379 : STD_LOGIC;
signal Ain_3_IBUF_380 : STD_LOGIC;
signal R2_DFF4_Q_381 : STD_LOGIC;
signal R2_DFF5_Q_382 : STD_LOGIC;
signal R2_DFF6_Q_383 : STD_LOGIC;
signal R2_DFF7_Q_384 : STD_LOGIC;
signal R2_DFF8_Q_385 : STD_LOGIC;
signal R2_DFF9_Q_386 : STD_LOGIC;
signal R1_DFF0_Q_1_387 : STD_LOGIC;
signal R1_DFF1_Q_1_389 : STD_LOGIC;
signal R1_DFF2_Q_1_391 : STD_LOGIC;
signal R1_DFF3_Q_1_393 : STD_LOGIC;
signal R0_DFF0_Q_1_395 : STD_LOGIC;
signal R1_DFF2_Q_399 : STD_LOGIC;
signal R0_DFF1_Q_400 : STD_LOGIC;
signal R0_DFF2_Q_403 : STD_LOGIC;
signal R1_DFF1_Q_404 : STD_LOGIC;
signal R1_DFF0_Q_405 : STD_LOGIC;
signal MAC_S2_1_0 : STD_LOGIC;
signal R2_DFF1_Q_408 : STD_LOGIC;
signal R2_DFF0_Q_409 : STD_LOGIC;
signal R0_DFF0_Q_411 : STD_LOGIC;
signal N7_0 : STD_LOGIC;
signal N6_0 : STD_LOGIC;
signal FA_FA6_Cout1_O : STD_LOGIC;
signal FA_D_5_0 : STD_LOGIC;
signal FA_FA6_Cout1_SW2_O : STD_LOGIC;
signal N15_0 : STD_LOGIC;
signal S3_7_0 : STD_LOGIC;
signal FA_D_1_0 : STD_LOGIC;
signal FA_FA6_Cout1_SW0_O : STD_LOGIC;
signal MAC_C3_2_0 : STD_LOGIC;
signal R1_DFF3_Q_423 : STD_LOGIC;
signal R0_DFF3_Q_424 : STD_LOGIC;
signal MAC_S3_2_0 : STD_LOGIC;
signal N2_0 : STD_LOGIC;
signal MAC_HAM23_A : STD_LOGIC;
signal MAC_FAM30_A_0 : STD_LOGIC;
signal MAC_C2_0_0 : STD_LOGIC;
signal MAC_S2_2_0 : STD_LOGIC;
signal MAC_C2_1_0 : STD_LOGIC;
signal S3_4_0 : STD_LOGIC;
signal FA_D_2_0 : STD_LOGIC;
signal N11_0 : STD_LOGIC;
signal FA_D_3_0 : STD_LOGIC;
signal N18_0 : STD_LOGIC;
signal S3_5_0 : STD_LOGIC;
signal MAC_S1_1_0 : STD_LOGIC;
signal MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O : STD_LOGIC;
signal N4_0 : STD_LOGIC;
signal Aout_2_O : STD_LOGIC;
signal Aout_1_O : STD_LOGIC;
signal Result_2_O : STD_LOGIC;
signal MAC_S3_1_pack_1 : STD_LOGIC;
signal MAC_C3_1_pack_1 : STD_LOGIC;
signal MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O_pack_1 : STD_LOGIC;
signal R2_DFF6_Q_DYMUX_1195 : STD_LOGIC;
signal R2_DFF6_Q_CLKINV_1186 : STD_LOGIC;
signal S3_3_pack_1 : STD_LOGIC;
signal MAC_FAM30_A : STD_LOGIC;
signal R2_DFF0_Q_DYMUX_1216 : STD_LOGIC;
signal R2_DFF0_Q_CLKINV_1207 : STD_LOGIC;
signal N15 : STD_LOGIC;
signal S3_6_pack_1 : STD_LOGIC;
signal R2_DFF2_Q_DYMUX_1243 : STD_LOGIC;
signal R2_DFF2_Q_CLKINV_1234 : STD_LOGIC;
signal R2_DFF4_Q_DYMUX_1279 : STD_LOGIC;
signal R2_DFF4_Q_CLKINV_1270 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal R2_DFF5_Q_DYMUX_1177 : STD_LOGIC;
signal R2_DFF5_Q_CLKINV_1168 : STD_LOGIC;
signal R0_DFF0_Q_DYMUX_1312 : STD_LOGIC;
signal R0_DFF0_Q_CLKINV_1310 : STD_LOGIC;
signal MAC_C1_0_pack_2 : STD_LOGIC;
signal R2_DFF3_Q_DYMUX_1261 : STD_LOGIC;
signal R2_DFF3_Q_CLKINV_1252 : STD_LOGIC;
signal FA_D_4_pack_1 : STD_LOGIC;
signal N7 : STD_LOGIC;
signal N6 : STD_LOGIC;
signal R0_DFF1_Q_DYMUX_1345 : STD_LOGIC;
signal R0_DFF1_Q_CLKINV_1343 : STD_LOGIC;
signal R0_DFF2_Q_DYMUX_1354 : STD_LOGIC;
signal R0_DFF2_Q_CLKINV_1352 : STD_LOGIC;
signal MAC_S1_2_pack_1 : STD_LOGIC;
signal MAC_C2_2_pack_1 : STD_LOGIC;
signal MAC_HAM23_A_pack_1 : STD_LOGIC;
signal S3_2_pack_1 : STD_LOGIC;
signal R0_DFF3_Q_DYMUX_1363 : STD_LOGIC;
signal R0_DFF3_Q_CLKINV_1361 : STD_LOGIC;
signal R1_DFF0_Q_DYMUX_1372 : STD_LOGIC;
signal R1_DFF0_Q_CLKINV_1370 : STD_LOGIC;
signal R1_DFF1_Q_DYMUX_1381 : STD_LOGIC;
signal R1_DFF1_Q_CLKINV_1379 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal R1_DFF3_Q_DYMUX_1411 : STD_LOGIC;
signal R1_DFF3_Q_CLKINV_1409 : STD_LOGIC;
signal Aout_0_O : STD_LOGIC;
signal Result_0_O : STD_LOGIC;
signal Result_1_O : STD_LOGIC;
signal R1_DFF2_Q_DYMUX_1402 : STD_LOGIC;
signal R1_DFF2_Q_CLKINV_1400 : STD_LOGIC;
signal N18 : STD_LOGIC;
signal Aout_3_O : STD_LOGIC;
signal Result_3_O : STD_LOGIC;
signal Result_7_O : STD_LOGIC;
signal Bin_0_IFF_IFFDMUX_570 : STD_LOGIC;
signal Bin_0_IFF_ICLK1INV_572 : STD_LOGIC;
signal Bin_0_INBUF : STD_LOGIC;
signal Bin_1_INBUF : STD_LOGIC;
signal Result_8_O : STD_LOGIC;
signal Result_6_O : STD_LOGIC;
signal Result_5_O : STD_LOGIC;
signal Result_9_O : STD_LOGIC;
signal Result_4_O : STD_LOGIC;
signal Bin_2_INBUF : STD_LOGIC;
signal Bin_3_INBUF : STD_LOGIC;
signal Bout_1_O : STD_LOGIC;
signal Bout_0_O : STD_LOGIC;
signal Ain_1_INBUF : STD_LOGIC;
signal Ain_0_INBUF : STD_LOGIC;
signal Bout_2_O : STD_LOGIC;
signal Bout_3_O : STD_LOGIC;
signal CLK_INBUF : STD_LOGIC;
signal R2_DFF1_Q_DXMUX_757 : STD_LOGIC;
signal S3_0_pack_2 : STD_LOGIC;
signal R2_DFF1_Q_CLKINV_740 : STD_LOGIC;
signal Ain_3_INBUF : STD_LOGIC;
signal Ain_2_INBUF : STD_LOGIC;
signal R2_DFF9_Q_DXMUX_787 : STD_LOGIC;
signal FA_FA6_Cout1_O_pack_2 : STD_LOGIC;
signal R2_DFF9_Q_CLKINV_771 : STD_LOGIC;
signal S3_1_pack_1 : STD_LOGIC;
signal MAC_C1_1_pack_2 : STD_LOGIC;
signal R2_DFF7_Q_DXMUX_871 : STD_LOGIC;
signal FA_FA6_Cout1_SW0_O_pack_2 : STD_LOGIC;
signal R2_DFF7_Q_CLKINV_854 : STD_LOGIC;
signal R2_DFF8_Q_DXMUX_817 : STD_LOGIC;
signal FA_FA6_Cout1_SW2_O_pack_2 : STD_LOGIC;
signal R2_DFF8_Q_CLKINV_802 : STD_LOGIC;
signal CLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal CLK_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal MAC_C4_1_pack_1 : STD_LOGIC;
signal Aout_2_OUTPUT_OFF_O1INV_484 : STD_LOGIC;
signal R0_DFF2_Q_1_487 : STD_LOGIC;
signal Aout_2_OUTPUT_OTCLK1INV_481 : STD_LOGIC;
signal Aout_3_OUTPUT_OFF_O1INV_508 : STD_LOGIC;
signal R0_DFF3_Q_1_511 : STD_LOGIC;
signal Aout_3_OUTPUT_OTCLK1INV_505 : STD_LOGIC;
signal Aout_1_OUTPUT_OFF_O1INV_460 : STD_LOGIC;
signal R0_DFF1_Q_1_463 : STD_LOGIC;
signal Aout_1_OUTPUT_OTCLK1INV_457 : STD_LOGIC;
signal Ain_0_IFF_ICLK1INV_672 : STD_LOGIC;
signal Ain_0_IFF_IFFDMUX_670 : STD_LOGIC;
signal Bin_1_IFF_ICLK1INV_589 : STD_LOGIC;
signal Bin_1_IFF_IFFDMUX_587 : STD_LOGIC;
signal Bin_2_IFF_ICLK1INV_606 : STD_LOGIC;
signal Bin_2_IFF_IFFDMUX_604 : STD_LOGIC;
signal Bin_3_IFF_ICLK1INV_623 : STD_LOGIC;
signal Bin_3_IFF_IFFDMUX_621 : STD_LOGIC;
signal VCC : STD_LOGIC;
signal GND : STD_LOGIC;
signal MAC_C1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal MAC_S1 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal S3 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal MAC_C4 : STD_LOGIC_VECTOR ( 1 downto 1 );
signal MAC_C3 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal MAC_S3 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal MAC_C2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal FA_D : STD_LOGIC_VECTOR ( 5 downto 1 );
signal MAC_S2 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal S6 : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
Aout_2_OBUF : X_OBUF
generic map(
LOC => "PAD181"
)
port map (
I => Aout_2_O,
O => Aout(2)
);
Aout_1_OBUF : X_OBUF
generic map(
LOC => "PAD236"
)
port map (
I => Aout_1_O,
O => Aout(1)
);
Result_2_OBUF : X_OBUF
generic map(
LOC => "PAD222"
)
port map (
I => Result_2_O,
O => Result(2)
);
S3_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X5Y6",
PATHPULSE => 605 ps
)
port map (
I => S3(4),
O => S3_4_0
);
S3_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_S3_1_pack_1,
O => MAC_S3(1)
);
S3_5_XUSED : X_BUF
generic map(
LOC => "SLICE_X7Y6",
PATHPULSE => 605 ps
)
port map (
I => S3(5),
O => S3_5_0
);
S3_5_YUSED : X_BUF
generic map(
LOC => "SLICE_X7Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_C3_1_pack_1,
O => MAC_C3(1)
);
MAC_S2_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_S2(2),
O => MAC_S2_2_0
);
MAC_S2_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X6Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O_pack_1,
O => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O
);
R2_DFF6_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y8",
PATHPULSE => 605 ps
)
port map (
I => S6(6),
O => R2_DFF6_Q_DYMUX_1195
);
R2_DFF6_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y8",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF6_Q_CLKINV_1186
);
FA_D_3_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y6",
PATHPULSE => 605 ps
)
port map (
I => FA_D(3),
O => FA_D_3_0
);
FA_D_3_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y6",
PATHPULSE => 605 ps
)
port map (
I => S3_3_pack_1,
O => S3(3)
);
R2_DFF0_Q_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y8",
PATHPULSE => 605 ps
)
port map (
I => MAC_FAM30_A,
O => MAC_FAM30_A_0
);
R2_DFF0_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X4Y8",
PATHPULSE => 605 ps
)
port map (
I => S6(0),
O => R2_DFF0_Q_DYMUX_1216
);
R2_DFF0_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X4Y8",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF0_Q_CLKINV_1207
);
N15_XUSED : X_BUF
generic map(
LOC => "SLICE_X5Y7",
PATHPULSE => 605 ps
)
port map (
I => N15,
O => N15_0
);
N15_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y7",
PATHPULSE => 605 ps
)
port map (
I => S3_6_pack_1,
O => S3(6)
);
R2_DFF2_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X5Y8",
PATHPULSE => 605 ps
)
port map (
I => S6(2),
O => R2_DFF2_Q_DYMUX_1243
);
R2_DFF2_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X5Y8",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF2_Q_CLKINV_1234
);
R2_DFF4_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y7",
PATHPULSE => 605 ps
)
port map (
I => S6(4),
O => R2_DFF4_Q_DYMUX_1279
);
R2_DFF4_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y7",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF4_Q_CLKINV_1270
);
N4_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y6",
PATHPULSE => 605 ps
)
port map (
I => N4,
O => N4_0
);
N4_YUSED : X_BUF
generic map(
LOC => "SLICE_X6Y6",
PATHPULSE => 605 ps
)
port map (
I => N11,
O => N11_0
);
R2_DFF5_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y6",
PATHPULSE => 605 ps
)
port map (
I => S6(5),
O => R2_DFF5_Q_DYMUX_1177
);
R2_DFF5_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y6",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF5_Q_CLKINV_1168
);
R0_DFF0_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X1Y5",
PATHPULSE => 605 ps
)
port map (
I => Ain_0_INBUF,
O => R0_DFF0_Q_DYMUX_1312
);
R0_DFF0_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X1Y5",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF0_Q_CLKINV_1310
);
MAC_C2_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_C2(0),
O => MAC_C2_0_0
);
MAC_C2_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_C1_0_pack_2,
O => MAC_C1(0)
);
R2_DFF3_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y7",
PATHPULSE => 605 ps
)
port map (
I => S6(3),
O => R2_DFF3_Q_DYMUX_1261
);
R2_DFF3_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y7",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF3_Q_CLKINV_1252
);
FA_D_5_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y6",
PATHPULSE => 605 ps
)
port map (
I => FA_D(5),
O => FA_D_5_0
);
FA_D_5_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y6",
PATHPULSE => 605 ps
)
port map (
I => FA_D_4_pack_1,
O => FA_D(4)
);
N7_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y8",
PATHPULSE => 605 ps
)
port map (
I => N7,
O => N7_0
);
N7_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y8",
PATHPULSE => 605 ps
)
port map (
I => N6,
O => N6_0
);
R0_DFF1_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y10",
PATHPULSE => 605 ps
)
port map (
I => Ain_1_IBUF_376,
O => R0_DFF1_Q_DYMUX_1345
);
R0_DFF1_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y10",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF1_Q_CLKINV_1343
);
R0_DFF2_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X7Y3",
PATHPULSE => 605 ps
)
port map (
I => Ain_2_IBUF_378,
O => R0_DFF2_Q_DYMUX_1354
);
R0_DFF2_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X7Y3",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF2_Q_CLKINV_1352
);
MAC_C2_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y7",
PATHPULSE => 605 ps
)
port map (
I => MAC_C2(1),
O => MAC_C2_1_0
);
MAC_C2_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y7",
PATHPULSE => 605 ps
)
port map (
I => MAC_S1_2_pack_1,
O => MAC_S1(2)
);
MAC_S3_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X7Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_S3(2),
O => MAC_S3_2_0
);
MAC_S3_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X7Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_C2_2_pack_1,
O => MAC_C2(2)
);
MAC_C3_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_C3(2),
O => MAC_C3_2_0
);
MAC_C3_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X6Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_HAM23_A_pack_1,
O => MAC_HAM23_A
);
FA_D_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X5Y4",
PATHPULSE => 605 ps
)
port map (
I => FA_D(2),
O => FA_D_2_0
);
FA_D_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y4",
PATHPULSE => 605 ps
)
port map (
I => S3_2_pack_1,
O => S3(2)
);
R0_DFF3_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X5Y5",
PATHPULSE => 605 ps
)
port map (
I => Ain_3_IBUF_380,
O => R0_DFF3_Q_DYMUX_1363
);
R0_DFF3_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X5Y5",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF3_Q_CLKINV_1361
);
R1_DFF0_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y4",
PATHPULSE => 605 ps
)
port map (
I => Bin_0_INBUF,
O => R1_DFF0_Q_DYMUX_1372
);
R1_DFF0_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y4",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF0_Q_CLKINV_1370
);
R1_DFF1_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y3",
PATHPULSE => 605 ps
)
port map (
I => Bin_1_INBUF,
O => R1_DFF1_Q_DYMUX_1381
);
R1_DFF1_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y3",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF1_Q_CLKINV_1379
);
N2_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y7",
PATHPULSE => 605 ps
)
port map (
I => N2,
O => N2_0
);
R1_DFF3_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X22Y0",
PATHPULSE => 605 ps
)
port map (
I => Bin_3_INBUF,
O => R1_DFF3_Q_DYMUX_1411
);
R1_DFF3_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X22Y0",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF3_Q_CLKINV_1409
);
Aout_0_OBUF : X_OBUF
generic map(
LOC => "PAD205"
)
port map (
I => Aout_0_O,
O => Aout(0)
);
Result_0_OBUF : X_OBUF
generic map(
LOC => "PAD216"
)
port map (
I => Result_0_O,
O => Result(0)
);
Result_1_OBUF : X_OBUF
generic map(
LOC => "PAD220"
)
port map (
I => Result_1_O,
O => Result(1)
);
R1_DFF2_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y3",
PATHPULSE => 605 ps
)
port map (
I => Bin_2_INBUF,
O => R1_DFF2_Q_DYMUX_1402
);
R1_DFF2_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y3",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF2_Q_CLKINV_1400
);
MAC_S1_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_S1(1),
O => MAC_S1_1_0
);
MAC_S1_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y5",
PATHPULSE => 605 ps
)
port map (
I => N18,
O => N18_0
);
Aout_3_OBUF : X_OBUF
generic map(
LOC => "PAD204"
)
port map (
I => Aout_3_O,
O => Aout(3)
);
Result_3_OBUF : X_OBUF
generic map(
LOC => "PAD223"
)
port map (
I => Result_3_O,
O => Result(3)
);
Result_7_OBUF : X_OBUF
generic map(
LOC => "PAD182"
)
port map (
I => Result_7_O,
O => Result(7)
);
R1_DFF0_Q_1 : X_FF
generic map(
LOC => "PAD173",
INIT => '0'
)
port map (
I => Bin_0_IFF_IFFDMUX_570,
CE => VCC,
CLK => Bin_0_IFF_ICLK1INV_572,
SET => GND,
RST => GND,
O => R1_DFF0_Q_1_387
);
Bin_0_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD173",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_0_IFF_ICLK1INV_572
);
Bin_0_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD173",
PATHPULSE => 605 ps
)
port map (
I => Bin_0_INBUF,
O => Bin_0_IFF_IFFDMUX_570
);
Bin_0_IBUF : X_BUF
generic map(
LOC => "PAD173",
PATHPULSE => 605 ps
)
port map (
I => Bin(0),
O => Bin_0_INBUF
);
Bin_1_IBUF : X_BUF
generic map(
LOC => "PAD171",
PATHPULSE => 605 ps
)
port map (
I => Bin(1),
O => Bin_1_INBUF
);
Result_8_OBUF : X_OBUF
generic map(
LOC => "PAD218"
)
port map (
I => Result_8_O,
O => Result(8)
);
Result_6_OBUF : X_OBUF
generic map(
LOC => "PAD219"
)
port map (
I => Result_6_O,
O => Result(6)
);
Result_5_OBUF : X_OBUF
generic map(
LOC => "PAD221"
)
port map (
I => Result_5_O,
O => Result(5)
);
Result_9_OBUF : X_OBUF
generic map(
LOC => "PAD217"
)
port map (
I => Result_9_O,
O => Result(9)
);
Result_4_OBUF : X_OBUF
generic map(
LOC => "PAD215"
)
port map (
I => Result_4_O,
O => Result(4)
);
Bin_2_IBUF : X_BUF
generic map(
LOC => "PAD168",
PATHPULSE => 605 ps
)
port map (
I => Bin(2),
O => Bin_2_INBUF
);
Bin_3_IBUF : X_BUF
generic map(
LOC => "PAD167",
PATHPULSE => 605 ps
)
port map (
I => Bin(3),
O => Bin_3_INBUF
);
Bout_1_OBUF : X_OBUF
generic map(
LOC => "PAD172"
)
port map (
I => Bout_1_O,
O => Bout(1)
);
Bout_0_OBUF : X_OBUF
generic map(
LOC => "PAD174"
)
port map (
I => Bout_0_O,
O => Bout(0)
);
Ain_1_IBUF : X_BUF
generic map(
LOC => "PAD235",
PATHPULSE => 605 ps
)
port map (
I => Ain(1),
O => Ain_1_INBUF
);
Ain_0_IBUF : X_BUF
generic map(
LOC => "PAD206",
PATHPULSE => 605 ps
)
port map (
I => Ain(0),
O => Ain_0_INBUF
);
Bout_2_OBUF : X_OBUF
generic map(
LOC => "PAD166"
)
port map (
I => Bout_2_O,
O => Bout(2)
);
Bout_3_OBUF : X_OBUF
generic map(
LOC => "PAD164"
)
port map (
I => Bout_3_O,
O => Bout(3)
);
CLK_BUFGP_IBUFG : X_BUF
generic map(
LOC => "PAD169",
PATHPULSE => 605 ps
)
port map (
I => CLK,
O => CLK_INBUF
);
R2_DFF1_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y10",
PATHPULSE => 605 ps
)
port map (
I => S6(1),
O => R2_DFF1_Q_DXMUX_757
);
R2_DFF1_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y10",
PATHPULSE => 605 ps
)
port map (
I => S3_0_pack_2,
O => S3(0)
);
R2_DFF1_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y10",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF1_Q_CLKINV_740
);
Ain_3_IBUF : X_BUF
generic map(
LOC => "PAD203",
PATHPULSE => 605 ps
)
port map (
I => Ain(3),
O => Ain_3_INBUF
);
Ain_2_IBUF : X_BUF
generic map(
LOC => "PAD183",
PATHPULSE => 605 ps
)
port map (
I => Ain(2),
O => Ain_2_INBUF
);
R2_DFF9_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y9",
PATHPULSE => 605 ps
)
port map (
I => S6(9),
O => R2_DFF9_Q_DXMUX_787
);
R2_DFF9_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y9",
PATHPULSE => 605 ps
)
port map (
I => FA_FA6_Cout1_O_pack_2,
O => FA_FA6_Cout1_O
);
R2_DFF9_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y9",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF9_Q_CLKINV_771
);
FA_D_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y11",
PATHPULSE => 605 ps
)
port map (
I => FA_D(1),
O => FA_D_1_0
);
FA_D_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y11",
PATHPULSE => 605 ps
)
port map (
I => S3_1_pack_1,
O => S3(1)
);
MAC_S2_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_S2(1),
O => MAC_S2_1_0
);
MAC_S2_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_C1_1_pack_2,
O => MAC_C1(1)
);
R2_DFF7_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X3Y9",
PATHPULSE => 605 ps
)
port map (
I => S6(7),
O => R2_DFF7_Q_DXMUX_871
);
R2_DFF7_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y9",
PATHPULSE => 605 ps
)
port map (
I => FA_FA6_Cout1_SW0_O_pack_2,
O => FA_FA6_Cout1_SW0_O
);
R2_DFF7_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y9",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF7_Q_CLKINV_854
);
R2_DFF8_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X5Y9",
PATHPULSE => 605 ps
)
port map (
I => S6(8),
O => R2_DFF8_Q_DXMUX_817
);
R2_DFF8_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y9",
PATHPULSE => 605 ps
)
port map (
I => FA_FA6_Cout1_SW2_O_pack_2,
O => FA_FA6_Cout1_SW2_O
);
R2_DFF8_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X5Y9",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF8_Q_CLKINV_802
);
CLK_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX0"
)
port map (
I0 => CLK_BUFGP_BUFG_I0_INV,
I1 => GND,
S => CLK_BUFGP_BUFG_S_INVNOT,
O => CLK_BUFGP
);
CLK_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX0",
PATHPULSE => 605 ps
)
port map (
I => '1',
O => CLK_BUFGP_BUFG_S_INVNOT
);
CLK_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX0",
PATHPULSE => 605 ps
)
port map (
I => CLK_INBUF,
O => CLK_BUFGP_BUFG_I0_INV
);
S3_7_XUSED : X_BUF
generic map(
LOC => "SLICE_X7Y7",
PATHPULSE => 605 ps
)
port map (
I => S3(7),
O => S3_7_0
);
S3_7_YUSED : X_BUF
generic map(
LOC => "SLICE_X7Y7",
PATHPULSE => 605 ps
)
port map (
I => MAC_C4_1_pack_1,
O => MAC_C4(1)
);
Aout_2_OUTPUT_OFF_O1INV : X_BUF
generic map(
LOC => "PAD181",
PATHPULSE => 605 ps
)
port map (
I => Ain_2_IBUF_378,
O => Aout_2_OUTPUT_OFF_O1INV_484
);
Aout_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD181",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF2_Q_1_487,
O => Aout_2_O
);
Aout_2_OUTPUT_OTCLK1INV : X_BUF
generic map(
LOC => "PAD181",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Aout_2_OUTPUT_OTCLK1INV_481
);
R0_DFF2_Q_1 : X_FF
generic map(
LOC => "PAD181",
INIT => '0'
)
port map (
I => Aout_2_OUTPUT_OFF_O1INV_484,
CE => VCC,
CLK => Aout_2_OUTPUT_OTCLK1INV_481,
SET => GND,
RST => GND,
O => R0_DFF2_Q_1_487
);
R0_DFF3_Q_1 : X_FF
generic map(
LOC => "PAD204",
INIT => '0'
)
port map (
I => Aout_3_OUTPUT_OFF_O1INV_508,
CE => VCC,
CLK => Aout_3_OUTPUT_OTCLK1INV_505,
SET => GND,
RST => GND,
O => R0_DFF3_Q_1_511
);
Aout_3_OUTPUT_OFF_O1INV : X_BUF
generic map(
LOC => "PAD204",
PATHPULSE => 605 ps
)
port map (
I => Ain_3_IBUF_380,
O => Aout_3_OUTPUT_OFF_O1INV_508
);
Aout_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD204",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF3_Q_1_511,
O => Aout_3_O
);
Aout_3_OUTPUT_OTCLK1INV : X_BUF
generic map(
LOC => "PAD204",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Aout_3_OUTPUT_OTCLK1INV_505
);
R0_DFF1_Q_1 : X_FF
generic map(
LOC => "PAD236",
INIT => '0'
)
port map (
I => Aout_1_OUTPUT_OFF_O1INV_460,
CE => VCC,
CLK => Aout_1_OUTPUT_OTCLK1INV_457,
SET => GND,
RST => GND,
O => R0_DFF1_Q_1_463
);
Aout_1_OUTPUT_OFF_O1INV : X_BUF
generic map(
LOC => "PAD236",
PATHPULSE => 605 ps
)
port map (
I => Ain_1_IBUF_376,
O => Aout_1_OUTPUT_OFF_O1INV_460
);
Aout_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD236",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF1_Q_1_463,
O => Aout_1_O
);
Aout_1_OUTPUT_OTCLK1INV : X_BUF
generic map(
LOC => "PAD236",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Aout_1_OUTPUT_OTCLK1INV_457
);
Ain_0_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD206",
PATHPULSE => 605 ps
)
port map (
I => Ain_0_INBUF,
O => Ain_0_IFF_IFFDMUX_670
);
Ain_0_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD206",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Ain_0_IFF_ICLK1INV_672
);
R0_DFF0_Q_1 : X_FF
generic map(
LOC => "PAD206",
INIT => '0'
)
port map (
I => Ain_0_IFF_IFFDMUX_670,
CE => VCC,
CLK => Ain_0_IFF_ICLK1INV_672,
SET => GND,
RST => GND,
O => R0_DFF0_Q_1_395
);
Bin_1_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD171",
PATHPULSE => 605 ps
)
port map (
I => Bin_1_INBUF,
O => Bin_1_IFF_IFFDMUX_587
);
Bin_1_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD171",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_1_IFF_ICLK1INV_589
);
R1_DFF1_Q_1 : X_FF
generic map(
LOC => "PAD171",
INIT => '0'
)
port map (
I => Bin_1_IFF_IFFDMUX_587,
CE => VCC,
CLK => Bin_1_IFF_ICLK1INV_589,
SET => GND,
RST => GND,
O => R1_DFF1_Q_1_389
);
R1_DFF2_Q_1 : X_FF
generic map(
LOC => "PAD168",
INIT => '0'
)
port map (
I => Bin_2_IFF_IFFDMUX_604,
CE => VCC,
CLK => Bin_2_IFF_ICLK1INV_606,
SET => GND,
RST => GND,
O => R1_DFF2_Q_1_391
);
Bin_2_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD168",
PATHPULSE => 605 ps
)
port map (
I => Bin_2_INBUF,
O => Bin_2_IFF_IFFDMUX_604
);
Bin_2_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD168",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_2_IFF_ICLK1INV_606
);
R1_DFF3_Q_1 : X_FF
generic map(
LOC => "PAD167",
INIT => '0'
)
port map (
I => Bin_3_IFF_IFFDMUX_621,
CE => VCC,
CLK => Bin_3_IFF_ICLK1INV_623,
SET => GND,
RST => GND,
O => R1_DFF3_Q_1_393
);
Bin_3_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD167",
PATHPULSE => 605 ps
)
port map (
I => Bin_3_INBUF,
O => Bin_3_IFF_IFFDMUX_621
);
Bin_3_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD167",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_3_IFF_ICLK1INV_623
);
Ain_3_IFF_IMUX : X_BUF
generic map(
LOC => "PAD203",
PATHPULSE => 605 ps
)
port map (
I => Ain_3_INBUF,
O => Ain_3_IBUF_380
);
R2_DFF9_Q : X_FF
generic map(
LOC => "SLICE_X2Y9",
INIT => '0'
)
port map (
I => R2_DFF9_Q_DXMUX_787,
CE => VCC,
CLK => R2_DFF9_Q_CLKINV_771,
SET => GND,
RST => GND,
O => R2_DFF9_Q_386
);
FA_FA6_Cout1 : X_LUT4
generic map(
INIT => X"FAA0",
LOC => "SLICE_X2Y9"
)
port map (
ADR0 => S3(6),
ADR1 => VCC,
ADR2 => FA_D_5_0,
ADR3 => R2_DFF6_Q_383,
O => FA_FA6_Cout1_O_pack_2
);
FA_FA6_Cout1_SW2 : X_LUT4
generic map(
INIT => X"1117",
LOC => "SLICE_X5Y9"
)
port map (
ADR0 => S3_7_0,
ADR1 => R2_DFF7_Q_384,
ADR2 => R2_DFF6_Q_383,
ADR3 => S3(6),
O => FA_FA6_Cout1_SW2_O_pack_2
);
MAC_HAM11_H1_Cout1 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X4Y6"
)
port map (
ADR0 => R0_DFF2_Q_403,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF0_Q_405,
ADR3 => R1_DFF1_Q_404,
O => MAC_C1_1_pack_2
);
MAC_FAM21_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"963C",
LOC => "SLICE_X4Y6"
)
port map (
ADR0 => R0_DFF1_Q_400,
ADR1 => MAC_C1(1),
ADR2 => MAC_S1(2),
ADR3 => R1_DFF2_Q_399,
O => MAC_S2(1)
);
MAC_S0_0_and00001 : X_LUT4
generic map(
INIT => X"AA00",
LOC => "SLICE_X2Y10"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => R1_DFF0_Q_405,
O => S3_0_pack_2
);
Ain_1_IFF_IMUX : X_BUF
generic map(
LOC => "PAD235",
PATHPULSE => 605 ps
)
port map (
I => Ain_1_INBUF,
O => Ain_1_IBUF_376
);
R2_DFF1_Q : X_FF
generic map(
LOC => "SLICE_X2Y10",
INIT => '0'
)
port map (
I => R2_DFF1_Q_DXMUX_757,
CE => VCC,
CLK => R2_DFF1_Q_CLKINV_740,
SET => GND,
RST => GND,
O => R2_DFF1_Q_408
);
FA_FA9_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"A959",
LOC => "SLICE_X2Y9"
)
port map (
ADR0 => R2_DFF9_Q_386,
ADR1 => N6_0,
ADR2 => FA_FA6_Cout1_O,
ADR3 => N7_0,
O => S6(9)
);
Ain_2_IFF_IMUX : X_BUF
generic map(
LOC => "PAD183",
PATHPULSE => 605 ps
)
port map (
I => Ain_2_INBUF,
O => Ain_2_IBUF_378
);
FA_FA1_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"963C",
LOC => "SLICE_X2Y10"
)
port map (
ADR0 => R2_DFF0_Q_409,
ADR1 => R2_DFF1_Q_408,
ADR2 => S3(1),
ADR3 => S3(0),
O => S6(1)
);
MAC_HAM10_H1_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6CA0",
LOC => "SLICE_X2Y11"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF1_Q_404,
ADR3 => R1_DFF0_Q_405,
O => S3_1_pack_1
);
MAC_FAM30_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6996",
LOC => "SLICE_X3Y6"
)
port map (
ADR0 => MAC_C2_0_0,
ADR1 => N11_0,
ADR2 => MAC_C1(1),
ADR3 => MAC_S1(2),
O => S3_3_pack_1
);
MAC_FAM31_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"963C",
LOC => "SLICE_X5Y6"
)
port map (
ADR0 => R1_DFF3_Q_423,
ADR1 => MAC_S2_2_0,
ADR2 => MAC_C2_1_0,
ADR3 => R0_DFF1_Q_400,
O => MAC_S3_1_pack_1
);
MAC_HAM23_A1 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X6Y4"
)
port map (
ADR0 => VCC,
ADR1 => R0_DFF3_Q_424,
ADR2 => VCC,
ADR3 => R1_DFF2_Q_399,
O => MAC_HAM23_A_pack_1
);
FA_FA1_Cout1 : X_LUT4
generic map(
INIT => X"E8C0",
LOC => "SLICE_X2Y11"
)
port map (
ADR0 => R2_DFF0_Q_409,
ADR1 => R2_DFF1_Q_408,
ADR2 => S3(1),
ADR3 => S3(0),
O => FA_D(1)
);
FA_FA8_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"A965",
LOC => "SLICE_X5Y9"
)
port map (
ADR0 => R2_DFF8_Q_385,
ADR1 => FA_D_5_0,
ADR2 => N15_0,
ADR3 => FA_FA6_Cout1_SW2_O,
O => S6(8)
);
MAC_FA41_Cout1 : X_LUT4
generic map(
INIT => X"E888",
LOC => "SLICE_X7Y7"
)
port map (
ADR0 => MAC_C3(1),
ADR1 => MAC_S3_2_0,
ADR2 => N2_0,
ADR3 => MAC_S3(1),
O => MAC_C4_1_pack_1
);
MAC_FA42_Cout1 : X_LUT4
generic map(
INIT => X"EA80",
LOC => "SLICE_X7Y7"
)
port map (
ADR0 => MAC_C3_2_0,
ADR1 => R0_DFF3_Q_424,
ADR2 => R1_DFF3_Q_423,
ADR3 => MAC_C4(1),
O => S3(7)
);
FA_FA3_Cout1 : X_LUT4
generic map(
INIT => X"FCC0",
LOC => "SLICE_X3Y6"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF3_Q_379,
ADR2 => S3(3),
ADR3 => FA_D_2_0,
O => FA_D(3)
);
MAC_FA42_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9666",
LOC => "SLICE_X5Y7"
)
port map (
ADR0 => MAC_C3_2_0,
ADR1 => MAC_C4(1),
ADR2 => R1_DFF3_Q_423,
ADR3 => R0_DFF3_Q_424,
O => S3_6_pack_1
);
MAC_FAM32_Cout1 : X_LUT4
generic map(
INIT => X"E8A0",
LOC => "SLICE_X6Y4"
)
port map (
ADR0 => MAC_C2(2),
ADR1 => R0_DFF2_Q_403,
ADR2 => MAC_HAM23_A,
ADR3 => R1_DFF3_Q_423,
O => MAC_C3(2)
);
MAC_HA40_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"1E78",
LOC => "SLICE_X5Y6"
)
port map (
ADR0 => MAC_FAM30_A_0,
ADR1 => MAC_C2_0_0,
ADR2 => MAC_S3(1),
ADR3 => MAC_S2_1_0,
O => S3(4)
);
FA_FA7_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"17E8",
LOC => "SLICE_X3Y9"
)
port map (
ADR0 => S3(6),
ADR1 => FA_D_5_0,
ADR2 => R2_DFF6_Q_383,
ADR3 => FA_FA6_Cout1_SW0_O,
O => S6(7)
);
R2_DFF7_Q : X_FF
generic map(
LOC => "SLICE_X3Y9",
INIT => '0'
)
port map (
I => R2_DFF7_Q_DXMUX_871,
CE => VCC,
CLK => R2_DFF7_Q_CLKINV_854,
SET => GND,
RST => GND,
O => R2_DFF7_Q_384
);
FA_FA6_Cout1_SW0 : X_LUT4
generic map(
INIT => X"0FF0",
LOC => "SLICE_X3Y9"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => S3_7_0,
ADR3 => R2_DFF7_Q_384,
O => FA_FA6_Cout1_SW0_O_pack_2
);
R2_DFF8_Q : X_FF
generic map(
LOC => "SLICE_X5Y9",
INIT => '0'
)
port map (
I => R2_DFF8_Q_DXMUX_817,
CE => VCC,
CLK => R2_DFF8_Q_CLKINV_802,
SET => GND,
RST => GND,
O => R2_DFF8_Q_385
);
FA_FA5_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X0Y6"
)
port map (
ADR0 => S3_5_0,
ADR1 => FA_D(4),
ADR2 => VCC,
ADR3 => R2_DFF5_Q_382,
O => S6(5)
);
MAC_FAM20_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9666",
LOC => "SLICE_X5Y4"
)
port map (
ADR0 => MAC_C1(0),
ADR1 => MAC_S1_1_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF2_Q_399,
O => S3_2_pack_1
);
MAC_FAM21_Cout1 : X_LUT4
generic map(
INIT => X"F880",
LOC => "SLICE_X4Y7"
)
port map (
ADR0 => R0_DFF1_Q_400,
ADR1 => R1_DFF2_Q_399,
ADR2 => MAC_S1(2),
ADR3 => MAC_C1(1),
O => MAC_C2(1)
);
MAC_FAM32_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"936C",
LOC => "SLICE_X7Y5"
)
port map (
ADR0 => R1_DFF3_Q_423,
ADR1 => MAC_HAM23_A,
ADR2 => R0_DFF2_Q_403,
ADR3 => MAC_C2(2),
O => MAC_S3(2)
);
FA_FA5_Cout1 : X_LUT4
generic map(
INIT => X"EE88",
LOC => "SLICE_X2Y6"
)
port map (
ADR0 => S3_5_0,
ADR1 => R2_DFF5_Q_382,
ADR2 => VCC,
ADR3 => FA_D(4),
O => FA_D(5)
);
MAC_FAM22_H2_Mxor_Sout_Result1_SW0 : X_LUT4
generic map(
INIT => X"55FF",
LOC => "SLICE_X6Y5"
)
port map (
ADR0 => R1_DFF1_Q_404,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => R0_DFF3_Q_424,
O => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O_pack_1
);
FA_FA6_Cout1_SW1 : X_LUT4
generic map(
INIT => X"173F",
LOC => "SLICE_X5Y7"
)
port map (
ADR0 => R2_DFF6_Q_383,
ADR1 => R2_DFF7_Q_384,
ADR2 => S3_7_0,
ADR3 => S3(6),
O => N15
);
FA_FA2_Cout1 : X_LUT4
generic map(
INIT => X"FCC0",
LOC => "SLICE_X5Y4"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF2_Q_377,
ADR2 => S3(2),
ADR3 => FA_D_1_0,
O => FA_D(2)
);
MAC_HAM12_H1_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6CA0",
LOC => "SLICE_X4Y7"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF2_Q_403,
ADR2 => R0_DFF3_Q_424,
ADR3 => R1_DFF1_Q_404,
O => MAC_S1_2_pack_1
);
MAC_HAM10_H1_Cout1 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X4Y4"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF1_Q_404,
ADR3 => R0_DFF0_Q_411,
O => MAC_C1_0_pack_2
);
MAC_FAM22_Cout1 : X_LUT4
generic map(
INIT => X"C080",
LOC => "SLICE_X7Y5"
)
port map (
ADR0 => R1_DFF2_Q_399,
ADR1 => N18_0,
ADR2 => R1_DFF1_Q_404,
ADR3 => R1_DFF0_Q_405,
O => MAC_C2_2_pack_1
);
MAC_FAM22_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"CB07",
LOC => "SLICE_X6Y5"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF2_Q_403,
ADR2 => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O,
ADR3 => R1_DFF2_Q_399,
O => MAC_S2(2)
);
MAC_FA41_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"3C96",
LOC => "SLICE_X7Y6"
)
port map (
ADR0 => MAC_S3(1),
ADR1 => MAC_S3_2_0,
ADR2 => MAC_C3(1),
ADR3 => N4_0,
O => S3(5)
);
MAC_FAM20_Cout1 : X_LUT4
generic map(
INIT => X"EC80",
LOC => "SLICE_X4Y4"
)
port map (
ADR0 => R1_DFF2_Q_399,
ADR1 => MAC_S1_1_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => MAC_C1(0),
O => MAC_C2(0)
);
MAC_FAM31_Cout1 : X_LUT4
generic map(
INIT => X"E8C0",
LOC => "SLICE_X7Y6"
)
port map (
ADR0 => R1_DFF3_Q_423,
ADR1 => MAC_C2_1_0,
ADR2 => MAC_S2_2_0,
ADR3 => R0_DFF1_Q_400,
O => MAC_C3_1_pack_1
);
FA_FA4_Cout1 : X_LUT4
generic map(
INIT => X"FAA0",
LOC => "SLICE_X2Y6"
)
port map (
ADR0 => R2_DFF4_Q_381,
ADR1 => VCC,
ADR2 => FA_D_3_0,
ADR3 => S3_4_0,
O => FA_D_4_pack_1
);
FA_FA2_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"C33C",
LOC => "SLICE_X5Y8"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF2_Q_377,
ADR2 => S3(2),
ADR3 => FA_D_1_0,
O => S6(2)
);
R2_DFF3_Q : X_FF
generic map(
LOC => "SLICE_X2Y7",
INIT => '0'
)
port map (
I => R2_DFF3_Q_DYMUX_1261,
CE => VCC,
CLK => R2_DFF3_Q_CLKINV_1252,
SET => GND,
RST => GND,
O => R2_DFF3_Q_379
);
R2_DFF6_Q : X_FF
generic map(
LOC => "SLICE_X2Y8",
INIT => '0'
)
port map (
I => R2_DFF6_Q_DYMUX_1195,
CE => VCC,
CLK => R2_DFF6_Q_CLKINV_1186,
SET => GND,
RST => GND,
O => R2_DFF6_Q_383
);
MAC_FAM30_H2_Mxor_Sout_Result1_SW0 : X_LUT4
generic map(
INIT => X"6AC0",
LOC => "SLICE_X6Y6"
)
port map (
ADR0 => R0_DFF1_Q_400,
ADR1 => R1_DFF3_Q_423,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF2_Q_399,
O => N11
);
MAC_FAM30_A1 : X_LUT4
generic map(
INIT => X"8888",
LOC => "SLICE_X4Y8"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => R1_DFF3_Q_423,
ADR2 => VCC,
ADR3 => VCC,
O => MAC_FAM30_A
);
FA_FA8_H2_Cout1_SW1 : X_LUT4
generic map(
INIT => X"555F",
LOC => "SLICE_X3Y8"
)
port map (
ADR0 => R2_DFF8_Q_385,
ADR1 => VCC,
ADR2 => S3_7_0,
ADR3 => R2_DFF7_Q_384,
O => N7
);
R0_DFF0_Q : X_FF
generic map(
LOC => "SLICE_X1Y5",
INIT => '0'
)
port map (
I => R0_DFF0_Q_DYMUX_1312,
CE => VCC,
CLK => R0_DFF0_Q_CLKINV_1310,
SET => GND,
RST => GND,
O => R0_DFF0_Q_411
);
FA_FA8_H2_Cout1_SW0 : X_LUT4
generic map(
INIT => X"5FFF",
LOC => "SLICE_X3Y8"
)
port map (
ADR0 => R2_DFF8_Q_385,
ADR1 => VCC,
ADR2 => S3_7_0,
ADR3 => R2_DFF7_Q_384,
O => N6
);
R2_DFF2_Q : X_FF
generic map(
LOC => "SLICE_X5Y8",
INIT => '0'
)
port map (
I => R2_DFF2_Q_DYMUX_1243,
CE => VCC,
CLK => R2_DFF2_Q_CLKINV_1234,
SET => GND,
RST => GND,
O => R2_DFF2_Q_377
);
R2_DFF5_Q : X_FF
generic map(
LOC => "SLICE_X0Y6",
INIT => '0'
)
port map (
I => R2_DFF5_Q_DYMUX_1177,
CE => VCC,
CLK => R2_DFF5_Q_CLKINV_1168,
SET => GND,
RST => GND,
O => R2_DFF5_Q_382
);
FA_FA4_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X3Y7"
)
port map (
ADR0 => R2_DFF4_Q_381,
ADR1 => FA_D_3_0,
ADR2 => VCC,
ADR3 => S3_4_0,
O => S6(4)
);
R2_DFF4_Q : X_FF
generic map(
LOC => "SLICE_X3Y7",
INIT => '0'
)
port map (
I => R2_DFF4_Q_DYMUX_1279,
CE => VCC,
CLK => R2_DFF4_Q_CLKINV_1270,
SET => GND,
RST => GND,
O => R2_DFF4_Q_381
);
MAC_HA40_Cout1_SW1 : X_LUT4
generic map(
INIT => X"1777",
LOC => "SLICE_X6Y6"
)
port map (
ADR0 => MAC_S2_1_0,
ADR1 => MAC_C2_0_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF3_Q_423,
O => N4
);
FA_FA6_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"C33C",
LOC => "SLICE_X2Y8"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF6_Q_383,
ADR2 => FA_D_5_0,
ADR3 => S3(6),
O => S6(6)
);
FA_HA0_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"66CC",
LOC => "SLICE_X4Y8"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => R2_DFF0_Q_409,
ADR2 => VCC,
ADR3 => R1_DFF0_Q_405,
O => S6(0)
);
R2_DFF0_Q : X_FF
generic map(
LOC => "SLICE_X4Y8",
INIT => '0'
)
port map (
I => R2_DFF0_Q_DYMUX_1216,
CE => VCC,
CLK => R2_DFF0_Q_CLKINV_1207,
SET => GND,
RST => GND,
O => R2_DFF0_Q_409
);
FA_FA3_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9696",
LOC => "SLICE_X2Y7"
)
port map (
ADR0 => FA_D_2_0,
ADR1 => S3(3),
ADR2 => R2_DFF3_Q_379,
ADR3 => VCC,
O => S6(3)
);
R1_DFF0_Q : X_FF
generic map(
LOC => "SLICE_X18Y4",
INIT => '0'
)
port map (
I => R1_DFF0_Q_DYMUX_1372,
CE => VCC,
CLK => R1_DFF0_Q_CLKINV_1370,
SET => GND,
RST => GND,
O => R1_DFF0_Q_405
);
R1_DFF1_Q : X_FF
generic map(
LOC => "SLICE_X14Y3",
INIT => '0'
)
port map (
I => R1_DFF1_Q_DYMUX_1381,
CE => VCC,
CLK => R1_DFF1_Q_CLKINV_1379,
SET => GND,
RST => GND,
O => R1_DFF1_Q_404
);
MAC_FAM22_Cout1_SW0 : X_LUT4
generic map(
INIT => X"F000",
LOC => "SLICE_X4Y5"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => R0_DFF2_Q_403,
ADR3 => R0_DFF3_Q_424,
O => N18
);
R0_DFF3_Q : X_FF
generic map(
LOC => "SLICE_X5Y5",
INIT => '0'
)
port map (
I => R0_DFF3_Q_DYMUX_1363,
CE => VCC,
CLK => R0_DFF3_Q_CLKINV_1361,
SET => GND,
RST => GND,
O => R0_DFF3_Q_424
);
MAC_HA40_Cout1_SW0 : X_LUT4
generic map(
INIT => X"E888",
LOC => "SLICE_X6Y7"
)
port map (
ADR0 => MAC_S2_1_0,
ADR1 => MAC_C2_0_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF3_Q_423,
O => N2
);
R1_DFF2_Q : X_FF
generic map(
LOC => "SLICE_X16Y3",
INIT => '0'
)
port map (
I => R1_DFF2_Q_DYMUX_1402,
CE => VCC,
CLK => R1_DFF2_Q_CLKINV_1400,
SET => GND,
RST => GND,
O => R1_DFF2_Q_399
);
R0_DFF2_Q : X_FF
generic map(
LOC => "SLICE_X7Y3",
INIT => '0'
)
port map (
I => R0_DFF2_Q_DYMUX_1354,
CE => VCC,
CLK => R0_DFF2_Q_CLKINV_1352,
SET => GND,
RST => GND,
O => R0_DFF2_Q_403
);
R1_DFF3_Q : X_FF
generic map(
LOC => "SLICE_X22Y0",
INIT => '0'
)
port map (
I => R1_DFF3_Q_DYMUX_1411,
CE => VCC,
CLK => R1_DFF3_Q_CLKINV_1409,
SET => GND,
RST => GND,
O => R1_DFF3_Q_423
);
MAC_HAM11_H1_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6AC0",
LOC => "SLICE_X4Y5"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF1_Q_404,
ADR3 => R0_DFF2_Q_403,
O => MAC_S1(1)
);
R0_DFF1_Q : X_FF
generic map(
LOC => "SLICE_X0Y10",
INIT => '0'
)
port map (
I => R0_DFF1_Q_DYMUX_1345,
CE => VCC,
CLK => R0_DFF1_Q_CLKINV_1343,
SET => GND,
RST => GND,
O => R0_DFF1_Q_400
);
Result_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD222",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF2_Q_377,
O => Result_2_O
);
Aout_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD205",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF0_Q_1_395,
O => Aout_0_O
);
Result_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD216",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF0_Q_409,
O => Result_0_O
);
Result_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD220",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF1_Q_408,
O => Result_1_O
);
Result_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD223",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF3_Q_379,
O => Result_3_O
);
Result_7_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD182",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF7_Q_384,
O => Result_7_O
);
Result_8_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD218",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF8_Q_385,
O => Result_8_O
);
Result_6_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD219",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF6_Q_383,
O => Result_6_O
);
Result_5_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD221",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF5_Q_382,
O => Result_5_O
);
Result_9_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD217",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF9_Q_386,
O => Result_9_O
);
Result_4_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD215",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF4_Q_381,
O => Result_4_O
);
Bout_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD172",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF1_Q_1_389,
O => Bout_1_O
);
Bout_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD174",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF0_Q_1_387,
O => Bout_0_O
);
Bout_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD166",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF2_Q_1_391,
O => Bout_2_O
);
Bout_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD164",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF3_Q_1_393,
O => Bout_3_O
);
NlwBlock_DPU_matrix_multiplication_VCC : X_ONE
port map (
O => VCC
);
NlwBlock_DPU_matrix_multiplication_GND : X_ZERO
port map (
O => GND
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| mit | 88cc61a582e53d4486b9d436ceb748f3 | 0.485614 | 2.68066 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/temperature.vhd | 3 | 3,083 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity temperature is
PORT( CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);
TEMP_SPI : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC
);
end temperature;
architecture behavioral of temperature is
component DS1722
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
ADDRESS : in std_logic_vector(7 downto 0);
START : in std_logic;
DONE : out std_logic;
TEMP_SPI : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC
);
end component;
signal TEMP_DATA_IN : STD_LOGIC_VECTOR (7 downto 0);
signal TEMP_DATA_OUT : STD_LOGIC_VECTOR (7 downto 0);
signal TEMP_ADDRESS : STD_LOGIC_VECTOR (7 downto 0);
signal TEMP_START : std_logic;
signal TEMP_DONE : std_logic;
type TEMPERATURE_STATES is (TEMP_IDLE, TEMP_SETUP, TEMP_SETUP_COMPLETE,
TEMP_GET_DATA, TEMP_GET_DATA_COMPLETE);
signal TEMP_state : TEMPERATURE_STATES;
begin
tsensor: DS1722
PORT MAP( CLK_I => CLK_I,
RST_I => RST_I,
DATA_IN => TEMP_DATA_IN,
DATA_OUT => TEMP_DATA_OUT,
ADDRESS => TEMP_ADDRESS,
START => TEMP_START,
DONE => TEMP_DONE,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
-- State machine to step though the process of getting data
-- from the Digital Thermometer.
--
process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
TEMP_state <= TEMP_IDLE;
TEMP_START <= '0';
TEMP_ADDRESS <= "00000000";
TEMP_DATA_IN <= "00000000";
else
case TEMP_state is
when TEMP_IDLE =>
TEMP_START <= '0';
TEMP_ADDRESS <= "00000000";
TEMP_DATA_IN <= "00000000";
TEMP_state <= TEMP_SETUP;
when TEMP_SETUP =>
TEMP_ADDRESS <= "10000000";
TEMP_DATA_IN <= "11101000";
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_SETUP_COMPLETE;
TEMP_START <= '0';
else
TEMP_state <= TEMP_SETUP;
TEMP_START <= '1';
end if;
when TEMP_SETUP_COMPLETE =>
TEMP_START <= '0';
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_SETUP_COMPLETE;
else
TEMP_state <= TEMP_GET_DATA;
end if;
when TEMP_GET_DATA =>
TEMP_ADDRESS <= "00000010";
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_GET_DATA_COMPLETE;
DATA_OUT <= TEMP_DATA_OUT;
TEMP_START <= '0';
else
TEMP_state <= TEMP_GET_DATA;
TEMP_START <= '1';
end if;
when TEMP_GET_DATA_COMPLETE =>
TEMP_START <= '0';
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_GET_DATA_COMPLETE;
else
TEMP_state <= TEMP_GET_DATA;
end if;
end case;
end if;
end if;
end process;
end behavioral;
| mit | d1a8ba5193c1cbe09c8f627a3934822c | 0.577035 | 2.815525 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Advanced/harware_interface.vhd | 1 | 6,620 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0);
aclMISO : IN std_logic;
aclMOSI : OUT std_logic;
aclSCLK : OUT std_logic;
aclCS : OUT std_logic;
RGB1_Red : OUT std_logic;
RGB1_Green : OUT std_logic;
RGB1_Blue : OUT std_logic
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component spi_accel port (
clk100MHz : in STD_LOGIC;
masterReset : in STD_LOGIC;
CS : out STD_LOGIC;
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
READY : out STD_LOGIC;
X_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Y_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Z_VAL : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component led_bright port(
clk : IN std_logic;
masterReset : IN std_logic;
ready : IN std_logic;
accel_val : IN std_logic_vector(7 downto 0);
pwm_out : OUT std_logic
);
end component;
component bcd_display port (
clk : in std_logic;
masterReset : in std_logic;
byte_in : in STD_LOGIC_VECTOR(7 downto 0);
bcd_val : out STD_LOGIC_VECTOR(11 downto 0)
);
end component;
--Central Button
signal masterReset : std_logic;
signal buttonLeft : std_logic;
signal buttonRight : std_logic;
signal buttonUp : std_logic;
signal buttonDown : std_logic;
signal displayLower : std_logic_vector(15 downto 0);
signal displayUpper : std_logic_vector(15 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
-- Component Signals
signal CS : std_logic := '1';
signal SCLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal MISO : std_logic := '0';
signal READY : std_logic := '0';
signal X_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal Y_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal Z_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal X_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal Y_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal Z_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal X_PWM : std_logic := '0';
signal Y_PWM : std_logic := '0';
signal Z_PWM : std_logic := '0';
begin
--Central Button
masterReset <= pushButtons(4);
buttonLeft <= pushButtons(3);
buttonRight <= pushButtons(0);
buttonUp <= pushButtons(2);
buttonDown <= pushButtons(1);
LEDs (15 downto 8) <= clockScalers(26 downto 19);
--logic_analyzer (7 downto 0) <= clockScalers(26 downto 19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayLower (3 downto 0),
digit2_p => displayLower (7 downto 4),
digit3_p => displayLower (11 downto 8),
digit4_p => displayLower (15 downto 12),
digit5_p => displayUpper (3 downto 0),
digit6_p => displayUpper (7 downto 4),
digit7_p => displayUpper (11 downto 8),
digit8_p => displayUpper (15 downto 12)
);
m1 : spi_accel port map (clk100Mhz, masterReset, CS, SCLK, MOSI, MISO, READY, X_VAL, Y_VAL, Z_VAL);
logic_analyzer(0) <= clk100Mhz;
logic_analyzer(1) <= masterReset;
logic_analyzer(2) <= CS;
logic_analyzer(3) <= SCLK;
logic_analyzer(4) <= MOSI;
logic_analyzer(5) <= MISO;
logic_analyzer(6) <= READY;
--logic_analyzer(7) <= '0';
--Accel Linking
aclCS <= CS;
aclSCLK <= SCLk;
aclMOSI <= MOSI;
MISO <= aclMISO;
-- displayLower(15 downto 8) <= X_VAL;
-- displayLower(7 downto 0) <= Y_VAL;
-- displayUpper(7 downto 0) <= Z_VAL;
D1 : bcd_display port map (Ready, masterReset, X_VAL, X_VAL_D);
D2 : bcd_display port map (Ready, masterReset, Y_VAL, Y_VAL_D);
D3 : bcd_display port map (Ready, masterReset, Z_VAL, Z_VAL_D);
--PWM Linking
P1 : led_bright port map(clk100Mhz, masterReset, ready, X_VAL, X_PWM);
P2 : led_bright port map(clk100Mhz, masterReset, ready, Y_VAL, Y_PWM);
P3 : led_bright port map(clk100Mhz, masterReset, ready, Z_VAL, Z_PWM);
--LEDBAR and PWM Linking
process ( slideSwitches(15 downto 13) ) begin
if ( (slideSwitches(15) = '0') and (slideSwitches(14) = '0') and (slideSwitches(13) = '1')) then
LEDs(7 downto 0) <= Y_VAL;
displayLower(11 downto 0) <= Y_VAL_D;
logic_analyzer(7) <= Y_PWM;
RGB1_Red <= '0';
RGB1_Green <= Y_PWM;
RGB1_Blue <= '0';
elsif ( (slideSwitches(15) = '0') and (slideSwitches(14) = '1') and (slideSwitches(13) = '0')) then
LEDs(7 downto 0) <= X_VAL;
displayLower(11 downto 0) <= X_VAL_D;
logic_analyzer(7) <= X_PWM;
RGB1_Red <= X_PWM;
RGB1_Green <= '0';
RGB1_Blue <= '0';
elsif ( (slideSwitches(15) = '1') and (slideSwitches(14) = '0') and (slideSwitches(13) = '0')) then
LEDs(7 downto 0) <= Z_VAL;
displayLower(11 downto 0) <= Z_VAL_D;
logic_analyzer(7) <= Z_PWM;
RGB1_Red <= '0';
RGB1_Green <= '0';
RGB1_Blue <= Z_PWM;
elsif ( (slideSwitches(15) = '1') and (slideSwitches(14) = '1') and (slideSwitches(13) = '1')) then
LEDs(7 downto 0) <= "10101010";
RGB1_Red <= X_PWM;
RGB1_Green <= Y_PWM;
RGB1_Blue <= Z_PWM;
else
LEDs(7 downto 0) <= (others => '0');
RGB1_Red <= '0';
RGB1_Green <= '0';
RGB1_Blue <= '0';
end if;
end process;
end Behavioral; | apache-2.0 | 15e9b0791352f49abe0692609ce3d845 | 0.617221 | 2.762938 | false | false | false | false |
scarter93/RSA-Encryption | test_module_tb.vhd | 1 | 1,278 | library ieee;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.math_real.all;
library lpm;
use lpm.lpm_components.all;
entity test_module_tb is
end entity;
architecture test of test_module_tb is
CONSTANT WIDTH_IN : integer := 8;
CONSTANT clk_period : time := 1 ns;
signal N_in : integer;
signal Exp_in : real;
signal M_in : unsigned(WIDTH_IN-1 downto 0);
signal clk_in : std_logic;
signal reset_in : std_logic;
signal C_out : unsigned(WIDTH_IN-1 downto 0);
component test_module is
Generic( WIDTH_IN : integer := 8
);
Port( N : in integer; --Number
Exp : in real; --Exponent
M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
--latch_in: in std_logic;
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0)
);
end component;
begin
dut : test_module PORT MAP(N=>N_in, Exp=>Exp_in, M => M_in, clk => clk_in, reset => reset_in, C => C_out);
clk_process : Process
Begin
clk_in <= '0';
wait for clk_period/2;
clk_in <= '1';
wait for clk_period/2;
end process;
stim_process: process
Begin
N_in <= integer(9);
Exp_in <= real(7);
M_in <= "10001111";
reset_in <= '0';
wait for 9 * clk_period;
wait;
end process;
end architecture;
| mit | 6d66921066637ca3f7416ba0b22271c3 | 0.661972 | 2.651452 | false | true | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_next.vhd | 1 | 1,295 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_next is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : positive := 1;
check_overlapping : ovl_chk_overlap := OVL_CHK_OVERLAP_OFF;
check_missing_start : ovl_ctrl := OVL_OFF;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
start_event : in std_logic;
test_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_next;
| mit | 45f52ae90839a9863d3c37161fde9dd1 | 0.567568 | 3.270202 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/BaudGen.vhd | 1 | 1,425 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use STD.TEXTIO.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BaudGen is
Generic(bg_clock_freq : integer; bg_baud_rate : integer);
Port( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : out std_logic
);
end BaudGen;
architecture Behavioral of BaudGen is
-- divide bg_clock_freq and bg_baud_rate
-- by their common divisor...
--
function gcd(M, N: integer) return integer is
begin
if ((M mod N) = 0) then return N;
else return gcd(N, M mod N);
end if;
end;
constant common_div : integer := gcd(bg_clock_freq, 16 * bg_baud_rate);
constant clock_freq : integer := bg_clock_freq / common_div;
constant baud_freq : integer := 16 * bg_baud_rate / common_div;
constant limit : integer := clock_freq - baud_freq;
signal COUNTER : integer range 0 to clock_freq - 1;
begin
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle
if (CLR = '1') then
COUNTER <= 0;
elsif (COUNTER >= limit) then
CE_16 <= '1';
COUNTER <= COUNTER - limit;
else
COUNTER <= COUNTER + baud_freq;
end if;
end if;
end process;
end Behavioral;
| mit | 1536aa39bcb31a4f023c6931cb97128f | 0.65193 | 3.025478 | false | false | false | false |
jaruiz/light8080 | src/vhdl/rtl/light8080.vhdl | 1 | 35,964 | --##############################################################################
-- light8080 : Intel 8080 binary compatible core
--##############################################################################
-- v1.4 (01 dec 2016) Moved to GitHub, uC extracted to separate package.
-- v1.3 (12 feb 2012) Fix: General solution to AND, OR, XOR clearing CY,ACY.
-- v1.2 (08 jul 2010) Fix: XOR operations were not clearing CY,ACY.
-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
--
-- This file and all the light8080 project files are freeware (See COPYING.TXT)
--##############################################################################
-- (See timing diagrams at bottom of file. More comprehensive explainations can
-- be found in the design notes)
--##############################################################################
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.light8080_ucode_pkg.all;
--##############################################################################
-- vma : enable a memory or io r/w access.
-- io : access in progress is io (and not memory)
-- rd : read memory or io
-- wr : write memory or io
-- data_out : data output
-- addr_out : memory and io address
-- data_in : data input
-- halt : halt status (1 when in halt state)
-- inte : interrupt status (1 when enabled)
-- intr : interrupt request
-- inta : interrupt acknowledge
-- reset : synchronous reset
-- clk : clock
--
-- (see timing diagrams at bottom of file)
--##############################################################################
entity light8080 is
generic (
-- uCode ROM implementation: BRAM or LUT {"block"|"distributed"}.
UCODE_ROM_STYLE : string := "distributed"
);
port (
addr_out : out std_logic_vector(15 downto 0);
inta : out std_logic;
inte : out std_logic;
halt : out std_logic;
intr : in std_logic;
vma : out std_logic;
io : out std_logic;
rd : out std_logic;
wr : out std_logic;
fetch : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
clk : in std_logic;
reset : in std_logic
);
end light8080;
--##############################################################################
-- All memory and io accesses are synchronous (rising clock edge). Signal vma
-- works as the master memory and io synchronous enable. More specifically:
--
-- * All memory/io control signals (io,rd,wr) are valid only when vma is
-- high. They never activate when vma is inactive.
-- * Signals data_out and address are only valid when vma='1'. The high
-- address byte is 0x00 for all io accesses.
-- * Signal data_in should be valid by the end of the cycle after vma='1',
-- data is clocked in by the rising clock edge.
--
-- All signals are assumed to be synchronous to the master clock. Prevention of
-- metastability, if necessary, is up to you.
--
-- Signal reset needs to be active for just 1 clock cycle (it is sampled on a
-- positive clock edge and is subject to setup and hold times).
-- Once reset is deasserted, the first fetch at address 0x0000 will happen 4
-- cycles later.
--
-- Signal intr is sampled on all positive clock edges. If asserted when inte is
-- high, interrupts will be disabled, inta will be asserted high and a fetch
-- cycle will occur immediately after the current instruction ends execution,
-- except if intr was asserted at the last cycle of an instruction. In that case
-- it will be honored after the next instruction ends.
-- The fetched instruction will be executed normally, except that PC will not
-- be valid in any subsequent fetch cycles of the same instruction,
-- and will not be incremented (In practice, the same as the original 8080).
-- inta will remain high for the duration of the fetched instruction, including
-- fetch and execution time (in the original 8080 it was high only for the
-- opcode fetch cycle).
-- PC will not be autoincremented while inta is high, but it can be explicitly
-- modified (e.g. RST, CALL, etc.). Again, the same as the original.
-- Interrupts will be disabled upon assertion of inta, and remain disabled
-- until explicitly enabled by the program (as in the original).
-- If intr is asserted when inte is low, the interrupt will not be attended but
-- it will be registered in an int_pending flag, so it will be honored when
-- interrupts are enabled.
--
--
-- The above means that any instruction can be supplied in an inta cycle,
-- either single byte or multibyte. See the design notes.
--##############################################################################
architecture microcoded of light8080 is
-- addr_low: low byte of address
signal addr_low : std_logic_vector(7 downto 0);
-- IR: instruction register. some bits left unused.
signal IR : std_logic_vector(7 downto 0);
-- s_field: IR field, sss source reg code
signal s_field : std_logic_vector(2 downto 0);
-- d_field: IR field, ddd destination reg code
signal d_field : std_logic_vector(2 downto 0);
-- p_field: IR field, pp 16-bit reg pair code
signal p_field : std_logic_vector(1 downto 0);
-- rbh: 1 when p_field=11, used in reg bank addressing for 'special' regs
signal rbh : std_logic; -- 1 when P=11 (special case)
-- alu_op: uinst field, ALU operation code
signal alu_op : std_logic_vector(3 downto 0);
-- DI: data input to ALU block from data_in, unregistered
signal DI : std_logic_vector(7 downto 0);
-- uc_addr: microcode (ucode) address
signal uc_addr : unsigned(7 downto 0);
-- next_uc_addr: computed next microcode address (uaddr++/jump/ret/fetch)
signal next_uc_addr : unsigned(8 downto 0);
-- uc_jmp_addr: uinst field, absolute ucode jump address
signal uc_jmp_addr : std_logic_vector(7 downto 0);
-- uc_ret_address: ucode return address saved in previous jump
signal uc_ret_addr : std_logic_vector(7 downto 0);
-- addr_plus_1: uaddr + 1
signal addr_plus_1 : std_logic_vector(7 downto 0);
-- do_reset: reset, delayed 1 cycle -- used to reset the microcode sequencer
signal do_reset : std_logic;
-- uc_flags1: uinst field, encoded flag of group 1 (see ucode file)
signal uc_flags1 : std_logic_vector(2 downto 0);
-- uc_flags2: uinst field, encoded flag of group 2 (see ucode file)
signal uc_flags2 : std_logic_vector(2 downto 0);
-- uc_addr_sel: selection of next uc_addr, composition of 4 flags
signal uc_addr_sel : std_logic_vector(3 downto 0);
-- NOTE: see microcode file for information on flags
signal uc_jsr : std_logic; -- uinst field, decoded 'jsr' flag
signal uc_tjsr : std_logic; -- uinst field, decoded 'tjsr' flag
signal uc_decode : std_logic; -- uinst field, decoded 'decode' flag
signal uc_end : std_logic; -- uinst field, decoded 'end' flag
signal condition_reg :std_logic; -- registered tjst condition
-- condition: tjsr condition (computed ccc condition from '80 instructions)
signal condition : std_logic;
-- condition_sel: IR field, ccc condition code
signal condition_sel :std_logic_vector(2 downto 0);
signal uc_do_jmp : std_logic; -- uinst jump (jsr/tjsr) flag, pipelined
signal uc_do_ret : std_logic; -- ret flag, pipelined
signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag
signal uc_halt : std_logic; -- halt command
signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal
signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag
signal uc_di : std_logic; -- uinst field, decoded 'di' flag
signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal
signal int_pending : std_logic; -- intr requested, inta not active yet
signal inta_reg : std_logic; -- inta status reg, output as 'inta'
signal clr_t1 : std_logic; -- uinst field, explicitly erase T1
signal do_clr_t1 : std_logic; -- clr_t1 pipelined
signal clr_t2 : std_logic; -- uinst field, explicitly erase T2
signal do_clr_t2 : std_logic; -- clr_t2 pipelined
signal ucode : std_logic_vector(31 downto 0); -- microcode word
signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode
-- used to delay interrup enable for one entire instruction after EI
signal delayed_ei : std_logic;
-- microcode ROM : see design notes and microcode source file
signal rom : t_rom := microcode;
-- Xilinx attribute for BRAM-vs-LUT implementation choice.
attribute rom_style : string;
attribute rom_style of rom : signal is UCODE_ROM_STYLE;
signal load_al : std_logic; -- uinst field, load AL reg from rbank
signal load_addr : std_logic; -- uinst field, enable external addr reg load
signal load_t1 : std_logic; -- uinst field, load reg T1
signal load_t2 : std_logic; -- uinst field, load reg T2
signal mux_in : std_logic; -- uinst field, T1/T2 input data selection
signal load_do : std_logic; -- uinst field, pipelined, load DO reg
-- rb_addr_sel: uinst field, rbank address selection: (sss,ddd,pp,ra_field)
signal rb_addr_sel : std_logic_vector(1 downto 0);
-- ra_field: uinst field, explicit reg bank address
signal ra_field : std_logic_vector(3 downto 0);
-- rb_wr_index: uinst field, explicit reg bank wr address
--signal rb_wr_index : std_logic_vector(3 downto 0);
signal rbank_data : std_logic_vector(7 downto 0); -- rbank output
signal alu_output : std_logic_vector(7 downto 0); -- ALU output
-- data_output: datapath output: ALU output vs. F reg
signal data_output : std_logic_vector(7 downto 0);
signal T1 : std_logic_vector(7 downto 0); -- T1 reg (ALU operand)
signal T2 : std_logic_vector(7 downto 0); -- T2 reg (ALU operand)
-- alu_input: data loaded into T1, T2: rbank data vs. DI
signal alu_input : std_logic_vector(7 downto 0);
signal we_rb : std_logic; -- uinst field, commands a write to the rbank
signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA)
signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr
signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr
signal DO : std_logic_vector(7 downto 0); -- data output reg
-- Register bank as an array of 16 bytes.
-- This will be implemented as asynchronous LUT RAM in those devices where this
-- feature is available (Xilinx) and as multiplexed registers where it isn't
-- (Altera).
type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0);
-- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP]
signal rbank : t_reg_bank;
signal flag_reg : std_logic_vector(7 downto 0); -- F register
-- flag_pattern: uinst field, F update pattern: which flags are updated
signal flag_pattern : std_logic_vector(1 downto 0);
signal flag_s : std_logic; -- new computed S flag
signal flag_z : std_logic; -- new computed Z flag
signal flag_p : std_logic; -- new computed P flag
signal flag_cy : std_logic; -- new computed C flag
signal flag_cy_1 : std_logic; -- C flag computed from arith/logic operation
signal flag_cy_2 : std_logic; -- C flag computed from CPC circuit
signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.)
signal do_cy_op_d : std_logic; -- do_cy_op, pipelined
signal do_cpc : std_logic; -- ALU operation is CPC
signal do_cpc_d : std_logic; -- do_cpc, pipelined
signal do_daa : std_logic; -- ALU operation is DAA
signal clear_cy : std_logic; -- Instruction unconditionally clears CY
signal clear_ac : std_logic; -- Instruction unconditionally clears AC
signal set_ac : std_logic; -- Instruction unconditionally sets AC
signal flag_ac : std_logic; -- New computed half carry (AC) flag
signal flag_ac_daa : std_logic; -- AC flag computed in the special case of DAA
signal flag_ac_and : std_logic; -- AC flag computed in the special case of AN*
-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
signal flag_aux_cy : std_logic;
signal load_psw : std_logic; -- load F register
-- aux carry computation and control signals
signal use_aux : std_logic; -- decoded from flags in 1st phase
signal use_aux_cy : std_logic; -- 2nd phase signal
signal reg_aux_cy : std_logic;
signal aux_cy_in : std_logic;
signal set_aux_cy : std_logic;
signal set_aux : std_logic;
-- ALU control signals -- together they select ALU operation
signal alu_fn : std_logic_vector(1 downto 0);
signal use_logic : std_logic; -- logic/arith mux control
signal mux_fn : std_logic_vector(1 downto 0);
signal use_psw : std_logic; -- ALU/F mux control
-- ALU arithmetic operands and result
signal arith_op1 : signed(8 downto 0);
signal arith_op2 : signed(8 downto 0);
signal arith_op2_sgn: signed(8 downto 0);
signal arith_res : signed(8 downto 0);
signal arith_res8 : signed(7 downto 0);
-- ALU DAA intermediate signals (DAA has fully dedicated logic)
signal daa_res9 : signed(8 downto 0);
signal daa_test1 : std_logic;
signal daa_test1a : std_logic;
signal daa_test2 : std_logic;
signal daa_test2a : std_logic;
signal arith_daa_res :std_logic_vector(7 downto 0);
signal cy_daa : std_logic;
signal acc_low_gt9 : std_logic;
signal acc_high_gt9 : std_logic;
signal acc_high_ge9 : std_logic;
signal daa_adjust : std_logic_vector(8 downto 0);
-- ALU CY flag intermediate signals
signal cy_in_sgn : std_logic;
signal cy_in : std_logic;
signal cy_in_gated : std_logic;
signal cy_adder : std_logic;
signal cy_arith : std_logic;
signal cy_shifter : std_logic;
-- ALU intermediate results
signal logic_res : std_logic_vector(7 downto 0);
signal shift_res : std_logic_vector(7 downto 0);
signal alu_mux1 : std_logic_vector(7 downto 0);
begin
DI <= data_in;
process(clk) -- IR register, load when uc_decode flag activates
begin
if clk'event and clk='1' then
if uc_decode = '1' then
IR <= DI;
end if;
end if;
end process;
s_field <= IR(2 downto 0); -- IR field extraction : sss reg code
d_field <= IR(5 downto 3); -- ddd reg code
p_field <= IR(5 downto 4); -- pp 16-bit reg pair code
--##############################################################################
-- Microcode sequencer
process(clk) -- do_reset is reset delayed 1 cycle
begin
if clk'event and clk='1' then
do_reset <= reset;
end if;
end process;
uc_flags1 <= ucode(31 downto 29);
uc_flags2 <= ucode(28 downto 26);
-- microcode address control flags are gated by do_reset (reset has priority)
uc_do_ret <= '1' when uc_flags2 = "011" and do_reset = '0' else '0';
uc_jsr <= '1' when uc_flags2 = "010" and do_reset = '0' else '0';
uc_tjsr <= '1' when uc_flags2 = "100" and do_reset = '0' else '0';
uc_decode <= '1' when uc_flags1 = "001" and do_reset = '0' else '0';
uc_end <= '1' when (uc_flags2 = "001" or (uc_tjsr='1' and condition_reg='0'))
and do_reset = '0' else '0';
-- other microinstruction flags are decoded
uc_halt_flag <= '1' when uc_flags1 = "111" else '0';
uc_halt <= '1' when uc_halt_flag='1' and inta_reg='0' else '0';
uc_ei <= '1' when uc_flags1 = "011" else '0';
uc_di <= '1' when uc_flags1 = "010" or inta_reg='1' else '0';
-- clr_t1/2 clears T1/T2 when explicitly commanded; T2 and T1 clear implicitly
-- at the end of each instruction (by uc_decode)
clr_t2 <= '1' when uc_flags2 = "001" else '0';
clr_t1 <= '1' when uc_flags1 = "110" else '0';
use_aux <= '1' when uc_flags1 = "101" else '0';
set_aux <= '1' when uc_flags2 = "111" else '0';
load_al <= ucode(24);
load_addr <= ucode(25);
do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op
do_cpc_d <= ucode(0); -- decode CPC ALU op; valid only when do_cy_op_d='1'
-- uinst jump command, either unconditional or on a given condition
uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg);
vma <= load_addr; -- addr is valid, either for memmory or io
-- assume the only uinst that does memory access in the range 0..f is 'fetch'
fetch <= '1' when uc_addr(7 downto 4)=X"0" and load_addr='1' else '0';
-- external bus interface control signals
io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory)
rd <= '1' when uc_flags2="101" else '0'; -- RD access
wr <= '1' when uc_flags2="110" else '0'; -- WR access
uc_jmp_addr <= ucode(11 downto 10) & ucode(5 downto 0);
uc_addr_sel <= uc_do_ret & uc_do_jmp & uc_decode & uc_end;
addr_plus_1 <= std_logic_vector(uc_addr + 1);
-- TODO simplify this!!
-- NOTE: when end='1' we jump either to the FETCH ucode ot to the HALT ucode
-- depending on the value of the halt signal.
-- We use the unregistered uc_halt instead of halt_reg because otherwise #end
-- should be on the cycle following #halt, wasting a cycle.
-- This means that the flag #halt has to be used with #end or will be ignored.
with uc_addr_sel select next_uc_addr <=
unsigned('0'&uc_ret_addr) when "1000", -- ret
unsigned('0'&uc_jmp_addr) when "0100", -- jsr/tjsr
unsigned('0'&addr_plus_1) when "0000", -- uaddr++
unsigned'("000000"&uc_halt&"11") when "0001", -- end: go to fetch/halt
unsigned('1'&DI) when others; -- decode fetched address
-- Note how we used DI (containing instruction opcode) as a microcode address
-- read microcode rom
process (clk)
begin
if clk'event and clk='1' then
ucode <= rom(to_integer(next_uc_addr));
end if;
end process;
-- microcode address register
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' then
uc_addr <= X"00";
else
uc_addr <= next_uc_addr(7 downto 0);
end if;
end if;
end process;
-- ucode address 1-level 'return stack'
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' then
uc_ret_addr <= X"00";
elsif uc_do_jmp='1' then
uc_ret_addr <= addr_plus_1;
end if;
end if;
end process;
alu_op <= ucode(3 downto 0);
-- pipeline uinst field2 for 1-cycle delayed execution.
-- note the same rbank addr field is used in cycles 1 and 2; this enforces
-- some constraints on uinst programming but simplifies the system.
process(clk)
begin
if clk'event and clk='1' then
ucode_field2 <= do_cy_op_d & do_cpc_d & clr_t2 & clr_t1 &
--set_aux & use_aux & rb_wr_index &
set_aux & use_aux & rbank_rd_addr &
ucode(14 downto 4) & alu_op;
end if;
end process;
--#### HALT logic
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' or int_pending = '1' then --inta_reg
halt_reg <= '0';
else
if uc_halt = '1' then
halt_reg <= '1';
end if;
end if;
end if;
end process;
halt <= halt_reg;
--#### INTE logic -- inte_reg = '1' means interrupts ENABLED
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
inte_reg <= '0';
delayed_ei <= '0';
else
if (uc_di='1' or uc_ei='1') and uc_end='1' then
--inte_reg <= uc_ei;
delayed_ei <= uc_ei; -- FIXME DI must not be delayed
end if;
if uc_end = '1' then -- at the last cycle of every instruction...
if uc_di='1' then -- ...disable interrupts if the instruction is DI...
inte_reg <= '0';
else
-- ...of enable interrupts after the instruction following EI
inte_reg <= delayed_ei;
end if;
end if;
end if;
end if;
end process;
inte <= inte_reg;
-- interrupts are ignored when inte='0' but they are registered and will be
-- honored when interrupts are enabled
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
int_pending <= '0';
else
-- intr will raise int_pending only if inta has not been asserted.
-- Otherwise, if intr overlapped inta, we'd enter a microcode endless
-- loop, executing the interrupt vector again and again.
if intr='1' and inte_reg='1' and int_pending='0' and inta_reg='0' then
int_pending <= '1';
else
-- int_pending is cleared when we're about to service the interrupt,
-- that is when interrupts are enabled and the current instruction ends.
if inte_reg = '1' and uc_end='1' then
int_pending <= '0';
end if;
end if;
end if;
end if;
end process;
--#### INTA logic
-- INTA goes high from END to END, that is for the entire time the instruction
-- takes to fetch and execute; in the original 8080 it was asserted only for
-- the M1 cycle.
-- All instructions can be used in an inta cycle, including XTHL which was
-- forbidden in the original 8080.
-- It's up to you figuring out which cycle is which in multibyte instructions.
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
inta_reg <= '0';
else
if int_pending = '1' and uc_end='1' then
-- enter INTA state
inta_reg <= '1';
else
-- exit INTA state
-- NOTE: don't reset inta when exiting halt state (uc_halt_flag='1').
-- If we omit this condition, when intr happens on halt state, inta
-- will only last for 1 cycle, because in halt state uc_end is
-- always asserted.
if uc_end = '1' and uc_halt_flag='0' then
inta_reg <= '0';
end if;
end if;
end if;
end if;
end process;
inta <= inta_reg;
--##############################################################################
-- Datapath
-- extract pipelined microcode fields
ra_field <= ucode(18 downto 15);
--rb_wr_index <= ucode(13 downto 10);
load_t1 <= ucode(23);
load_t2 <= ucode(22);
mux_in <= ucode(21);
rb_addr_sel <= ucode(20 downto 19);
load_do <= ucode_field2(7);
set_aux_cy <= ucode_field2(20);
do_clr_t1 <= ucode_field2(21);
do_clr_t2 <= ucode_field2(22);
-- T1 register
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' or uc_decode = '1' or do_clr_t1='1' then
T1 <= X"00";
else
if load_t1 = '1' then
T1 <= alu_input;
end if;
end if;
end if;
end process;
-- T2 register
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' or uc_decode = '1' or do_clr_t2='1' then
T2 <= X"00";
else
if load_t2 = '1' then
T2 <= alu_input;
end if;
end if;
end if;
end process;
-- T1/T2 input data mux
alu_input <= rbank_data when mux_in = '1' else DI;
-- register bank address mux logic
rbh <= '1' when p_field = "11" else '0';
with rb_addr_sel select
rbank_rd_addr <= ra_field when "00",
"0"&s_field when "01",
"0"&d_field when "10",
rbh&p_field&ra_field(0) when others;
-- RBank writes are inhibited in INTA state, but only for PC increments.
inhibit_pc_increment <= '1' when inta_reg='1' and use_aux_cy='1'
and rbank_wr_addr(3 downto 1) = "100"
else '0';
we_rb <= ucode_field2(6) and not inhibit_pc_increment;
-- Register bank logic
-- NOTE: read is asynchronous, while write is synchronous; but note also
-- that write phase for a given uinst happens the cycle after the read phase.
-- This way we give the ALU time to do its job.
rbank_wr_addr <= ucode_field2(18 downto 15);
process(clk)
begin
if clk'event and clk='1' then
if we_rb = '1' then
rbank( to_integer(unsigned(rbank_wr_addr))) <= alu_output;
end if;
end if;
end process;
rbank_data <= rbank( to_integer(unsigned(rbank_rd_addr)));
-- should we read F register or ALU output?
use_psw <= '1' when ucode_field2(5 downto 4)="11" else '0';
data_output <= flag_reg when use_psw = '1' else alu_output;
process (clk)
begin
if clk'event and clk='1' then
if load_do = '1' then
DO <= data_output;
end if;
end if;
end process;
--##############################################################################
-- ALU
alu_fn <= ucode_field2(1 downto 0);
use_logic <= ucode_field2(2);
mux_fn <= ucode_field2(4 downto 3);
--#### make sure this is "00" in the microcode when no F updates should happen!
flag_pattern <= ucode_field2(9 downto 8);
use_aux_cy <= ucode_field2(19);
do_cpc <= ucode_field2(23);
do_cy_op <= ucode_field2(24);
do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';
-- ucode_field2(14) will be set for those instructions that modify CY and AC
-- without following the standard rules -- AND, OR and XOR instructions.
-- Some instructions will unconditionally clear CY (AND, OR, XOR)
clear_cy <= ucode_field2(14);
-- Some instructions will unconditionally clear AC (OR, XOR)...
clear_ac <= '1' when ucode_field2(14) = '1' and
ucode_field2(5 downto 0) /= "000100"
else '0';
-- ...and some others unconditionally SET AC (AND)
set_ac <= '1' when ucode_field2(14) = '1' and
ucode_field2(5 downto 0) = "000100"
else '0';
aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';
-- carry input selection: normal or aux (for 16 bit increments)?
cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;
-- carry is not used (0) in add/sub operations
cy_in_gated <= cy_in and alu_fn(0);
--##### Adder/substractor
-- zero extend adder operands to 9 bits to ease CY output synthesis
-- use zero extension because we're only interested in cy from 7 to 8
arith_op1 <= signed('0' & T2);
arith_op2 <= signed('0' & T1);
-- The adder/substractor is done in 2 stages to help XSL synth it properly
-- Other codings result in 1 adder + a substractor + 1 mux
-- do 2nd op 2's complement if substracting...
arith_op2_sgn <= arith_op2 when alu_fn(1) = '0' else not arith_op2;
-- ...and complement cy input too
cy_in_sgn <= cy_in_gated when alu_fn(1) = '0' else not cy_in_gated;
-- once 2nd operand has been negated (or not) add operands normally
arith_res <= arith_op1 + arith_op2_sgn + signed(std_logic_vector'("00000000"&cy_in_sgn));
-- take only 8 bits; 9th bit of adder is cy output
arith_res8 <= arith_res(7 downto 0);
cy_adder <= arith_res(8);
--##### DAA dedicated logic
-- Intel documentation does not cover many details of this instruction.
-- It has been experimentally determined that the following is the algorithm
-- employed in the actual original silicon:
--
-- 1.- If ACC(3..0) > 9 OR AC=1 then add 06h to ACC.
-- 2.- If (ACC(7..4) > 9 OR AC=1) OR (ACC(7..4)==9 AND (CY=1 OR ACC(3..0) > 9))
-- then add 60h to ACC.
-- Steps 1 and 2 are performed in parallel.
-- AC = 1 iif ACC(3..0) >= 10
-- CY = 1 if CY was already 1 OR
-- (ACC(7..4)>=9 AND ACC(3..0)>=10) OR
-- ACC(7..4)>=10
-- else CY is zero.
-- Note a DAA takes 2 cycles to complete; the adjutment addition is registered
-- so that it does not become the speed bottleneck. The DAA microcode will
-- execute two ALU DAA operations in a row before taking the ALU result.
-- '1' when ACC(3..0) > 9
acc_low_gt9 <= '1' when
to_integer(unsigned(arith_op2(3 downto 0))) > 9
--arith_op2(3 downto 2)="11" or arith_op2(3 downto 1)="101"
else '0';
-- '1' when ACC(7..4) > 9
acc_high_gt9 <= '1' when
to_integer(unsigned(arith_op2(7 downto 4))) > 9
--arith_op2(7 downto 6)="11" or arith_op2(7 downto 5)="101"
else '0';
-- '1' when ACC(7..4) >= 9
acc_high_ge9 <= '1' when
to_integer(unsigned(arith_op2(7 downto 4))) >= 9
else '0';
-- Condition for adding 6 to the low nibble
daa_test1 <= '1' when
acc_low_gt9='1' or -- A(3..0) > 9
flag_reg(4)='1' -- AC set
else '0';
-- condition for adding 6 to the high nibble
daa_test2 <= '1' when
(acc_high_gt9='1' or -- A(7..4) > 9
flag_reg(0)='1') or -- CY set
(daa_test2a = '1') -- condition below
else '0';
-- A(7..4)==9 && (CY or ACC(3..0)>9)
daa_test2a <= '1' when
arith_op2(7 downto 4)="1001" and (flag_reg(0)='1' or acc_low_gt9='1')
else '0';
-- daa_adjust is what we will add to ACC in order to adjust it to BCD
daa_adjust(3 downto 0) <= "0110" when daa_test1='1' else "0000";
daa_adjust(7 downto 4) <= "0110" when daa_test2='1' else "0000";
daa_adjust(8) <= '0';
-- The adder is registered so as to improve the clock rate. This takes the DAA
-- logic out of the critical speed path at the cost of an extra cycle for DAA,
-- which is a good compromise.
daa_adjutment_adder:
process(clk)
begin
if clk'event and clk='1' then
daa_res9 <= arith_op2 + signed(daa_adjust);
end if;
end process daa_adjutment_adder;
-- AC flag raised if the low nibble was > 9, cleared otherwise.
flag_ac_daa <= acc_low_gt9;
-- CY flag raised if the condition above holds, otherwise keeps current value.
cy_daa <= '1' when
flag_reg(0)='1' or -- If CY is already 1, keep value
( (acc_high_ge9='1' and acc_low_gt9='1') or (acc_low_gt9='1') )
else '0';
-- DAA vs. adder mux
with do_daa select arith_daa_res <=
std_logic_vector(daa_res9(7 downto 0)) when '1',
std_logic_vector(arith_res8) when others;
-- DAA vs. adder CY mux
cy_arith <= cy_daa when do_daa='1' else cy_adder;
--##### Logic operations block
logic_res <= T1 and T2 when alu_fn = "00" else
T1 xor T2 when alu_fn = "01" else
T1 or T2 when alu_fn = "10" else
not T1;
--##### Shifter
shifter:
for i in 1 to 6 generate
begin
shift_res(i) <= T1(i-1) when alu_fn(0) = '0' else T1(i+1);
end generate;
shift_res(0) <= T1(7) when alu_fn = "00" else -- rot left
cy_in when alu_fn = "10" else -- rot left through carry
T1(1); -- rot right
shift_res(7) <= T1(0) when alu_fn = "01" else -- rot right
cy_in when alu_fn = "11" else -- rot right through carry
T1(6); -- rot left
cy_shifter <= T1(7) when alu_fn(0) = '0' else -- left
T1(0); -- right
alu_mux1 <= logic_res when use_logic = '1' else shift_res;
with mux_fn select
alu_output <= alu_mux1 when "00",
arith_daa_res when "01",
not alu_mux1 when "10",
"00"&d_field&"000" when others; -- RST
--###### flag computation
flag_s <= alu_output(7);
flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
flag_z <= '1' when alu_output=X"00" else '0';
-- AC is either the CY from bit 4 OR 0 if the instruction clears it implicitly
flag_ac <= flag_ac_and when set_ac = '1' and do_daa='0' else
'0' when clear_ac = '1' else
flag_ac_daa when do_daa = '1' else
(arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
-- AN* instructions deal with AC flag a bit differently
flag_ac_and <= T1(3) or T2(3);
-- CY comes from the adder or the shifter, or is 0 if the instruction
-- implicitly clears it.
flag_cy_1 <= '0' when clear_cy = '1' else
cy_arith when use_logic = '1' and clear_cy = '0' else
cy_shifter;
-- CY can also be explicitly set or complemented by STC and CMC
flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
-- No do the actual CY update
flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
flag_aux_cy <= cy_adder;
-- auxiliary carry reg
process(clk)
begin
if clk'event and clk='1' then
if reset='1' or uc_decode = '1' then
reg_aux_cy <= '1'; -- inits to 0 every instruction
else
reg_aux_cy <= flag_aux_cy;
end if;
end if;
end process;
-- load PSW from ALU (i.e. POP AF) or from flag signals
load_psw <= '1' when we_rb='1' and rbank_wr_addr="0110" else '0';
-- The F register has been split in two separate groupt that always update
-- together (C and all others).
-- F register, flags S,Z,AC,P
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
flag_reg(7) <= '0';
flag_reg(6) <= '0';
flag_reg(4) <= '0';
flag_reg(2) <= '0';
elsif flag_pattern(1) = '1' then
if load_psw = '1' then
flag_reg(7) <= alu_output(7);
flag_reg(6) <= alu_output(6);
flag_reg(4) <= alu_output(4);
flag_reg(2) <= alu_output(2);
else
flag_reg(7) <= flag_s;
flag_reg(6) <= flag_z;
flag_reg(4) <= flag_ac;
flag_reg(2) <= flag_p;
end if;
end if;
end if;
end procesS;
-- F register, flag C
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
flag_reg(0) <= '0';
elsif flag_pattern(0) = '1' then
if load_psw = '1' then
flag_reg(0) <= alu_output(0);
else
flag_reg(0) <= flag_cy;
end if;
end if;
end if;
end procesS;
flag_reg(5) <= '0'; -- constant flag
flag_reg(3) <= '0'; -- constant flag
flag_reg(1) <= '1'; -- constant flag
--##### Condition computation
condition_sel <= d_field(2 downto 0);
with condition_sel select
condition <=
not flag_reg(6) when "000", -- NZ
flag_reg(6) when "001", -- Z
not flag_reg(0) when "010", -- NC
flag_reg(0) when "011", -- C
not flag_reg(2) when "100", -- PO
flag_reg(2) when "101", -- PE
not flag_reg(7) when "110", -- P
flag_reg(7) when others;-- M
-- condition is registered to shorten the delay path; the extra 1-cycle
-- delay is not relevant because conditions are tested in the next instruction
-- at the earliest, and there's at least the fetch uinsts intervening.
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
condition_reg <= '0';
else
condition_reg <= condition;
end if;
end if;
end process;
-- low byte address register
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
addr_low <= X"00";
elsif load_al = '1' then
addr_low <= rbank_data;
end if;
end if;
end process;
-- note external address registers (high byte) are loaded directly from rbank
addr_out <= rbank_data & addr_low;
data_out <= DO;
end microcoded;
--------------------------------------------------------------------------------
-- Timing diagram 1: RD and WR cycles
--------------------------------------------------------------------------------
-- 1 2 3 4 5 6 7 8
-- __ __ __ __ __ __ __ __
-- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
--
-- ==|=====|=====|=====|=====|=====|=====|=====|=====|
--
-- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx
--
-- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx
--
-- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx
-- _____ _____
-- vma_o ______________/ \___________/ \___________
-- _____
-- rd_o ______________/ \_____________________________
-- _____
-- wr_o ________________________________/ \___________
--
-- (functional diagram, actual time delays not shown)
--------------------------------------------------------------------------------
-- This diagram shows a read cycle and a write cycle back to back.
-- In clock edges (4) and (7), the address is loaded into the external
-- synchronous RAM address register.
-- In clock edge (5), read data is loaded into the CPU.
-- In clock edge (7), write data is loaded into the external synchronous RAM.
-- In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock
-- cycles, which is a waste of RAM bandwidth.
--
| lgpl-2.1 | 229bbbc336321ffadab61a38101a9583 | 0.60238 | 3.3043 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/mem_content.vhd | 3 | 26,582 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mem_content is
-- content of m_0_0
constant m_0_0_0 : BIT_VECTOR := X"9A94D4AD3DA5B5B3494A5E7F5F52F4B7E85E86F55BD2599BBED556D0FA186008";
constant m_0_0_1 : BIT_VECTOR := X"00000012FD4A9064A212F0B44569BF76453534FFD37B9A99B5352DA9A945352A";
constant m_0_0_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_0_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_0_1
constant m_0_1_0 : BIT_VECTOR := X"8CEDE77380EE7714C866432D57265582E6CAA054C9540EDCCD2B6B37844E6B08";
constant m_0_1_1 : BIT_VECTOR := X"0000007C3995A229037D7FCEF399199AEB19D542318B68EAB319C098CE1319D9";
constant m_0_1_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_1_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_0_2
constant m_0_2_0 : BIT_VECTOR := X"92F586973F82F429A96D4F64537EC5C66DD8B8C5EB151DE87C895C36445C4718";
constant m_0_2_1 : BIT_VECTOR := X"00000052C44FD2B4A712EC5ED8BDD4FA5525FB9252615AFC9525F9492FC525FA";
constant m_0_2_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_2_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_0_3
constant m_0_3_0 : BIT_VECTOR := X"C0E5B63BFF2769008C646709642017108602F210D05C4C60E88C4C26454D0B9B";
constant m_0_3_1 : BIT_VECTOR := X"0000005092DDB23DD35198EFC1DB01DF6181DA02181648EC9181C80C0E6181C8";
constant m_0_3_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_3_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_0_4
constant m_0_4_0 : BIT_VECTOR := X"C0E5B711C00228848C646100633007006600E00CD01E8640628C0C8350670813";
constant m_0_4_1 : BIT_VECTOR := X"0000002C60000200446C0C45C08B90C76181DA0A180400EC9181CC0C0E5181C8";
constant m_0_4_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_4_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_0_5
constant m_0_5_0 : BIT_VECTOR := X"1220A1207F2409A149124C89655696B4E852C29D5A5AD202A250542545230551";
constant m_0_5_1 : BIT_VECTOR := X"00000041000407007FC014834506854D04244299424092240424452122042442";
constant m_0_5_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_5_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_0_6
constant m_0_6_0 : BIT_VECTOR := X"DA868408C001183549524880634486242890C485421A102A0494100001290119";
constant m_0_6_1 : BIT_VECTOR := X"0000003EFF03C0F0773E04234446040405B508D25B6C9284D5B509ADA855B50A";
constant m_0_6_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_6_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_0_7
constant m_0_7_0 : BIT_VECTOR := X"00228000C000180048024000611006802200D004001800000240000001210011";
constant m_0_7_1 : BIT_VECTOR := X"0000000000000000000004034006800520004009000000204000400002000040";
constant m_0_7_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_0_7_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_0
constant m_1_0_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_1
constant m_1_1_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_2
constant m_1_2_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_3
constant m_1_3_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_4
constant m_1_4_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_5
constant m_1_5_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_6
constant m_1_6_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_7
constant m_1_7_0 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_1 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_2 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_3 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_8 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
end mem_content;
package body mem_content is
end mem_content;
| mit | ceb0bd5dee09db5f7e97fa2490fecab8 | 0.839252 | 5.064203 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/buttons/many_buttons.vhd | 1 | 1,001 | -- Implement the button functionality described in button_pkg.
-- buttons are implemented on an individual character-by-character basis. This
-- entity instantiates 26 button-pressed/toggled detectors
library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.button_pkg.all;
use virtual_button_lib.utils.all;
entity many_buttons is
port(
ctrl : in ctrl_t;
data : in ascii_vector;
new_data : in std_logic;
buttons : out button_arr
);
end;
architecture rtl of many_buttons is
begin
gen_buttons:
for lowercase_enum in lowercase_enum'left to lowercase_enum'right generate
single_button_1 : entity virtual_button_lib.single_button
generic map (
the_char => lowercase_enum)
port map (
ctrl => ctrl,
rx_data => data,
new_data => new_data,
pressed => buttons(lowercase_enum).pressed,
toggle => buttons(lowercase_enum).toggle
);
end generate;
end;
| bsd-2-clause | 583175d072ddb8f93d8602645de81b93 | 0.671329 | 3.72119 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/uart_tx.vhd | 1 | 1,721 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
PORT( CLK_I : in std_logic;
CLR : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : in std_logic; -- toggle to send data
SER_OUT : out std_logic; -- Serial output line
DATA_FLAGQ : out std_logic -- Transmitting Flag
);
end UART_TX;
architecture TX_UART_arch of UART_TX is
signal BUF : std_logic_vector(7 downto 0);
signal TODO : integer range 0 to 9; -- bits to send
signal FLAGQ : std_logic;
signal CE_1 : std_logic;
signal C16 : std_logic_vector(3 downto 0);
begin
DATA_FLAGQ <= FLAGQ;
-- generate a CE_1 every 16 CE_16...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
CE_1 <= '0';
if (CLR = '1') then
C16 <= "0000";
elsif (CE_16 = '1') then
if (C16 = "1111") then
CE_1 <= '1';
end if;
C16 <= C16 + "0001";
end if;
end if;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
SER_OUT <= '1';
BUF <= "11111111";
TODO <= 0;
FLAGQ <= DATA_FLAG; -- idle
elsif (CE_1 = '1') then
if (TODO > 0) then -- transmitting
SER_OUT <= BUF(0); -- next bit
BUF <= '1' & BUF(7 downto 1);
if (TODO = 1) then
FLAGQ <= DATA_FLAG;
end if;
TODO <= TODO - 1;
elsif (FLAGQ /= DATA_FLAG) then -- new byte
SER_OUT <= '0'; -- start bit
TODO <= 9;
BUF <= DATA;
end if;
end if;
end if;
end process;
end TX_UART_arch;
| mit | 2bd06941913695ced3223fe6c02c69f2 | 0.525857 | 2.693271 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/MAC4/MAC4_tb.vhd | 1 | 1,406 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MAC4_tb IS
END MAC4_tb;
architecture tb OF MAC4_tb IS
component MAC4
port(A,B : in std_logic_vector(3 downto 0); Z : out std_logic_vector(7 downto 0));
end component;
signal A : std_logic_vector(3 downto 0);-- := (others => '0');
signal B : std_logic_vector(3 downto 0);-- := (others => '0');
signal Z : std_logic_vector(7 downto 0);
-- signal Ai,Bi: integer;
begin
mapping: MAC4 port map(A, B, Z);
process
begin
A(3) <= '0'; wait for 128 ns;
A(3) <= '1'; wait for 128 ns;
end process;
process
begin
A(2) <= '0'; wait for 64 ns;
A(2) <= '1'; wait for 64 ns;
end process;
process
begin
A(1) <= '0'; wait for 32 ns;
A(1) <= '1'; wait for 32 ns;
end process;
process
begin
A(0) <= '0'; wait for 16 ns;
A(0) <= '1'; wait for 16 ns;
end process;
process
begin
B(3) <= '0'; wait for 8 ns;
B(3) <= '1'; wait for 8 ns;
end process;
process
begin
B(2) <= '0'; wait for 4 ns;
B(2) <= '1'; wait for 4 ns;
end process;
process
begin
B(1) <= '0'; wait for 2 ns;
B(1) <= '1'; wait for 2 ns;
end process;
process
begin
B(0) <= '0'; wait for 1 ns;
B(0) <= '1'; wait for 1 ns;
end process;
end tb;
configuration cfg_tb of MAC4_tb is
for tb
end for;
end cfg_tb; | mit | dc4818da4f728db64e6b8f318b4e5579 | 0.534139 | 2.784158 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/cygraph_kernel.vhd | 1 | 30,214 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- CyGraph Kernel
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity cygraph_kernel is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
current_level : in unsigned(31 downto 0); -- Current Level
cq_count : in unsigned(31 downto 0); -- Number of nodes to visit in the current level
-- kernels communication signals
kernel_tx_done : out std_logic; -- 0 kernel done, 1 kernel working
kernel_tx_vld : out std_logic;
kernel_tx_count : out unsigned(31 downto 0);
kernel_rx_done : in std_logic; -- 0 previous kernel done, 1 previous kernel working
kernel_rx_vld : in std_logic;
kernel_rx_count : in unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData : in std_logic_vector(63 downto 0);
graphInfo : in std_logic_vector(63 downto 0);
cq_address : in std_logic_vector(63 downto 0);
nq_address : in std_logic_vector(63 downto 0);
reach_queue : in std_logic_vector(63 downto 0);
-- Parameters for next kernel
nxtk_rst : out std_logic;
nxtk_enable : out std_logic;
nextk_busy : in std_logic;
nxtk_current_lvl : out unsigned(31 downto 0);
nxtk_cq_count : out unsigned(31 downto 0);
nxtk_graphData : out std_logic_vector(63 downto 0);
nxtk_graphInfo : out std_logic_vector(63 downto 0);
nxtk_cq_address : out std_logic_vector(63 downto 0);
nxtk_nq_address : out std_logic_vector(63 downto 0);
nxtk_reach_queue : out std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0);
-- MC flush signals
mc_req_flush : out std_logic;
mc_rsp_flush_cmplt : in std_logic
);
end cygraph_kernel;
architecture Behavioral of cygraph_kernel is
component master is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic;
done : out std_logic;
started : out std_logic;
-- kernels communication signals
current_level : in unsigned(31 downto 0); -- Current Level
kernel_rx_vld : in std_logic;
wr_offset : in unsigned(31 downto 0);
wr_reserved_space : in unsigned(31 downto 0);
wr_used_space : out unsigned(31 downto 0);
-- Memory pointers
graphInfo : in std_logic_vector(63 downto 0);
nq_address : in std_logic_vector(63 downto 0);
reach_queue : in std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC flush signals
mc_req_flush : out std_logic;
mc_rsp_flush_cmplt : in std_logic;
-- Process 1 signals
p1_req_q_rd_enb : out std_logic;
p1_req_q_dout : in std_logic_vector(63 downto 0);
p1_req_q_valid : in std_logic;
p1_req_q_empty : in std_logic;
-- Process 2 signals
p2_req_q_rd_enb : out std_logic;
p2_req_q_dout : in std_logic_vector(63 downto 0);
p2_req_q_valid : in std_logic;
p2_req_q_empty : in std_logic;
-- Process 3 signals
p3_req_q_rd_enb : out std_logic;
p3_req_q_dout : in std_logic_vector(63 downto 0);
p3_req_q_valid : in std_logic;
p3_req_q_empty : in std_logic;
-- Process 4 signals
p4_done : in std_logic;
p4_addr_q_rd_enb : out std_logic;
p4_addr_q_dout : in std_logic_vector(63 downto 0);
p4_addr_q_valid : in std_logic;
p4_addr_q_empty : in std_logic;
p4_info_q_rd_enb : out std_logic;
p4_info_q_dout : in std_logic_vector(63 downto 0);
p4_info_q_valid : in std_logic;
p4_info_q_empty : in std_logic
);
end component;
component process1 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0);
ae_id : in std_logic_vector(1 downto 0);
kernels_count : in unsigned(7 downto 0);
cq_count : in unsigned(31 downto 0);
-- Queue pointers
cq_address : in std_logic_vector(63 downto 0);
-- Process 1 signals
p1_done : out std_logic;
p1_count : out unsigned(31 downto 0);
-- Process 1 req queue signals
p1_req_q_almost_full : in std_logic;
p1_req_q_wr_en : out std_logic;
p1_req_q_din : out std_logic_vector(63 downto 0);
p1_req_q_full : in std_logic
);
end component;
component process2
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 2 information
p2_done : out std_logic;
p2_busy : out std_logic;
p2_count_1 : out unsigned(31 downto 0);
p2_count_2 : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphData : in std_logic_vector(63 downto 0);
-- Process 1 information
p1_done : in std_logic;
p1_count : in unsigned(31 downto 0);
-- Process 1 response queue signals
p1_rsp_q_rd_en : in std_logic;
p1_rsp_q_rd_enb : out std_logic;
p1_rsp_q_dout : in std_logic_vector(63 downto 0);
p1_rsp_q_valid : in std_logic;
p1_rsp_q_empty : in std_logic;
-- Process 2 request queue signals
p2_req_q_almost_full : in std_logic;
p2_req_q_wr_en : out std_logic;
p2_req_q_din : out std_logic_vector(63 downto 0)
);
end component;
component process3
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 3 signals
p3_done : out std_logic;
p3_count : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count_2 : in unsigned(31 downto 0);
-- Process 3 req queue signals
p3_req_q_almost_full : in std_logic;
p3_req_q_wr_en : out std_logic;
p3_req_q_din : out std_logic_vector(63 downto 0);
p3_req_q_full : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end component;
component fifo_generator_32_512 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
component fifo_generator_64_512 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
-- type addr_array is array (0 to 7) of std_logic_vector(63 downto 0);
signal k_rst : std_logic;
signal k_busy : std_logic;
-- Master process signals
signal started : std_logic;
signal wr_offset : unsigned(31 downto 0); -- Next queue write offset (get it from previous kernel)
signal wr_demand_count : unsigned(31 downto 0); -- Space that kernel needs to reserve to write to next queue
signal wr_reserved_space : unsigned(31 downto 0); -- What I already reserved previously
signal wr_used_space : unsigned(31 downto 0); -- What I consumed from the reserved space
signal out_done : std_logic;
-- registers for output
signal out_kernel_tx_vld : std_logic;
-- Process 1 signals
signal p1_done : std_logic;
signal p1_count : unsigned(31 downto 0);
signal p1_offset : unsigned(31 downto 0);
signal p1_req_q_rd_enb : std_logic;
signal p1_rsp_q_rd_enb : std_logic;
signal p1_req_q_almost_full : std_logic;
signal p1_req_q_wr_en : std_logic;
signal p1_req_q_rd_en : std_logic;
signal p1_req_q_din : std_logic_vector(63 downto 0);
signal p1_req_q_dout : std_logic_vector(63 downto 0);
signal p1_req_q_valid : std_logic;
signal p1_req_q_full : std_logic;
signal p1_req_q_empty : std_logic;
signal p1_rsp_q_almost_full : std_logic;
signal p1_rsp_q_wr_en : std_logic;
signal p1_rsp_q_rd_en : std_logic;
signal p1_rsp_q_din : std_logic_vector(63 downto 0);
signal p1_rsp_q_dout : std_logic_vector(63 downto 0);
signal p1_rsp_q_valid : std_logic;
signal p1_rsp_q_full : std_logic;
signal p1_rsp_q_empty : std_logic;
-- Process 2 signals
signal p2_done : std_logic;
signal p2_busy : std_logic;
signal p2_count_1 : unsigned(31 downto 0);
signal p2_count_2 : unsigned(31 downto 0);
signal p2_req_q_rd_enb : std_logic;
signal p2_rsp_q_rd_enb : std_logic;
signal p2_req_q_almost_full : std_logic;
signal p2_req_q_wr_en : std_logic;
signal p2_req_q_rd_en : std_logic;
signal p2_req_q_din : std_logic_vector(63 downto 0);
signal p2_req_q_dout : std_logic_vector(63 downto 0);
signal p2_req_q_valid : std_logic;
signal p2_req_q_full : std_logic;
signal p2_req_q_empty : std_logic;
signal p2_rsp_q_almost_full : std_logic;
signal p2_rsp_q_wr_en : std_logic;
signal p2_rsp_q_rd_en : std_logic;
signal p2_rsp_q_din : std_logic_vector(31 downto 0);
signal p2_rsp_q_dout : std_logic_vector(31 downto 0);
signal p2_rsp_q_valid : std_logic;
signal p2_rsp_q_full : std_logic;
signal p2_rsp_q_empty : std_logic;
-- Process 3 signals
signal p3_done : std_logic;
signal p3_count : unsigned(31 downto 0);
signal p3_req_q_rd_enb : std_logic;
signal p3_rsp_q_rd_enb : std_logic;
signal p3_req_q_almost_full : std_logic;
signal p3_req_q_wr_en : std_logic;
signal p3_req_q_rd_en : std_logic;
signal p3_req_q_din : std_logic_vector(63 downto 0);
signal p3_req_q_dout : std_logic_vector(63 downto 0);
signal p3_req_q_valid : std_logic;
signal p3_req_q_full : std_logic;
signal p3_req_q_empty : std_logic;
signal p3_rsp_q_almost_full : std_logic;
signal p3_rsp_q_wr_en : std_logic;
signal p3_rsp_q_rd_en : std_logic;
signal p3_rsp_q_din : std_logic_vector(63 downto 0);
signal p3_rsp_q_dout : std_logic_vector(63 downto 0);
signal p3_rsp_q_valid : std_logic;
signal p3_rsp_q_full : std_logic;
signal p3_rsp_q_empty : std_logic;
-- Process 4 signals
signal p4_done : std_logic;
signal p4_count : unsigned(31 downto 0);
signal p4_state : unsigned(1 downto 0);
signal p4_addr_q_rd_enb : std_logic;
signal p4_info_q_rd_enb : std_logic;
signal p4_addr_q_almost_full : std_logic;
signal p4_addr_q_wr_en : std_logic;
signal p4_addr_q_rd_en : std_logic;
signal p4_addr_q_din : std_logic_vector(63 downto 0);
signal p4_addr_q_dout : std_logic_vector(63 downto 0);
signal p4_addr_q_valid : std_logic;
signal p4_addr_q_full : std_logic;
signal p4_addr_q_empty : std_logic;
signal p4_info_q_almost_full : std_logic;
signal p4_info_q_wr_en : std_logic;
signal p4_info_q_rd_en : std_logic;
signal p4_info_q_din : std_logic_vector(63 downto 0);
signal p4_info_q_dout : std_logic_vector(63 downto 0);
signal p4_info_q_valid : std_logic;
signal p4_info_q_full : std_logic;
signal p4_info_q_empty : std_logic;
begin
-- Output signals
busy <= k_busy or nextk_busy;
done <= out_done;
kernel_tx_vld <= out_kernel_tx_vld; -- when out_done = '0' else kernel_rx_vld;
-- mask rd enable signals with empty signals
p1_req_q_rd_en <= p1_req_q_rd_enb and not p1_req_q_empty;
p1_rsp_q_rd_en <= p1_rsp_q_rd_enb and not p1_rsp_q_empty and not p2_busy; -- TEST -- WERID!! WHY I NEED THE BUSY SIGNAL??
p2_req_q_rd_en <= p2_req_q_rd_enb and not p2_req_q_empty;
p2_rsp_q_rd_en <= p2_rsp_q_rd_enb and not p2_rsp_q_empty and not p3_rsp_q_empty;
p3_req_q_rd_en <= p3_req_q_rd_enb and not p3_req_q_empty;
p3_rsp_q_rd_en <= p3_rsp_q_rd_enb and not p2_rsp_q_empty and not p3_rsp_q_empty;
p4_addr_q_rd_en <= p4_addr_q_rd_enb and not p4_addr_q_empty;
p4_info_q_rd_en <= p4_info_q_rd_enb and not p4_info_q_empty;
p0: master
port map (
-- control signals
clk => clk,
rst => k_rst,
enable => enable,
busy => k_busy,
done => out_done,
started => started,
-- kernels communication signals
current_level => current_level,
kernel_rx_vld => kernel_rx_vld,
wr_offset => wr_offset,
wr_reserved_space => wr_reserved_space,
wr_used_space => wr_used_space,
-- Memory pointers
graphInfo => graphInfo,
nq_address => nq_address,
reach_queue => reach_queue,
-- MC request port signals
mc_req_ld => mc_req_ld,
mc_req_st => mc_req_st,
mc_req_size => mc_req_size,
mc_req_vaddr => mc_req_vaddr,
mc_req_wrd_rdctl => mc_req_wrd_rdctl,
mc_rd_rq_stall => mc_rd_rq_stall,
mc_wr_rq_stall => mc_wr_rq_stall,
-- MC flush signals
mc_req_flush => mc_req_flush,
mc_rsp_flush_cmplt => mc_rsp_flush_cmplt,
-- Process 1 signals
p1_req_q_rd_enb => p1_req_q_rd_enb,
p1_req_q_dout => p1_req_q_dout,
p1_req_q_valid => p1_req_q_valid,
p1_req_q_empty => p1_req_q_empty,
-- Process 2 signals
p2_req_q_rd_enb => p2_req_q_rd_enb,
p2_req_q_dout => p2_req_q_dout,
p2_req_q_valid => p2_req_q_valid,
p2_req_q_empty => p2_req_q_empty,
-- Process 3 signals
p3_req_q_rd_enb => p3_req_q_rd_enb,
p3_req_q_dout => p3_req_q_dout,
p3_req_q_valid => p3_req_q_valid,
p3_req_q_empty => p3_req_q_empty,
-- Process 4 signals
p4_done => p4_done,
p4_addr_q_rd_enb => p4_addr_q_rd_enb,
p4_addr_q_dout => p4_addr_q_dout,
p4_addr_q_valid => p4_addr_q_valid,
p4_addr_q_empty => p4_addr_q_empty,
p4_info_q_rd_enb => p4_info_q_rd_enb,
p4_info_q_dout => p4_info_q_dout,
p4_info_q_valid => p4_info_q_valid,
p4_info_q_empty => p4_info_q_empty
);
p1: process1
port map (
-- control signals
clk => clk,
rst => k_rst,
started => started,
-- Kernel Parameters
kernel_id => kernel_id,
ae_id => ae_id,
kernels_count => kernels_count,
cq_count => cq_count,
-- Queue pointers
cq_address => cq_address,
-- Process 1 signals
p1_done => p1_done,
p1_count => p1_count,
-- Process 1 req queue signals
p1_req_q_almost_full => p1_req_q_almost_full,
p1_req_q_wr_en => p1_req_q_wr_en,
p1_req_q_din => p1_req_q_din,
p1_req_q_full => p1_req_q_full
);
p2: process2
port map (
-- control signals
clk => clk,
rst => k_rst,
started => started,
-- Process 2 information
p2_done => p2_done,
p2_busy => p2_busy,
p2_count_1 => p2_count_1,
p2_count_2 => p2_count_2,
-- Input Graph Pointers (Represented in Custom CSR)
graphData => graphData,
-- Process 1 information
p1_done => p1_done,
p1_count => p1_count,
-- Process 1 response queue signals
p1_rsp_q_rd_en => p1_rsp_q_rd_en,
p1_rsp_q_rd_enb => p1_rsp_q_rd_enb,
p1_rsp_q_dout => p1_rsp_q_dout,
p1_rsp_q_valid => p1_rsp_q_valid,
p1_rsp_q_empty => p1_rsp_q_empty,
-- Process 2 request queue signals
p2_req_q_almost_full => p2_req_q_almost_full,
p2_req_q_wr_en => p2_req_q_wr_en,
p2_req_q_din => p2_req_q_din
);
p3: process3
port map (
-- control signals
clk => clk,
rst => k_rst,
started => started,
-- Process 3 signals
p3_done => p3_done,
p3_count => p3_count,
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo => graphInfo,
-- Process 2 information
p2_done => p2_done,
p2_count_2 => p2_count_2,
-- Process 3 req queue signals
p3_req_q_almost_full => p3_req_q_almost_full,
p3_req_q_wr_en => p3_req_q_wr_en,
p3_req_q_din => p3_req_q_din,
p3_req_q_full => p3_req_q_full,
-- MC response port signals
mc_rsp_push => mc_rsp_push,
mc_rsp_data => mc_rsp_data,
mc_rsp_rdctl => mc_rsp_rdctl
);
-- Process 1 request queue
p1_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p1_req_q_almost_full,
wr_en => p1_req_q_wr_en,
rd_en => p1_req_q_rd_enb,
din => p1_req_q_din,
dout => p1_req_q_dout,
full => p1_req_q_full,
empty => p1_req_q_empty,
valid => p1_req_q_valid
);
-- process 1 respond queue
p1_rsp_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p1_rsp_q_almost_full,
wr_en => p1_rsp_q_wr_en,
rd_en => p1_rsp_q_rd_en,
din => p1_rsp_q_din,
dout => p1_rsp_q_dout,
full => p1_rsp_q_full,
empty => p1_rsp_q_empty,
valid => p1_rsp_q_valid
);
-- process 2 request queue
p2_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_req_q_almost_full,
wr_en => p2_req_q_wr_en,
rd_en => p2_req_q_rd_en,
din => p2_req_q_din,
dout => p2_req_q_dout,
full => p2_req_q_full,
empty => p2_req_q_empty,
valid => p2_req_q_valid
);
-- process 2 respond queue
p2_rsp_q : fifo_generator_32_512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_rsp_q_almost_full,
wr_en => p2_rsp_q_wr_en,
rd_en => p2_rsp_q_rd_en,
din => p2_rsp_q_din,
dout => p2_rsp_q_dout,
full => p2_rsp_q_full,
empty => p2_rsp_q_empty,
valid => p2_rsp_q_valid
);
-- process 3 request queue
p3_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p3_req_q_almost_full,
wr_en => p3_req_q_wr_en,
rd_en => p3_req_q_rd_en,
din => p3_req_q_din,
dout => p3_req_q_dout,
full => p3_req_q_full,
empty => p3_req_q_empty,
valid => p3_req_q_valid
);
-- process 3 respond queue
p3_rsp_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p3_rsp_q_almost_full,
wr_en => p3_rsp_q_wr_en,
rd_en => p3_rsp_q_rd_en,
din => p3_rsp_q_din,
dout => p3_rsp_q_dout,
full => p3_rsp_q_full,
empty => p3_rsp_q_empty,
valid => p3_rsp_q_valid
);
-- process 4 address queue
p4_addr_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p4_addr_q_almost_full,
wr_en => p4_addr_q_wr_en,
rd_en => p4_addr_q_rd_en,
din => p4_addr_q_din,
dout => p4_addr_q_dout,
full => p4_addr_q_full,
empty => p4_addr_q_empty,
valid => p4_addr_q_valid
);
-- process 4 information queue (custom csr)
p4_info_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p4_info_q_almost_full,
wr_en => p4_info_q_wr_en,
rd_en => p4_info_q_rd_en,
din => p4_info_q_din,
dout => p4_info_q_dout,
full => p4_info_q_full,
empty => p4_info_q_empty,
valid => p4_info_q_valid
);
-- Avoid rst signal fanout problem
p_rst : process(clk)
begin
if (rising_edge(clk)) then
k_rst <= rst;
if (k_rst = '1') then
nxtk_rst <= '0'; -- CHECK THIS, shouldn't this always be <= rst
nxtk_enable <= '0';
nxtk_current_lvl <= (others => '0');
nxtk_cq_count <= (others => '0');
nxtk_graphData <= (others => '0');
nxtk_graphInfo <= (others => '0');
nxtk_cq_address <= (others => '0');
nxtk_nq_address <= (others => '0');
nxtk_reach_queue <= (others => '0');
else
nxtk_rst <= rst;
nxtk_enable <= enable;
nxtk_current_lvl <= current_level;
nxtk_cq_count <= cq_count;
nxtk_graphData <= graphData;
nxtk_graphInfo <= graphInfo;
nxtk_cq_address <= cq_address;
nxtk_nq_address <= nq_address;
nxtk_reach_queue <= reach_queue;
end if;
end if;
end process; -- rst
-- Kernel-to-kenrel process
-- Get the previous kernel reserved count, reserve yours and send it to the next kernel
k2k : process (clk, rst, k_rst)
begin
if (rising_edge(clk)) then
if (k_rst = '1') then
out_kernel_tx_vld <= '0';
kernel_tx_count <= (others => '0');
kernel_tx_done <= '0';
wr_demand_count <= (others => '0');
wr_reserved_space <= (others => '0');
wr_offset <= (others => '0');
else
-- If kernel busy
--- Incrmenet demand count when something is pushed to p4 queues
--- Wait for valid signal from previous kernel, and reserve space
--- Send done signal if done
if (enable = '1') then
out_kernel_tx_vld <= '0';
kernel_tx_count <= (others => '0');
kernel_tx_done <= '0';
wr_demand_count <= (others => '0');
wr_reserved_space <= (others => '0');
wr_offset <= (others => '0');
else
-- Inrease demand count whenever new item is pushed to p4 queues
if (p4_info_q_wr_en = '1') then
wr_demand_count <= wr_demand_count + 1;
end if;
-- if reserved space are consumed, request more ------------------------------------ FIX THAT
if (wr_used_space = wr_reserved_space and kernel_rx_vld = '1') then
out_kernel_tx_vld <= '1';
kernel_tx_count <= kernel_rx_count + wr_demand_count - wr_reserved_space;
wr_reserved_space <= wr_demand_count;
wr_offset <= kernel_rx_count;
-- elsif (wr_used_space < wr_reserved_space and kernel_rx_vld = '1') then
elsif (kernel_rx_vld = '1') then
out_kernel_tx_vld <= '1';
kernel_tx_count <= kernel_rx_count;
else
out_kernel_tx_vld <= '0';
end if;
-- if previous kernel is done and this kernel is done, assert kernel_tx_done
if (kernel_rx_done = '1' and out_done = '1') then
kernel_tx_done <= '1';
else
kernel_tx_done <= '0';
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- Kernel-to-kernel communication
p4 : process (clk, k_rst)
begin
if (rising_edge(clk)) then
if (k_rst = '1') then
p4_done <= '0';
p4_count <= (others => '0');
p4_state <= "00";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
else
if (started = '0') then
p4_done <= '0';
p4_count <= (others => '0');
p4_state <= "00";
-- set queues signals to default
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
elsif (started = '1') then
case (p4_state) is
-- Nothing was popped from queues before
when "00" =>
if (p2_rsp_q_empty = '0' and p3_rsp_q_empty = '0' and p4_info_q_almost_full = '0' and p4_addr_q_almost_full = '0') then
p2_rsp_q_rd_enb <= '1';
p3_rsp_q_rd_enb <= '1';
p4_count <= p4_count + 1;
p4_state <= "01";
-- set queues signals to default
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
else
p4_state <= "00";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end if;
-- Neighbor info is popped from p3_rsp and p2_rsp
when "01" =>
if (p3_rsp_q_valid = '1' and p2_rsp_q_valid = '1') then
-- if not visited, push address and csr to p4 queue
if (p3_rsp_q_dout(0) = '0') then
p4_addr_q_wr_en <= '1';
p4_addr_q_din <= x"00000000" & p2_rsp_q_dout;
if (unsigned(p3_rsp_q_dout(31 downto 1)) > 0) then
p4_info_q_wr_en <= '1';
p4_info_q_din <= p3_rsp_q_dout;
else
p4_info_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
end if;
else
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end if;
-- If there is more, pop them
if (p2_rsp_q_empty = '0' and p3_rsp_q_empty = '0' and p4_info_q_almost_full = '0' and p4_addr_q_almost_full = '0') then
p4_state <= "01";
p2_rsp_q_rd_enb <= '1';
p3_rsp_q_rd_enb <= '1';
p4_count <= p4_count + 1;
else
p4_state <= "00";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
end if;
-- nothing popped yet, keep waiting
else
-- set queues signals to default
p4_state <= "01";
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end if;
when others =>
p4_state <= "00";
-- set queues signals to default
p2_rsp_q_rd_enb <= '0';
p3_rsp_q_rd_enb <= '0';
p4_info_q_wr_en <= '0';
p4_addr_q_wr_en <= '0';
p4_info_q_din <= (others => '0');
p4_addr_q_din <= (others => '0');
end case;
-- Process 4 is done if process 3 is done and p3_count = p4_count = p2_count_2
if p3_done = '1' and p4_count >= p2_count_2 and p4_count >= p3_count and p2_rsp_q_empty = '1' and p4_state = "00" then
p4_done <= '1';
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 4
-- MC Response decoder process
mc_rsp_decoder : process(clk, k_rst)
begin
if rising_edge(clk) then
if (k_rst = '1') then
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
mc_rsp_stall <= '0';
else
if (started = '0') then
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
mc_rsp_stall <= '0';
elsif (started = '1') then
if (mc_rsp_push = '1') then
-- Get process 1 response
if (mc_rsp_rdctl(7 downto 0) = x"01") then
-- push results to p1 response queue
p1_rsp_q_wr_en <= '1';
p1_rsp_q_din <= mc_rsp_data;
-- reset others
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
-- Get process 2 response
elsif (mc_rsp_rdctl(7 downto 0) = x"02") then
-- push results to p2 response queue
p2_rsp_q_wr_en <= '1';
p2_rsp_q_din <= mc_rsp_data(31 downto 0);
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
-- Get process 3 response
elsif (mc_rsp_rdctl(7 downto 0) = x"03") then
-- push results to p3 response queue
p3_rsp_q_wr_en <= '1';
p3_rsp_q_din <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
else
-- set p1 response qeueue signals to defaults
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
-- set p2 response qeueue signals to defaults
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
-- set p3 response qeueue signals to defaults
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
end if;
else
-- set p1 response qeueue signals to defaults
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
-- set p2 response qeueue signals to defaults
p2_rsp_q_wr_en <= '0';
p2_rsp_q_din <= (others => '0');
-- set p3 response qeueue signals to defaults
p3_rsp_q_wr_en <= '0';
p3_rsp_q_din <= (others => '0');
end if;
-- Control mc_rsp_stall signal
if (p1_rsp_q_almost_full = '1' or p2_rsp_q_almost_full = '1' or p3_rsp_q_almost_full = '1'
or p3_req_q_almost_full = '1' or p4_info_q_almost_full = '1' or p4_addr_q_almost_full = '1') then
mc_rsp_stall <= '1';
else
mc_rsp_stall <= '0';
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- end process rsp decoder
end Behavioral;
| apache-2.0 | 81aeb2d2b8bb3f3e3f24d40c8e7681b0 | 0.566228 | 2.452634 | false | false | false | false |
willtmwu/vhdlExamples | Project/ssegDriver.vhd | 4 | 3,930 | --generated by V2 synthesiser
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ssegDriver is port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0) := "0000";
digit2_p : in std_logic_vector(3 downto 0) := "0000";
digit3_p : in std_logic_vector(3 downto 0) := "0000";
digit4_p : in std_logic_vector(3 downto 0) := "0000";
digit5_p : in std_logic_vector(3 downto 0) := "0000";
digit6_p : in std_logic_vector(3 downto 0) := "0000";
digit7_p : in std_logic_vector(3 downto 0) := "0000";
digit8_p : in std_logic_vector(3 downto 0) := "0000"
); end ssegDriver;
------------------------------------------------
architecture behavioural of ssegDriver is
signal digit_reg : std_logic_vector(31 downto 0);
signal anode_reg : std_logic_vector(7 downto 0);
signal digitout_reg : std_logic_vector(3 downto 0);
signal digit_sel : std_logic_vector(2 downto 0);
signal next_sel : std_logic_vector(2 downto 0);
begin
--Clock and set state machine
process (clk, rst)
begin
if (rst = '1') then
digit_reg <= "00000000000000000000000000000000";
digit_sel <= "000";
next_sel <= "000";
digitout_reg <= "0000";
anode_reg <= "11111111";
elsif (clk'event and clk = '1') then
--latch digits into register on clock edge
digit_reg(3 downto 0) <= digit1_p;
digit_reg(7 downto 4) <= digit2_p;
digit_reg(11 downto 8) <= digit3_p;
digit_reg(15 downto 12) <= digit4_p;
digit_reg(19 downto 16) <= digit5_p;
digit_reg(23 downto 20) <= digit6_p;
digit_reg(27 downto 24) <= digit7_p;
digit_reg(31 downto 28) <= digit8_p;
digit_sel <= next_sel;
case digit_sel is
when "000" =>
anode_reg <= "11111110";
digitout_reg <= digit_reg(3 downto 0);
next_sel <= "001";
when "001" =>
anode_reg <= "11111101";
digitout_reg <= digit_reg(7 downto 4);
digit_sel <= "010";
when "010" =>
anode_reg <= "11111011";
digitout_reg <= digit_reg(11 downto 8);
next_sel <= "011";
when "011" =>
anode_reg <= "11110111";
digitout_reg <= digit_reg(15 downto 12);
next_sel <= "100";
when "100" =>
anode_reg <= "11101111";
digitout_reg <= digit_reg(19 downto 16);
next_sel <= "101";
when "101" =>
anode_reg <= "11011111";
digitout_reg <= digit_reg(23 downto 20);
next_sel <= "110";
when "110" =>
anode_reg <= "10111111";
digitout_reg <= digit_reg(27 downto 24);
next_sel <= "111";
when "111" =>
anode_reg <= "01111111";
digitout_reg <= digit_reg(31 downto 28);
next_sel <= "000";
when others =>
anode_reg <= "11111111";
digitout_reg <= "0000";
next_sel <= "000";
end case;
end if;
end process;
--Connect the Cathode values
with digitout_reg select
cathode_p <= "11000000"when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10011000" when "1001", -- 9
"10001000" when "1010", -- A
"10000011" when "1011", -- B
"11000110" when "1100", -- C
"10100001" when "1101", -- D
"10000110" when "1110", -- E
"10001110" when "1111"; -- F
--Connect the Anode values
anode_p <= anode_reg;
end behavioural; | apache-2.0 | 44e93d41e5b9c41db75f3037cb615165 | 0.534097 | 3.136472 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/uart/uart_top.vhd | 1 | 2,436 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.uart_constants.all;
entity uart_top is
port(
ctrl : in ctrl_t;
uart_rx : in std_logic;
uart_tx : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
received : out std_logic;
framing_error : out std_logic;
run_counter_dbg : out std_logic
);
end;
architecture rtl of uart_top is
--rx signals
signal rx_data_int : std_logic_vector(7 downto 0);
--tx signals
signal ready : std_logic;
signal send : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
--others
signal received_int : std_logic;
-- framing error
constant framing_error_extension_time : time := 2 sec;
constant framing_error_counter_max : integer := framing_error_extension_time / clk_period;
signal framing_error_counter : integer range 0 to framing_error_counter_max;
signal framing_error_raw : std_logic;
signal run_framing_error_counter : std_logic;
begin
uart_rx_1 : entity virtual_button_lib.uart_rx
port map (
ctrl => ctrl,
uart_rx => uart_rx,
new_data => received_int,
framing_error => framing_error_raw,
data => rx_data_int,
run_counter_dbg => run_counter_dbg
);
uart_tx_1 : entity virtual_button_lib.uart_tx
port map (
ctrl => ctrl,
send => send,
data => tx_data,
ready => ready,
uart_tx => uart_tx);
--Create a loopback for the UART
send <= received_int;
tx_data <= rx_data_int;
rx_data <= rx_data_int;
received <= received_int;
extend_framing_error : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
framing_error_counter <= 0;
framing_error <= '0';
elsif framing_error_raw = '1' then
run_framing_error_counter <= '1';
framing_error <= '1';
elsif framing_error_counter = framing_error_counter_max then
framing_error_counter <= 0;
framing_error <= '0';
run_framing_error_counter <= '0';
elsif run_framing_error_counter = '1' then
framing_error_counter <= framing_error_counter + 1;
end if;
end if;
end process;
end architecture;
| bsd-2-clause | 0df28d365bb8796d2b1247f630141c6a | 0.607143 | 3.445545 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/buttons/button_pkg.vhd | 1 | 2,259 | -- the logipi has only two discrete buttons. That is not very many.
-- The code in this folder emulates the presence of more buttons by translating
-- every character rxed by the UART into a strobe or a level change in a signal.
--
-- The this package exports a type called button_arr which holds whether a
-- button has been pressed (indicated by a single clock strobe) or whether a
-- button has been toggled (indicated by a level change). By examining a signal
-- of button_arr, it is thus possible to test for user input with expressions
-- like this: 'if buttons(a).pressed then....'
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package button_pkg is
-- Enumerate the characters that may be pressed
type lowercase_enum is
(a, b, c, d, e, f, g, h, i, j, k, l, m,
n, o, p, q, r, s, t, u, v, w, x, y, z);
type lowercase_to_ascii_arr is array (lowercase_enum'left to lowercase_enum'right)
of character;
-- There is no convenient direct way to get the ascii value of a lowercase,
-- thus we must map it individually
constant lowercase_to_ascii_mapping : lowercase_to_ascii_arr := (
a => 'a',
b => 'b',
c => 'c',
d => 'd',
e => 'e',
f => 'f',
g => 'g',
h => 'h',
i => 'i',
j => 'j',
k => 'k',
l => 'l',
m => 'm',
n => 'n',
o => 'o',
p => 'p',
q => 'q',
r => 'r',
s => 's',
t => 't',
u => 'u',
v => 'v',
w => 'w',
x => 'x',
y => 'y',
z => 'z');
-- Convenience type for representing the data received from UART.
subtype ascii_vector is std_logic_vector(7 downto 0);
-- Elaboration-only function.
-- Maps lowercase_enum into its corresponding ascii value.
function to_ascii_vector(char : in lowercase_enum) return ascii_vector;
type button_output is record
pressed : std_logic;
toggle : std_logic;
end record;
type button_arr is array (lowercase_enum'left to lowercase_enum'right)
of button_output;
end;
package body button_pkg is
function to_ascii_vector(char : in lowercase_enum) return ascii_vector is
begin
return
std_logic_vector(
to_unsigned(character'pos(lowercase_to_ascii_mapping(char)),
8));
end;
end;
| bsd-2-clause | 5fd3c6f82ce86d244f714448ad461d85 | 0.612218 | 3.376682 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/ovl_never_unknown_async_rtl.vhd | 1 | 3,422 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
-- $$ Special comments:
-- $$ 'reset_n' added to checker process sensitivity list to enable immediate check upon reset deactivation
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_never_unknown_async is
constant assert_name : string := "OVL_NEVER_UNKNOWN_ASYNC";
constant path : string := rtl'path_name;
signal reset_n : std_logic;
signal fatal_sig : std_logic;
signal test_expr_x01 : std_logic_vector(width - 1 downto 0);
shared variable error_count : natural;
begin
test_expr_x01 <= to_x01(test_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
-- No 2-state assertion for this checker.
fire(0) <= '0';
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_EXPLICIT_XCHECK)) generate
ovl_assert_p : process (reset_n, test_expr_x01)
begin
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif ((reset_n = '1') and ovl_is_x(test_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_EXPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
-- No coverage for this checker.
fire(2) <= '0';
end architecture rtl;
| mit | 4f9e4051b8272acc92a1e13257b6f73b | 0.429573 | 4.61186 | false | true | false | false |
scarter93/RSA-Encryption | mathpack.vhd | 1 | 50,004 | ------------------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93 Added RANDOM()
-- Version 0.6 Jose A. Torres 4/23/93 Renamed RANDOM as
-- UNIFORM. Modified
-- rights banner.
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--
-- commonly used constants
--
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
--attribute FOREIGN : string; -- predefined attribute in VHDL-1992
--
-- function declarations
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns integer FLOOR(X + 0.5) if X > 0;
-- return integer CEIL(X - 0.5) if X < 0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real);
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
-- function SRAND (seed: in integer ) return integer;
-- --
-- -- sets value of seed for sequence of
-- -- pseudo-random numbers.
-- -- It uses the foreign native C function srand().
-- attribute FOREIGN of SRAND : function is "C_NATIVE";
--
-- function RAND return integer;
-- --
-- -- returns an integer pseudo-random number with uniform distribution.
-- -- It uses the foreign native C function rand().
-- -- Seed for the sequence is initialized with the
-- -- SRAND() function and value of the seed is changed every
-- -- time SRAND() is called, but it is not visible.
-- -- The range of generated values is platform dependent.
-- attribute FOREIGN of RAND : function is "C_NATIVE";
--
-- function GET_RAND_MAX return integer;
-- --
-- -- returns the upper bound of the range of the
-- -- pseudo-random numbers generated by RAND().
-- -- The support for this function is platform dependent, and
-- -- it uses foreign native C functions or constants.
-- -- It may not be available in some platforms.
-- -- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- -- pseudo-random number distributed between 0 & 1.
-- attribute FOREIGN of GET_RAND_MAX : function is "C_NATIVE";
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
end MATH_REAL;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93
-- Version 0.6 Jose A. Torres 4/23/93 Added unary minus
-- and CONJ for polar
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_COMPLEX is
type COMPLEX is record RE, IM: real; end record;
type COMPLEX_VECTOR is array (integer range <>) of COMPLEX;
type COMPLEX_POLAR is record MAG: real; ARG: real; end record;
constant CBASE_1: complex := COMPLEX'(1.0, 0.0);
constant CBASE_j: complex := COMPLEX'(0.0, 1.0);
constant CZERO: complex := COMPLEX'(0.0, 0.0);
function CABS(Z: in complex ) return real;
-- returns absolute value (magnitude) of Z
function CARG(Z: in complex ) return real;
-- returns argument (angle) in radians of a complex number
function CMPLX(X: in real; Y: in real:= 0.0 ) return complex;
-- returns complex number X + iY
function "-" (Z: in complex ) return complex;
-- unary minus
function "-" (Z: in complex_polar ) return complex_polar;
-- unary minus
function CONJ (Z: in complex) return complex;
-- returns complex conjugate
function CONJ (Z: in complex_polar) return complex_polar;
-- returns complex conjugate
function CSQRT(Z: in complex ) return complex_vector;
-- returns square root of Z; 2 values
function CEXP(Z: in complex ) return complex;
-- returns e**Z
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar;
-- converts complex to complex_polar
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex;
-- converts complex_polar to complex
-- arithmetic operators
function "+" ( L: in complex; R: in complex ) return complex;
function "+" ( L: in complex_polar; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in complex ) return complex;
function "+" ( L: in complex; R: in complex_polar) return complex;
function "+" ( L: in real; R: in complex ) return complex;
function "+" ( L: in complex; R: in real ) return complex;
function "+" ( L: in real; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in real) return complex;
function "-" ( L: in complex; R: in complex ) return complex;
function "-" ( L: in complex_polar; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in complex ) return complex;
function "-" ( L: in complex; R: in complex_polar) return complex;
function "-" ( L: in real; R: in complex ) return complex;
function "-" ( L: in complex; R: in real ) return complex;
function "-" ( L: in real; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in real) return complex;
function "*" ( L: in complex; R: in complex ) return complex;
function "*" ( L: in complex_polar; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in complex ) return complex;
function "*" ( L: in complex; R: in complex_polar) return complex;
function "*" ( L: in real; R: in complex ) return complex;
function "*" ( L: in complex; R: in real ) return complex;
function "*" ( L: in real; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in real) return complex;
function "/" ( L: in complex; R: in complex ) return complex;
function "/" ( L: in complex_polar; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in complex ) return complex;
function "/" ( L: in complex; R: in complex_polar) return complex;
function "/" ( L: in real; R: in complex ) return complex;
function "/" ( L: in complex; R: in real ) return complex;
function "/" ( L: in real; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in real) return complex;
end MATH_COMPLEX;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code and algorithms for this package body comes from the
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators), Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
-------------------------------------------------------------
Library IEEE;
Package body MATH_REAL is
--
-- some constants for use in the package body only
--
constant Q_PI : real := MATH_PI/4.0;
constant HALF_PI : real := MATH_PI/2.0;
constant TWO_PI : real := MATH_PI*2.0;
constant MAX_ITER: integer := 27; -- max precision factor for cordic
--
-- some type declarations for cordic operations
--
constant KC : REAL := 6.0725293500888142e-01; -- constant for cordic
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to max_iter);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- auxiliary functions for cordic algorithms
--
function POWER_OF_2_SERIES (d : NATURAL_VECTOR; initial_value : REAL;
number_of_values : NATURAL) return REAL_VECTOR is
variable v : REAL_VECTOR (0 to number_of_values);
variable temp : REAL := initial_value;
variable flag : boolean := true;
begin
for i in 0 to number_of_values loop
v(i) := temp;
for p in d'range loop
if i = d(p) then
flag := false;
end if;
end loop;
if flag then
temp := temp/2.0;
end if;
flag := true;
end loop;
return v;
end POWER_OF_2_SERIES;
constant two_at_minus : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant epsilon : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( x0 : REAL;
y0 : REAL;
z0 : REAL;
n : NATURAL; -- precision factor
CORDIC_MODE : CORDIC_MODE_TYPE -- rotation (z -> 0)
-- or vectoring (y -> 0)
) return REAL_ARR_3 is
variable x : REAL := x0;
variable y : REAL := y0;
variable z : REAL := z0;
variable x_temp : REAL;
begin
if CORDIC_MODE = ROTATION then
for k in 0 to n loop
x_temp := x;
if ( z >= 0.0) then
x := x - y * two_at_minus(k);
y := y + x_temp * two_at_minus(k);
z := z - epsilon(k);
else
x := x + y * two_at_minus(k);
y := y - x_temp * two_at_minus(k);
z := z + epsilon(k);
end if;
end loop;
else
for k in 0 to n loop
x_temp := x;
if ( y < 0.0) then
x := x - y * two_at_minus(k);
y := y + x_temp * two_at_minus(k);
z := z - epsilon(k);
else
x := x + y * two_at_minus(k);
y := y - x_temp * two_at_minus(k);
z := z + epsilon(k);
end if;
end loop;
end if;
return REAL_ARR_3'(x, y, z);
end CORDIC;
--
-- non-trascendental functions
--
function SIGN (X: real ) return real is
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : real ) return real is
-- returns smallest integer value (as real) not less than X
-- No conversion to an integer type is expected, so truncate cannot
-- overflow for large arguments.
variable large: real := 1073741824.0;
type long is range -1073741824 to 1073741824;
-- 2**30 is longer than any single-precision mantissa
variable rd: real;
begin
if abs( X) >= large then
return X;
else
rd := real ( long( X));
if X > 0.0 then
if rd >= X then
return rd;
else
return rd + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if rd <= X then
return rd;
else
return rd - 1.0;
end if;
end if;
end if;
end CEIL;
function FLOOR (X : real ) return real is
-- returns largest integer value (as real) not greater than X
-- No conversion to an integer type is expected, so truncate
-- cannot overflow for large arguments.
--
variable large: real := 1073741824.0;
type long is range -1073741824 to 1073741824;
-- 2**30 is longer than any single-precision mantissa
variable rd: real;
begin
if abs( X ) >= large then
return X;
else
rd := real ( long( X));
if X > 0.0 then
if rd <= X then
return rd;
else
return rd - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if rd >= X then
return rd;
else
return rd + 1.0;
end if;
end if;
end if;
end FLOOR;
function ROUND (X : real ) return real is
-- returns integer FLOOR(X + 0.5) if X > 0;
-- return integer CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function FMAX (X, Y : real ) return real is
-- returns the algebraically larger of X and Y
begin
if X > Y then
return X;
else
return Y;
end if;
end FMAX;
function FMIN (X, Y : real ) return real is
-- returns the algebraically smaller of X and Y
begin
if X < Y then
return X;
else
return Y;
end if;
end FMIN;
--
-- Pseudo-random number generators
--
procedure UNIFORM(variable Seed1,Seed2:inout integer;variable X:out real) is
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
variable z, k: integer;
begin
k := Seed1/53668;
Seed1 := 40014 * (Seed1 - k * 53668) - k * 12211;
if Seed1 < 0 then
Seed1 := Seed1 + 2147483563;
end if;
k := Seed2/52774;
Seed2 := 40692 * (Seed2 - k * 52774) - k * 3791;
if Seed2 < 0 then
Seed2 := Seed2 + 2147483399;
end if;
z := Seed1 - Seed2;
if z < 1 then
z := z + 2147483562;
end if;
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SRAND (seed: in integer ) return integer is
--
-- sets value of seed for sequence of
-- pseudo-random numbers.
-- Returns the value of the seed.
-- It uses the foreign native C function srand().
begin
end SRAND;
function RAND return integer is
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the foreign native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
begin
end RAND;
function GET_RAND_MAX return integer is
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent, and
-- it uses foreign native C functions or constants.
-- It may not be available in some platforms.
-- Note: the value of (RAND / GET_RAND_MAX) is a
-- pseudo-random number distributed between 0 & 1.
begin
end GET_RAND_MAX;
--
-- trascendental and trigonometric functions
--
function SQRT (X : real ) return real is
-- returns square root of X; X >= 0
--
-- Computes square root using the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)];
--
constant inival: real := 1.5;
constant eps : real := 0.000001;
constant relative_err : real := eps*X;
variable oldval : real ;
variable newval : real ;
begin
-- check validity of argument
if ( X < 0.0 ) then
assert false report "X < 0 in SQRT(X)"
severity ERROR;
return (0.0);
end if;
-- get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0; -- return exact value
end if;
end if;
-- get the square root for general cases
oldval := inival;
newval := (X/oldval + oldval)/2.0;
while ( abs(newval -oldval) > relative_err ) loop
oldval := newval;
newval := (X/oldval + oldval)/2.0;
end loop;
return newval;
end SQRT;
function CBRT (X : real ) return real is
-- returns cube root of X
-- Computes square root using the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant inival: real := 1.5;
constant eps : real := 0.000001;
constant relative_err : real := eps*abs(X);
variable xlocal : real := X;
variable negative : boolean := X < 0.0;
variable oldval : real ;
variable newval : real ;
begin
-- compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- compute root for general cases
if negative then
xlocal := -X;
end if;
oldval := inival;
newval := (xlocal/(oldval*oldval) + 2.0*oldval)/3.0;
while ( abs(newval -oldval) > relative_err ) loop
oldval := newval;
newval :=(xlocal/(oldval*oldval) + 2.0*oldval)/3.0;
end loop;
if negative then
newval := -newval;
end if;
return newval;
end CBRT;
function "**" (X : integer; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0 ) and ( Y <= 0.0 ) then
assert false report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false report "X < 0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : real; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0.0 ) and ( Y <= 0.0 ) then
assert false report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0.0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false report "X < 0.0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (X));
end "**";
function EXP (X : real ) return real is
-- returns e**X; where e = MATH_E
--
-- This function computes the exponential using the following series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; x > 0
--
constant eps : real := 0.000001; -- precision criteria
variable reciprocal: boolean := x < 0.0;-- check sign of argument
variable xlocal : real := abs(x); -- use positive value
variable oldval: real ; -- following variables are
variable num: real ; -- used for series evaluation
variable count: integer ;
variable denom: real ;
variable newval: real ;
begin
-- compute value for special cases
if X = 0.0 then
return 1.0;
else
if X = 1.0 then
return MATH_E;
end if;
end if;
-- compute value for general cases
oldval := 1.0;
num := xlocal;
count := 1;
denom := 1.0;
newval:= oldval + num/denom;
while ( abs(newval - oldval) > eps ) loop
oldval := newval;
num := num*xlocal;
count := count +1;
denom := denom*(real(count));
newval := oldval + num/denom;
end loop;
if reciprocal then
newval := 1.0/newval;
end if;
return newval;
end EXP;
function LOG (X : real ) return real is
-- returns natural logarithm of X; X > 0
--
-- This function computes the exponential using the following series:
-- log(x) = 2[ (x-1)/(x+1) + (((x-1)/(x+1))**3)/3.0 + ...] ; x > 0
--
constant eps : real := 0.000001; -- precision criteria
variable xlocal: real ; -- following variables are
variable oldval: real ; -- used to evaluate the series
variable xlocalsqr: real ;
variable factor : real ;
variable count: integer ;
variable newval: real ;
begin
-- check validity of argument
if ( x <= 0.0 ) then
assert false report "X <= 0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- compute value for special cases
if ( X = 1.0 ) then
return 0.0;
else
if ( X = MATH_E ) then
return 1.0;
end if;
end if;
-- compute value for general cases
xlocal := (X - 1.0)/(X + 1.0);
oldval := xlocal;
xlocalsqr := xlocal*xlocal;
factor := xlocal*xlocalsqr;
count := 3;
newval := oldval + (factor/real(count));
while ( abs(newval - oldval) > eps ) loop
oldval := newval;
count := count +2;
factor := factor * xlocalsqr;
newval := oldval + factor/real(count);
end loop;
newval := newval * 2.0;
return newval;
end LOG;
function LOG (BASE: positive; X : real) return real is
-- returns logarithm base BASE of X; X > 0
begin
-- check validity of argument
if ( BASE <= 0 ) or ( x <= 0.0 ) then
assert false report "BASE <= 0 or X <= 0.0 in LOG(BASE, X)"
severity ERROR;
return(REAL'LOW);
end if;
-- compute the value
return ( LOG(X)/LOG(REAL(BASE)));
end LOG;
function SIN (X : real ) return real is
-- returns sin X; X in radians
variable n : INTEGER;
begin
if (x < 1.6 ) and (x > -1.6) then
return CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
n := INTEGER( x / HALF_PI );
case QUADRANT( n mod 4 ) is
when 0 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 1 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 2 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 3 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
end case;
end SIN;
function COS (x : REAL) return REAL is
-- returns cos X; X in radians
variable n : INTEGER;
begin
if (x < 1.6 ) and (x > -1.6) then
return CORDIC( KC, 0.0, x, 27, ROTATION)(0);
end if;
n := INTEGER( x / HALF_PI );
case QUADRANT( n mod 4 ) is
when 0 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 1 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
when 2 =>
return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0);
when 3 =>
return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1);
end case;
end COS;
function TAN (x : REAL) return REAL is
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
variable n : INTEGER := INTEGER( x / HALF_PI );
variable v : REAL_ARR_3 :=
CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION);
begin
if n mod 2 = 0 then
return v(1)/v(0);
else
return -v(0)/v(1);
end if;
end TAN;
function ASIN (x : real ) return real is
-- returns -PI/2 < asin X < PI/2; | X | <= 1
begin
if abs x > 1.0 then
assert false report "Out of range parameter passed to ASIN"
severity ERROR;
return x;
elsif abs x < 0.9 then
return atan(x/(sqrt(1.0 - x*x)));
elsif x > 0.0 then
return HALF_PI - atan(sqrt(1.0 - x*x)/x);
else
return - HALF_PI + atan((sqrt(1.0 - x*x))/x);
end if;
end ASIN;
function ACOS (x : REAL) return REAL is
-- returns 0 < acos X < PI; | X | <= 1
begin
if abs x > 1.0 then
assert false report "Out of range parameter passed to ACOS"
severity ERROR;
return x;
elsif abs x > 0.9 then
if x > 0.0 then
return atan(sqrt(1.0 - x*x)/x);
else
return MATH_PI - atan(sqrt(1.0 - x*x)/x);
end if;
else
return HALF_PI - atan(x/sqrt(1.0 - x*x));
end if;
end ACOS;
function ATAN (x : REAL) return REAL is
-- returns -PI/2 < atan X < PI/2
begin
return CORDIC( 1.0, x, 0.0, 27, VECTORING )(2);
end ATAN;
function ATAN2 (x : REAL; y : REAL) return REAL is
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
begin
if y = 0.0 then
if x = 0.0 then
assert false report "atan2(0.0, 0.0) is undetermined, returned 0,0"
severity NOTE;
return 0.0;
elsif x > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
elsif x > 0.0 then
return CORDIC( x, y, 0.0, 27, VECTORING )(2);
else
return MATH_PI + CORDIC( x, y, 0.0, 27, VECTORING )(2);
end if;
end ATAN2;
function SINH (X : real) return real is
-- hyperbolic sine; returns (e**X - e**(-X))/2
begin
return ( (EXP(X) - EXP(-X))/2.0 );
end SINH;
function COSH (X : real) return real is
-- hyperbolic cosine; returns (e**X + e**(-X))/2
begin
return ( (EXP(X) + EXP(-X))/2.0 );
end COSH;
function TANH (X : real) return real is
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
begin
return ( (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) );
end TANH;
function ASINH (X : real) return real is
-- returns ln( X + sqrt( X**2 + 1))
begin
return ( LOG( X + SQRT( X**2 + 1.0)) );
end ASINH;
function ACOSH (X : real) return real is
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
begin
if abs x >= 1.0 then
assert false report "Out of range parameter passed to ACOSH"
severity ERROR;
return x;
end if;
return ( LOG( X + SQRT( X**2 - 1.0)) );
end ACOSH;
function ATANH (X : real) return real is
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
begin
if abs x < 1.0 then
assert false report "Out of range parameter passed to ATANH"
severity ERROR;
return x;
end if;
return( LOG( (1.0+X)/(1.0-X) )/2.0 );
end ATANH;
end MATH_REAL;
-----------------------------------------------------------------
----
---- This source file may be used and distributed without restriction.
---- No declarations or definitions shall be included in this package.
---- This package cannot be sold or distributed for profit.
----
---- ****************************************************************
---- * *
---- * W A R N I N G *
---- * *
---- * This DRAFT version IS NOT endorsed or approved by IEEE *
---- * *
---- ****************************************************************
----
---- Title: PACKAGE BODY MATH_COMPLEX
----
---- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
---- which contains common complex constants and basic complex
---- functions and operations.
----
---- Author: IEEE VHDL Math Package Study Group
----
---- Notes:
---- The package body uses package IEEE.MATH_REAL
----
---- The package body shall be considered the formal definition of
---- the semantics of this package. Tool developers may choose to implement
---- the package body in the most efficient manner available to them.
----
---- Source code for this package body comes from the following
---- following sources:
---- IEEE VHDL Math Package Study Group participants,
---- U. of Mississippi, Mentor Graphics, Synopsys,
---- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
---- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
---- Random Number Generators, Handbook of Mathematical Functions
---- by Milton Abramowitz and Irene A. Stegun (Dover).
----
---- History:
---- Version 0.1 Jose A. Torres 4/23/93 First draft
---- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
----
---------------------------------------------------------------
--Library IEEE;
--
--Use IEEE.MATH_REAL.all; -- real trascendental operations
--
--Package body MATH_COMPLEX is
--
-- function CABS(Z: in complex ) return real is
-- -- returns absolute value (magnitude) of Z
-- variable ztemp : complex_polar;
-- begin
-- ztemp := COMPLEX_TO_POLAR(Z);
-- return ztemp.mag;
-- end CABS;
--
-- function CARG(Z: in complex ) return real is
-- -- returns argument (angle) in radians of a complex number
-- variable ztemp : complex_polar;
-- begin
-- ztemp := COMPLEX_TO_POLAR(Z);
-- return ztemp.arg;
-- end CARG;
--
-- function CMPLX(X: in real; Y: in real := 0.0 ) return complex is
-- -- returns complex number X + iY
-- begin
-- return COMPLEX'(X, Y);
-- end CMPLX;
--
-- function "-" (Z: in complex ) return complex is
-- -- unary minus; returns -x -jy for z= x + jy
-- begin
-- return COMPLEX'(-z.Re, -z.Im);
-- end "-";
--
-- function "-" (Z: in complex_polar ) return complex_polar is
-- -- unary minus; returns (z.mag, z.arg + MATH_PI)
-- begin
-- return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI);
-- end "-";
--
-- function CONJ (Z: in complex) return complex is
-- -- returns complex conjugate (x-jy for z = x+ jy)
-- begin
-- return COMPLEX'(z.Re, -z.Im);
-- end CONJ;
--
-- function CONJ (Z: in complex_polar) return complex_polar is
-- -- returns complex conjugate (z.mag, -z.arg)
-- begin
-- return COMPLEX_POLAR'(z.mag, -z.arg);
-- end CONJ;
--
-- function CSQRT(Z: in complex ) return complex_vector is
-- -- returns square root of Z; 2 values
-- variable ztemp : complex_polar;
-- variable zout : complex_vector (0 to 1);
-- variable temp : real;
-- begin
-- ztemp := COMPLEX_TO_POLAR(Z);
-- temp := SQRT(ztemp.mag);
-- zout(0).re := temp*COS(ztemp.arg/2.0);
-- zout(0).im := temp*SIN(ztemp.arg/2.0);
--
-- zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI);
-- zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI);
--
-- return zout;
-- end CSQRT;
--
-- function CEXP(Z: in complex ) return complex is
-- -- returns e**Z
-- begin
-- return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im));
-- end CEXP;
--
-- function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is
-- -- converts complex to complex_polar
-- begin
-- return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.re,z.im));
-- end COMPLEX_TO_POLAR;
--
-- function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is
-- -- converts complex_polar to complex
-- begin
-- return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) );
-- end POLAR_TO_COMPLEX;
--
--
-- --
-- -- arithmetic operators
-- --
--
-- function "+" ( L: in complex; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L.Re + R.Re, L.Im + R.Im);
-- end "+";
--
-- function "+" (L: in complex_polar; R: in complex_polar) return complex is
-- variable zL, zR : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im);
-- end "+";
--
-- function "+" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im);
-- end "+";
--
-- function "+" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im);
-- end "+";
--
-- function "+" ( L: in real; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L + R.Re, R.Im);
-- end "+";
--
-- function "+" ( L: in complex; R: in real ) return complex is
-- begin
-- return COMPLEX'(L.Re + R, L.Im);
-- end "+";
--
-- function "+" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L + zR.Re, zR.Im);
-- end "+";
--
-- function "+" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re + R, zL.Im);
-- end "+";
--
-- function "-" ( L: in complex; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L.Re - R.Re, L.Im - R.Im);
-- end "-";
--
-- function "-" ( L: in complex_polar; R: in complex_polar) return complex is
-- variable zL, zR : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im);
-- end "-";
--
-- function "-" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im);
-- end "-";
--
-- function "-" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im);
-- end "-";
--
-- function "-" ( L: in real; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L - R.Re, -1.0 * R.Im);
-- end "-";
--
-- function "-" ( L: in complex; R: in real ) return complex is
-- begin
-- return COMPLEX'(L.Re - R, L.Im);
-- end "-";
--
-- function "-" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L - zR.Re, -1.0*zR.Im);
-- end "-";
--
-- function "-" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re - R, zL.Im);
-- end "-";
--
-- function "*" ( L: in complex; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re);
-- end "*";
--
-- function "*" ( L: in complex_polar; R: in complex_polar) return complex is
-- variable zout : complex_polar;
-- begin
-- zout.mag := L.mag * R.mag;
-- zout.arg := L.arg + R.arg;
-- return POLAR_TO_COMPLEX(zout);
-- end "*";
--
-- function "*" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re);
-- end "*";
--
-- function "*" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re);
-- end "*";
--
-- function "*" ( L: in real; R: in complex ) return complex is
-- begin
-- return COMPLEX'(L * R.Re, L * R.Im);
-- end "*";
--
-- function "*" ( L: in complex; R: in real ) return complex is
-- begin
-- return COMPLEX'(L.Re * R, L.Im * R);
-- end "*";
--
-- function "*" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex;
-- begin
-- zR := POLAR_TO_COMPLEX( R );
-- return COMPLEX'(L * zR.Re, L * zR.Im);
-- end "*";
--
-- function "*" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex;
-- begin
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'(zL.Re * R, zL.Im * R);
-- end "*";
--
-- function "/" ( L: in complex; R: in complex ) return complex is
-- variable magrsq : REAL := R.Re ** 2 + R.Im ** 2;
-- begin
-- if (magrsq = 0.0) then
-- assert FALSE report "Attempt to divide by (0,0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq,
-- (L.Im * R.Re - L.Re * R.Im) / magrsq);
-- end if;
-- end "/";
--
-- function "/" ( L: in complex_polar; R: in complex_polar) return complex is
-- variable zout : complex_polar;
-- begin
-- if (R.mag = 0.0) then
-- assert FALSE report "Attempt to divide by (0,0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- zout.mag := L.mag/R.mag;
-- zout.arg := L.arg - R.arg;
-- return POLAR_TO_COMPLEX(zout);
-- end if;
-- end "/";
--
-- function "/" ( L: in complex_polar; R: in complex ) return complex is
-- variable zL : complex;
-- variable temp : REAL := R.Re ** 2 + R.Im ** 2;
-- begin
-- if (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- zL := POLAR_TO_COMPLEX( L );
-- return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp,
-- (zL.Im * R.Re - zL.Re * R.Im) / temp);
-- end if;
-- end "/";
--
-- function "/" ( L: in complex; R: in complex_polar) return complex is
-- variable zR : complex := POLAR_TO_COMPLEX( R );
-- variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
-- begin
-- if (R.mag = 0.0) or (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp,
-- (L.Im * zR.Re - L.Re * zR.Im) / temp);
-- end if;
-- end "/";
--
-- function "/" ( L: in real; R: in complex ) return complex is
-- variable temp : REAL := R.Re ** 2 + R.Im ** 2;
-- begin
-- if (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- temp := L / temp;
-- return COMPLEX'( temp * R.Re, -temp * R.Im );
-- end if;
-- end "/";
--
-- function "/" ( L: in complex; R: in real ) return complex is
-- begin
-- if (R = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'(L.Re / R, L.Im / R);
-- end if;
-- end "/";
--
-- function "/" ( L: in real; R: in complex_polar) return complex is
-- variable zR : complex := POLAR_TO_COMPLEX( R );
-- variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
-- begin
-- if (R.mag = 0.0) or (temp = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- temp := L / temp;
-- return COMPLEX'( temp * zR.Re, -temp * zR.Im );
-- end if;
-- end "/";
--
-- function "/" ( L: in complex_polar; R: in real) return complex is
-- variable zL : complex := POLAR_TO_COMPLEX( L );
-- begin
-- if (R = 0.0) then
-- assert FALSE report "Attempt to divide by (0.0,0.0)"
-- severity ERROR;
-- return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
-- else
-- return COMPLEX'(zL.Re / R, zL.Im / R);
-- end if;
-- end "/";
--end MATH_COMPLEX;
--
| mit | 56583c23babc3fc277f599cc8ad2ab9e | 0.538297 | 3.382992 | false | false | false | false |
jaruiz/light8080 | boards/de1/de1_top.vhdl | 1 | 10,933 | --##############################################################################
-- Light8080 MPU demo on Terasic's DE-1 board.
--##############################################################################
--
-- This is a minimal demo of the light8080 MPU wrapper targetting Terasic's DE-1
-- development board for Cyclone-2 FPGAs.
-- Since the demo uses little board resources other than the serial port it
-- should be easy to port it to other platforms.
--
-- The MPU entity contains a block of RAM that is used for both program and
-- data. The BRAM is initialized at synthesis time with a constant taken from
-- package 'obj_code_pkg'. This package can be built from an object code file
-- in Intel HEX format with utility '/tools/build_rom' included with this
-- project. There's an example of this in the TB makefiles.
--
-- This demo has been built from a generic template for designs targetting the
-- DE-1 development board. The entity defines all the inputs and outputs present
-- in the actual board, whether or not they are used in the design at hand.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Package that contains the program object code in VHDL constant format.
use work.obj_code_pkg.all;
-- Define the entity outputs as they are connected in the DE-1 development
-- board. Many of the outputs will be left unused in this demo.
entity DE1_TOP is
port (
-- ***** Clocks
clk_50MHz : in std_logic;
-- ***** Flash 4MB
flash_addr : out std_logic_vector(21 downto 0);
flash_data : in std_logic_vector(7 downto 0);
flash_oe_n : out std_logic;
flash_we_n : out std_logic;
flash_reset_n : out std_logic;
-- ***** SRAM 256K x 16
sram_addr : out std_logic_vector(17 downto 0);
sram_data : inout std_logic_vector(15 downto 0);
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
sram_we_n : out std_logic;
-- ***** RS-232
rxd : in std_logic;
txd : out std_logic;
-- ***** Switches and buttons
switches : in std_logic_vector(9 downto 0);
buttons : in std_logic_vector(3 downto 0);
-- ***** Quad 7-seg displays
hex0 : out std_logic_vector(0 to 6);
hex1 : out std_logic_vector(0 to 6);
hex2 : out std_logic_vector(0 to 6);
hex3 : out std_logic_vector(0 to 6);
-- ***** Leds
red_leds : out std_logic_vector(9 downto 0);
green_leds : out std_logic_vector(7 downto 0);
-- ***** SD Card
sd_data : in std_logic;
sd_cs : out std_logic;
sd_cmd : out std_logic;
sd_clk : out std_logic
);
end DE1_TOP;
architecture minimal of DE1_TOP is
--##############################################################################
-- MCU and immediate glue logic.
-- light8080 MCU signals -------------------------------------------------------
signal p1in : std_logic_vector(7 downto 0);
signal p2out : std_logic_vector(7 downto 0);
signal uart_txd : std_logic;
signal uart_rxd : std_logic;
signal extint : std_logic_vector(3 downto 0);
-- Signals for external SRAM synchronization -----------------------------------
signal sram_data_out : std_logic_vector(7 downto 0); -- sram output reg
signal sram_write : std_logic; -- sram we register
signal address_reg : std_logic_vector(15 downto 0); -- registered addr bus
--##############################################################################
-- On-board device interface signals.
-- Quad 7-segment display (non multiplexed) & LEDS -----------------------------
signal display_data : std_logic_vector(15 downto 0);
-- Clock & reset signals -------------------------------------------------------
signal clk_1hz : std_logic;
signal clk_master : std_logic;
signal reset : std_logic;
signal clk : std_logic;
signal counter_1hz : unsigned(25 downto 0);
-- SD control signals ----------------------------------------------------------
-- SD connector unused, unconnected
--## Functions #################################################################
-- Converts hex nibble to 7-segment (sinthesizable).
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
function nibble_to_7seg(nibble : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case nibble is
when X"0" => return "0000001";
when X"1" => return "1001111";
when X"2" => return "0010010";
when X"3" => return "0000110";
when X"4" => return "1001100";
when X"5" => return "0100100";
when X"6" => return "0100000";
when X"7" => return "0001111";
when X"8" => return "0000000";
when X"9" => return "0000100";
when X"a" => return "0001000";
when X"b" => return "1100000";
when X"c" => return "0110001";
when X"d" => return "1000010";
when X"e" => return "0110000";
when X"f" => return "0111000";
when others => return "0111111"; -- can't happen
end case;
end function nibble_to_7seg;
begin
-- MCU instantiation.
mcu: entity work.mcu80
generic map (
OBJ_CODE => work.obj_code_pkg.object_code,
UART_HARDWIRED => false, -- UART baud rate NOT run-time programmable.
UART_IRQ_LINE => 3, -- UART uses IRQ3 line of irq controller.
BAUD_RATE => 115200, -- UART baud rate.
CLOCK_FREQ => 125E6 -- Clock frequency in Hz.
)
port map (
clk => clk,
reset => reset,
p1_i => p1in,
p2_o => p2out,
extint_i => extint,
txd_o => uart_txd,
rxd_i => uart_rxd
);
-- Input port connected to switches for lack of better use
p1in <= switches(7 downto 0);
--##### Input ports ###########################################################
--##############################################################################
-- terasIC Cyclone II STARTER KIT BOARD
--##############################################################################
--##############################################################################
-- FLASH (flash is unused in this demo)
--##############################################################################
flash_addr <= (others => '0');
flash_we_n <= '1'; -- all enable signals inactive
flash_oe_n <= '1';
flash_reset_n <= '1';
--##############################################################################
-- SRAM (wired as 64K x 8)
-- The SRAM is unused in this demo.
--##############################################################################
-- These registera make the external, asynchronous SRAM behave like an
-- internal syncronous BRAM, except for the timing.
-- Since the SoC has no wait state capability, the SoC clock rate must
-- accomodate the SRAM timing -- including FPGA clock-to-output, RAM delays
-- and FPGA input setup and hold times. Setting up the synthesis constraints
-- is left to the user too.
sram_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
sram_addr <= "000000000000000000";
address_reg <= "0000000000000000";
sram_data_out <= X"00";
sram_write <= '0';
else
end if;
end if;
end process sram_registers;
sram_data(15 downto 8) <= "ZZZZZZZZ"; -- high byte unused
sram_data(7 downto 0) <= "ZZZZZZZZ" when sram_write='0' else sram_data_out;
-- (the X"ZZ" will physically be the read input data)
-- sram access controlled by WE_N
sram_oe_n <= '0';
sram_ce_n <= '0';
sram_we_n <= not sram_write;
sram_ub_n <= '1'; -- always disable
sram_lb_n <= '0';
--##############################################################################
-- RESET, CLOCK
--##############################################################################
-- Use button 0 as reset
reset <= not buttons(0);
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
process(clk_50MHz)
begin
if clk_50MHz'event and clk_50MHz='1' then
if reset = '1' then
clk_1hz <= '0';
counter_1hz <= (others => '0');
else
if to_integer(counter_1hz) = 50000000 then
counter_1hz <= (others => '0');
clk_1hz <= not clk_1hz;
else
counter_1hz <= counter_1hz + 1;
end if;
end if;
end if;
end process;
-- Master clock is external 50MHz oscillator
clk <= clk_50MHz;
--##############################################################################
-- LEDS, SWITCHES
--##############################################################################
-- Display the contents of an output port at the green leds bar
green_leds <= p2out;
-- Red leds unused except for 1-Hz clock
red_leds(9 downto 1) <= (others => '0');
red_leds(0) <= clk_1hz;
--##############################################################################
-- QUAD 7-SEGMENT DISPLAYS
--##############################################################################
-- Display the contents of the output port at the hex displays.
--display_data <= X"42" & switches(7 downto 0); --p2out & p1in;
display_data <= p2out & p1in;
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
hex3 <= nibble_to_7seg(display_data(15 downto 12));
hex2 <= nibble_to_7seg(display_data(11 downto 8));
hex1 <= nibble_to_7seg(display_data( 7 downto 4));
hex0 <= nibble_to_7seg(display_data( 3 downto 0));
--##############################################################################
-- SD card interface
--##############################################################################
-- SD card unused in this demo
sd_cs <= '0';
sd_cmd <= '0';
sd_clk <= '0';
--sd_in <= '0';
--##############################################################################
-- SERIAL
--##############################################################################
-- Txd & rxd connected straight to the SoC
txd <= uart_txd;
uart_rxd <= rxd;
end minimal;
| lgpl-2.1 | 401b5d4e424f7362e9b4f000081e6596 | 0.460532 | 4.357513 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Medium/test_bcd_1_adder.vhd | 2 | 5,259 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:06 08/14/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac3/test_bcd_1_adder.vhd
-- Project Name: prac3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: bcd_1_adder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY test_bcd_1_adder IS
END test_bcd_1_adder;
ARCHITECTURE behavior OF test_bcd_1_adder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_1_adder
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
C_IN : IN std_logic;
SUM : OUT std_logic_vector(3 downto 0);
C_OUT : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal C_IN : std_logic := '0';
--Outputs
signal SUM : std_logic_vector(3 downto 0);
signal C_OUT : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_1_adder PORT MAP (
A => A,
B => B,
C_IN => C_IN,
SUM => SUM,
C_OUT => C_OUT
);
-- Stimulus process
stim_proc: process begin
A <= (others => '0');
B <= (others => '0');
C_IN <= '0';
wait for 10ps;
for I in 0 to 7 loop
wait for 1ps;
for J in 0 to 7 loop
wait for 1ps;
for K in 0 to 1 loop
wait for 1ps;
--Black Box testing
--0 input
if (A = "0000" and B = "0000" and C_IN = '0') then
assert (sum = "0000") report "bad gate - stuck at 0S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 0C0" severity error;
elsif (A = "0000" and B = "0000" and C_IN = '1') then
assert (sum = "0001") report "bad gate - stuck at 0S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 0C1" severity error;
--less than 9
elsif (A = "0100" and B = "0001" and C_IN = '0') then
assert (sum = "0101") report "bad gate - stuck at less than 9S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at less than 9C0" severity error;
elsif (A = "0100" and B = "0001" and C_IN = '1') then
assert (sum = "0110") report "bad gate - stuck at less than 9S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at less than 9C1" severity error;
--At 9
elsif (A = "0101" and B = "0100" and C_IN = '0') then
assert (sum = "1001") report "bad gate - stuck at 9S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 9C0" severity error;
elsif (A = "0100" and B = "0100" and C_IN = '1') then
assert (sum = "1001") report "bad gate - stuck at 9S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 9C1" severity error;
--More than 9
elsif (A = "0111" and B = "0100" and C_IN = '0') then
assert (sum = "0111") report "bad gate - stuck at more than 9S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at more than 9C0" severity error;
elsif (A = "0111" and B = "0100" and C_IN = '1') then
assert (sum = "0010") report "bad gate - stuck at more than 9S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at more than 9C1" severity error;
--More than 7 + 9
elsif (A = "0111" and B = "1001" and C_IN = '0') then
assert (sum = "0110") report "bad gate - stuck at 7S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C0" severity error;
elsif (A = "0111" and B = "1001" and C_IN = '1') then
assert (sum = "0111") report "bad gate - stuck at 7S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C1" severity error;
--More than 8 + 9
elsif (A = "1000" and B = "1001" and C_IN = '0') then
assert (sum = "0111") report "bad gate - stuck at 7S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C0" severity error;
elsif (A = "1000" and B = "1001" and C_IN = '1') then
assert (sum = "1000") report "bad gate - stuck at 7S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C1" severity error;
end if;
C_IN <= NOT(C_IN);
end loop;
B <= B + '1';
end loop;
A <= A + '1';
end loop;
wait;
end process;
END;
| apache-2.0 | 4e1380783b17685c5f5b9583a9bac505 | 0.55657 | 3.19696 | false | true | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/DPU_array_matrix_multiplication_3/DPU_array_matrix_multiplication_3_tb.vhd | 1 | 2,986 | library ieee;
use ieee.std_logic_1164.all;
entity DPU_array_matrix_multiplication_3_tb is
end DPU_array_matrix_multiplication_3_tb;
architecture tb OF DPU_array_matrix_multiplication_3_tb is
-- Component Declaration for the Unit Under Test (UUT)
component DPU_array_matrix_multiplication_3
port(
A0 : IN std_logic_vector(3 downto 0);
A1 : IN std_logic_vector(3 downto 0);
A2 : IN std_logic_vector(3 downto 0);
B0 : IN std_logic_vector(3 downto 0);
B1 : IN std_logic_vector(3 downto 0);
B2 : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
clear: IN std_logic;
O0 : OUT std_logic_vector(9 downto 0);
O1 : OUT std_logic_vector(9 downto 0);
O2 : OUT std_logic_vector(9 downto 0);
O3 : OUT std_logic_vector(9 downto 0);
O4 : OUT std_logic_vector(9 downto 0);
O5 : OUT std_logic_vector(9 downto 0);
O6 : OUT std_logic_vector(9 downto 0);
O7 : OUT std_logic_vector(9 downto 0);
O8 : OUT std_logic_vector(9 downto 0)
);
end component;
signal A0 : std_logic_vector(3 downto 0) := (others => '0');
signal A1 : std_logic_vector(3 downto 0) := (others => '0');
signal A2 : std_logic_vector(3 downto 0) := (others => '0');
signal B0 : std_logic_vector(3 downto 0) := (others => '0');
signal B1 : std_logic_vector(3 downto 0) := (others => '0');
signal B2 : std_logic_vector(3 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal clear: std_logic := '0';
signal O0 : std_logic_vector(9 downto 0);
signal O1 : std_logic_vector(9 downto 0);
signal O2 : std_logic_vector(9 downto 0);
signal O3 : std_logic_vector(9 downto 0);
signal O4 : std_logic_vector(9 downto 0);
signal O5 : std_logic_vector(9 downto 0);
signal O6 : std_logic_vector(9 downto 0);
signal O7 : std_logic_vector(9 downto 0);
signal O8 : std_logic_vector(9 downto 0);
begin
uut: DPU_array_matrix_multiplication_3 port map(A0,A1,A2,B0,B1,B2,CLK,clear,O0,O1,O2,O3,O4,O5,O6,O7,O8);
process
begin
clear<='0';wait for 1 ps;
clear<='1';
wait;
end process;
process
begin
CLK<='1'; wait for 1 ps;
CLK<='0'; wait for 1 ps;
end process;
process
begin
wait for 2 ps;
A0<=x"1";
B0<=x"1";
wait for 2 ps;
A0<=x"2";
B0<=x"2";
wait for 2 ps;
A0<=x"3";
B0<=x"3";
wait for 2 ps;
A0<=x"0";
B0<=x"0";
wait;
end process;
process
begin
wait for 2 ps;
A1<=x"0";
B1<=x"0";
wait for 2 ps;
A1<=x"2";
B1<=x"2";
wait for 2 ps;
A1<=x"3";
B1<=x"3";
wait for 2 ps;
A1<=x"1";
B1<=x"1";
wait for 2 ps;
A1<=x"0";
B1<=x"0";
wait;
end process;
process
begin
wait for 2 ps;
A2<=x"0";
B2<=x"0";
wait for 4 ps;
A2<=x"3";
B2<=x"3";
wait for 2 ps;
A2<=x"1";
B2<=x"1";
wait for 2 ps;
A2<=x"2";
B2<=x"2";
wait for 2 ps;
A2<=x"0";
B2<=x"0";
wait;
end process;
end tb; | mit | a537b575f881a2b4ec910b1406066dfe | 0.577026 | 2.547782 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/midi/midi_ram.vhd | 1 | 2,974 | -- Ram entity for midi files. Mostly a fork from midi_ram.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity midi_ram is
generic(
queue_depth : positive;
queue_width : positive
);
port (
ctrl : in ctrl_t;
enqueue : in std_logic;
write_in_data : in std_logic_vector(queue_width - 1 downto 0);
-- the long expression is really (addr_length - 1 downto 0), but I couldn't
-- write that because VHDL prohibits addr_length from being defined by this
-- point :/
read_addr : in unsigned(integer(ceil(log2(real(queue_depth)))) - 1 downto 0);
read_out_data : out std_logic_vector(queue_width - 1 downto 0);
empty : out std_logic;
full : out std_logic;
contents_count : out natural range 0 to queue_depth
);
end;
architecture rtl of midi_ram is
constant addr_length : integer := integer(ceil(log2(real(queue_depth))));
constant data_width : integer := 8;
--ram signals
signal write_enable : std_logic;
signal next_write_addr : unsigned(addr_length - 1 downto 0) := (others => '0');
--
signal full_int : std_logic := '0';
signal empty_int : std_logic := '0';
signal contents_count_int : natural range 0 to queue_depth;
begin
ram_1 : entity virtual_button_lib.ram
generic map(
depth => queue_depth,
width => queue_width
)
port map (
ctrl => ctrl,
read_addr => read_addr,
next_write_addr => next_write_addr,
write_enable => write_enable,
write_in => write_in_data,
read_out => read_out_data);
calc_contents_count : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
-- the true part is needed because otherwise contents_count would be 0
-- when the fifo was full.
if full_int = '1' then
contents_count_int <= queue_depth;
else
contents_count_int <= natural(to_integer(next_write_addr));
end if;
end if;
end process;
full <= full_int;
empty <= '1' when contents_count_int = 0 else
'0';
contents_count <= contents_count_int;
write_enable <= '1' when full_int = '0' and enqueue = '1'
else '0';
--Allow a write to be performed, except when there is no more room
update_write_address : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
next_write_addr <= to_unsigned(0, next_write_addr'length);
full_int <= '0';
else
if enqueue = '1' and full_int = '0' then
next_write_addr <= next_write_addr + 1;
if next_write_addr + 1 = queue_depth then
full_int <= '1';
end if;
end if;
end if;
end if;
end process;
end;
| bsd-2-clause | 961292bdb73384a4f75c355a51ec0820 | 0.593813 | 3.519527 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/cpu.vhd | 3 | 6,045 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_pack.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity cpu is
PORT( CLK_I : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR( 7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
XM_WE : out STD_LOGIC;
XM_CE : out STD_LOGIC
);
end cpu;
architecture behavioral of cpu is
COMPONENT bin_to_7segment
PORT( CLK_I : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
SEG1 : OUT std_logic_vector(7 downto 1);
SEG2 : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT cpu_engine
PORT( CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0);
DAT_O : out std_logic_vector( 7 downto 0);
RST_I : in std_logic;
ACK_I : in std_logic;
ADR_O : out std_logic_vector(15 downto 0);
CYC_O : out std_logic;
STB_O : out std_logic;
TGA_O : out std_logic_vector(0 downto 0);
WE_O : out std_logic;
INT : in std_logic;
HALT : out std_logic;
-- debug signals
--
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT input_output
PORT( CLK_I : IN std_logic;
CYC_I : IN std_logic;
RST_O : OUT std_logic;
STB_I : IN std_logic;
ACK_O : OUT std_logic;
IO : IN std_logic;
WE_I : IN std_logic;
ADR_I : IN std_logic_vector(7 downto 0);
TEMP_SPO : IN std_logic;
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic;
SER_IN : IN std_logic;
SER_OUT : OUT std_logic;
SWITCH : IN std_logic_vector(9 downto 0);
LED : OUT std_logic_vector(7 downto 0);
IO_WDAT : IN std_logic_vector(7 downto 0);
IO_RDAT : OUT std_logic_vector(7 downto 0);
INT : OUT std_logic;
HALT : in std_logic
);
END COMPONENT;
signal CLR : std_logic;
signal ADR : std_logic_vector(15 downto 0);
signal CYC : std_logic;
signal STB : std_logic;
signal XM_STB : std_logic;
signal IO_STB : std_logic;
signal ACK : std_logic;
signal XM_ACK : std_logic;
signal IO_ACK : std_logic;
signal HALT : std_logic;
signal INT : std_logic;
signal IO : std_logic;
signal WE : std_logic;
signal IO_RDAT : std_logic_vector( 7 downto 0);
signal WDAT : std_logic_vector( 7 downto 0);
signal RDAT : std_logic_vector( 7 downto 0);
signal PC : std_logic_vector(15 downto 0);
signal Q_C_SX : std_logic_vector(1 downto 0);
signal Q_C_SY : std_logic_vector(3 downto 0);
signal Q_C_OP : std_logic_vector(4 downto 0);
signal Q_C_SA : std_logic_vector(4 downto 0);
signal Q_C_SMQ : std_logic;
signal Q_C_WE_RR : std_logic;
signal Q_C_WE_LL : std_logic;
signal Q_C_WE_SP : SP_OP;
signal Q_C_RR : std_logic_vector(15 downto 0);
signal Q_C_LL : std_logic_vector(15 downto 0);
signal Q_C_SP : std_logic_vector(15 downto 0);
signal Q_C_OPC : std_logic_vector( 7 downto 0);
signal Q_C_CAT : op_category;
signal Q_C_IMM : std_logic_vector(15 downto 0);
signal Q_C_CYC : cycle;
begin
SEG1(0) <= HALT;
XM_ADR <= ADR;
XM_WDAT <= WDAT;
XM_WE <= WE;
XM_STB <= STB and not IO;
IO_STB <= STB and IO;
XM_ACK <= XM_STB;
XM_CE <= CYC and not IO;
RDAT <= IO_RDAT when (IO = '1') else XM_RDAT;
ACK <= IO_ACK when (IO = '1') else XM_ACK;
seg7: bin_to_7segment
PORT MAP( CLK_I => CLK_I,
PC => PC,
SEG1 => SEG1(7 downto 1), -- SEG1(0) is HALT
SEG2 => SEG2
);
eng: cpu_engine
PORT MAP( CLK_I => CLK_I,
DAT_I => RDAT,
DAT_O => WDAT,
RST_I => CLR, -- SW-1 (RESET)
ACK_I => ACK,
CYC_O => CYC,
STB_O => STB,
ADR_O => ADR,
TGA_O(0) => IO,
WE_O => WE,
INT => INT,
HALT => HALT,
Q_PC => PC,
Q_OPC => Q_C_OPC,
Q_CAT => Q_C_CAT,
Q_IMM => Q_C_IMM,
Q_CYC => Q_C_CYC,
Q_SX => Q_C_SX,
Q_SY => Q_C_SY,
Q_OP => Q_C_OP,
Q_SA => Q_C_SA,
Q_SMQ => Q_C_SMQ,
Q_WE_RR => Q_C_WE_RR,
Q_WE_LL => Q_C_WE_LL,
Q_WE_SP => Q_C_WE_SP,
Q_RR => Q_C_RR,
Q_LL => Q_C_LL,
Q_SP => Q_C_SP
);
ino: input_output
PORT MAP( CLK_I => CLK_I,
CYC_I => CYC,
RST_O => CLR,
STB_I => IO_STB,
ACK_O => IO_ACK,
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
SER_IN => SER_IN,
SER_OUT => SER_OUT,
SWITCH => SWITCH,
LED => LED,
IO => IO,
WE_I => WE,
ADR_I => ADR(7 downto 0),
IO_RDAT => IO_RDAT,
IO_WDAT => WDAT,
INT => INT,
HALT => HALT
);
end behavioral;
| mit | 377d79acd8634a937ce35ca97d51aee0 | 0.532341 | 2.515605 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/scc_process1.vhd | 1 | 3,206 | -- Author: Osama G. Attia
-- email: ogamal [at] iastate dot edu
-- Create Date: 16:57:25 06/23/2014
-- Module Name: scc_kernel - Behavioral
-- Description: Read from the reachability queue
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity scc_process1 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
-- Queue pointers
reach_count : in std_logic_vector(63 downto 0); -- Number of nodes in reachability queue
reach_queue : in std_logic_vector(63 downto 0); -- Reach queue pointer (could be FW or BW reach queue)
-- Process 1 signals
p1_done : out std_logic;
-- p1_count : out unsigned(63 downto 0);
-- Process 1 req queue signals
p1_req_q_almost_full : in std_logic;
p1_req_q_wr_en : out std_logic;
p1_req_q_din : out std_logic_vector(63 downto 0)
);
end scc_process1;
architecture Behavioral of scc_process1 is
signal p1_offset : unsigned(63 downto 0);
-- signal count : unsigned(63 downto 0);
-- Helping signals
signal ae_id_x16 : unsigned(5 downto 0);
signal u_reach_queue : unsigned(63 downto 0);
signal u_reach_count : unsigned(63 downto 0);
signal read_pointer : unsigned(63 downto 0);
signal read_pointer_x8 : unsigned(63 downto 0);
begin
-- p1_count <= count;
ae_id_x16 <= unsigned("0" & ae_id & "000"); --------this is for 32 kernels, make this ae_id & "0000" for 64 kernels
u_reach_queue <= unsigned(reach_queue);
u_reach_count <= unsigned(reach_count);
read_pointer <= p1_offset + kernel_id + ae_id_x16;
read_pointer_x8 <= read_pointer(60 downto 0) & "000";
p1 : process(clk, rst)
begin
if rising_edge(clk) then
if (rst = '1') then
p1_done <= '0';
-- count <= (others => '0');
p1_offset <= (others => '0');
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
else
if (enable = '1') then
if (read_pointer < u_reach_count and p1_req_q_almost_full = '0') then
-- request reach_queue[p1_offset + kernel_id + ae_id]
p1_req_q_wr_en <= '1';
p1_req_q_din <= std_logic_vector(resize(u_reach_queue + read_pointer_x8, 64));
-- Increment nodes count and read offset
-- count <= count + 1;
p1_offset <= p1_offset + kernels_count;
else
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
if (p1_req_q_almost_full = '0') then
p1_done <= '1';
end if;
end if;
else
p1_done <= '0';
-- count <= (others => '0');
p1_offset <= (others => '0');
-- set the p1 request queue signals to default
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 1
end Behavioral;
| apache-2.0 | 82dbde53274aac81a31dbe9834873618 | 0.577979 | 2.865058 | false | false | false | false |
willtmwu/vhdlExamples | Finite State Machines/tast_fsm_v2_prac4.vhd | 1 | 2,610 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_fsm_v2_prac4 IS
END test_fsm_v2_prac4;
ARCHITECTURE behavior OF test_fsm_v2_prac4 IS
COMPONENT fsm_prac4
PORT(
X : IN std_logic;
RESET : IN std_logic;
clk100mhz : IN std_logic;
Z : OUT std_logic;
DEBUG_CHECK : OUT std_logic_vector (3 downto 0);
DEBUG_OUT : OUT std_logic_vector (3 downto 0)
);
END COMPONENT;
signal X : std_logic := '0';
signal RESET : std_logic := '0';
signal clk100mhz : std_logic := '0';
signal Z : std_logic;
signal DEBUG_CHECK : std_logic_vector(3 downto 0) := (others => '0');
signal DEBUG_OUT : std_logic_vector(3 downto 0) := (others => '0');
signal check_data_line : std_logic_vector (15 downto 0) := "0101110110011010";
signal check_data_match : std_logic_vector (15 downto 0) := "0000000000000000";
signal check_state_trans : std_logic_vector (19 downto 0) := "11010011101100011010";
constant clk100mhz_period : time := 10 ns;
signal full_check_state : std_logic_vector(31 downto 0) := (others => '0');
subtype counter_bit_int is integer range 0 to 31;
BEGIN
full_check_state(31 downto 16) <= check_data_line;
full_check_state(15 downto 0) <= check_data_match;
uut: fsm_prac4 PORT MAP (
X => X,
RESET => RESET,
clk100mhz => clk100mhz,
Z => Z,
DEBUG_CHECK => DEBUG_CHECK,
DEBUG_OUT => DEBUG_OUT
);
-- Clock process definitions
clk100mhz_process :process
begin
clk100mhz <= '0';
wait for clk100mhz_period/2;
clk100mhz <= '1';
wait for clk100mhz_period/2;
end process;
RESET <= '1';
-- Stimulus process
-- stim_proc: process
-- begin
-- RESET <= '0' ;
-- wait for clk100mhz_period*10;
-- RESET <= '1' ;
-- wait for clk100mhz_period*10;
--
-- FOR I in 19 downto 0 loop
-- wait until clk100mhz'event;
-- if clk100mhz = '1' then
-- X <= check_state_trans(I);
-- end if;
-- --assert ( Z = check_data_match(I) ) report "MATCH ERROR" severity error;
-- END loop;
-- wait until clk100mhz'event and clk100mhz = '1';
--
-- wait for clk100mhz_period*10;
-- wait;
-- end process;
tester : process (clk100mHz)
variable counter : counter_bit_int := 0;
begin
--wait until submitButton'event and submitButton = '1' ;
if (clk100mhz'event and clk100mhz = '1') then
if (counter >= 0) then
X <= full_check_state(counter);
counter := counter - 1;
else
counter := 31;
end if;
end if;
end process;
END;
| apache-2.0 | 4b2c3afa83f8ec5adc1c4fd9822a56b1 | 0.595785 | 3.003452 | false | false | false | false |
SDRG-UCT/RHINO_CALF | programming/blinky.vhd | 1 | 3,590 | --Simon Scott, 2011
--modified by Gordon Inggs, 2015
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM; --included because Xilinx Primitives are used
use UNISIM.VComponents.all;
entity blinky is
Port (
SYS_CLK_N : in STD_LOGIC; --System Clock Negative input port
SYS_CLK_P : in STD_LOGIC; --System Clock Positive input port
USER_LED : out STD_LOGIC_VECTOR(7 downto 0) --Output byte representing the 8 LEDs
);
end blinky;
architecture Behavioral of blinky is
--Declare signals
signal SYS_CLK_BUF : STD_LOGIC;
signal SYS_CLK_SLOW : STD_LOGIC;
signal SYS_CLK_FB : STD_LOGIC;
begin
--BUFG for SYS_CLOCK, the differential buffer for the System Clock
IBUFGDS_SYS_CLK: IBUFGDS
generic map
(
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE)
IOSTANDARD => "LVDS_25"
)
port map
(
I => SYS_CLK_P,
IB => SYS_CLK_N,
O => SYS_CLK_BUF
);
--PLL_BASE, the phase-lock loop
PLL_SYS_CLK : PLL_BASE
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN_PERIOD => 10.0,
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1, --Defined clock division
CLKFBOUT_MULT => 4,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.1
)
port map
(
CLKFBIN => SYS_CLK_FB,
CLKIN => SYS_CLK_BUF,
RST => '0',
CLKFBOUT => SYS_CLK_FB,
CLKOUT0 => SYS_CLK_SLOW, --The output used
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open
);
--Run each time clock changes state
DATAPATH: process(SYS_CLK_SLOW) --defining the LED behaviour as a stand alone process
variable led_status1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001"; --various variables used during the behaviour
variable led_status2 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
variable shift_dir : integer range 0 to 15 := 0;
variable count : integer := 0;
begin
if SYS_CLK_SLOW'event and SYS_CLK_SLOW = '1' then --each clock edge
count := count + 1; --a simple counter is used to sub-divide the clock, so the change in the LEDs is visible to the naked eye.
if count > 400000000 then
--Shift LEDs
USER_LED <= led_status1 or led_status2;
if shift_dir = 0 then
--Shift left
led_status1 := STD_LOGIC_VECTOR(signed(led_status1) sll 1); -- conversion to a STD_LOGIC_VECTOR is used to take advantage of the shifts
led_status2 := STD_LOGIC_VECTOR(signed(led_status2) srl 1);
else
--Shift right
led_status1 := STD_LOGIC_VECTOR(signed(led_status1) srl 1);
led_status2 := STD_LOGIC_VECTOR(signed(led_status2) sll 1);
end if;
--Reverse direction if necessary
if led_status1 = "10000000" then
shift_dir := 1;
elsif led_status1 = "00000001" then
shift_dir := 0;
end if;
count := 0;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 35d91e7e459f1075c7595f5954554656 | 0.615042 | 3.037225 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Advanced/led_bright.vhd | 1 | 1,581 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity led_bright is
PORT(
clk : IN STD_LOGIC;
masterReset : IN STD_LOGIC;
ready : IN STD_LOGIC;
accel_val : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pwm_out : OUT STD_LOGIC);
end led_bright;
architecture Behavioral of led_bright is
COMPONENT pwm
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
en : IN std_logic;
duty : IN std_logic_vector(7 downto 0);
pwm_out : OUT std_logic
);
END COMPONENT;
signal en : std_logic := '0';
signal duty : std_logic_vector(7 downto 0) := (others => '0');
signal clkEdge : std_logic := '0';
type DETECT_FSM is (WAITING, DELAY1);
signal DETECT_STATE : DETECT_FSM := WAITING;
begin
M1: pwm PORT MAP (clk, masterReset, en, duty, pwm_out);
duty <= accel_val;
--Control Ready and enable latching
process (masterReset, clk) begin
if (masterReset = '1') then
en <= '0';
clkEdge <= '0';
DETECT_STATE <= WAITING;
elsif ( clk'event and clk = '0') then
if(clkEdge = '0' and ready = '1') then
DETECT_STATE <= DELAY1;
en <= '1';
else
case DETECT_STATE is
when DELAY1 =>
DETECT_STATE <= WAITING;
when WAITING =>
en <= '0';
end case;
end if;
clkEdge <= ready;
end if;
end process;
end Behavioral;
| apache-2.0 | d7471391f6891091f672757e17ec62ca | 0.503479 | 3.634483 | false | false | false | false |
zambreno/RCL | parallelCyGraph/vhdl/process3.vhd | 1 | 2,567 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 3:
-- Read nodes from p2 response queue, request node CSR/Info
-- NOTE: (P2 response queue = P3 request queue + graphInfo)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity process3 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 3 information
p3_done : out std_logic;
p3_count : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count_2 : in unsigned(31 downto 0);
-- Process 3 req queue signals
p3_req_q_almost_full : in std_logic;
p3_req_q_wr_en : out std_logic;
p3_req_q_din : out std_logic_vector(63 downto 0);
p3_req_q_full : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end entity ; -- process3
architecture arch of process3 is
signal count : unsigned (31 downto 0);
begin
p3_count <= count;
p3 : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p3_done <= '0';
count <= (others => '0');
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
else
if (started = '1') then
-- Got process 2 response
if (p3_req_q_almost_full = '0' and mc_rsp_push = '1' and mc_rsp_rdctl(7 downto 0) = x"02") then
-- request graphInfo + Neigh ID
p3_req_q_wr_en <= '1';
p3_req_q_din <= std_logic_vector(resize(8 * unsigned(mc_rsp_data(31 downto 0)) + unsigned(graphInfo), 64));
count <= count + 1;
else
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
end if;
-- Process 3 is done if process 2 is done and count = p2_count_2
if (p2_done = '1' and count = p2_count_2) then
p3_done <= '1';
end if;
else
p3_done <= '0';
count <= (others => '0');
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 3
end architecture; -- arch | apache-2.0 | 7fdceb4c75889e23264d170ed309889f | 0.550448 | 2.820879 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/DFF_PC/DFF_PC.vhd | 1 | 876 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DFF_PC is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
preset : in STD_LOGIC;
clear : in STD_LOGIC;
Q : out STD_LOGIC;
Qnot : out STD_LOGIC);
end DFF_PC;
architecture DFF_PC_arch of DFF_PC is
--signal S1,S2,S3,S4,S5,S6,S7,S8,S9,S10 : STD_LOGIC;
begin
process (CLK, clear, preset)
begin
if clear='0' then
Q <= '0';
elsif preset='0' then
Q <= '1';
elsif (CLK'event and CLK='1') then
Q <= D;
Qnot <= not D;
end if;
end process;
-- S1 <= NOT D;
-- S2 <= D NAND CLK;
-- S3 <= S1 NAND CLK;
-- S4 <= (preset NAND S2) NAND S5;
-- S5 <= (clear NAND S3) NAND S4;
-- S6 <= NOT S1;
-- S7 <= S4 NAND S6;
-- S8 <= S5 NAND S6;
-- S9 <= (preset NAND S7) NAND S10;
-- S10 <= (clear NAND S8) NAND S9;
-- Q <= S9;
-- Qnot <= S10;
end DFF_PC_arch; | mit | 1ba6b55d05019987b71a6c86a8352e91 | 0.539954 | 2.348525 | false | false | false | false |
scarter93/RSA-Encryption | testpy/me_tb_template.vhd | 1 | 1,960 | -- Entity name: modular_exponentiation_tb
-- Author: Luis Gallet, Jacob Barnett
-- Contact: [email protected], [email protected]
-- Date: ${DATE}
-- Description:
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
entity modular_exponentiation_tb is
end entity;
architecture test of modular_exponentiation_tb is
-- define the ALU compontent to be tested
component modular_exponentiation is
generic(
WIDTH_IN : integer := ${DATA_WIDTH}
);
port( N : in unsigned(WIDTH_IN-1 downto 0); --Number
Exp : in unsigned(WIDTH_IN-1 downto 0); --Exponent
M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
--latch_in: in std_logic;
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0) --Output
--C : out std_logic
);
end component;
CONSTANT WIDTH_IN : integer := ${DATA_WIDTH};
CONSTANT clk_period : time := 1 ns;
Signal M_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
Signal N_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
Signal Exp_in : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal latch_in : std_logic := '0';
Signal clk : std_logic := '0';
Signal reset_t : std_logic := '0';
Signal C_out : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
--signal c_out : std_logic;
Begin
-- device under test
dut: modular_exponentiation
generic map(WIDTH_IN => WIDTH_IN)
PORT MAP( N => N_in,
Exp => Exp_in,
M => M_in,
--latch_in => latch_in,
clk => clk,
reset => reset_t,
C => C_out
);
-- process for clock
clk_process : Process
Begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_process: process
Begin
reset_t <= '1';
wait for 1 * clk_period;
reset_t <= '0';
wait for 1 * clk_period;
${TEST_BODY}
wait;
end process;
end;
| mit | c7888460b57cfef7d15a4d9a6a71aaeb | 0.646939 | 2.681259 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/cygraph_process2.vhd | 1 | 5,680 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 2:
-- Read p1 response, get start, end address
-- request neighbors id from graphData
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity process2 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 2 information
p2_done : out std_logic;
p2_busy : out std_logic;
p2_count_1 : out unsigned(31 downto 0);
p2_count_2 : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphData : in std_logic_vector(63 downto 0);
-- Process 1 information
p1_done : in std_logic;
p1_count : in unsigned(31 downto 0);
-- Process 1 response queue signals
p1_rsp_q_rd_en : in std_logic;
p1_rsp_q_rd_enb : out std_logic;
p1_rsp_q_dout : in std_logic_vector(63 downto 0);
p1_rsp_q_valid : in std_logic;
p1_rsp_q_empty : in std_logic;
-- Process 2 request queue signals
p2_req_q_almost_full : in std_logic;
p2_req_q_wr_en : out std_logic;
p2_req_q_din : out std_logic_vector(63 downto 0)
);
end entity ; -- process2
architecture arch of process2 is
type state_type is (s0, s1, s2, s3);
signal p2_state : state_type;
signal done_out : std_logic;
signal count_1 : unsigned(31 downto 0);
signal count_2 : unsigned(31 downto 0);
signal start_index : unsigned(31 downto 0);
signal neigh_count : unsigned(30 downto 0);
signal busy : std_logic;
signal rd_offset : unsigned(31 downto 0);
begin
-- assign count signals
p2_count_1 <= count_1;
p2_count_2 <= count_2;
-- assign p2_done signal
p2_done <= done_out;
--p2_done <= '1' when started = '1' and p1_done = '1' and busy = '0' and p1_count = count_1 else '0';
p2_busy <= busy;
p2: process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p2_state <= s0;
done_out <= '0';
busy <= '0';
count_1 <= (others => '0');
count_2 <= (others => '0');
start_index <= (others => '0');
neigh_count <= (others => '0');
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
else
p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * start_index, 64));
if (started = '1') then
case (p2_state) is
-- Start:
when s0 =>
-- If p1_rsp_q NOT empty, pop, go to s1
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
-- if p1_rsp_q empty, keep waiting
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
-- Reset Signals
p2_req_q_wr_en <= '0';
-- Request a neighbor
when s1 =>
-- There at least one neighbor to request
if (p1_rsp_q_valid = '1' and or_reduce(p1_rsp_q_dout(31 downto 1)) /= '0') then
-- Save start index and neighbors count, go to s2
start_index <= unsigned(p1_rsp_q_dout(63 downto 32));
neigh_count <= unsigned(p1_rsp_q_dout(31 downto 1));
p2_state <= s2;
-- Reset Signals
p1_rsp_q_rd_enb <= '0';
-- No neighbors to request
elsif (p1_rsp_q_valid = '1') then
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
-- Data isn't ready yet, keep waiting in s1
else
p2_state <= s1;
-- reset signals
p1_rsp_q_rd_enb <= '0';
end if;
-- Reset Signals
p2_req_q_wr_en <= '0';
-- Request more neighbors
when s2 =>
-- There at least one neighbor to request
if (neigh_count /= 0) then
-- p2_req_q is ready, request a neighbor
if (p2_req_q_almost_full = '0') then
p2_req_q_wr_en <= '1';
count_2 <= count_2 + 1;
start_index <= start_index + 1;
neigh_count <= neigh_count - 1;
p2_state <= s2;
-- Reset signals
p1_rsp_q_rd_enb <= '0';
-- p2_req_q is NOT ready (i.e. full)
else
-- Go to s2
p2_state <= s2;
-- Reset Signals
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
end if;
-- No neighbors to request
else
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
p2_req_q_wr_en <= '0';
end if;
-- Uknown state
when others =>
-- Reset Signals
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_state <= s0;
end case;
if (p1_done = '1' and count_1 >= p1_count and p2_state = s0 and neigh_count = 0 and p1_rsp_q_valid = '0' and p1_rsp_q_empty = '1') then
done_out <= '1';
else
done_out <= '0';
end if;
else
-- reset everything
p2_state <= s0;
done_out <= '0';
busy <= '0';
count_1 <= (others => '0');
count_2 <= (others => '0');
start_index <= (others => '0');
neigh_count <= (others => '0');
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
end if; -- end if started
end if; -- end if rst
end if; -- end if clk
end process; -- p2
end architecture; -- arch
| apache-2.0 | a6364ad57c19782554ae8a73fd2c5a96 | 0.519894 | 2.556256 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_1/testbench_adder.vhdl | 1 | 1,360 | -- testbench_adder
-- A suite of tests for an 8-bit adder.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity testbench_adder is
end entity;
architecture behaviorial of testbench_adder is
component adder is
generic(n: integer);
port(
x: in std_logic_vector(n-1 downto 0);
y: in std_logic_vector(n-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(n-1 downto 0);
cout: out std_logic
);
end component;
signal x, y, s: std_logic_vector(7 downto 0);
signal cin, cout: std_logic;
begin
uut: adder
generic map(n => 8)
port map(x => x, y => y, s => s, cin => cin, cout => cout);
test_process: process
begin
cin <= '0';
x <= "00000000";
y <= "00000000";
wait for 10 ns;
cin <= '0';
x <= "11111111";
y <= "00000001";
wait for 10 ns;
cin <= '1';
x <= "11101011";
y <= "01010001";
wait for 10 ns;
cin <= '0';
x <= "11111100";
y <= "11000001";
wait for 10 ns;
cin <= '1';
x <= "11111011";
y <= "00100001";
wait for 10 ns;
cin <= '0';
x <= "01111111";
y <= "00000001";
wait for 10 ns;
end process;
end;
| unlicense | 8f7d76f3f53b5e2aa6f6283b733ff1f9 | 0.477206 | 3.685637 | false | true | false | false |
tommylommykins/logipi-midi-player | tb/spi/mock_spi_master.vhd | 1 | 2,314 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mock_spi_master is
port (
frequency : in integer;
cpol : in integer;
cpha : in integer;
send : in boolean;
force_cs_low : in boolean;
ready : out boolean;
data : in std_logic_vector(7 downto 0);
cs_n : out std_logic := '1';
sclk : out std_logic; -- initialized elsewhere
mosi : out std_logic := '0'
);
end entity mock_spi_master;
----------------------------------------------------------------------------------------------------
architecture behavioural of mock_spi_master is
signal bit_time : time;
signal duty_time : time;
signal clk_is_base : boolean := true;
signal desired_cs_n : std_logic := '1';
begin
bit_time <= 1 sec / frequency;
duty_time <= bit_time / 2;
sender : process is
begin
ready <= true;
wait on send;
ready <= false;
desired_cs_n <= '0';
for bit_index in 7 downto 0 loop --send MSB first.
for duty_period in 0 to 1 loop
if duty_period = 0 then
if cpha = 0 then
mosi <= data(bit_index);
end if;
--deliberately desynchronize clk and data to make effect of cpha more apparant.
wait for duty_time * 0.1;
clk_is_base <= true;
wait for duty_time * 0.9;
else
if cpha = 1 then
mosi <= data(bit_index);
end if;
wait for duty_time * 0.1;
clk_is_base <= false;
wait for duty_time * 0.9;
end if;
end loop;
end loop;
--implement porch if at end of msg.
if force_cs_low then
wait for duty_time * 0.5;
end if;
desired_cs_n <= '1';
clk_is_base <= true;
mosi <= '0';
end process sender;
calc_sclk : process (cpol, clk_is_base) is
begin
if cpol = 0 then
if clk_is_base then
sclk <= '0';
else
sclk <= '1';
end if;
else
if clk_is_base then
sclk <= '1';
else
sclk <= '0';
end if;
end if;
end process calc_sclk;
calc_cs_n : process (force_cs_low, desired_cs_n) is
begin
if force_cs_low then
cs_n <= '0';
else
cs_n <= desired_cs_n;
end if;
end process;
end;
| bsd-2-clause | 77db313009bc07daf19b06ff28e8d940 | 0.510804 | 3.576507 | false | false | false | false |
jmgc/myhdl-numeric | vhdl/numeric_std_additions.vhdl | 2 | 94,283 | ------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.numeric_std_additions.all;
-- (this package is independant of "std_logic_1164_additions")
-- Last Modified: $Date: 2010/09/22 18:33:32 $
-- RCS ID: $Id: numeric_std_additions.vhdl,v 1.10 2010/09/22 18:33:32 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package numeric_std_additions is
-- Make these a subtype of "signed" and "unsigned" for compatability
-- type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
-- type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
subtype UNRESOLVED_UNSIGNED is UNSIGNED;
subtype UNRESOLVED_SIGNED is SIGNED;
-- alias U_UNSIGNED is UNRESOLVED_UNSIGNED;
-- alias U_SIGNED is UNRESOLVED_SIGNED;
subtype U_UNSIGNED is UNSIGNED;
subtype U_SIGNED is SIGNED;
-- Id: A.3R
function "+"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.3 where R is a one bit UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.4R
function "+"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.4 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.4 where L is bit 0 of a non-negative
-- SIGNED
-- Id: A.9R
function "-"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.10R
function "-"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: M.2B
-- %%% function "?=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic;
function \?=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- Id: M.3B
-- %%% function "?=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic;
function \?=\ (L, R : SIGNED) return STD_ULOGIC;
function \?/=\ (L, R : SIGNED) return STD_ULOGIC;
function \?>\ (L, R : SIGNED) return STD_ULOGIC;
function \?>=\ (L, R : SIGNED) return STD_ULOGIC;
function \?<\ (L, R : SIGNED) return STD_ULOGIC;
function \?<=\ (L, R : SIGNED) return STD_ULOGIC;
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
-- Result subtype: std_ulogic
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Overloaded functions from "std_logic_1164"
function To_X01 (s : UNSIGNED) return UNSIGNED;
function To_X01 (s : SIGNED) return SIGNED;
function To_X01Z (s : UNSIGNED) return UNSIGNED;
function To_X01Z (s : SIGNED) return SIGNED;
function To_UX01 (s : UNSIGNED) return UNSIGNED;
function To_UX01 (s : SIGNED) return SIGNED;
function Is_X (s : UNSIGNED) return BOOLEAN;
function Is_X (s : SIGNED) return BOOLEAN;
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit funcitons, using the local ">" operator
function maximum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l, r : SIGNED) -- inputs
return SIGNED;
function minimum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l, r : SIGNED) -- inputs
return SIGNED;
function maximum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function maximum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function minimum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function minimum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function maximum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
function minimum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
-- Finds the first "Y" in the input string. Returns an integer index
-- into that string. If "Y" does not exist in the string, then the
-- "find_rightmost" returns arg'low -1, and "find_leftmost" returns -1
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
alias TO_U_UNSIGNED is
TO_UNRESOLVED_UNSIGNED[NATURAL, NATURAL return UNRESOLVED_UNSIGNED];
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
alias TO_U_SIGNED is
TO_UNRESOLVED_SIGNED[NATURAL, NATURAL return UNRESOLVED_SIGNED];
-- L.15
function "and" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.16
function "and" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.17
function "or" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.18
function "or" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.19
function "nand" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.20
function "nand" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.21
function "nor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.22
function "nor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.23
function "xor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.24
function "xor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.25
function "xnor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.26
function "xnor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.27
function "and" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.28
function "and" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.29
function "or" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.30
function "or" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.31
function "nand" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.32
function "nand" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.33
function "nor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.34
function "nor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.35
function "xor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.36
function "xor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.37
function "xnor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.38
function "xnor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- %%% remove 12 functions (old syntax)
function and_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
function and_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( l : SIGNED ) RETURN std_ulogic;
-- function "nand" ( l : SIGNED ) RETURN std_ulogic;
-- function "or" ( l : SIGNED ) RETURN std_ulogic;
-- function "nor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : SIGNED ) RETURN std_ulogic;
-- function "and" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nand" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "or" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : UNSIGNED ) RETURN std_ulogic;
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- string functions
-------------------------------------------------------------------
function to_string (value : UNSIGNED) return STRING;
function to_string (value : SIGNED) return STRING;
-- explicitly defined operations
alias to_bstring is to_string [UNSIGNED return STRING];
alias to_bstring is to_string [SIGNED return STRING];
alias to_binary_string is to_string [UNSIGNED return STRING];
alias to_binary_string is to_string [SIGNED return STRING];
function to_ostring (value : UNSIGNED) return STRING;
function to_ostring (value : SIGNED) return STRING;
alias to_octal_string is to_ostring [UNSIGNED return STRING];
alias to_octal_string is to_ostring [SIGNED return STRING];
function to_hstring (value : UNSIGNED) return STRING;
function to_hstring (value : SIGNED) return STRING;
alias to_hex_string is to_hstring [UNSIGNED return STRING];
alias to_hex_string is to_hstring [SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNSIGNED);
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNSIGNED];
alias BREAD is READ [LINE, SIGNED];
alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNSIGNED];
alias BINARY_READ is READ [LINE, SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out SIGNED);
alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNSIGNED];
alias OCTAL_READ is OREAD [LINE, SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out SIGNED);
alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNSIGNED];
alias HEX_READ is HREAD [LINE, SIGNED];
alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
end package numeric_std_additions;
package body numeric_std_additions is
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
function MAX (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end function MAX;
-- Id: A.3R
function "+"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4R
function "+"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.9R
function "-"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10R
function "-"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - |
);
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ ( l, r : STD_ULOGIC ) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: UNSIGNED) return std_ulogic is
-- end function "?=";
-- Id: M.3B
function \?=\ (L, R: SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: signed) return std_ulogic is
-- end function "?=";
-- Id: C.75
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_UNSIGNED(L, R'length), R);
end function \?=\;
-- Id: C.76
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_SIGNED(L, R'length), R);
end function \?=\;
-- Id: C.77
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?=\ (L, TO_UNSIGNED(R, L'length));
end function \?=\;
-- Id: C.78
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?=\ (L, TO_SIGNED(R, L'length));
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?/=";
function \?/=\ (L, R : SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?/=";
-- Id: C.75
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_UNSIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.76
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_SIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.77
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?/=\ (L, TO_UNSIGNED(R, L'length));
end function \?/=\;
-- Id: C.78
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?/=\ (L, TO_SIGNED(R, L'length));
end function \?/=\;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>";
-- Id: C.57
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_UNSIGNED(L, R'length), R);
end function \?>\;
-- Id: C.58
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_SIGNED(L, R'length),R);
end function \?>\;
-- Id: C.59
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>\ (L, TO_UNSIGNED(R, L'length));
end function \?>\;
-- Id: C.60
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>\ (L, TO_SIGNED(R, L'length));
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_UNSIGNED(L, R'length), R);
end function \?>=\;
-- Id: C.64
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_SIGNED(L, R'length),R);
end function \?>=\;
-- Id: C.65
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>=\ (L, TO_UNSIGNED(R, L'length));
end function \?>=\;
-- Id: C.66
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>=\ (L, TO_SIGNED(R, L'length));
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<";
-- Id: C.57
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_UNSIGNED(L, R'length), R);
end function \?<\;
-- Id: C.58
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_SIGNED(L, R'length),R);
end function \?<\;
-- Id: C.59
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<\ (L, TO_UNSIGNED(R, L'length));
end function \?<\;
-- Id: C.60
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<\ (L, TO_SIGNED(R, L'length));
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<=";
-- Id: C.63
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_UNSIGNED(L, R'length), R);
end function \?<=\;
-- Id: C.64
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_SIGNED(L, R'length),R);
end function \?<=\;
-- Id: C.65
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<=\ (L, TO_UNSIGNED(R, L'length));
end function \?<=\;
-- Id: C.66
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<=\ (L, TO_SIGNED(R, L'length));
end function \?<=\;
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
-- begin LCS-2006-120
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- These functions are in std_logic_1164 and are defined for
-- std_logic_vector. They are overloaded here.
function To_X01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01Z ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_X01Z ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_UX01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function To_UX01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-----------------------------------------------------------------------------
-- New/updated functions for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit functions, using the local ">" operator
-- UNSIGNED output
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- signed output
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- UNSIGNED output
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- signed output
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(to_unsigned (arg, size));
end function TO_UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(to_signed (arg, size));
end function TO_UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
-- Performs the boolean operation on every bit in the vector
-- L.15
function "and" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.16
function "and" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.17
function "or" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.18
function "or" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.19
function "nand" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.20
function "nand" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.21
function "nor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.22
function "nor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.23
function "xor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.24
function "xor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.25
function "xnor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.26
function "xnor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-- L.27
function "and" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.28
function "and" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.29
function "or" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.30
function "or" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.31
function "nand" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.32
function "nand" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.33
function "nor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.34
function "nor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.35
function "xor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.36
function "xor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.37
function "xnor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.38
function "xnor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
--------------------------------------------------------------------------
-- Reduction operations
--------------------------------------------------------------------------
-- %%% Remove the following 12 funcitons (old syntax)
function and_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return and_reduce (UNSIGNED ( l ));
end function and_reduce;
function and_reduce ( l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '1'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "and" (BUS_int(BUS_int'right),BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "and" (Upper, Lower);
end if;
end if;
return Result;
end function and_reduce;
function nand_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce ( l ));
end function nand_reduce;
function nand_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce (l ));
end function nand_reduce;
function or_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return or_reduce (UNSIGNED ( l ));
end function or_reduce;
function or_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "or" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "or" (Upper, Lower);
end if;
end if;
return Result;
end function or_reduce;
function nor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function nor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function xor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return xor_reduce (UNSIGNED ( l ));
end function xor_reduce;
function xor_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "xor" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "xor" (Upper, Lower);
end if;
end if;
return Result;
end function xor_reduce;
function xnor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
function xnor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% Replace the above with the following 12 functions (New syntax)
-- function "and" ( l : SIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "and" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "nand" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "nand" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "or" ( l : SIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "or" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "nor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "nor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "xor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xnor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- function "xnor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- TO_STRING
-------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
function to_string (value : UNSIGNED) return STRING is
alias ivalue : UNSIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_string (value : SIGNED) return STRING is
alias ivalue : SIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_hstring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value(value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value (value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_hstring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-----------------------------------------------------------------------------
-- Read and Write routines
-----------------------------------------------------------------------------
-- Routines copied from the "std_logic_1164_additions" package
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
good := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
-- purpose: or reduction
function or_reduce (
arg : STD_ULOGIC_VECTOR)
return STD_ULOGIC is
variable uarg : UNSIGNED (arg'range);
begin
uarg := unsigned(arg);
return or_reduce (uarg);
end function or_reduce;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
-- End copied code.
procedure READ (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- rtl_synthesis on
-- pragma synthesis_on
end package body numeric_std_additions;
| lgpl-2.1 | 6403953714d180982fab460ba8c14c2a | 0.543088 | 3.722775 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod01_sv_for_vhdlers/SystemVerilog_for_VHDL_Engineers_Primer/primer_examples/assignments/blocking_non_blocking/multadd.vhd | 1 | 1,131 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY multadd_vhdl IS
PORT(
a : IN std_logic_vector ( 7 DOWNTO 0 );
b : IN std_logic_vector ( 7 DOWNTO 0 );
c : IN std_logic_vector ( 7 DOWNTO 0 );
d : IN std_logic_vector ( 7 DOWNTO 0 );
clk : IN std_logic;
rst_n : IN std_logic;
mulsum : OUT std_logic_vector ( 16 DOWNTO 0 )
);
-- Declarations
END multadd_vhdl ;
--
ARCHITECTURE rtl OF multadd_vhdl IS
shared variable ab : std_logic_vector (15 downto 0) ;
shared variable cd : std_logic_vector( 15 downto 0) ;
shared variable ab_cd : std_logic_vector(16 downto 0);
BEGIN
mul_add_logic : process ( A , B, C, D)
begin
ab := A * B;
cd := C * D;
ab_cd := ("0"&ab) + ("0"&cd);
end process;
mul_add_reg : process (clk)
begin
if rst_n = '0' then
mulsum <= "00000000000000000";
elsif clk'event and clk = '1' then
mulsum <= ab_cd;
end if;
end process;
END ARCHITECTURE rtl;
| mit | 257d6a247538dced8a51d56ea58f4f43 | 0.551724 | 3.194915 | false | false | false | false |
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