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asicguy/gplgpu | hdl/sim_lib/hardcopyiv_pcie_hip_components.vhd | 1 | 71,800 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package HARDCOPYIV_PCIE_HIP_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function alpha_tolower (given_string : string) return string;
-- GENERIC utility functions END
--
-- hardcopyiv_pciehip_pciexp_dcfiforam
--
COMPONENT hardcopyiv_pciehip_pciexp_dcfiforam
GENERIC (
addr_width : INTEGER := 4;
data_width : INTEGER := 32
);
PORT (
data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
wrclock : IN STD_LOGIC;
rdclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiv_hssi_pcie_hip
--
COMPONENT hardcopyiv_hssi_pcie_hip
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrpl : VitalDelayType01 := DefpropDelay01;
tipd_bistscanen : VitalDelayType01 := DefpropDelay01;
tipd_bistscanin : VitalDelayType01 := DefpropDelay01;
tipd_bisttesten : VitalDelayType01 := DefpropDelay01;
tipd_coreclkin : VitalDelayType01 := DefpropDelay01;
tipd_corecrst : VitalDelayType01 := DefpropDelay01;
tipd_corepor : VitalDelayType01 := DefpropDelay01;
tipd_corerst : VitalDelayType01 := DefpropDelay01;
tipd_coresrst : VitalDelayType01 := DefpropDelay01;
tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cplpending : VitalDelayType01 := DefpropDelay01;
tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01;
tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01;
tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01;
tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01;
tipd_dlreqwake : VitalDelayType01 := DefpropDelay01;
tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01;
tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01;
tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01;
tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01;
tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmirden : VitalDelayType01 := DefpropDelay01;
tipd_lmiwren : VitalDelayType01 := DefpropDelay01;
tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanen : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanin : VitalDelayType01 := DefpropDelay01;
tipd_pclkcentral : VitalDelayType01 := DefpropDelay01;
tipd_pclkch0 : VitalDelayType01 := DefpropDelay01;
tipd_phyrst : VitalDelayType01 := DefpropDelay01;
tipd_physrst : VitalDelayType01 := DefpropDelay01;
tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pldclk : VitalDelayType01 := DefpropDelay01;
tipd_pldrst : VitalDelayType01 := DefpropDelay01;
tipd_pldsrst : VitalDelayType01 := DefpropDelay01;
tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanen : VitalDelayType01 := DefpropDelay01;
tipd_scanmoden : VitalDelayType01 := DefpropDelay01;
tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappintasts : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmevent : VitalDelayType01 := DefpropDelay01;
tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01;
tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01;
tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_type : STRING := "hardcopyiv_hssi_pcie_hip";
advanced_errors : STRING := "false";
allow_rx_valid_empty : STRING := "false"; -- july3,2008
bar0_64bit_mem_space : STRING := "true";
bar0_io_space : STRING := "false";
bar0_prefetchable : STRING := "true";
bar0_size_mask : INTEGER := 32;
bar1_64bit_mem_space : STRING := "false";
bar1_io_space : STRING := "false";
bar1_prefetchable : STRING := "false";
bar1_size_mask : INTEGER := 4;
bar2_64bit_mem_space : STRING := "false";
bar2_io_space : STRING := "false";
bar2_prefetchable : STRING := "false";
bar2_size_mask : INTEGER := 4;
bar3_64bit_mem_space : STRING := "false";
bar3_io_space : STRING := "false";
bar3_prefetchable : STRING := "false";
bar3_size_mask : INTEGER := 4;
bar4_64bit_mem_space : STRING := "false";
bar4_io_space : STRING := "false";
bar4_prefetchable : STRING := "false";
bar4_size_mask : INTEGER := 4;
bar5_64bit_mem_space : STRING := "false";
bar5_io_space : STRING := "false";
bar5_prefetchable : STRING := "false";
bar5_size_mask : INTEGER := 4;
bar_io_window_size : STRING := "NONE";
bar_prefetchable : INTEGER := 0;
base_address : INTEGER := 0;
bridge_port_ssid_support : STRING := "false";
bridge_port_vga_enable : STRING := "false";
bypass_cdc : STRING := "false";
bypass_tl : STRING := "false";
class_code : INTEGER := 16711680;
completion_timeout : STRING := "ABCD";
core_clk_divider : INTEGER := 1;
core_clk_source : STRING := "PLL_FIXED_CLK";
credit_buffer_allocation_aux : STRING := "BALANCED";
deemphasis_enable : STRING := "false";
device_address : INTEGER := 0;
device_id : INTEGER := 1;
device_number : INTEGER := 0;
diffclock_nfts_count : INTEGER := 128;
disable_async_l2_logic : STRING := "false"; -- july2,2008
disable_cdc_clk_ppm : STRING := "true";
disable_device_number_mismatch : STRING := "false";
disable_link_x2_support : STRING := "false";
disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
dll_active_report_support : STRING := "false";
ei_delay_powerdown_count : INTEGER := 10;
eie_before_nfts_count : INTEGER := 4;
enable_adapter_half_rate_mode : STRING := "false";
enable_ch0_pclk_out : STRING := "false";
enable_completion_timeout_disable : STRING := "true";
enable_coreclk_out_half_rate : STRING := "false";
enable_d1pm_support : STRING := "false";
enable_d2pm_support : STRING := "false";
enable_ecrc_check : STRING := "false";
enable_ecrc_gen : STRING := "false";
enable_function_msi_support : STRING := "true";
enable_function_msix_support : STRING := "false";
enable_gen2_core : STRING := "true";
enable_hip_x1_loopback : STRING := "false";
enable_l1_aspm : STRING := "false";
enable_msi_64bit_addressing : STRING := "true";
enable_msi_masking : STRING := "false";
enable_rcv0buf_a_we : STRING := "true";
enable_rcv0buf_b_re : STRING := "true";
enable_rcv0buf_output_regs : STRING := "false";
enable_rcv1buf_a_we : STRING := "true";
enable_rcv1buf_b_re : STRING := "true";
enable_rcv1buf_output_regs : STRING := "false";
enable_retrybuf_a_we : STRING := "true";
enable_retrybuf_b_re : STRING := "true";
enable_retrybuf_ecc : STRING := "false"; -- ww12
enable_retrybuf_output_regs : STRING := "false";
enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx0buf_ecc : STRING := "false"; -- ww12
enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx1buf_ecc : STRING := "false"; -- ww12
enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx_buffer_checking : STRING := "false";
enable_rx_ei_l0s_exit_refined : STRING := "false";
enable_rx_reordering : STRING := "true";
enable_slot_register : STRING := "false";
endpoint_l0_latency : INTEGER := 0;
endpoint_l1_latency : INTEGER := 0;
expansion_base_address_register : INTEGER := 0;
extend_tag_field : STRING := "false";
fc_init_timer : INTEGER := 1024;
flow_control_timeout_count : INTEGER := 200;
flow_control_update_count : INTEGER := 30;
gen2_diffclock_nfts_count : INTEGER := 255;
gen2_lane_rate_mode : STRING := "false";
gen2_sameclock_nfts_count : INTEGER := 255;
hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
iei_logic : STRING := "IEI_IIIS";
indicator : INTEGER := 7;
l01_entry_latency : INTEGER := 31;
l0_exit_latency_diffclock : INTEGER := 6;
l0_exit_latency_sameclock : INTEGER := 6;
l1_exit_latency_diffclock : INTEGER := 0;
l1_exit_latency_sameclock : INTEGER := 0;
lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000";
low_priority_vc : INTEGER := 0;
max_link_width : INTEGER := 4;
max_payload_size : INTEGER := 2;
maximum_current : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
millisecond_cycle_count : INTEGER := 0;
mram_bist_settings : STRING := "";
msi_function_count : INTEGER := 2;
msix_pba_bir : INTEGER := 0;
msix_pba_offset : INTEGER := 0;
msix_table_bir : INTEGER := 0;
msix_table_offset : INTEGER := 0;
msix_table_size : INTEGER := 0;
no_command_completed : STRING := "true";
no_soft_reset : STRING := "false";
pcie_mode : STRING := "SHARED_MODE";
pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
port_link_number : INTEGER := 1;
port_address : INTEGER := 0;
register_pipe_signals : STRING := "false";
retry_buffer_last_active_address : INTEGER := 2047;
retry_buffer_memory_settings : INTEGER := 0;
revision_id : INTEGER := 1;
rx0_adap_fifo_full_value : INTEGER := 9;
rx1_adap_fifo_full_value : INTEGER := 9;
rx_cdc_full_value : INTEGER := 12;
rx_idl_os_count : INTEGER := 0;
rx_ptr0_nonposted_dpram_max : INTEGER := 0;
rx_ptr0_nonposted_dpram_min : INTEGER := 0;
rx_ptr0_posted_dpram_max : INTEGER := 0;
rx_ptr0_posted_dpram_min : INTEGER := 0;
rx_ptr1_nonposted_dpram_max : INTEGER := 0;
rx_ptr1_nonposted_dpram_min : INTEGER := 0;
rx_ptr1_posted_dpram_max : INTEGER := 0;
rx_ptr1_posted_dpram_min : INTEGER := 0;
sameclock_nfts_count : INTEGER := 128;
single_rx_detect : INTEGER := 0;
skp_os_schedule_count : INTEGER := 0;
slot_number : INTEGER := 0;
slot_power_limit : INTEGER := 0;
slot_power_scale : INTEGER := 0;
ssid : INTEGER := 0;
ssvid : INTEGER := 0;
subsystem_device_id : INTEGER := 1;
subsystem_vendor_id : INTEGER := 4466;
surprise_down_error_support : STRING := "false";
tx0_adap_fifo_full_value : INTEGER := 11;
tx1_adap_fifo_full_value : INTEGER := 11;
tx_cdc_full_value : INTEGER := 12;
tx_cdc_stop_dummy_full_value : INTEGER := 11;
use_crc_forwarding : STRING := "false";
vc0_clk_enable : STRING := "true";
vc0_rx_buffer_memory_settings : INTEGER := 0;
vc0_rx_flow_ctrl_compl_data : INTEGER := 448;
vc0_rx_flow_ctrl_compl_header : INTEGER := 112;
vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc0_rx_flow_ctrl_posted_data : INTEGER := 360;
vc0_rx_flow_ctrl_posted_header : INTEGER := 50;
vc1_clk_enable : STRING := "false";
vc1_rx_buffer_memory_settings : INTEGER := 0;
vc1_rx_flow_ctrl_compl_data : INTEGER := 448;
vc1_rx_flow_ctrl_compl_header : INTEGER := 112;
vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc1_rx_flow_ctrl_posted_data : INTEGER := 360;
vc1_rx_flow_ctrl_posted_header : INTEGER := 50;
vc_arbitration : INTEGER := 1;
vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
vendor_id : INTEGER := 4466
);
PORT (
bistenrcv0 : IN STD_LOGIC := '0';
bistenrcv1 : IN STD_LOGIC := '0';
bistenrpl : IN STD_LOGIC := '0';
bistscanen : IN STD_LOGIC := '0';
bistscanin : IN STD_LOGIC := '0';
bisttesten : IN STD_LOGIC := '0';
coreclkin : IN STD_LOGIC := '0';
corecrst : IN STD_LOGIC := '0';
corepor : IN STD_LOGIC := '0';
corerst : IN STD_LOGIC := '0';
coresrst : IN STD_LOGIC := '0';
cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
cplpending : IN STD_LOGIC := '0';
dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0');
dlaspmcr0 : IN STD_LOGIC := '0';
dlcomclkreg : IN STD_LOGIC := '0';
dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0');
dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlinhdllp : IN STD_LOGIC := '1';
dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlrequpfc : IN STD_LOGIC := '0';
dlreqwake : IN STD_LOGIC := '0';
dlrxecrcchk : IN STD_LOGIC := '0';
dlsndupfc : IN STD_LOGIC := '0';
dltxcfgextsy : IN STD_LOGIC := '0';
dltxreqpm : IN STD_LOGIC := '0';
dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0');
lmirden : IN STD_LOGIC := '0';
lmiwren : IN STD_LOGIC := '0';
mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
mramhiptestenable : IN STD_LOGIC := '0';
mramregscanen : IN STD_LOGIC := '0';
mramregscanin : IN STD_LOGIC := '0';
pclkcentral : IN STD_LOGIC := '0';
pclkch0 : IN STD_LOGIC := '0';
phyrst : IN STD_LOGIC := '0';
physrst : IN STD_LOGIC := '0';
phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
pldclk : IN STD_LOGIC := '0';
pldrst : IN STD_LOGIC := '0';
pldsrst : IN STD_LOGIC := '0';
pllfixedclk : IN STD_LOGIC := '0';
rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxmaskvc0 : IN STD_LOGIC := '0';
rxmaskvc1 : IN STD_LOGIC := '0';
rxreadyvc0 : IN STD_LOGIC := '0';
rxreadyvc1 : IN STD_LOGIC := '0';
rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
scanen : IN STD_LOGIC := '0';
scanmoden : IN STD_LOGIC := '0';
swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0');
tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappintasts : IN STD_LOGIC := '0';
tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappmsireq : IN STD_LOGIC := '0';
tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpmauxpwr : IN STD_LOGIC := '0';
tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
tlpmetocr : IN STD_LOGIC := '0';
tlpmevent : IN STD_LOGIC := '0';
tlslotclkcfg : IN STD_LOGIC := '0';
txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txeopvc00 : IN STD_LOGIC := '0';
txeopvc01 : IN STD_LOGIC := '0';
txeopvc10 : IN STD_LOGIC := '0';
txeopvc11 : IN STD_LOGIC := '0';
txerrvc0 : IN STD_LOGIC := '0';
txerrvc1 : IN STD_LOGIC := '0';
txsopvc00 : IN STD_LOGIC := '0';
txsopvc01 : IN STD_LOGIC := '0';
txsopvc10 : IN STD_LOGIC := '0';
txsopvc11 : IN STD_LOGIC := '0';
txvalidvc0 : IN STD_LOGIC := '0';
txvalidvc1 : IN STD_LOGIC := '0';
bistdonearcv0 : OUT STD_LOGIC;
bistdonearcv1 : OUT STD_LOGIC;
bistdonearpl : OUT STD_LOGIC;
bistdonebrcv0 : OUT STD_LOGIC;
bistdonebrcv1 : OUT STD_LOGIC;
bistdonebrpl : OUT STD_LOGIC;
bistpassrcv0 : OUT STD_LOGIC;
bistpassrcv1 : OUT STD_LOGIC;
bistpassrpl : OUT STD_LOGIC;
bistscanoutrcv0 : OUT STD_LOGIC;
bistscanoutrcv1 : OUT STD_LOGIC;
bistscanoutrpl : OUT STD_LOGIC;
clrrxpath : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataenablen : OUT STD_LOGIC;
derrcorextrcv0 : OUT STD_LOGIC;
derrcorextrcv1 : OUT STD_LOGIC;
derrcorextrpl : OUT STD_LOGIC;
derrrpl : OUT STD_LOGIC;
dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dlackrequpfc : OUT STD_LOGIC;
dlacksndupfc : OUT STD_LOGIC;
dlcurrentdeemp : OUT STD_LOGIC;
dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dldllreq : OUT STD_LOGIC;
dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlerrphy : OUT STD_LOGIC;
dllinkautobdwstatus : OUT STD_LOGIC;
dllinkbdwmngstatus : OUT STD_LOGIC;
dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlrpbufemp : OUT STD_LOGIC;
dlrstentercompbit : OUT STD_LOGIC;
dlrsttxmarginfield : OUT STD_LOGIC;
dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
dlrxvalpm : OUT STD_LOGIC;
dltxackpm : OUT STD_LOGIC;
dlup : OUT STD_LOGIC;
dlupexit : OUT STD_LOGIC;
dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC;
dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
ev128ns : OUT STD_LOGIC;
ev1us : OUT STD_LOGIC;
extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0);
gen2rate : OUT STD_LOGIC;
gen2rategnd : OUT STD_LOGIC;
hotrstexit : OUT STD_LOGIC;
intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
l2exit : OUT STD_LOGIC;
laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
linkup : OUT STD_LOGIC;
lmiack : OUT STD_LOGIC;
lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
ltssml0state : OUT STD_LOGIC;
mramregscanout : OUT STD_LOGIC;
powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0);
resetstatus : OUT STD_LOGIC;
rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxeopvc00 : OUT STD_LOGIC;
rxeopvc01 : OUT STD_LOGIC;
rxeopvc10 : OUT STD_LOGIC;
rxeopvc11 : OUT STD_LOGIC;
rxerrvc0 : OUT STD_LOGIC;
rxerrvc1 : OUT STD_LOGIC;
rxfifoemptyvc0 : OUT STD_LOGIC;
rxfifoemptyvc1 : OUT STD_LOGIC;
rxfifofullvc0 : OUT STD_LOGIC;
rxfifofullvc1 : OUT STD_LOGIC;
rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxsopvc00 : OUT STD_LOGIC;
rxsopvc01 : OUT STD_LOGIC;
rxsopvc10 : OUT STD_LOGIC;
rxsopvc11 : OUT STD_LOGIC;
rxvalidvc0 : OUT STD_LOGIC;
rxvalidvc1 : OUT STD_LOGIC;
r2cerr0ext : OUT STD_LOGIC;
serrout : OUT STD_LOGIC;
successspeednegoint : OUT STD_LOGIC;
swdnwake : OUT STD_LOGIC;
swuphotrst : OUT STD_LOGIC;
testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
tlappintaack : OUT STD_LOGIC;
tlappmsiack : OUT STD_LOGIC;
tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
tlcfgctlwr : OUT STD_LOGIC;
tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0);
tlcfgstswr : OUT STD_LOGIC;
tlpmetosr : OUT STD_LOGIC;
txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txfifoemptyvc0 : OUT STD_LOGIC;
txfifoemptyvc1 : OUT STD_LOGIC;
txfifofullvc0 : OUT STD_LOGIC;
txfifofullvc1 : OUT STD_LOGIC;
txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
txreadyvc0 : OUT STD_LOGIC;
txreadyvc1 : OUT STD_LOGIC;
wakeoen : OUT STD_LOGIC
);
END COMPONENT;
end hardcopyiv_pcie_hip_components;
package body HARDCOPYIV_PCIE_HIP_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
end HARDCOPYIV_PCIE_HIP_COMPONENTS;
| gpl-3.0 | 3ed9f7f9966a86fd809b85139792f22f | 0.522841 | 4.297343 | false | false | false | false |
google/myelin-acorn-electron-hardware | standalone_cartridge_programmer/cpld/tristate_everything.vhd | 1 | 1,502 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity standalone_programmer is
Port (
-- cartridge address
cart_nINFC,
cart_nINFD,
cart_ROMQA : out std_logic;
cart_A : out std_logic_vector (13 downto 0);
-- cartridge data
cart_D : inout std_logic_vector(7 downto 0);
-- cartridge clock and memory control
cart_PHI0,
cart_16MHZ,
cart_RnW,
cart_nOE,
cart_nOE2 : out std_logic;
-- avr SPI signals
avr_MOSI,
avr_SCK,
cpld_SS : in std_logic;
avr_MISO : out std_logic
);
end standalone_programmer;
architecture Behavioural of standalone_programmer is
begin
cart_nINFC <= 'Z';
cart_nINFD <= 'Z';
cart_ROMQA <= 'Z';
cart_A <= "ZZZZZZZZZZZZZZ";
cart_D <= "ZZZZZZZZ";
cart_PHI0 <= 'Z';
cart_16MHZ <= 'Z';
cart_RnW <= 'Z';
cart_nOE <= 'Z';
cart_nOE2 <= 'Z';
avr_MISO <= 'Z';
end Behavioural;
| apache-2.0 | 1bdeac0487d2190bd614ef55625daa6c | 0.663116 | 3.390519 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiigx_hssi_components.vhd | 1 | 66,300 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package STRATIXIIGX_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- stratixiigx_hssi_refclk_divider
--
COMPONENT stratixiigx_hssi_refclk_divider
GENERIC (
enable_divider : STRING := "true";
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
refclk_coupling_termination : STRING := "dc_coupling_external_termination"; -- new in 5.1 SP1
dprio_config_mode : INTEGER := 0; -- 6.1
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
inclk : IN STD_LOGIC;
dprioin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
--
-- stratixiigx_hssi_cmu_clock_divider
--
COMPONENT stratixiigx_hssi_cmu_clock_divider
GENERIC (
inclk_select : integer := 0;
use_vco_bypass : string := "false";
use_digital_refclk_post_divider : string := "false";
use_coreclk_out_post_divider : string := "false";
divide_by : integer := 4;
enable_refclk_out : string := "true";
enable_pclk_x8_out : string := "false";
select_neighbor_pclk : string := "false";
coreclk_out_gated_by_quad_reset: string := "false";
select_refclk_dig : string := "false";
dprio_config_mode : INTEGER := 0; -- 6.1
tipd_clk : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pclkin : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayArrayType01(29 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_powerdn : VitalDelayType01 := DefPropDelay01;
tipd_quadreset : VitalDelayType01 := DefPropDelay01;
tipd_refclkdig : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanshift : VitalDelayType01 := DefPropDelay01;
tipd_scanmode : VitalDelayType01 := DefPropDelay01;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_clk_coreclkout : VitalDelayType01 := DefPropDelay01;
tpd_clk_pclkx8out : VitalDelayType01 := DefPropDelay01;
tpd_pclkin_coreclkout : VitalDelayType01 := DefPropDelay01;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_digitalrefclkout_phase_shift : INTEGER := 0;
sim_pclkx8out_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
pclkin : IN STD_LOGIC := '0';
dprioin : IN STD_LOGIC_VECTOR(29 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN STD_LOGIC := '1';
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
refclkdig : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS => '0');
scanshift : IN STD_LOGIC := '0';
scanmode : IN STD_LOGIC := '0';
vcobypassin : IN STD_LOGIC := '0';
analogrefclkout : OUT STD_LOGIC;
analogfastrefclkout : OUT STD_LOGIC;
digitalrefclkout : OUT STD_LOGIC;
pclkx8out : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(29 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0));
END COMPONENT;
--
-- stratixiigx_hssi_calibration_block
--
COMPONENT stratixiigx_hssi_calibration_block
GENERIC (
use_continuous_calibration_mode: string := "false";
rx_calibration_write_test_value: integer := 0;
tx_calibration_write_test_value: integer := 0;
enable_rx_calibration_test_write: string := "false";
enable_tx_calibration_test_write: string := "false";
send_rx_calibration_status : string := "true");
PORT (
clk : IN std_logic := '0';
powerdn : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;
--
-- stratixiigx_hssi_cmu_pll
--
COMPONENT stratixiigx_hssi_cmu_pll
GENERIC (
inclk0_period : INTEGER := 0; -- time period in ps
inclk1_period : INTEGER := 0;
inclk2_period : INTEGER := 0;
inclk3_period : INTEGER := 0;
inclk4_period : INTEGER := 0;
inclk5_period : INTEGER := 0;
inclk6_period : INTEGER := 0;
inclk7_period : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
multiply_by : INTEGER := 1;
divide_by : INTEGER := 1;
low_speed_test_sel : INTEGER := 0;
pll_type : STRING := "normal"; -- normal,fast,auto
charge_pump_current_test_enable : INTEGER := 0;
vco_range : STRING := "low";
loop_filter_resistor_control : INTEGER := 0;
loop_filter_ripple_capacitor_control : INTEGER := 0;
use_default_charge_pump_current_selection : STRING := "false";
use_default_charge_pump_supply_vccm_vod_control : STRING := "false";
pll_number : INTEGER := 0; -- PLL 0-2
charge_pump_current_control : INTEGER := 0;
up_down_control_percent : INTEGER := 0;
charge_pump_tristate_enable : STRING := "false";
enable_pll_cascade : STRING := "false"; -- 6.1
dprio_config_mode : INTEGER := 0; -- 6.1
protocol_hint : STRING := "basic"; -- 6.1
remapped_to_new_loop_filter_charge_pump_settings : STRING := "false";
tipd_clk : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_pllreset : VitalDelayType01 := DefPropDelay01;
tipd_pllpowerdn : VitalDelayType01 := DefPropDelay01;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0
);
PORT (
clk : IN std_logic_vector(7 DOWNTO 0);
dprioin : IN std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN std_logic := '1';
pllreset : IN std_logic := '0';
pllpowerdn : IN std_logic := '0';
clkout : OUT std_logic;
locked : OUT std_logic;
dprioout : OUT std_logic_vector(39 DOWNTO 0);
fbclkout : OUT std_logic;
vcobypassout : OUT std_logic);
END COMPONENT;
--
-- stratixiigx_hssi_central_management_unit
--
COMPONENT stratixiigx_hssi_central_management_unit
GENERIC (
in_xaui_mode : string := "false";
portaddr : integer := 1; -- 1-based
devaddr : integer := 1; -- 1-based
bonded_quad_mode : string := "none";
use_deskew_fifo : string := "false";
num_con_errors_for_align_loss : integer := 2;
num_con_good_data_for_align_approach: integer := 3;
num_con_align_chars_for_align : integer := 4;
offset_all_errors_align : string := "false";
dprio_config_mode : INTEGER := 0; -- 6.1
rx_dprio_width : INTEGER := 800; -- 6.1
tx_dprio_width : INTEGER := 400; -- 6.1
lpm_type : string := "stratixiigx_hssi_central_management_unit";
rx0_cru_clock0_physical_mapping: string := "refclk0";
rx0_cru_clock1_physical_mapping: string := "refclk1";
rx0_cru_clock2_physical_mapping: string := "iq0";
rx0_cru_clock3_physical_mapping: string := "iq1";
rx0_cru_clock4_physical_mapping: string := "iq2";
rx0_cru_clock5_physical_mapping: string := "iq3";
rx0_cru_clock6_physical_mapping: string := "iq4";
rx0_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx0_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx1_cru_clock0_physical_mapping: string := "refclk0";
rx1_cru_clock1_physical_mapping: string := "refclk1";
rx1_cru_clock2_physical_mapping: string := "iq0";
rx1_cru_clock3_physical_mapping: string := "iq1";
rx1_cru_clock4_physical_mapping: string := "iq2";
rx1_cru_clock5_physical_mapping: string := "iq3";
rx1_cru_clock6_physical_mapping: string := "iq4";
rx1_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx1_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx2_cru_clock0_physical_mapping: string := "refclk0";
rx2_cru_clock1_physical_mapping: string := "refclk1";
rx2_cru_clock2_physical_mapping: string := "iq0";
rx2_cru_clock3_physical_mapping: string := "iq1";
rx2_cru_clock4_physical_mapping: string := "iq2";
rx2_cru_clock5_physical_mapping: string := "iq3";
rx2_cru_clock6_physical_mapping: string := "iq4";
rx2_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx2_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx3_cru_clock0_physical_mapping: string := "refclk0";
rx3_cru_clock1_physical_mapping: string := "refclk1";
rx3_cru_clock2_physical_mapping: string := "iq0";
rx3_cru_clock3_physical_mapping: string := "iq1";
rx3_cru_clock4_physical_mapping: string := "iq2";
rx3_cru_clock5_physical_mapping: string := "iq3";
rx3_cru_clock6_physical_mapping: string := "iq4";
rx3_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx3_cru_clock8_physical_mapping: string := "cmu_div_clk";
tx0_pll_fast_clk0_physical_mapping: string := "pll0";
tx0_pll_fast_clk1_physical_mapping: string := "pll1";
tx1_pll_fast_clk0_physical_mapping: string := "pll0";
tx1_pll_fast_clk1_physical_mapping: string := "pll1";
tx2_pll_fast_clk0_physical_mapping: string := "pll0";
tx2_pll_fast_clk1_physical_mapping: string := "pll1";
tx3_pll_fast_clk0_physical_mapping: string := "pll0";
tx3_pll_fast_clk1_physical_mapping: string := "pll1";
pll0_inclk0_logical_to_physical_mapping: string := "iq0";
pll0_inclk1_logical_to_physical_mapping: string := "iq1";
pll0_inclk2_logical_to_physical_mapping: string := "iq2";
pll0_inclk3_logical_to_physical_mapping: string := "iq3";
pll0_inclk4_logical_to_physical_mapping: string := "iq4";
pll0_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll0_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll0_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
pll1_inclk0_logical_to_physical_mapping: string := "iq0";
pll1_inclk1_logical_to_physical_mapping: string := "iq1";
pll1_inclk2_logical_to_physical_mapping: string := "iq2";
pll1_inclk3_logical_to_physical_mapping: string := "iq3";
pll1_inclk4_logical_to_physical_mapping: string := "iq4";
pll1_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll1_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll1_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
pll2_inclk0_logical_to_physical_mapping: string := "iq0";
pll2_inclk1_logical_to_physical_mapping: string := "iq1";
pll2_inclk2_logical_to_physical_mapping: string := "iq2";
pll2_inclk3_logical_to_physical_mapping: string := "iq3";
pll2_inclk4_logical_to_physical_mapping: string := "iq4";
pll2_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll2_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll2_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
cmu_divider_inclk0_physical_mapping: string := "pll0";
cmu_divider_inclk1_physical_mapping: string := "pll1";
cmu_divider_inclk2_physical_mapping: string := "pll2";
rx0_logical_to_physical_mapping: integer := 0;
rx1_logical_to_physical_mapping: integer := 1;
rx2_logical_to_physical_mapping: integer := 2;
rx3_logical_to_physical_mapping: integer := 3;
tx0_logical_to_physical_mapping: integer := 0;
tx1_logical_to_physical_mapping: integer := 1;
tx2_logical_to_physical_mapping: integer := 2;
tx3_logical_to_physical_mapping: integer := 3;
pll0_logical_to_physical_mapping: integer := 0;
pll1_logical_to_physical_mapping: integer := 1;
pll2_logical_to_physical_mapping: integer := 2;
refclk_divider0_logical_to_physical_mapping: integer := 0;
refclk_divider1_logical_to_physical_mapping: integer := 1;
sim_dump_dprio_internal_reg_at_time: integer := 0;
sim_dump_filename: string := "sim_dprio_dump.txt";
analog_test_bus_enable: string := "false";
bypass_bandgap: string := "true";
central_test_bus_select: integer := 5;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_dpclk: VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable: VitalDelayType01 := DefpropDelay01;
tipd_dprioin: VitalDelayType01 := DefpropDelay01;
tipd_dprioload: VitalDelayType01 := DefpropDelay01;
tipd_fixedclk: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_quadenable: VitalDelayType01 := DefpropDelay01;
tipd_quadreset: VitalDelayType01 := DefpropDelay01;
tipd_rxanalogreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxclk: VitalDelayType01 := DefpropDelay01;
tipd_rxdigitalreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxpowerdown: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_txclk: VitalDelayType01 := DefpropDelay01;
tipd_txdigitalreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
adet : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
cmudividerdprioin : IN std_logic_vector(29 DOWNTO 0) := (OTHERS => '0');
cmuplldprioin : IN std_logic_vector(119 DOWNTO 0) := (OTHERS => '0');
dpclk : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic := '0';
dprioload : IN std_logic := '0';
fixedclk : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
quadenable : IN std_logic := '1';
quadreset : IN std_logic := '0';
rdalign : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rdenablesync : IN std_logic := '1';
recovclk : IN std_logic := '0';
refclkdividerdprioin : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
rxanalogreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxclk : IN std_logic := '0';
rxctrl : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdatain : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdprioin : IN std_logic_vector(rx_dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
rxpowerdown : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
syncstatus : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txclk : IN std_logic := '0';
txctrl : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txdatain : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
txdigitalreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txdprioin : IN std_logic_vector(tx_dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
alignstatus : OUT std_logic;
clkdivpowerdn : OUT std_logic;
cmudividerdprioout : OUT std_logic_vector(29 DOWNTO 0);
cmuplldprioout : OUT std_logic_vector(119 DOWNTO 0);
dpriodisableout : OUT std_logic;
dpriooe : OUT std_logic;
dprioout : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic;
pllresetout : OUT std_logic_vector(2 DOWNTO 0);
pllpowerdn : OUT std_logic_vector(2 DOWNTO 0);
quadresetout : OUT std_logic;
refclkdividerdprioout : OUT std_logic_vector(1 DOWNTO 0);
rxadcepowerdn : OUT std_logic_vector(3 DOWNTO 0);
rxadceresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxcruresetout : OUT std_logic_vector(3 DOWNTO 0);
rxcrupowerdn : OUT std_logic_vector(3 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0);
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdprioout : OUT std_logic_vector(rx_dprio_width - 1 DOWNTO 0);
rxibpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0);
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
txdetectrxpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txdividerpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txobpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txdprioout : OUT std_logic_vector(tx_dprio_width - 1 DOWNTO 0);
digitaltestout : OUT std_logic_vector(9 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiigx_hssi_receiver
--
COMPONENT stratixiigx_hssi_receiver
GENERIC (
adaptive_equalization_mode : string := "none"; -- <continuous/stopped/none>;
align_loss_sync_error_num : integer := 4; -- <integer 0-7>;// wordalign
align_ordered_set_based : string := "false"; -- <true/false>;
align_pattern : string := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : integer := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only: string := "false"; -- <true/false>;
allow_align_polarity_inversion : string := "false"; -- <true/false>;
allow_pipe_polarity_inversion : string := "false"; -- <true/false>;
allow_serial_loopback : string := "false"; -- <true/false>;
bandwidth_mode : integer := 0; -- <integer 0-3>;
bit_slip_enable : string := "false"; -- <true/false>;
byte_order_pad_pattern : string := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : string := "0101111100"; -- <10-bit binary string>;
byte_ordering_mode : string := "none"; -- <none/pattern-based/syncstatus-based>;
channel_number : integer := 0; -- <integer 0-3>;
channel_bonding : string := "none"; -- <none, x4, x8>;
channel_width : integer := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : string := "recvd_clk"; -- <recvd_clk, master_clk, local_refclk, digital_refclk>;
clk2_mux_select : string := "recvd_clk"; -- <recvd_clk, local_refclk, digital_refclk, core_clk>;
cru_clock_select : integer := 0; -- <CRUCLK<n> where n is 0 through 7 >
cru_divide_by : integer := 1; -- <1,2,4>;
cru_multiply_by : integer := 10; -- <1,2,4,5,8,10,16,20,25>;
cru_pre_divide_by : integer := 1; -- <1,2,4,8>;
cruclk0_period : integer := 10000; -- in ps
cruclk1_period : integer := 10000; -- in ps
cruclk2_period : integer := 10000; -- in ps
cruclk3_period : integer := 10000; -- in ps
cruclk4_period : integer := 10000; -- in ps
cruclk5_period : integer := 10000; -- in ps
cruclk6_period : integer := 10000; -- in ps
cruclk7_period : integer := 10000; -- in ps
datapath_protocol : string := "basic"; -- <basic/pipe/xaui>;
dec_8b_10b_compatibility_mode : string := "true"; -- <true/false>;
dec_8b_10b_mode : string := "none"; -- <normal/cascaded/none>;
deskew_pattern : string := "1100111100"; -- K28.3
disable_auto_idle_insertion : string := "false"; -- <true/false>;
disable_ph_low_latency_mode : string := "false"; -- <true/false>;
disable_running_disp_in_word_align: string := "false"; -- <true/false>;
disallow_kchar_after_pattern_ordered_set: string := "false"; -- <true/false>;
dprio_mode : string := "none"; -- <none/pma_electricals/full>;
enable_bit_reversal : string := "false"; -- <true/false>;
enable_byte_order_control_sig : string := "false"; -- <true/false>;
enable_dc_coupling : string := "false"; -- <true/false>;
enable_deep_align : string := "false"; -- <true/false>;
enable_deep_align_byte_swap : string := "false"; -- <true/false>;
enable_lock_to_data_sig : string := "false"; -- <true/false>;
enable_lock_to_refclk_sig : string := "true"; -- <true/false>;
enable_self_test_mode : string := "false"; -- <true/false>;
enable_true_complement_match_in_word_align: string := "true"; -- <true/false>;
eq_adapt_seq_control : integer := 0; -- <integer 0-3>;
eq_max_gradient_control : integer := 0; -- <integer 0-7>;
equalizer_ctrl_a : integer := 0; -- <integer 0-7>;
equalizer_ctrl_b : integer := 0; -- < integer 0-7>;
equalizer_ctrl_c : integer := 0; -- < integer 0-7>;
equalizer_ctrl_d : integer := 0; -- < integer 0-7>;
equalizer_ctrl_v : integer := 0; -- < integer 0-7>;
equalizer_dc_gain : integer := 0; -- <integer 0-3>;
force_freq_det_high : string := "false"; -- <true/false>;
force_freq_det_low : string := "false"; -- <true/false>;
force_signal_detect : string := "false"; -- <true/false>;
force_signal_detect_dig : string := "false"; -- <true/false>;
ignore_lock_detect : string := "false"; -- <true/false>;
infiniband_invalid_code : integer := 0; -- <integer 0-3>;
insert_pad_on_underflow : string := "false";
num_align_code_groups_in_ordered_set: integer := 1; -- <integer 0-3>;
num_align_cons_good_data : integer := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : integer := 4; -- <Integer 1-256>;
phystatus_reset_toggle : string := "false"; -- new in 6.0 - default false
ppmselect : integer := 20; -- <integer 0-63>;
prbs_all_one_detect : string := "false"; -- <true/false>;
rate_match_almost_empty_threshold: integer := 11; -- <integer 0-15>;
rate_match_almost_full_threshold: integer := 13; -- <integer 0-15>;
rate_match_back_to_back : string := "false"; -- <true/false>;
rate_match_fifo_mode : string := "none"; -- <normal/cascaded/generic/cascaded_generic/none>;
rate_match_ordered_set_based : string := "false";
rate_match_pattern_size : integer := 10; -- <integer 10 or 20>;
rate_match_pattern1 : string := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : string := "00000000000010111100"; -- <20-bit binary string>;
rate_match_skip_set_based : string := "false"; -- <true/false>;
rd_clk_mux_select : string := "int_clk"; -- <int_clk, core_clk>;
recovered_clk_mux_select : string := "recvd_clk"; -- <recvd_clk, local_refclk, digital_refclk>;
reset_clock_output_during_digital_reset: string := "false"; -- <true/false>;
run_length : integer := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : string := "false"; -- <true/false>;
rx_detect_bypass : string := "false";
self_test_mode : string := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
send_direct_reverse_serial_loopback: string := "false"; -- <true/false>;
signal_detect_threshold : integer := 0; -- <integer 0-7 (actual values determined after PE char)>;
termination : string := "OCT_100_OHMS"; -- new in 5.1 SP1
use_align_state_machine : string := "false"; -- <true/false>;
use_deserializer_double_data_mode: string := "false"; -- <true/false>;
use_deskew_fifo : string := "false"; -- <true/false>;
use_double_data_mode : string := "false"; -- <true/false>;
use_parallel_loopback : string := "false"; -- <true/false>;
use_rate_match_pattern1_only : string := "false"; -- <true/false>;
use_rising_edge_triggered_pattern_align: string := "false"; -- <true/false>;
common_mode : string := "0.9V"; -- new in 5.1 SP1
loop_filter_resistor_control : integer := 0; -- new in 6.0;
loop_filter_ripple_capacitor_control : integer := 0; -- new in 6.0;
pd_mode_charge_pump_current_control : integer := 0; -- new in 6.0;
signal_detect_hysteresis_enabled : string := "false"; -- new in 5.1 SP1
single_detect_hysteresis_enabled : string := "false"; -- new in 5.1 SP1 - used in code
use_termvoltage_signal : string := "true"; -- new in 5.1 SP1
vco_range : string := "high"; -- new in 6.0
sim_offset_cycle_count : integer := 10; -- new in 7.1 for adce
protocol_hint : string := "basic"; -- new in 6.0
dprio_config_mode : INTEGER := 0; -- 6.1
dprio_width : INTEGER := 200; -- 6.1
allow_vco_bypass : string := "false"; -- <true/false>
charge_pump_current_control : integer := 0; -- <integer 0-3>;
up_dn_mismatch_control : integer := 0; -- <integer 0-3>;
charge_pump_test_enable : string := "false"; -- <true/false>;
charge_pump_current_test_control_pos: string := "false"; -- <true/false>
charge_pump_tristate_enable : string := "false"; -- <true/false>;
low_speed_test_select : integer := 0; -- <integer 0-15>;
cru_clk_sel_during_vco_bypass : string := "refclk1"; -- <refclk1/refclk2/ext1/ext2>
test_bus_sel : integer := 0 ; -- <integer 0-7>;
enable_phfifo_bypass : string := "false";
sim_rxpll_clkout_phase_shift : integer := 0;
sim_rxpll_clkout_latency : integer := 0;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_a1a2size: VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn: VitalDelayType01 := DefpropDelay01;
tipd_adcereset: VitalDelayType01 := DefpropDelay01;
tipd_alignstatus: VitalDelayType01 := DefpropDelay01;
tipd_alignstatussync: VitalDelayType01 := DefpropDelay01;
tipd_analogreset: VitalDelayType01 := DefpropDelay01;
tipd_bitslip: VitalDelayType01 := DefpropDelay01;
tipd_coreclk: VitalDelayType01 := DefpropDelay01;
tipd_cruclk: VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
tipd_crupowerdn: VitalDelayType01 := DefpropDelay01;
tipd_crureset: VitalDelayType01 := DefpropDelay01;
tipd_datain: VitalDelayType01 := DefpropDelay01;
tipd_digitalreset: VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin: VitalDelayType01 := DefpropDelay01;
tipd_disablefifowrin: VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable: VitalDelayType01 := DefpropDelay01;
tipd_enabledeskew: VitalDelayType01 := DefpropDelay01;
tipd_enabyteord: VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign: VitalDelayType01 := DefpropDelay01;
tipd_fifordin: VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd: VitalDelayType01 := DefpropDelay01;
tipd_ibpowerdn: VitalDelayType01 := DefpropDelay01;
tipd_invpol: VitalDelayType01 := DefpropDelay01;
tipd_localrefclk: VitalDelayType01 := DefpropDelay01;
tipd_locktodata: VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk: VitalDelayType01 := DefpropDelay01;
tipd_masterclk: VitalDelayType01 := DefpropDelay01;
tipd_parallelfdbk: VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tipd_phfifordenable: VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset: VitalDelayType01 := DefpropDelay01;
tipd_phfifowrdisable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8bytesel: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable: VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity: VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown: VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_pipepowerstate: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_quadreset: VitalDelayType01 := DefpropDelay01;
tipd_refclk: VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa: VitalDelayType01 := DefpropDelay01;
tipd_revbyteorderwa: VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena: VitalDelayType01 := DefpropDelay01;
tipd_rmfiforeset: VitalDelayType01 := DefpropDelay01;
tipd_rmfifowrena: VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid: VitalDelayType01 := DefpropDelay01;
tipd_rxfound: VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_serialfdbk: VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken: VitalDelayType01 := DefpropDelay01;
tipd_termvoltage: VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tipd_testsel: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrlin: VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain: VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
a1a2size : IN std_logic := '0';
adcepowerdn : IN std_logic := '0';
adcereset : IN std_logic := '0';
alignstatus : IN std_logic := '0';
alignstatussync : IN std_logic := '0';
analogreset : IN std_logic := '0';
bitslip : IN std_logic := '0';
coreclk : IN std_logic := '0';
cruclk : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
crupowerdn : IN std_logic := '0';
crureset : IN std_logic := '0';
datain : IN std_logic := '0';
digitalreset : IN std_logic := '0';
disablefifordin : IN std_logic := '0';
disablefifowrin : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic_vector(dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
enabledeskew : IN std_logic := '0';
enabyteord : IN std_logic := '0';
enapatternalign : IN std_logic := '0';
fifordin : IN std_logic := '0';
fiforesetrd : IN std_logic := '0';
ibpowerdn : IN std_logic := '0';
invpol : IN std_logic := '0';
localrefclk : IN std_logic := '0';
locktodata : IN std_logic := '0';
locktorefclk : IN std_logic := '0';
masterclk : IN std_logic := '0';
parallelfdbk : IN std_logic_vector(19 DOWNTO 0) := (OTHERS => '0');
phfifordenable : IN std_logic := '1';
phfiforeset : IN std_logic := '0';
phfifowrdisable : IN std_logic := '0';
phfifox4bytesel : IN std_logic := '0';
phfifox4rdenable : IN std_logic := '0';
phfifox4wrclk : IN std_logic := '0';
phfifox4wrenable : IN std_logic := '0';
phfifox8bytesel : IN std_logic := '0';
phfifox8rdenable : IN std_logic := '0';
phfifox8wrclk : IN std_logic := '0';
phfifox8wrenable : IN std_logic := '0';
pipe8b10binvpolarity : IN std_logic := '0'; -- new in rev1.2
pipepowerdown : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); -- width from 1 -> 2 in rev1.2
pipepowerstate : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); -- width change from 3 to 4 in rev1.3
quadreset : IN std_logic := '0';
refclk : IN std_logic := '0';
revbitorderwa : IN std_logic := '0';
revbyteorderwa : IN std_logic := '0';
rmfifordena : IN std_logic := '1';
rmfiforeset : IN std_logic := '0';
rmfifowrena : IN std_logic := '1';
rxdetectvalid : IN std_logic := '0';
rxfound : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
serialfdbk : IN std_logic := '0';
seriallpbken : IN std_logic := '0';
termvoltage : IN std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
testsel : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
xgmctrlin : IN std_logic := '0';
xgmdatain : IN std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
a1a2sizeout : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
a1detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
a2detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
adetectdeskew : OUT std_logic;
alignstatussyncout : OUT std_logic;
analogtestbus : OUT std_logic_vector(7 DOWNTO 0);
bistdone : OUT std_logic;
bisterr : OUT std_logic;
byteorderalignstatus : OUT std_logic;
clkout : OUT std_logic;
cmudivclkout : OUT std_logic;
ctrldetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dataoutfull : OUT std_logic_vector(63 DOWNTO 0);
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
disperr : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
dprioout : OUT std_logic_vector(dprio_width - 1 DOWNTO 0);
errdetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
fifordout : OUT std_logic;
freqlock : OUT std_logic;
k1detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
k2detect : OUT std_logic_vector(1 DOWNTO 0);
patterndetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
phaselockloss : OUT std_logic;
phfifobyteselout : OUT std_logic;
phfifooverflow : OUT std_logic;
phfifordenableout : OUT std_logic;
phfifounderflow : OUT std_logic;
phfifowrclkout : OUT std_logic;
phfifowrenableout : OUT std_logic;
pipebufferstat : OUT std_logic_vector(3 DOWNTO 0);
pipedatavalid : OUT std_logic;
pipeelecidle : OUT std_logic;
pipephydonestatus : OUT std_logic;
pipestatus : OUT std_logic_vector(2 DOWNTO 0);
pipestatetransdoneout : OUT std_logic;
rdalign : OUT std_logic;
recovclkout : OUT std_logic;
revparallelfdbkdata : OUT std_logic_vector(19 DOWNTO 0);
revserialfdbkout : OUT std_logic;
rlv : OUT std_logic;
rmfifoalmostempty : OUT std_logic;
rmfifoalmostfull : OUT std_logic;
rmfifodatadeleted : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
rmfifodatainserted : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
rmfifoempty : OUT std_logic;
rmfifofull : OUT std_logic;
runningdisp : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
signaldetect : OUT std_logic;
syncstatus : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
syncstatusdeskew : OUT std_logic;
xgmctrldet : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0);
xgmdatavalid : OUT std_logic;
xgmrunningdisp : OUT std_logic);
END COMPONENT;
--
-- stratixiigx_hssi_transmitter
--
COMPONENT stratixiigx_hssi_transmitter
GENERIC (
allow_polarity_inversion : string := "false";
channel_bonding : string := "none"; -- none, x8, x4
channel_number : integer := 0;
channel_width : integer := 8;
disable_ph_low_latency_mode : string := "false";
disparity_mode : string := "none"; -- legacy, new, none
divider_refclk_select_pll_fast_clk0: string := "true";
dprio_mode : string := "none";
elec_idle_delay : integer := 5; -- new in 6.0
enable_bit_reversal : string := "false";
enable_idle_selection : string := "false";
enable_symbol_swap : string := "false";
enable_reverse_parallel_loopback: string := "false";
enable_reverse_serial_loopback : string := "false";
enable_self_test_mode : string := "false";
enc_8b_10b_compatibility_mode : string := "true";
enc_8b_10b_mode : string := "none"; -- cascade, normal, none
force_echar : string := "false";
force_kchar : string := "false";
low_speed_test_select : integer := 0;
prbs_all_one_detect : string := "false";
protocol_hint : string := "basic"; -- new in 6.0
refclk_divide_by : integer := 1;
refclk_select : string := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset: string := "false";
rxdetect_ctrl : integer := 0;
self_test_mode : string := "incremental";
serializer_clk_select : string := "local"; -- analogx4refclk, anlogx8refclk
transmit_protocol : string := "basic"; -- xaui-pipe-gige-basic?
use_double_data_mode : string := "false";
use_serializer_double_data_mode: string := "false";
wr_clk_mux_select : string := "CORE_CLK"; -- INT_CLK -- int_clk
vod_selection : integer := 0;
enable_slew_rate : string := "false";
preemp_tap_1 : integer := 0;
preemp_tap_2 : integer := 0;
preemp_pretap : integer := 0;
termination : string := "OCT_100_OHMS"; -- new in 5.1 SP1
preemp_tap_2_inv : string := "false"; -- New in rev 2.1
preemp_pretap_inv : string := "false"; -- New in rev 2.1
use_termvoltage_signal : string := "true"; -- new in 5.1 SP1
common_mode : string := "0.6V"; -- new in 5.1 SP1
analog_power : string := "1.5V"; -- new in 5.1 SP1
dprio_config_mode : INTEGER := 0; -- 6.1
dprio_width : INTEGER := 100; -- 6.1
allow_vco_bypass : string := "false";
enable_phfifo_bypass : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_coreclk : VitalDelayType01 := DefPropDelay01;
tipd_ctrlenable : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefPropDelay01;
tipd_quadreset : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull : VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefPropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefPropDelay01;
tipd_analogx8fastrefclk : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefPropDelay01;
tipd_analogx8refclk : VitalDelayType01 := DefPropDelay01;
tipd_pma_width : VitalDelayType01 := DefPropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefPropDelay01;
tipd_pma_doublewidth : VitalDelayType01 := DefPropDelay01;
tipd_revparallelfdbk : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox8rdclk : VitalDelayType01 := DefPropDelay01;
tipd_obpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_termvoltage : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forceelecidle : VitalDelayType01 := DefPropDelay01;
tipd_powerdn : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefPropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dispval : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_analogx4fastrefclk : VitalDelayType01 := DefPropDelay01;
tipd_refclk : VitalDelayType01 := DefPropDelay01;
tipd_analogreset : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox8rdenable : VitalDelayType01 := DefPropDelay01;
tipd_invpol : VitalDelayType01 := DefPropDelay01;
tipd_enrevparallellpbk : VitalDelayType01 := DefPropDelay01;
tipd_digitalreset : VitalDelayType01 := DefPropDelay01;
tipd_phfifox8bytesel : VitalDelayType01 := DefPropDelay01;
tipd_dividerpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_analogx4refclk : VitalDelayType01 := DefPropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefPropDelay01;
tipd_revserialfdbk : VitalDelayType01 := DefPropDelay01;
tipd_clkin0 : VitalDelayType01 := DefPropDelay01;
tipd_clkin1 : VitalDelayType01 := DefPropDelay01;
tipd_reset : VitalDelayType01 := DefPropDelay01;
tipd_detectrxloop : VitalDelayType01 := DefPropDelay01;
tipd_pllfastclk : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdclk : VitalDelayType01 := DefPropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefPropDelay01;
tipd_detectrxpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_phfiforddisable : VitalDelayType01 := DefPropDelay01;
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datainfull_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datainfull_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
analogreset : IN std_logic := '0';
analogx4fastrefclk : IN std_logic := '0';
analogx4refclk : IN std_logic := '0';
analogx8fastrefclk : IN std_logic := '0';
analogx8refclk : IN std_logic := '0';
coreclk : IN std_logic := '0';
ctrlenable : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
datainfull : IN std_logic_vector(43 DOWNTO 0) := (OTHERS => '0');
detectrxloop : IN std_logic := '0';
detectrxpowerdn : IN std_logic := '0';
digitalreset : IN std_logic := '0';
dispval : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
dividerpowerdn : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic_vector(dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
enrevparallellpbk : IN std_logic := '0';
forcedispcompliance : IN std_logic := '0';
forcedisp : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN std_logic := '0';
invpol : IN std_logic := '0';
obpowerdn : IN std_logic := '0';
phfiforddisable : IN std_logic := '0';
phfiforeset : IN std_logic := '0';
phfifowrenable : IN std_logic := '1';
phfifox4bytesel : IN std_logic := '0';
phfifox4rdclk : IN std_logic := '0';
phfifox4rdenable : IN std_logic := '0';
phfifox4wrenable : IN std_logic := '0';
phfifox8bytesel : IN std_logic := '0';
phfifox8rdclk : IN std_logic := '0';
phfifox8rdenable : IN std_logic := '0';
phfifox8wrenable : IN std_logic := '0';
pipestatetransdone : IN std_logic := '0';
pllfastclk : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
quadreset : IN std_logic := '0';
refclk : IN std_logic := '0';
revserialfdbk : IN std_logic := '0';
revparallelfdbk : IN std_logic_vector(19 DOWNTO 0) := (OTHERS => '0');
termvoltage : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
vcobypassin : IN std_logic := '0'; -- PE-POF only
xgmctrl : IN std_logic := '0';
xgmdatain : IN std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
clkout : OUT std_logic;
dataout : OUT std_logic;
dprioout : OUT std_logic_vector(dprio_width - 1 DOWNTO 0);
parallelfdbkout : OUT std_logic_vector(19 DOWNTO 0);
phfifooverflow : OUT std_logic;
phfifounderflow : OUT std_logic;
phfifobyteselout : OUT std_logic;
phfifordclkout : OUT std_logic;
phfifordenableout : OUT std_logic;
phfifowrenableout : OUT std_logic;
pipepowerdownout : OUT std_logic_vector(1 DOWNTO 0);
pipepowerstateout : OUT std_logic_vector(3 DOWNTO 0);
rdenablesync : OUT std_logic;
refclkout : OUT std_logic;
rxdetectvalidout : OUT std_logic;
rxfoundout : OUT std_logic_vector(1 DOWNTO 0);
serialfdbkout : OUT std_logic;
xgmctrlenable : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
end stratixiigx_hssi_components;
package body STRATIXIIGX_HSSI_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end STRATIXIIGX_HSSI_COMPONENTS;
| gpl-3.0 | 1cd82b0585454c0771b5df3b3248dfb7 | 0.550784 | 3.925865 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/step_chan.vhd | 1 | 4,333 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity STEP_CHAN is
port (
RESET: in std_logic;
CLK: in std_logic;
pos_capt: in std_logic;
pos_hi: out std_logic_vector(31 downto 0);
pos_lo: out std_logic_vector(31 downto 0);
targetvel: in std_logic_vector(31 downto 0);
deltalim: in std_logic_vector(31 downto 0);
step_len: in std_logic_vector(31 downto 0);
dir_hold_dly: in std_logic_vector(31 downto 0);
dir_setup_dly: in std_logic_vector(31 downto 0);
OUT_EN: in std_logic;
IDLE: out std_logic;
STP_OUT: out std_logic;
STP_DIR: out std_logic
);
end;
architecture rtl of STEP_CHAN is
signal vel: std_logic_vector(47 downto 0);
signal vel_target: std_logic_vector(47 downto 0);
signal vel_delta_lim_pos: std_logic_vector(47 downto 0);
signal vel_delta_lim_neg: std_logic_vector(47 downto 0);
signal vel_delta: std_logic_vector(47 downto 0);
signal timer_step_len: std_logic_vector(31 downto 0);
signal timer_step_len_run: std_logic;
signal timer_dir_hold_dly: std_logic_vector(31 downto 0);
signal timer_dir_hold_dly_run: std_logic;
signal timer_dir_setup_dly: std_logic_vector(31 downto 0);
signal timer_dir_setup_dly_run: std_logic;
signal direction: std_logic;
signal direction_old: std_logic;
signal capture: std_logic;
signal accu: std_logic_vector(63 downto 0);
signal accu_inc: std_logic_vector(63 downto 0);
signal accu_reg: std_logic_vector(31 downto 0);
signal stepflag: std_logic;
begin
-- set position output
pos_hi <= accu(63 downto 32);
capture_proc: process(RESET, CLK)
begin
if RESET = '1' then
pos_lo <= (others => '0');
elsif rising_edge(CLK) then
if pos_capt = '1' then
pos_lo <= accu(31 downto 0);
end if;
end if;
end process;
-- check for running timers
timer_step_len_run <= '1' when timer_step_len /= 0 else '0';
timer_dir_hold_dly_run <= '1' when timer_dir_hold_dly /= 0 else '0';
timer_dir_setup_dly_run <= '1' when timer_dir_setup_dly /= 0 else '0';
-- calc velocity delta limit
vel_target <= targetvel & "0000000000000000" when OUT_EN = '1' else (others => '0');
vel_delta_lim_pos <= "0000000000000000" & deltalim;
vel_delta_lim_neg <= 0 - vel_delta_lim_pos;
vel_delta <= vel_target - vel;
-- get command direction
direction <= vel(47);
-- expand vel to akku size with respect to sign
accu_inc(63 downto 32) <= (others => vel(47));
accu_inc(31 downto 0) <= vel(47 downto 16);
stepgen_proc: process(CLK)
begin
if RESET = '1' then
vel <= (others => '0');
timer_step_len <= (others => '0');
timer_dir_hold_dly <= (others => '0');
timer_dir_setup_dly <= (others => '0');
accu <= (others => '0');
stepflag <= '0';
STP_DIR <= '0';
elsif rising_edge(CLK) then
-- update velocity
if signed(vel_delta) < signed(vel_delta_lim_neg) then
vel <= vel + vel_delta_lim_neg;
elsif signed(vel_delta) > signed(vel_delta_lim_pos) then
vel <= vel + vel_delta_lim_pos;
else
vel <= vel + vel_delta;
end if;
-- update timers
if timer_step_len_run = '1' then
timer_step_len <= timer_step_len - 1;
elsif timer_dir_hold_dly_run = '1' then
timer_dir_hold_dly <= timer_dir_hold_dly - 1;
elsif timer_dir_setup_dly_run = '1' then
timer_dir_setup_dly <= timer_dir_setup_dly - 1;
end if;
-- check for direction change
direction_old <= direction;
if direction_old /= direction then
timer_dir_hold_dly <= dir_hold_dly;
timer_dir_setup_dly <= dir_setup_dly;
else
if timer_dir_hold_dly_run = '0' then
-- update motor direction
STP_DIR <= direction;
-- dds
if timer_dir_setup_dly_run = '0' then
accu <= accu + accu_inc;
stepflag <= accu(32);
if stepflag /= accu(32) then
timer_step_len <= step_len;
end if;
end if;
end if;
end if;
end if;
end process;
-- generate step pulse
STP_OUT <= timer_step_len_run;
-- set idle output
IDLE <= '1' when vel = 0 else '0';
end;
| gpl-3.0 | f3384ae5c5dab05bcf7a6f6c9d47a110 | 0.606047 | 3.167398 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/hardcopyii_components.vhd | 1 | 52,020 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyii_atom_pack.all;
package hardcopyii_components is
--
-- hardcopyii_ram_block
--
COMPONENT hardcopyii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "hardcopyii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyii_routing_wire
--
COMPONENT hardcopyii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_jtag
--
COMPONENT hardcopyii_jtag
generic (
lpm_type : string := "hardcopyii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- hardcopyii_lcell_ff
--
COMPONENT hardcopyii_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "hardcopyii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_lcell_comb
--
COMPONENT hardcopyii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "hardcopyii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_clkctrl
--
COMPONENT hardcopyii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "hardcopyii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- hardcopyii_io
--
COMPONENT hardcopyii_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "hardcopyii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_pll
--
COMPONENT hardcopyii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "hardcopyii_pll";
family_name : string := "StratixII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- hardcopyii_mac_mult
--
COMPONENT hardcopyii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "hardcopyii_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_mac_out
--
COMPONENT hardcopyii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "hardcopyii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_lvds_transmitter
--
COMPONENT hardcopyii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "hardcopyii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_lvds_receiver
--
COMPONENT hardcopyii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "hardcopyii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_dll
--
COMPONENT hardcopyii_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "hardcopyii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_termination
--
COMPONENT hardcopyii_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "hardcopyii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyii_lcell_hsadder
--
COMPONENT hardcopyii_lcell_hsadder
generic (
use_cin1_for_sumout : string := "on";
lpm_type : string := "hardcopyii_lcell_hsadder";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '0';
sumout0 : out std_logic;
sumout1 : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
end hardcopyii_components;
| gpl-3.0 | a33c76159e8947216559f9ca9b58809f | 0.481853 | 4.294914 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/enc_mod.vhd | 1 | 3,621 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity ENC_MOD is
generic (
-- IO-REQ: 7 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000100";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of ENC_MOD is
signal wb_data_mux : std_logic_vector(31 downto 0);
signal capture: std_logic;
signal timestamp: std_logic_vector(31 downto 0);
signal cnt_reg_a: std_logic_vector(31 downto 0);
signal ts_reg_a: std_logic_vector(31 downto 0);
signal idx_reg_a: std_logic_vector(31 downto 0);
signal cnt_reg_b: std_logic_vector(31 downto 0);
signal ts_reg_b: std_logic_vector(31 downto 0);
signal idx_reg_b: std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR, WB_STB_RD, timestamp, cnt_reg_a, idx_reg_a, cnt_reg_b, idx_reg_b)
begin
capture <= '0';
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
capture <= WB_STB_RD;
wb_data_mux <= timestamp;
when WB_ADDR_OFFSET + 1 =>
wb_data_mux <= cnt_reg_a;
when WB_ADDR_OFFSET + 2 =>
wb_data_mux <= ts_reg_a;
when WB_ADDR_OFFSET + 3 =>
wb_data_mux <= idx_reg_a;
when WB_ADDR_OFFSET + 4 =>
wb_data_mux <= cnt_reg_b;
when WB_ADDR_OFFSET + 5 =>
wb_data_mux <= ts_reg_b;
when WB_ADDR_OFFSET + 6 =>
wb_data_mux <= idx_reg_b;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
----------------------------------------------------------
--- timestamp generator
----------------------------------------------------------
timestamp_proc: process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
timestamp <= (others => '0');
elsif rising_edge(WB_CLK) then
timestamp <= timestamp + 1;
end if;
end process;
----------------------------------------------------------
--- encoder instances
----------------------------------------------------------
U_ENC_A: entity work.ENC_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
CAPTURE => capture,
TIMESTAMP => timestamp,
CNT_REG => cnt_reg_a,
TS_REG => ts_reg_a,
IDX_REG => idx_reg_a,
ENC_A => not SV(10),
ENC_B => not SV(8),
ENC_I => not SV(6)
);
U_ENC_B: entity work.ENC_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
CAPTURE => capture,
TIMESTAMP => timestamp,
CNT_REG => cnt_reg_b,
TS_REG => ts_reg_b,
IDX_REG => idx_reg_b,
ENC_A => not SV(9),
ENC_B => not SV(7),
ENC_I => not SV(5)
);
-- hold unused pins to GND
SV(4 downto 3) <= (others => '0');
end;
| gpl-3.0 | 29dc00cccdf33f88ef8c3cc79ad2f30c | 0.515051 | 3.3129 | false | false | false | false |
alvieboy/xtc-base | fetch.vhd | 1 | 6,106 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity fetch is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to ROM
stall: in std_logic;
valid: in std_logic;
address: out std_logic_vector(31 downto 0);
read: in std_logic_vector(31 downto 0);
enable: out std_logic;
strobe: out std_logic;
seq: out std_logic;
abort: out std_logic;
nseq: out std_logic;
-- Control
freeze: in std_logic;
jump: in std_logic;
jumppriv: in std_logic;
jumpaddr: in word_type;
dual: in std_logic;
-- Outputs for next stages
fuo: out fetch_output_type
);
end entity fetch;
architecture behave of fetch is
signal fr: fetch_regs_type;
signal opcode0, opcode1: std_logic_vector(15 downto 0);
signal strobe_i: std_logic;
-- debug only
signal busycnt: unsigned(31 downto 0);
begin
fault1: if FAULTCHECKS generate
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
busycnt<=(others =>'0');
else
if strobe_i='1' and stall='1' then
busycnt<=busycnt+1;
else
busycnt<=(others =>'0');
end if;
end if;
end if;
end process;
fuo.internalfault<='1' when busycnt > 65535 else '0';
end generate;
strobe<=strobe_i;
fuo.r <= fr;
fuo.opcode <= opcode0 & opcode1;
address <= std_logic_vector(fr.fpc);
nseq <= '1' when fr.state=jumping else '0';
seq <= fr.seq;
process(fr, rst, clk, stall, valid, freeze, dual, jump, jumpaddr,read)
variable fw: fetch_regs_type;
variable npc: word_type;
variable realnpc: word_type;
begin
fw := fr;
npc := fr.fpc + 4;
if dual='1' then
realnpc := fr.pc + 4;
else
realnpc := fr.pc + 2;
end if;
fuo.npc <= realnpc;
fuo.valid <= valid;
abort <= '0';
enable <= not freeze;
--strobe_i <= not freeze;
strobe_i<='1';
if fr.unaligned_jump='1' and read(15)='1' then -- Extended opcode.
fuo.valid <= '0';
end if;
opcode0 <= read(31 downto 16);
if fr.invert_readout='1' then
opcode1 <= fr.qopc;
else
opcode1 <= read(15 downto 0);
end if;
fuo.inverted <= fr.unaligned;
case fr.state is
when running =>
if jump='0' then
if stall='0' and freeze='0' then
fw.fpc := npc;
end if;
if valid='1' then
if freeze='0' then
if not (fr.unaligned_jump='1' and dual='1') then
fw.pc := realnpc;
fw.seq := '1';
end if;
fw.qopc := read(15 downto 0);
fw.unaligned_jump := '0';
end if;
-- simple check
--if dual='1' and fr.unaligned_jump='1' then
-- report "DUAL" severity note;
--end if;
end if;
if dual='0' and valid='1' and freeze='0' then
-- Will go unaligned
if fr.unaligned='0' then
fw.unaligned := '1';
fw.invert_readout:='1';
--enable <= '0';
--strobe_i <= '0';
else
if fr.invert_readout='1' then
strobe_i<='0';
if fr.unaligned_jump='1' then
--strobe_i<='1';
end if;
fw.fpc := fr.fpc;
else
strobe_i <='1';
end if;
-- If we had an unaligned jump, we have to trick
-- the system into outputting directly from the RAM, since this
-- is the value usually queued.
fw.unaligned := '0';
fw.invert_readout := '0';
end if;
else
if dual='1' and freeze='0' and fr.unaligned_jump='1' then
fw.invert_readout:='1';
else
--fw.invert_readout:='0';
end if;
end if;
else
-- Jump request
fw.fpc := jumpaddr;
fw.priv:= jumppriv;
fw.unaligned := jumpaddr(1);
fw.fpc(1 downto 0) := "00";
fw.seq := '0';
fw.pc := jumpaddr;
fw.pc(0) := '0';
fw.unaligned_jump := jumpaddr(1);
fw.state := jumping;
strobe_i <= '0';
enable <= '0';
abort <= '1';
--fuo.valid <= '0';
end if;
when jumping =>
if true then
strobe_i <= '1';
enable <= '1';
if stall='0' then
fw.fpc := npc;
fw.seq := '1';
--fw.unaligned := fr.unaligned_jump;
if fr.unaligned_jump='1' then
fw.invert_readout := '1';
fw.state := aligning;
fw.unaligned_jump:='0';
else
fw.invert_readout := '0';
fw.state := running;
end if;
end if;
else
fw.fpc := jumpaddr;
fw.unaligned := jumpaddr(1);
fw.fpc(1 downto 0) := "00";
fw.pc := jumpaddr;
fw.pc(0) := '0';
fw.unaligned_jump := jumpaddr(1);
--fw.state := jumping;
strobe_i <= '0';
enable <= '0';
abort <= '1';
end if;
fuo.valid<='0';
when aligning =>
fuo.valid<='0';
if valid='1' then
fw.qopc := read(15 downto 0);
--fw.unaligned := '0';
fw.fpc := npc;
fw.seq := '1';
fw.state := running;
end if;
when others =>
end case;
if rst='1' then
fw.pc := RESETADDRESS;
fw.fpc := RESETADDRESS;
fw.seq := '0';
fw.priv:='1';
--strobe_i <= '0';
--enable <= '0';
fw.unaligned := '0';
fw.unaligned_jump := '0';
fw.invert_readout := '0';
fw.state := jumping;
fw.qopc := (others => '0');
--fuo.valid<='0';
end if;
if rising_edge(clk) then
fr <= fw;
end if;
end process;
end behave;
| bsd-3-clause | 86af136332f646bd15430e1d872cd214 | 0.471176 | 3.645373 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiv_components.vhd | 1 | 38,459 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiv_atom_pack.all;
package cycloneiv_components is
--
-- cycloneiv_lcell_comb
--
COMPONENT cycloneiv_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_routing_wire
--
COMPONENT cycloneiv_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_ff
--
COMPONENT cycloneiv_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- cycloneiv_ram_block
--
COMPONENT cycloneiv_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiv_mac_mult
--
COMPONENT cycloneiv_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_mac_out
--
COMPONENT cycloneiv_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiv_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_io_ibuf
--
COMPONENT cycloneiv_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- cycloneiv_io_obuf
--
COMPONENT cycloneiv_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiv_ddio_oe
--
COMPONENT cycloneiv_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_ddio_out
--
COMPONENT cycloneiv_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiv_io_pad
--
COMPONENT cycloneiv_io_pad
GENERIC (
lpm_type : string := "cycloneiv_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- cycloneiv_clkctrl
--
COMPONENT cycloneiv_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiv_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- cycloneiv_pseudo_diff_out
--
COMPONENT cycloneiv_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiv_rublock
--
COMPONENT cycloneiv_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
sim_init_config_is_application : string := "false";
sim_init_watchdog_enabled : string := "false";
operation_mode : string := "active_serial_remote";
lpm_type : string := "cycloneiv_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_termination
--
COMPONENT cycloneiv_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- cycloneiv_jtag
--
COMPONENT cycloneiv_jtag
generic (
lpm_type : string := "cycloneiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneiv_crcblock
--
COMPONENT cycloneiv_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiv_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_oscillator
--
COMPONENT cycloneiv_oscillator
generic
(
lpm_type: string := "cycloneiv_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
observableoutputport: out std_logic;
clkout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_controller
--
COMPONENT cycloneiv_controller
generic
(
lpm_type: string := "cycloneiv_controller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
END COMPONENT;
--
-- cycloneiv_pll
--
COMPONENT cycloneiv_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
feedback_source : integer := 0;
feedback_external_loop_divider : string := "false";
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 1;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiv_pll";
lpm_hint : string := "unused";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
family_name : string := "Cyclone IV GX";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fref : out std_logic;
icdrclk : out std_logic
);
END COMPONENT;
end cycloneiv_components;
| gpl-3.0 | dcba58270a870c2df2f668abb2b4b7c1 | 0.473595 | 4.339276 | false | false | false | false |
keith-epidev/md2x | build/code/top.vhdl | 1 | 3,917 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.my_lib.all;
entity top is
port (
CLK: in std_logic;
SW : in std_logic_vector(17 downto 0);
KEY : in std_logic_vector(3 downto 0);
LEDR : out std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(7 downto 0);
HEX : out hex_array;
LCD_RS: out std_logic;
LCD_RW: out std_logic;
LCD_EN: out std_logic;
LCD_DATA: out std_logic_vector (7 downto 0);
LCD_ON: out std_logic;
PS2_CLK: in std_logic;
PS2_DAT: in std_logic
);
end top;
architecture arch of top is
component lcd is
port(
clk: in std_logic;
reset: in std_logic;
rs: out std_logic;
rw: out std_logic;
e: out std_logic;
data: out std_logic_vector(7 downto 0);
disp: in disp_chars
);
end component;
component keyboard is
port(
sys_clk: in std_logic;
reset: in std_logic;
PS2C: in std_logic;
PS2D: in std_logic;
output: out std_logic_vector(8*3-1 downto 0);
new_val: out std_logic;
leds: out std_logic_vector(8 downto 0)
);
end component;
component keyboard2 IS
PORT( keyboard_clk, keyboard_data, clock_25Mhz ,reset, reads : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
scan_ready : OUT STD_LOGIC
);
END component;
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
component seven_segment is
port (
clk : in std_logic;
val : in std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
mode: in std_logic
);
end component;
signal reset : std_logic;
--LCD
signal data: std_logic_vector(7 downto 0);
signal e: std_logic;
signal lcd_disp : disp_chars;
--Keyboard
signal clr: std_logic;
signal keys : std_logic_vector(7downto 0);
signal key_buffer : std_logic_vector(3*8-1 downto 0);
signal key_output : std_logic_vector(3*8-1 downto 0);
signal new_key :std_logic;
signal counter : std_logic_vector(3 downto 0);
signal clk25 : std_logic;
signal reads : std_logic;
signal send : std_logic;
signal o : std_logic;
begin
reset <= not KEY(0);
LCD_DATA <= data;
LCD_EN <= e;
LEDG <= data;
--LEDR(0) <= e;
LEDR(0) <= o;
LEDR(4 downto 1) <= counter;
lcd1 : lcd port map(clk,reset,LCD_RS,LCD_RW,e,data,lcd_disp);
LCD_ON <= '1';
--0lcd_latch <= '1';
--lcd_disp(0 to 4) <= (X"4B",X"45",X"49",X"54",X"48");
--lcd_disp(16 to 16+1) <= (X"48",X"49");
--keyb: keyboard2 port map( PS2_CLK, PS2_DAT, clk25, '0',reads, keys, new_key);
p1: pulser generic map(delay=>2) port map(clk, '1', clk25);
p2: pulser generic map(delay=>50000000) port map(clk, '1', send);
keyb : keyboard port map(clk,reset,PS2_CLK,PS2_DAT,key_output,new_key,LEDR(16 downto 8));
hex0: seven_segment port map(clk,key_output(3 downto 0),HEX(0),'0');
hex1: seven_segment port map(clk,key_output(7 downto 4),HEX(1),'0');
----
hex2: seven_segment port map(clk,key_output(11 downto 8),HEX(2),'0');
hex3: seven_segment port map(clk,key_output(15 downto 12),HEX(3),'0');
----
hex4: seven_segment port map(clk,key_output(19 downto 16),HEX(4),'0');
hex5: seven_segment port map(clk,key_output(23 downto 20),HEX(5),'0');
--
process(clk,reset)
variable index : integer := 0;
begin
if(reset = '1')then
index := 0;
lcd_disp <= (others=>(X"20"));
elsif(clk'event and clk = '1')then
if(new_key = '1')then
key_buffer <= key_output;
lcd_disp(index) <= key_output(7 downto 0);
index := index +1;
if(index = 32)then
index := 0;
end if;
counter <= counter +1;
end if;
end if;
end process;
end arch;
| gpl-2.0 | 4dee77d4e3fa0b8d495eda7a7d9bcf1d | 0.606842 | 2.708852 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaii_hssi_components.vhd | 1 | 127,541 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package ARRIAII_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function rx_top_basic_width (channel_width : integer) return integer;
function rx_top_num_of_basic (channel_width : integer) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function alpha_tolower (given_string : string) return string;
function arriaii_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string;
function arriaii_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer;
function arriaii_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- arriaii_hssi_clock_divider
--
COMPONENT arriaii_hssi_clock_divider
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_refclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchdonein :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_clk0in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_vcobypassin : VitalDelayType01 := DefpropDelay01;
tipd_clk1in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchbaseclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdig : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(100 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_hssi_clock_divider";
channel_num : INTEGER := 0;
coreclk_out_gated_by_quad_reset : STRING := "false";
data_rate : INTEGER := 0;
divide_by : INTEGER := 4;
divider_type : STRING := "CHANNEL_REGULAR";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
enable_refclk_out : STRING := "false";
inclk_select : INTEGER := 0;
logical_channel_address : INTEGER := 0;
pre_divide_by : INTEGER := 1;
rate_switch_base_clk_in_select : INTEGER := 0;
rate_switch_done_in_select : INTEGER := 0;
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
refclkin_select : INTEGER := 0;
select_local_rate_switch_base_clock : STRING := "false";
select_local_rate_switch_done : STRING := "true"; -- shawn
select_local_refclk : STRING := "false";
select_refclk_dig : STRING := "false";
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0;
sim_refclkout_phase_shift : INTEGER := 0;
use_coreclk_out_post_divider : STRING := "false";
use_refclk_post_divider : STRING := "false";
use_vco_bypass : STRING := "false"
);
PORT (
clk0in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
clk1in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(100 - 1 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchbaseclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rateswitchdonein : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclkdig : IN STD_LOGIC := '0';
refclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
vcobypassin : IN STD_LOGIC := '0';
analogfastrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogfastrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkpulse : OUT STD_LOGIC;
analogrefclkpulseshifted : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(100 - 1 DOWNTO 0);
rateswitchbaseclock : OUT STD_LOGIC;
rateswitchdone : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
refclkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_hssi_pll
--
COMPONENT arriaii_hssi_pll
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_earlyeios : VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk : VitalDelayType01 := DefpropDelay01;
tipd_pfdfbclk : VitalDelayType01 := DefpropDelay01;
tipd_powerdown : VitalDelayType01 := DefpropDelay01;
tipd_inclk :VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tpd_inclk_clk : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaii_hssi_pll";
auto_settings : STRING := "true";
bandwidth_type : STRING := "Auto";
base_data_rate : STRING := "unused";
channel_num : INTEGER := 0;
charge_pump_current_bits : INTEGER := 0;
charge_pump_mode_bits : INTEGER := 0;
charge_pump_test_enable : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
fast_lock_control : STRING := "false";
inclk0_input_period : INTEGER := 0;
inclk1_input_period : INTEGER := 0;
inclk2_input_period : INTEGER := 0;
inclk3_input_period : INTEGER := 0;
inclk4_input_period : INTEGER := 0;
inclk5_input_period : INTEGER := 0;
inclk6_input_period : INTEGER := 0;
inclk7_input_period : INTEGER := 0;
inclk8_input_period : INTEGER := 0;
inclk9_input_period : INTEGER := 0;
input_clock_frequency : STRING := "unused";
logical_channel_address : INTEGER := 0;
logical_tx_pll_number : INTEGER := 0;
loop_filter_c_bits : INTEGER := 0;
loop_filter_r_bits : INTEGER := 0;
m : INTEGER := 0;
n : INTEGER := 0;
pd_charge_pump_current_bits : INTEGER := 0;
pd_loop_filter_r_bits : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
pfd_fb_select : STRING := "internal";
pll_type : STRING := "Auto";
protocol_hint : STRING := "basic";
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
sim_is_negative_ppm_drift : STRING := "false";
sim_net_ppm_variation : INTEGER := 0;
test_charge_pump_current_down : STRING := "false";
test_charge_pump_current_up : STRING := "false";
use_refclk_pin : STRING := "false";
vco_data_rate : INTEGER := 0;
vco_divide_by : INTEGER := 0;
vco_range : STRING := "low";
vco_multiply_by : INTEGER := 0;
vco_post_scale : INTEGER := 0;
vco_tuning_bits : INTEGER := 0;
volt_reg_control_bits : INTEGER := 0;
volt_reg_output_bits : INTEGER := 0;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0;
PARAM_DELAY : INTEGER := 0
);
PORT (
areset : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
earlyeios : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 - 1 DOWNTO 0) := (others => '0');
inclk : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
locktorefclk : IN STD_LOGIC := '1';
pfdfbclk : IN STD_LOGIC := '0';
powerdown : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
clk : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locked : OUT STD_LOGIC;
pfdfbclkout : OUT STD_LOGIC;
pfdrefclkout : OUT STD_LOGIC;
vcobypassout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_hssi_tx_pma
--
COMPONENT arriaii_hssi_tx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_datain :VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(20 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0inpulse : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_pclk : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_fastrefclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_refclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk4inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_rxdetecten : VitalDelayType01 := DefpropDelay01;
tipd_refclk1inpulse : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpmareset : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revserialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_refclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxpowerdown : VitalDelayType01 := DefpropDelay01;
tipd_refclk3inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdetectclk : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "arriaii_hssi_tx_pma";
analog_power : STRING := "1.5V";
channel_number : INTEGER := 9999;
channel_type : STRING := "auto";
clkin_select : INTEGER := 0; -- 9999; out of bound in loading
clkmux_delay : STRING := "false";
common_mode : STRING := "0.6V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_reverse_serial_loopback : STRING := "false";
logical_channel_address : INTEGER := 0;
logical_protocol_hint_0 : STRING := "basic";
logical_protocol_hint_1 : STRING := "basic";
logical_protocol_hint_2 : STRING := "basic";
logical_protocol_hint_3 : STRING := "basic";
low_speed_test_select : INTEGER := 9999;
physical_clkin0_mapping : STRING := "x1";
physical_clkin1_mapping : STRING := "x4";
physical_clkin2_mapping : STRING := "xn_top";
physical_clkin3_mapping : STRING := "xn_bottom";
physical_clkin4_mapping : STRING := "hypertransport";
preemp_pretap : INTEGER := 0;
preemp_pretap_inv : STRING := "false";
preemp_tap_1 : INTEGER := 0;
preemp_tap_1_a : INTEGER := 0;
preemp_tap_1_b : INTEGER := 0;
preemp_tap_1_c : INTEGER := 0;
preemp_tap_2 : INTEGER := 0;
preemp_tap_2_inv : STRING := "false";
protocol_hint : STRING := "basic";
rx_detect : INTEGER := 9999;
serialization_factor : INTEGER := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_pclk : STRING := "false";
use_pma_direct : STRING := "false";
use_rx_detect : STRING := "false";
use_ser_double_data_mode : STRING := "false";
vod_selection : INTEGER := 0;
vod_selection_a : INTEGER := 0;
vod_selection_b : INTEGER := 0;
vod_selection_c : INTEGER := 0;
vod_selection_d : INTEGER := 0
);
PORT (
datain : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(20 - 1 DOWNTO 0) := (others => '0');
detectrxpowerdown : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(11 - 1 DOWNTO 0) := (others => '0');
fastrefclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN STD_LOGIC := '0';
pclk : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk0inpulse : IN STD_LOGIC := '0';
refclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk1inpulse : IN STD_LOGIC := '0';
refclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk2inpulse : IN STD_LOGIC := '0';
refclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk3inpulse : IN STD_LOGIC := '0';
refclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
refclk4inpulse : IN STD_LOGIC := '0';
revserialfdbk : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
txpmareset : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dftout : OUT STD_LOGIC_VECTOR(6 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_hssi_rx_pma
--
COMPONENT arriaii_hssi_rx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_rxpmareset : VitalDelayType01 := DefpropDelay01;
tipd_plllocked : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_ignorephslck : VitalDelayType01 := DefpropDelay01;
tipd_locktoref : VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_adcestandby : VitalDelayType01 := DefpropDelay01;
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken : VitalDelayType01 := DefpropDelay01;
tipd_adcereset : VitalDelayType01 := DefpropDelay01;
tipd_deserclock :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_locktodata : VitalDelayType01 := DefpropDelay01;
tipd_freqlock : VitalDelayType01 := DefpropDelay01;
tipd_offsetcancellationen : VitalDelayType01 := DefpropDelay01;
tipd_testbussel :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoverdatain :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_seriallpbkin : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_adaptcapture : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_hssi_rx_pma";
adaptive_equalization_mode : STRING := "none";
allow_serial_loopback : STRING := "false";
allow_vco_bypass : INTEGER := 0;
analog_power : STRING := "1.4V";
channel_number : INTEGER := 0;
channel_type : STRING := "auto";
common_mode : STRING := "0.82V";
deserialization_factor : INTEGER := 8;
dfe_piclk_bandwidth : INTEGER := 0;
dfe_piclk_phase : INTEGER := 0;
dfe_piclk_sel : INTEGER := 0;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
eq_adapt_seq_control : INTEGER := 0;
eq_dc_gain : INTEGER := 0;
eq_max_gradient_control : INTEGER := 0;
eqa_ctrl : INTEGER := 0;
eqb_ctrl : INTEGER := 0;
eqc_ctrl : INTEGER := 0;
eqd_ctrl : INTEGER := 0;
eqv_ctrl : INTEGER := 0;
eyemon_bandwidth : INTEGER := 0;
force_signal_detect : STRING := "true";
ignore_lock_detect : STRING := "false";
logical_channel_address : INTEGER := 0;
low_speed_test_select : INTEGER := 0;
offset_cancellation : INTEGER := 0;
ppm_gen1_2_xcnt_en : INTEGER := 1;
ppm_post_eidle : INTEGER := 0;
ppmselect : INTEGER := 0;
protocol_hint : STRING := "basic";
send_direct_reverse_serial_loopback : STRING := "None";
signal_detect_hysteresis : INTEGER := 4;
signal_detect_hysteresis_valid_threshold : INTEGER := 2;
signal_detect_loss_threshold : INTEGER := 3;
termination : STRING := "OCT 100 Ohms";
use_deser_double_data_width : STRING := "false";
use_external_termination : STRING := "false";
use_pma_direct : STRING := "false";
PARAM_DELAY : INTEGER := 0
);
PORT (
adaptcapture : IN STD_LOGIC := '0';
adcepowerdn : IN STD_LOGIC := '0';
adcereset : IN STD_LOGIC := '0';
adcestandby : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
deserclock : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(38 - 1 DOWNTO 0) := (others => '0');
freqlock : IN STD_LOGIC := '0';
ignorephslck : IN STD_LOGIC := '0';
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
offsetcancellationen : IN STD_LOGIC := '0';
plllocked : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
recoverdatain : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rxpmareset : IN STD_LOGIC := '0';
seriallpbken : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
testbussel : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
adaptdone : OUT STD_LOGIC;
analogtestbus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dataoutfull : OUT STD_LOGIC_VECTOR(20 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
locktorefout : OUT STD_LOGIC;
ppmdetectclkrel : OUT STD_LOGIC;
recoverdataout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
revserialfdbkout : OUT STD_LOGIC;
signaldetect : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_hssi_tx_pcs
--
COMPONENT arriaii_hssi_tx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01;
tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_freezptr : VitalDelayType01 := DefpropDelay01;
tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01;
tipd_pipetxswing : VitalDelayType01 := DefpropDelay01;
tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaii_hssi_tx_pcs";
allow_polarity_inversion : STRING := "false";
auto_spd_self_switch_enable : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none"; -- none, x8, x4
channel_number : INTEGER := 0;
channel_width : INTEGER := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL=
datapath_protocol : STRING := "basic"; --replaced by protocol_hint
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none"; -- legacy, new, none
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6>
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_symbol_swap : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "true";
enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none";
ph_fifo_xn_mapping1 : STRING := "none";
ph_fifo_xn_mapping2 : STRING := "none";
ph_fifo_xn_select : INTEGER := 9999;
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL=
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "incremental";
use_double_data_mode : STRING := "false";
use_serializer_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "core_clk"; -- INT_CLK // int_clk
use_top_quad_as_mater : STRING := "true"; -- NEW_PARAM todo: select top/bottom to provide phfifo pointers
dprio_width : INTEGER := 150
);
PORT (
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0');
coreclk : IN STD_LOGIC := '0';
ctrlenable : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
datain : IN STD_LOGIC_VECTOR(39 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(43 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); --fix_width
forcedispcompliance : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
freezptr : IN STD_LOGIC := '0';
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
hiptxdeemph : IN STD_LOGIC := '0';
hiptxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
invpol : IN STD_LOGIC := '0';
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
localrefclk : IN STD_LOGIC := '0';
phfifobyteserdisable : IN STD_LOGIC := '0';
phfifoptrsreset : IN STD_LOGIC := '0';
phfiforddisable : IN STD_LOGIC := '0';
phfiforeset : IN STD_LOGIC := '0';
phfifowrenable : IN STD_LOGIC := '1';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifoxnbottombytesel : IN STD_LOGIC := '0';
phfifoxnbottomrdclk : IN STD_LOGIC := '0';
phfifoxnbottomrdenable : IN STD_LOGIC := '0';
phfifoxnbottomwrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxntopbytesel : IN STD_LOGIC := '0';
phfifoxntoprdclk : IN STD_LOGIC := '0';
phfifoxntoprdenable : IN STD_LOGIC := '0';
phfifoxntopwrenable : IN STD_LOGIC := '0';
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
pipestatetransdone : IN STD_LOGIC := '0';
pipetxdeemph : IN STD_LOGIC := '0'; --NEW; RTL=txdeemph;
pipetxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); --NEW; RTL=txmargin[2:0]
pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0'; --NEW, RTL=rate
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
xgmctrl : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hiptxclkout : OUT STD_LOGIC;
iqpphfifobyteselout : OUT STD_LOGIC;
iqpphfifordclkout : OUT STD_LOGIC;
iqpphfifordenableout : OUT STD_LOGIC;
iqpphfifowrenableout : OUT STD_LOGIC;
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifooverflow : OUT STD_LOGIC;
phfifordclkout : OUT STD_LOGIC;
phfiforddisableout : OUT STD_LOGIC;
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenableout : OUT STD_LOGIC;
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rateswitchout : OUT STD_LOGIC;
rdenablesync : OUT STD_LOGIC;
txdetectrx : OUT STD_LOGIC;
xgmctrlenable : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_hssi_rx_pcs
--
COMPONENT arriaii_hssi_rx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_phfifox8bytesel : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_parallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidlerateswitch : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerstate :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_alignstatussync : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_hippowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk : VitalDelayType01 := DefpropDelay01;
tipd_enabyteord : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable : VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01;
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnptrsreset :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_signaldetected : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_autospdxnconfigsel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoveredclk : VitalDelayType01 := DefpropDelay01;
tipd_hiprateswitch : VitalDelayType01 := DefpropDelay01;
tipd_phfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_elecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_iqpautospdxnspgchg :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_rxfound :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_autospdxnspdchg :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaii_hssi_rx_pcs";
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- <true/false>;
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
auto_spd_self_switch_enable : STRING := "false";
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_double_data_mode_mask_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode
byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165
cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : INTEGER := 0;
cdrctrl_min_lock_to_ref_cycle : INTEGER := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none"; -- <none, x4, x8>;
channel_number : INTEGER := 0; -- <integer 0-3>;
channel_width : INTEGER := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
clk2_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
clk_pd_enable : STRING := "false"; --ww47_cram_p1
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic"; -- <basic/pipe/xaui> replaced by protocol_hint
dec_8b_10b_compatibility_mode : STRING := "true";
dec_8b_10b_mode : STRING := "none"; -- <normal/cascaded/none>;
dec_8b_10b_polarity_inv_enable : STRING := "false";
deskew_pattern : STRING := "1100111100"; -- K28.3
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_k_detect : STRING := "false";
elec_idle_num_com_detect : INTEGER := 0;
enable_bit_reversal : STRING := "false";
enable_deep_align : STRING := "false";
enable_deep_align_byte_swap : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_true_complement_match_in_word_align : STRING := "true";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : INTEGER := 0; -- <integer 0-3>;
insert_pad_on_underflow : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false"; -- b165
num_align_code_groups_in_ordered_set : INTEGER := 1; -- <integer 0-3>;
num_align_cons_good_data : INTEGER := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : INTEGER := 4; -- <Integer 1-256>;
num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num
ph_fifo_disable : STRING := "false";
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping1 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping2 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_select : INTEGER := 9999;
phystatus_delay : INTEGER := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_hip_enable : STRING := "false"; --NEW_PARAM todo: remove
pma_done_count : INTEGER := 53392; --ww47_cram_p1
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
rate_match_almost_empty_threshold : INTEGER := 11; -- <integer 0-15>;
rate_match_almost_full_threshold : INTEGER := 13; -- <integer 0-15>;
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : INTEGER := 13;
rate_match_empty_threshold : INTEGER := 5;
rate_match_fifo_mode : STRING := "false"; -- <normal/cascaded/generic/cascaded_generic/none> in s2gx, bool in s4gx;
rate_match_full_threshold : INTEGER := 20;
rate_match_insert_threshold : INTEGER := 11;
rate_match_ordered_set_based : STRING := "false"; -- <integer 10 or 20>;
rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern_size : INTEGER := 10; -- <integer 10 or 20>;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : INTEGER := 7;
rd_clk_mux_select : STRING := "int_clk"; -- <INT_CLK, CORE_CLK>;
recovered_clk_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
reset_clock_output_during_digital_reset : STRING := "false";
run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : INTEGER := 32;
rxstatus_error_report_mode : INTEGER := 0;
self_test_mode : STRING := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
test_bus_sel : INTEGER := 0;
use_alignment_state_machine : STRING := "false";
use_deserializer_double_data_mode : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
use_rising_edge_triggered_pattern_align : STRING := "false"; -- <true/false>; //83 para: new=23 rem=40
enable_phfifo_bypass : STRING := "false"
);
PORT (
a1a2size : IN STD_LOGIC := '0';
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
autospdxnconfigsel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- config_sel_centrl, quad_up, quad_down
autospdxnspdchg : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- From CMU.spped-change_centrl, rx3(up), rx0(down)
bitslip : IN STD_LOGIC := '0';
cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr
coreclk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); --NEW: updated width
digitalreset : IN STD_LOGIC := '0';
disablefifordin : IN STD_LOGIC := '0';
disablefifowrin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
fifordin : IN STD_LOGIC := '0';
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch
hiprateswitch : IN STD_LOGIC := '0'; -- hip_rate
invpol : IN STD_LOGIC := '0';
iqpautospdxnspgchg : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- speed_change_in_pipe_quad_up, down
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnptrsreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- reset_pc_ptrs_in_pipe_quad_up, down
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rd_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnwrclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rx_div2_sync_in_pipe_quad_up, down
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
phfifordenable : IN STD_LOGIC := '1';
phfiforeset : IN STD_LOGIC := '0';
phfifowrdisable : IN STD_LOGIC := '0';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifox8bytesel : IN STD_LOGIC := '0';
phfifox8rdenable : IN STD_LOGIC := '0';
phfifox8wrclk : IN STD_LOGIC := '0';
phfifox8wrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rx_we_in_centrl, quad_up, quad_down
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to both RX & TX.
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rd_enable_in_centrl, quad_up, quad_down
phfifoxnwrclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to RX.
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- wr_enable_in_centrl, quad_up, quad_down
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
rmfifordena : IN STD_LOGIC := '0';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '0';
rxdetectvalid : IN STD_LOGIC := '0';
rxelecidlerateswitch : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
signaldetected : IN STD_LOGIC := '0';
wareset : IN STD_LOGIC := '0'; -- new in 9.1
xauidelcondmet : IN STD_LOGIC := '0';
xauififoovr : IN STD_LOGIC := '0';
xauiinsertincomplete : IN STD_LOGIC := '0';
xauilatencycomp : IN STD_LOGIC := '0';
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins ---
a1a2sizeout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
adetectdeskew : OUT STD_LOGIC;
alignstatussyncout : OUT STD_LOGIC;
autospdrateswitchout : OUT STD_LOGIC;
autospdspdchgout : OUT STD_LOGIC; --ww47_out speed_chang_out_pipe
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD?
cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR.
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
ctrldetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- new in 6.1
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
disablefifordout : OUT STD_LOGIC;
disablefifowrout : OUT STD_LOGIC;
disperr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
errdetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
fifordout : OUT STD_LOGIC;
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0)
hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid
hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle
hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0)
iqpphfifobyteselout : OUT STD_LOGIC; --ww47_out rx_we_out_pipe
iqpphfifoptrsresetout : OUT STD_LOGIC; --ww47_out reset_pc_pters_out_pipe
iqpphfifordenableout : OUT STD_LOGIC; --ww47_out rd_enable_pipe_out
iqpphfifowrclkout : OUT STD_LOGIC; --ww47_out rx_div2_sync_out_pipe
iqpphfifowrenableout : OUT STD_LOGIC; --ww47_out wr_enable_out_pipe
k1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
k2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
patterndetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifobyteserdisableout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifooverflow : OUT STD_LOGIC;
phfifoptrsresetout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifounderflow : OUT STD_LOGIC;
phfifowrclkout : OUT STD_LOGIC;
phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifowrenableout : OUT STD_LOGIC;
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipephydonestatus : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
pipestatetransdoneout : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
rdalign : OUT STD_LOGIC;
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifoalmostempty : OUT STD_LOGIC;
rmfifoalmostfull : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
runningdisp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
signaldetect : OUT STD_LOGIC;
syncstatus : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
xauidelcondmetout : OUT STD_LOGIC;
xauififoovrout : OUT STD_LOGIC;
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_hssi_cmu
--
COMPONENT arriaii_hssi_cmu
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanclk : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchdonein : VitalDelayType01 := DefpropDelay01;
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpllreset : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdividerdprioin : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_scanmode : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_cmuplldprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_txcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cmudividerdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01;
tipd_scanshift : VitalDelayType01 := DefpropDelay01;
tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01;
tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaii_hssi_cmu";
analog_test_bus_enable : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
bonded_quad_mode : STRING := "none";
bypass_bandgap : STRING := "false";
central_test_bus_select : INTEGER := 0;
cmu_type : STRING := "regular";
devaddr : INTEGER := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
migrated_from_prev_family : STRING := "false";
num_con_align_chars_for_align : INTEGER := 4;
num_con_errors_for_align_loss : INTEGER := 2;
num_con_good_data_for_align_approach : INTEGER := 3;
offset_all_errors_align : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pma_done_count : INTEGER := 0;
portaddr : INTEGER := 1;
rx0_auto_spd_self_switch_enable : STRING := "false";
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_phfifo_wait_cnt : INTEGER := 0;
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx_master_direction : STRING := "none";
rx_xaui_sm_backward_compatible_enable : STRING := "false";
test_mode : STRING := "false";
tx0_auto_spd_self_switch_enable : STRING := "false";
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_ph_fifo_reg_mode : STRING := "false";
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "int clock";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx_master_direction : STRING := "none";
tx_pll0_used_as_rx_cdr : STRING := "false";
tx_pll1_used_as_rx_cdr : STRING := "false";
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_deskew_fifo : STRING := "false";
vcceh_voltage : STRING := "3.0V";
vcceh_voltage_user_specified_auto : STRING := "true";
protocol_hint : STRING := "basic";
clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1";
cmu_divider0_inclk0_physical_mapping : STRING := "pll0";
cmu_divider0_inclk1_physical_mapping : STRING := "pll1";
cmu_divider0_inclk2_physical_mapping : STRING := "x4";
cmu_divider0_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider0_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider1_inclk0_physical_mapping : STRING := "pll0";
cmu_divider1_inclk1_physical_mapping : STRING := "pll1";
cmu_divider1_inclk2_physical_mapping : STRING := "x4";
cmu_divider1_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider1_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider2_inclk0_physical_mapping : STRING := "pll0";
cmu_divider2_inclk1_physical_mapping : STRING := "pll1";
cmu_divider2_inclk2_physical_mapping : STRING := "x4";
cmu_divider2_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider2_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider3_inclk0_physical_mapping : STRING := "pll0";
cmu_divider3_inclk1_physical_mapping : STRING := "pll1";
cmu_divider3_inclk2_physical_mapping : STRING := "x4";
cmu_divider3_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider3_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider4_inclk0_physical_mapping : STRING := "pll0";
cmu_divider4_inclk1_physical_mapping : STRING := "pll1";
cmu_divider4_inclk2_physical_mapping : STRING := "x4";
cmu_divider4_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider4_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider5_inclk0_physical_mapping : STRING := "pll0";
cmu_divider5_inclk1_physical_mapping : STRING := "pll1";
cmu_divider5_inclk2_physical_mapping : STRING := "x4";
cmu_divider5_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider5_inclk4_physical_mapping : STRING := "xn_b";
pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll0_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll0_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll0_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll0_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll0_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll0_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll1_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll1_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll1_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll1_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll1_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll1_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll2_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll2_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll2_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll2_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll2_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll2_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll3_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll3_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll3_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll3_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll3_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll3_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll4_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll4_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll4_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll4_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll4_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll4_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll5_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll5_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll5_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll5_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll5_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll5_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll0_logical_to_physical_mapping : INTEGER := 0;
pll1_logical_to_physical_mapping : INTEGER := 1;
pll2_logical_to_physical_mapping : INTEGER := 2;
pll3_logical_to_physical_mapping : INTEGER := 3;
pll4_logical_to_physical_mapping : INTEGER := 4;
pll5_logical_to_physical_mapping : INTEGER := 5;
refclk_divider0_logical_to_physical_mapping : INTEGER := 0;
refclk_divider1_logical_to_physical_mapping : INTEGER := 1;
rx0_logical_to_physical_mapping : INTEGER := 0;
rx1_logical_to_physical_mapping : INTEGER := 1;
rx2_logical_to_physical_mapping : INTEGER := 2;
rx3_logical_to_physical_mapping : INTEGER := 3;
rx4_logical_to_physical_mapping : INTEGER := 4;
rx5_logical_to_physical_mapping : INTEGER := 5;
tx0_logical_to_physical_mapping : INTEGER := 0;
tx1_logical_to_physical_mapping : INTEGER := 1;
tx2_logical_to_physical_mapping : INTEGER := 2;
tx3_logical_to_physical_mapping : INTEGER := 3;
tx4_logical_to_physical_mapping : INTEGER := 4;
tx5_logical_to_physical_mapping : INTEGER := 5;
tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps
sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs
);
PORT (
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (others => '0');
fixedclk : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
lccmurtestbussel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchdonein : IN STD_LOGIC := '0';
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rdenablesync : IN STD_LOGIC := '0';
recovclk : IN STD_LOGIC := '0';
refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
rxanalogreset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxclk : IN STD_LOGIC := '0';
rxcoreclk : IN STD_LOGIC := '0';
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0');
rxphfifordenable : IN STD_LOGIC := '0';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
rxpowerdown : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (others => '0');
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(9999 DOWNTO 0) := (others => '0');
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txpllreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
txpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
alignstatus : OUT STD_LOGIC;
autospdx4configsel : OUT STD_LOGIC;
autospdx4rateswitchout : OUT STD_LOGIC;
autospdx4spdchg : OUT STD_LOGIC;
clkdivpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpriodisableout : OUT STD_LOGIC;
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
extra10gout : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
lccmutestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
phfifiox4ptrsreset : OUT STD_LOGIC;
pllpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pllresetout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
quadresetout : OUT STD_LOGIC;
refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxadcepowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxadceresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcrupowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcruresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
testout : OUT STD_LOGIC_VECTOR(6999 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_hssi_calibration_block
--
COMPONENT arriaii_hssi_calibration_block
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_clk : VitalDelayType01 := DefpropDelay01;
lpm_type : string := "arriaii_hssi_calibration_block";
cont_cal_mode : string := "false";
enable_rx_cal_tw : string := "false";
enable_tx_cal_tw : string := "false";
migrated_from_prev_family : string := "false";
rtest : string := "false";
rx_cal_wt_value : integer := 0;
send_rx_cal_status : string := "true";
tx_cal_wt_value : integer := 1);
PORT (
clk : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
powerdn : IN std_logic := '0';
testctrl : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
nonusertocmu : OUT std_logic);
END COMPONENT;
--
-- arriaii_hssi_refclk_divider
--
COMPONENT arriaii_hssi_refclk_divider
GENERIC (
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
enable_divider : STRING := "false";
lpm_type : STRING := "arriaii_hssi_refclk_divider";
refclk_coupling_termination : STRING := "dc_coupling_external_termination";
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
inclk : IN STD_LOGIC:= '0';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
end arriaii_hssi_components;
package body ARRIAII_HSSI_COMPONENTS is
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function rx_top_basic_width (channel_width : integer) return integer is
variable basic_width : integer;
begin
if (channel_width mod 10 = 0) then
basic_width := 10;
else
basic_width := 8;
end if;
return(basic_width);
end rx_top_basic_width;
function rx_top_num_of_basic (channel_width : integer) return integer is
variable num_of_basic : integer;
begin
if (channel_width mod 10 = 0) then
num_of_basic := channel_width/10;
else
num_of_basic := channel_width/8;
end if;
return(num_of_basic);
end rx_top_num_of_basic;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
function arriaii_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is
begin
CASE ph_fifo_xn_select IS
WHEN 0 => RETURN ph_fifo_xn_mapping0;
WHEN 1 => RETURN ph_fifo_xn_mapping1;
WHEN 2 => RETURN ph_fifo_xn_mapping2;
WHEN OTHERS => RETURN "none";
END CASE;
end arriaii_tx_pcs_mph_fifo_xn_mapping;
function arriaii_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end arriaii_tx_pcs_mphfifo_index;
function arriaii_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end arriaii_tx_pcs_miqp_phfifo_index;
end ARRIAII_HSSI_COMPONENTS;
| gpl-3.0 | 2c495d9422ff660a958d0997de8985a7 | 0.499565 | 4.279325 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaiigz_atoms.vhd | 1 | 936,743 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package arriaiigz_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE arriaiigz_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end arriaiigz_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body arriaiigz_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end arriaiigz_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package arriaiigz_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end arriaiigz_pllpack;
package body arriaiigz_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end arriaiigz_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriaiigz_dffe : entity is TRUE;
end arriaiigz_dffe;
-- architecture body --
architecture behave of arriaiigz_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- arriaiigz_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of arriaiigz_mux21 : entity is TRUE;
end arriaiigz_mux21;
architecture AltVITAL of arriaiigz_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- arriaiigz_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_mux41 : entity is TRUE;
end arriaiigz_mux41;
architecture AltVITAL of arriaiigz_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- arriaiigz_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaiigz_atom_pack.all;
-- entity declaration --
entity arriaiigz_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriaiigz_and1 : entity is TRUE;
end arriaiigz_and1;
-- architecture body --
architecture AltVITAL of arriaiigz_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : arriaiigz_jtag
--
-- Description : Stratix JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_jtag is
generic (
lpm_type : string := "arriaiigz_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end arriaiigz_jtag;
architecture architecture_jtag of arriaiigz_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : arriaiigz_crcblock
--
-- Description : Stratix CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_crcblock is
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "arriaiigz_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end arriaiigz_crcblock;
architecture architecture_crcblock of arriaiigz_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : arriaiigz_lcell_comb
--
-- Description : ARRIAIIGZ LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "arriaiigz_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_lcell_comb : entity is TRUE;
end arriaiigz_lcell_comb;
architecture vital_lcell_comb of arriaiigz_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : arriaiigz_routing_wire
--
-- Description : ARRIAIIGZ Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_routing_wire : entity is TRUE;
end arriaiigz_routing_wire;
ARCHITECTURE behave of arriaiigz_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_lvds_tx_reg : ENTITY is TRUE;
END arriaiigz_lvds_tx_reg;
ARCHITECTURE vital_arriaiigz_lvds_tx_reg of arriaiigz_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_arriaiigz_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriaiigz_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriaiigz_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the ARRIAIIGZ
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE std.textio.all;
ENTITY arriaiigz_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END arriaiigz_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of arriaiigz_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriaiigz_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE std.textio.all;
ENTITY arriaiigz_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END arriaiigz_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of arriaiigz_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriaiigz_lvds_transmitter
--
-- Description : Timing simulation model for the ARRIAIIGZ LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) ARRIAIIGZ_lvds_tx_parallel_register and
-- 3) ARRIAIIGZ_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE std.textio.all;
USE work.arriaiigz_lvds_tx_parallel_register;
USE work.arriaiigz_lvds_tx_out_block;
USE work.arriaiigz_lvds_tx_reg;
ENTITY arriaiigz_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- ARRIAIIGZ
tx_output_path_delay_engineering_bits : Integer := -1; -- ARRIAIIGZ
enable_dpaclk_to_lvdsout : string := "off"; -- ARRIAIIGZ
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriaiigz_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- ARRIAIIGZ
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- ARRIAIIGZ
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- ARRIAIIGZ
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end arriaiigz_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of arriaiigz_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;-- ARRIAIIGZ
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT arriaiigz_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT arriaiigz_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT arriaiigz_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);-- ARRIAIIGZ
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: arriaiigz_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: arriaiigz_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: arriaiigz_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd, -- ARRIAIIGZ
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then-- ARRIAIIGZ
dataout_tmp := dpaclkin_ipd;-- ARRIAIIGZ
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then -- ARRIAIIGZ
VitalPathDelay01 ( -- ARRIAIIGZ
OutSignal => dataout, -- ARRIAIIGZ
OutSignalName => "DATAOUT", -- ARRIAIIGZ
OutTemp => dataout_tmp, -- ARRIAIIGZ
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)), -- ARRIAIIGZ
GlitchData => dataout_VitalGlitchData, -- ARRIAIIGZ
Mode => DefGlitchMode, -- ARRIAIIGZ
XOn => XOn, -- ARRIAIIGZ
MsgOn => MsgOn ); -- ARRIAIIGZ
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--
--
-- ARRIAIIGZ_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
--ADD_CYCLONEIV sim_init_config_is_application : string := "false";
--ADD_CYCLONEIV sim_init_watchdog_enabled : string := "false";
--ADD_CYCLONEIV operation_mode : string := "active_serial_remote";
lpm_type : string := "arriaiigz_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end arriaiigz_rublock;
architecture architecture_rublock of arriaiigz_rublock is
begin
end architecture_rublock;
----------------------------------------------------------------------------
-- Module Name : arriaiigz_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END arriaiigz_ram_register;
ARCHITECTURE reg_arch OF arriaiigz_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : arriaiigz_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF arriaiigz_ram_pulse_generator:ENTITY IS TRUE;
END arriaiigz_ram_pulse_generator;
ARCHITECTURE pgen_arch OF arriaiigz_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE work.arriaiigz_ram_register;
USE work.arriaiigz_ram_pulse_generator;
ENTITY arriaiigz_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriaiigz_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END arriaiigz_ram_block;
ARCHITECTURE block_arch OF arriaiigz_ram_block IS
COMPONENT arriaiigz_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT arriaiigz_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : arriaiigz_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : arriaiigz_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : arriaiigz_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : arriaiigz_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : arriaiigz_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : arriaiigz_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : arriaiigz_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : arriaiigz_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : arriaiigz_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : arriaiigz_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : arriaiigz_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : arriaiigz_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : arriaiigz_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : arriaiigz_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : arriaiigz_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : arriaiigz_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : arriaiigz_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : arriaiigz_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : arriaiigz_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : arriaiigz_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : arriaiigz_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : arriaiigz_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : arriaiigz_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : arriaiigz_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaiigz_ff
--
-- Description : ARRIAIIGZ FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_and1;
entity arriaiigz_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "arriaiigz_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_ff : entity is TRUE;
end arriaiigz_ff;
architecture vital_lcell_ff of arriaiigz_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component arriaiigz_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: arriaiigz_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: arriaiigz_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: arriaiigz_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for ARRIAIIGZ CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- ARRIAIIGZ_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_clkselect is
generic (
lpm_type : STRING := "arriaiigz_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_clkselect : entity is TRUE;
end arriaiigz_clkselect;
architecture vital_clkselect of arriaiigz_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- arriaiigz_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaiigz_atom_pack.all;
-- entity declaration --
entity arriaiigz_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriaiigz_and2 : entity is TRUE;
end arriaiigz_and2;
-- architecture body --
architecture AltVITAL of arriaiigz_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaiigz_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_ena_reg : entity is TRUE;
end arriaiigz_ena_reg;
ARCHITECTURE behave of arriaiigz_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for ARRIAIIGZ CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- ARRIAIIGZ_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_ena_reg;
use work.arriaiigz_and2;
entity arriaiigz_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriaiigz_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_clkena : entity is TRUE;
end arriaiigz_clkena;
architecture vital_clkena of arriaiigz_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component arriaiigz_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component arriaiigz_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : arriaiigz_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : arriaiigz_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : arriaiigz_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : arriaiigz_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Module Name : arriaiigz_mlab_cell_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_mlab_cell_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF arriaiigz_mlab_cell_pulse_generator:ENTITY IS TRUE;
END arriaiigz_mlab_cell_pulse_generator;
ARCHITECTURE pgen_arch OF arriaiigz_mlab_cell_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE work.arriaiigz_mlab_cell_pulse_generator;
ENTITY arriaiigz_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "arriaiigz_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END arriaiigz_mlab_cell;
ARCHITECTURE block_arch OF arriaiigz_mlab_cell IS
COMPONENT arriaiigz_mlab_cell_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
-- -------- internal signals ---------
-- Write address
SIGNAL write_address : INTEGER := 0;
SIGNAL read_address : INTEGER := 0;
-- pulses
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
SIGNAL mask_vector : mask_write := (
normal => (OTHERS => '0'),
inverse => (OTHERS => 'X')
);
-- output
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_write IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END LOOP;
RETURN mask;
END get_mask;
SIGNAL clk0_ipd : STD_LOGIC;
SIGNAL ena0_ipd : STD_LOGIC;
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0';
BEGIN
-- interconnect delays
WireDelay : BLOCK
BEGIN
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
END GENERATE;
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
END GENERATE;
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
END BLOCK;
-- setup/hold checks
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd,clk0_ipd,ena0_ipd)
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
BEGIN
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_enable,
TimingData => TimingData_clk_enable,
TestSignal => ena0_ipd,
TestSignalName => "ena0",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_ena0_clk0_noedge_posedge,
SetupLow => tsetup_ena0_clk0_noedge_posedge,
HoldHigh => thold_ena0_clk0_noedge_posedge,
HoldLow => thold_ena0_clk0_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_address,
TimingData => TimingData_clk_address,
TestSignal => portaaddr_ipd,
TestSignalName => "portaaddr",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
HoldLow => thold_portaaddr_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_bemasks,
TimingData => TimingData_clk_bemasks,
TestSignal => portabyteenamasks_ipd,
TestSignalName => "portabyteenamasks",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
END PROCESS setup_hold_checks;
-- latch CE signal
PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
-- output path delay
PROCESS (portbaddr_ipd)
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
CQDelay := SelectDelay(
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
);
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
END PROCESS;
-- memory initialization
init_mem <= TRUE;
write_clock <= NOT clk0_ipd;
write_address <= alt_conv_integer(portaaddr_ipd);
-- Write pulse generation (neg edge)
wpgen_a : arriaiigz_mlab_cell_pulse_generator
PORT MAP (
clk => write_clock,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (portabyteenamasks_ipd)
VARIABLE mask : mask_write;
BEGIN
IF (portabyteenamasks_ipd'EVENT) THEN
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
mask_vector <= mask;
END IF;
END PROCESS mask_create;
mem_rw : PROCESS (init_mem, write_pulse)
-- mem init
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_word_type;
BEGIN
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
END LOOP;
mem(write_address) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(normal)(i) = '0') THEN
mem(write_address)(i) <= portadatain(i);
mem_data_p(i) := portadatain(i);
ELSIF (mask_vector(inverse)(i) = 'X') THEN
mem(write_address)(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS mem_rw;
-- Continuous read
portbdataout <= mem(read_address);
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaiigz_io_ibuf
--
-- Description : ARRIAIIGZ IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "arriaiigz_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END arriaiigz_io_ibuf;
ARCHITECTURE arch OF arriaiigz_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaiigz_io_obuf
--
-- Description : ARRIAIIGZ IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "arriaiigz_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END arriaiigz_io_obuf;
ARCHITECTURE arch OF arriaiigz_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
SIGNAL parallelterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
g2 :for i in parallelterminationcontrol'range generate
VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : arriaiigz_ddio_in
--
-- Description : ARRIAIIGZ DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "arriaiigz_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaiigz_ddio_in;
ARCHITECTURE arch OF arriaiigz_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaiigz_ddio_oe
--
-- Description : ARRIAIIGZ DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "arriaiigz_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaiigz_ddio_oe;
ARCHITECTURE arch OF arriaiigz_ddio_oe IS
component arriaiigz_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : arriaiigz_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaiigz_ddio_out
--
-- Description : ARRIAIIGZ DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "arriaiigz_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaiigz_ddio_out;
ARCHITECTURE arch OF arriaiigz_ddio_out IS
component arriaiigz_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : arriaiigz_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: arriaiigz_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY arriaiigz_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END arriaiigz_rt_sm;
ARCHITECTURE arriaiigz_rt_sm_rtl OF arriaiigz_rt_sm IS
CONSTANT ARRIAIIGZ_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT ARRIAIIGZ_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT ARRIAIIGZ_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT ARRIAIIGZ_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT ARRIAIIGZ_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT ARRIAIIGZ_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT ARRIAIIGZ_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT ARRIAIIGZ_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT ARRIAIIGZ_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= ARRIAIIGZ_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN ARRIAIIGZ_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= ARRIAIIGZ_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= ARRIAIIGZ_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= ARRIAIIGZ_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= ARRIAIIGZ_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= ARRIAIIGZ_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= ARRIAIIGZ_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN ARRIAIIGZ_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= ARRIAIIGZ_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN ARRIAIIGZ_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN ARRIAIIGZ_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN ARRIAIIGZ_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN ARRIAIIGZ_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN ARRIAIIGZ_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= ARRIAIIGZ_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN ARRIAIIGZ_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN ARRIAIIGZ_RTOCT_DONE =>
next_state <= ARRIAIIGZ_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= ARRIAIIGZ_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END arriaiigz_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: arriaiigz_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY arriaiigz_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END arriaiigz_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF arriaiigz_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : arriaiigz_termination
--
-- Description : ARRIAIIGZ Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.arriaiigz_atom_pack.all;
USE WORK.arriaiigz_termination_aux_clock_div;
USE WORK.arriaiigz_rt_sm;
ENTITY arriaiigz_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "arriaiigz_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END arriaiigz_termination;
ARCHITECTURE arriaiigz_oct_arch OF arriaiigz_termination IS
COMPONENT arriaiigz_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT arriaiigz_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : arriaiigz_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : arriaiigz_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END arriaiigz_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : arriaiigz_termination_logic
--
-- Description : ARRIAIIGZ Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "arriaiigz_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END arriaiigz_termination_logic;
ARCHITECTURE arriaiigz_oct_logic_arch OF arriaiigz_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END arriaiigz_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package arriaiigz_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end arriaiigz_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body arriaiigz_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end arriaiigz_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY arriaiigz_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END arriaiigz_dll_gray_encoder;
ARCHITECTURE arriaiigz_dll_gray_encoder_arch OF arriaiigz_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END arriaiigz_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY arriaiigz_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END arriaiigz_dll_gray_decoder;
ARCHITECTURE arriaiigz_dll_gray_decoder_arch OF arriaiigz_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END arriaiigz_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: arriaiigz_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_dll_gray_decoder;
ENTITY arriaiigz_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END arriaiigz_ddr_delay_chain_s;
ARCHITECTURE arriaiigz_ddr_delay_chain_s_arch OF arriaiigz_ddr_delay_chain_s IS
COMPONENT arriaiigz_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : arriaiigz_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END arriaiigz_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of arriaiigz_ddr_io_reg : entity is TRUE;
end arriaiigz_ddr_io_reg;
architecture vital_arriaiigz_ddr_io_reg of arriaiigz_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_arriaiigz_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaiigz_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriaiigz_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : ARRIAIIGZ_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_pllpack.all;
use work.arriaiigz_atom_ddr_pack.all;
use work.arriaiigz_dll_gray_encoder;
ENTITY arriaiigz_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "arriaiigz_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END arriaiigz_dll;
ARCHITECTURE vital_arriaiigzdll of arriaiigz_dll is
COMPONENT arriaiigz_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in arriaiigz
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in arriaiigz
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in arriaiigz
signal pc_comp_range : integer := 0; -- new in arriaiigz
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : arriaiigz_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in arriaiigz
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_arriaiigzdll;
-------------------------------------------------------------------------------
--
-- Entity Name : ARRIAIIGZ_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
USE work.arriaiigz_pllpack.all;
use work.arriaiigz_atom_ddr_pack.all;
use work.arriaiigz_dll_gray_encoder;
use work.arriaiigz_dll_gray_decoder;
ENTITY arriaiigz_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "arriaiigz_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END arriaiigz_dll_offset_ctrl;
ARCHITECTURE vital_arriaiigzoffset of arriaiigz_dll_offset_ctrl is
COMPONENT arriaiigz_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaiigz_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : arriaiigz_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : arriaiigz_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : arriaiigz_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : arriaiigz_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_arriaiigzoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_dll_gray_decoder;
ENTITY arriaiigz_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_dqs_delay_chain_arch OF arriaiigz_dqs_delay_chain IS
-- component section
COMPONENT arriaiigz_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : arriaiigz_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : arriaiigz_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END arriaiigz_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_dqs_enable IS
GENERIC (
lpm_type : string := "arriaiigz_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_dqs_enable_arch OF arriaiigz_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END arriaiigz_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_ddr_io_reg;
use work.arriaiigz_ddr_delay_chain_s;
ENTITY arriaiigz_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_dqs_enable_ctrl_arch OF arriaiigz_dqs_enable_ctrl IS
-- component section
COMPONENT arriaiigz_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component arriaiigz_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : arriaiigz_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : arriaiigz_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : arriaiigz_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : arriaiigz_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : arriaiigz_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END arriaiigz_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "arriaiigz_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_delay_chain_arch OF arriaiigz_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END arriaiigz_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_ddr_delay_chain_s;
ENTITY arriaiigz_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_io_clock_divider_arch OF arriaiigz_io_clock_divider IS
-- component section
COMPONENT arriaiigz_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : arriaiigz_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END arriaiigz_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_ddr_io_reg;
use work.arriaiigz_ddr_delay_chain_s;
ENTITY arriaiigz_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "arriaiigz_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_output_phase_alignment_arch OF arriaiigz_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT arriaiigz_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component arriaiigz_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : arriaiigz_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : arriaiigz_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END arriaiigz_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_ddr_io_reg;
use work.arriaiigz_ddr_delay_chain_s;
ENTITY arriaiigz_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_input_phase_alignment_arch OF arriaiigz_input_phase_alignment IS
-- component section
COMPONENT arriaiigz_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component arriaiigz_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : arriaiigz_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END arriaiigz_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
use work.arriaiigz_ddr_io_reg;
ENTITY arriaiigz_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "arriaiigz_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_half_rate_input_arch OF arriaiigz_half_rate_input IS
-- component section
component arriaiigz_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : arriaiigz_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END arriaiigz_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "arriaiigz_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_io_config_arch OF arriaiigz_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END arriaiigz_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaiigz_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "arriaiigz_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE arriaiigz_dqs_config_arch OF arriaiigz_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAIIGZ_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END arriaiigz_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: arriaiigz_mac_bit_register --
-- Description: ARRIAIIGZ MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END arriaiigz_mac_bit_register;
ARCHITECTURE arch OF arriaiigz_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: arriaiigz_mac_register --
-- Description: ARRIAIIGZ MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END arriaiigz_mac_register;
ARCHITECTURE arch OF arriaiigz_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: arriaiigz_mac_multiplier --
-- Description: ARRIAIIGZ MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END arriaiigz_mac_multiplier;
ARCHITECTURE arch OF arriaiigz_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: arriaiigz_mac_mult_atom --
-- Description: Simulation model for arriaiigz mac mult atom. --
-- This model instantiates the following components. --
-- 1.arriaiigz_mac_bit_register. --
-- 2.arriaiigz_mac_register. --
-- 3.arriaiigz_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "arriaiigz_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaiigz_mac_mult;
ARCHITECTURE arch OF arriaiigz_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT arriaiigz_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaiigz_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaiigz_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : arriaiigz_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : arriaiigz_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : arriaiigz_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : arriaiigz_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_fsa_isse --
-- Description: ARRIAIIGZ first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END arriaiigz_fsa_isse;
ARCHITECTURE arch OF arriaiigz_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_first_stage_add_sub --
-- Description: ARRIAIIGZ First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END arriaiigz_first_stage_add_sub;
ARCHITECTURE arch OF arriaiigz_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_second_stage_add_accum --
-- Description: ARRIAIIGZ Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END arriaiigz_second_stage_add_accum;
ARCHITECTURE arch OF arriaiigz_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_round_block --
-- Description: ARRIAIIGZ round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END arriaiigz_round_block;
ARCHITECTURE arch OF arriaiigz_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_saturate_block --
-- Description: ARRIAIIGZ saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END arriaiigz_saturate_block;
ARCHITECTURE arch OF arriaiigz_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
IF (round = '1') THEN
max(i) <= 'X';
min(i) <= 'X';
ELSE
max(i) <= '1';
min(i) <= '0';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
IF (round = '1') THEN
min(conv_integer(datain_width) - round_width) <= '1';
ELSE
min(0) <= '1';
END IF;
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_round_saturate_block --
-- Description: ARRIAIIGZ round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.arriaiigz_round_block. --
-- 2.arriaiigz_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END arriaiigz_round_saturate_block;
ARCHITECTURE arch OF arriaiigz_round_saturate_block IS
COMPONENT arriaiigz_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaiigz_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : arriaiigz_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : arriaiigz_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_rotate_shift_block --
-- Description: ARRIAIIGZ roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END arriaiigz_rotate_shift_block;
ARCHITECTURE arch OF arriaiigz_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaiigz_carry_chain_adder --
-- Description: ARRIAIIGZ carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END arriaiigz_carry_chain_adder;
ARCHITECTURE arch OF arriaiigz_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: arriaiigz_mac_out_atom --
-- Description: Simulation model for arriaiigz mac out atom --
-- This model instantiates the following components --
-- 1.arriaiigz_mac_bit_register --
-- 2.arriaiigz_mac_register --
-- 3.arriaiigz_fsa_isse --
-- 4.arriaiigz_first_stage_add_sub --
-- 5.arriaiigz_second_stage_add_accum --
-- 6.arriaiigz_round_saturate_block --
-- 7.arriaiigz_rotate_shift_block --
-- 8.arriaiigz_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY arriaiigz_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "arriaiigz_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END arriaiigz_mac_out;
ARCHITECTURE arch OF arriaiigz_mac_out IS
COMPONENT arriaiigz_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaiigz_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaiigz_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaiigz_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaiigz_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT arriaiigz_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT arriaiigz_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaiigz_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : arriaiigz_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : arriaiigz_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : arriaiigz_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : arriaiigz_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : arriaiigz_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : arriaiigz_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : arriaiigz_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : arriaiigz_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : arriaiigz_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : arriaiigz_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : arriaiigz_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : arriaiigz_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : arriaiigz_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : arriaiigz_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : arriaiigz_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : arriaiigz_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : arriaiigz_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : arriaiigz_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : arriaiigz_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : arriaiigz_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : arriaiigz_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : arriaiigz_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : arriaiigz_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : arriaiigz_io_pad
-- Description : Simulation model for arriaiigz IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY arriaiigz_io_pad IS
GENERIC (
lpm_type : string := "arriaiigz_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END arriaiigz_io_pad;
ARCHITECTURE arch OF arriaiigz_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaiigz_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the ARRIAIIGZ PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriaiigz_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END arriaiigz_mn_cntr;
ARCHITECTURE behave of arriaiigz_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaiigz_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the ARRIAIIGZ PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriaiigz_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END arriaiigz_scale_cntr;
ARCHITECTURE behave of arriaiigz_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaiigz_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY arriaiigz_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end arriaiigz_pll_reg;
ARCHITECTURE behave of arriaiigz_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaiigz_pll
--
-- Description : Timing simulation model for the ARRIAIIGZ PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.arriaiigz_atom_pack.all;
USE work.arriaiigz_pllpack.all;
USE work.arriaiigz_mn_cntr;
USE work.arriaiigz_scale_cntr;
USE work.arriaiigz_dffe;
USE work.arriaiigz_pll_reg;
-- New Features : The list below outlines key new features in ARRIAIIGZ:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY arriaiigz_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriaiigz_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "ARRIAIIGZ";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END arriaiigz_pll;
ARCHITECTURE vital_pll of arriaiigz_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT arriaiigz_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT arriaiigz_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT arriaiigz_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT arriaiigz_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : arriaiigz_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : arriaiigz_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : arriaiigz_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : arriaiigz_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : arriaiigz_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : arriaiigz_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : arriaiigz_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : arriaiigz_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : arriaiigz_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : arriaiigz_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : arriaiigz_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : arriaiigz_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/arriaiigz_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/arriaiigz_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : arriaiigz_asmiblock
--
-- Description : ARRIAIIGZ ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_asmiblock is
generic (
lpm_type : string := "arriaiigz_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end arriaiigz_asmiblock;
architecture architecture_asmiblock of arriaiigz_asmiblock is
begin
end architecture_asmiblock; -- end of arriaiigz_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END arriaiigz_lvds_reg;
ARCHITECTURE vital_arriaiigz_lvds_reg of arriaiigz_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriaiigz_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END arriaiigz_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF arriaiigz_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE work.arriaiigz_lvds_rx_fifo_sync_ram;
ENTITY arriaiigz_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END arriaiigz_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of arriaiigz_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT arriaiigz_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : arriaiigz_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE work.arriaiigz_lvds_reg;
ENTITY arriaiigz_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END arriaiigz_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF arriaiigz_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT arriaiigz_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : arriaiigz_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : arriaiigz_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_lvds_rx_deser
--
-- Description : Timing simulation model for the arriaiigz LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaiigz_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF arriaiigz_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the arriaiigz LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaiigz_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF arriaiigz_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : arriaiigz_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY arriaiigz_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END arriaiigz_pclk_divider;
ARCHITECTURE arch OF arriaiigz_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : arriaiigz_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY arriaiigz_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END arriaiigz_select_ini_phase_dpaclk;
ARCHITECTURE trans OF arriaiigz_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : arriaiigz_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY arriaiigz_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END arriaiigz_dpa_retime_block;
ARCHITECTURE trans OF arriaiigz_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : arriaiigz_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.arriaiigz_dpa_retime_block;
ENTITY arriaiigz_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END arriaiigz_dpa_block;
ARCHITECTURE trans OF arriaiigz_dpa_block IS
COMPONENT arriaiigz_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : arriaiigz_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaiigz_LVDS_RECEIVER
--
-- Description : Timing simulation model for the arriaiigz LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) arriaiigz_lvds_rx_fifo
-- 2) arriaiigz_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) arriaiigz_lvds_rx_parallel_reg
-- 5) arriaiigz_pclk_divider
-- 6) arriaiigz_select_ini_phase_dpaclk
-- 7) arriaiigz_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaiigz_atom_pack.all;
USE work.arriaiigz_lvds_rx_bitslip;
USE work.arriaiigz_lvds_rx_fifo;
USE work.arriaiigz_lvds_rx_deser;
USE work.arriaiigz_lvds_rx_parallel_reg;
USE work.arriaiigz_lvds_reg;
USE work.arriaiigz_pclk_divider;
USE work.arriaiigz_select_ini_phase_dpaclk;
USE work.arriaiigz_dpa_block;
ENTITY arriaiigz_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "arriaiigz_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaiigz_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF arriaiigz_lvds_receiver IS
COMPONENT arriaiigz_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaiigz_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaiigz_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriaiigz_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriaiigz_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriaiigz_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT arriaiigz_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT arriaiigz_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal in_reg_data_dly : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
signal ini_dpa_clk_dly : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
process(in_reg_data)
begin
if(dpaswitch_ipd = '1') then
if(rx_input_path_delay_engineering_bits = 1) then
in_reg_data_dly <= TRANSPORT in_reg_data after 60 ps;
elsif(rx_input_path_delay_engineering_bits = 2) then
in_reg_data_dly <= TRANSPORT in_reg_data after 120 ps;
elsif(rx_input_path_delay_engineering_bits = 3) then
in_reg_data_dly <= TRANSPORT in_reg_data after 180 ps;
else
in_reg_data_dly <= in_reg_data;
end if;
else
in_reg_data_dly <= in_reg_data;
end if;
end process;
xhdl_12 <= devclrn OR devpor;
process(ini_dpa_clk)
begin
ini_dpa_clk_dly <= ini_dpa_clk;
end process;
-- input register in non-DPA mode for sampling incoming data
in_reg : arriaiigz_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : arriaiigz_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: arriaiigz_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : arriaiigz_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => ini_dpa_clk_dly,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : arriaiigz_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: arriaiigz_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: arriaiigz_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : arriaiigz_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : arriaiigz_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" ) else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : arriaiigz_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : arriaiigz_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : arriaiigz_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: arriaiigz_pseudo_diff_out --
--Description: Simulation model for ARRIAIIGZ Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "arriaiigz_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END arriaiigz_pseudo_diff_out;
ARCHITECTURE arch OF arriaiigz_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : arriaiigz_bias_logic
--
-- Description : ARRIAIIGZ Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of arriaiigz_bias_logic : ENTITY IS TRUE;
end arriaiigz_bias_logic;
ARCHITECTURE vital_bias_logic of arriaiigz_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : arriaiigz_bias_generator
--
-- Description : ARRIAIIGZ Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of arriaiigz_bias_generator : ENTITY IS TRUE;
end arriaiigz_bias_generator;
ARCHITECTURE vital_bias_generator of arriaiigz_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 202;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : arriaiigz_bias_block
--
-- Description : ARRIAIIGZ Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
ENTITY arriaiigz_bias_block IS
GENERIC (
lpm_type : string := "arriaiigz_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of arriaiigz_bias_block : ENTITY IS TRUE;
end arriaiigz_bias_block;
ARCHITECTURE vital_bias_block of arriaiigz_bias_block IS
COMPONENT arriaiigz_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT arriaiigz_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : arriaiigz_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : arriaiigz_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : arriaiigz_tsdblock
--
-- Description : ARRIAIIGZ TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaiigz_atom_pack.all;
entity arriaiigz_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "arriaiigz_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end arriaiigz_tsdblock;
architecture architecture_tsdblock of arriaiigz_tsdblock is
begin
end architecture_tsdblock; -- end of arriaiigz_tsdblock
| gpl-3.0 | b9f212e76a46f9c647fd84d59e3c888e | 0.469278 | 4.151751 | false | false | false | false |
keith-epidev/md2x | build/code/keyboard.vhdl | 1 | 4,384 | library ieee;
use ieee.std_logic_1164.all;
use work.my_lib.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keyboard is
port(
sys_clk: in std_logic;
reset: in std_logic;
PS2C: in std_logic;
PS2D: in std_logic;
output: out std_logic_vector(8*3-1 downto 0);
new_val: out std_logic;
leds: out std_logic_vector(8 downto 0)
);
end keyboard;
architecture Behavioral of keyboard is
type state_type is (wait_start_bit, get_bits, get_parity, wait_stop);
signal state: state_type;
signal clk, last_clk, data: std_logic;
signal PS2C_filter,PS2D_filter: std_logic_vector(7 downto 0);
signal bit_count: std_logic_vector(3 downto 0);
signal temp : std_logic_vector(7 downto 0);
signal parity : std_logic;
signal available : std_logic;
signal calc_parity: std_logic;
signal delay_count: std_logic_vector(7 downto 0);
signal ready : std_logic;
signal newval : std_logic;
signal output_buffer : std_logic_vector(8*3-1 downto 0);
signal temp_buffer : std_logic_vector(8*3-1 downto 0);
-- signal shift1,shift2,shift3: std_logic_vector(10 downto 0);
-- signal keyval1s,keyval2s,keyval3s: std_logic_vector(7 downto 0);
-- signal bit_count: std_logic_vector(3 downto 0);
-- constant bit_count_max: std_logic_vector(3 downto 0) := "1011";
begin
calc_parity <= temp(0) xor temp(1) xor temp(2) xor temp(3) xor temp(4) xor temp(5) xor temp(6) xor temp(7);
output <= output_buffer;
new_val <= newval;
leds(7 downto 0) <= temp;
leds(8) <= data;
-- leds <= "1000" when state = wait_start_bit else999999999999
-- "0100" when state = get_bits else
-- "0010" when state = get_parity else
-- "0001" when state = wait_stop else
-- "0000";
--filter the signal
filterC: process(sys_clk,reset)
begin
if reset = '1' then
PS2C_filter <= (others=>'0');
clk <= '1';
last_clk <= '1';
else if (sys_clk'event and sys_clk ='1' ) then
--shift down
PS2C_filter(7) <= PS2C;
PS2C_filter(6 downto 0) <= PS2C_filter(7 downto 1);
if PS2C_filter = X"FF" then
clk <= '1';
last_clk <= clk;
else if PS2C_filter = X"00" then
clk <= '0';
last_clk <= clk;
end if;
end if;
end if;
end if;
end process filterC;
--filter the signal
filterD: process(sys_clk,reset)
begin
if reset = '1' then
PS2D_filter <= (others=>'0');
data <= '1';
else if (sys_clk'event and sys_clk ='1' ) then
--shift down
PS2D_filter(7) <= PS2D;
PS2D_filter(6 downto 0) <= PS2D_filter(7 downto 1);
if PS2D_filter = X"FF" then
data <= '1';
else if PS2D_filter = X"00" then
data <= '0';
end if;
end if;
end if;
end if;
end process filterD;
--state machine
skey: process(sys_clk,reset)
begin
if(reset = '1') then
state <= wait_start_bit;
bit_count <= (others=>'0');
output_buffer <= (others=>'0');
newval <= '0';
ready <= '0';
available <= '0';
else if (sys_clk'event and sys_clk = '0') then
case state is
when wait_start_bit =>
if(last_clk = '1' and clk = '0') then
if(data = '0')then
state <= get_bits;
end if;
end if;
if(available = '1')then
if(delay_count= "11111111")then
available <= '0';
delay_count <= (others=>'0');
temp_buffer <= (others=>'0');
output_buffer <= temp_buffer;
else
delay_count <= delay_count + 1;
end if;
end if;
when get_bits =>
delay_count <= (others=>'0');
if(last_clk = '1' and clk = '0') then
temp <= data & temp(7 downto 1) ;
if(bit_count = 7)then
state <= get_parity;
bit_count <= (others => '0');
else
bit_count <= bit_count +1;
end if;
end if;
when get_parity =>
if(last_clk = '1' and clk = '0') then
parity <= data;
state <= wait_stop;
end if;
when wait_stop =>
if(last_clk = '1' and clk = '0') then
state <= wait_start_bit;
temp_buffer <= temp & temp_buffer(3*8-1 downto 8);
available <= '1';
end if;
end case;
end if;
end if;
end process skey;
end Behavioral; | gpl-2.0 | 9a087a5dd51d224313ca9070cd1cff88 | 0.562272 | 2.857888 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_axi_bram_ctrl_0_0/synth/base_zynq_design_axi_bram_ctrl_0_0.vhd | 1 | 16,091 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY base_zynq_design_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END base_zynq_design_axi_bram_ctrl_0_0;
ARCHITECTURE base_zynq_design_axi_bram_ctrl_0_0_arch OF base_zynq_design_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF base_zynq_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "base_zynq_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "base_zynq_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END base_zynq_design_axi_bram_ctrl_0_0_arch;
| gpl-3.0 | 6d722422a48dcd9acf95b1ce3285fe69 | 0.676527 | 3.072561 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/uart_fifo_inst.vhd | 1 | 213 | uart_fifo_inst : uart_fifo PORT MAP (
clock => clock_sig,
data => data_sig,
rdreq => rdreq_sig,
wrreq => wrreq_sig,
empty => empty_sig,
full => full_sig,
q => q_sig,
usedw => usedw_sig
);
| apache-2.0 | 02d3f9510ec7776e69574e9cb7c7f929 | 0.558685 | 2.448276 | false | false | false | false |
EPiCS/reconos | pcores/reconos_fifo_v1_00_a/hdl/vhdl/reconos_fifo.vhd | 2 | 4,662 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - FIFO
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple unidirectional FIFO accessible on both sides
-- from the hardware via the known FIFO interface.
--
-- REMARK: Different clocks for FIFO-Rd and FIFO-Wr are
-- not supported yet. FIFO_S_Clk is used and
-- FIFO_M_Clk are just added for the future.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity reconos_fifo is
generic (
-- FIFO parameters
C_FIFO_DEPTH : integer := 32;
C_FIFO_WIDTH : integer := 32
);
port (
-- FIFO ports
FIFO_S_Clk : in std_logic;
FIFO_S_Data : out std_logic_vector(31 downto 0);
FIFO_S_Fill : out std_logic_vector(15 downto 0);
FIFO_S_Empty : out std_logic;
FIFO_S_RE : in std_logic;
FIFO_M_Clk : in std_logic;
FIFO_M_Data : in std_logic_vector(31 downto 0);
FIFO_M_Rem : out std_logic_vector(15 downto 0);
FIFO_M_Full : out std_logic;
FIFO_M_WE : in std_logic;
FIFO_Rst : in std_logic;
FIFO_Has_Data : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of FIFO_S_Clk : signal is "Clk";
attribute SIGIS of FIFO_M_Clk : signal is "Clk";
attribute SIGIS of FIFO_Rst : signal is "Rst";
attribute SIGIS of FIFO_Has_Data : signal is "Intr_Level_High";
end entity reconos_fifo;
architecture implementation of reconos_fifo is
-- Definition of FIFO-Memory
-- No Block-RAM because the FIFO depth should be small (around 32)
type MEM_T is array (0 to C_FIFO_DEPTH - 1) of std_logic_vector(31 downto 0);
signal fifo : MEM_T;
signal m_wrptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_rdptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_fill : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal m_rem : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_empty : std_logic;
signal m_full : std_logic;
signal s_dout : std_logic_vector(31 downto 0);
signal m_din : std_logic_vector(31 downto 0);
signal pad_16 : std_logic_vector(15 - clog2(C_FIFO_DEPTH) downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
-- this has the intended effect in sythesis (it is infact the same signal)
-- but causes a different behaviour in simulation
clk <= FIFO_S_Clk;
rst <= FIFO_Rst;
pad_16 <= (others => '0');
FIFO_Has_Data <= not s_empty;
FIFO_S_Data <= s_dout;
m_din <= FIFO_M_Data;
FIFO_S_Fill <= pad_16 & s_fill;
FIFO_M_Rem <= pad_16 & m_rem;
FIFO_S_Empty <= s_empty;
FIFO_M_Full <= m_full;
s_fill <= m_wrptr - s_rdptr - 1;
m_rem <= s_rdptr - m_wrptr - 1;
fifo_proc : process(clk,rst) is
begin
if rst = '1' then
s_rdptr <= (others => '0');
m_wrptr <= (others => '0');
s_empty <= '1';
m_full <= '0';
elsif rising_edge(clk) then
-- writing into fifo which is not full
if FIFO_M_WE = '1' and m_full = '0' then
fifo(CONV_INTEGER(m_wrptr)) <= m_din;
m_wrptr <= m_wrptr + 1;
if or_reduce(m_rem) = '0' then
m_full <= '1';
end if;
-- since reading from an empty FIFO has no effect
-- after writing into a FIFO its never empty
s_empty <= '0';
end if;
-- reading from fifo which is not empty
if FIFO_S_RE = '1' and s_empty = '0' then
s_rdptr <= s_rdptr + 1;
if or_reduce(s_fill) = '0' then
s_empty <= '1';
end if;
-- since writing into a full FIFO has no effect
-- after reading from a FIFO its never full
m_full <= '0';
end if;
-- do not change status if reading and writing concurrently
if (FIFO_M_WE = '1' and m_full = '0')
and (FIFO_S_RE = '1' and s_empty = '0') then
s_empty <= s_empty;
m_full <= m_full;
end if;
end if;
end process fifo_proc;
s_dout <= fifo(CONV_INTEGER(s_rdptr));
end implementation;
| gpl-2.0 | d2be51ab72bada6f44fb6e99cfc67ed8 | 0.545377 | 3.044415 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_decoder.vhd | 1 | 30,070 | -------------------------------------------------------------------------------
--
-- The decoder unit.
-- Implements the instruction opcodes and controls all units of the T400 core.
--
-- $Id: t400_decoder.vhd,v 1.7 2008-05-01 19:49:55 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_decoder is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
out_en_i : in boolean;
in_en_i : in boolean;
icyc_en_i : in boolean;
-- Module Control Interface -----------------------------------------------
pc_op_o : out pc_op_t;
stack_op_o : out stack_op_t;
dmem_op_o : out dmem_op_t;
b_op_o : out b_op_t;
skip_op_o : out skip_op_t;
alu_op_o : out alu_op_t;
io_l_op_o : out io_l_op_t;
io_d_op_o : out io_d_op_t;
io_g_op_o : out io_g_op_t;
io_in_op_o : out io_in_op_t;
sio_op_o : out sio_op_t;
dec_data_o : out dec_data_t;
en_o : out dw_t;
-- Skip Interface ---------------------------------------------------------
skip_i : in boolean;
skip_lbi_i : in boolean;
is_lbi_o : out boolean;
int_i : in boolean;
-- Program Memory Interface -----------------------------------------------
pm_addr_i : in pc_t;
pm_data_i : in byte_t
);
end t400_decoder;
library ieee;
use ieee.numeric_std.all;
use work.t400_mnemonic_pack.all;
architecture rtl of t400_decoder is
signal cyc_cnt_q : unsigned(2 downto 0);
signal ibyte1_q,
ibyte2_q : byte_t;
signal opcode_s : byte_t;
signal second_cyc_q : boolean;
signal mnemonic_rec_s : mnemonic_rec_t;
signal mnemonic_s,
mnemonic_q : mnemonic_t;
signal multi_byte_s,
multi_byte_q : boolean;
signal last_cycle_s : boolean;
signal force_mc_s : boolean;
signal en_q : dw_t;
signal set_en_s : boolean;
signal ack_int_s : boolean;
begin
-----------------------------------------------------------------------------
-- Theory of operation:
--
-- a) One instruction cycle lasts at least 4 ck_i cycles.
-- b) PC for instruction/parameter fetch must be valid during cycle 2.
-- => cycle 2 is the opcode fetch cycle
-- c) Cycle 3 is the opcode decode cycle.
-- => opcode_s is valid with cycle 3
-- d) mnemonic_q is then valid with cycle 0 until end of instruction.
-- So is ibyte1_q.
-- e) PC for is incremented during last instruction cycle.
-- => fetch of either new instruction or second instruction byte
-- f) Second instruction byte is saved in ibyte2_q for cycle 0.
-- Valid until end of instruction.
--
-- Constraints:
--
-- a) PC of next instruction must be pushed in cycle 0 or 1.
-- b) PC for next instruction must be poped latest in cycle 1.
-- c) PC for next instruction can only be calculated latest in cycle 1.
-- d) IO output is enabled by out_en_i
-- e) IO inputs are sampled with in_en_i
--
-- d) and e) are required for proper timing in relation to phi1
-- (SK clock/sync output).
--
-- Conventions:
--
-- a) ALU operations take place in cycle 1.
--
-----------------------------------------------------------------------------
last_cycle_s <= (not multi_byte_q and
not second_cyc_q and not force_mc_s)
or
second_cyc_q;
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the various sequential elements.
-- Cycle counter:
-- It identifies the execution cycle of the
-- current instruction.
-- Instruction registers:
-- They save the first and second byte of an instruction for
-- further processing.
-- New instruction flag:
-- Indicates when a new instruction is fetched from the program
-- memory. Implemented as a flip-flop to control the multiplexer
-- which saves power by gating the combinational opcode decoder.
-- Mnemonic register:
-- Latches the decoded mnemonic of the current instruction.
-- Multi byte flag:
-- Latches the decoded multi byte status information.
--
seq: process (ck_i, por_i)
begin
if por_i then
cyc_cnt_q <= to_unsigned(1, cyc_cnt_q'length);
second_cyc_q <= false;
ibyte1_q <= (others => '0');
ibyte2_q <= (others => '0');
mnemonic_q <= MN_CLRA;
multi_byte_q <= false;
en_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
mnemonic_q <= MN_CLRA;
multi_byte_q <= false;
cyc_cnt_q <= (others => '0');
en_q <= (others => '0');
elsif ck_en_i then
-- cycle counter ------------------------------------------------------
if icyc_en_i then
-- new instruction cycle started
cyc_cnt_q <= (others => '0');
elsif cyc_cnt_q /= 4 then
cyc_cnt_q <= cyc_cnt_q + 1;
end if;
-- second cycle flag --------------------------------------------------
if icyc_en_i then
if not last_cycle_s then
second_cyc_q <= true;
else
second_cyc_q <= false;
end if;
end if;
-- instruction byte 1 and mnemonic info -------------------------------
if icyc_en_i and last_cycle_s then
if not ack_int_s then
-- update instruction descriptors in normal mode
ibyte1_q <= pm_data_i;
mnemonic_q <= mnemonic_s;
multi_byte_q <= multi_byte_s;
else
-- force NOP instruction when vectoring to interrupt routine
ibyte1_q <= "01000100";
mnemonic_q <= MN_NOP;
multi_byte_q <= false;
end if;
end if;
-- instruction byte 2 -------------------------------------------------
if icyc_en_i and not last_cycle_s then
ibyte2_q <= pm_data_i;
end if;
-- EN register --------------------------------------------------------
if set_en_s then
en_q <= ibyte2_q(dw_range_t);
elsif ack_int_s then
-- reset interrupt enable when INT has been acknowledged
en_q(1) <= '0';
end if;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Opcode multiplexer
-----------------------------------------------------------------------------
opcode_s <= pm_data_i
when icyc_en_i else
ibyte1_q;
-----------------------------------------------------------------------------
-- Opcode decoder table
--
mnemonic_rec_s <= decode_opcode_f(opcode => opcode_s,
opt_type => opt_type_g);
--
mnemonic_s <= mnemonic_rec_s.mnemonic;
multi_byte_s <= mnemonic_rec_s.multi_byte;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process decoder_ctrl
--
-- Purpose:
-- Implements the controlling logic of the decoder module.
--
decoder_ctrl: process (icyc_en_i,
out_en_i, in_en_i,
cyc_cnt_q,
mnemonic_q, second_cyc_q, last_cycle_s,
ibyte1_q, ibyte2_q,
skip_i, skip_lbi_i,
en_q, int_i,
pm_addr_i, pm_data_i)
variable cyc_v : natural range 0 to 4;
variable t41x_type_v,
t420_type_v : boolean;
variable en_int_v : boolean;
begin
-- default assignments
pc_op_o <= PC_NONE;
stack_op_o <= STACK_NONE;
dmem_op_o <= DMEM_RB; -- default is read via B
b_op_o <= B_NONE;
skip_op_o <= SKIP_NONE;
alu_op_o <= ALU_NONE;
io_l_op_o <= IOL_NONE;
io_d_op_o <= IOD_NONE;
io_g_op_o <= IOG_NONE;
io_in_op_o <= IOIN_NONE;
sio_op_o <= SIO_NONE;
dec_data_o <= (others => '0');
is_lbi_o <= false;
set_en_s <= false;
force_mc_s <= false;
en_int_v := true;
ack_int_s <= false;
cyc_v := to_integer(cyc_cnt_q);
-- determine type
t41x_type_v := opt_type_g = t400_opt_type_410_c;
t420_type_v := opt_type_g = t400_opt_type_420_c;
if icyc_en_i then
-- immediately increment program counter
-- this happens at two occasions:
-- a) right before new mnemonic becomes valid
-- b) before the second instruction cycle begins
pc_op_o <= PC_INC_PC;
end if;
if icyc_en_i and last_cycle_s then
-- update skip state when last instruction cycle ends
skip_op_o <= SKIP_UPDATE;
end if;
-- skip instruction execution
if not skip_i then
-- implement instruction control
case mnemonic_q is
-- Mnemonic ASC -------------------------------------------------------
when MN_ASC =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD_C;
skip_op_o <= SKIP_CARRY;
end if;
-- Mnemonic ADD -------------------------------------------------------
when MN_ADD =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD;
end if;
-- Mnemonic ADT -------------------------------------------------------
when MN_ADT =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD_10;
end if;
-- Mnemonic AISC ------------------------------------------------------
when MN_AISC =>
dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_ADD_DEC;
skip_op_o <= SKIP_CARRY;
end if;
-- Mnemonic CASC ------------------------------------------------------
when MN_CASC =>
case cyc_v is
when 0 =>
alu_op_o <= ALU_COMP;
when 1 =>
alu_op_o <= ALU_ADD_C;
skip_op_o <= SKIP_CARRY;
when others =>
null;
end case;
-- Mnemonic CLRA ------------------------------------------------------
when MN_CLRA =>
if cyc_v = 1 then
alu_op_o <= ALU_CLRA;
end if;
-- Mnemonic COMP ------------------------------------------------------
when MN_COMP =>
if cyc_v = 1 then
alu_op_o <= ALU_COMP;
end if;
-- Mnemonic NOP -------------------------------------------------------
when MN_NOP =>
-- do nothing
null;
-- Mnemonic C ---------------------------------------------------------
when MN_C =>
if cyc_v = 1 then
if ibyte1_q(4) = '1' then
alu_op_o <= ALU_RC;
else
alu_op_o <= ALU_SC;
end if;
end if;
-- Mnemonic XOR -------------------------------------------------------
when MN_XOR =>
if cyc_v = 1 then
alu_op_o <= ALU_XOR;
end if;
-- Mnemonic JID -------------------------------------------------------
when MN_JID =>
force_mc_s <= true;
en_int_v := false;
dec_data_o(byte_t'range) <= pm_data_i;
if cyc_v = 1 then
if not second_cyc_q then
-- first cycle: load PC from A and M
pc_op_o <= PC_LOAD_A_M;
else
-- second cycle: load PC from program memory
pc_op_o <= PC_LOAD_8;
end if;
end if;
if icyc_en_i and not second_cyc_q then
-- do not increment PC for second instruction cycle
pc_op_o <= PC_NONE;
end if;
-- Mnemonic JMP -------------------------------------------------------
when MN_JMP =>
en_int_v := false;
dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
if second_cyc_q and cyc_v = 1 then
pc_op_o <= PC_LOAD;
end if;
-- Mnemonic JP_JSRP ---------------------------------------------------
when MN_JP_JSRP =>
en_int_v := false;
-- universal decoder data
dec_data_o <= '0' & "01" & ibyte1_q(6 downto 0);
if cyc_v = 1 then
if pm_addr_i(9 downto 7) = "001" then
-- JP within pages 2 & 3
pc_op_o <= PC_LOAD_7;
elsif ibyte1_q(6) = '1' then
-- JP outside of pages 2 & 3
pc_op_o <= PC_LOAD_6;
else
-- JSRP to page 2
pc_op_o <= PC_LOAD;
stack_op_o <= STACK_PUSH;
end if;
end if;
-- Mnemonic JSR -------------------------------------------------------
when MN_JSR =>
en_int_v := false;
dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
if second_cyc_q and cyc_v = 1 then
pc_op_o <= PC_LOAD;
stack_op_o <= STACK_PUSH;
end if;
-- Mnemonic RET -------------------------------------------------------
when MN_RET =>
en_int_v := false;
if cyc_v = 1 then
pc_op_o <= PC_POP;
stack_op_o <= STACK_POP;
if t420_type_v then
-- always restore skip state in case this was an interrupt
skip_op_o <= SKIP_POP;
end if;
end if;
-- Mnemonic RETSK -----------------------------------------------------
when MN_RETSK =>
en_int_v := false;
if cyc_v = 1 then
pc_op_o <= PC_POP;
stack_op_o <= STACK_POP;
skip_op_o <= SKIP_NOW;
end if;
-- Mnemonic LD --------------------------------------------------------
when MN_LD =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_M;
b_op_o <= B_XOR_BR;
end if;
-- Mnemonic LDD_XAD ---------------------------------------------------
when MN_LDD_XAD =>
-- preload decoder data
dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
if second_cyc_q then
case ibyte2_q(7 downto 6) is
-- LDD
when "00" =>
if not t41x_type_v then
case cyc_v is
when 1 =>
dmem_op_o <= DMEM_RDEC;
when 2 =>
alu_op_o <= ALU_LOAD_M;
when others =>
null;
end case;
end if;
-- XAD
when "10" =>
if not t41x_type_v or
unsigned(ibyte2_q(b_range_t)) = 63 then
case cyc_v is
when 1 =>
dmem_op_o <= DMEM_RDEC;
when 2 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WDEC_SRC_A;
when others =>
null;
end case;
end if;
when others =>
null;
end case;
end if;
-- Mnemonic LQID ------------------------------------------------------
when MN_LQID =>
force_mc_s <= true;
en_int_v := false;
if not second_cyc_q then
-- first cycle: push PC and set PC from A/M,
-- read IOL from program memory
if cyc_v = 1 then
stack_op_o <= STACK_PUSH;
pc_op_o <= PC_LOAD_A_M;
end if;
if out_en_i then
io_l_op_o <= IOL_LOAD_PM;
end if;
else
if cyc_v = 1 then
-- second cycle: pop PC
stack_op_o <= STACK_POP;
pc_op_o <= PC_POP;
end if;
end if;
if icyc_en_i and not second_cyc_q then
-- do not increment PC for second instruction cycle
pc_op_o <= PC_NONE;
end if;
-- Mnemonic RMB -------------------------------------------------------
when MN_RMB =>
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_RES_BIT;
-- select bit to be reset
case ibyte1_q(dw_range_t) is
when "1100" =>
dec_data_o(dw_range_t) <= "0001";
when "0101" =>
dec_data_o(dw_range_t) <= "0010";
when "0010" =>
dec_data_o(dw_range_t) <= "0100";
when "0011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic SMB -------------------------------------------------------
when MN_SMB =>
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_SET_BIT;
-- select bit to be set
case ibyte1_q(dw_range_t) is
when "1101" =>
dec_data_o(dw_range_t) <= "0001";
when "0111" =>
dec_data_o(dw_range_t) <= "0010";
when "0110" =>
dec_data_o(dw_range_t) <= "0100";
when "1011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic STII ------------------------------------------------------
when MN_STII =>
dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_SRC_DEC;
b_op_o <= B_INC_BD;
end if;
-- Mnemonic X ---------------------------------------------------------
when MN_X =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_XOR_BR;
end if;
-- Mnemonic XDS -------------------------------------------------------
when MN_XDS =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
case cyc_v is
when 1 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_DEC_BD;
when 2 =>
b_op_o <= B_XOR_BR;
skip_op_o <= SKIP_BD_UFLOW;
when others =>
null;
end case;
-- Mnemonic XIS -------------------------------------------------------
when MN_XIS =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
case cyc_v is
when 1 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_INC_BD;
when 2 =>
b_op_o <= B_XOR_BR;
skip_op_o <= SKIP_BD_OFLOW;
when others =>
null;
end case;
-- Mnemonic CAB -------------------------------------------------------
when MN_CAB =>
if cyc_v = 1 then
b_op_o <= B_SET_BD;
end if;
-- Mnemonic CBA -------------------------------------------------------
when MN_CBA =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_BD;
end if;
-- Mnemonic LBI -------------------------------------------------------
when MN_LBI =>
is_lbi_o <= true;
en_int_v := false;
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
dec_data_o(bd_range_t) <= ibyte1_q(bd_range_t);
if cyc_v = 1 and not skip_lbi_i then
-- increment Bd by 1
b_op_o <= B_SET_B_INC;
skip_op_o <= SKIP_LBI;
end if;
-- Mnemonic XABR ------------------------------------------------------
when MN_XABR =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_BR;
b_op_o <= B_SET_BR;
end if;
-- Mnemonic SKC -------------------------------------------------------
when MN_SKC =>
if cyc_v = 1 then
skip_op_o <= SKIP_C;
end if;
-- Mnemonic SKE -------------------------------------------------------
when MN_SKE =>
if cyc_v = 1 then
skip_op_o <= SKIP_A_M;
end if;
-- Mnemonic SKMBZ -----------------------------------------------------
when MN_SKMBZ =>
if cyc_v = 1 then
skip_op_o <= SKIP_M_BIT;
-- select bit to be checked
case ibyte1_q is
when "00000001" =>
dec_data_o(dw_range_t) <= "0001";
when "00010001" =>
dec_data_o(dw_range_t) <= "0010";
when "00000011" =>
dec_data_o(dw_range_t) <= "0100";
when "00010011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic SKT -------------------------------------------------------
when MN_SKT =>
if cyc_v = 1 then
skip_op_o <= SKIP_TIMER;
end if;
-- Mnemonic XAS -------------------------------------------------------
when MN_XAS =>
if out_en_i then
sio_op_o <= SIO_LOAD;
alu_op_o <= ALU_LOAD_SIO;
end if;
-- Mnemonic EXT -------------------------------------------------------
when MN_EXT =>
if second_cyc_q then
case ibyte2_q is
-- CAMQ
when "00111100" =>
if out_en_i then
io_l_op_o <= IOL_LOAD_AM;
end if;
-- CQMA
when "00101100" =>
if not t41x_type_v and in_en_i then
io_l_op_o <= IOL_OUTPUT_Q;
alu_op_o <= ALU_LOAD_Q;
dmem_op_o <= DMEM_WB_SRC_Q;
end if;
-- SKGZ
when "00100001" =>
if in_en_i then
skip_op_o <= SKIP_G_ZERO;
end if;
-- SKGBZ
when "00000001" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0001";
end if;
when "00010001" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0010";
end if;
when "00000011" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0100";
end if;
when "00010011" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "1000";
end if;
-- ING
when "00101010" =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_G;
end if;
-- INL
when "00101110" =>
if in_en_i then
io_l_op_o <= IOL_OUTPUT_L;
alu_op_o <= ALU_LOAD_Q;
dmem_op_o <= DMEM_WB_SRC_Q;
end if;
-- ININ
when "00101000" =>
if not t41x_type_v and in_en_i then
alu_op_o <= ALU_LOAD_IN;
end if;
-- INIL
when "00101001" =>
if not t41x_type_v and in_en_i then
alu_op_o <= ALU_LOAD_IL;
io_in_op_o <= IOIN_INIL;
end if;
-- OBD
when "00111110" =>
if out_en_i then
io_d_op_o <= IOD_LOAD;
end if;
-- OMG
when "00111010" =>
if out_en_i then
io_g_op_o <= IOG_LOAD_M;
end if;
-- multiple codes
when others =>
-- apply default decoder output, largest required vector
dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
-- LBI
if ibyte2_q(7 downto 6) = "10" and not t41x_type_v then
is_lbi_o <= true;
en_int_v := false;
if cyc_v > 0 and not skip_lbi_i then
b_op_o <= B_SET_B;
skip_op_o <= SKIP_LBI;
end if;
end if;
-- LEI
if ibyte2_q(7 downto 4) = "0110" and in_en_i then
-- dec_data_o applied by default
set_en_s <= true;
-- acknowledge pending interrupt when EN(1) is not
-- enabled - will clear them until interrupts are
-- enabled with EN(1) = '1'
if en_q(1) = '0' then
io_in_op_o <= IOIN_INTACK;
end if;
end if;
-- OGI
if ibyte2_q(7 downto 4) = "0101" and out_en_i and
not t41x_type_v then
-- dec_data_o applied by default
io_g_op_o <= IOG_LOAD_DEC;
end if;
end case;
end if;
when others =>
null;
end case;
end if;
-- Interrupt handling -----------------------------------------------------
if t420_type_v and
en_q(1) = '1' and int_i and en_int_v then
if last_cycle_s then
if cyc_v = 1 then
stack_op_o <= STACK_PUSH;
end if;
if icyc_en_i then
ack_int_s <= true;
io_in_op_o <= IOIN_INTACK;
pc_op_o <= PC_INT;
-- push skip state that was determined by current instruction
-- and will be valid for the next instruction which is delayed
-- by the interrupt
skip_op_o <= SKIP_PUSH;
end if;
end if;
end if;
end process decoder_ctrl;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
en_o <= en_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/05 14:20:34 arniml
-- interface comments added
--
-- Revision 1.5 2006/05/28 15:32:14 arniml
-- execute virtual NOP at location 0x0ff when vectoring to interrupt routine
--
-- Revision 1.4 2006/05/27 19:14:18 arniml
-- interrupt functionality added
--
-- Revision 1.3 2006/05/22 00:02:36 arniml
-- instructions ININ and INIL implemented
--
-- Revision 1.2 2006/05/07 02:24:16 arniml
-- fix sensitivity list
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | e1ee27d4bff3e1a89285278e47c9f14a | 0.408314 | 4.091156 | false | false | false | false |
alvieboy/xtc-base | fifo.vhd | 1 | 3,122 | --
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11;
datawidth: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(datawidth-1 downto 0);
read : out std_logic_vector(datawidth-1 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(datawidth-1 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
| bsd-3-clause | 2d0ee2f3cb1140b168ebfbd632683c83 | 0.644459 | 3.681604 | false | false | false | false |
freecores/t400 | rtl/vhdl/system/t420.vhd | 1 | 8,108 | -------------------------------------------------------------------------------
--
-- T420 system toplevel.
--
-- $Id: t420.vhd,v 1.8 2008-08-28 18:51:58 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t420 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_8_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t420;
use work.t400_system_comp_pack.t420_notri;
architecture struct of t420 is
signal io_l_from_t420_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t420_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_from_t420_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
begin
-----------------------------------------------------------------------------
-- T420 without tri-states
-----------------------------------------------------------------------------
t420_notri_b : t420_notri
generic map (
opt_type_g => t400_opt_type_420_c,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => opt_microbus_g,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => cko_i,
io_l_i => io_l_b,
io_l_o => io_l_from_t420_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t420_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_b,
io_g_o => io_g_from_t420_s,
io_g_en_o => io_g_en_s,
io_in_i => io_in_i,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t420_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 3 downto 0 generate
io_d_o(idx) <= io_d_from_t420_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 3 downto 0 generate
io_g_b(idx) <= io_g_from_t420_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.7 2008/08/23 11:19:20 arniml
-- added name keyword
--
-- Revision 1.6 2006/06/11 13:49:18 arniml
-- * hand generic opt_type_g down to t420_notri
-- * full generic list
--
-- Revision 1.5 2006/06/05 20:04:11 arniml
-- connect microbus generic
--
-- Revision 1.4 2006/05/23 01:16:05 arniml
-- routi CKO to t400_core
--
-- Revision 1.3 2006/05/20 02:49:04 arniml
-- select CK divide by 8
--
-- Revision 1.2 2006/05/17 00:38:31 arniml
-- connect missing input direction for IO G
--
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 26928c45095a2dbe2f3ab04795bc329f | 0.539591 | 2.953734 | false | false | false | false |
EPiCS/reconos | demos/matrixmul/hw/hwt_matrixmul_v2_00_a/hdl/vhdl/matrixmultiplier.vhd | 2 | 4,284 | ------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to 31);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to 31);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to 31);
o_RAM_C_WE : out std_logic
);
end matrixmultiplier;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture Behavioral of matrixmultiplier is
type STATE_TYPE is (
STATE_IDLE,
STATE_LOAD,
STATE_LOAD_WAIT,
STATE_SUM,
STATE_DELAY_1,
STATE_DELAY_2,
STATE_STORE,
STATE_STORE_WAIT,
STATE_FINISH_CYCLE
);
signal state : STATE_TYPE;
signal temp : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
signal prod,delay : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
begin
multiply : process(clk, reset, start) is
variable j : integer := 0;
variable k : integer := 0;
begin
if (reset = '1') then
done <= '0';
o_RAM_A_Addr <= (others=>'0');
o_RAM_B_Addr <= (others=>'0');
o_RAM_C_Addr <= (others=>'0');
o_RAM_C_Data <= (others=>'0');
o_RAM_C_WE <= '0';
state <= STATE_IDLE;
elsif (clk'event and clk = '1') then
o_RAM_C_WE <= '0';
o_RAM_C_Data <= (others=>'0');
case state is
when STATE_IDLE =>
done <= '0';
if (start = '1') then
j := 0;
k := 0;
temp <= (others=>'0');
state <= STATE_LOAD;
end if;
when STATE_LOAD =>
o_RAM_A_Addr <= conv_std_logic_vector(integer(k), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_B_Addr <= conv_std_logic_vector(integer(k*G_LINE_LEN_MATRIX+j), G_RAM_ADDR_WIDTH_MATRIX_B);
k := k + 1;
state <= STATE_LOAD_WAIT;
when STATE_LOAD_WAIT =>
state <= STATE_DELAY_1;
when STATE_DELAY_1 =>
state <= STATE_DELAY_2;
when STATE_DELAY_2 =>
state <= STATE_SUM;
when STATE_SUM =>
temp <= temp + prod;
if (k = G_LINE_LEN_MATRIX) then
k := 0;
state <= STATE_STORE;
else
state <= STATE_LOAD;
end if;
when STATE_STORE =>
o_RAM_C_Addr <= conv_std_logic_vector(integer(j), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_C_WE <= '1';
o_RAM_C_Data <= temp;
state <= STATE_STORE_WAIT;
when STATE_STORE_WAIT =>
o_RAM_C_WE <= '0';
state <= STATE_FINISH_CYCLE;
when STATE_FINISH_CYCLE =>
j := j + 1;
if (j = G_LINE_LEN_MATRIX) then
j := 0;
done <= '1';
state <= STATE_IDLE;
else
temp <= (others => '0');
state <= STATE_LOAD;
end if;
end case;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
delay <= conv_std_logic_vector(signed(i_RAM_A_Data)*signed(i_RAM_B_Data),G_RAM_DATA_WIDTH);
prod <= delay;
end if;
end process;
end Behavioral;
| gpl-2.0 | e33538ed7793e706293d5a1c8c3eee44 | 0.501401 | 3.014778 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiv_pcie_hip_components.vhd | 1 | 71,791 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package STRATIXIV_PCIE_HIP_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function alpha_tolower (given_string : string) return string;
-- GENERIC utility functions END
--
-- stratixiv_pciehip_pciexp_dcfiforam
--
COMPONENT stratixiv_pciehip_pciexp_dcfiforam
GENERIC (
addr_width : INTEGER := 4;
data_width : INTEGER := 32
);
PORT (
data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
wrclock : IN STD_LOGIC;
rdclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_hssi_pcie_hip
--
COMPONENT stratixiv_hssi_pcie_hip
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrpl : VitalDelayType01 := DefpropDelay01;
tipd_bistscanen : VitalDelayType01 := DefpropDelay01;
tipd_bistscanin : VitalDelayType01 := DefpropDelay01;
tipd_bisttesten : VitalDelayType01 := DefpropDelay01;
tipd_coreclkin : VitalDelayType01 := DefpropDelay01;
tipd_corecrst : VitalDelayType01 := DefpropDelay01;
tipd_corepor : VitalDelayType01 := DefpropDelay01;
tipd_corerst : VitalDelayType01 := DefpropDelay01;
tipd_coresrst : VitalDelayType01 := DefpropDelay01;
tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cplpending : VitalDelayType01 := DefpropDelay01;
tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01;
tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01;
tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01;
tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01;
tipd_dlreqwake : VitalDelayType01 := DefpropDelay01;
tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01;
tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01;
tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01;
tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01;
tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmirden : VitalDelayType01 := DefpropDelay01;
tipd_lmiwren : VitalDelayType01 := DefpropDelay01;
tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanen : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanin : VitalDelayType01 := DefpropDelay01;
tipd_pclkcentral : VitalDelayType01 := DefpropDelay01;
tipd_pclkch0 : VitalDelayType01 := DefpropDelay01;
tipd_phyrst : VitalDelayType01 := DefpropDelay01;
tipd_physrst : VitalDelayType01 := DefpropDelay01;
tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pldclk : VitalDelayType01 := DefpropDelay01;
tipd_pldrst : VitalDelayType01 := DefpropDelay01;
tipd_pldsrst : VitalDelayType01 := DefpropDelay01;
tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanen : VitalDelayType01 := DefpropDelay01;
tipd_scanmoden : VitalDelayType01 := DefpropDelay01;
tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappintasts : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmevent : VitalDelayType01 := DefpropDelay01;
tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01;
tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01;
tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_type : STRING := "stratixiv_hssi_pcie_hip";
advanced_errors : STRING := "false";
allow_rx_valid_empty : STRING := "false"; -- july3,2008
bar0_64bit_mem_space : STRING := "true";
bar0_io_space : STRING := "false";
bar0_prefetchable : STRING := "true";
bar0_size_mask : INTEGER := 32;
bar1_64bit_mem_space : STRING := "false";
bar1_io_space : STRING := "false";
bar1_prefetchable : STRING := "false";
bar1_size_mask : INTEGER := 4;
bar2_64bit_mem_space : STRING := "false";
bar2_io_space : STRING := "false";
bar2_prefetchable : STRING := "false";
bar2_size_mask : INTEGER := 4;
bar3_64bit_mem_space : STRING := "false";
bar3_io_space : STRING := "false";
bar3_prefetchable : STRING := "false";
bar3_size_mask : INTEGER := 4;
bar4_64bit_mem_space : STRING := "false";
bar4_io_space : STRING := "false";
bar4_prefetchable : STRING := "false";
bar4_size_mask : INTEGER := 4;
bar5_64bit_mem_space : STRING := "false";
bar5_io_space : STRING := "false";
bar5_prefetchable : STRING := "false";
bar5_size_mask : INTEGER := 4;
bar_io_window_size : STRING := "NONE";
bar_prefetchable : INTEGER := 0;
base_address : INTEGER := 0;
bridge_port_ssid_support : STRING := "false";
bridge_port_vga_enable : STRING := "false";
bypass_cdc : STRING := "false";
bypass_tl : STRING := "false";
class_code : INTEGER := 16711680;
completion_timeout : STRING := "ABCD";
core_clk_divider : INTEGER := 1;
core_clk_source : STRING := "PLL_FIXED_CLK";
credit_buffer_allocation_aux : STRING := "BALANCED";
deemphasis_enable : STRING := "false";
device_address : INTEGER := 0;
device_id : INTEGER := 1;
device_number : INTEGER := 0;
diffclock_nfts_count : INTEGER := 128;
disable_async_l2_logic : STRING := "false"; -- july2,2008
disable_cdc_clk_ppm : STRING := "true";
disable_device_number_mismatch : STRING := "false";
disable_link_x2_support : STRING := "false";
disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
dll_active_report_support : STRING := "false";
ei_delay_powerdown_count : INTEGER := 10;
eie_before_nfts_count : INTEGER := 4;
enable_adapter_half_rate_mode : STRING := "false";
enable_ch0_pclk_out : STRING := "false";
enable_completion_timeout_disable : STRING := "true";
enable_coreclk_out_half_rate : STRING := "false";
enable_d1pm_support : STRING := "false";
enable_d2pm_support : STRING := "false";
enable_ecrc_check : STRING := "false";
enable_ecrc_gen : STRING := "false";
enable_function_msi_support : STRING := "true";
enable_function_msix_support : STRING := "false";
enable_gen2_core : STRING := "true";
enable_hip_x1_loopback : STRING := "false";
enable_l1_aspm : STRING := "false";
enable_msi_64bit_addressing : STRING := "true";
enable_msi_masking : STRING := "false";
enable_rcv0buf_a_we : STRING := "true";
enable_rcv0buf_b_re : STRING := "true";
enable_rcv0buf_output_regs : STRING := "false";
enable_rcv1buf_a_we : STRING := "true";
enable_rcv1buf_b_re : STRING := "true";
enable_rcv1buf_output_regs : STRING := "false";
enable_retrybuf_a_we : STRING := "true";
enable_retrybuf_b_re : STRING := "true";
enable_retrybuf_ecc : STRING := "false"; -- ww12
enable_retrybuf_output_regs : STRING := "false";
enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx0buf_ecc : STRING := "false"; -- ww12
enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx1buf_ecc : STRING := "false"; -- ww12
enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx_buffer_checking : STRING := "false";
enable_rx_ei_l0s_exit_refined : STRING := "false";
enable_rx_reordering : STRING := "true";
enable_slot_register : STRING := "false";
endpoint_l0_latency : INTEGER := 0;
endpoint_l1_latency : INTEGER := 0;
expansion_base_address_register : INTEGER := 0;
extend_tag_field : STRING := "false";
fc_init_timer : INTEGER := 1024;
flow_control_timeout_count : INTEGER := 200;
flow_control_update_count : INTEGER := 30;
gen2_diffclock_nfts_count : INTEGER := 255;
gen2_lane_rate_mode : STRING := "false";
gen2_sameclock_nfts_count : INTEGER := 255;
hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
iei_logic : STRING := "IEI_IIIS";
indicator : INTEGER := 7;
l01_entry_latency : INTEGER := 31;
l0_exit_latency_diffclock : INTEGER := 6;
l0_exit_latency_sameclock : INTEGER := 6;
l1_exit_latency_diffclock : INTEGER := 0;
l1_exit_latency_sameclock : INTEGER := 0;
lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000";
low_priority_vc : INTEGER := 0;
max_link_width : INTEGER := 4;
max_payload_size : INTEGER := 2;
maximum_current : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
millisecond_cycle_count : INTEGER := 0;
mram_bist_settings : STRING := "";
msi_function_count : INTEGER := 2;
msix_pba_bir : INTEGER := 0;
msix_pba_offset : INTEGER := 0;
msix_table_bir : INTEGER := 0;
msix_table_offset : INTEGER := 0;
msix_table_size : INTEGER := 0;
no_command_completed : STRING := "true";
no_soft_reset : STRING := "false";
pcie_mode : STRING := "SHARED_MODE";
pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
port_link_number : INTEGER := 1;
port_address : INTEGER := 0;
register_pipe_signals : STRING := "false";
retry_buffer_last_active_address : INTEGER := 2047;
retry_buffer_memory_settings : INTEGER := 0;
revision_id : INTEGER := 1;
rx0_adap_fifo_full_value : INTEGER := 9;
rx1_adap_fifo_full_value : INTEGER := 9;
rx_cdc_full_value : INTEGER := 12;
rx_idl_os_count : INTEGER := 0;
rx_ptr0_nonposted_dpram_max : INTEGER := 0;
rx_ptr0_nonposted_dpram_min : INTEGER := 0;
rx_ptr0_posted_dpram_max : INTEGER := 0;
rx_ptr0_posted_dpram_min : INTEGER := 0;
rx_ptr1_nonposted_dpram_max : INTEGER := 0;
rx_ptr1_nonposted_dpram_min : INTEGER := 0;
rx_ptr1_posted_dpram_max : INTEGER := 0;
rx_ptr1_posted_dpram_min : INTEGER := 0;
sameclock_nfts_count : INTEGER := 128;
single_rx_detect : INTEGER := 0;
skp_os_schedule_count : INTEGER := 0;
slot_number : INTEGER := 0;
slot_power_limit : INTEGER := 0;
slot_power_scale : INTEGER := 0;
ssid : INTEGER := 0;
ssvid : INTEGER := 0;
subsystem_device_id : INTEGER := 1;
subsystem_vendor_id : INTEGER := 4466;
surprise_down_error_support : STRING := "false";
tx0_adap_fifo_full_value : INTEGER := 11;
tx1_adap_fifo_full_value : INTEGER := 11;
tx_cdc_full_value : INTEGER := 12;
tx_cdc_stop_dummy_full_value : INTEGER := 11;
use_crc_forwarding : STRING := "false";
vc0_clk_enable : STRING := "true";
vc0_rx_buffer_memory_settings : INTEGER := 0;
vc0_rx_flow_ctrl_compl_data : INTEGER := 448;
vc0_rx_flow_ctrl_compl_header : INTEGER := 112;
vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc0_rx_flow_ctrl_posted_data : INTEGER := 360;
vc0_rx_flow_ctrl_posted_header : INTEGER := 50;
vc1_clk_enable : STRING := "false";
vc1_rx_buffer_memory_settings : INTEGER := 0;
vc1_rx_flow_ctrl_compl_data : INTEGER := 448;
vc1_rx_flow_ctrl_compl_header : INTEGER := 112;
vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc1_rx_flow_ctrl_posted_data : INTEGER := 360;
vc1_rx_flow_ctrl_posted_header : INTEGER := 50;
vc_arbitration : INTEGER := 1;
vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
vendor_id : INTEGER := 4466
);
PORT (
bistenrcv0 : IN STD_LOGIC := '0';
bistenrcv1 : IN STD_LOGIC := '0';
bistenrpl : IN STD_LOGIC := '0';
bistscanen : IN STD_LOGIC := '0';
bistscanin : IN STD_LOGIC := '0';
bisttesten : IN STD_LOGIC := '0';
coreclkin : IN STD_LOGIC := '0';
corecrst : IN STD_LOGIC := '0';
corepor : IN STD_LOGIC := '0';
corerst : IN STD_LOGIC := '0';
coresrst : IN STD_LOGIC := '0';
cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
cplpending : IN STD_LOGIC := '0';
dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0');
dlaspmcr0 : IN STD_LOGIC := '0';
dlcomclkreg : IN STD_LOGIC := '0';
dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0');
dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlinhdllp : IN STD_LOGIC := '1';
dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlrequpfc : IN STD_LOGIC := '0';
dlreqwake : IN STD_LOGIC := '0';
dlrxecrcchk : IN STD_LOGIC := '0';
dlsndupfc : IN STD_LOGIC := '0';
dltxcfgextsy : IN STD_LOGIC := '0';
dltxreqpm : IN STD_LOGIC := '0';
dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0');
lmirden : IN STD_LOGIC := '0';
lmiwren : IN STD_LOGIC := '0';
mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
mramhiptestenable : IN STD_LOGIC := '0';
mramregscanen : IN STD_LOGIC := '0';
mramregscanin : IN STD_LOGIC := '0';
pclkcentral : IN STD_LOGIC := '0';
pclkch0 : IN STD_LOGIC := '0';
phyrst : IN STD_LOGIC := '0';
physrst : IN STD_LOGIC := '0';
phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
pldclk : IN STD_LOGIC := '0';
pldrst : IN STD_LOGIC := '0';
pldsrst : IN STD_LOGIC := '0';
pllfixedclk : IN STD_LOGIC := '0';
rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxmaskvc0 : IN STD_LOGIC := '0';
rxmaskvc1 : IN STD_LOGIC := '0';
rxreadyvc0 : IN STD_LOGIC := '0';
rxreadyvc1 : IN STD_LOGIC := '0';
rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
scanen : IN STD_LOGIC := '0';
scanmoden : IN STD_LOGIC := '0';
swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0');
tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappintasts : IN STD_LOGIC := '0';
tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappmsireq : IN STD_LOGIC := '0';
tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpmauxpwr : IN STD_LOGIC := '0';
tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
tlpmetocr : IN STD_LOGIC := '0';
tlpmevent : IN STD_LOGIC := '0';
tlslotclkcfg : IN STD_LOGIC := '0';
txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txeopvc00 : IN STD_LOGIC := '0';
txeopvc01 : IN STD_LOGIC := '0';
txeopvc10 : IN STD_LOGIC := '0';
txeopvc11 : IN STD_LOGIC := '0';
txerrvc0 : IN STD_LOGIC := '0';
txerrvc1 : IN STD_LOGIC := '0';
txsopvc00 : IN STD_LOGIC := '0';
txsopvc01 : IN STD_LOGIC := '0';
txsopvc10 : IN STD_LOGIC := '0';
txsopvc11 : IN STD_LOGIC := '0';
txvalidvc0 : IN STD_LOGIC := '0';
txvalidvc1 : IN STD_LOGIC := '0';
bistdonearcv0 : OUT STD_LOGIC;
bistdonearcv1 : OUT STD_LOGIC;
bistdonearpl : OUT STD_LOGIC;
bistdonebrcv0 : OUT STD_LOGIC;
bistdonebrcv1 : OUT STD_LOGIC;
bistdonebrpl : OUT STD_LOGIC;
bistpassrcv0 : OUT STD_LOGIC;
bistpassrcv1 : OUT STD_LOGIC;
bistpassrpl : OUT STD_LOGIC;
bistscanoutrcv0 : OUT STD_LOGIC;
bistscanoutrcv1 : OUT STD_LOGIC;
bistscanoutrpl : OUT STD_LOGIC;
clrrxpath : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataenablen : OUT STD_LOGIC;
derrcorextrcv0 : OUT STD_LOGIC;
derrcorextrcv1 : OUT STD_LOGIC;
derrcorextrpl : OUT STD_LOGIC;
derrrpl : OUT STD_LOGIC;
dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dlackrequpfc : OUT STD_LOGIC;
dlacksndupfc : OUT STD_LOGIC;
dlcurrentdeemp : OUT STD_LOGIC;
dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dldllreq : OUT STD_LOGIC;
dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlerrphy : OUT STD_LOGIC;
dllinkautobdwstatus : OUT STD_LOGIC;
dllinkbdwmngstatus : OUT STD_LOGIC;
dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlrpbufemp : OUT STD_LOGIC;
dlrstentercompbit : OUT STD_LOGIC;
dlrsttxmarginfield : OUT STD_LOGIC;
dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
dlrxvalpm : OUT STD_LOGIC;
dltxackpm : OUT STD_LOGIC;
dlup : OUT STD_LOGIC;
dlupexit : OUT STD_LOGIC;
dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC;
dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
ev128ns : OUT STD_LOGIC;
ev1us : OUT STD_LOGIC;
extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0);
gen2rate : OUT STD_LOGIC;
gen2rategnd : OUT STD_LOGIC;
hotrstexit : OUT STD_LOGIC;
intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
l2exit : OUT STD_LOGIC;
laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
linkup : OUT STD_LOGIC;
lmiack : OUT STD_LOGIC;
lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
ltssml0state : OUT STD_LOGIC;
mramregscanout : OUT STD_LOGIC;
powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0);
resetstatus : OUT STD_LOGIC;
rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxeopvc00 : OUT STD_LOGIC;
rxeopvc01 : OUT STD_LOGIC;
rxeopvc10 : OUT STD_LOGIC;
rxeopvc11 : OUT STD_LOGIC;
rxerrvc0 : OUT STD_LOGIC;
rxerrvc1 : OUT STD_LOGIC;
rxfifoemptyvc0 : OUT STD_LOGIC;
rxfifoemptyvc1 : OUT STD_LOGIC;
rxfifofullvc0 : OUT STD_LOGIC;
rxfifofullvc1 : OUT STD_LOGIC;
rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxsopvc00 : OUT STD_LOGIC;
rxsopvc01 : OUT STD_LOGIC;
rxsopvc10 : OUT STD_LOGIC;
rxsopvc11 : OUT STD_LOGIC;
rxvalidvc0 : OUT STD_LOGIC;
rxvalidvc1 : OUT STD_LOGIC;
r2cerr0ext : OUT STD_LOGIC;
serrout : OUT STD_LOGIC;
successspeednegoint : OUT STD_LOGIC;
swdnwake : OUT STD_LOGIC;
swuphotrst : OUT STD_LOGIC;
testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
tlappintaack : OUT STD_LOGIC;
tlappmsiack : OUT STD_LOGIC;
tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
tlcfgctlwr : OUT STD_LOGIC;
tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0);
tlcfgstswr : OUT STD_LOGIC;
tlpmetosr : OUT STD_LOGIC;
txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txfifoemptyvc0 : OUT STD_LOGIC;
txfifoemptyvc1 : OUT STD_LOGIC;
txfifofullvc0 : OUT STD_LOGIC;
txfifofullvc1 : OUT STD_LOGIC;
txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
txreadyvc0 : OUT STD_LOGIC;
txreadyvc1 : OUT STD_LOGIC;
wakeoen : OUT STD_LOGIC
);
END COMPONENT;
end stratixiv_pcie_hip_components;
package body STRATIXIV_PCIE_HIP_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
end STRATIXIV_PCIE_HIP_COMPONENTS;
| gpl-3.0 | 601ca2398b478dac81d23d3f975578b7 | 0.522781 | 4.297576 | false | false | false | false |
Shadytel/Computer | Emulator/FPGA/Debouncer.vhd | 1 | 1,528 | ----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 21:58:16 09/22/2011
-- Design Name:
-- Module Name: Debouncer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Debouncer is
Port (
CLK : in STD_LOGIC;
x : in STD_LOGIC;
DBx : out STD_LOGIC
);
end Debouncer;
architecture Behavioral of Debouncer is
type State_Type is (S0, S1);
signal State : State_Type := S0;
signal DPB, SPB : STD_LOGIC;
signal DReg : STD_LOGIC_VECTOR (7 downto 0);
begin
Debounce: process (CLK, x)
variable SDC : integer;
constant Delay : integer := 50000;
begin
if CLK'Event and CLK = '1' then
-- Double latch input signal
DPB <= SPB;
SPB <= x;
case State is
when S0 =>
DReg <= DReg(6 downto 0) & DPB;
SDC := Delay;
State <= S1;
when S1 =>
SDC := SDC - 1;
if SDC = 0 then
State <= S0;
end if;
when others =>
State <= S0;
end case;
if DReg = X"FF" then
DBx <= '1';
elsif DReg = X"00" then
DBx <= '0';
end if;
end if;
end process;
end Behavioral; | bsd-3-clause | 188841e155bf7658f2c8cd5758192c50 | 0.48822 | 3.745098 | false | false | false | false |
keith-epidev/md2x | build/code/keyboard_old.vhd | 1 | 4,764 | library ieee;
use ieee.std_logic_1164.all;
use work.my_lib.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keyboard is
port(
clk: in std_logic;
clr: in std_logic;
PS2C: in std_logic;
PS2D: in std_logic;
keyval1: out std_logic_vector(7 downto 0);
keyval2: out std_logic_vector(7 downto 0);
keyval3: out std_logic_vector(7 downto 0)
);
end keyboard;
architecture Behavioral of keyboard is
type state_type is (start, wait_clk_hi_1, wait_clk_lo_1, get_key_1, wait_clk_hi_2, wait_clk_lo_2, get_key_2, breakkey, wait_clk_hi_3, wait_clk_lo_3, get_key_3);
signal state: state_type;
signal PS2Cf, PS2Df: std_logic;
signal PS2C_filter,PS2D_filter: std_logic_vector(7 downto 0);
signal shift1,shift2,shift3: std_logic_vector(10 downto 0);
signal keyval1s,keyval2s,keyval3s: std_logic_vector(7 downto 0);
signal bit_count: std_logic_vector(3 downto 0);
constant bit_count_max: std_logic_vector(3 downto 0) := "1011";
begin
--filter the signal
filterC: process(clk,clr)
begin
if clr = '1' then
PS2C_filter <= (others=>'0');
PS2Cf <= '1';
else if (clk'event and clk ='1' ) then
--shift down
PS2C_filter(7) <= PS2C;
PS2C_filter(6 downto 0) <= PS2C_filter(7 downto 1);
if PS2C_filter = X"FF" then
PS2Cf <= '1';
else if PS2C_filter = X"00" then
PS2Cf <= '0';
end if;
end if;
end if;
end if;
end process filterC;
--filter the signal
filterD: process(clk,clr)
begin
if clr = '1' then
PS2D_filter <= (others=>'0');
PS2Df <= '1';
else if (clk'event and clk ='1' ) then
--shift down
PS2D_filter(7) <= PS2D;
PS2D_filter(6 downto 0) <= PS2D_filter(7 downto 1);
if PS2D_filter = X"FF" then
PS2Df <= '1';
else if PS2D_filter = X"00" then
PS2Df <= '0';
end if;
end if;
end if;
end if;
end process filterD;
--state machine
skey: process(clk,clr)
begin
if(clr = '1') then
state <= start;
bit_count <= (others=>'0');
shift1 <= (others=>'0');
shift2 <= (others=>'0');
shift2 <= (others=>'0');
keyval1s <= (others=>'0');
keyval2s <= (others=>'0');
keyval3s <= (others=>'0');
else if (clk'event and clk = '1') then
case state is
when start =>
if PS2Df = '1' then
state <=start;
else
state <= wait_clk_lo_1;
end if;
when wait_clk_lo_1 =>
if bit_count < bit_count_max then
if PS2Cf = '1' then
state <= wait_clk_lo_1;
else
state <= wait_clk_hi_1;
shift1 <= PS2Df & shift1(10 downto 1);
end if;
else
state <= get_key_1;
end if;
when wait_clk_hi_1 =>
if PS2Cf = '0' then
state <= wait_clk_hi_1;
else
state <= wait_clk_lo_1;
bit_count <= bit_count + 1;
end if;
when get_key_1 =>
keyval1s <= shift1(8 downto 1);
bit_count <= (others=>'0');
state <= wait_clk_lo_2;
----
when wait_clk_lo_2 =>
if bit_count < bit_count_max then
if PS2Cf = '1' then
state <= wait_clk_lo_2;
else
state <= wait_clk_hi_2;
shift2 <= PS2Df & shift2(10 downto 1);
end if;
else
state <= get_key_2;
end if;
when wait_clk_hi_2 =>
if PS2Cf = '0' then
state <= wait_clk_hi_2;
else
state <= wait_clk_lo_2;
bit_count <= bit_count + 1;
end if;
when get_key_2 =>
keyval2s <= shift2(8 downto 1);
bit_count <= (others=>'0');
state <= breakkey;
when breakkey =>
if keyval2s = X"F0" then
state <= wait_clk_lo_3;
else
if keyval1s = X"E0" then
state <= wait_clk_lo_1;
else
state <= wait_clk_lo_2;
end if;
end if;
when wait_clk_lo_3 =>
if bit_count < bit_count_max then
if PS2Cf = '1' then
state <= wait_clk_lo_3;
else
state <= wait_clk_hi_3;
shift3 <= PS2Df & shift3(10 downto 1);
end if;
else
state <= get_key_3;
end if;
when wait_clk_hi_3 =>
if PS2Cf = '0' then
state <= wait_clk_hi_3;
else
state <= wait_clk_lo_3;
bit_count <= bit_count +1;
end if;
when get_key_3 =>
keyval3s <= shift3(8 downto 1);
bit_count <= (others=>'0');
state <= wait_clk_lo_1;
end case;
end if;
end if;
end process skey;
keyval1 <= keyval1s;
keyval2 <= keyval2s;
keyval3 <= keyval3s;
end Behavioral; | gpl-2.0 | 309a6f60348fc517d389bb59a387bbef | 0.524979 | 2.750577 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/internal_osc/synthesis/internal_osc.vhd | 2 | 908 | -- internal_osc.vhd
-- Generated using ACDS version 17.1 590
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity internal_osc is
port (
clkout : out std_logic; -- clkout.clk
oscena : in std_logic := '0' -- oscena.oscena
);
end entity internal_osc;
architecture rtl of internal_osc is
component altera_int_osc is
generic (
DEVICE_FAMILY : string := "";
DEVICE_ID : string := "UNKNOWN";
CLOCK_FREQUENCY : string := "UNKNOWN"
);
port (
oscena : in std_logic := 'X'; -- oscena
clkout : out std_logic -- clk
);
end component altera_int_osc;
begin
int_osc_0 : component altera_int_osc
generic map (
DEVICE_FAMILY => "MAX 10",
DEVICE_ID => "04",
CLOCK_FREQUENCY => "116"
)
port map (
oscena => oscena, -- oscena.oscena
clkout => clkout -- clkout.clk
);
end architecture rtl; -- of internal_osc
| apache-2.0 | 20321c0ce91f01c540c04e88c9b801b6 | 0.620044 | 3.006623 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_io_pack-p.vhd | 1 | 2,298 | -------------------------------------------------------------------------------
--
-- $Id: t400_io_pack-p.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t400_io_pack is
function io_out_f(dat : in std_logic;
opt : in integer) return std_logic;
function io_en_f (en : in std_logic;
dat : in std_logic;
opt : in integer) return std_logic;
end t400_io_pack;
use work.t400_opt_pack.all;
package body t400_io_pack is
function io_out_f(dat : in std_logic;
opt : in integer) return std_logic is
variable result_v : std_logic;
begin
result_v := '-';
case opt is
-- Open drain type output drivers ---------------------------------------
when t400_opt_out_type_od_c =>
result_v := '0';
-- Push/pull type output drivers ----------------------------------------
when t400_opt_out_type_std_c |
t400_opt_out_type_led_c |
t400_opt_out_type_pp_c =>
result_v := dat;
when others =>
null;
end case;
return result_v;
end io_out_f;
function io_en_f (en : in std_logic;
dat : in std_logic;
opt : in integer) return std_logic is
variable result_v : std_logic;
begin
result_v := '0';
case opt is
-- Open drain type output drivers ---------------------------------------
when t400_opt_out_type_od_c =>
if en = '1' and dat = '0' then
result_v := '1';
end if;
-- Push/pull type output drivers ----------------------------------------
when t400_opt_out_type_std_c |
t400_opt_out_type_led_c |
t400_opt_out_type_pp_c =>
result_v := en;
when others =>
null;
end case;
return result_v;
end io_en_f;
end t400_io_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | ac3a7f8fde0e47422b50974cec4af366 | 0.429939 | 3.914821 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/step_mod.vhd | 1 | 7,794 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity STEP_MOD is
generic (
-- IO-REQ: 19 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000101";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
OUT_EN: in std_logic;
IDLE: out std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of STEP_MOD is
signal wb_data_mux : std_logic_vector(31 downto 0);
signal step_len: std_logic_vector(31 downto 0);
signal dir_hold_dly: std_logic_vector(31 downto 0);
signal dir_setup_dly: std_logic_vector(31 downto 0);
signal targetvel_a: std_logic_vector(31 downto 0);
signal deltalim_a: std_logic_vector(31 downto 0);
signal pos_capt_a: std_logic;
signal pos_hi_a: std_logic_vector(31 downto 0);
signal pos_lo_a: std_logic_vector(31 downto 0);
signal idle_a: std_logic;
signal targetvel_b: std_logic_vector(31 downto 0);
signal deltalim_b: std_logic_vector(31 downto 0);
signal pos_capt_b: std_logic;
signal pos_hi_b: std_logic_vector(31 downto 0);
signal pos_lo_b: std_logic_vector(31 downto 0);
signal idle_b: std_logic;
signal targetvel_c: std_logic_vector(31 downto 0);
signal deltalim_c: std_logic_vector(31 downto 0);
signal pos_capt_c: std_logic;
signal pos_hi_c: std_logic_vector(31 downto 0);
signal pos_lo_c: std_logic_vector(31 downto 0);
signal idle_c: std_logic;
signal targetvel_d: std_logic_vector(31 downto 0);
signal deltalim_d: std_logic_vector(31 downto 0);
signal pos_capt_d: std_logic;
signal pos_hi_d: std_logic_vector(31 downto 0);
signal pos_lo_d: std_logic_vector(31 downto 0);
signal idle_d: std_logic;
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
pos_capt_a <= '0';
pos_capt_b <= '0';
pos_capt_c <= '0';
pos_capt_d <= '0';
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= step_len;
when WB_ADDR_OFFSET + 1 =>
wb_data_mux <= dir_hold_dly;
when WB_ADDR_OFFSET + 2 =>
wb_data_mux <= dir_setup_dly;
when WB_ADDR_OFFSET + 3 =>
wb_data_mux <= targetvel_a;
when WB_ADDR_OFFSET + 4 =>
wb_data_mux <= deltalim_a;
when WB_ADDR_OFFSET + 5 =>
pos_capt_a <= WB_STB_RD;
wb_data_mux <= pos_hi_a;
when WB_ADDR_OFFSET + 6 =>
wb_data_mux <= pos_lo_a;
when WB_ADDR_OFFSET + 7 =>
wb_data_mux <= targetvel_b;
when WB_ADDR_OFFSET + 8 =>
wb_data_mux <= deltalim_b;
when WB_ADDR_OFFSET + 9 =>
pos_capt_b <= WB_STB_RD;
wb_data_mux <= pos_hi_b;
when WB_ADDR_OFFSET + 10 =>
wb_data_mux <= pos_lo_b;
when WB_ADDR_OFFSET + 11 =>
wb_data_mux <= targetvel_c;
when WB_ADDR_OFFSET + 12 =>
wb_data_mux <= deltalim_c;
when WB_ADDR_OFFSET + 13 =>
pos_capt_c <= WB_STB_RD;
wb_data_mux <= pos_hi_c;
when WB_ADDR_OFFSET + 14 =>
wb_data_mux <= pos_lo_c;
when WB_ADDR_OFFSET + 15 =>
wb_data_mux <= targetvel_d;
when WB_ADDR_OFFSET + 16 =>
wb_data_mux <= deltalim_d;
when WB_ADDR_OFFSET + 17 =>
pos_capt_d <= WB_STB_RD;
wb_data_mux <= pos_hi_d;
when WB_ADDR_OFFSET + 18 =>
wb_data_mux <= pos_lo_d;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
step_len <= (others => '0');
dir_hold_dly <= (others => '0');
dir_setup_dly <= (others => '0');
targetvel_a <= (others => '0');
deltalim_a <= (others => '0');
targetvel_b <= (others => '0');
deltalim_b <= (others => '0');
targetvel_c <= (others => '0');
deltalim_c <= (others => '0');
targetvel_d <= (others => '0');
deltalim_d <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
step_len <= WB_DATA_IN;
when WB_ADDR_OFFSET + 1 =>
dir_hold_dly <= WB_DATA_IN;
when WB_ADDR_OFFSET + 2 =>
dir_setup_dly <= WB_DATA_IN;
when WB_ADDR_OFFSET + 3 =>
targetvel_a <= WB_DATA_IN;
when WB_ADDR_OFFSET + 4 =>
deltalim_a <= WB_DATA_IN;
when WB_ADDR_OFFSET + 7 =>
targetvel_b <= WB_DATA_IN;
when WB_ADDR_OFFSET + 8 =>
deltalim_b <= WB_DATA_IN;
when WB_ADDR_OFFSET + 11 =>
targetvel_c <= WB_DATA_IN;
when WB_ADDR_OFFSET + 12 =>
deltalim_c <= WB_DATA_IN;
when WB_ADDR_OFFSET + 15 =>
targetvel_d <= WB_DATA_IN;
when WB_ADDR_OFFSET + 16 =>
deltalim_d <= WB_DATA_IN;
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- stepgen instances
----------------------------------------------------------
IDLE <= idle_a and idle_b and idle_c and idle_d;
U_STEP_A: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_a,
pos_hi => pos_hi_a,
pos_lo => pos_lo_a,
targetvel => targetvel_a,
deltalim => deltalim_a,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_a,
STP_OUT => SV(10),
STP_DIR => SV(9)
);
U_STEP_B: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_b,
pos_hi => pos_hi_b,
pos_lo => pos_lo_b,
targetvel => targetvel_b,
deltalim => deltalim_b,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_b,
STP_OUT => SV(8),
STP_DIR => SV(7)
);
U_STEP_C: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_c,
pos_hi => pos_hi_c,
pos_lo => pos_lo_c,
targetvel => targetvel_c,
deltalim => deltalim_c,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_c,
STP_OUT => SV(6),
STP_DIR => SV(5)
);
U_STEP_D: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_d,
pos_hi => pos_hi_d,
pos_lo => pos_lo_d,
targetvel => targetvel_d,
deltalim => deltalim_d,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_d,
STP_OUT => SV(4),
STP_DIR => SV(3)
);
end;
| gpl-3.0 | 838073d7a8fe26d4d275b25a7daa96bb | 0.527842 | 3.052879 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/elk_user_flash.vhd | 1 | 6,100 | -- Copyright 2018 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Convert altera_onchip_flash signals to something that works more like an
-- ordinary flash chip at 2MHz. altera_onchip_flash is designed to run at a
-- super high clock rate, but requires a few clock cycles to return data.
-- From the Max 10 UFM User Guide:
-- 10M04SC only has the UFM0 sector -- no UFM1, or CFM{0, 1, 2}.
-- UFM0 has 8 x 16kb (2kB) pages, for a total of 16kB of user flash.
-- Either a whole sector, or an individual page, can be erased.
-- csr_addr = '0' => read-only status register
-- "1111111111111111111111" & sp5 & sp4 & sp3 & sp2 & sp1 & es & ws & rs & busy[2]
-- csr_addr = '1' => read/write control register
-- "1111" & wp5 & wp4 & wp3 & wp2 & wp1 & se[3] & pe[20]
entity elk_user_flash is
port (
slow_clock : in std_logic; -- 2MHz clock
fast_clock : in std_logic; -- 116MHz clock
reset_n : in std_logic;
address : std_logic_vector(13 downto 0);
en : in std_logic; -- active-high read enable
data_out : out std_logic_vector(7 downto 0)
);
end elk_user_flash;
architecture rtl of elk_user_flash is
signal slow_clock_sync : std_logic_vector(2 downto 0);
signal address_reg : std_logic_vector(13 downto 0);
signal data_reg : std_logic_vector(7 downto 0) := x"75";
signal flash_read : std_logic := '0';
signal flash_readdatavalid : std_logic;
signal flash_readdata : std_logic_vector(31 downto 0);
signal flash_waitrequest : std_logic;
signal csr_readdata : std_logic_vector(31 downto 0);
-- 10M04 internal flash
component internal_flash is
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avmm_data_addr : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
avmm_data_read : in std_logic := 'X'; -- read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_data_write : in std_logic := 'X'; -- write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
avmm_data_waitrequest : out std_logic; -- waitrequest
avmm_data_readdatavalid : out std_logic; -- readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
avmm_csr_addr : in std_logic := 'X'; -- address
avmm_csr_read : in std_logic := 'X'; -- read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_csr_write : in std_logic := 'X'; -- write
avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component internal_flash;
begin
-- latched data from the last successful read
data_out <= data_reg;
-- everything is synchronous to the flash clock
process (fast_clock)
begin
if rising_edge(fast_clock) then
-- clear read pulse from last clock
flash_read <= '0';
-- sync and edge detect on elk clock
slow_clock_sync <= slow_clock_sync(1 downto 0) & slow_clock;
if slow_clock_sync(2) = '1' and slow_clock_sync(1) = '0' and en = '1' then
-- rising edge of elk clock and we're enabled: start a read
address_reg <= address;
flash_read <= '1';
end if;
-- this will take 5-6 clocks, i.e. ~75 ns plus the time to register flash_read and data_reg
-- register flash output when we get a successful read
if flash_readdatavalid = '1' then
case address_reg(1 downto 0) is
when "00" => data_reg <= flash_readdata(7 downto 0);
when "01" => data_reg <= flash_readdata(15 downto 8);
when "10" => data_reg <= flash_readdata(23 downto 16);
when "11" => data_reg <= flash_readdata(31 downto 24);
end case;
end if;
end if;
end process;
-- Max 10 internal flash
flash0 : component internal_flash
port map (
clock => fast_clock, -- clk.clk
reset_n => reset_n, -- nreset.reset_n
avmm_data_addr => address_reg(13 downto 2), -- data.address
avmm_data_read => flash_read, -- .read
avmm_data_writedata => (others => '0'), -- .writedata
avmm_data_write => '0', -- .write
avmm_data_readdata => flash_readdata, -- .readdata
avmm_data_waitrequest => flash_waitrequest, -- .waitrequest
avmm_data_readdatavalid => flash_readdatavalid, -- .readdatavalid
avmm_data_burstcount => std_logic_vector(to_unsigned(1, 4)), -- .burstcount
avmm_csr_addr => '0', -- csr.address
avmm_csr_read => '0', -- .read
avmm_csr_writedata => (others => '0'), -- .writedata
avmm_csr_write => '0', -- .write
avmm_csr_readdata => csr_readdata -- .readdata
);
end rtl;
| apache-2.0 | 0dcce01df5e225c504d00d39a51965d3 | 0.552951 | 3.795893 | false | false | false | false |
EPiCS/reconos | pcores/reconos_osif_fifo_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 10,506 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - OSIF FIFO - FIFO implementation
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple bidirectional FIFO accessible from the AXI-Bus
-- and from other hardware via the known FIFO interface.
-- This FIFO is used to connect the hwts to the AXI-Bus
-- and therefore to the processing system.
-- Register Definition (as seen from Bus):
-- Reg0: Read data
-- Reg1: Write data
-- Reg2: Fill - number of elements in receive-FIFO
-- Reg3: Rem - free space in send-FIFO
--
-- REMARK: Different clocks for AXI, FIFO-Rd and FIFO-Wr
-- are not supported yet. S_AXI_ACKL is used and
-- FIFO_**_Clk are just added for the future.
--
-- known issues: Because reading of the first word must happen one clock
-- cycle after RE has been set (RE must propagate to the
-- fifo) the bus transaction should be delayed one clock
-- cycle too. Since one bus transaction takes longer than
-- one clock cycle everything is totaly fine.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
-- FIFO parameters
C_FIFO_DEPTH : integer := 32;
-- Bus protocol parameters
C_NUM_REG : integer := 4;
C_SLV_DWIDTH : integer := 32
);
port (
-- FIFO ports
OSIF_FIFO_Sw2Hw_Clk : in std_logic;
OSIF_FIFO_Sw2Hw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : out std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : out std_logic;
OSIF_FIFO_Sw2Hw_RE : in std_logic;
OSIF_FIFO_Hw2Sw_Clk : in std_logic;
OSIF_FIFO_Hw2Sw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : out std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : out std_logic;
OSIF_FIFO_Hw2Sw_WE : in std_logic;
OSIF_FIFO_Rst : in std_logic;
-- Bus protocol ports
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- Interrupt for Bus (only hw2bus)
OSIF_FIFO_Has_Data : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of OSIF_FIFO_Sw2Hw_Clk : signal is "Clk";
attribute SIGIS of OSIF_FIFO_Hw2Sw_Clk : signal is "Clk";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
attribute SIGIS of OSIF_FIFO_Rst : signal is "Rst";
attribute SIGIS of OSIF_FIFO_Has_Data : signal is "Intr_Level_High";
end entity user_logic;
architecture implementation of user_logic is
-- Definition of FIFO-Memory
-- No Block-RAM because the FIFO depth should be small (around 32)
type MEM_T is array (0 to C_FIFO_DEPTH - 1) of std_logic_vector(31 downto 0);
signal hw2bus_fifo : MEM_T;
signal bus2hw_fifo : MEM_T;
signal hw2bus_wrptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal hw2bus_rdptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal hw2bus_fill : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal hw2bus_rem : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal hw2bus_empty : std_logic;
signal hw2bus_full : std_logic;
signal bus2hw_wrptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal bus2hw_rdptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal bus2hw_fill : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal bus2hw_rem : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal bus2hw_empty : std_logic;
signal bus2hw_full : std_logic;
signal bus2hw_dout : std_logic_vector(31 downto 0);
signal bus2hw_din : std_logic_vector(31 downto 0);
signal hw2bus_dout : std_logic_vector(31 downto 0);
signal hw2bus_din : std_logic_vector(31 downto 0);
signal pad_16 : std_logic_vector(15 - clog2(C_FIFO_DEPTH) downto 0);
signal pad_31 : std_logic_vector(30 - clog2(C_FIFO_DEPTH) downto 0);
-- Signals for user logic slave model s/w accessible register
signal slv_reg_write_sel : std_logic_vector(3 downto 0);
signal slv_reg_read_sel : std_logic_vector(3 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
-- this has the intended effect in sythesis (it is infact the same signal)
-- but causes a different behaviour in simulation
clk <= Bus2Ip_Clk;
rst <= OSIF_FIFO_Rst or not Bus2IP_Resetn;
pad_16 <= (others => '0');
pad_31 <= (others => '0');
OSIF_FIFO_Sw2Hw_Data <= bus2hw_dout;
hw2bus_din <= OSIF_FIFO_Hw2Sw_Data;
IP2Bus_Data <= slv_ip2bus_data;
bus2hw_din <= Bus2IP_Data;
OSIF_FIFO_Sw2Hw_Fill <= pad_16 & bus2hw_fill;
OSIF_FIFO_Hw2Sw_Rem <= pad_16 & hw2bus_rem;
OSIF_FIFO_Sw2Hw_Empty <= bus2hw_empty;
OSIF_FIFO_Hw2Sw_Full <= hw2bus_full;
OSIF_FIFO_Has_Data <= not hw2bus_empty;
slv_reg_write_sel <= Bus2IP_WrCE(3 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(3 downto 0);
slv_write_ack <= or_reduce(Bus2IP_WrCE);
slv_read_ack <= or_reduce(Bus2IP_RdCE);
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
fifo_hw2bus_proc : process(clk,rst) is
begin
if rst = '1' then
hw2bus_rdptr <= (others => '0');
hw2bus_wrptr <= (others => '0');
hw2bus_fill <= (others => '0');
hw2bus_rem <= (others => '1');
hw2bus_empty <= '1';
hw2bus_full <= '0';
elsif rising_edge(clk) then
-- writing into fifo which is not full
if OSIF_FIFO_Hw2Sw_WE = '1' and hw2bus_full = '0' then
hw2bus_fifo(CONV_INTEGER(hw2bus_wrptr)) <= hw2bus_din;
hw2bus_wrptr <= hw2bus_wrptr + 1;
if hw2bus_empty = '1' then
hw2bus_empty <= '0';
else
hw2bus_fill <= hw2bus_fill + 1;
end if;
if or_reduce(hw2bus_rem) = '0' then
hw2bus_full <= '1';
else
hw2bus_rem <= hw2bus_rem - 1;
end if;
end if;
-- reading from fifo which is not empty
if slv_reg_read_sel = "1000" and hw2bus_empty = '0' then
hw2bus_rdptr <= hw2bus_rdptr + 1;
if or_reduce(hw2bus_fill) = '0' then
hw2bus_empty <= '1';
else
hw2bus_fill <= hw2bus_fill - 1;
end if;
if hw2bus_full = '1' then
hw2bus_full <= '0';
else
hw2bus_rem <= hw2bus_rem + 1;
end if;
end if;
-- do not change status if reading and writing concurrently
if (OSIF_FIFO_Hw2Sw_WE = '1' and hw2bus_full = '0')
and (slv_reg_read_sel = "1000" and hw2bus_empty = '0') then
hw2bus_fill <= hw2bus_fill;
hw2bus_rem <= hw2bus_rem;
hw2bus_empty <= hw2bus_empty;
hw2bus_full <= hw2bus_full;
end if;
end if;
end process fifo_hw2bus_proc;
hw2bus_dout <= hw2bus_fifo(CONV_INTEGER(hw2bus_rdptr));
fifo_bus2hw_proc : process(clk,rst) is
begin
if rst = '1' then
bus2hw_rdptr <= (others => '0');
bus2hw_wrptr <= (others => '0');
bus2hw_fill <= (others => '0');
bus2hw_rem <= (others => '1');
bus2hw_empty <= '1';
bus2hw_full <= '0';
elsif rising_edge(clk) then
-- writing into fifo which is not full
if slv_reg_write_sel = "0100" and bus2hw_full = '0' then
-- ignoring byte enable
bus2hw_fifo(CONV_INTEGER(bus2hw_wrptr)) <= bus2hw_din;
bus2hw_wrptr <= bus2hw_wrptr + 1;
if bus2hw_empty = '1' then
bus2hw_empty <= '0';
else
bus2hw_fill <= bus2hw_fill + 1;
end if;
if or_reduce(bus2hw_rem) = '0' then
bus2hw_full <= '1';
else
bus2hw_rem <= bus2hw_rem - 1;
end if;
end if;
-- reading from fifo which is not empty
if OSIF_FIFO_Sw2Hw_RE = '1' and bus2hw_empty = '0' then
bus2hw_rdptr <= bus2hw_rdptr + 1;
if or_reduce(bus2hw_fill) = '0' then
bus2hw_empty <= '1';
else
bus2hw_fill <= bus2hw_fill - 1;
end if;
if bus2hw_full = '1' then
bus2hw_full <= '0';
else
bus2hw_rem <= bus2hw_rem + 1;
end if;
end if;
-- do not change fill and rem if reading and writing concurrently
if (slv_reg_write_sel = "0100" and bus2hw_full = '0')
and (OSIF_FIFO_Sw2Hw_RE = '1' and bus2hw_empty = '0') then
bus2hw_fill <= bus2hw_fill;
bus2hw_rem <= bus2hw_rem;
bus2hw_empty <= bus2hw_empty;
bus2hw_full <= bus2hw_full;
end if;
end if;
end process fifo_bus2hw_proc;
bus2hw_dout <= bus2hw_fifo(CONV_INTEGER(bus2hw_rdptr));
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
bus_reg_read_proc : process(slv_reg_read_sel,hw2bus_dout,
hw2bus_empty,hw2bus_fill,
bus2hw_full,bus2hw_rem) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= hw2bus_dout;
when "0010" => slv_ip2bus_data <= hw2bus_empty & pad_31 & hw2bus_fill;
when "0001" => slv_ip2bus_data <= bus2hw_full & pad_31 & bus2hw_rem;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process bus_reg_read_proc;
end implementation;
| gpl-2.0 | b1a9f2cac2cba6c9da26c7238905556c | 0.585055 | 2.849973 | false | false | false | false |
EPiCS/reconos | demos/reconf_led/hw/hwt_led_off_v1_00_a/hdl/vhdl/hwt_led_off.vhd | 2 | 3,398 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_led_off is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
USER_Led : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_led_off;
architecture imp of hwt_led_off is
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
type STATE_TYPE is (STATE_RECV_CMD,STATE_EXEC,STATE_SEND_ACK);
signal state : STATE_TYPE;
signal data : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
-- drive memif constant
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Mem2Hwt_RE <= '0';
USER_Led <= '0';
-- os and memory synchronisation state machine
RECONOS_FSM_PROCESS: process (clk,rst) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
done := false;
state <= STATE_RECV_CMD;
elsif rising_edge(clk) then
case state is
when STATE_RECV_CMD =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, data, done);
if done then
counter <= data(31 downto 0);
state <= STATE_EXEC;
end if;
when STATE_EXEC =>
if or_reduce(counter) = '0' then
state <= STATE_SEND_ACK;
else
counter <= counter - 1;
end if;
when STATE_SEND_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, (others => '0'), ignore, done);
if done then
state <= STATE_RECV_CMD;
end if;
end case;
end if;
end process RECONOS_FSM_PROCESS;
end architecture imp;
| gpl-2.0 | 605d255c82c7644a50a1d9d45bdbf3ac | 0.654503 | 2.669285 | false | false | false | false |
Shadytel/Computer | Emulator/FPGA/WordRegister.vhd | 1 | 1,432 | ----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 20:48:18 09/22/2011
-- Design Name:
-- Module Name: WordRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity WordRegister is
Port
(
WR: in std_logic; --Write
OEN: in std_logic; --OutputEnable
OUTPUT: out std_logic_vector(11 downto 0);
DATABUS: inout std_logic_vector(11 downto 0)
);
end WordRegister;
architecture Behavioral of WordRegister is
signal stores: std_logic_vector(11 downto 0);
begin
DATABUS <= stores when (OEN = '1') else "ZZZZZZZZZZZZ";
OUTPUT <= stores when (OEN = '1') else "ZZZZZZZZZZZZ";
process (WR, DATABUS, stores)
begin
if(WR'event and WR = '1') then
stores <= DATABUS;
end if;
end process;
end Behavioral;
| bsd-3-clause | 08ccc48ff9a6e7eb64e0cd1c607a3d47 | 0.601257 | 3.901907 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixv_hssi_atoms.vhd | 1 | 363,400 | -- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_atx_pll is
generic (
avmm_group_channel_index : integer := 0 ;
output_clock_frequency : string := "" ;
reference_clock_frequency : string := "" ;
use_default_base_address : string := "true" ;
user_base_address0 : integer := 0 ;
user_base_address1 : integer := 0 ;
user_base_address2 : integer := 0 ;
cp_current_ctrl : integer := 300 ;
cp_current_test : string := "enable_ch_pump_normal" ;
cp_hs_levshift_power_supply_setting : integer := 1 ;
cp_replica_bias_ctrl : string := "disable_replica_bias_ctrl" ;
cp_rgla_bypass : string := "false" ;
cp_rgla_volt_inc : string := "boost_30pct" ;
l_counter : integer := 1 ;
lcpll_atb_select : string := "atb_disable" ;
lcpll_d2a_sel : string := "volt_1p02v" ;
lcpll_hclk_driver_enable : string := "driver_off" ;
lcvco_gear_sel : string := "high_gear" ;
lcvco_sel : string := "high_freq_14g" ;
lpf_ripple_cap_ctrl : string := "none" ;
lpf_rxpll_pfd_bw_ctrl : integer := 2400 ;
m_counter : integer := 4 ;
ref_clk_div : integer := 1 ;
refclk_sel : string := "refclk" ;
vreg1_lcvco_volt_inc : string := "volt_1p1v" ;
vreg1_vccehlow : string := "normal_operation" ;
vreg2_lcpll_volt_sel : string := "vreg2_volt_1p0v" ;
vreg3_lcpll_volt_sel : string := "vreg3_volt_1p0v"
);
port (
avmmaddress : in std_logic_vector( 10 downto 0 );
avmmbyteen : in std_logic_vector( 1 downto 0 );
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector( 15 downto 0 );
avmmreaddata : out std_logic_vector( 15 downto 0 );
blockselect : out std_logic;
ch0rcsrlc : in std_logic_vector( 31 downto 0 );
ch1rcsrlc : in std_logic_vector( 31 downto 0 );
ch2rcsrlc : in std_logic_vector( 31 downto 0 );
cmurstn : in std_logic;
cmurstnlpf : in std_logic;
extfbclk : in std_logic;
iqclklc : in std_logic;
pldclklc : in std_logic;
pllfbswblc : in std_logic;
pllfbswtlc : in std_logic;
refclklc : in std_logic;
clk010g : out std_logic;
clk025g : out std_logic;
clk18010g : out std_logic;
clk18025g : out std_logic;
clk33cmu : out std_logic;
clklowcmu : out std_logic;
frefcmu : out std_logic;
iqclkatt : out std_logic;
pfdmodelockcmu : out std_logic;
pldclkatt : out std_logic;
refclkatt : out std_logic;
txpllhclk : out std_logic
);
end stratixv_atx_pll;
architecture behavior of stratixv_atx_pll is
component stratixv_atx_pll_encrypted
generic (
avmm_group_channel_index : integer := 0 ;
output_clock_frequency : string := "" ;
reference_clock_frequency : string := "" ;
use_default_base_address : string := "true" ;
user_base_address0 : integer := 0 ;
user_base_address1 : integer := 0 ;
user_base_address2 : integer := 0 ;
cp_current_ctrl : integer := 300 ;
cp_current_test : string := "enable_ch_pump_normal" ;
cp_hs_levshift_power_supply_setting : integer := 1 ;
cp_replica_bias_ctrl : string := "disable_replica_bias_ctrl" ;
cp_rgla_bypass : string := "false" ;
cp_rgla_volt_inc : string := "boost_30pct" ;
l_counter : integer := 1 ;
lcpll_atb_select : string := "atb_disable" ;
lcpll_d2a_sel : string := "volt_1p02v" ;
lcpll_hclk_driver_enable : string := "driver_off" ;
lcvco_gear_sel : string := "high_gear" ;
lcvco_sel : string := "high_freq_14g" ;
lpf_ripple_cap_ctrl : string := "none" ;
lpf_rxpll_pfd_bw_ctrl : integer := 2400 ;
m_counter : integer := 4 ;
ref_clk_div : integer := 1 ;
refclk_sel : string := "refclk" ;
vreg1_lcvco_volt_inc : string := "volt_1p1v" ;
vreg1_vccehlow : string := "normal_operation" ;
vreg2_lcpll_volt_sel : string := "vreg2_volt_1p0v" ;
vreg3_lcpll_volt_sel : string := "vreg3_volt_1p0v"
);
port (
avmmaddress : in std_logic_vector( 10 downto 0 );
avmmbyteen : in std_logic_vector( 1 downto 0 );
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector( 15 downto 0 );
avmmreaddata : out std_logic_vector( 15 downto 0 );
blockselect : out std_logic;
ch0rcsrlc : in std_logic_vector( 31 downto 0 );
ch1rcsrlc : in std_logic_vector( 31 downto 0 );
ch2rcsrlc : in std_logic_vector( 31 downto 0 );
cmurstn : in std_logic;
cmurstnlpf : in std_logic;
extfbclk : in std_logic;
iqclklc : in std_logic;
pldclklc : in std_logic;
pllfbswblc : in std_logic;
pllfbswtlc : in std_logic;
refclklc : in std_logic;
clk010g : out std_logic;
clk025g : out std_logic;
clk18010g : out std_logic;
clk18025g : out std_logic;
clk33cmu : out std_logic;
clklowcmu : out std_logic;
frefcmu : out std_logic;
iqclkatt : out std_logic;
pfdmodelockcmu : out std_logic;
pldclkatt : out std_logic;
refclkatt : out std_logic;
txpllhclk : out std_logic
);
end component;
begin
inst : stratixv_atx_pll_encrypted
generic map (
avmm_group_channel_index => avmm_group_channel_index ,
output_clock_frequency => output_clock_frequency ,
reference_clock_frequency => reference_clock_frequency ,
use_default_base_address => use_default_base_address ,
user_base_address0 => user_base_address0 ,
user_base_address1 => user_base_address1 ,
user_base_address2 => user_base_address2 ,
cp_current_ctrl => cp_current_ctrl ,
cp_current_test => cp_current_test ,
cp_hs_levshift_power_supply_setting => cp_hs_levshift_power_supply_setting ,
cp_replica_bias_ctrl => cp_replica_bias_ctrl ,
cp_rgla_bypass => cp_rgla_bypass ,
cp_rgla_volt_inc => cp_rgla_volt_inc ,
l_counter => l_counter ,
lcpll_atb_select => lcpll_atb_select ,
lcpll_d2a_sel => lcpll_d2a_sel ,
lcpll_hclk_driver_enable => lcpll_hclk_driver_enable ,
lcvco_gear_sel => lcvco_gear_sel ,
lcvco_sel => lcvco_sel ,
lpf_ripple_cap_ctrl => lpf_ripple_cap_ctrl ,
lpf_rxpll_pfd_bw_ctrl => lpf_rxpll_pfd_bw_ctrl ,
m_counter => m_counter ,
ref_clk_div => ref_clk_div ,
refclk_sel => refclk_sel ,
vreg1_lcvco_volt_inc => vreg1_lcvco_volt_inc ,
vreg1_vccehlow => vreg1_vccehlow ,
vreg2_lcpll_volt_sel => vreg2_lcpll_volt_sel ,
vreg3_lcpll_volt_sel => vreg3_lcpll_volt_sel
)
port map (
avmmaddress => avmmaddress ,
avmmbyteen => avmmbyteen ,
avmmclk => avmmclk ,
avmmread => avmmread ,
avmmrstn => avmmrstn ,
avmmwrite => avmmwrite ,
avmmwritedata => avmmwritedata ,
avmmreaddata => avmmreaddata ,
blockselect => blockselect ,
ch0rcsrlc => ch0rcsrlc ,
ch1rcsrlc => ch1rcsrlc ,
ch2rcsrlc => ch2rcsrlc ,
cmurstn => cmurstn ,
cmurstnlpf => cmurstnlpf ,
extfbclk => extfbclk ,
iqclklc => iqclklc ,
pldclklc => pldclklc ,
pllfbswblc => pllfbswblc ,
pllfbswtlc => pllfbswtlc ,
refclklc => refclklc ,
clk010g => clk010g ,
clk025g => clk025g ,
clk18010g => clk18010g ,
clk18025g => clk18025g ,
clk33cmu => clk33cmu ,
clklowcmu => clklowcmu ,
frefcmu => frefcmu ,
iqclkatt => iqclkatt ,
pfdmodelockcmu => pfdmodelockcmu ,
pldclkatt => pldclkatt ,
refclkatt => refclkatt ,
txpllhclk => txpllhclk
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_channel_pll is
generic
(
avmm_group_channel_index : integer := 0;
output_clock_frequency : string := "0 ps";
reference_clock_frequency : string := "0 ps";
sim_use_fast_model : string := "true";
use_default_base_address : string := "true";
user_base_address : integer := 0;
bbpd_salatch_offset_ctrl_clk0 : string := "clk0_offset_0mv";
bbpd_salatch_offset_ctrl_clk180 : string := "clk180_offset_0mv";
bbpd_salatch_offset_ctrl_clk270 : string := "clk270_offset_0mv";
bbpd_salatch_offset_ctrl_clk90 : string := "clk90_offset_0mv";
bbpd_salatch_sel : string := "normal";
bypass_cp_rgla : string := "false";
cdr_atb_select : string := "atb_disable";
cgb_clk_enable : string := "false";
charge_pump_current_test : string := "enable_ch_pump_normal";
clklow_fref_to_ppm_div_sel : integer := 1;
clock_monitor : string := "lpbk_data";
diag_rev_lpbk : string := "false";
eye_monitor_bbpd_data_ctrl : string := "cdr_data";
fast_lock_mode : string := "false";
fb_sel : string := "vcoclk";
gpon_lock2ref_ctrl : string := "lck2ref";
hs_levshift_power_supply_setting : integer := 1;
ignore_phslock : string := "false";
l_counter_pd_clock_disable : string := "false";
m_counter : integer := 25;
pcie_freq_control : string := "pcie_100mhz";
pd_charge_pump_current_ctrl : integer := 5;
pd_l_counter : integer := 1;
pfd_charge_pump_current_ctrl : integer := 20;
pfd_l_counter : integer := 1;
powerdown : string := "false";
ref_clk_div : integer := 1;
regulator_volt_inc : string := "volt_inc_0pct";
replica_bias_ctrl : string := "true";
reverse_serial_lpbk : string := "false";
ripple_cap_ctrl : string := "none";
rxpll_pd_bw_ctrl : integer := 300;
rxpll_pfd_bw_ctrl : integer := 3200;
txpll_hclk_driver_enable : string := "false";
vco_overange_ref : string := "off";
vco_range_ctrl_en : string := "false"
);
port
(
avmmaddress : in std_logic_vector(10 downto 0);
avmmbyteen : in std_logic;
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector(15 downto 0);
clk270eye : in std_logic;
clk270beyerm : in std_logic;
clk90eye : in std_logic;
clk90beyerm : in std_logic;
clkindeser : in std_logic;
crurstb : in std_logic;
deeye : in std_logic;
deeyerm : in std_logic;
doeye : in std_logic;
doeyerm : in std_logic;
earlyeios : in std_logic;
extclk : in std_logic;
extfbctrla : in std_logic;
extfbctrlb : in std_logic;
gpblck2refb : in std_logic;
lpbkpreen : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
occalen : in std_logic;
pciel : in std_logic;
pciem : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
ppmlock : in std_logic;
refclk : in std_logic;
rstn : in std_logic;
rxp : in std_logic;
sd : in std_logic;
avmmreaddata : out std_logic_vector(15 downto 0);
blockselect : out std_logic;
ck0pd : out std_logic;
ck180pd : out std_logic;
ck270pd : out std_logic;
ck90pd : out std_logic;
clk270bcdr : out std_logic;
clk270bdes : out std_logic;
clk90bcdr : out std_logic;
clk90bdes : out std_logic;
clkcdr : out std_logic;
clklow : out std_logic;
decdr : out std_logic;
deven : out std_logic;
docdr : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pdof : out std_logic_vector(3 downto 0);
pfdmodelock : out std_logic;
rxlpbdp : out std_logic;
rxlpbp : out std_logic;
rxplllock : out std_logic;
txpllhclk : out std_logic;
txrlpbk : out std_logic;
vctrloverrange : out std_logic
);
end stratixv_channel_pll;
architecture behavior of stratixv_channel_pll is
component stratixv_channel_pll_encrypted
generic (
avmm_group_channel_index : integer := 0;
output_clock_frequency : string := "0 ps";
reference_clock_frequency : string := "0 ps";
sim_use_fast_model : string := "true";
use_default_base_address : string := "true";
user_base_address : integer := 0;
bbpd_salatch_offset_ctrl_clk0 : string := "clk0_offset_0mv";
bbpd_salatch_offset_ctrl_clk180 : string := "clk180_offset_0mv";
bbpd_salatch_offset_ctrl_clk270 : string := "clk270_offset_0mv";
bbpd_salatch_offset_ctrl_clk90 : string := "clk90_offset_0mv";
bbpd_salatch_sel : string := "normal";
bypass_cp_rgla : string := "false";
cdr_atb_select : string := "atb_disable";
cgb_clk_enable : string := "false";
charge_pump_current_test : string := "enable_ch_pump_normal";
clklow_fref_to_ppm_div_sel : integer := 1;
clock_monitor : string := "lpbk_data";
diag_rev_lpbk : string := "false";
eye_monitor_bbpd_data_ctrl : string := "cdr_data";
fast_lock_mode : string := "false";
fb_sel : string := "vcoclk";
gpon_lock2ref_ctrl : string := "lck2ref";
hs_levshift_power_supply_setting : integer := 1;
ignore_phslock : string := "false";
l_counter_pd_clock_disable : string := "false";
m_counter : integer := 25;
pcie_freq_control : string := "pcie_100mhz";
pd_charge_pump_current_ctrl : integer := 5;
pd_l_counter : integer := 1;
pfd_charge_pump_current_ctrl : integer := 20;
pfd_l_counter : integer := 1;
powerdown : string := "false";
ref_clk_div : integer := 1;
regulator_volt_inc : string := "volt_inc_0pct";
replica_bias_ctrl : string := "true";
reverse_serial_lpbk : string := "false";
ripple_cap_ctrl : string := "none";
rxpll_pd_bw_ctrl : integer := 300;
rxpll_pfd_bw_ctrl : integer := 3200;
txpll_hclk_driver_enable : string := "false";
vco_overange_ref : string := "off";
vco_range_ctrl_en : string := "false"
);
port (
avmmaddress : in std_logic_vector(10 downto 0);
avmmbyteen : in std_logic;
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector(15 downto 0);
clk270eye : in std_logic;
clk270beyerm : in std_logic;
clk90eye : in std_logic;
clk90beyerm : in std_logic;
clkindeser : in std_logic;
crurstb : in std_logic;
deeye : in std_logic;
deeyerm : in std_logic;
doeye : in std_logic;
doeyerm : in std_logic;
earlyeios : in std_logic;
extclk : in std_logic;
extfbctrla : in std_logic;
extfbctrlb : in std_logic;
gpblck2refb : in std_logic;
lpbkpreen : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
occalen : in std_logic;
pciel : in std_logic;
pciem : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
ppmlock : in std_logic;
refclk : in std_logic;
rstn : in std_logic;
rxp : in std_logic;
sd : in std_logic;
avmmreaddata : out std_logic_vector(15 downto 0);
blockselect : out std_logic;
ck0pd : out std_logic;
ck180pd : out std_logic;
ck270pd : out std_logic;
ck90pd : out std_logic;
clk270bcdr : out std_logic;
clk270bdes : out std_logic;
clk90bcdr : out std_logic;
clk90bdes : out std_logic;
clkcdr : out std_logic;
clklow : out std_logic;
decdr : out std_logic;
deven : out std_logic;
docdr : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pdof : out std_logic_vector(3 downto 0);
pfdmodelock : out std_logic;
rxlpbdp : out std_logic;
rxlpbp : out std_logic;
rxplllock : out std_logic;
txpllhclk : out std_logic;
txrlpbk : out std_logic;
vctrloverrange : out std_logic
);
end component;
begin
inst : stratixv_channel_pll_encrypted
generic map
(
avmm_group_channel_index => avmm_group_channel_index,
output_clock_frequency => output_clock_frequency,
reference_clock_frequency => reference_clock_frequency,
sim_use_fast_model => sim_use_fast_model,
use_default_base_address => use_default_base_address,
user_base_address => user_base_address,
bbpd_salatch_offset_ctrl_clk0 => bbpd_salatch_offset_ctrl_clk0,
bbpd_salatch_offset_ctrl_clk180 => bbpd_salatch_offset_ctrl_clk180,
bbpd_salatch_offset_ctrl_clk270 => bbpd_salatch_offset_ctrl_clk270,
bbpd_salatch_offset_ctrl_clk90 => bbpd_salatch_offset_ctrl_clk90,
bbpd_salatch_sel => bbpd_salatch_sel,
bypass_cp_rgla => bypass_cp_rgla,
cdr_atb_select => cdr_atb_select,
cgb_clk_enable => cgb_clk_enable,
charge_pump_current_test => charge_pump_current_test,
clklow_fref_to_ppm_div_sel => clklow_fref_to_ppm_div_sel,
clock_monitor => clock_monitor,
diag_rev_lpbk => diag_rev_lpbk,
eye_monitor_bbpd_data_ctrl => eye_monitor_bbpd_data_ctrl,
fast_lock_mode => fast_lock_mode,
fb_sel => fb_sel,
gpon_lock2ref_ctrl => gpon_lock2ref_ctrl,
hs_levshift_power_supply_setting => hs_levshift_power_supply_setting,
ignore_phslock => ignore_phslock,
l_counter_pd_clock_disable => l_counter_pd_clock_disable,
m_counter => m_counter,
pcie_freq_control => pcie_freq_control,
pd_charge_pump_current_ctrl => pd_charge_pump_current_ctrl,
pd_l_counter => pd_l_counter,
pfd_charge_pump_current_ctrl => pfd_charge_pump_current_ctrl,
pfd_l_counter => pfd_l_counter,
powerdown => powerdown,
ref_clk_div => ref_clk_div,
regulator_volt_inc => regulator_volt_inc,
replica_bias_ctrl => replica_bias_ctrl,
reverse_serial_lpbk => reverse_serial_lpbk,
ripple_cap_ctrl => ripple_cap_ctrl,
rxpll_pd_bw_ctrl => rxpll_pd_bw_ctrl,
rxpll_pfd_bw_ctrl => rxpll_pfd_bw_ctrl,
txpll_hclk_driver_enable => txpll_hclk_driver_enable,
vco_overange_ref => vco_overange_ref,
vco_range_ctrl_en => vco_range_ctrl_en
)
port map
(
avmmaddress => avmmaddress,
avmmbyteen => avmmbyteen,
avmmclk => avmmclk,
avmmread => avmmread,
avmmrstn => avmmrstn,
avmmwrite => avmmwrite,
avmmwritedata => avmmwritedata,
clk270eye => clk270eye,
clk270beyerm => clk270beyerm,
clk90eye => clk90eye,
clk90beyerm => clk90beyerm,
clkindeser => clkindeser,
crurstb => crurstb,
deeye => deeye,
deeyerm => deeyerm,
doeye => doeye,
doeyerm => doeyerm,
earlyeios => earlyeios,
extclk => extclk,
extfbctrla => extfbctrla,
extfbctrlb => extfbctrlb,
gpblck2refb => gpblck2refb,
lpbkpreen => lpbkpreen,
ltd => ltd,
ltr => ltr,
occalen => occalen,
pciel => pciel,
pciem => pciem,
pciesw => pciesw,
ppmlock => ppmlock,
refclk => refclk,
rstn => rstn,
rxp => rxp,
sd => sd,
avmmreaddata => avmmreaddata,
blockselect => blockselect,
ck0pd => ck0pd,
ck180pd => ck180pd,
ck270pd => ck270pd,
ck90pd => ck90pd,
clk270bcdr => clk270bcdr,
clk270bdes => clk270bdes,
clk90bcdr => clk90bcdr,
clk90bdes => clk90bdes,
clkcdr => clkcdr,
clklow => clklow,
decdr => decdr,
deven => deven,
docdr => docdr,
dodd => dodd,
fref => fref,
pdof => pdof,
pfdmodelock => pfdmodelock,
rxlpbdp => rxlpbdp,
rxlpbp => rxlpbp,
rxplllock => rxplllock,
txpllhclk => txpllhclk,
txrlpbk => txrlpbk,
vctrloverrange => vctrloverrange
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_pcs_aggregate is
generic (
xaui_sm_operation : string := "en_xaui_sm";
dskw_sm_operation : string := "dskw_xaui_sm";
data_agg_bonding : string := "agg_disable";
prot_mode_tx : string := "pipe_g1_tx";
pcs_dw_datapath : string := "sw_data_path";
dskw_control : string := "dskw_write_control";
refclkdig_sel : string := "dis_refclk_dig_sel"
);
port (
refclkdig : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rcvdclkch0 : in std_logic_vector(0 downto 0);
rcvdclkch1 : in std_logic_vector(0 downto 0);
hardrst : in std_logic_vector(0 downto 0);
txpcsrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
dprioagg : in std_logic_vector(63 downto 0);
rcvdclkout : out std_logic_vector(0 downto 0);
rcvdclkouttop : out std_logic_vector(0 downto 0);
rcvdclkoutbot : out std_logic_vector(0 downto 0);
rdenablesynctopch1 : in std_logic_vector(0 downto 0);
txdatatctopch1 : in std_logic_vector(7 downto 0);
txctltctopch1 : in std_logic_vector(0 downto 0);
syncstatustopch1 : in std_logic_vector(0 downto 0);
rdaligntopch1 : in std_logic_vector(1 downto 0);
aligndetsynctopch1 : in std_logic_vector(1 downto 0);
fifordintopch1 : in std_logic_vector(0 downto 0);
alignstatussynctopch1 : in std_logic_vector(0 downto 0);
cgcomprddintopch1 : in std_logic_vector(1 downto 0);
cgcompwrintopch1 : in std_logic_vector(1 downto 0);
delcondmetintopch1 : in std_logic_vector(0 downto 0);
fifoovrintopch1 : in std_logic_vector(0 downto 0);
latencycompintopch1 : in std_logic_vector(0 downto 0);
insertincompleteintopch1 : in std_logic_vector(0 downto 0);
decdatatopch1 : in std_logic_vector(7 downto 0);
decctltopch1 : in std_logic_vector(0 downto 0);
decdatavalidtopch1 : in std_logic_vector(0 downto 0);
runningdisptopch1 : in std_logic_vector(1 downto 0);
txdatatstopch1 : out std_logic_vector(7 downto 0);
txctltstopch1 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch1 : out std_logic_vector(0 downto 0);
endskwqdtopch1 : out std_logic_vector(0 downto 0);
endskwrdptrstopch1 : out std_logic_vector(0 downto 0);
alignstatustopch1 : out std_logic_vector(0 downto 0);
alignstatussync0topch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch1 : out std_logic_vector(0 downto 0);
cgcomprddalltopch1 : out std_logic_vector(0 downto 0);
cgcompwralltopch1 : out std_logic_vector(0 downto 0);
delcondmet0topch1 : out std_logic_vector(0 downto 0);
insertincomplete0topch1 : out std_logic_vector(0 downto 0);
fifoovr0topch1 : out std_logic_vector(0 downto 0);
latencycomp0topch1 : out std_logic_vector(0 downto 0);
rxdatarstopch1 : out std_logic_vector(7 downto 0);
rxctlrstopch1 : out std_logic_vector(0 downto 0);
rdenablesynctopch0 : in std_logic_vector(0 downto 0);
txdatatctopch0 : in std_logic_vector(7 downto 0);
txctltctopch0 : in std_logic_vector(0 downto 0);
syncstatustopch0 : in std_logic_vector(0 downto 0);
rdaligntopch0 : in std_logic_vector(1 downto 0);
aligndetsynctopch0 : in std_logic_vector(1 downto 0);
fifordintopch0 : in std_logic_vector(0 downto 0);
alignstatussynctopch0 : in std_logic_vector(0 downto 0);
cgcomprddintopch0 : in std_logic_vector(1 downto 0);
cgcompwrintopch0 : in std_logic_vector(1 downto 0);
delcondmetintopch0 : in std_logic_vector(0 downto 0);
fifoovrintopch0 : in std_logic_vector(0 downto 0);
latencycompintopch0 : in std_logic_vector(0 downto 0);
insertincompleteintopch0 : in std_logic_vector(0 downto 0);
decdatatopch0 : in std_logic_vector(7 downto 0);
decctltopch0 : in std_logic_vector(0 downto 0);
decdatavalidtopch0 : in std_logic_vector(0 downto 0);
runningdisptopch0 : in std_logic_vector(1 downto 0);
txdatatstopch0 : out std_logic_vector(7 downto 0);
txctltstopch0 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch0 : out std_logic_vector(0 downto 0);
endskwqdtopch0 : out std_logic_vector(0 downto 0);
endskwrdptrstopch0 : out std_logic_vector(0 downto 0);
alignstatustopch0 : out std_logic_vector(0 downto 0);
alignstatussync0topch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch0 : out std_logic_vector(0 downto 0);
cgcomprddalltopch0 : out std_logic_vector(0 downto 0);
cgcompwralltopch0 : out std_logic_vector(0 downto 0);
delcondmet0topch0 : out std_logic_vector(0 downto 0);
insertincomplete0topch0 : out std_logic_vector(0 downto 0);
fifoovr0topch0 : out std_logic_vector(0 downto 0);
latencycomp0topch0 : out std_logic_vector(0 downto 0);
rxdatarstopch0 : out std_logic_vector(7 downto 0);
rxctlrstopch0 : out std_logic_vector(0 downto 0);
rdenablesyncch2 : in std_logic_vector(0 downto 0);
txdatatcch2 : in std_logic_vector(7 downto 0);
txctltcch2 : in std_logic_vector(0 downto 0);
syncstatusch2 : in std_logic_vector(0 downto 0);
rdalignch2 : in std_logic_vector(1 downto 0);
aligndetsyncch2 : in std_logic_vector(1 downto 0);
fifordinch2 : in std_logic_vector(0 downto 0);
alignstatussyncch2 : in std_logic_vector(0 downto 0);
cgcomprddinch2 : in std_logic_vector(1 downto 0);
cgcompwrinch2 : in std_logic_vector(1 downto 0);
delcondmetinch2 : in std_logic_vector(0 downto 0);
fifoovrinch2 : in std_logic_vector(0 downto 0);
latencycompinch2 : in std_logic_vector(0 downto 0);
insertincompleteinch2 : in std_logic_vector(0 downto 0);
decdatach2 : in std_logic_vector(7 downto 0);
decctlch2 : in std_logic_vector(0 downto 0);
decdatavalidch2 : in std_logic_vector(0 downto 0);
runningdispch2 : in std_logic_vector(1 downto 0);
txdatatsch2 : out std_logic_vector(7 downto 0);
txctltsch2 : out std_logic_vector(0 downto 0);
fiforstrdqdch2 : out std_logic_vector(0 downto 0);
endskwqdch2 : out std_logic_vector(0 downto 0);
endskwrdptrsch2 : out std_logic_vector(0 downto 0);
alignstatusch2 : out std_logic_vector(0 downto 0);
alignstatussync0ch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch2 : out std_logic_vector(0 downto 0);
cgcomprddallch2 : out std_logic_vector(0 downto 0);
cgcompwrallch2 : out std_logic_vector(0 downto 0);
delcondmet0ch2 : out std_logic_vector(0 downto 0);
insertincomplete0ch2 : out std_logic_vector(0 downto 0);
fifoovr0ch2 : out std_logic_vector(0 downto 0);
latencycomp0ch2 : out std_logic_vector(0 downto 0);
rxdatarsch2 : out std_logic_vector(7 downto 0);
rxctlrsch2 : out std_logic_vector(0 downto 0);
rdenablesyncch1 : in std_logic_vector(0 downto 0);
txdatatcch1 : in std_logic_vector(7 downto 0);
txctltcch1 : in std_logic_vector(0 downto 0);
syncstatusch1 : in std_logic_vector(0 downto 0);
rdalignch1 : in std_logic_vector(1 downto 0);
aligndetsyncch1 : in std_logic_vector(1 downto 0);
fifordinch1 : in std_logic_vector(0 downto 0);
alignstatussyncch1 : in std_logic_vector(0 downto 0);
cgcomprddinch1 : in std_logic_vector(1 downto 0);
cgcompwrinch1 : in std_logic_vector(1 downto 0);
delcondmetinch1 : in std_logic_vector(0 downto 0);
fifoovrinch1 : in std_logic_vector(0 downto 0);
latencycompinch1 : in std_logic_vector(0 downto 0);
insertincompleteinch1 : in std_logic_vector(0 downto 0);
decdatach1 : in std_logic_vector(7 downto 0);
decctlch1 : in std_logic_vector(0 downto 0);
decdatavalidch1 : in std_logic_vector(0 downto 0);
runningdispch1 : in std_logic_vector(1 downto 0);
txdatatsch1 : out std_logic_vector(7 downto 0);
txctltsch1 : out std_logic_vector(0 downto 0);
fiforstrdqdch1 : out std_logic_vector(0 downto 0);
endskwqdch1 : out std_logic_vector(0 downto 0);
endskwrdptrsch1 : out std_logic_vector(0 downto 0);
alignstatusch1 : out std_logic_vector(0 downto 0);
alignstatussync0ch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch1 : out std_logic_vector(0 downto 0);
cgcomprddallch1 : out std_logic_vector(0 downto 0);
cgcompwrallch1 : out std_logic_vector(0 downto 0);
delcondmet0ch1 : out std_logic_vector(0 downto 0);
insertincomplete0ch1 : out std_logic_vector(0 downto 0);
fifoovr0ch1 : out std_logic_vector(0 downto 0);
latencycomp0ch1 : out std_logic_vector(0 downto 0);
rxdatarsch1 : out std_logic_vector(7 downto 0);
rxctlrsch1 : out std_logic_vector(0 downto 0);
rdenablesyncch0 : in std_logic_vector(0 downto 0);
txdatatcch0 : in std_logic_vector(7 downto 0);
txctltcch0 : in std_logic_vector(0 downto 0);
syncstatusch0 : in std_logic_vector(0 downto 0);
rdalignch0 : in std_logic_vector(1 downto 0);
aligndetsyncch0 : in std_logic_vector(1 downto 0);
fifordinch0 : in std_logic_vector(0 downto 0);
alignstatussyncch0 : in std_logic_vector(0 downto 0);
cgcomprddinch0 : in std_logic_vector(1 downto 0);
cgcompwrinch0 : in std_logic_vector(1 downto 0);
delcondmetinch0 : in std_logic_vector(0 downto 0);
fifoovrinch0 : in std_logic_vector(0 downto 0);
latencycompinch0 : in std_logic_vector(0 downto 0);
insertincompleteinch0 : in std_logic_vector(0 downto 0);
decdatach0 : in std_logic_vector(7 downto 0);
decctlch0 : in std_logic_vector(0 downto 0);
decdatavalidch0 : in std_logic_vector(0 downto 0);
runningdispch0 : in std_logic_vector(1 downto 0);
txdatatsch0 : out std_logic_vector(7 downto 0);
txctltsch0 : out std_logic_vector(0 downto 0);
fiforstrdqdch0 : out std_logic_vector(0 downto 0);
endskwqdch0 : out std_logic_vector(0 downto 0);
endskwrdptrsch0 : out std_logic_vector(0 downto 0);
alignstatusch0 : out std_logic_vector(0 downto 0);
alignstatussync0ch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch0 : out std_logic_vector(0 downto 0);
cgcomprddallch0 : out std_logic_vector(0 downto 0);
cgcompwrallch0 : out std_logic_vector(0 downto 0);
delcondmet0ch0 : out std_logic_vector(0 downto 0);
insertincomplete0ch0 : out std_logic_vector(0 downto 0);
fifoovr0ch0 : out std_logic_vector(0 downto 0);
latencycomp0ch0 : out std_logic_vector(0 downto 0);
rxdatarsch0 : out std_logic_vector(7 downto 0);
rxctlrsch0 : out std_logic_vector(0 downto 0);
rdenablesyncbotch2 : in std_logic_vector(0 downto 0);
txdatatcbotch2 : in std_logic_vector(7 downto 0);
txctltcbotch2 : in std_logic_vector(0 downto 0);
syncstatusbotch2 : in std_logic_vector(0 downto 0);
rdalignbotch2 : in std_logic_vector(1 downto 0);
aligndetsyncbotch2 : in std_logic_vector(1 downto 0);
fifordinbotch2 : in std_logic_vector(0 downto 0);
alignstatussyncbotch2 : in std_logic_vector(0 downto 0);
cgcomprddinbotch2 : in std_logic_vector(1 downto 0);
cgcompwrinbotch2 : in std_logic_vector(1 downto 0);
delcondmetinbotch2 : in std_logic_vector(0 downto 0);
fifoovrinbotch2 : in std_logic_vector(0 downto 0);
latencycompinbotch2 : in std_logic_vector(0 downto 0);
insertincompleteinbotch2 : in std_logic_vector(0 downto 0);
decdatabotch2 : in std_logic_vector(7 downto 0);
decctlbotch2 : in std_logic_vector(0 downto 0);
decdatavalidbotch2 : in std_logic_vector(0 downto 0);
runningdispbotch2 : in std_logic_vector(1 downto 0);
txdatatsbotch2 : out std_logic_vector(7 downto 0);
txctltsbotch2 : out std_logic_vector(0 downto 0);
fiforstrdqdbotch2 : out std_logic_vector(0 downto 0);
endskwqdbotch2 : out std_logic_vector(0 downto 0);
endskwrdptrsbotch2 : out std_logic_vector(0 downto 0);
alignstatusbotch2 : out std_logic_vector(0 downto 0);
alignstatussync0botch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0botch2 : out std_logic_vector(0 downto 0);
cgcomprddallbotch2 : out std_logic_vector(0 downto 0);
cgcompwrallbotch2 : out std_logic_vector(0 downto 0);
delcondmet0botch2 : out std_logic_vector(0 downto 0);
insertincomplete0botch2 : out std_logic_vector(0 downto 0);
fifoovr0botch2 : out std_logic_vector(0 downto 0);
latencycomp0botch2 : out std_logic_vector(0 downto 0);
rxdatarsbotch2 : out std_logic_vector(7 downto 0);
rxctlrsbotch2 : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_pcs_aggregate;
architecture behavior of stratixv_hssi_8g_pcs_aggregate is
component stratixv_hssi_8g_pcs_aggregate_encrypted
generic (
xaui_sm_operation : string := "en_xaui_sm";
dskw_sm_operation : string := "dskw_xaui_sm";
data_agg_bonding : string := "agg_disable";
prot_mode_tx : string := "pipe_g1_tx";
pcs_dw_datapath : string := "sw_data_path";
dskw_control : string := "dskw_write_control";
refclkdig_sel : string := "dis_refclk_dig_sel"
);
port (
refclkdig : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rcvdclkch0 : in std_logic_vector(0 downto 0);
rcvdclkch1 : in std_logic_vector(0 downto 0);
hardrst : in std_logic_vector(0 downto 0);
txpcsrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
dprioagg : in std_logic_vector(63 downto 0);
rcvdclkout : out std_logic_vector(0 downto 0);
rcvdclkouttop : out std_logic_vector(0 downto 0);
rcvdclkoutbot : out std_logic_vector(0 downto 0);
rdenablesynctopch1 : in std_logic_vector(0 downto 0);
txdatatctopch1 : in std_logic_vector(7 downto 0);
txctltctopch1 : in std_logic_vector(0 downto 0);
syncstatustopch1 : in std_logic_vector(0 downto 0);
rdaligntopch1 : in std_logic_vector(1 downto 0);
aligndetsynctopch1 : in std_logic_vector(1 downto 0);
fifordintopch1 : in std_logic_vector(0 downto 0);
alignstatussynctopch1 : in std_logic_vector(0 downto 0);
cgcomprddintopch1 : in std_logic_vector(1 downto 0);
cgcompwrintopch1 : in std_logic_vector(1 downto 0);
delcondmetintopch1 : in std_logic_vector(0 downto 0);
fifoovrintopch1 : in std_logic_vector(0 downto 0);
latencycompintopch1 : in std_logic_vector(0 downto 0);
insertincompleteintopch1 : in std_logic_vector(0 downto 0);
decdatatopch1 : in std_logic_vector(7 downto 0);
decctltopch1 : in std_logic_vector(0 downto 0);
decdatavalidtopch1 : in std_logic_vector(0 downto 0);
runningdisptopch1 : in std_logic_vector(1 downto 0);
txdatatstopch1 : out std_logic_vector(7 downto 0);
txctltstopch1 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch1 : out std_logic_vector(0 downto 0);
endskwqdtopch1 : out std_logic_vector(0 downto 0);
endskwrdptrstopch1 : out std_logic_vector(0 downto 0);
alignstatustopch1 : out std_logic_vector(0 downto 0);
alignstatussync0topch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch1 : out std_logic_vector(0 downto 0);
cgcomprddalltopch1 : out std_logic_vector(0 downto 0);
cgcompwralltopch1 : out std_logic_vector(0 downto 0);
delcondmet0topch1 : out std_logic_vector(0 downto 0);
insertincomplete0topch1 : out std_logic_vector(0 downto 0);
fifoovr0topch1 : out std_logic_vector(0 downto 0);
latencycomp0topch1 : out std_logic_vector(0 downto 0);
rxdatarstopch1 : out std_logic_vector(7 downto 0);
rxctlrstopch1 : out std_logic_vector(0 downto 0);
rdenablesynctopch0 : in std_logic_vector(0 downto 0);
txdatatctopch0 : in std_logic_vector(7 downto 0);
txctltctopch0 : in std_logic_vector(0 downto 0);
syncstatustopch0 : in std_logic_vector(0 downto 0);
rdaligntopch0 : in std_logic_vector(1 downto 0);
aligndetsynctopch0 : in std_logic_vector(1 downto 0);
fifordintopch0 : in std_logic_vector(0 downto 0);
alignstatussynctopch0 : in std_logic_vector(0 downto 0);
cgcomprddintopch0 : in std_logic_vector(1 downto 0);
cgcompwrintopch0 : in std_logic_vector(1 downto 0);
delcondmetintopch0 : in std_logic_vector(0 downto 0);
fifoovrintopch0 : in std_logic_vector(0 downto 0);
latencycompintopch0 : in std_logic_vector(0 downto 0);
insertincompleteintopch0 : in std_logic_vector(0 downto 0);
decdatatopch0 : in std_logic_vector(7 downto 0);
decctltopch0 : in std_logic_vector(0 downto 0);
decdatavalidtopch0 : in std_logic_vector(0 downto 0);
runningdisptopch0 : in std_logic_vector(1 downto 0);
txdatatstopch0 : out std_logic_vector(7 downto 0);
txctltstopch0 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch0 : out std_logic_vector(0 downto 0);
endskwqdtopch0 : out std_logic_vector(0 downto 0);
endskwrdptrstopch0 : out std_logic_vector(0 downto 0);
alignstatustopch0 : out std_logic_vector(0 downto 0);
alignstatussync0topch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch0 : out std_logic_vector(0 downto 0);
cgcomprddalltopch0 : out std_logic_vector(0 downto 0);
cgcompwralltopch0 : out std_logic_vector(0 downto 0);
delcondmet0topch0 : out std_logic_vector(0 downto 0);
insertincomplete0topch0 : out std_logic_vector(0 downto 0);
fifoovr0topch0 : out std_logic_vector(0 downto 0);
latencycomp0topch0 : out std_logic_vector(0 downto 0);
rxdatarstopch0 : out std_logic_vector(7 downto 0);
rxctlrstopch0 : out std_logic_vector(0 downto 0);
rdenablesyncch2 : in std_logic_vector(0 downto 0);
txdatatcch2 : in std_logic_vector(7 downto 0);
txctltcch2 : in std_logic_vector(0 downto 0);
syncstatusch2 : in std_logic_vector(0 downto 0);
rdalignch2 : in std_logic_vector(1 downto 0);
aligndetsyncch2 : in std_logic_vector(1 downto 0);
fifordinch2 : in std_logic_vector(0 downto 0);
alignstatussyncch2 : in std_logic_vector(0 downto 0);
cgcomprddinch2 : in std_logic_vector(1 downto 0);
cgcompwrinch2 : in std_logic_vector(1 downto 0);
delcondmetinch2 : in std_logic_vector(0 downto 0);
fifoovrinch2 : in std_logic_vector(0 downto 0);
latencycompinch2 : in std_logic_vector(0 downto 0);
insertincompleteinch2 : in std_logic_vector(0 downto 0);
decdatach2 : in std_logic_vector(7 downto 0);
decctlch2 : in std_logic_vector(0 downto 0);
decdatavalidch2 : in std_logic_vector(0 downto 0);
runningdispch2 : in std_logic_vector(1 downto 0);
txdatatsch2 : out std_logic_vector(7 downto 0);
txctltsch2 : out std_logic_vector(0 downto 0);
fiforstrdqdch2 : out std_logic_vector(0 downto 0);
endskwqdch2 : out std_logic_vector(0 downto 0);
endskwrdptrsch2 : out std_logic_vector(0 downto 0);
alignstatusch2 : out std_logic_vector(0 downto 0);
alignstatussync0ch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch2 : out std_logic_vector(0 downto 0);
cgcomprddallch2 : out std_logic_vector(0 downto 0);
cgcompwrallch2 : out std_logic_vector(0 downto 0);
delcondmet0ch2 : out std_logic_vector(0 downto 0);
insertincomplete0ch2 : out std_logic_vector(0 downto 0);
fifoovr0ch2 : out std_logic_vector(0 downto 0);
latencycomp0ch2 : out std_logic_vector(0 downto 0);
rxdatarsch2 : out std_logic_vector(7 downto 0);
rxctlrsch2 : out std_logic_vector(0 downto 0);
rdenablesyncch1 : in std_logic_vector(0 downto 0);
txdatatcch1 : in std_logic_vector(7 downto 0);
txctltcch1 : in std_logic_vector(0 downto 0);
syncstatusch1 : in std_logic_vector(0 downto 0);
rdalignch1 : in std_logic_vector(1 downto 0);
aligndetsyncch1 : in std_logic_vector(1 downto 0);
fifordinch1 : in std_logic_vector(0 downto 0);
alignstatussyncch1 : in std_logic_vector(0 downto 0);
cgcomprddinch1 : in std_logic_vector(1 downto 0);
cgcompwrinch1 : in std_logic_vector(1 downto 0);
delcondmetinch1 : in std_logic_vector(0 downto 0);
fifoovrinch1 : in std_logic_vector(0 downto 0);
latencycompinch1 : in std_logic_vector(0 downto 0);
insertincompleteinch1 : in std_logic_vector(0 downto 0);
decdatach1 : in std_logic_vector(7 downto 0);
decctlch1 : in std_logic_vector(0 downto 0);
decdatavalidch1 : in std_logic_vector(0 downto 0);
runningdispch1 : in std_logic_vector(1 downto 0);
txdatatsch1 : out std_logic_vector(7 downto 0);
txctltsch1 : out std_logic_vector(0 downto 0);
fiforstrdqdch1 : out std_logic_vector(0 downto 0);
endskwqdch1 : out std_logic_vector(0 downto 0);
endskwrdptrsch1 : out std_logic_vector(0 downto 0);
alignstatusch1 : out std_logic_vector(0 downto 0);
alignstatussync0ch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch1 : out std_logic_vector(0 downto 0);
cgcomprddallch1 : out std_logic_vector(0 downto 0);
cgcompwrallch1 : out std_logic_vector(0 downto 0);
delcondmet0ch1 : out std_logic_vector(0 downto 0);
insertincomplete0ch1 : out std_logic_vector(0 downto 0);
fifoovr0ch1 : out std_logic_vector(0 downto 0);
latencycomp0ch1 : out std_logic_vector(0 downto 0);
rxdatarsch1 : out std_logic_vector(7 downto 0);
rxctlrsch1 : out std_logic_vector(0 downto 0);
rdenablesyncch0 : in std_logic_vector(0 downto 0);
txdatatcch0 : in std_logic_vector(7 downto 0);
txctltcch0 : in std_logic_vector(0 downto 0);
syncstatusch0 : in std_logic_vector(0 downto 0);
rdalignch0 : in std_logic_vector(1 downto 0);
aligndetsyncch0 : in std_logic_vector(1 downto 0);
fifordinch0 : in std_logic_vector(0 downto 0);
alignstatussyncch0 : in std_logic_vector(0 downto 0);
cgcomprddinch0 : in std_logic_vector(1 downto 0);
cgcompwrinch0 : in std_logic_vector(1 downto 0);
delcondmetinch0 : in std_logic_vector(0 downto 0);
fifoovrinch0 : in std_logic_vector(0 downto 0);
latencycompinch0 : in std_logic_vector(0 downto 0);
insertincompleteinch0 : in std_logic_vector(0 downto 0);
decdatach0 : in std_logic_vector(7 downto 0);
decctlch0 : in std_logic_vector(0 downto 0);
decdatavalidch0 : in std_logic_vector(0 downto 0);
runningdispch0 : in std_logic_vector(1 downto 0);
txdatatsch0 : out std_logic_vector(7 downto 0);
txctltsch0 : out std_logic_vector(0 downto 0);
fiforstrdqdch0 : out std_logic_vector(0 downto 0);
endskwqdch0 : out std_logic_vector(0 downto 0);
endskwrdptrsch0 : out std_logic_vector(0 downto 0);
alignstatusch0 : out std_logic_vector(0 downto 0);
alignstatussync0ch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch0 : out std_logic_vector(0 downto 0);
cgcomprddallch0 : out std_logic_vector(0 downto 0);
cgcompwrallch0 : out std_logic_vector(0 downto 0);
delcondmet0ch0 : out std_logic_vector(0 downto 0);
insertincomplete0ch0 : out std_logic_vector(0 downto 0);
fifoovr0ch0 : out std_logic_vector(0 downto 0);
latencycomp0ch0 : out std_logic_vector(0 downto 0);
rxdatarsch0 : out std_logic_vector(7 downto 0);
rxctlrsch0 : out std_logic_vector(0 downto 0);
rdenablesyncbotch2 : in std_logic_vector(0 downto 0);
txdatatcbotch2 : in std_logic_vector(7 downto 0);
txctltcbotch2 : in std_logic_vector(0 downto 0);
syncstatusbotch2 : in std_logic_vector(0 downto 0);
rdalignbotch2 : in std_logic_vector(1 downto 0);
aligndetsyncbotch2 : in std_logic_vector(1 downto 0);
fifordinbotch2 : in std_logic_vector(0 downto 0);
alignstatussyncbotch2 : in std_logic_vector(0 downto 0);
cgcomprddinbotch2 : in std_logic_vector(1 downto 0);
cgcompwrinbotch2 : in std_logic_vector(1 downto 0);
delcondmetinbotch2 : in std_logic_vector(0 downto 0);
fifoovrinbotch2 : in std_logic_vector(0 downto 0);
latencycompinbotch2 : in std_logic_vector(0 downto 0);
insertincompleteinbotch2 : in std_logic_vector(0 downto 0);
decdatabotch2 : in std_logic_vector(7 downto 0);
decctlbotch2 : in std_logic_vector(0 downto 0);
decdatavalidbotch2 : in std_logic_vector(0 downto 0);
runningdispbotch2 : in std_logic_vector(1 downto 0);
txdatatsbotch2 : out std_logic_vector(7 downto 0);
txctltsbotch2 : out std_logic_vector(0 downto 0);
fiforstrdqdbotch2 : out std_logic_vector(0 downto 0);
endskwqdbotch2 : out std_logic_vector(0 downto 0);
endskwrdptrsbotch2 : out std_logic_vector(0 downto 0);
alignstatusbotch2 : out std_logic_vector(0 downto 0);
alignstatussync0botch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0botch2 : out std_logic_vector(0 downto 0);
cgcomprddallbotch2 : out std_logic_vector(0 downto 0);
cgcompwrallbotch2 : out std_logic_vector(0 downto 0);
delcondmet0botch2 : out std_logic_vector(0 downto 0);
insertincomplete0botch2 : out std_logic_vector(0 downto 0);
fifoovr0botch2 : out std_logic_vector(0 downto 0);
latencycomp0botch2 : out std_logic_vector(0 downto 0);
rxdatarsbotch2 : out std_logic_vector(7 downto 0);
rxctlrsbotch2 : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_pcs_aggregate_encrypted
generic map (
xaui_sm_operation => xaui_sm_operation,
dskw_sm_operation => dskw_sm_operation,
data_agg_bonding => data_agg_bonding,
prot_mode_tx => prot_mode_tx,
pcs_dw_datapath => pcs_dw_datapath,
dskw_control => dskw_control,
refclkdig_sel => refclkdig_sel
)
port map (
refclkdig => refclkdig,
scanmoden => scanmoden,
scanshiftn => scanshiftn,
txpmaclk => txpmaclk,
rcvdclkch0 => rcvdclkch0,
rcvdclkch1 => rcvdclkch1,
hardrst => hardrst,
txpcsrst => txpcsrst,
rxpcsrst => rxpcsrst,
dprioagg => dprioagg,
rcvdclkout => rcvdclkout,
rcvdclkouttop => rcvdclkouttop,
rcvdclkoutbot => rcvdclkoutbot,
rdenablesynctopch1 => rdenablesynctopch1,
txdatatctopch1 => txdatatctopch1,
txctltctopch1 => txctltctopch1,
syncstatustopch1 => syncstatustopch1,
rdaligntopch1 => rdaligntopch1,
aligndetsynctopch1 => aligndetsynctopch1,
fifordintopch1 => fifordintopch1,
alignstatussynctopch1 => alignstatussynctopch1,
cgcomprddintopch1 => cgcomprddintopch1,
cgcompwrintopch1 => cgcompwrintopch1,
delcondmetintopch1 => delcondmetintopch1,
fifoovrintopch1 => fifoovrintopch1,
latencycompintopch1 => latencycompintopch1,
insertincompleteintopch1 => insertincompleteintopch1,
decdatatopch1 => decdatatopch1,
decctltopch1 => decctltopch1,
decdatavalidtopch1 => decdatavalidtopch1,
runningdisptopch1 => runningdisptopch1,
txdatatstopch1 => txdatatstopch1,
txctltstopch1 => txctltstopch1,
fiforstrdqdtopch1 => fiforstrdqdtopch1,
endskwqdtopch1 => endskwqdtopch1,
endskwrdptrstopch1 => endskwrdptrstopch1,
alignstatustopch1 => alignstatustopch1,
alignstatussync0topch1 => alignstatussync0topch1,
fifordoutcomp0topch1 => fifordoutcomp0topch1,
cgcomprddalltopch1 => cgcomprddalltopch1,
cgcompwralltopch1 => cgcompwralltopch1,
delcondmet0topch1 => delcondmet0topch1,
insertincomplete0topch1 => insertincomplete0topch1,
fifoovr0topch1 => fifoovr0topch1,
latencycomp0topch1 => latencycomp0topch1,
rxdatarstopch1 => rxdatarstopch1,
rxctlrstopch1 => rxctlrstopch1,
rdenablesynctopch0 => rdenablesynctopch0,
txdatatctopch0 => txdatatctopch0,
txctltctopch0 => txctltctopch0,
syncstatustopch0 => syncstatustopch0,
rdaligntopch0 => rdaligntopch0,
aligndetsynctopch0 => aligndetsynctopch0,
fifordintopch0 => fifordintopch0,
alignstatussynctopch0 => alignstatussynctopch0,
cgcomprddintopch0 => cgcomprddintopch0,
cgcompwrintopch0 => cgcompwrintopch0,
delcondmetintopch0 => delcondmetintopch0,
fifoovrintopch0 => fifoovrintopch0,
latencycompintopch0 => latencycompintopch0,
insertincompleteintopch0 => insertincompleteintopch0,
decdatatopch0 => decdatatopch0,
decctltopch0 => decctltopch0,
decdatavalidtopch0 => decdatavalidtopch0,
runningdisptopch0 => runningdisptopch0,
txdatatstopch0 => txdatatstopch0,
txctltstopch0 => txctltstopch0,
fiforstrdqdtopch0 => fiforstrdqdtopch0,
endskwqdtopch0 => endskwqdtopch0,
endskwrdptrstopch0 => endskwrdptrstopch0,
alignstatustopch0 => alignstatustopch0,
alignstatussync0topch0 => alignstatussync0topch0,
fifordoutcomp0topch0 => fifordoutcomp0topch0,
cgcomprddalltopch0 => cgcomprddalltopch0,
cgcompwralltopch0 => cgcompwralltopch0,
delcondmet0topch0 => delcondmet0topch0,
insertincomplete0topch0 => insertincomplete0topch0,
fifoovr0topch0 => fifoovr0topch0,
latencycomp0topch0 => latencycomp0topch0,
rxdatarstopch0 => rxdatarstopch0,
rxctlrstopch0 => rxctlrstopch0,
rdenablesyncch2 => rdenablesyncch2,
txdatatcch2 => txdatatcch2,
txctltcch2 => txctltcch2,
syncstatusch2 => syncstatusch2,
rdalignch2 => rdalignch2,
aligndetsyncch2 => aligndetsyncch2,
fifordinch2 => fifordinch2,
alignstatussyncch2 => alignstatussyncch2,
cgcomprddinch2 => cgcomprddinch2,
cgcompwrinch2 => cgcompwrinch2,
delcondmetinch2 => delcondmetinch2,
fifoovrinch2 => fifoovrinch2,
latencycompinch2 => latencycompinch2,
insertincompleteinch2 => insertincompleteinch2,
decdatach2 => decdatach2,
decctlch2 => decctlch2,
decdatavalidch2 => decdatavalidch2,
runningdispch2 => runningdispch2,
txdatatsch2 => txdatatsch2,
txctltsch2 => txctltsch2,
fiforstrdqdch2 => fiforstrdqdch2,
endskwqdch2 => endskwqdch2,
endskwrdptrsch2 => endskwrdptrsch2,
alignstatusch2 => alignstatusch2,
alignstatussync0ch2 => alignstatussync0ch2,
fifordoutcomp0ch2 => fifordoutcomp0ch2,
cgcomprddallch2 => cgcomprddallch2,
cgcompwrallch2 => cgcompwrallch2,
delcondmet0ch2 => delcondmet0ch2,
insertincomplete0ch2 => insertincomplete0ch2,
fifoovr0ch2 => fifoovr0ch2,
latencycomp0ch2 => latencycomp0ch2,
rxdatarsch2 => rxdatarsch2,
rxctlrsch2 => rxctlrsch2,
rdenablesyncch1 => rdenablesyncch1,
txdatatcch1 => txdatatcch1,
txctltcch1 => txctltcch1,
syncstatusch1 => syncstatusch1,
rdalignch1 => rdalignch1,
aligndetsyncch1 => aligndetsyncch1,
fifordinch1 => fifordinch1,
alignstatussyncch1 => alignstatussyncch1,
cgcomprddinch1 => cgcomprddinch1,
cgcompwrinch1 => cgcompwrinch1,
delcondmetinch1 => delcondmetinch1,
fifoovrinch1 => fifoovrinch1,
latencycompinch1 => latencycompinch1,
insertincompleteinch1 => insertincompleteinch1,
decdatach1 => decdatach1,
decctlch1 => decctlch1,
decdatavalidch1 => decdatavalidch1,
runningdispch1 => runningdispch1,
txdatatsch1 => txdatatsch1,
txctltsch1 => txctltsch1,
fiforstrdqdch1 => fiforstrdqdch1,
endskwqdch1 => endskwqdch1,
endskwrdptrsch1 => endskwrdptrsch1,
alignstatusch1 => alignstatusch1,
alignstatussync0ch1 => alignstatussync0ch1,
fifordoutcomp0ch1 => fifordoutcomp0ch1,
cgcomprddallch1 => cgcomprddallch1,
cgcompwrallch1 => cgcompwrallch1,
delcondmet0ch1 => delcondmet0ch1,
insertincomplete0ch1 => insertincomplete0ch1,
fifoovr0ch1 => fifoovr0ch1,
latencycomp0ch1 => latencycomp0ch1,
rxdatarsch1 => rxdatarsch1,
rxctlrsch1 => rxctlrsch1,
rdenablesyncch0 => rdenablesyncch0,
txdatatcch0 => txdatatcch0,
txctltcch0 => txctltcch0,
syncstatusch0 => syncstatusch0,
rdalignch0 => rdalignch0,
aligndetsyncch0 => aligndetsyncch0,
fifordinch0 => fifordinch0,
alignstatussyncch0 => alignstatussyncch0,
cgcomprddinch0 => cgcomprddinch0,
cgcompwrinch0 => cgcompwrinch0,
delcondmetinch0 => delcondmetinch0,
fifoovrinch0 => fifoovrinch0,
latencycompinch0 => latencycompinch0,
insertincompleteinch0 => insertincompleteinch0,
decdatach0 => decdatach0,
decctlch0 => decctlch0,
decdatavalidch0 => decdatavalidch0,
runningdispch0 => runningdispch0,
txdatatsch0 => txdatatsch0,
txctltsch0 => txctltsch0,
fiforstrdqdch0 => fiforstrdqdch0,
endskwqdch0 => endskwqdch0,
endskwrdptrsch0 => endskwrdptrsch0,
alignstatusch0 => alignstatusch0,
alignstatussync0ch0 => alignstatussync0ch0,
fifordoutcomp0ch0 => fifordoutcomp0ch0,
cgcomprddallch0 => cgcomprddallch0,
cgcompwrallch0 => cgcompwrallch0,
delcondmet0ch0 => delcondmet0ch0,
insertincomplete0ch0 => insertincomplete0ch0,
fifoovr0ch0 => fifoovr0ch0,
latencycomp0ch0 => latencycomp0ch0,
rxdatarsch0 => rxdatarsch0,
rxctlrsch0 => rxctlrsch0,
rdenablesyncbotch2 => rdenablesyncbotch2,
txdatatcbotch2 => txdatatcbotch2,
txctltcbotch2 => txctltcbotch2,
syncstatusbotch2 => syncstatusbotch2,
rdalignbotch2 => rdalignbotch2,
aligndetsyncbotch2 => aligndetsyncbotch2,
fifordinbotch2 => fifordinbotch2,
alignstatussyncbotch2 => alignstatussyncbotch2,
cgcomprddinbotch2 => cgcomprddinbotch2,
cgcompwrinbotch2 => cgcompwrinbotch2,
delcondmetinbotch2 => delcondmetinbotch2,
fifoovrinbotch2 => fifoovrinbotch2,
latencycompinbotch2 => latencycompinbotch2,
insertincompleteinbotch2 => insertincompleteinbotch2,
decdatabotch2 => decdatabotch2,
decctlbotch2 => decctlbotch2,
decdatavalidbotch2 => decdatavalidbotch2,
runningdispbotch2 => runningdispbotch2,
txdatatsbotch2 => txdatatsbotch2,
txctltsbotch2 => txctltsbotch2,
fiforstrdqdbotch2 => fiforstrdqdbotch2,
endskwqdbotch2 => endskwqdbotch2,
endskwrdptrsbotch2 => endskwrdptrsbotch2,
alignstatusbotch2 => alignstatusbotch2,
alignstatussync0botch2 => alignstatussync0botch2,
fifordoutcomp0botch2 => fifordoutcomp0botch2,
cgcomprddallbotch2 => cgcomprddallbotch2,
cgcompwrallbotch2 => cgcompwrallbotch2,
delcondmet0botch2 => delcondmet0botch2,
insertincomplete0botch2 => insertincomplete0botch2,
fifoovr0botch2 => fifoovr0botch2,
latencycomp0botch2 => latencycomp0botch2,
rxdatarsbotch2 => rxdatarsbotch2,
rxctlrsbotch2 => rxctlrsbotch2
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_rx_pcs is
generic (
prot_mode : string := "gige";
tx_rx_parallel_loopback : string := "dis_plpbk";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
polarity_inversion : string := "dis_pol_inv";
wa_pd : string := "wa_pd_10";
wa_pd_data : bit_vector := B"0000000000000000000000000000000000000000";
wa_boundary_lock_ctrl : string := "bit_slip";
wa_pld_controlled : string := "dis_pld_ctrl";
wa_sync_sm_ctrl : string := "gige_sync_sm";
wa_rknumber_data : bit_vector := B"00000000";
wa_renumber_data : bit_vector := B"000000";
wa_rgnumber_data : bit_vector := B"00000000";
wa_rosnumber_data : bit_vector := B"00";
wa_kchar : string := "dis_kchar";
wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm";
wa_clk_slip_spacing : string := "min_clk_slip_spacing";
wa_clk_slip_spacing_data : bit_vector := B"0000010000";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
deskew_pattern : bit_vector := B"1101101000";
deskew_prog_pattern_only : string := "en_deskew_prog_pat_only";
rate_match : string := "dis_rm";
eightb_tenb_decoder : string := "dis_8b10b";
err_flags_sel : string := "err_flags_wa";
polinv_8b10b_dec : string := "dis_polinv_8b10b_dec";
eightbtenb_decoder_output_sel : string := "data_8b10b_decoder";
invalid_code_flag_only : string := "dis_invalid_code_only";
auto_error_replacement : string := "dis_err_replace";
pad_or_edb_error_replace : string := "replace_edb";
byte_deserializer : string := "dis_bds";
byte_order : string := "dis_bo";
re_bo_on_wa : string := "dis_re_bo_on_wa";
bo_pattern : bit_vector := B"00000000000000000000";
bo_pad : bit_vector := B"0000000000";
phase_compensation_fifo : string := "low_latency";
prbs_ver : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_ver : string := "dis_bist";
cdr_ctrl : string := "dis_cdr_ctrl";
cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask";
wait_cnt : bit_vector := B"00000000";
mask_cnt : bit_vector := B"1111111111";
auto_deassert_pc_rst_cnt_data : bit_vector := B"00000";
auto_pc_en_cnt_data : bit_vector := B"0000000";
eidle_entry_sd : string := "dis_eidle_sd";
eidle_entry_eios : string := "dis_eidle_eios";
eidle_entry_iei : string := "dis_eidle_iei";
rx_rcvd_clk : string := "rcvd_clk_rcvd_clk";
rx_clk1 : string := "rcvd_clk_clk1";
rx_clk2 : string := "rcvd_clk_clk2";
rx_rd_clk : string := "pld_rx_clk";
dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo";
comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
agg_block_sel : string := "same_smrt_pack";
test_bus_sel : string := "test_bus_sel";
wa_rvnumber_data : bit_vector := B"0000000000000";
ctrl_plane_bonding_compensation : string := "dis_compensation";
clock_gate_rx : string := "dis_clk_gating";
prbs_ver_clr_flag : string := "dis_prbs_clr_flag";
hip_mode : string := "dis_hip";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
ctrl_plane_bonding_consumption : string := "individual";
pma_done_count : bit_vector := B"000000000000000000";
test_mode : string := "prbs";
bist_ver_clr_flag : string := "dis_bist_clr_flag";
wa_disp_err_flag : string := "dis_disp_err_flag";
wait_for_phfifo_cnt_data : bit_vector := B"000000";
runlength_check : string := "en_runlength_sw";
test_bus_sel_val : bit_vector := B"0000";
runlength_val : bit_vector := B"000000";
force_signal_detect : string := "en_force_signal_detect";
deskew : string := "dis_deskew";
rx_wr_clk : string := "rx_clk2_div_1_2_4";
rx_clk_free_running : string := "en_rx_clk_free_run";
rx_pcs_urst : string := "en_rx_pcs_urst";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
pipe_if_enable : string := "dis_pipe_rx";
pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
ibm_invalid_code : string := "dis_ibm_invalid_code";
channel_number : string := "int";
rx_refclk : string := "dis_refclk_sel"
);
port (
hrdrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
rmfifouserrst : in std_logic_vector(0 downto 0);
phfifouserrst : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
enablecommadetect : in std_logic_vector(0 downto 0);
a1a2size : in std_logic_vector(0 downto 0);
bitslip : in std_logic_vector(0 downto 0);
rmfiforeadenable : in std_logic_vector(0 downto 0);
rmfifowriteenable : in std_logic_vector(0 downto 0);
pldrxclk : in std_logic_vector(0 downto 0);
softresetrclk1 : out std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
bitreversalenable : in std_logic_vector(0 downto 0);
bytereversalenable : in std_logic_vector(0 downto 0);
rcvdclkpma : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(19 downto 0);
sigdetfrompma : in std_logic_vector(0 downto 0);
fiforstrdqd : in std_logic_vector(0 downto 0);
endskwqd : in std_logic_vector(0 downto 0);
endskwrdptrs : in std_logic_vector(0 downto 0);
alignstatus : in std_logic_vector(0 downto 0);
fiforstrdqdtoporbot : in std_logic_vector(0 downto 0);
endskwqdtoporbot : in std_logic_vector(0 downto 0);
endskwrdptrstoporbot : in std_logic_vector(0 downto 0);
alignstatustoporbot : in std_logic_vector(0 downto 0);
datafrinaggblock : in std_logic_vector(7 downto 0);
ctrlfromaggblock : in std_logic_vector(0 downto 0);
rxdatarstoporbot : in std_logic_vector(7 downto 0);
rxcontrolrstoporbot : in std_logic_vector(0 downto 0);
rcvdclk0pma : in std_logic_vector(0 downto 0);
parallelloopback : in std_logic_vector(19 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
byteorder : in std_logic_vector(0 downto 0);
pxfifowrdisable : in std_logic_vector(0 downto 0);
pcfifordenable : in std_logic_vector(0 downto 0);
pmatestbus : in std_logic_vector(7 downto 0);
encodertestbus : in std_logic_vector(9 downto 0);
txctrltestbus : in std_logic_vector(9 downto 0);
phystatusinternal : in std_logic_vector(0 downto 0);
rxvalidinternal : in std_logic_vector(0 downto 0);
rxstatusinternal : in std_logic_vector(2 downto 0);
phystatuspcsgen3 : in std_logic_vector(0 downto 0);
rxvalidpcsgen3 : in std_logic_vector(0 downto 0);
rxstatuspcsgen3 : in std_logic_vector(2 downto 0);
rxdatavalidpcsgen3 : in std_logic_vector(3 downto 0);
rxblkstartpcsgen3 : in std_logic_vector(3 downto 0);
rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0);
rxdatapcsgen3 : in std_logic_vector(63 downto 0);
pipepowerdown : in std_logic_vector(1 downto 0);
rateswitchcontrol : in std_logic_vector(0 downto 0);
gen2ngen1 : in std_logic_vector(0 downto 0);
gen2ngen1bundle : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
pipeloopbk : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
txdiv2syncoutpipeup : in std_logic_vector(0 downto 0);
fifoselectoutpipeup : in std_logic_vector(0 downto 0);
txwrenableoutpipeup : in std_logic_vector(0 downto 0);
txrdenableoutpipeup : in std_logic_vector(0 downto 0);
txdiv2syncoutpipedown : in std_logic_vector(0 downto 0);
fifoselectoutpipedown : in std_logic_vector(0 downto 0);
txwrenableoutpipedown : in std_logic_vector(0 downto 0);
txrdenableoutpipedown : in std_logic_vector(0 downto 0);
alignstatussync0 : in std_logic_vector(0 downto 0);
rmfifordincomp0 : in std_logic_vector(0 downto 0);
cgcomprddall : in std_logic_vector(0 downto 0);
cgcompwrall : in std_logic_vector(0 downto 0);
delcondmet0 : in std_logic_vector(0 downto 0);
fifoovr0 : in std_logic_vector(0 downto 0);
latencycomp0 : in std_logic_vector(0 downto 0);
insertincomplete0 : in std_logic_vector(0 downto 0);
alignstatussync0toporbot : in std_logic_vector(0 downto 0);
fifordincomp0toporbot : in std_logic_vector(0 downto 0);
cgcomprddalltoporbot : in std_logic_vector(0 downto 0);
cgcompwralltoporbot : in std_logic_vector(0 downto 0);
delcondmet0toporbot : in std_logic_vector(0 downto 0);
fifoovr0toporbot : in std_logic_vector(0 downto 0);
latencycomp0toporbot : in std_logic_vector(0 downto 0);
insertincomplete0toporbot : in std_logic_vector(0 downto 0);
alignstatussync : out std_logic_vector(0 downto 0);
fifordoutcomp : out std_logic_vector(0 downto 0);
cgcomprddout : out std_logic_vector(1 downto 0);
cgcompwrout : out std_logic_vector(1 downto 0);
delcondmetout : out std_logic_vector(0 downto 0);
fifoovrout : out std_logic_vector(0 downto 0);
latencycompout : out std_logic_vector(0 downto 0);
insertincompleteout : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(63 downto 0);
parallelrevloopback : out std_logic_vector(19 downto 0);
clocktopld : out std_logic_vector(0 downto 0);
bisterr : out std_logic_vector(0 downto 0);
clk2b : out std_logic_vector(0 downto 0);
rcvdclkpmab : out std_logic_vector(0 downto 0);
syncstatus : out std_logic_vector(0 downto 0);
decoderdatavalid : out std_logic_vector(0 downto 0);
decoderdata : out std_logic_vector(7 downto 0);
decoderctrl : out std_logic_vector(0 downto 0);
runningdisparity : out std_logic_vector(1 downto 0);
selftestdone : out std_logic_vector(0 downto 0);
selftesterr : out std_logic_vector(0 downto 0);
errdata : out std_logic_vector(15 downto 0);
errctrl : out std_logic_vector(1 downto 0);
prbsdone : out std_logic_vector(0 downto 0);
prbserrlt : out std_logic_vector(0 downto 0);
signaldetectout : out std_logic_vector(0 downto 0);
aligndetsync : out std_logic_vector(1 downto 0);
rdalign : out std_logic_vector(1 downto 0);
bistdone : out std_logic_vector(0 downto 0);
runlengthviolation : out std_logic_vector(0 downto 0);
rlvlt : out std_logic_vector(0 downto 0);
rmfifopartialfull : out std_logic_vector(0 downto 0);
rmfifofull : out std_logic_vector(0 downto 0);
rmfifopartialempty : out std_logic_vector(0 downto 0);
rmfifoempty : out std_logic_vector(0 downto 0);
pcfifofull : out std_logic_vector(0 downto 0);
pcfifoempty : out std_logic_vector(0 downto 0);
a1a2k1k2flag : out std_logic_vector(3 downto 0);
byteordflag : out std_logic_vector(0 downto 0);
rxpipeclk : out std_logic_vector(0 downto 0);
channeltestbusout : out std_logic_vector(9 downto 0);
rxpipesoftreset : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
pipedata : out std_logic_vector(63 downto 0);
rxdatavalid : out std_logic_vector(3 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
speedchange : out std_logic_vector(0 downto 0);
eidledetected : out std_logic_vector(0 downto 0);
wordalignboundary : out std_logic_vector(4 downto 0);
rxclkslip : out std_logic_vector(0 downto 0);
eidleexit : out std_logic_vector(0 downto 0);
earlyeios : out std_logic_vector(0 downto 0);
ltr : out std_logic_vector(0 downto 0);
pcswrapbackin : in std_logic_vector(69 downto 0);
rxdivsyncinchnlup : in std_logic_vector(1 downto 0);
rxdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
rxweinchnlup : in std_logic_vector(1 downto 0);
rxweinchnldown : in std_logic_vector(1 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
configselinchnlup : in std_logic_vector(0 downto 0);
configselinchnldown : in std_logic_vector(0 downto 0);
speedchangeinchnlup : in std_logic_vector(0 downto 0);
speedchangeinchnldown : in std_logic_vector(0 downto 0);
pcieswitch : out std_logic_vector(0 downto 0);
rxdivsyncoutchnlup : out std_logic_vector(1 downto 0);
rxweoutchnlup : out std_logic_vector(1 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
resetpcptrsoutchnlup : out std_logic_vector(0 downto 0);
speedchangeoutchnlup : out std_logic_vector(0 downto 0);
configseloutchnlup : out std_logic_vector(0 downto 0);
rxdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rxweoutchnldown : out std_logic_vector(1 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsoutchnldown : out std_logic_vector(0 downto 0);
speedchangeoutchnldown : out std_logic_vector(0 downto 0);
configseloutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsinchnluppipe : out std_logic_vector(0 downto 0);
resetpcptrsinchnldownpipe : out std_logic_vector(0 downto 0);
speedchangeinchnluppipe : out std_logic_vector(0 downto 0);
speedchangeinchnldownpipe : out std_logic_vector(0 downto 0);
disablepcfifobyteserdes : out std_logic_vector(0 downto 0);
resetpcptrs : out std_logic_vector(0 downto 0);
rcvdclkagg : in std_logic_vector(0 downto 0);
rcvdclkaggtoporbot : in std_logic_vector(0 downto 0);
dispcbytegen3 : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txfifordclkraw : in std_logic_vector(0 downto 0);
resetpcptrsgen3 : in std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_rx_pcs;
architecture behavior of stratixv_hssi_8g_rx_pcs is
component stratixv_hssi_8g_rx_pcs_encrypted
generic (
prot_mode : string := "gige";
tx_rx_parallel_loopback : string := "dis_plpbk";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
polarity_inversion : string := "dis_pol_inv";
wa_pd : string := "wa_pd_10";
wa_pd_data : bit_vector := B"0000000000000000000000000000000000000000";
wa_boundary_lock_ctrl : string := "bit_slip";
wa_pld_controlled : string := "dis_pld_ctrl";
wa_sync_sm_ctrl : string := "gige_sync_sm";
wa_rknumber_data : bit_vector := B"00000000";
wa_renumber_data : bit_vector := B"000000";
wa_rgnumber_data : bit_vector := B"00000000";
wa_rosnumber_data : bit_vector := B"00";
wa_kchar : string := "dis_kchar";
wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm";
wa_clk_slip_spacing : string := "min_clk_slip_spacing";
wa_clk_slip_spacing_data : bit_vector := B"0000010000";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
deskew_pattern : bit_vector := B"1101101000";
deskew_prog_pattern_only : string := "en_deskew_prog_pat_only";
rate_match : string := "dis_rm";
eightb_tenb_decoder : string := "dis_8b10b";
err_flags_sel : string := "err_flags_wa";
polinv_8b10b_dec : string := "dis_polinv_8b10b_dec";
eightbtenb_decoder_output_sel : string := "data_8b10b_decoder";
invalid_code_flag_only : string := "dis_invalid_code_only";
auto_error_replacement : string := "dis_err_replace";
pad_or_edb_error_replace : string := "replace_edb";
byte_deserializer : string := "dis_bds";
byte_order : string := "dis_bo";
re_bo_on_wa : string := "dis_re_bo_on_wa";
bo_pattern : bit_vector := B"00000000000000000000";
bo_pad : bit_vector := B"0000000000";
phase_compensation_fifo : string := "low_latency";
prbs_ver : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_ver : string := "dis_bist";
cdr_ctrl : string := "dis_cdr_ctrl";
cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask";
wait_cnt : bit_vector := B"00000000";
mask_cnt : bit_vector := B"1111111111";
auto_deassert_pc_rst_cnt_data : bit_vector := B"00000";
auto_pc_en_cnt_data : bit_vector := B"0000000";
eidle_entry_sd : string := "dis_eidle_sd";
eidle_entry_eios : string := "dis_eidle_eios";
eidle_entry_iei : string := "dis_eidle_iei";
rx_rcvd_clk : string := "rcvd_clk_rcvd_clk";
rx_clk1 : string := "rcvd_clk_clk1";
rx_clk2 : string := "rcvd_clk_clk2";
rx_rd_clk : string := "pld_rx_clk";
dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo";
comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
agg_block_sel : string := "same_smrt_pack";
test_bus_sel : string := "test_bus_sel";
wa_rvnumber_data : bit_vector := B"0000000000000";
ctrl_plane_bonding_compensation : string := "dis_compensation";
clock_gate_rx : string := "dis_clk_gating";
prbs_ver_clr_flag : string := "dis_prbs_clr_flag";
hip_mode : string := "dis_hip";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
ctrl_plane_bonding_consumption : string := "individual";
pma_done_count : bit_vector := B"000000000000000000";
test_mode : string := "prbs";
bist_ver_clr_flag : string := "dis_bist_clr_flag";
wa_disp_err_flag : string := "dis_disp_err_flag";
wait_for_phfifo_cnt_data : bit_vector := B"000000";
runlength_check : string := "en_runlength_sw";
test_bus_sel_val : bit_vector := B"0000";
runlength_val : bit_vector := B"000000";
force_signal_detect : string := "en_force_signal_detect";
deskew : string := "dis_deskew";
rx_wr_clk : string := "rx_clk2_div_1_2_4";
rx_clk_free_running : string := "en_rx_clk_free_run";
rx_pcs_urst : string := "en_rx_pcs_urst";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
pipe_if_enable : string := "dis_pipe_rx";
pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
ibm_invalid_code : string := "dis_ibm_invalid_code";
channel_number : string := "int";
rx_refclk : string := "dis_refclk_sel"
);
port (
hrdrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
rmfifouserrst : in std_logic_vector(0 downto 0);
phfifouserrst : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
enablecommadetect : in std_logic_vector(0 downto 0);
a1a2size : in std_logic_vector(0 downto 0);
bitslip : in std_logic_vector(0 downto 0);
rmfiforeadenable : in std_logic_vector(0 downto 0);
rmfifowriteenable : in std_logic_vector(0 downto 0);
pldrxclk : in std_logic_vector(0 downto 0);
softresetrclk1 : out std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
bitreversalenable : in std_logic_vector(0 downto 0);
bytereversalenable : in std_logic_vector(0 downto 0);
rcvdclkpma : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(19 downto 0);
sigdetfrompma : in std_logic_vector(0 downto 0);
fiforstrdqd : in std_logic_vector(0 downto 0);
endskwqd : in std_logic_vector(0 downto 0);
endskwrdptrs : in std_logic_vector(0 downto 0);
alignstatus : in std_logic_vector(0 downto 0);
fiforstrdqdtoporbot : in std_logic_vector(0 downto 0);
endskwqdtoporbot : in std_logic_vector(0 downto 0);
endskwrdptrstoporbot : in std_logic_vector(0 downto 0);
alignstatustoporbot : in std_logic_vector(0 downto 0);
datafrinaggblock : in std_logic_vector(7 downto 0);
ctrlfromaggblock : in std_logic_vector(0 downto 0);
rxdatarstoporbot : in std_logic_vector(7 downto 0);
rxcontrolrstoporbot : in std_logic_vector(0 downto 0);
rcvdclk0pma : in std_logic_vector(0 downto 0);
parallelloopback : in std_logic_vector(19 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
byteorder : in std_logic_vector(0 downto 0);
pxfifowrdisable : in std_logic_vector(0 downto 0);
pcfifordenable : in std_logic_vector(0 downto 0);
pmatestbus : in std_logic_vector(7 downto 0);
encodertestbus : in std_logic_vector(9 downto 0);
txctrltestbus : in std_logic_vector(9 downto 0);
phystatusinternal : in std_logic_vector(0 downto 0);
rxvalidinternal : in std_logic_vector(0 downto 0);
rxstatusinternal : in std_logic_vector(2 downto 0);
phystatuspcsgen3 : in std_logic_vector(0 downto 0);
rxvalidpcsgen3 : in std_logic_vector(0 downto 0);
rxstatuspcsgen3 : in std_logic_vector(2 downto 0);
rxdatavalidpcsgen3 : in std_logic_vector(3 downto 0);
rxblkstartpcsgen3 : in std_logic_vector(3 downto 0);
rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0);
rxdatapcsgen3 : in std_logic_vector(63 downto 0);
pipepowerdown : in std_logic_vector(1 downto 0);
rateswitchcontrol : in std_logic_vector(0 downto 0);
gen2ngen1 : in std_logic_vector(0 downto 0);
gen2ngen1bundle : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
pipeloopbk : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
txdiv2syncoutpipeup : in std_logic_vector(0 downto 0);
fifoselectoutpipeup : in std_logic_vector(0 downto 0);
txwrenableoutpipeup : in std_logic_vector(0 downto 0);
txrdenableoutpipeup : in std_logic_vector(0 downto 0);
txdiv2syncoutpipedown : in std_logic_vector(0 downto 0);
fifoselectoutpipedown : in std_logic_vector(0 downto 0);
txwrenableoutpipedown : in std_logic_vector(0 downto 0);
txrdenableoutpipedown : in std_logic_vector(0 downto 0);
alignstatussync0 : in std_logic_vector(0 downto 0);
rmfifordincomp0 : in std_logic_vector(0 downto 0);
cgcomprddall : in std_logic_vector(0 downto 0);
cgcompwrall : in std_logic_vector(0 downto 0);
delcondmet0 : in std_logic_vector(0 downto 0);
fifoovr0 : in std_logic_vector(0 downto 0);
latencycomp0 : in std_logic_vector(0 downto 0);
insertincomplete0 : in std_logic_vector(0 downto 0);
alignstatussync0toporbot : in std_logic_vector(0 downto 0);
fifordincomp0toporbot : in std_logic_vector(0 downto 0);
cgcomprddalltoporbot : in std_logic_vector(0 downto 0);
cgcompwralltoporbot : in std_logic_vector(0 downto 0);
delcondmet0toporbot : in std_logic_vector(0 downto 0);
fifoovr0toporbot : in std_logic_vector(0 downto 0);
latencycomp0toporbot : in std_logic_vector(0 downto 0);
insertincomplete0toporbot : in std_logic_vector(0 downto 0);
alignstatussync : out std_logic_vector(0 downto 0);
fifordoutcomp : out std_logic_vector(0 downto 0);
cgcomprddout : out std_logic_vector(1 downto 0);
cgcompwrout : out std_logic_vector(1 downto 0);
delcondmetout : out std_logic_vector(0 downto 0);
fifoovrout : out std_logic_vector(0 downto 0);
latencycompout : out std_logic_vector(0 downto 0);
insertincompleteout : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(63 downto 0);
parallelrevloopback : out std_logic_vector(19 downto 0);
clocktopld : out std_logic_vector(0 downto 0);
bisterr : out std_logic_vector(0 downto 0);
clk2b : out std_logic_vector(0 downto 0);
rcvdclkpmab : out std_logic_vector(0 downto 0);
syncstatus : out std_logic_vector(0 downto 0);
decoderdatavalid : out std_logic_vector(0 downto 0);
decoderdata : out std_logic_vector(7 downto 0);
decoderctrl : out std_logic_vector(0 downto 0);
runningdisparity : out std_logic_vector(1 downto 0);
selftestdone : out std_logic_vector(0 downto 0);
selftesterr : out std_logic_vector(0 downto 0);
errdata : out std_logic_vector(15 downto 0);
errctrl : out std_logic_vector(1 downto 0);
prbsdone : out std_logic_vector(0 downto 0);
prbserrlt : out std_logic_vector(0 downto 0);
signaldetectout : out std_logic_vector(0 downto 0);
aligndetsync : out std_logic_vector(1 downto 0);
rdalign : out std_logic_vector(1 downto 0);
bistdone : out std_logic_vector(0 downto 0);
runlengthviolation : out std_logic_vector(0 downto 0);
rlvlt : out std_logic_vector(0 downto 0);
rmfifopartialfull : out std_logic_vector(0 downto 0);
rmfifofull : out std_logic_vector(0 downto 0);
rmfifopartialempty : out std_logic_vector(0 downto 0);
rmfifoempty : out std_logic_vector(0 downto 0);
pcfifofull : out std_logic_vector(0 downto 0);
pcfifoempty : out std_logic_vector(0 downto 0);
a1a2k1k2flag : out std_logic_vector(3 downto 0);
byteordflag : out std_logic_vector(0 downto 0);
rxpipeclk : out std_logic_vector(0 downto 0);
channeltestbusout : out std_logic_vector(9 downto 0);
rxpipesoftreset : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
pipedata : out std_logic_vector(63 downto 0);
rxdatavalid : out std_logic_vector(3 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
speedchange : out std_logic_vector(0 downto 0);
eidledetected : out std_logic_vector(0 downto 0);
wordalignboundary : out std_logic_vector(4 downto 0);
rxclkslip : out std_logic_vector(0 downto 0);
eidleexit : out std_logic_vector(0 downto 0);
earlyeios : out std_logic_vector(0 downto 0);
ltr : out std_logic_vector(0 downto 0);
pcswrapbackin : in std_logic_vector(69 downto 0);
rxdivsyncinchnlup : in std_logic_vector(1 downto 0);
rxdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
rxweinchnlup : in std_logic_vector(1 downto 0);
rxweinchnldown : in std_logic_vector(1 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
configselinchnlup : in std_logic_vector(0 downto 0);
configselinchnldown : in std_logic_vector(0 downto 0);
speedchangeinchnlup : in std_logic_vector(0 downto 0);
speedchangeinchnldown : in std_logic_vector(0 downto 0);
pcieswitch : out std_logic_vector(0 downto 0);
rxdivsyncoutchnlup : out std_logic_vector(1 downto 0);
rxweoutchnlup : out std_logic_vector(1 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
resetpcptrsoutchnlup : out std_logic_vector(0 downto 0);
speedchangeoutchnlup : out std_logic_vector(0 downto 0);
configseloutchnlup : out std_logic_vector(0 downto 0);
rxdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rxweoutchnldown : out std_logic_vector(1 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsoutchnldown : out std_logic_vector(0 downto 0);
speedchangeoutchnldown : out std_logic_vector(0 downto 0);
configseloutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsinchnluppipe : out std_logic_vector(0 downto 0);
resetpcptrsinchnldownpipe : out std_logic_vector(0 downto 0);
speedchangeinchnluppipe : out std_logic_vector(0 downto 0);
speedchangeinchnldownpipe : out std_logic_vector(0 downto 0);
disablepcfifobyteserdes : out std_logic_vector(0 downto 0);
resetpcptrs : out std_logic_vector(0 downto 0);
rcvdclkagg : in std_logic_vector(0 downto 0);
rcvdclkaggtoporbot : in std_logic_vector(0 downto 0);
dispcbytegen3 : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txfifordclkraw : in std_logic_vector(0 downto 0);
resetpcptrsgen3 : in std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_rx_pcs_encrypted
generic map (
prot_mode => prot_mode,
tx_rx_parallel_loopback => tx_rx_parallel_loopback,
pma_dw => pma_dw,
pcs_bypass => pcs_bypass,
polarity_inversion => polarity_inversion,
wa_pd => wa_pd,
wa_pd_data => wa_pd_data,
wa_boundary_lock_ctrl => wa_boundary_lock_ctrl,
wa_pld_controlled => wa_pld_controlled,
wa_sync_sm_ctrl => wa_sync_sm_ctrl,
wa_rknumber_data => wa_rknumber_data,
wa_renumber_data => wa_renumber_data,
wa_rgnumber_data => wa_rgnumber_data,
wa_rosnumber_data => wa_rosnumber_data,
wa_kchar => wa_kchar,
wa_det_latency_sync_status_beh => wa_det_latency_sync_status_beh,
wa_clk_slip_spacing => wa_clk_slip_spacing,
wa_clk_slip_spacing_data => wa_clk_slip_spacing_data,
bit_reversal => bit_reversal,
symbol_swap => symbol_swap,
deskew_pattern => deskew_pattern,
deskew_prog_pattern_only => deskew_prog_pattern_only,
rate_match => rate_match,
eightb_tenb_decoder => eightb_tenb_decoder,
err_flags_sel => err_flags_sel,
polinv_8b10b_dec => polinv_8b10b_dec,
eightbtenb_decoder_output_sel => eightbtenb_decoder_output_sel,
invalid_code_flag_only => invalid_code_flag_only,
auto_error_replacement => auto_error_replacement,
pad_or_edb_error_replace => pad_or_edb_error_replace,
byte_deserializer => byte_deserializer,
byte_order => byte_order,
re_bo_on_wa => re_bo_on_wa,
bo_pattern => bo_pattern,
bo_pad => bo_pad,
phase_compensation_fifo => phase_compensation_fifo,
prbs_ver => prbs_ver,
cid_pattern => cid_pattern,
cid_pattern_len => cid_pattern_len,
bist_ver => bist_ver,
cdr_ctrl => cdr_ctrl,
cdr_ctrl_rxvalid_mask => cdr_ctrl_rxvalid_mask,
wait_cnt => wait_cnt,
mask_cnt => mask_cnt,
auto_deassert_pc_rst_cnt_data => auto_deassert_pc_rst_cnt_data,
auto_pc_en_cnt_data => auto_pc_en_cnt_data,
eidle_entry_sd => eidle_entry_sd,
eidle_entry_eios => eidle_entry_eios,
eidle_entry_iei => eidle_entry_iei,
rx_rcvd_clk => rx_rcvd_clk,
rx_clk1 => rx_clk1,
rx_clk2 => rx_clk2,
rx_rd_clk => rx_rd_clk,
dw_one_or_two_symbol_bo => dw_one_or_two_symbol_bo,
comp_fifo_rst_pld_ctrl => comp_fifo_rst_pld_ctrl,
bypass_pipeline_reg => bypass_pipeline_reg,
agg_block_sel => agg_block_sel,
test_bus_sel => test_bus_sel,
wa_rvnumber_data => wa_rvnumber_data,
ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation,
clock_gate_rx => clock_gate_rx,
prbs_ver_clr_flag => prbs_ver_clr_flag,
hip_mode => hip_mode,
ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
pma_done_count => pma_done_count,
test_mode => test_mode,
bist_ver_clr_flag => bist_ver_clr_flag,
wa_disp_err_flag => wa_disp_err_flag,
wait_for_phfifo_cnt_data => wait_for_phfifo_cnt_data,
runlength_check => runlength_check,
test_bus_sel_val => test_bus_sel_val,
runlength_val => runlength_val,
force_signal_detect => force_signal_detect,
deskew => deskew,
rx_wr_clk => rx_wr_clk,
rx_clk_free_running => rx_clk_free_running,
rx_pcs_urst => rx_pcs_urst,
self_switch_dw_scaling => self_switch_dw_scaling,
pipe_if_enable => pipe_if_enable,
pc_fifo_rst_pld_ctrl => pc_fifo_rst_pld_ctrl,
auto_speed_nego_gen2 => auto_speed_nego_gen2,
auto_speed_nego_gen3 => auto_speed_nego_gen3,
ibm_invalid_code => ibm_invalid_code,
channel_number => channel_number,
rx_refclk => rx_refclk
)
port map (
hrdrst => hrdrst,
rxpcsrst => rxpcsrst,
rmfifouserrst => rmfifouserrst,
phfifouserrst => phfifouserrst,
scanmode => scanmode,
enablecommadetect => enablecommadetect,
a1a2size => a1a2size,
bitslip => bitslip,
rmfiforeadenable => rmfiforeadenable,
rmfifowriteenable => rmfifowriteenable,
pldrxclk => pldrxclk,
softresetrclk1 => softresetrclk1,
polinvrx => polinvrx,
bitreversalenable => bitreversalenable,
bytereversalenable => bytereversalenable,
rcvdclkpma => rcvdclkpma,
datain => datain,
sigdetfrompma => sigdetfrompma,
fiforstrdqd => fiforstrdqd,
endskwqd => endskwqd,
endskwrdptrs => endskwrdptrs,
alignstatus => alignstatus,
fiforstrdqdtoporbot => fiforstrdqdtoporbot,
endskwqdtoporbot => endskwqdtoporbot,
endskwrdptrstoporbot => endskwrdptrstoporbot,
alignstatustoporbot => alignstatustoporbot,
datafrinaggblock => datafrinaggblock,
ctrlfromaggblock => ctrlfromaggblock,
rxdatarstoporbot => rxdatarstoporbot,
rxcontrolrstoporbot => rxcontrolrstoporbot,
rcvdclk0pma => rcvdclk0pma,
parallelloopback => parallelloopback,
txpmaclk => txpmaclk,
byteorder => byteorder,
pxfifowrdisable => pxfifowrdisable,
pcfifordenable => pcfifordenable,
pmatestbus => pmatestbus,
encodertestbus => encodertestbus,
txctrltestbus => txctrltestbus,
phystatusinternal => phystatusinternal,
rxvalidinternal => rxvalidinternal,
rxstatusinternal => rxstatusinternal,
phystatuspcsgen3 => phystatuspcsgen3,
rxvalidpcsgen3 => rxvalidpcsgen3,
rxstatuspcsgen3 => rxstatuspcsgen3,
rxdatavalidpcsgen3 => rxdatavalidpcsgen3,
rxblkstartpcsgen3 => rxblkstartpcsgen3,
rxsynchdrpcsgen3 => rxsynchdrpcsgen3,
rxdatapcsgen3 => rxdatapcsgen3,
pipepowerdown => pipepowerdown,
rateswitchcontrol => rateswitchcontrol,
gen2ngen1 => gen2ngen1,
gen2ngen1bundle => gen2ngen1bundle,
eidleinfersel => eidleinfersel,
pipeloopbk => pipeloopbk,
pldltr => pldltr,
prbscidenable => prbscidenable,
txdiv2syncoutpipeup => txdiv2syncoutpipeup,
fifoselectoutpipeup => fifoselectoutpipeup,
txwrenableoutpipeup => txwrenableoutpipeup,
txrdenableoutpipeup => txrdenableoutpipeup,
txdiv2syncoutpipedown => txdiv2syncoutpipedown,
fifoselectoutpipedown => fifoselectoutpipedown,
txwrenableoutpipedown => txwrenableoutpipedown,
txrdenableoutpipedown => txrdenableoutpipedown,
alignstatussync0 => alignstatussync0,
rmfifordincomp0 => rmfifordincomp0,
cgcomprddall => cgcomprddall,
cgcompwrall => cgcompwrall,
delcondmet0 => delcondmet0,
fifoovr0 => fifoovr0,
latencycomp0 => latencycomp0,
insertincomplete0 => insertincomplete0,
alignstatussync0toporbot => alignstatussync0toporbot,
fifordincomp0toporbot => fifordincomp0toporbot,
cgcomprddalltoporbot => cgcomprddalltoporbot,
cgcompwralltoporbot => cgcompwralltoporbot,
delcondmet0toporbot => delcondmet0toporbot,
fifoovr0toporbot => fifoovr0toporbot,
latencycomp0toporbot => latencycomp0toporbot,
insertincomplete0toporbot => insertincomplete0toporbot,
alignstatussync => alignstatussync,
fifordoutcomp => fifordoutcomp,
cgcomprddout => cgcomprddout,
cgcompwrout => cgcompwrout,
delcondmetout => delcondmetout,
fifoovrout => fifoovrout,
latencycompout => latencycompout,
insertincompleteout => insertincompleteout,
dataout => dataout,
parallelrevloopback => parallelrevloopback,
clocktopld => clocktopld,
bisterr => bisterr,
clk2b => clk2b,
rcvdclkpmab => rcvdclkpmab,
syncstatus => syncstatus,
decoderdatavalid => decoderdatavalid,
decoderdata => decoderdata,
decoderctrl => decoderctrl,
runningdisparity => runningdisparity,
selftestdone => selftestdone,
selftesterr => selftesterr,
errdata => errdata,
errctrl => errctrl,
prbsdone => prbsdone,
prbserrlt => prbserrlt,
signaldetectout => signaldetectout,
aligndetsync => aligndetsync,
rdalign => rdalign,
bistdone => bistdone,
runlengthviolation => runlengthviolation,
rlvlt => rlvlt,
rmfifopartialfull => rmfifopartialfull,
rmfifofull => rmfifofull,
rmfifopartialempty => rmfifopartialempty,
rmfifoempty => rmfifoempty,
pcfifofull => pcfifofull,
pcfifoempty => pcfifoempty,
a1a2k1k2flag => a1a2k1k2flag,
byteordflag => byteordflag,
rxpipeclk => rxpipeclk,
channeltestbusout => channeltestbusout,
rxpipesoftreset => rxpipesoftreset,
phystatus => phystatus,
rxvalid => rxvalid,
rxstatus => rxstatus,
pipedata => pipedata,
rxdatavalid => rxdatavalid,
rxblkstart => rxblkstart,
rxsynchdr => rxsynchdr,
speedchange => speedchange,
eidledetected => eidledetected,
wordalignboundary => wordalignboundary,
rxclkslip => rxclkslip,
eidleexit => eidleexit,
earlyeios => earlyeios,
ltr => ltr,
pcswrapbackin => pcswrapbackin,
rxdivsyncinchnlup => rxdivsyncinchnlup,
rxdivsyncinchnldown => rxdivsyncinchnldown,
wrenableinchnlup => wrenableinchnlup,
wrenableinchnldown => wrenableinchnldown,
rdenableinchnlup => rdenableinchnlup,
rdenableinchnldown => rdenableinchnldown,
rxweinchnlup => rxweinchnlup,
rxweinchnldown => rxweinchnldown,
resetpcptrsinchnlup => resetpcptrsinchnlup,
resetpcptrsinchnldown => resetpcptrsinchnldown,
configselinchnlup => configselinchnlup,
configselinchnldown => configselinchnldown,
speedchangeinchnlup => speedchangeinchnlup,
speedchangeinchnldown => speedchangeinchnldown,
pcieswitch => pcieswitch,
rxdivsyncoutchnlup => rxdivsyncoutchnlup,
rxweoutchnlup => rxweoutchnlup,
wrenableoutchnlup => wrenableoutchnlup,
rdenableoutchnlup => rdenableoutchnlup,
resetpcptrsoutchnlup => resetpcptrsoutchnlup,
speedchangeoutchnlup => speedchangeoutchnlup,
configseloutchnlup => configseloutchnlup,
rxdivsyncoutchnldown => rxdivsyncoutchnldown,
rxweoutchnldown => rxweoutchnldown,
wrenableoutchnldown => wrenableoutchnldown,
rdenableoutchnldown => rdenableoutchnldown,
resetpcptrsoutchnldown => resetpcptrsoutchnldown,
speedchangeoutchnldown => speedchangeoutchnldown,
configseloutchnldown => configseloutchnldown,
resetpcptrsinchnluppipe => resetpcptrsinchnluppipe,
resetpcptrsinchnldownpipe => resetpcptrsinchnldownpipe,
speedchangeinchnluppipe => speedchangeinchnluppipe,
speedchangeinchnldownpipe => speedchangeinchnldownpipe,
disablepcfifobyteserdes => disablepcfifobyteserdes,
resetpcptrs => resetpcptrs,
rcvdclkagg => rcvdclkagg,
rcvdclkaggtoporbot => rcvdclkaggtoporbot,
dispcbytegen3 => dispcbytegen3,
refclkdig => refclkdig,
txfifordclkraw => txfifordclkraw,
resetpcptrsgen3 => resetpcptrsgen3,
syncdatain => syncdatain,
observablebyteserdesclock => observablebyteserdesclock
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_tx_pcs is
generic (
prot_mode : string := "basic";
hip_mode : string := "dis_hip";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
phase_compensation_fifo : string := "low_latency";
tx_compliance_controlled_disparity : string := "dis_txcompliance";
force_kchar : string := "dis_force_kchar";
force_echar : string := "dis_force_echar";
byte_serializer : string := "dis_bs";
data_selection_8b10b_encoder_input : string := "normal_data_path";
eightb_tenb_disp_ctrl : string := "dis_disp_ctrl";
eightb_tenb_encoder : string := "dis_8b10b";
prbs_gen : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_gen : string := "dis_bist";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
polarity_inversion : string := "dis_polinv";
tx_bitslip : string := "dis_tx_bitslip";
agg_block_sel : string := "same_smrt_pack";
revloop_back_rm : string := "dis_rev_loopback_rx_rm";
phfifo_write_clk_sel : string := "pld_tx_clk";
ctrl_plane_bonding_consumption : string := "individual";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
test_mode : string := "prbs";
clock_gate_tx : string := "dis_clk_gating";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
ctrl_plane_bonding_compensation : string := "dis_compensation";
refclk_b_clk_sel : string := "tx_pma_clock";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
channel_number : string := "int"
);
port (
txpcsreset : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(43 downto 0);
coreclk : in std_logic_vector(0 downto 0);
invpol : in std_logic_vector(0 downto 0);
xgmdatain : in std_logic_vector(7 downto 0);
xgmctrl : in std_logic_vector(0 downto 0);
xgmdataintoporbottom : in std_logic_vector(7 downto 0);
xgmctrltoporbottom : in std_logic_vector(0 downto 0);
txpmalocalclk : in std_logic_vector(0 downto 0);
enrevparallellpbk : in std_logic_vector(0 downto 0);
revparallellpbkdata : in std_logic_vector(19 downto 0);
phfifowrenable : in std_logic_vector(0 downto 0);
phfiforddisable : in std_logic_vector(0 downto 0);
phfiforeset : in std_logic_vector(0 downto 0);
detectrxloopin : in std_logic_vector(0 downto 0);
powerdn : in std_logic_vector(1 downto 0);
pipeenrevparallellpbkin : in std_logic_vector(0 downto 0);
pipetxswing : in std_logic_vector(0 downto 0);
pipetxdeemph : in std_logic_vector(0 downto 0);
pipetxmargin : in std_logic_vector(2 downto 0);
rxpolarityin : in std_logic_vector(0 downto 0);
polinvrxin : in std_logic_vector(0 downto 0);
elecidleinfersel : in std_logic_vector(2 downto 0);
rateswitch : in std_logic_vector(0 downto 0);
rateswitchbundle : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
bitslipboundaryselect : in std_logic_vector(4 downto 0);
phfifooverflow : out std_logic_vector(0 downto 0);
phfifounderflow : out std_logic_vector(0 downto 0);
clkout : out std_logic_vector(0 downto 0);
clkoutgen3 : out std_logic_vector(0 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(19 downto 0);
rdenablesync : out std_logic_vector(0 downto 0);
refclkb : out std_logic_vector(0 downto 0);
parallelfdbkout : out std_logic_vector(19 downto 0);
txpipeclk : out std_logic_vector(0 downto 0);
encodertestbus : out std_logic_vector(9 downto 0);
txctrltestbus : out std_logic_vector(9 downto 0);
txpipesoftreset : out std_logic_vector(0 downto 0);
txpipeelectidle : out std_logic_vector(0 downto 0);
detectrxloopout : out std_logic_vector(0 downto 0);
pipepowerdownout : out std_logic_vector(1 downto 0);
pipeenrevparallellpbkout : out std_logic_vector(0 downto 0);
phfifotxswing : out std_logic_vector(0 downto 0);
phfifotxdeemph : out std_logic_vector(0 downto 0);
phfifotxmargin : out std_logic_vector(2 downto 0);
txdataouttogen3 : out std_logic_vector(31 downto 0);
txdatakouttogen3 : out std_logic_vector(3 downto 0);
txdatavalidouttogen3 : out std_logic_vector(3 downto 0);
txblkstartout : out std_logic_vector(3 downto 0);
txsynchdrout : out std_logic_vector(1 downto 0);
txcomplianceout : out std_logic_vector(0 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
rxpolarityout : out std_logic_vector(0 downto 0);
polinvrxout : out std_logic_vector(0 downto 0);
grayelecidleinferselout : out std_logic_vector(2 downto 0);
txdivsyncinchnlup : in std_logic_vector(1 downto 0);
txdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
fifoselectinchnlup : in std_logic_vector(1 downto 0);
fifoselectinchnldown : in std_logic_vector(1 downto 0);
resetpcptrs : in std_logic_vector(0 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
dispcbyte : in std_logic_vector(0 downto 0);
txdivsyncoutchnlup : out std_logic_vector(1 downto 0);
txdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
fifoselectoutchnlup : out std_logic_vector(1 downto 0);
fifoselectoutchnldown : out std_logic_vector(1 downto 0);
txfifordclkraw : out std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_tx_pcs;
architecture behavior of stratixv_hssi_8g_tx_pcs is
component stratixv_hssi_8g_tx_pcs_encrypted
generic (
prot_mode : string := "basic";
hip_mode : string := "dis_hip";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
phase_compensation_fifo : string := "low_latency";
tx_compliance_controlled_disparity : string := "dis_txcompliance";
force_kchar : string := "dis_force_kchar";
force_echar : string := "dis_force_echar";
byte_serializer : string := "dis_bs";
data_selection_8b10b_encoder_input : string := "normal_data_path";
eightb_tenb_disp_ctrl : string := "dis_disp_ctrl";
eightb_tenb_encoder : string := "dis_8b10b";
prbs_gen : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_gen : string := "dis_bist";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
polarity_inversion : string := "dis_polinv";
tx_bitslip : string := "dis_tx_bitslip";
agg_block_sel : string := "same_smrt_pack";
revloop_back_rm : string := "dis_rev_loopback_rx_rm";
phfifo_write_clk_sel : string := "pld_tx_clk";
ctrl_plane_bonding_consumption : string := "individual";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
test_mode : string := "prbs";
clock_gate_tx : string := "dis_clk_gating";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
ctrl_plane_bonding_compensation : string := "dis_compensation";
refclk_b_clk_sel : string := "tx_pma_clock";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
channel_number : string := "int"
);
port (
txpcsreset : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(43 downto 0);
coreclk : in std_logic_vector(0 downto 0);
invpol : in std_logic_vector(0 downto 0);
xgmdatain : in std_logic_vector(7 downto 0);
xgmctrl : in std_logic_vector(0 downto 0);
xgmdataintoporbottom : in std_logic_vector(7 downto 0);
xgmctrltoporbottom : in std_logic_vector(0 downto 0);
txpmalocalclk : in std_logic_vector(0 downto 0);
enrevparallellpbk : in std_logic_vector(0 downto 0);
revparallellpbkdata : in std_logic_vector(19 downto 0);
phfifowrenable : in std_logic_vector(0 downto 0);
phfiforddisable : in std_logic_vector(0 downto 0);
phfiforeset : in std_logic_vector(0 downto 0);
detectrxloopin : in std_logic_vector(0 downto 0);
powerdn : in std_logic_vector(1 downto 0);
pipeenrevparallellpbkin : in std_logic_vector(0 downto 0);
pipetxswing : in std_logic_vector(0 downto 0);
pipetxdeemph : in std_logic_vector(0 downto 0);
pipetxmargin : in std_logic_vector(2 downto 0);
rxpolarityin : in std_logic_vector(0 downto 0);
polinvrxin : in std_logic_vector(0 downto 0);
elecidleinfersel : in std_logic_vector(2 downto 0);
rateswitch : in std_logic_vector(0 downto 0);
rateswitchbundle : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
bitslipboundaryselect : in std_logic_vector(4 downto 0);
phfifooverflow : out std_logic_vector(0 downto 0);
phfifounderflow : out std_logic_vector(0 downto 0);
clkout : out std_logic_vector(0 downto 0);
clkoutgen3 : out std_logic_vector(0 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(19 downto 0);
rdenablesync : out std_logic_vector(0 downto 0);
refclkb : out std_logic_vector(0 downto 0);
parallelfdbkout : out std_logic_vector(19 downto 0);
txpipeclk : out std_logic_vector(0 downto 0);
encodertestbus : out std_logic_vector(9 downto 0);
txctrltestbus : out std_logic_vector(9 downto 0);
txpipesoftreset : out std_logic_vector(0 downto 0);
txpipeelectidle : out std_logic_vector(0 downto 0);
detectrxloopout : out std_logic_vector(0 downto 0);
pipepowerdownout : out std_logic_vector(1 downto 0);
pipeenrevparallellpbkout : out std_logic_vector(0 downto 0);
phfifotxswing : out std_logic_vector(0 downto 0);
phfifotxdeemph : out std_logic_vector(0 downto 0);
phfifotxmargin : out std_logic_vector(2 downto 0);
txdataouttogen3 : out std_logic_vector(31 downto 0);
txdatakouttogen3 : out std_logic_vector(3 downto 0);
txdatavalidouttogen3 : out std_logic_vector(3 downto 0);
txblkstartout : out std_logic_vector(3 downto 0);
txsynchdrout : out std_logic_vector(1 downto 0);
txcomplianceout : out std_logic_vector(0 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
rxpolarityout : out std_logic_vector(0 downto 0);
polinvrxout : out std_logic_vector(0 downto 0);
grayelecidleinferselout : out std_logic_vector(2 downto 0);
txdivsyncinchnlup : in std_logic_vector(1 downto 0);
txdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
fifoselectinchnlup : in std_logic_vector(1 downto 0);
fifoselectinchnldown : in std_logic_vector(1 downto 0);
resetpcptrs : in std_logic_vector(0 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
dispcbyte : in std_logic_vector(0 downto 0);
txdivsyncoutchnlup : out std_logic_vector(1 downto 0);
txdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
fifoselectoutchnlup : out std_logic_vector(1 downto 0);
fifoselectoutchnldown : out std_logic_vector(1 downto 0);
txfifordclkraw : out std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_tx_pcs_encrypted
generic map (
prot_mode => prot_mode,
hip_mode => hip_mode,
pma_dw => pma_dw,
pcs_bypass => pcs_bypass,
phase_compensation_fifo => phase_compensation_fifo,
tx_compliance_controlled_disparity => tx_compliance_controlled_disparity,
force_kchar => force_kchar,
force_echar => force_echar,
byte_serializer => byte_serializer,
data_selection_8b10b_encoder_input => data_selection_8b10b_encoder_input,
eightb_tenb_disp_ctrl => eightb_tenb_disp_ctrl,
eightb_tenb_encoder => eightb_tenb_encoder,
prbs_gen => prbs_gen,
cid_pattern => cid_pattern,
cid_pattern_len => cid_pattern_len,
bist_gen => bist_gen,
bit_reversal => bit_reversal,
symbol_swap => symbol_swap,
polarity_inversion => polarity_inversion,
tx_bitslip => tx_bitslip,
agg_block_sel => agg_block_sel,
revloop_back_rm => revloop_back_rm,
phfifo_write_clk_sel => phfifo_write_clk_sel,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
bypass_pipeline_reg => bypass_pipeline_reg,
ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution,
test_mode => test_mode,
clock_gate_tx => clock_gate_tx,
self_switch_dw_scaling => self_switch_dw_scaling,
ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation,
refclk_b_clk_sel => refclk_b_clk_sel,
auto_speed_nego_gen2 => auto_speed_nego_gen2,
auto_speed_nego_gen3 => auto_speed_nego_gen3,
channel_number => channel_number
)
port map (
txpcsreset => txpcsreset,
refclkdig => refclkdig,
scanmode => scanmode,
datain => datain,
coreclk => coreclk,
invpol => invpol,
xgmdatain => xgmdatain,
xgmctrl => xgmctrl,
xgmdataintoporbottom => xgmdataintoporbottom,
xgmctrltoporbottom => xgmctrltoporbottom,
txpmalocalclk => txpmalocalclk,
enrevparallellpbk => enrevparallellpbk,
revparallellpbkdata => revparallellpbkdata,
phfifowrenable => phfifowrenable,
phfiforddisable => phfiforddisable,
phfiforeset => phfiforeset,
detectrxloopin => detectrxloopin,
powerdn => powerdn,
pipeenrevparallellpbkin => pipeenrevparallellpbkin,
pipetxswing => pipetxswing,
pipetxdeemph => pipetxdeemph,
pipetxmargin => pipetxmargin,
rxpolarityin => rxpolarityin,
polinvrxin => polinvrxin,
elecidleinfersel => elecidleinfersel,
rateswitch => rateswitch,
rateswitchbundle => rateswitchbundle,
prbscidenable => prbscidenable,
bitslipboundaryselect => bitslipboundaryselect,
phfifooverflow => phfifooverflow,
phfifounderflow => phfifounderflow,
clkout => clkout,
clkoutgen3 => clkoutgen3,
xgmdataout => xgmdataout,
xgmctrlenable => xgmctrlenable,
dataout => dataout,
rdenablesync => rdenablesync,
refclkb => refclkb,
parallelfdbkout => parallelfdbkout,
txpipeclk => txpipeclk,
encodertestbus => encodertestbus,
txctrltestbus => txctrltestbus,
txpipesoftreset => txpipesoftreset,
txpipeelectidle => txpipeelectidle,
detectrxloopout => detectrxloopout,
pipepowerdownout => pipepowerdownout,
pipeenrevparallellpbkout => pipeenrevparallellpbkout,
phfifotxswing => phfifotxswing,
phfifotxdeemph => phfifotxdeemph,
phfifotxmargin => phfifotxmargin,
txdataouttogen3 => txdataouttogen3,
txdatakouttogen3 => txdatakouttogen3,
txdatavalidouttogen3 => txdatavalidouttogen3,
txblkstartout => txblkstartout,
txsynchdrout => txsynchdrout,
txcomplianceout => txcomplianceout,
txelecidleout => txelecidleout,
rxpolarityout => rxpolarityout,
polinvrxout => polinvrxout,
grayelecidleinferselout => grayelecidleinferselout,
txdivsyncinchnlup => txdivsyncinchnlup,
txdivsyncinchnldown => txdivsyncinchnldown,
wrenableinchnlup => wrenableinchnlup,
wrenableinchnldown => wrenableinchnldown,
rdenableinchnlup => rdenableinchnlup,
rdenableinchnldown => rdenableinchnldown,
fifoselectinchnlup => fifoselectinchnlup,
fifoselectinchnldown => fifoselectinchnldown,
resetpcptrs => resetpcptrs,
resetpcptrsinchnlup => resetpcptrsinchnlup,
resetpcptrsinchnldown => resetpcptrsinchnldown,
dispcbyte => dispcbyte,
txdivsyncoutchnlup => txdivsyncoutchnlup,
txdivsyncoutchnldown => txdivsyncoutchnldown,
rdenableoutchnlup => rdenableoutchnlup,
rdenableoutchnldown => rdenableoutchnldown,
wrenableoutchnlup => wrenableoutchnlup,
wrenableoutchnldown => wrenableoutchnldown,
fifoselectoutchnlup => fifoselectoutchnlup,
fifoselectoutchnldown => fifoselectoutchnldown,
txfifordclkraw => txfifordclkraw,
syncdatain => syncdatain,
observablebyteserdesclock => observablebyteserdesclock
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pipe_gen1_2 is
generic (
prot_mode : string := "pipe_g1";
hip_mode : string := "dis_hip";
tx_pipe_enable : string := "dis_pipe_tx";
rx_pipe_enable : string := "dis_pipe_rx";
pipe_byte_de_serializer_en : string := "dont_care_bds";
txswing : string := "dis_txswing";
rxdetect_bypass : string := "dis_rxdetect_bypass";
error_replace_pad : string := "replace_edb";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle : string := "dis_phystatus_rst_toggle";
elecidle_delay : string := "elec_idle_delay";
elec_idle_delay_val : bit_vector := B"000";
phy_status_delay : string := "phystatus_delay";
phystatus_delay_val : bit_vector := B"000";
ctrl_plane_bonding_consumption : string := "individual";
byte_deserializer : string := "dis_bds"
);
port (
pipetxclk : in std_logic_vector(0 downto 0);
piperxclk : in std_logic_vector(0 downto 0);
refclkb : in std_logic_vector(0 downto 0);
txpipereset : in std_logic_vector(0 downto 0);
rxpipereset : in std_logic_vector(0 downto 0);
refclkbreset : in std_logic_vector(0 downto 0);
rrdwidthrx : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txelecidlein : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txswingport : in std_logic_vector(0 downto 0);
txdch : in std_logic_vector(43 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
sigdetni : in std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdch : out std_logic_vector(63 downto 0);
phystatus : out std_logic_vector(0 downto 0);
revloopback : in std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
txd : out std_logic_vector(43 downto 0);
revloopbk : out std_logic_vector(0 downto 0);
revloopbkpcsgen3 : in std_logic_vector(0 downto 0);
rxelectricalidlepcsgen3 : in std_logic_vector(0 downto 0);
txelecidlecomp : in std_logic_vector(0 downto 0);
rindvrx : in std_logic_vector(0 downto 0);
rmasterrx : in std_logic_vector(1 downto 0);
speedchange : in std_logic_vector(0 downto 0);
speedchangechnlup : in std_logic_vector(0 downto 0);
speedchangechnldown : in std_logic_vector(0 downto 0);
rxd : in std_logic_vector(63 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
txdetectrx : out std_logic_vector(0 downto 0);
powerstate : out std_logic_vector(3 downto 0);
rxfound : in std_logic_vector(0 downto 0);
rxdetectvalid : in std_logic_vector(0 downto 0);
rxelectricalidle : in std_logic_vector(0 downto 0);
powerstatetransitiondone : in std_logic_vector(0 downto 0);
powerstatetransitiondoneena : in std_logic_vector(0 downto 0);
txdeemphint : out std_logic_vector(0 downto 0);
txmarginint : out std_logic_vector(2 downto 0);
txswingint : out std_logic_vector(0 downto 0);
rxelectricalidleout : out std_logic_vector(0 downto 0);
rxpolaritypcsgen3 : in std_logic_vector(0 downto 0);
polinvrxint : out std_logic_vector(0 downto 0);
speedchangeout : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_pipe_gen1_2;
architecture behavior of stratixv_hssi_pipe_gen1_2 is
component stratixv_hssi_pipe_gen1_2_encrypted
generic (
prot_mode : string := "pipe_g1";
hip_mode : string := "dis_hip";
tx_pipe_enable : string := "dis_pipe_tx";
rx_pipe_enable : string := "dis_pipe_rx";
pipe_byte_de_serializer_en : string := "dont_care_bds";
txswing : string := "dis_txswing";
rxdetect_bypass : string := "dis_rxdetect_bypass";
error_replace_pad : string := "replace_edb";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle : string := "dis_phystatus_rst_toggle";
elecidle_delay : string := "elec_idle_delay";
elec_idle_delay_val : bit_vector := B"000";
phy_status_delay : string := "phystatus_delay";
phystatus_delay_val : bit_vector := B"000";
ctrl_plane_bonding_consumption : string := "individual";
byte_deserializer : string := "dis_bds"
);
port (
pipetxclk : in std_logic_vector(0 downto 0);
piperxclk : in std_logic_vector(0 downto 0);
refclkb : in std_logic_vector(0 downto 0);
txpipereset : in std_logic_vector(0 downto 0);
rxpipereset : in std_logic_vector(0 downto 0);
refclkbreset : in std_logic_vector(0 downto 0);
rrdwidthrx : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txelecidlein : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txswingport : in std_logic_vector(0 downto 0);
txdch : in std_logic_vector(43 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
sigdetni : in std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdch : out std_logic_vector(63 downto 0);
phystatus : out std_logic_vector(0 downto 0);
revloopback : in std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
txd : out std_logic_vector(43 downto 0);
revloopbk : out std_logic_vector(0 downto 0);
revloopbkpcsgen3 : in std_logic_vector(0 downto 0);
rxelectricalidlepcsgen3 : in std_logic_vector(0 downto 0);
txelecidlecomp : in std_logic_vector(0 downto 0);
rindvrx : in std_logic_vector(0 downto 0);
rmasterrx : in std_logic_vector(1 downto 0);
speedchange : in std_logic_vector(0 downto 0);
speedchangechnlup : in std_logic_vector(0 downto 0);
speedchangechnldown : in std_logic_vector(0 downto 0);
rxd : in std_logic_vector(63 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
txdetectrx : out std_logic_vector(0 downto 0);
powerstate : out std_logic_vector(3 downto 0);
rxfound : in std_logic_vector(0 downto 0);
rxdetectvalid : in std_logic_vector(0 downto 0);
rxelectricalidle : in std_logic_vector(0 downto 0);
powerstatetransitiondone : in std_logic_vector(0 downto 0);
powerstatetransitiondoneena : in std_logic_vector(0 downto 0);
txdeemphint : out std_logic_vector(0 downto 0);
txmarginint : out std_logic_vector(2 downto 0);
txswingint : out std_logic_vector(0 downto 0);
rxelectricalidleout : out std_logic_vector(0 downto 0);
rxpolaritypcsgen3 : in std_logic_vector(0 downto 0);
polinvrxint : out std_logic_vector(0 downto 0);
speedchangeout : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_pipe_gen1_2_encrypted
generic map (
prot_mode => prot_mode,
hip_mode => hip_mode,
tx_pipe_enable => tx_pipe_enable,
rx_pipe_enable => rx_pipe_enable,
pipe_byte_de_serializer_en => pipe_byte_de_serializer_en,
txswing => txswing,
rxdetect_bypass => rxdetect_bypass,
error_replace_pad => error_replace_pad,
ind_error_reporting => ind_error_reporting,
phystatus_rst_toggle => phystatus_rst_toggle,
elecidle_delay => elecidle_delay,
elec_idle_delay_val => elec_idle_delay_val,
phy_status_delay => phy_status_delay,
phystatus_delay_val => phystatus_delay_val,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
byte_deserializer => byte_deserializer
)
port map (
pipetxclk => pipetxclk,
piperxclk => piperxclk,
refclkb => refclkb,
txpipereset => txpipereset,
rxpipereset => rxpipereset,
refclkbreset => refclkbreset,
rrdwidthrx => rrdwidthrx,
txdetectrxloopback => txdetectrxloopback,
txelecidlein => txelecidlein,
powerdown => powerdown,
txdeemph => txdeemph,
txmargin => txmargin,
txswingport => txswingport,
txdch => txdch,
rxpolarity => rxpolarity,
sigdetni => sigdetni,
rxvalid => rxvalid,
rxelecidle => rxelecidle,
rxstatus => rxstatus,
rxdch => rxdch,
phystatus => phystatus,
revloopback => revloopback,
polinvrx => polinvrx,
txd => txd,
revloopbk => revloopbk,
revloopbkpcsgen3 => revloopbkpcsgen3,
rxelectricalidlepcsgen3 => rxelectricalidlepcsgen3,
txelecidlecomp => txelecidlecomp,
rindvrx => rindvrx,
rmasterrx => rmasterrx,
speedchange => speedchange,
speedchangechnlup => speedchangechnlup,
speedchangechnldown => speedchangechnldown,
rxd => rxd,
txelecidleout => txelecidleout,
txdetectrx => txdetectrx,
powerstate => powerstate,
rxfound => rxfound,
rxdetectvalid => rxdetectvalid,
rxelectricalidle => rxelectricalidle,
powerstatetransitiondone => powerstatetransitiondone,
powerstatetransitiondoneena => powerstatetransitiondoneena,
txdeemphint => txdeemphint,
txmarginint => txmarginint,
txswingint => txswingint,
rxelectricalidleout => rxelectricalidleout,
rxpolaritypcsgen3 => rxpolaritypcsgen3,
polinvrxint => polinvrxint,
speedchangeout => speedchangeout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pipe_gen3 is
generic (
mode : string := "pipe_g1";
ctrl_plane_bonding : string := "individual";
pipe_clk_sel : string := "func_clk";
rate_match_pad_insertion : string := "dis_rm_fifo_pad_ins";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle_g3 : string := "dis_phystatus_rst_toggle_g3";
phystatus_rst_toggle_g12 : string := "dis_phystatus_rst_toggle";
cdr_control : string := "en_cdr_ctrl";
cid_enable : string := "en_cid_mode";
parity_chk_ts1 : string := "en_ts1_parity_chk";
rxvalid_mask : string := "rxvalid_mask_en";
ph_fifo_reg_mode : string := "phfifo_reg_mode_dis";
test_mode_timers : string := "dis_test_mode_timers";
inf_ei_enable : string := "dis_inf_ei";
spd_chnge_g2_sel : string := "false";
cp_up_mstr : string := "false";
cp_dwn_mstr : string := "false";
cp_cons_sel : string := "cp_cons_default";
elecidle_delay_g12_data : bit_vector := B"000";
elecidle_delay_g12 : string := "elecidle_delay_g12";
elecidle_delay_g3_data : bit_vector := B"000";
elecidle_delay_g3 : string := "elecidle_delay_g3";
phy_status_delay_g12_data : bit_vector := B"000";
phy_status_delay_g12 : string := "phy_status_delay_g12";
phy_status_delay_g3_data : bit_vector := B"000";
phy_status_delay_g3 : string := "phy_status_delay_g3";
sigdet_wait_counter_data : bit_vector := B"00000000";
sigdet_wait_counter : string := "sigdet_wait_counter";
data_mask_count_val : bit_vector := B"0000000000";
data_mask_count : string := "data_mask_count";
pma_done_counter_data : bit_vector := B"000000000000000000";
pma_done_counter : string := "pma_done_count";
pc_en_counter_data : bit_vector := B"00000";
pc_en_counter : string := "pc_en_count";
pc_rst_counter_data : bit_vector := B"0000";
pc_rst_counter : string := "pc_rst_count";
phfifo_flush_wait_data : bit_vector := B"000000";
phfifo_flush_wait : string := "phfifo_flush_wait";
asn_clk_enable : string := "false";
free_run_clk_enable : string := "true";
asn_enable : string := "dis_asn"
);
port (
rcvdclk : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
pcsdigclk : in std_logic_vector(0 downto 0);
pllfixedclk : in std_logic_vector(0 downto 0);
rtxgen3capen : in std_logic_vector(0 downto 0);
rrxgen3capen : in std_logic_vector(0 downto 0);
rtxdigclksel : in std_logic_vector(0 downto 0);
rrxdigclksel : in std_logic_vector(0 downto 0);
rxrstn : in std_logic_vector(0 downto 0);
txrstn : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
pldasyncstatus : out std_logic_vector(5 downto 0);
testout : out std_logic_vector(19 downto 0);
gen3datasel : out std_logic_vector(0 downto 0);
gen3clksel : out std_logic_vector(0 downto 0);
pcsrst : out std_logic_vector(0 downto 0);
dispcbyte : out std_logic_vector(0 downto 0);
resetpcprts : out std_logic_vector(0 downto 0);
shutdownclk : out std_logic_vector(0 downto 0);
txdata : in std_logic_vector(31 downto 0);
txdatak : in std_logic_vector(3 downto 0);
txdataskip : in std_logic_vector(0 downto 0);
txsynchdr : in std_logic_vector(1 downto 0);
txblkstart : in std_logic_vector(0 downto 0);
txelecidle : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txcompliance : in std_logic_vector(0 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
rate : in std_logic_vector(1 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txswing : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
currentcoeff : in std_logic_vector(17 downto 0);
currentrxpreset : in std_logic_vector(2 downto 0);
rxupdatefc : in std_logic_vector(0 downto 0);
rxdataskip : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdataint : in std_logic_vector(31 downto 0);
rxdatakint : in std_logic_vector(3 downto 0);
rxdataskipint : in std_logic_vector(0 downto 0);
rxsynchdrint : in std_logic_vector(1 downto 0);
rxblkstartint : in std_logic_vector(0 downto 0);
txdataint : out std_logic_vector(31 downto 0);
txdatakint : out std_logic_vector(3 downto 0);
txdataskipint : out std_logic_vector(0 downto 0);
txsynchdrint : out std_logic_vector(1 downto 0);
txblkstartint : out std_logic_vector(0 downto 0);
testinfei : out std_logic_vector(18 downto 0);
eidetint : in std_logic_vector(0 downto 0);
eipartialdetint : in std_logic_vector(0 downto 0);
idetint : in std_logic_vector(0 downto 0);
blkalgndint : in std_logic_vector(0 downto 0);
clkcompinsertint : in std_logic_vector(0 downto 0);
clkcompdeleteint : in std_logic_vector(0 downto 0);
clkcompoverflint : in std_logic_vector(0 downto 0);
clkcompundflint : in std_logic_vector(0 downto 0);
errdecodeint : in std_logic_vector(0 downto 0);
rcvlfsrchkint : in std_logic_vector(0 downto 0);
errencodeint : in std_logic_vector(0 downto 0);
rxpolarityint : out std_logic_vector(0 downto 0);
revlpbkint : out std_logic_vector(0 downto 0);
inferredrxvalidint : out std_logic_vector(0 downto 0);
rxd8gpcsin : in std_logic_vector(63 downto 0);
rxelecidle8gpcsin : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
rxd8gpcsout : out std_logic_vector(63 downto 0);
revlpbk8gpcsout : out std_logic_vector(0 downto 0);
pmarxdetectvalid : in std_logic_vector(0 downto 0);
pmarxfound : in std_logic_vector(0 downto 0);
pmasignaldet : in std_logic_vector(0 downto 0);
pmapcieswdone : in std_logic_vector(1 downto 0);
pmapcieswitch : out std_logic_vector(1 downto 0);
pmatxmargin : out std_logic_vector(2 downto 0);
pmatxdeemph : out std_logic_vector(0 downto 0);
pmatxswing : out std_logic_vector(0 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmatxelecidle : out std_logic_vector(0 downto 0);
pmatxdetectrx : out std_logic_vector(0 downto 0);
ppmeidleexit : out std_logic_vector(0 downto 0);
pmaltr : out std_logic_vector(0 downto 0);
pmaearlyeios : out std_logic_vector(0 downto 0);
pmarxdetpd : out std_logic_vector(0 downto 0);
bundlingindown : in std_logic_vector(9 downto 0);
bundlingoutdown : out std_logic_vector(9 downto 0);
rxpolarity8gpcsout : out std_logic_vector(0 downto 0);
speedchangeg2 : in std_logic_vector(0 downto 0);
bundlingoutup : out std_logic_vector(9 downto 0);
bundlinginup : in std_logic_vector(9 downto 0);
masktxpll : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_pipe_gen3;
architecture behavior of stratixv_hssi_pipe_gen3 is
component stratixv_hssi_pipe_gen3_encrypted
generic (
mode : string := "pipe_g1";
ctrl_plane_bonding : string := "individual";
pipe_clk_sel : string := "func_clk";
rate_match_pad_insertion : string := "dis_rm_fifo_pad_ins";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle_g3 : string := "dis_phystatus_rst_toggle_g3";
phystatus_rst_toggle_g12 : string := "dis_phystatus_rst_toggle";
cdr_control : string := "en_cdr_ctrl";
cid_enable : string := "en_cid_mode";
parity_chk_ts1 : string := "en_ts1_parity_chk";
rxvalid_mask : string := "rxvalid_mask_en";
ph_fifo_reg_mode : string := "phfifo_reg_mode_dis";
test_mode_timers : string := "dis_test_mode_timers";
inf_ei_enable : string := "dis_inf_ei";
spd_chnge_g2_sel : string := "false";
cp_up_mstr : string := "false";
cp_dwn_mstr : string := "false";
cp_cons_sel : string := "cp_cons_default";
elecidle_delay_g12_data : bit_vector := B"000";
elecidle_delay_g12 : string := "elecidle_delay_g12";
elecidle_delay_g3_data : bit_vector := B"000";
elecidle_delay_g3 : string := "elecidle_delay_g3";
phy_status_delay_g12_data : bit_vector := B"000";
phy_status_delay_g12 : string := "phy_status_delay_g12";
phy_status_delay_g3_data : bit_vector := B"000";
phy_status_delay_g3 : string := "phy_status_delay_g3";
sigdet_wait_counter_data : bit_vector := B"00000000";
sigdet_wait_counter : string := "sigdet_wait_counter";
data_mask_count_val : bit_vector := B"0000000000";
data_mask_count : string := "data_mask_count";
pma_done_counter_data : bit_vector := B"000000000000000000";
pma_done_counter : string := "pma_done_count";
pc_en_counter_data : bit_vector := B"00000";
pc_en_counter : string := "pc_en_count";
pc_rst_counter_data : bit_vector := B"0000";
pc_rst_counter : string := "pc_rst_count";
phfifo_flush_wait_data : bit_vector := B"000000";
phfifo_flush_wait : string := "phfifo_flush_wait";
asn_clk_enable : string := "false";
free_run_clk_enable : string := "true";
asn_enable : string := "dis_asn"
);
port (
rcvdclk : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
pcsdigclk : in std_logic_vector(0 downto 0);
pllfixedclk : in std_logic_vector(0 downto 0);
rtxgen3capen : in std_logic_vector(0 downto 0);
rrxgen3capen : in std_logic_vector(0 downto 0);
rtxdigclksel : in std_logic_vector(0 downto 0);
rrxdigclksel : in std_logic_vector(0 downto 0);
rxrstn : in std_logic_vector(0 downto 0);
txrstn : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
pldasyncstatus : out std_logic_vector(5 downto 0);
testout : out std_logic_vector(19 downto 0);
gen3datasel : out std_logic_vector(0 downto 0);
gen3clksel : out std_logic_vector(0 downto 0);
pcsrst : out std_logic_vector(0 downto 0);
dispcbyte : out std_logic_vector(0 downto 0);
resetpcprts : out std_logic_vector(0 downto 0);
shutdownclk : out std_logic_vector(0 downto 0);
txdata : in std_logic_vector(31 downto 0);
txdatak : in std_logic_vector(3 downto 0);
txdataskip : in std_logic_vector(0 downto 0);
txsynchdr : in std_logic_vector(1 downto 0);
txblkstart : in std_logic_vector(0 downto 0);
txelecidle : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txcompliance : in std_logic_vector(0 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
rate : in std_logic_vector(1 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txswing : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
currentcoeff : in std_logic_vector(17 downto 0);
currentrxpreset : in std_logic_vector(2 downto 0);
rxupdatefc : in std_logic_vector(0 downto 0);
rxdataskip : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdataint : in std_logic_vector(31 downto 0);
rxdatakint : in std_logic_vector(3 downto 0);
rxdataskipint : in std_logic_vector(0 downto 0);
rxsynchdrint : in std_logic_vector(1 downto 0);
rxblkstartint : in std_logic_vector(0 downto 0);
txdataint : out std_logic_vector(31 downto 0);
txdatakint : out std_logic_vector(3 downto 0);
txdataskipint : out std_logic_vector(0 downto 0);
txsynchdrint : out std_logic_vector(1 downto 0);
txblkstartint : out std_logic_vector(0 downto 0);
testinfei : out std_logic_vector(18 downto 0);
eidetint : in std_logic_vector(0 downto 0);
eipartialdetint : in std_logic_vector(0 downto 0);
idetint : in std_logic_vector(0 downto 0);
blkalgndint : in std_logic_vector(0 downto 0);
clkcompinsertint : in std_logic_vector(0 downto 0);
clkcompdeleteint : in std_logic_vector(0 downto 0);
clkcompoverflint : in std_logic_vector(0 downto 0);
clkcompundflint : in std_logic_vector(0 downto 0);
errdecodeint : in std_logic_vector(0 downto 0);
rcvlfsrchkint : in std_logic_vector(0 downto 0);
errencodeint : in std_logic_vector(0 downto 0);
rxpolarityint : out std_logic_vector(0 downto 0);
revlpbkint : out std_logic_vector(0 downto 0);
inferredrxvalidint : out std_logic_vector(0 downto 0);
rxd8gpcsin : in std_logic_vector(63 downto 0);
rxelecidle8gpcsin : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
rxd8gpcsout : out std_logic_vector(63 downto 0);
revlpbk8gpcsout : out std_logic_vector(0 downto 0);
pmarxdetectvalid : in std_logic_vector(0 downto 0);
pmarxfound : in std_logic_vector(0 downto 0);
pmasignaldet : in std_logic_vector(0 downto 0);
pmapcieswdone : in std_logic_vector(1 downto 0);
pmapcieswitch : out std_logic_vector(1 downto 0);
pmatxmargin : out std_logic_vector(2 downto 0);
pmatxdeemph : out std_logic_vector(0 downto 0);
pmatxswing : out std_logic_vector(0 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmatxelecidle : out std_logic_vector(0 downto 0);
pmatxdetectrx : out std_logic_vector(0 downto 0);
ppmeidleexit : out std_logic_vector(0 downto 0);
pmaltr : out std_logic_vector(0 downto 0);
pmaearlyeios : out std_logic_vector(0 downto 0);
pmarxdetpd : out std_logic_vector(0 downto 0);
bundlingindown : in std_logic_vector(9 downto 0);
bundlingoutdown : out std_logic_vector(9 downto 0);
rxpolarity8gpcsout : out std_logic_vector(0 downto 0);
speedchangeg2 : in std_logic_vector(0 downto 0);
bundlingoutup : out std_logic_vector(9 downto 0);
bundlinginup : in std_logic_vector(9 downto 0);
masktxpll : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_pipe_gen3_encrypted
generic map (
mode => mode,
ctrl_plane_bonding => ctrl_plane_bonding,
pipe_clk_sel => pipe_clk_sel,
rate_match_pad_insertion => rate_match_pad_insertion,
ind_error_reporting => ind_error_reporting,
phystatus_rst_toggle_g3 => phystatus_rst_toggle_g3,
phystatus_rst_toggle_g12 => phystatus_rst_toggle_g12,
cdr_control => cdr_control,
cid_enable => cid_enable,
parity_chk_ts1 => parity_chk_ts1,
rxvalid_mask => rxvalid_mask,
ph_fifo_reg_mode => ph_fifo_reg_mode,
test_mode_timers => test_mode_timers,
inf_ei_enable => inf_ei_enable,
spd_chnge_g2_sel => spd_chnge_g2_sel,
cp_up_mstr => cp_up_mstr,
cp_dwn_mstr => cp_dwn_mstr,
cp_cons_sel => cp_cons_sel,
elecidle_delay_g12_data => elecidle_delay_g12_data,
elecidle_delay_g12 => elecidle_delay_g12,
elecidle_delay_g3_data => elecidle_delay_g3_data,
elecidle_delay_g3 => elecidle_delay_g3,
phy_status_delay_g12_data => phy_status_delay_g12_data,
phy_status_delay_g12 => phy_status_delay_g12,
phy_status_delay_g3_data => phy_status_delay_g3_data,
phy_status_delay_g3 => phy_status_delay_g3,
sigdet_wait_counter_data => sigdet_wait_counter_data,
sigdet_wait_counter => sigdet_wait_counter,
data_mask_count_val => data_mask_count_val,
data_mask_count => data_mask_count,
pma_done_counter_data => pma_done_counter_data,
pma_done_counter => pma_done_counter,
pc_en_counter_data => pc_en_counter_data,
pc_en_counter => pc_en_counter,
pc_rst_counter_data => pc_rst_counter_data,
pc_rst_counter => pc_rst_counter,
phfifo_flush_wait_data => phfifo_flush_wait_data,
phfifo_flush_wait => phfifo_flush_wait,
asn_clk_enable => asn_clk_enable,
free_run_clk_enable => free_run_clk_enable,
asn_enable => asn_enable
)
port map (
rcvdclk => rcvdclk,
txpmaclk => txpmaclk,
pcsdigclk => pcsdigclk,
pllfixedclk => pllfixedclk,
rtxgen3capen => rtxgen3capen,
rrxgen3capen => rrxgen3capen,
rtxdigclksel => rtxdigclksel,
rrxdigclksel => rrxdigclksel,
rxrstn => rxrstn,
txrstn => txrstn,
scanmoden => scanmoden,
pldasyncstatus => pldasyncstatus,
testout => testout,
gen3datasel => gen3datasel,
gen3clksel => gen3clksel,
pcsrst => pcsrst,
dispcbyte => dispcbyte,
resetpcprts => resetpcprts,
shutdownclk => shutdownclk,
txdata => txdata,
txdatak => txdatak,
txdataskip => txdataskip,
txsynchdr => txsynchdr,
txblkstart => txblkstart,
txelecidle => txelecidle,
txdetectrxloopback => txdetectrxloopback,
txcompliance => txcompliance,
rxpolarity => rxpolarity,
powerdown => powerdown,
rate => rate,
txmargin => txmargin,
txdeemph => txdeemph,
txswing => txswing,
eidleinfersel => eidleinfersel,
currentcoeff => currentcoeff,
currentrxpreset => currentrxpreset,
rxupdatefc => rxupdatefc,
rxdataskip => rxdataskip,
rxsynchdr => rxsynchdr,
rxblkstart => rxblkstart,
rxvalid => rxvalid,
phystatus => phystatus,
rxelecidle => rxelecidle,
rxstatus => rxstatus,
rxdataint => rxdataint,
rxdatakint => rxdatakint,
rxdataskipint => rxdataskipint,
rxsynchdrint => rxsynchdrint,
rxblkstartint => rxblkstartint,
txdataint => txdataint,
txdatakint => txdatakint,
txdataskipint => txdataskipint,
txsynchdrint => txsynchdrint,
txblkstartint => txblkstartint,
testinfei => testinfei,
eidetint => eidetint,
eipartialdetint => eipartialdetint,
idetint => idetint,
blkalgndint => blkalgndint,
clkcompinsertint => clkcompinsertint,
clkcompdeleteint => clkcompdeleteint,
clkcompoverflint => clkcompoverflint,
clkcompundflint => clkcompundflint,
errdecodeint => errdecodeint,
rcvlfsrchkint => rcvlfsrchkint,
errencodeint => errencodeint,
rxpolarityint => rxpolarityint,
revlpbkint => revlpbkint,
inferredrxvalidint => inferredrxvalidint,
rxd8gpcsin => rxd8gpcsin,
rxelecidle8gpcsin => rxelecidle8gpcsin,
pldltr => pldltr,
rxd8gpcsout => rxd8gpcsout,
revlpbk8gpcsout => revlpbk8gpcsout,
pmarxdetectvalid => pmarxdetectvalid,
pmarxfound => pmarxfound,
pmasignaldet => pmasignaldet,
pmapcieswdone => pmapcieswdone,
pmapcieswitch => pmapcieswitch,
pmatxmargin => pmatxmargin,
pmatxdeemph => pmatxdeemph,
pmatxswing => pmatxswing,
pmacurrentcoeff => pmacurrentcoeff,
pmacurrentrxpreset => pmacurrentrxpreset,
pmatxelecidle => pmatxelecidle,
pmatxdetectrx => pmatxdetectrx,
ppmeidleexit => ppmeidleexit,
pmaltr => pmaltr,
pmaearlyeios => pmaearlyeios,
pmarxdetpd => pmarxdetpd,
bundlingindown => bundlingindown,
bundlingoutdown => bundlingoutdown,
rxpolarity8gpcsout => rxpolarity8gpcsout,
speedchangeg2 => speedchangeg2,
bundlingoutup => bundlingoutup,
bundlinginup => bundlinginup,
masktxpll => masktxpll
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_cdr_refclk_select_mux is
generic (
lpm_type : string := "stratixv_hssi_pma_cdr_refclk_select_mux";
channel_number : integer := 0;
refclk_select : string := "ref_iqclk0";
mux_type : string := "cdr_refclk_select_mux";
reference_clock_frequency : string := "0 ps"
);
port (
calclk : in std_logic;
ffplloutbot : in std_logic;
ffpllouttop : in std_logic;
pldclk : in std_logic;
refiqclk0 : in std_logic;
refiqclk1 : in std_logic;
refiqclk10 : in std_logic;
refiqclk2 : in std_logic;
refiqclk3 : in std_logic;
refiqclk4 : in std_logic;
refiqclk5 : in std_logic;
refiqclk6 : in std_logic;
refiqclk7 : in std_logic;
refiqclk8 : in std_logic;
refiqclk9 : in std_logic;
rxiqclk0 : in std_logic;
rxiqclk1 : in std_logic;
rxiqclk10 : in std_logic;
rxiqclk2 : in std_logic;
rxiqclk3 : in std_logic;
rxiqclk4 : in std_logic;
rxiqclk5 : in std_logic;
rxiqclk6 : in std_logic;
rxiqclk7 : in std_logic;
rxiqclk8 : in std_logic;
rxiqclk9 : in std_logic;
clkout : out std_logic
);
end stratixv_hssi_pma_cdr_refclk_select_mux;
architecture behavior of stratixv_hssi_pma_cdr_refclk_select_mux is
component stratixv_hssi_pma_cdr_refclk_select_mux_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_cdr_refclk_select_mux";
channel_number : integer := 0;
refclk_select : string := "ref_iqclk0";
reference_clock_frequency : string := "0 ps"
);
port (
calclk : in std_logic;
ffplloutbot : in std_logic;
ffpllouttop : in std_logic;
pldclk : in std_logic;
refiqclk0 : in std_logic;
refiqclk1 : in std_logic;
refiqclk10 : in std_logic;
refiqclk2 : in std_logic;
refiqclk3 : in std_logic;
refiqclk4 : in std_logic;
refiqclk5 : in std_logic;
refiqclk6 : in std_logic;
refiqclk7 : in std_logic;
refiqclk8 : in std_logic;
refiqclk9 : in std_logic;
rxiqclk0 : in std_logic;
rxiqclk1 : in std_logic;
rxiqclk10 : in std_logic;
rxiqclk2 : in std_logic;
rxiqclk3 : in std_logic;
rxiqclk4 : in std_logic;
rxiqclk5 : in std_logic;
rxiqclk6 : in std_logic;
rxiqclk7 : in std_logic;
rxiqclk8 : in std_logic;
rxiqclk9 : in std_logic;
clkout : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_cdr_refclk_select_mux_encrypted
generic map (
lpm_type => lpm_type,
channel_number => channel_number,
refclk_select => refclk_select,
reference_clock_frequency => reference_clock_frequency
)
port map (
calclk => calclk,
ffplloutbot => ffplloutbot,
ffpllouttop => ffpllouttop,
pldclk => pldclk,
refiqclk0 => refiqclk0,
refiqclk1 => refiqclk1,
refiqclk10 => refiqclk10,
refiqclk2 => refiqclk2,
refiqclk3 => refiqclk3,
refiqclk4 => refiqclk4,
refiqclk5 => refiqclk5,
refiqclk6 => refiqclk6,
refiqclk7 => refiqclk7,
refiqclk8 => refiqclk8,
refiqclk9 => refiqclk9,
rxiqclk0 => rxiqclk0,
rxiqclk1 => rxiqclk1,
rxiqclk10 => rxiqclk10,
rxiqclk2 => rxiqclk2,
rxiqclk3 => rxiqclk3,
rxiqclk4 => rxiqclk4,
rxiqclk5 => rxiqclk5,
rxiqclk6 => rxiqclk6,
rxiqclk7 => rxiqclk7,
rxiqclk8 => rxiqclk8,
rxiqclk9 => rxiqclk9,
clkout => clkout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_rx_buf is
generic (
lpm_type : string := "stratixv_hssi_pma_rx_buf";
adce_pd : string := "false";
bypass_eqz_stages_123 : string := "all_stages_enabled";
eq_bw_sel : string := "bw_full_12p5";
input_vcm_sel : string := "high_vcm";
pdb_dfe : string := "false";
pdb_sd : string := "false";
qpi_enable : string := "false";
rx_dc_gain : string := "dc_gain_0db";
rx_sel_bias_source : string := "bias_vcmdrv";
sd_off : string := "clk_divrx_2";
sd_on : string := "data_pulse_6";
sd_threshold : string := "sdlv_30mv";
serial_loopback : string := "lpbkp_dis";
term_sel : string := "r_100ohm";
vccela_supply_voltage : string := "vccela_1p0v";
vcm_sel : string := "vtt_0p7v";
channel_number : integer := 0
);
port (
adaptcapture : in std_logic;
adaptdone : out std_logic;
adcestandby : in std_logic;
hardoccaldone : out std_logic;
hardoccalen : in std_logic;
eyemonitor : in std_logic_vector(4 downto 0);
ck0sigdet : in std_logic;
datain : in std_logic;
fined2aout : in std_logic;
lpbkp : in std_logic;
refclklpbk : in std_logic;
rstn : in std_logic;
rxqpipulldn : in std_logic;
slpbk : in std_logic;
dataout : out std_logic;
nonuserfrompmaux : out std_logic;
rdlpbkp : out std_logic;
rxpadce : out std_logic;
sd : out std_logic
);
end stratixv_hssi_pma_rx_buf;
architecture behavior of stratixv_hssi_pma_rx_buf is
component stratixv_hssi_pma_rx_buf_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_rx_buf";
adce_pd : string := "false";
bypass_eqz_stages_123 : string := "all_stages_enabled";
eq_bw_sel : string := "bw_full_12p5";
input_vcm_sel : string := "high_vcm";
pdb_dfe : string := "false";
pdb_sd : string := "false";
qpi_enable : string := "false";
rx_dc_gain : string := "dc_gain_0db";
rx_sel_bias_source : string := "bias_vcmdrv";
sd_off : string := "clk_divrx_2";
sd_on : string := "data_pulse_6";
sd_threshold : string := "sdlv_30mv";
serial_loopback : string := "lpbkp_dis";
term_sel : string := "r_100ohm";
vccela_supply_voltage : string := "vccela_1p0v";
vcm_sel : string := "vtt_0p7v";
channel_number : integer := 0
);
port (
ck0sigdet : in std_logic;
datain : in std_logic;
fined2aout : in std_logic;
lpbkp : in std_logic;
adaptcapture : in std_logic;
adaptdone : out std_logic;
adcestandby : in std_logic;
hardoccaldone : out std_logic;
hardoccalen : in std_logic;
eyemonitor : in std_logic_vector(4 downto 0);
refclklpbk : in std_logic;
rstn : in std_logic;
rxqpipulldn : in std_logic;
slpbk : in std_logic;
dataout : out std_logic;
nonuserfrompmaux : out std_logic;
rdlpbkp : out std_logic;
rxpadce : out std_logic;
sd : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_rx_buf_encrypted
generic map (
lpm_type => lpm_type,
adce_pd => adce_pd,
bypass_eqz_stages_123 => bypass_eqz_stages_123,
eq_bw_sel => eq_bw_sel,
input_vcm_sel => input_vcm_sel,
pdb_dfe => pdb_dfe,
pdb_sd => pdb_sd,
qpi_enable => qpi_enable,
rx_dc_gain => rx_dc_gain,
rx_sel_bias_source => rx_sel_bias_source,
sd_off => sd_off,
sd_on => sd_on,
sd_threshold => sd_threshold,
serial_loopback => serial_loopback,
term_sel => term_sel,
vccela_supply_voltage => vccela_supply_voltage,
vcm_sel => vcm_sel,
channel_number => channel_number
)
port map (
ck0sigdet => ck0sigdet,
datain => datain,
fined2aout => fined2aout,
lpbkp => lpbkp,
hardoccalen => hardoccalen,
refclklpbk => refclklpbk,
rstn => rstn,
rxqpipulldn => rxqpipulldn,
slpbk => slpbk,
dataout => dataout,
nonuserfrompmaux => nonuserfrompmaux,
rdlpbkp => rdlpbkp,
rxpadce => rxpadce,
sd => sd,
adaptcapture => adaptcapture,
adaptdone => adaptdone,
adcestandby => adcestandby,
hardoccaldone => hardoccaldone,
eyemonitor => eyemonitor
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_rx_deser is
generic (
lpm_type : string := "stratixv_hssi_pma_rx_deser";
auto_negotiation : string := "false";
bit_slip_bypass : string := "false";
mode : integer := 8;
sdclk_enable : string := "false";
vco_bypass : string := "vco_bypass_normal";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
bslip : in std_logic;
clk90b : in std_logic;
clk270b : in std_logic;
deven : in std_logic;
dodd : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pfdmodelock : in std_logic;
rstn : in std_logic;
clk33pcs : out std_logic;
clkdivrx : out std_logic;
clkdivrxrx : out std_logic;
dout : out std_logic_vector(39 downto 0);
pciel : out std_logic;
pciem : out std_logic
);
end stratixv_hssi_pma_rx_deser;
architecture behavior of stratixv_hssi_pma_rx_deser is
component stratixv_hssi_pma_rx_deser_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_rx_deser";
auto_negotiation : string := "false";
bit_slip_bypass : string := "false";
mode : integer := 8;
sdclk_enable : string := "false";
vco_bypass : string := "vco_bypass_normal";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
bslip : in std_logic;
clk90b : in std_logic;
clk270b : in std_logic;
deven : in std_logic;
dodd : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pfdmodelock : in std_logic;
rstn : in std_logic;
clk33pcs : out std_logic;
clkdivrx : out std_logic;
clkdivrxrx : out std_logic;
dout : out std_logic_vector(39 downto 0);
pciel : out std_logic;
pciem : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_rx_deser_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
bit_slip_bypass => bit_slip_bypass,
mode => mode,
sdclk_enable => sdclk_enable,
vco_bypass => vco_bypass,
channel_number => channel_number,
clk_forward_only_mode => clk_forward_only_mode
)
port map (
bslip => bslip,
clk90b => clk90b,
clk270b => clk270b,
deven => deven,
dodd => dodd,
pciesw => pciesw,
pfdmodelock => pfdmodelock,
rstn => rstn,
clk33pcs => clk33pcs,
clkdivrx => clkdivrx,
clkdivrxrx => clkdivrxrx,
dout => dout,
pciel => pciel,
pciem => pciem
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_buf is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_buf";
elec_idl_gate_ctrl : string := "true";
pre_emp_switching_ctrl_1st_post_tap : string := "fir_1pt_disabled";
pre_emp_switching_ctrl_2nd_post_tap : string := "fir_2pt_disabled";
pre_emp_switching_ctrl_pre_tap : string := "fir_pre_disabled";
qpi_en : string := "false";
rx_det : string := "mode_0";
rx_det_output_sel : string := "rx_det_pcie_out";
rx_det_pdb : string := "true";
sig_inv_2nd_tap : string := "false";
sig_inv_pre_tap : string := "false";
slew_rate_ctrl : string := "slew_30ps";
term_sel : string := "r_100ohm";
vod_switching_ctrl_main_tap : string := "fir_main_2p0ma";
channel_number : integer := 0
);
port (
datain : in std_logic;
rxdetclk : in std_logic;
txdetrx : in std_logic;
txelecidl : in std_logic;
txqpipulldn : in std_logic;
txqpipullup : in std_logic;
compass : out std_logic;
dataout : out std_logic;
detecton : out std_logic_vector(1 downto 0);
fixedclkout : out std_logic;
nonuserfrompmaux : out std_logic;
probepass : out std_logic;
rxdetectvalid : out std_logic;
rxfound : out std_logic
);
end stratixv_hssi_pma_tx_buf;
architecture behavior of stratixv_hssi_pma_tx_buf is
component stratixv_hssi_pma_tx_buf_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_buf";
elec_idl_gate_ctrl : string := "true";
pre_emp_switching_ctrl_1st_post_tap : string := "fir_1pt_disabled";
pre_emp_switching_ctrl_2nd_post_tap : string := "fir_2pt_disabled";
pre_emp_switching_ctrl_pre_tap : string := "fir_pre_disabled";
qpi_en : string := "false";
rx_det : string := "mode_0";
rx_det_output_sel : string := "rx_det_pcie_out";
rx_det_pdb : string := "true";
sig_inv_2nd_tap : string := "false";
sig_inv_pre_tap : string := "false";
slew_rate_ctrl : string := "slew_30ps";
term_sel : string := "r_100ohm";
vod_switching_ctrl_main_tap : string := "fir_main_2p0ma";
channel_number : integer := 0
);
port (
datain : in std_logic;
rxdetclk : in std_logic;
txdetrx : in std_logic;
txelecidl : in std_logic;
txqpipulldn : in std_logic;
txqpipullup : in std_logic;
compass : out std_logic;
dataout : out std_logic;
detecton : out std_logic_vector(1 downto 0);
fixedclkout : out std_logic;
nonuserfrompmaux : out std_logic;
probepass : out std_logic;
rxdetectvalid : out std_logic;
rxfound : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_buf_encrypted
generic map (
lpm_type => lpm_type,
elec_idl_gate_ctrl => elec_idl_gate_ctrl,
pre_emp_switching_ctrl_1st_post_tap => pre_emp_switching_ctrl_1st_post_tap,
pre_emp_switching_ctrl_2nd_post_tap => pre_emp_switching_ctrl_2nd_post_tap,
pre_emp_switching_ctrl_pre_tap => pre_emp_switching_ctrl_pre_tap,
qpi_en => qpi_en,
rx_det => rx_det,
rx_det_output_sel => rx_det_output_sel,
rx_det_pdb => rx_det_pdb,
sig_inv_2nd_tap => sig_inv_2nd_tap,
sig_inv_pre_tap => sig_inv_pre_tap,
slew_rate_ctrl => slew_rate_ctrl,
term_sel => term_sel,
vod_switching_ctrl_main_tap => vod_switching_ctrl_main_tap,
channel_number => channel_number
)
port map (
datain => datain,
rxdetclk => rxdetclk,
txdetrx => txdetrx,
txelecidl => txelecidl,
txqpipulldn => txqpipulldn,
txqpipullup => txqpipullup,
compass => compass,
dataout => dataout,
detecton => detecton,
fixedclkout => fixedclkout,
nonuserfrompmaux => nonuserfrompmaux,
probepass => probepass,
rxdetectvalid => rxdetectvalid,
rxfound => rxfound
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_cgb is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_cgb";
auto_negotiation : string := "false";
x1_div_m_sel : integer := 1;
channel_number : integer := 0;
data_rate : string := "";
mode : integer := 8;
rx_iqclk_sel : string := "cgb_x1_n_div";
tx_mux_power_down : string := "normal";
x1_clock_source_sel : string := "x1_clk_unused";
xn_clock_source_sel : string := "cgb_xn_unused";
xn_network_driver : string := "enable_clock_entwork_driver";
cgb_iqclk_sel : string := "cgb_x1_n_div";
ht_delay_enable : string := "false"
);
port (
clkbcdr1adj : in std_logic;
clkbcdr1loc : in std_logic;
clkbcdrloc : in std_logic;
clkbdnseg : in std_logic;
clkbffpll : in std_logic;
clkblcb : in std_logic;
clkblct : in std_logic;
clkbupseg : in std_logic;
clkcdr1adj : in std_logic;
clkcdr1loc : in std_logic;
clkcdrloc : in std_logic;
clkdnseg : in std_logic;
clkffpll : in std_logic;
clklcb : in std_logic;
clklct : in std_logic;
clkupseg : in std_logic;
cpulsex6adj : in std_logic;
cpulsex6loc : in std_logic;
cpulsexndn : in std_logic;
cpulsexnup : in std_logic;
hfclknx6adj : in std_logic;
hfclknx6loc : in std_logic;
hfclknxndn : in std_logic;
hfclknxnup : in std_logic;
hfclkpx6adj : in std_logic;
hfclkpx6loc : in std_logic;
hfclkpxndn : in std_logic;
hfclkpxnup : in std_logic;
lfclknx6adj : in std_logic;
lfclknx6loc : in std_logic;
lfclknxndn : in std_logic;
lfclknxnup : in std_logic;
lfclkpx6adj : in std_logic;
lfclkpx6loc : in std_logic;
lfclkpxndn : in std_logic;
lfclkpxnup : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0x6adj : in std_logic;
pclk0x6loc : in std_logic;
pclk0xndn : in std_logic;
pclk0xnup : in std_logic;
pclk1x6adj : in std_logic;
pclk1x6loc : in std_logic;
pclk1xndn : in std_logic;
pclk1xnup : in std_logic;
pclkx6adj : in std_logic_vector(2 downto 0);
pclkx6loc : in std_logic_vector(2 downto 0);
pclkxndn : in std_logic_vector(2 downto 0);
pclkxnup : in std_logic_vector(2 downto 0);
rxclk : in std_logic;
txpmarstb : in std_logic;
txpmasyncp : in std_logic;
xnresetin : in std_logic;
cpulse : out std_logic;
cpulseout : out std_logic;
hfclkn : out std_logic;
hfclknout : out std_logic;
hfclkp : out std_logic;
hfclkpout : out std_logic;
lfclkn : out std_logic;
lfclknout : out std_logic;
lfclkp : out std_logic;
lfclkpout : out std_logic;
pcieswdone : out std_logic_vector(1 downto 0);
pclk0 : out std_logic;
pclk0out : out std_logic;
pclk1 : out std_logic;
pclk1out : out std_logic;
pclk : out std_logic_vector(2 downto 0);
pclkout : out std_logic_vector(2 downto 0);
rxiqclk : out std_logic;
xnresetout : out std_logic
);
end stratixv_hssi_pma_tx_cgb;
architecture behavior of stratixv_hssi_pma_tx_cgb is
component stratixv_hssi_pma_tx_cgb_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_cgb";
auto_negotiation : string := "false";
x1_div_m_sel : integer := 1;
channel_number : integer := 0;
data_rate : string := "";
mode : integer := 8;
rx_iqclk_sel : string := "cgb_x1_n_div";
tx_mux_power_down : string := "normal";
x1_clock_source_sel : string := "x1_clk_unused";
xn_clock_source_sel : string := "cgb_xn_unused";
xn_network_driver : string := "enable_clock_entwork_driver";
cgb_iqclk_sel : string := "cgb_x1_n_div";
ht_delay_enable : string := "false"
);
port (
clkbcdr1adj : in std_logic;
clkbcdr1loc : in std_logic;
clkbcdrloc : in std_logic;
clkbdnseg : in std_logic;
clkbffpll : in std_logic;
clkblcb : in std_logic;
clkblct : in std_logic;
clkbupseg : in std_logic;
clkcdr1adj : in std_logic;
clkcdr1loc : in std_logic;
clkcdrloc : in std_logic;
clkdnseg : in std_logic;
clkffpll : in std_logic;
clklcb : in std_logic;
clklct : in std_logic;
clkupseg : in std_logic;
cpulsex6adj : in std_logic;
cpulsex6loc : in std_logic;
cpulsexndn : in std_logic;
cpulsexnup : in std_logic;
hfclknx6adj : in std_logic;
hfclknx6loc : in std_logic;
hfclknxndn : in std_logic;
hfclknxnup : in std_logic;
hfclkpx6adj : in std_logic;
hfclkpx6loc : in std_logic;
hfclkpxndn : in std_logic;
hfclkpxnup : in std_logic;
lfclknx6adj : in std_logic;
lfclknx6loc : in std_logic;
lfclknxndn : in std_logic;
lfclknxnup : in std_logic;
lfclkpx6adj : in std_logic;
lfclkpx6loc : in std_logic;
lfclkpxndn : in std_logic;
lfclkpxnup : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0x6adj : in std_logic;
pclk0x6loc : in std_logic;
pclk0xndn : in std_logic;
pclk0xnup : in std_logic;
pclk1x6adj : in std_logic;
pclk1x6loc : in std_logic;
pclk1xndn : in std_logic;
pclk1xnup : in std_logic;
pclkx6adj : in std_logic_vector(2 downto 0);
pclkx6loc : in std_logic_vector(2 downto 0);
pclkxndn : in std_logic_vector(2 downto 0);
pclkxnup : in std_logic_vector(2 downto 0);
rxclk : in std_logic;
txpmarstb : in std_logic;
txpmasyncp : in std_logic;
xnresetin : in std_logic;
cpulse : out std_logic;
cpulseout : out std_logic;
hfclkn : out std_logic;
hfclknout : out std_logic;
hfclkp : out std_logic;
hfclkpout : out std_logic;
lfclkn : out std_logic;
lfclknout : out std_logic;
lfclkp : out std_logic;
lfclkpout : out std_logic;
pcieswdone : out std_logic_vector(1 downto 0);
pclk0 : out std_logic;
pclk0out : out std_logic;
pclk1 : out std_logic;
pclk1out : out std_logic;
pclk : out std_logic_vector(2 downto 0);
pclkout : out std_logic_vector(2 downto 0);
rxiqclk : out std_logic;
xnresetout : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_cgb_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
x1_div_m_sel => x1_div_m_sel,
channel_number => channel_number,
data_rate => data_rate,
mode => mode,
rx_iqclk_sel => rx_iqclk_sel,
tx_mux_power_down => tx_mux_power_down,
x1_clock_source_sel => x1_clock_source_sel,
xn_clock_source_sel => xn_clock_source_sel,
xn_network_driver => xn_network_driver,
cgb_iqclk_sel => cgb_iqclk_sel,
ht_delay_enable => ht_delay_enable
)
port map (
clkbcdr1adj => clkbcdr1adj,
clkbcdr1loc => clkbcdr1loc,
clkbcdrloc => clkbcdrloc,
clkbdnseg => clkbdnseg,
clkbffpll => clkbffpll,
clkblcb => clkblcb,
clkblct => clkblct,
clkbupseg => clkbupseg,
clkcdr1adj => clkcdr1adj,
clkcdr1loc => clkcdr1loc,
clkcdrloc => clkcdrloc,
clkdnseg => clkdnseg,
clkffpll => clkffpll,
clklcb => clklcb,
clklct => clklct,
clkupseg => clkupseg,
cpulsex6adj => cpulsex6adj,
cpulsex6loc => cpulsex6loc,
cpulsexndn => cpulsexndn,
cpulsexnup => cpulsexnup,
hfclknx6adj => hfclknx6adj,
hfclknx6loc => hfclknx6loc,
hfclknxndn => hfclknxndn,
hfclknxnup => hfclknxnup,
hfclkpx6adj => hfclkpx6adj,
hfclkpx6loc => hfclkpx6loc,
hfclkpxndn => hfclkpxndn,
hfclkpxnup => hfclkpxnup,
lfclknx6adj => lfclknx6adj,
lfclknx6loc => lfclknx6loc,
lfclknxndn => lfclknxndn,
lfclknxnup => lfclknxnup,
lfclkpx6adj => lfclkpx6adj,
lfclkpx6loc => lfclkpx6loc,
lfclkpxndn => lfclkpxndn,
lfclkpxnup => lfclkpxnup,
pciesw => pciesw,
pclk0x6adj => pclk0x6adj,
pclk0x6loc => pclk0x6loc,
pclk0xndn => pclk0xndn,
pclk0xnup => pclk0xnup,
pclk1x6adj => pclk1x6adj,
pclk1x6loc => pclk1x6loc,
pclk1xndn => pclk1xndn,
pclk1xnup => pclk1xnup,
pclkx6adj => pclkx6adj,
pclkx6loc => pclkx6loc,
pclkxndn => pclkxndn,
pclkxnup => pclkxnup,
rxclk => rxclk,
txpmarstb => txpmarstb,
txpmasyncp => txpmasyncp,
xnresetin => xnresetin,
cpulse => cpulse,
cpulseout => cpulseout,
hfclkn => hfclkn,
hfclknout => hfclknout,
hfclkp => hfclkp,
hfclkpout => hfclkpout,
lfclkn => lfclkn,
lfclknout => lfclknout,
lfclkp => lfclkp,
lfclkpout => lfclkpout,
pcieswdone => pcieswdone,
pclk0 => pclk0,
pclk0out => pclk0out,
pclk1 => pclk1,
pclk1out => pclk1out,
pclk => pclk,
pclkout => pclkout,
rxiqclk => rxiqclk,
xnresetout => xnresetout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_ser is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_ser";
auto_negotiation : string := "false";
clk_divtx_deskew : string := "deskew_delay1";
mode : integer := 8;
post_tap_1_en : string := "false";
post_tap_2_en : string := "false";
pre_tap_en : string := "false";
ser_loopback : string := "false";
pclksel : string := "local_pclk";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
cpulse : in std_logic;
datain : in std_logic_vector(39 downto 0);
hfclk : in std_logic;
hfclkn : in std_logic;
lfclk : in std_logic;
lfclkn : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0 : in std_logic;
pclk1 : in std_logic;
pclk2 : in std_logic;
pclk : in std_logic_vector(2 downto 0);
rstn : in std_logic;
clkdivtx : out std_logic;
dataout : out std_logic;
div5 : out std_logic;
lbvop : out std_logic
);
end stratixv_hssi_pma_tx_ser;
architecture behavior of stratixv_hssi_pma_tx_ser is
component stratixv_hssi_pma_tx_ser_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_ser";
auto_negotiation : string := "false";
clk_divtx_deskew : string := "deskew_delay1";
mode : integer := 8;
post_tap_1_en : string := "false";
post_tap_2_en : string := "false";
pre_tap_en : string := "false";
ser_loopback : string := "false";
pclksel : string := "local_pclk";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
cpulse : in std_logic;
datain : in std_logic_vector(39 downto 0);
hfclk : in std_logic;
hfclkn : in std_logic;
lfclk : in std_logic;
lfclkn : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0 : in std_logic;
pclk1 : in std_logic;
pclk2 : in std_logic;
pclk : in std_logic_vector(2 downto 0);
rstn : in std_logic;
clkdivtx : out std_logic;
dataout : out std_logic;
div5 : out std_logic;
lbvop : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_ser_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
clk_divtx_deskew => clk_divtx_deskew,
mode => mode,
post_tap_1_en => post_tap_1_en,
post_tap_2_en => post_tap_2_en,
pre_tap_en => pre_tap_en,
ser_loopback => ser_loopback,
pclksel => pclksel,
channel_number => channel_number,
clk_forward_only_mode => clk_forward_only_mode
)
port map (
cpulse => cpulse,
datain => datain,
hfclk => hfclk,
hfclkn => hfclkn,
lfclk => lfclk,
lfclkn => lfclkn,
pciesw => pciesw,
pclk0 => pclk0,
pclk1 => pclk1,
pclk2 => pclk2,
pclk => pclk,
rstn => rstn,
clkdivtx => clkdivtx,
dataout => dataout,
div5 => div5,
lbvop => lbvop
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_common_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_common_pcs_pma_interface";
auto_speed_ena : string := "dis_auto_speed_ena";
force_freqdet : string := "force_freqdet_dis";
func_mode : string := "disable";
pcie_gen3_cap : string := "non_pcie_gen3_cap";
pipe_if_g3pcs : string := "pipe_if_8gpcs";
pma_if_dft_en : string := "dft_dis";
pma_if_dft_val : string := "dft_0";
ppm_cnt_rst : string := "ppm_cnt_rst_dis";
ppm_deassert_early : string := "deassert_early_dis";
ppm_gen1_2_cnt : string := "cnt_32k";
ppm_post_eidle_delay : string := "cnt_200_cycles";
ppmsel : string := "ppmsel_default";
prot_mode : string := "disabled_prot_mode";
refclk_dig_sel : string := "refclk_dig_dis";
selectpcs : string := "eight_g_pcs";
sup_mode : string := "full_mode"
);
port (
fref : in std_logic;
clklow : in std_logic;
pmapcieswdone : in std_logic_vector(1 downto 0);
pmarxfound : in std_logic;
pmarxdetectvalid : in std_logic;
pmahclk : in std_logic;
pldoffcalen : in std_logic;
aggrcvdclkagg : in std_logic;
aggtxdatats : in std_logic_vector(7 downto 0);
aggtxctlts : in std_logic;
aggfiforstrdqd : in std_logic;
aggendskwqd : in std_logic;
aggendskwrdptrs : in std_logic;
aggalignstatus : in std_logic;
aggalignstatussync0 : in std_logic;
aggcgcomprddall : in std_logic;
aggcgcompwrall : in std_logic;
aggfifordincomp0 : in std_logic;
aggdelcondmet0 : in std_logic;
agginsertincomplete0 : in std_logic;
aggfifoovr0 : in std_logic;
agglatencycomp0 : in std_logic;
aggrxdatars : in std_logic_vector(7 downto 0);
aggrxcontrolrs : in std_logic;
aggrcvdclkaggtoporbot : in std_logic;
aggtxdatatstoporbot : in std_logic_vector(7 downto 0);
aggtxctltstoporbot : in std_logic;
aggfiforstrdqdtoporbot : in std_logic;
aggendskwqdtoporbot : in std_logic;
aggendskwrdptrstoporbot : in std_logic;
aggalignstatustoporbot : in std_logic;
aggalignstatussync0toporbot : in std_logic;
aggcgcomprddalltoporbot : in std_logic;
aggcgcompwralltoporbot : in std_logic;
aggfifordincomp0toporbot : in std_logic;
aggdelcondmet0toporbot : in std_logic;
agginsertincomplete0toporbot : in std_logic;
aggfifoovr0toporbot : in std_logic;
agglatencycomp0toporbot : in std_logic;
aggrxdatarstoporbot : in std_logic_vector(7 downto 0);
aggrxcontrolrstoporbot : in std_logic;
pcsgen3pmapcieswitch : in std_logic_vector(1 downto 0);
pcsgen3pmatxmargin : in std_logic_vector(2 downto 0);
pcsgen3pmatxdeemph : in std_logic;
pcsgen3pmatxswing : in std_logic;
pcsgen3pmacurrentcoeff : in std_logic_vector(17 downto 0);
pcsgen3pmacurrentrxpreset : in std_logic_vector(2 downto 0);
pcsgen3pmatxelecidle : in std_logic;
pcsgen3pmatxdetectrx : in std_logic;
pcsgen3ppmeidleexit : in std_logic;
pcsgen3pmaltr : in std_logic;
pcsgen3pmaearlyeios : in std_logic;
pcs8gpcieswitch : in std_logic;
pcs8gtxelecidle : in std_logic;
pcs8gtxdetectrx : in std_logic;
pcs8gearlyeios : in std_logic;
pcs8gtxdeemphpma : in std_logic;
pcs8gtxmarginpma : in std_logic_vector(2 downto 0);
pcs8gtxswingpma : in std_logic;
pcs8gltrpma : in std_logic;
pcs8geidleexit : in std_logic;
pcsaggtxpcsrst : in std_logic;
pcsaggrxpcsrst : in std_logic;
pcsaggtxdatatc : in std_logic_vector(7 downto 0);
pcsaggtxctltc : in std_logic;
pcsaggrdenablesync : in std_logic;
pcsaggsyncstatus : in std_logic;
pcsaggaligndetsync : in std_logic_vector(1 downto 0);
pcsaggrdalign : in std_logic_vector(1 downto 0);
pcsaggalignstatussync : in std_logic;
pcsaggfifordoutcomp : in std_logic;
pcsaggcgcomprddout : in std_logic_vector(1 downto 0);
pcsaggcgcompwrout : in std_logic_vector(1 downto 0);
pcsaggdelcondmetout : in std_logic;
pcsaggfifoovrout : in std_logic;
pcsagglatencycompout : in std_logic;
pcsagginsertincompleteout : in std_logic;
pcsaggdecdatavalid : in std_logic;
pcsaggdecdata : in std_logic_vector(7 downto 0);
pcsaggdecctl : in std_logic;
pcsaggrunningdisp : in std_logic_vector(1 downto 0);
pldrxclkslip : in std_logic;
pldhardreset : in std_logic;
pcsscanmoden : in std_logic;
pcsscanshiftn : in std_logic;
pcsrefclkdig : in std_logic;
pcsaggscanmoden : in std_logic;
pcsaggscanshiftn : in std_logic;
pcsaggrefclkdig : in std_logic;
pcsgen3gen3datasel : in std_logic;
pldlccmurstb : in std_logic;
pmaoffcaldonein : in std_logic;
pmarxpmarstb : in std_logic;
pmahardreset : out std_logic;
freqlock : out std_logic;
pmapcieswitch : out std_logic_vector(1 downto 0);
pmaearlyeios : out std_logic;
pmatxdetectrx : out std_logic;
pmatxelecidle : out std_logic;
pmatxdeemph : out std_logic;
pmatxswing : out std_logic;
pmatxmargin : out std_logic_vector(2 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmaoffcaldoneout : out std_logic;
pmalccmurstb : out std_logic;
pmaltr : out std_logic;
aggtxpcsrst : out std_logic;
aggrxpcsrst : out std_logic;
aggtxdatatc : out std_logic_vector(7 downto 0);
aggtxctltc : out std_logic;
aggrdenablesync : out std_logic;
aggsyncstatus : out std_logic;
aggaligndetsync : out std_logic_vector(1 downto 0);
aggrdalign : out std_logic_vector(1 downto 0);
aggalignstatussync : out std_logic;
aggfifordoutcomp : out std_logic;
aggcgcomprddout : out std_logic_vector(1 downto 0);
aggcgcompwrout : out std_logic_vector(1 downto 0);
aggdelcondmetout : out std_logic;
aggfifoovrout : out std_logic;
agglatencycompout : out std_logic;
agginsertincompleteout : out std_logic;
aggdecdatavalid : out std_logic;
aggdecdata : out std_logic_vector(7 downto 0);
aggdecctl : out std_logic;
aggrunningdisp : out std_logic_vector(1 downto 0);
pcsgen3pmarxdetectvalid : out std_logic;
pcsgen3pmarxfound : out std_logic;
pcsgen3pmapcieswdone : out std_logic_vector(1 downto 0);
pcsgen3pllfixedclk : out std_logic;
pcsaggrcvdclkagg : out std_logic;
pcsaggtxdatats : out std_logic_vector(7 downto 0);
pcsaggtxctlts : out std_logic;
pcsaggfiforstrdqd : out std_logic;
pcsaggendskwqd : out std_logic;
pcsaggendskwrdptrs : out std_logic;
pcsaggalignstatus : out std_logic;
pcsaggalignstatussync0 : out std_logic;
pcsaggcgcomprddall : out std_logic;
pcsaggcgcompwrall : out std_logic;
pcsaggfifordincomp0 : out std_logic;
pcsaggdelcondmet0 : out std_logic;
pcsagginsertincomplete0 : out std_logic;
pcsaggfifoovr0 : out std_logic;
pcsagglatencycomp0 : out std_logic;
pcsaggrxdatars : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrs : out std_logic;
pcsaggrcvdclkaggtoporbot : out std_logic;
pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0);
pcsaggtxctltstoporbot : out std_logic;
pcsaggfiforstrdqdtoporbot : out std_logic;
pcsaggendskwqdtoporbot : out std_logic;
pcsaggendskwrdptrstoporbot : out std_logic;
pcsaggalignstatustoporbot : out std_logic;
pcsaggalignstatussync0toporbot : out std_logic;
pcsaggcgcomprddalltoporbot : out std_logic;
pcsaggcgcompwralltoporbot : out std_logic;
pcsaggfifordincomp0toporbot : out std_logic;
pcsaggdelcondmet0toporbot : out std_logic;
pcsagginsertincomplete0toporbot : out std_logic;
pcsaggfifoovr0toporbot : out std_logic;
pcsagglatencycomp0toporbot : out std_logic;
pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrstoporbot : out std_logic;
pcs8grxdetectvalid : out std_logic;
pcs8gpmarxfound : out std_logic;
pcs8ggen2ngen1 : out std_logic;
pcs8gpowerstatetransitiondone : out std_logic;
ppmcntlatch : out std_logic_vector(7 downto 0);
pldhclkout : out std_logic;
aggscanmoden : out std_logic;
aggscanshiftn : out std_logic;
aggrefclkdig : out std_logic;
pmaoffcalen : out std_logic;
pmafrefout : out std_logic;
pmaclklowout : out std_logic
);
end stratixv_hssi_common_pcs_pma_interface;
architecture behavior of stratixv_hssi_common_pcs_pma_interface is
component stratixv_hssi_common_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_common_pcs_pma_interface";
auto_speed_ena : string := "dis_auto_speed_ena";
force_freqdet : string := "force_freqdet_dis";
func_mode : string := "disable";
pcie_gen3_cap : string := "non_pcie_gen3_cap";
pipe_if_g3pcs : string := "pipe_if_8gpcs";
pma_if_dft_en : string := "dft_dis";
pma_if_dft_val : string := "dft_0";
ppm_cnt_rst : string := "ppm_cnt_rst_dis";
ppm_deassert_early : string := "deassert_early_dis";
ppm_gen1_2_cnt : string := "cnt_32k";
ppm_post_eidle_delay : string := "cnt_200_cycles";
ppmsel : string := "ppmsel_default";
prot_mode : string := "disabled_prot_mode";
refclk_dig_sel : string := "refclk_dig_dis";
selectpcs : string := "eight_g_pcs";
sup_mode : string := "full_mode"
);
port (
fref : in std_logic;
clklow : in std_logic;
pmapcieswdone : in std_logic_vector(1 downto 0);
pmarxfound : in std_logic;
pmarxdetectvalid : in std_logic;
pmahclk : in std_logic;
pldoffcalen : in std_logic;
aggrcvdclkagg : in std_logic;
aggtxdatats : in std_logic_vector(7 downto 0);
aggtxctlts : in std_logic;
aggfiforstrdqd : in std_logic;
aggendskwqd : in std_logic;
aggendskwrdptrs : in std_logic;
aggalignstatus : in std_logic;
aggalignstatussync0 : in std_logic;
aggcgcomprddall : in std_logic;
aggcgcompwrall : in std_logic;
aggfifordincomp0 : in std_logic;
aggdelcondmet0 : in std_logic;
agginsertincomplete0 : in std_logic;
aggfifoovr0 : in std_logic;
agglatencycomp0 : in std_logic;
aggrxdatars : in std_logic_vector(7 downto 0);
aggrxcontrolrs : in std_logic;
aggrcvdclkaggtoporbot : in std_logic;
aggtxdatatstoporbot : in std_logic_vector(7 downto 0);
aggtxctltstoporbot : in std_logic;
aggfiforstrdqdtoporbot : in std_logic;
aggendskwqdtoporbot : in std_logic;
aggendskwrdptrstoporbot : in std_logic;
aggalignstatustoporbot : in std_logic;
aggalignstatussync0toporbot : in std_logic;
aggcgcomprddalltoporbot : in std_logic;
aggcgcompwralltoporbot : in std_logic;
aggfifordincomp0toporbot : in std_logic;
aggdelcondmet0toporbot : in std_logic;
agginsertincomplete0toporbot : in std_logic;
aggfifoovr0toporbot : in std_logic;
agglatencycomp0toporbot : in std_logic;
aggrxdatarstoporbot : in std_logic_vector(7 downto 0);
aggrxcontrolrstoporbot : in std_logic;
pcsgen3pmapcieswitch : in std_logic_vector(1 downto 0);
pcsgen3pmatxmargin : in std_logic_vector(2 downto 0);
pcsgen3pmatxdeemph : in std_logic;
pcsgen3pmatxswing : in std_logic;
pcsgen3pmacurrentcoeff : in std_logic_vector(17 downto 0);
pcsgen3pmacurrentrxpreset : in std_logic_vector(2 downto 0);
pcsgen3pmatxelecidle : in std_logic;
pcsgen3pmatxdetectrx : in std_logic;
pcsgen3ppmeidleexit : in std_logic;
pcsgen3pmaltr : in std_logic;
pcsgen3pmaearlyeios : in std_logic;
pcs8gpcieswitch : in std_logic;
pcs8gtxelecidle : in std_logic;
pcs8gtxdetectrx : in std_logic;
pcs8gearlyeios : in std_logic;
pcs8gtxdeemphpma : in std_logic;
pcs8gtxmarginpma : in std_logic_vector(2 downto 0);
pcs8gtxswingpma : in std_logic;
pcs8gltrpma : in std_logic;
pcs8geidleexit : in std_logic;
pcsaggtxpcsrst : in std_logic;
pcsaggrxpcsrst : in std_logic;
pcsaggtxdatatc : in std_logic_vector(7 downto 0);
pcsaggtxctltc : in std_logic;
pcsaggrdenablesync : in std_logic;
pcsaggsyncstatus : in std_logic;
pcsaggaligndetsync : in std_logic_vector(1 downto 0);
pcsaggrdalign : in std_logic_vector(1 downto 0);
pcsaggalignstatussync : in std_logic;
pcsaggfifordoutcomp : in std_logic;
pcsaggcgcomprddout : in std_logic_vector(1 downto 0);
pcsaggcgcompwrout : in std_logic_vector(1 downto 0);
pcsaggdelcondmetout : in std_logic;
pcsaggfifoovrout : in std_logic;
pcsagglatencycompout : in std_logic;
pcsagginsertincompleteout : in std_logic;
pcsaggdecdatavalid : in std_logic;
pcsaggdecdata : in std_logic_vector(7 downto 0);
pcsaggdecctl : in std_logic;
pcsaggrunningdisp : in std_logic_vector(1 downto 0);
pldrxclkslip : in std_logic;
pldhardreset : in std_logic;
pcsscanmoden : in std_logic;
pcsscanshiftn : in std_logic;
pcsrefclkdig : in std_logic;
pcsaggscanmoden : in std_logic;
pcsaggscanshiftn : in std_logic;
pcsaggrefclkdig : in std_logic;
pcsgen3gen3datasel : in std_logic;
pldlccmurstb : in std_logic;
pmaoffcaldonein : in std_logic;
pmarxpmarstb : in std_logic;
pmahardreset : out std_logic;
freqlock : out std_logic;
pmapcieswitch : out std_logic_vector(1 downto 0);
pmaearlyeios : out std_logic;
pmatxdetectrx : out std_logic;
pmatxelecidle : out std_logic;
pmatxdeemph : out std_logic;
pmatxswing : out std_logic;
pmatxmargin : out std_logic_vector(2 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmaoffcaldoneout : out std_logic;
pmalccmurstb : out std_logic;
pmaltr : out std_logic;
aggtxpcsrst : out std_logic;
aggrxpcsrst : out std_logic;
aggtxdatatc : out std_logic_vector(7 downto 0);
aggtxctltc : out std_logic;
aggrdenablesync : out std_logic;
aggsyncstatus : out std_logic;
aggaligndetsync : out std_logic_vector(1 downto 0);
aggrdalign : out std_logic_vector(1 downto 0);
aggalignstatussync : out std_logic;
aggfifordoutcomp : out std_logic;
aggcgcomprddout : out std_logic_vector(1 downto 0);
aggcgcompwrout : out std_logic_vector(1 downto 0);
aggdelcondmetout : out std_logic;
aggfifoovrout : out std_logic;
agglatencycompout : out std_logic;
agginsertincompleteout : out std_logic;
aggdecdatavalid : out std_logic;
aggdecdata : out std_logic_vector(7 downto 0);
aggdecctl : out std_logic;
aggrunningdisp : out std_logic_vector(1 downto 0);
pcsgen3pmarxdetectvalid : out std_logic;
pcsgen3pmarxfound : out std_logic;
pcsgen3pmapcieswdone : out std_logic_vector(1 downto 0);
pcsgen3pllfixedclk : out std_logic;
pcsaggrcvdclkagg : out std_logic;
pcsaggtxdatats : out std_logic_vector(7 downto 0);
pcsaggtxctlts : out std_logic;
pcsaggfiforstrdqd : out std_logic;
pcsaggendskwqd : out std_logic;
pcsaggendskwrdptrs : out std_logic;
pcsaggalignstatus : out std_logic;
pcsaggalignstatussync0 : out std_logic;
pcsaggcgcomprddall : out std_logic;
pcsaggcgcompwrall : out std_logic;
pcsaggfifordincomp0 : out std_logic;
pcsaggdelcondmet0 : out std_logic;
pcsagginsertincomplete0 : out std_logic;
pcsaggfifoovr0 : out std_logic;
pcsagglatencycomp0 : out std_logic;
pcsaggrxdatars : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrs : out std_logic;
pcsaggrcvdclkaggtoporbot : out std_logic;
pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0);
pcsaggtxctltstoporbot : out std_logic;
pcsaggfiforstrdqdtoporbot : out std_logic;
pcsaggendskwqdtoporbot : out std_logic;
pcsaggendskwrdptrstoporbot : out std_logic;
pcsaggalignstatustoporbot : out std_logic;
pcsaggalignstatussync0toporbot : out std_logic;
pcsaggcgcomprddalltoporbot : out std_logic;
pcsaggcgcompwralltoporbot : out std_logic;
pcsaggfifordincomp0toporbot : out std_logic;
pcsaggdelcondmet0toporbot : out std_logic;
pcsagginsertincomplete0toporbot : out std_logic;
pcsaggfifoovr0toporbot : out std_logic;
pcsagglatencycomp0toporbot : out std_logic;
pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrstoporbot : out std_logic;
pcs8grxdetectvalid : out std_logic;
pcs8gpmarxfound : out std_logic;
pcs8ggen2ngen1 : out std_logic;
pcs8gpowerstatetransitiondone : out std_logic;
ppmcntlatch : out std_logic_vector(7 downto 0);
pldhclkout : out std_logic;
aggscanmoden : out std_logic;
aggscanshiftn : out std_logic;
aggrefclkdig : out std_logic;
pmaoffcalen : out std_logic;
pmafrefout : out std_logic;
pmaclklowout : out std_logic
);
end component;
begin
inst : stratixv_hssi_common_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
auto_speed_ena => auto_speed_ena,
force_freqdet => force_freqdet,
func_mode => func_mode,
pcie_gen3_cap => pcie_gen3_cap,
pipe_if_g3pcs => pipe_if_g3pcs,
pma_if_dft_en => pma_if_dft_en,
pma_if_dft_val => pma_if_dft_val,
ppm_cnt_rst => ppm_cnt_rst,
ppm_deassert_early => ppm_deassert_early,
ppm_gen1_2_cnt => ppm_gen1_2_cnt,
ppm_post_eidle_delay => ppm_post_eidle_delay,
ppmsel => ppmsel,
prot_mode => prot_mode,
refclk_dig_sel => refclk_dig_sel,
selectpcs => selectpcs,
sup_mode => sup_mode
)
port map (
fref => fref,
clklow => clklow,
pmapcieswdone => pmapcieswdone,
pmarxfound => pmarxfound,
pmarxdetectvalid => pmarxdetectvalid,
pmahclk => pmahclk,
pldoffcalen => pldoffcalen,
aggrcvdclkagg => aggrcvdclkagg,
aggtxdatats => aggtxdatats,
aggtxctlts => aggtxctlts,
aggfiforstrdqd => aggfiforstrdqd,
aggendskwqd => aggendskwqd,
aggendskwrdptrs => aggendskwrdptrs,
aggalignstatus => aggalignstatus,
aggalignstatussync0 => aggalignstatussync0,
aggcgcomprddall => aggcgcomprddall,
aggcgcompwrall => aggcgcompwrall,
aggfifordincomp0 => aggfifordincomp0,
aggdelcondmet0 => aggdelcondmet0,
agginsertincomplete0 => agginsertincomplete0,
aggfifoovr0 => aggfifoovr0,
agglatencycomp0 => agglatencycomp0,
aggrxdatars => aggrxdatars,
aggrxcontrolrs => aggrxcontrolrs,
aggrcvdclkaggtoporbot => aggrcvdclkaggtoporbot,
aggtxdatatstoporbot => aggtxdatatstoporbot,
aggtxctltstoporbot => aggtxctltstoporbot,
aggfiforstrdqdtoporbot => aggfiforstrdqdtoporbot,
aggendskwqdtoporbot => aggendskwqdtoporbot,
aggendskwrdptrstoporbot => aggendskwrdptrstoporbot,
aggalignstatustoporbot => aggalignstatustoporbot,
aggalignstatussync0toporbot => aggalignstatussync0toporbot,
aggcgcomprddalltoporbot => aggcgcomprddalltoporbot,
aggcgcompwralltoporbot => aggcgcompwralltoporbot,
aggfifordincomp0toporbot => aggfifordincomp0toporbot,
aggdelcondmet0toporbot => aggdelcondmet0toporbot,
agginsertincomplete0toporbot => agginsertincomplete0toporbot,
aggfifoovr0toporbot => aggfifoovr0toporbot,
agglatencycomp0toporbot => agglatencycomp0toporbot,
aggrxdatarstoporbot => aggrxdatarstoporbot,
aggrxcontrolrstoporbot => aggrxcontrolrstoporbot,
pcsgen3pmapcieswitch => pcsgen3pmapcieswitch,
pcsgen3pmatxmargin => pcsgen3pmatxmargin,
pcsgen3pmatxdeemph => pcsgen3pmatxdeemph,
pcsgen3pmatxswing => pcsgen3pmatxswing,
pcsgen3pmacurrentcoeff => pcsgen3pmacurrentcoeff,
pcsgen3pmacurrentrxpreset => pcsgen3pmacurrentrxpreset,
pcsgen3pmatxelecidle => pcsgen3pmatxelecidle,
pcsgen3pmatxdetectrx => pcsgen3pmatxdetectrx,
pcsgen3ppmeidleexit => pcsgen3ppmeidleexit,
pcsgen3pmaltr => pcsgen3pmaltr,
pcsgen3pmaearlyeios => pcsgen3pmaearlyeios,
pcs8gpcieswitch => pcs8gpcieswitch,
pcs8gtxelecidle => pcs8gtxelecidle,
pcs8gtxdetectrx => pcs8gtxdetectrx,
pcs8gearlyeios => pcs8gearlyeios,
pcs8gtxdeemphpma => pcs8gtxdeemphpma,
pcs8gtxmarginpma => pcs8gtxmarginpma,
pcs8gtxswingpma => pcs8gtxswingpma,
pcs8gltrpma => pcs8gltrpma,
pcs8geidleexit => pcs8geidleexit,
pcsaggtxpcsrst => pcsaggtxpcsrst,
pcsaggrxpcsrst => pcsaggrxpcsrst,
pcsaggtxdatatc => pcsaggtxdatatc,
pcsaggtxctltc => pcsaggtxctltc,
pcsaggrdenablesync => pcsaggrdenablesync,
pcsaggsyncstatus => pcsaggsyncstatus,
pcsaggaligndetsync => pcsaggaligndetsync,
pcsaggrdalign => pcsaggrdalign,
pcsaggalignstatussync => pcsaggalignstatussync,
pcsaggfifordoutcomp => pcsaggfifordoutcomp,
pcsaggcgcomprddout => pcsaggcgcomprddout,
pcsaggcgcompwrout => pcsaggcgcompwrout,
pcsaggdelcondmetout => pcsaggdelcondmetout,
pcsaggfifoovrout => pcsaggfifoovrout,
pcsagglatencycompout => pcsagglatencycompout,
pcsagginsertincompleteout => pcsagginsertincompleteout,
pcsaggdecdatavalid => pcsaggdecdatavalid,
pcsaggdecdata => pcsaggdecdata,
pcsaggdecctl => pcsaggdecctl,
pcsaggrunningdisp => pcsaggrunningdisp,
pldrxclkslip => pldrxclkslip,
pldhardreset => pldhardreset,
pcsscanmoden => pcsscanmoden,
pcsscanshiftn => pcsscanshiftn,
pcsrefclkdig => pcsrefclkdig,
pcsaggscanmoden => pcsaggscanmoden,
pcsaggscanshiftn => pcsaggscanshiftn,
pcsaggrefclkdig => pcsaggrefclkdig,
pcsgen3gen3datasel => pcsgen3gen3datasel,
pldlccmurstb => pldlccmurstb,
pmaoffcaldonein => pmaoffcaldonein,
pmarxpmarstb => pmarxpmarstb,
pmahardreset => pmahardreset,
freqlock => freqlock,
pmapcieswitch => pmapcieswitch,
pmaearlyeios => pmaearlyeios,
pmatxdetectrx => pmatxdetectrx,
pmatxelecidle => pmatxelecidle,
pmatxdeemph => pmatxdeemph,
pmatxswing => pmatxswing,
pmatxmargin => pmatxmargin,
pmacurrentcoeff => pmacurrentcoeff,
pmacurrentrxpreset => pmacurrentrxpreset,
pmaoffcaldoneout => pmaoffcaldoneout,
pmalccmurstb => pmalccmurstb,
pmaltr => pmaltr,
aggtxpcsrst => aggtxpcsrst,
aggrxpcsrst => aggrxpcsrst,
aggtxdatatc => aggtxdatatc,
aggtxctltc => aggtxctltc,
aggrdenablesync => aggrdenablesync,
aggsyncstatus => aggsyncstatus,
aggaligndetsync => aggaligndetsync,
aggrdalign => aggrdalign,
aggalignstatussync => aggalignstatussync,
aggfifordoutcomp => aggfifordoutcomp,
aggcgcomprddout => aggcgcomprddout,
aggcgcompwrout => aggcgcompwrout,
aggdelcondmetout => aggdelcondmetout,
aggfifoovrout => aggfifoovrout,
agglatencycompout => agglatencycompout,
agginsertincompleteout => agginsertincompleteout,
aggdecdatavalid => aggdecdatavalid,
aggdecdata => aggdecdata,
aggdecctl => aggdecctl,
aggrunningdisp => aggrunningdisp,
pcsgen3pmarxdetectvalid => pcsgen3pmarxdetectvalid,
pcsgen3pmarxfound => pcsgen3pmarxfound,
pcsgen3pmapcieswdone => pcsgen3pmapcieswdone,
pcsgen3pllfixedclk => pcsgen3pllfixedclk,
pcsaggrcvdclkagg => pcsaggrcvdclkagg,
pcsaggtxdatats => pcsaggtxdatats,
pcsaggtxctlts => pcsaggtxctlts,
pcsaggfiforstrdqd => pcsaggfiforstrdqd,
pcsaggendskwqd => pcsaggendskwqd,
pcsaggendskwrdptrs => pcsaggendskwrdptrs,
pcsaggalignstatus => pcsaggalignstatus,
pcsaggalignstatussync0 => pcsaggalignstatussync0,
pcsaggcgcomprddall => pcsaggcgcomprddall,
pcsaggcgcompwrall => pcsaggcgcompwrall,
pcsaggfifordincomp0 => pcsaggfifordincomp0,
pcsaggdelcondmet0 => pcsaggdelcondmet0,
pcsagginsertincomplete0 => pcsagginsertincomplete0,
pcsaggfifoovr0 => pcsaggfifoovr0,
pcsagglatencycomp0 => pcsagglatencycomp0,
pcsaggrxdatars => pcsaggrxdatars,
pcsaggrxcontrolrs => pcsaggrxcontrolrs,
pcsaggrcvdclkaggtoporbot => pcsaggrcvdclkaggtoporbot,
pcsaggtxdatatstoporbot => pcsaggtxdatatstoporbot,
pcsaggtxctltstoporbot => pcsaggtxctltstoporbot,
pcsaggfiforstrdqdtoporbot => pcsaggfiforstrdqdtoporbot,
pcsaggendskwqdtoporbot => pcsaggendskwqdtoporbot,
pcsaggendskwrdptrstoporbot => pcsaggendskwrdptrstoporbot,
pcsaggalignstatustoporbot => pcsaggalignstatustoporbot,
pcsaggalignstatussync0toporbot => pcsaggalignstatussync0toporbot,
pcsaggcgcomprddalltoporbot => pcsaggcgcomprddalltoporbot,
pcsaggcgcompwralltoporbot => pcsaggcgcompwralltoporbot,
pcsaggfifordincomp0toporbot => pcsaggfifordincomp0toporbot,
pcsaggdelcondmet0toporbot => pcsaggdelcondmet0toporbot,
pcsagginsertincomplete0toporbot => pcsagginsertincomplete0toporbot,
pcsaggfifoovr0toporbot => pcsaggfifoovr0toporbot,
pcsagglatencycomp0toporbot => pcsagglatencycomp0toporbot,
pcsaggrxdatarstoporbot => pcsaggrxdatarstoporbot,
pcsaggrxcontrolrstoporbot => pcsaggrxcontrolrstoporbot,
pcs8grxdetectvalid => pcs8grxdetectvalid,
pcs8gpmarxfound => pcs8gpmarxfound,
pcs8ggen2ngen1 => pcs8ggen2ngen1,
pcs8gpowerstatetransitiondone => pcs8gpowerstatetransitiondone,
ppmcntlatch => ppmcntlatch,
pldhclkout => pldhclkout,
aggscanmoden => aggscanmoden,
aggscanshiftn => aggscanshiftn,
aggrefclkdig => aggrefclkdig,
pmaoffcalen => pmaoffcalen,
pmafrefout => pmafrefout,
pmaclklowout => pmaclklowout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_common_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_common_pld_pcs_interface";
data_source : string := "pld";
emsip_enable : string := "emsip_disable";
selectpcs : string := "eight_g_pcs"
);
port (
pldhardresetin : in std_logic;
pldscanmoden : in std_logic;
pldscanshiftn : in std_logic;
pldgen3refclkdig : in std_logic;
pld10grefclkdig : in std_logic;
pld8grefclkdig : in std_logic;
pldaggrefclkdig : in std_logic;
pldpcspmaifrefclkdig : in std_logic;
pldrate : in std_logic_vector(1 downto 0);
pldeidleinfersel : in std_logic_vector(2 downto 0);
pld8gsoftresetallhssi : in std_logic;
pld8gplniotri : in std_logic;
pld8gprbsciden : in std_logic;
pld8gltr : in std_logic;
pld8gtxelecidle : in std_logic;
pld8gtxdetectrxloopback : in std_logic;
pld8gtxdeemph : in std_logic;
pld8gtxmargin : in std_logic_vector(2 downto 0);
pld8gtxswing : in std_logic;
pld8grxpolarity : in std_logic;
pld8gpowerdown : in std_logic_vector(1 downto 0);
pldgen3currentcoeff : in std_logic_vector(17 downto 0);
pldgen3currentrxpreset : in std_logic_vector(2 downto 0);
pcs10gtestdata : in std_logic_vector(19 downto 0);
pcs8gchnltestbusout : in std_logic_vector(9 downto 0);
pcs8grxvalid : in std_logic;
pcs8grxelecidle : in std_logic;
pcs8grxstatus : in std_logic_vector(2 downto 0);
pcs8gphystatus : in std_logic;
pldhclkin : in std_logic;
pcsgen3pldasyncstatus : in std_logic_vector(5 downto 0);
pcsgen3testout : in std_logic_vector(19 downto 0);
emsippcsreset : in std_logic_vector(2 downto 0);
emsippcsctrl : in std_logic_vector(38 downto 0);
pmafref : in std_logic;
pmaclklow : in std_logic;
pmaoffcaldone : in std_logic;
pldoffcalenin : in std_logic;
pcsgen3masktxpll : in std_logic;
rcomemsip : in std_logic;
rcomhipena : in std_logic;
rcomblocksel : in std_logic_vector(1 downto 0);
pldtestdata : out std_logic_vector(19 downto 0);
pld8grxvalid : out std_logic;
pld8grxelecidle : out std_logic;
pld8grxstatus : out std_logic_vector(2 downto 0);
pld8gphystatus : out std_logic;
pldgen3pldasyncstatus : out std_logic_vector(5 downto 0);
pcs10ghardresetn : out std_logic;
pcs10gscanmoden : out std_logic;
pcs10gscanshiftn : out std_logic;
pcs10grefclkdig : out std_logic;
pcs8ghardreset : out std_logic;
pcs8gsoftresetallhssi : out std_logic;
pcs8gplniotri : out std_logic;
pcs8gscanmoden : out std_logic;
pcs8gscanshiftn : out std_logic;
pcs8grefclkdig : out std_logic;
pcs8gprbsciden : out std_logic;
pcs8gltr : out std_logic;
pcs8gtxelecidle : out std_logic;
pcs8gtxdetectrxloopback : out std_logic;
pcs8gtxdeemph : out std_logic;
pcs8gtxmargin : out std_logic_vector(2 downto 0);
pcs8gtxswing : out std_logic;
pcs8grxpolarity : out std_logic;
pcs8grate : out std_logic;
pcs8gpowerdown : out std_logic_vector(1 downto 0);
pcs8geidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3pcsdigclk : out std_logic;
pcsgen3rate : out std_logic_vector(1 downto 0);
pcsgen3eidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3scanmoden : out std_logic;
pcsgen3scanshiftn : out std_logic;
pcsgen3pldltr : out std_logic;
pldhardresetout : out std_logic;
pcsgen3currentcoeff : out std_logic_vector(17 downto 0);
pcsgen3currentrxpreset : out std_logic_vector(2 downto 0);
pcsaggrefclkdig : out std_logic;
pcspcspmaifrefclkdig : out std_logic;
pcsaggscanmoden : out std_logic;
pcsaggscanshiftn : out std_logic;
pcspcspmaifscanmoden : out std_logic;
pcspcspmaifscanshiftn : out std_logic;
emsippcsclkout : out std_logic_vector(2 downto 0);
emsippcsstatus : out std_logic_vector(13 downto 0);
pldfref : out std_logic;
pldclklow : out std_logic;
emsipenabledusermode : out std_logic;
pldoffcalenout : out std_logic;
pldoffcaldone : out std_logic;
pldgen3masktxpll : out std_logic
);
end stratixv_hssi_common_pld_pcs_interface;
architecture behavior of stratixv_hssi_common_pld_pcs_interface is
component stratixv_hssi_common_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_common_pld_pcs_interface";
data_source : string := "pld";
emsip_enable : string := "emsip_disable";
selectpcs : string := "eight_g_pcs"
);
port (
pldhardresetin : in std_logic;
pldscanmoden : in std_logic;
pldscanshiftn : in std_logic;
pldgen3refclkdig : in std_logic;
pld10grefclkdig : in std_logic;
pld8grefclkdig : in std_logic;
pldaggrefclkdig : in std_logic;
pldpcspmaifrefclkdig : in std_logic;
pldrate : in std_logic_vector(1 downto 0);
pldeidleinfersel : in std_logic_vector(2 downto 0);
pld8gsoftresetallhssi : in std_logic;
pld8gplniotri : in std_logic;
pld8gprbsciden : in std_logic;
pld8gltr : in std_logic;
pld8gtxelecidle : in std_logic;
pld8gtxdetectrxloopback : in std_logic;
pld8gtxdeemph : in std_logic;
pld8gtxmargin : in std_logic_vector(2 downto 0);
pld8gtxswing : in std_logic;
pld8grxpolarity : in std_logic;
pld8gpowerdown : in std_logic_vector(1 downto 0);
pldgen3currentcoeff : in std_logic_vector(17 downto 0);
pldgen3currentrxpreset : in std_logic_vector(2 downto 0);
pcs10gtestdata : in std_logic_vector(19 downto 0);
pcs8gchnltestbusout : in std_logic_vector(9 downto 0);
pcs8grxvalid : in std_logic;
pcs8grxelecidle : in std_logic;
pcs8grxstatus : in std_logic_vector(2 downto 0);
pcs8gphystatus : in std_logic;
pldhclkin : in std_logic;
pcsgen3pldasyncstatus : in std_logic_vector(5 downto 0);
pcsgen3testout : in std_logic_vector(19 downto 0);
emsippcsreset : in std_logic_vector(2 downto 0);
emsippcsctrl : in std_logic_vector(38 downto 0);
pmafref : in std_logic;
pmaclklow : in std_logic;
pmaoffcaldone : in std_logic;
pldoffcalenin : in std_logic;
pcsgen3masktxpll : in std_logic;
rcomemsip : in std_logic;
rcomhipena : in std_logic;
rcomblocksel : in std_logic_vector(1 downto 0);
pldtestdata : out std_logic_vector(19 downto 0);
pld8grxvalid : out std_logic;
pld8grxelecidle : out std_logic;
pld8grxstatus : out std_logic_vector(2 downto 0);
pld8gphystatus : out std_logic;
pldgen3pldasyncstatus : out std_logic_vector(5 downto 0);
pcs10ghardresetn : out std_logic;
pcs10gscanmoden : out std_logic;
pcs10gscanshiftn : out std_logic;
pcs10grefclkdig : out std_logic;
pcs8ghardreset : out std_logic;
pcs8gsoftresetallhssi : out std_logic;
pcs8gplniotri : out std_logic;
pcs8gscanmoden : out std_logic;
pcs8gscanshiftn : out std_logic;
pcs8grefclkdig : out std_logic;
pcs8gprbsciden : out std_logic;
pcs8gltr : out std_logic;
pcs8gtxelecidle : out std_logic;
pcs8gtxdetectrxloopback : out std_logic;
pcs8gtxdeemph : out std_logic;
pcs8gtxmargin : out std_logic_vector(2 downto 0);
pcs8gtxswing : out std_logic;
pcs8grxpolarity : out std_logic;
pcs8grate : out std_logic;
pcs8gpowerdown : out std_logic_vector(1 downto 0);
pcs8geidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3pcsdigclk : out std_logic;
pcsgen3rate : out std_logic_vector(1 downto 0);
pcsgen3eidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3scanmoden : out std_logic;
pcsgen3scanshiftn : out std_logic;
pcsgen3pldltr : out std_logic;
pldhardresetout : out std_logic;
pcsgen3currentcoeff : out std_logic_vector(17 downto 0);
pcsgen3currentrxpreset : out std_logic_vector(2 downto 0);
pcsaggrefclkdig : out std_logic;
pcspcspmaifrefclkdig : out std_logic;
pcsaggscanmoden : out std_logic;
pcsaggscanshiftn : out std_logic;
pcspcspmaifscanmoden : out std_logic;
pcspcspmaifscanshiftn : out std_logic;
emsippcsclkout : out std_logic_vector(2 downto 0);
emsippcsstatus : out std_logic_vector(13 downto 0);
pldfref : out std_logic;
pldclklow : out std_logic;
emsipenabledusermode : out std_logic;
pldoffcalenout : out std_logic;
pldoffcaldone : out std_logic;
pldgen3masktxpll : out std_logic
);
end component;
begin
inst : stratixv_hssi_common_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
emsip_enable => emsip_enable,
selectpcs => selectpcs
)
port map (
pldhardresetin => pldhardresetin,
pldscanmoden => pldscanmoden,
pldscanshiftn => pldscanshiftn,
pldgen3refclkdig => pldgen3refclkdig,
pld10grefclkdig => pld10grefclkdig,
pld8grefclkdig => pld8grefclkdig,
pldaggrefclkdig => pldaggrefclkdig,
pldpcspmaifrefclkdig => pldpcspmaifrefclkdig,
pldrate => pldrate,
pldeidleinfersel => pldeidleinfersel,
pld8gsoftresetallhssi => pld8gsoftresetallhssi,
pld8gplniotri => pld8gplniotri,
pld8gprbsciden => pld8gprbsciden,
pld8gltr => pld8gltr,
pld8gtxelecidle => pld8gtxelecidle,
pld8gtxdetectrxloopback => pld8gtxdetectrxloopback,
pld8gtxdeemph => pld8gtxdeemph,
pld8gtxmargin => pld8gtxmargin,
pld8gtxswing => pld8gtxswing,
pld8grxpolarity => pld8grxpolarity,
pld8gpowerdown => pld8gpowerdown,
pldgen3currentcoeff => pldgen3currentcoeff,
pldgen3currentrxpreset => pldgen3currentrxpreset,
pcs10gtestdata => pcs10gtestdata,
pcs8gchnltestbusout => pcs8gchnltestbusout,
pcs8grxvalid => pcs8grxvalid,
pcs8grxelecidle => pcs8grxelecidle,
pcs8grxstatus => pcs8grxstatus,
pcs8gphystatus => pcs8gphystatus,
pldhclkin => pldhclkin,
pcsgen3pldasyncstatus => pcsgen3pldasyncstatus,
pcsgen3testout => pcsgen3testout,
emsippcsreset => emsippcsreset,
emsippcsctrl => emsippcsctrl,
pmafref => pmafref,
pmaclklow => pmaclklow,
pmaoffcaldone => pmaoffcaldone,
pldoffcalenin => pldoffcalenin,
pcsgen3masktxpll => pcsgen3masktxpll,
rcomemsip => rcomemsip,
rcomhipena => rcomhipena,
rcomblocksel => rcomblocksel,
pldtestdata => pldtestdata,
pld8grxvalid => pld8grxvalid,
pld8grxelecidle => pld8grxelecidle,
pld8grxstatus => pld8grxstatus,
pld8gphystatus => pld8gphystatus,
pldgen3pldasyncstatus => pldgen3pldasyncstatus,
pcs10ghardresetn => pcs10ghardresetn,
pcs10gscanmoden => pcs10gscanmoden,
pcs10gscanshiftn => pcs10gscanshiftn,
pcs10grefclkdig => pcs10grefclkdig,
pcs8ghardreset => pcs8ghardreset,
pcs8gsoftresetallhssi => pcs8gsoftresetallhssi,
pcs8gplniotri => pcs8gplniotri,
pcs8gscanmoden => pcs8gscanmoden,
pcs8gscanshiftn => pcs8gscanshiftn,
pcs8grefclkdig => pcs8grefclkdig,
pcs8gprbsciden => pcs8gprbsciden,
pcs8gltr => pcs8gltr,
pcs8gtxelecidle => pcs8gtxelecidle,
pcs8gtxdetectrxloopback => pcs8gtxdetectrxloopback,
pcs8gtxdeemph => pcs8gtxdeemph,
pcs8gtxmargin => pcs8gtxmargin,
pcs8gtxswing => pcs8gtxswing,
pcs8grxpolarity => pcs8grxpolarity,
pcs8grate => pcs8grate,
pcs8gpowerdown => pcs8gpowerdown,
pcs8geidleinfersel => pcs8geidleinfersel,
pcsgen3pcsdigclk => pcsgen3pcsdigclk,
pcsgen3rate => pcsgen3rate,
pcsgen3eidleinfersel => pcsgen3eidleinfersel,
pcsgen3scanmoden => pcsgen3scanmoden,
pcsgen3scanshiftn => pcsgen3scanshiftn,
pcsgen3pldltr => pcsgen3pldltr,
pldhardresetout => pldhardresetout,
pcsgen3currentcoeff => pcsgen3currentcoeff,
pcsgen3currentrxpreset => pcsgen3currentrxpreset,
pcsaggrefclkdig => pcsaggrefclkdig,
pcspcspmaifrefclkdig => pcspcspmaifrefclkdig,
pcsaggscanmoden => pcsaggscanmoden,
pcsaggscanshiftn => pcsaggscanshiftn,
pcspcspmaifscanmoden => pcspcspmaifscanmoden,
pcspcspmaifscanshiftn => pcspcspmaifscanshiftn,
emsippcsclkout => emsippcsclkout,
emsippcsstatus => emsippcsstatus,
pldfref => pldfref,
pldclklow => pldclklow,
emsipenabledusermode => emsipenabledusermode,
pldoffcalenout => pldoffcalenout,
pldoffcaldone => pldoffcaldone,
pldgen3masktxpll => pldgen3masktxpll
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_rx_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_rx_pcs_pma_interface";
clkslip_sel : string := "pld";
prot_mode : string := "other_protocols";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrompma : in std_logic_vector(39 downto 0);
pmasigdet : in std_logic;
pmasignalok : in std_logic;
pcs10grxclkiqout : in std_logic;
pcsgen3rxclkiqout : in std_logic;
pcs8grxclkiqout : in std_logic;
pcs8grxclkslip : in std_logic;
pmaclkdiv33txorrxin : in std_logic;
pmarxplllockin : in std_logic;
pldrxpmarstb : in std_logic;
pldrxclkslip : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxclkslipsel : in std_logic;
pmarxclkslip : out std_logic;
pmarxclkout : out std_logic;
clkoutto10gpcs : out std_logic;
dataoutto10gpcs : out std_logic_vector(39 downto 0);
pcs10gsignalok : out std_logic;
clockouttogen3pcs : out std_logic;
dataouttogen3pcs : out std_logic_vector(31 downto 0);
pcsgen3pmasignaldet : out std_logic;
clockoutto8gpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(19 downto 0);
pcs8gsigdetni : out std_logic;
pmaclkdiv33txorrxout : out std_logic;
pcs10gclkdiv33txorrx : out std_logic;
pmarxpmarstb : out std_logic;
pmarxplllockout : out std_logic
);
end stratixv_hssi_rx_pcs_pma_interface;
architecture behavior of stratixv_hssi_rx_pcs_pma_interface is
component stratixv_hssi_rx_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_rx_pcs_pma_interface";
clkslip_sel : string := "pld";
prot_mode : string := "other_protocols";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrompma : in std_logic_vector(39 downto 0);
pmasigdet : in std_logic;
pmasignalok : in std_logic;
pcs10grxclkiqout : in std_logic;
pcsgen3rxclkiqout : in std_logic;
pcs8grxclkiqout : in std_logic;
pcs8grxclkslip : in std_logic;
pmaclkdiv33txorrxin : in std_logic;
pmarxplllockin : in std_logic;
pldrxpmarstb : in std_logic;
pldrxclkslip : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxclkslipsel : in std_logic;
pmarxclkslip : out std_logic;
pmarxclkout : out std_logic;
clkoutto10gpcs : out std_logic;
dataoutto10gpcs : out std_logic_vector(39 downto 0);
pcs10gsignalok : out std_logic;
clockouttogen3pcs : out std_logic;
dataouttogen3pcs : out std_logic_vector(31 downto 0);
pcsgen3pmasignaldet : out std_logic;
clockoutto8gpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(19 downto 0);
pcs8gsigdetni : out std_logic;
pmaclkdiv33txorrxout : out std_logic;
pcs10gclkdiv33txorrx : out std_logic;
pmarxpmarstb : out std_logic;
pmarxplllockout : out std_logic
);
end component;
begin
inst : stratixv_hssi_rx_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
clkslip_sel => clkslip_sel,
prot_mode => prot_mode,
selectpcs => selectpcs
)
port map (
clockinfrompma => clockinfrompma,
datainfrompma => datainfrompma,
pmasigdet => pmasigdet,
pmasignalok => pmasignalok,
pcs10grxclkiqout => pcs10grxclkiqout,
pcsgen3rxclkiqout => pcsgen3rxclkiqout,
pcs8grxclkiqout => pcs8grxclkiqout,
pcs8grxclkslip => pcs8grxclkslip,
pmaclkdiv33txorrxin => pmaclkdiv33txorrxin,
pmarxplllockin => pmarxplllockin,
pldrxpmarstb => pldrxpmarstb,
pldrxclkslip => pldrxclkslip,
rrxblocksel => rrxblocksel,
rrxclkslipsel => rrxclkslipsel,
pmarxclkslip => pmarxclkslip,
pmarxclkout => pmarxclkout,
clkoutto10gpcs => clkoutto10gpcs,
dataoutto10gpcs => dataoutto10gpcs,
pcs10gsignalok => pcs10gsignalok,
clockouttogen3pcs => clockouttogen3pcs,
dataouttogen3pcs => dataouttogen3pcs,
pcsgen3pmasignaldet => pcsgen3pmasignaldet,
clockoutto8gpcs => clockoutto8gpcs,
dataoutto8gpcs => dataoutto8gpcs,
pcs8gsigdetni => pcs8gsigdetni,
pmaclkdiv33txorrxout => pmaclkdiv33txorrxout,
pcs10gclkdiv33txorrx => pcs10gclkdiv33txorrx,
pmarxpmarstb => pmarxpmarstb,
pmarxplllockout => pmarxplllockout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_rx_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_rx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false";
selectpcs : string := "eight_g_pcs"
);
port (
pld10grxpldclk : in std_logic;
pld10grxpldrstn : in std_logic;
pld10grxalignen : in std_logic;
pld10grxalignclr : in std_logic;
pld10grxrden : in std_logic;
pld10grxdispclr : in std_logic;
pld10grxclrerrblkcnt : in std_logic;
pld10grxclrbercount : in std_logic;
pld10grxprbserrclr : in std_logic;
pld10grxbitslip : in std_logic;
pld8grxurstpma : in std_logic;
pld8grxurstpcs : in std_logic;
pld8gcmpfifourst : in std_logic;
pld8gphfifourstrx : in std_logic;
pld8gencdt : in std_logic;
pld8ga1a2size : in std_logic;
pld8gbitslip : in std_logic;
pld8grdenablermf : in std_logic;
pld8gwrenablermf : in std_logic;
pld8gpldrxclk : in std_logic;
pld8gpolinvrx : in std_logic;
pld8gbitlocreven : in std_logic;
pld8gbytereven : in std_logic;
pld8gbytordpld : in std_logic;
pld8gwrdisablerx : in std_logic;
pld8grdenablerx : in std_logic;
pldgen3rxrstn : in std_logic;
pldrxclkslipin : in std_logic;
pld8gpldextrain : in std_logic_vector(3 downto 0);
clockinfrom10gpcs : in std_logic;
pcs10grxdatavalid : in std_logic;
datainfrom10gpcs : in std_logic_vector(63 downto 0);
pcs10grxcontrol : in std_logic_vector(9 downto 0);
pcs10grxempty : in std_logic;
pcs10grxpempty : in std_logic;
pcs10grxpfull : in std_logic;
pcs10grxoflwerr : in std_logic;
pcs10grxalignval : in std_logic;
pcs10grxblklock : in std_logic;
pcs10grxhiber : in std_logic;
pcs10grxframelock : in std_logic;
pcs10grxrdpossts : in std_logic;
pcs10grxrdnegsts : in std_logic;
pcs10grxskipins : in std_logic;
pcs10grxrxframe : in std_logic;
pcs10grxpyldins : in std_logic;
pcs10grxsyncerr : in std_logic;
pcs10grxscrmerr : in std_logic;
pcs10grxskiperr : in std_logic;
pcs10grxdiagerr : in std_logic;
pcs10grxsherr : in std_logic;
pcs10grxmfrmerr : in std_logic;
pcs10grxcrc32err : in std_logic;
pcs10grxdiagstatus : in std_logic_vector(1 downto 0);
datainfrom8gpcs : in std_logic_vector(63 downto 0);
clockinfrom8gpcs : in std_logic;
pcs8gbisterr : in std_logic;
pcs8grcvdclkpmab : in std_logic;
pcs8gsignaldetectout : in std_logic;
pcs8gbistdone : in std_logic;
pcs8grlvlt : in std_logic;
pcs8gfullrmf : in std_logic;
pcs8gemptyrmf : in std_logic;
pcs8gfullrx : in std_logic;
pcs8gemptyrx : in std_logic;
pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0);
pcs8gbyteordflag : in std_logic;
pcs8gwaboundary : in std_logic_vector(4 downto 0);
pcs8grxdatavalid : in std_logic_vector(3 downto 0);
pcs8grxsynchdr : in std_logic_vector(1 downto 0);
pcs8grxblkstart : in std_logic_vector(3 downto 0);
pmaclkdiv33txorrx : in std_logic;
emsippcsrxclkin : in std_logic_vector(2 downto 0);
emsippcsrxreset : in std_logic_vector(6 downto 0);
emsippcsrxctrl : in std_logic_vector(24 downto 0);
pmarxplllock : in std_logic;
pldrxpmarstbin : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10grxfifoinsert : in std_logic;
pld8gsyncsmeninput : in std_logic;
pcs10grxfifodel : in std_logic;
dataouttopld : out std_logic_vector(63 downto 0);
pld10grxclkout : out std_logic;
pld10grxdatavalid : out std_logic;
pld10grxcontrol : out std_logic_vector(9 downto 0);
pld10grxempty : out std_logic;
pld10grxpempty : out std_logic;
pld10grxpfull : out std_logic;
pld10grxoflwerr : out std_logic;
pld10grxalignval : out std_logic;
pld10grxblklock : out std_logic;
pld10grxhiber : out std_logic;
pld10grxframelock : out std_logic;
pld10grxrdpossts : out std_logic;
pld10grxrdnegsts : out std_logic;
pld10grxskipins : out std_logic;
pld10grxrxframe : out std_logic;
pld10grxpyldins : out std_logic;
pld10grxsyncerr : out std_logic;
pld10grxscrmerr : out std_logic;
pld10grxskiperr : out std_logic;
pld10grxdiagerr : out std_logic;
pld10grxsherr : out std_logic;
pld10grxmfrmerr : out std_logic;
pld10grxcrc32err : out std_logic;
pld10grxdiagstatus : out std_logic_vector(1 downto 0);
pld8grxclkout : out std_logic;
pld8gbisterr : out std_logic;
pld8grcvdclkpmab : out std_logic;
pld8gsignaldetectout : out std_logic;
pld8gbistdone : out std_logic;
pld8grlvlt : out std_logic;
pld8gfullrmf : out std_logic;
pld8gemptyrmf : out std_logic;
pld8gfullrx : out std_logic;
pld8gemptyrx : out std_logic;
pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0);
pld8gbyteordflag : out std_logic;
pld8gwaboundary : out std_logic_vector(4 downto 0);
pld8grxdatavalid : out std_logic_vector(3 downto 0);
pld8grxsynchdr : out std_logic_vector(1 downto 0);
pld8grxblkstart : out std_logic_vector(3 downto 0);
pcs10grxpldclk : out std_logic;
pcs10grxpldrstn : out std_logic;
pcs10grxalignen : out std_logic;
pcs10grxalignclr : out std_logic;
pcs10grxrden : out std_logic;
pcs10grxdispclr : out std_logic;
pcs10grxclrerrblkcnt : out std_logic;
pcs10grxclrbercount : out std_logic;
pcs10grxprbserrclr : out std_logic;
pcs10grxbitslip : out std_logic;
pcs8grxurstpma : out std_logic;
pcs8grxurstpcs : out std_logic;
pcs8gcmpfifourst : out std_logic;
pcs8gphfifourstrx : out std_logic;
pcs8gencdt : out std_logic;
pcs8ga1a2size : out std_logic;
pcs8gbitslip : out std_logic;
pcs8grdenablermf : out std_logic;
pcs8gwrenablermf : out std_logic;
pcs8gpldrxclk : out std_logic;
pcs8gpolinvrx : out std_logic;
pcs8gbitlocreven : out std_logic;
pcs8gbytereven : out std_logic;
pcs8gbytordpld : out std_logic;
pcs8gwrdisablerx : out std_logic;
pcs8grdenablerx : out std_logic;
pcs8gpldextrain : out std_logic_vector(3 downto 0);
pcsgen3rxrstn : out std_logic;
pldrxclkslipout : out std_logic;
pldclkdiv33txorrx : out std_logic;
emsiprxdata : out std_logic_vector(63 downto 0);
emsippcsrxclkout : out std_logic_vector(3 downto 0);
emsippcsrxstatus : out std_logic_vector(63 downto 0);
pldrxpmarstbout : out std_logic;
pldrxplllock : out std_logic;
pld10grxfifodel : out std_logic;
pldrxiqclkout : out std_logic;
pld10grxfifoinsert : out std_logic;
pcs8gsyncsmenoutput : out std_logic
);
end stratixv_hssi_rx_pld_pcs_interface;
architecture behavior of stratixv_hssi_rx_pld_pcs_interface is
component stratixv_hssi_rx_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_rx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false";
selectpcs : string := "eight_g_pcs"
);
port (
pld10grxpldclk : in std_logic;
pld10grxpldrstn : in std_logic;
pld10grxalignen : in std_logic;
pld10grxalignclr : in std_logic;
pld10grxrden : in std_logic;
pld10grxdispclr : in std_logic;
pld10grxclrerrblkcnt : in std_logic;
pld10grxclrbercount : in std_logic;
pld10grxprbserrclr : in std_logic;
pld10grxbitslip : in std_logic;
pld8grxurstpma : in std_logic;
pld8grxurstpcs : in std_logic;
pld8gcmpfifourst : in std_logic;
pld8gphfifourstrx : in std_logic;
pld8gencdt : in std_logic;
pld8ga1a2size : in std_logic;
pld8gbitslip : in std_logic;
pld8grdenablermf : in std_logic;
pld8gwrenablermf : in std_logic;
pld8gpldrxclk : in std_logic;
pld8gpolinvrx : in std_logic;
pld8gbitlocreven : in std_logic;
pld8gbytereven : in std_logic;
pld8gbytordpld : in std_logic;
pld8gwrdisablerx : in std_logic;
pld8grdenablerx : in std_logic;
pldgen3rxrstn : in std_logic;
pldrxclkslipin : in std_logic;
pld8gpldextrain : in std_logic_vector(3 downto 0);
clockinfrom10gpcs : in std_logic;
pcs10grxdatavalid : in std_logic;
datainfrom10gpcs : in std_logic_vector(63 downto 0);
pcs10grxcontrol : in std_logic_vector(9 downto 0);
pcs10grxempty : in std_logic;
pcs10grxpempty : in std_logic;
pcs10grxpfull : in std_logic;
pcs10grxoflwerr : in std_logic;
pcs10grxalignval : in std_logic;
pcs10grxblklock : in std_logic;
pcs10grxhiber : in std_logic;
pcs10grxframelock : in std_logic;
pcs10grxrdpossts : in std_logic;
pcs10grxrdnegsts : in std_logic;
pcs10grxskipins : in std_logic;
pcs10grxrxframe : in std_logic;
pcs10grxpyldins : in std_logic;
pcs10grxsyncerr : in std_logic;
pcs10grxscrmerr : in std_logic;
pcs10grxskiperr : in std_logic;
pcs10grxdiagerr : in std_logic;
pcs10grxsherr : in std_logic;
pcs10grxmfrmerr : in std_logic;
pcs10grxcrc32err : in std_logic;
pcs10grxdiagstatus : in std_logic_vector(1 downto 0);
datainfrom8gpcs : in std_logic_vector(63 downto 0);
clockinfrom8gpcs : in std_logic;
pcs8gbisterr : in std_logic;
pcs8grcvdclkpmab : in std_logic;
pcs8gsignaldetectout : in std_logic;
pcs8gbistdone : in std_logic;
pcs8grlvlt : in std_logic;
pcs8gfullrmf : in std_logic;
pcs8gemptyrmf : in std_logic;
pcs8gfullrx : in std_logic;
pcs8gemptyrx : in std_logic;
pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0);
pcs8gbyteordflag : in std_logic;
pcs8gwaboundary : in std_logic_vector(4 downto 0);
pcs8grxdatavalid : in std_logic_vector(3 downto 0);
pcs8grxsynchdr : in std_logic_vector(1 downto 0);
pcs8grxblkstart : in std_logic_vector(3 downto 0);
pmaclkdiv33txorrx : in std_logic;
emsippcsrxclkin : in std_logic_vector(2 downto 0);
emsippcsrxreset : in std_logic_vector(6 downto 0);
emsippcsrxctrl : in std_logic_vector(24 downto 0);
pmarxplllock : in std_logic;
pldrxpmarstbin : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10grxfifoinsert : in std_logic;
pld8gsyncsmeninput : in std_logic;
pcs10grxfifodel : in std_logic;
dataouttopld : out std_logic_vector(63 downto 0);
pld10grxclkout : out std_logic;
pld10grxdatavalid : out std_logic;
pld10grxcontrol : out std_logic_vector(9 downto 0);
pld10grxempty : out std_logic;
pld10grxpempty : out std_logic;
pld10grxpfull : out std_logic;
pld10grxoflwerr : out std_logic;
pld10grxalignval : out std_logic;
pld10grxblklock : out std_logic;
pld10grxhiber : out std_logic;
pld10grxframelock : out std_logic;
pld10grxrdpossts : out std_logic;
pld10grxrdnegsts : out std_logic;
pld10grxskipins : out std_logic;
pld10grxrxframe : out std_logic;
pld10grxpyldins : out std_logic;
pld10grxsyncerr : out std_logic;
pld10grxscrmerr : out std_logic;
pld10grxskiperr : out std_logic;
pld10grxdiagerr : out std_logic;
pld10grxsherr : out std_logic;
pld10grxmfrmerr : out std_logic;
pld10grxcrc32err : out std_logic;
pld10grxdiagstatus : out std_logic_vector(1 downto 0);
pld8grxclkout : out std_logic;
pld8gbisterr : out std_logic;
pld8grcvdclkpmab : out std_logic;
pld8gsignaldetectout : out std_logic;
pld8gbistdone : out std_logic;
pld8grlvlt : out std_logic;
pld8gfullrmf : out std_logic;
pld8gemptyrmf : out std_logic;
pld8gfullrx : out std_logic;
pld8gemptyrx : out std_logic;
pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0);
pld8gbyteordflag : out std_logic;
pld8gwaboundary : out std_logic_vector(4 downto 0);
pld8grxdatavalid : out std_logic_vector(3 downto 0);
pld8grxsynchdr : out std_logic_vector(1 downto 0);
pld8grxblkstart : out std_logic_vector(3 downto 0);
pcs10grxpldclk : out std_logic;
pcs10grxpldrstn : out std_logic;
pcs10grxalignen : out std_logic;
pcs10grxalignclr : out std_logic;
pcs10grxrden : out std_logic;
pcs10grxdispclr : out std_logic;
pcs10grxclrerrblkcnt : out std_logic;
pcs10grxclrbercount : out std_logic;
pcs10grxprbserrclr : out std_logic;
pcs10grxbitslip : out std_logic;
pcs8grxurstpma : out std_logic;
pcs8grxurstpcs : out std_logic;
pcs8gcmpfifourst : out std_logic;
pcs8gphfifourstrx : out std_logic;
pcs8gencdt : out std_logic;
pcs8ga1a2size : out std_logic;
pcs8gbitslip : out std_logic;
pcs8grdenablermf : out std_logic;
pcs8gwrenablermf : out std_logic;
pcs8gpldrxclk : out std_logic;
pcs8gpolinvrx : out std_logic;
pcs8gbitlocreven : out std_logic;
pcs8gbytereven : out std_logic;
pcs8gbytordpld : out std_logic;
pcs8gwrdisablerx : out std_logic;
pcs8grdenablerx : out std_logic;
pcs8gpldextrain : out std_logic_vector(3 downto 0);
pcsgen3rxrstn : out std_logic;
pldrxclkslipout : out std_logic;
pldclkdiv33txorrx : out std_logic;
emsiprxdata : out std_logic_vector(63 downto 0);
emsippcsrxclkout : out std_logic_vector(3 downto 0);
emsippcsrxstatus : out std_logic_vector(63 downto 0);
pldrxpmarstbout : out std_logic;
pldrxplllock : out std_logic;
pld10grxfifodel : out std_logic;
pldrxiqclkout : out std_logic;
pld10grxfifoinsert : out std_logic;
pcs8gsyncsmenoutput : out std_logic
);
end component;
begin
inst : stratixv_hssi_rx_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
is_10g_0ppm => is_10g_0ppm,
is_8g_0ppm => is_8g_0ppm,
selectpcs => selectpcs
)
port map (
pld10grxpldclk => pld10grxpldclk,
pld10grxpldrstn => pld10grxpldrstn,
pld10grxalignen => pld10grxalignen,
pld10grxalignclr => pld10grxalignclr,
pld10grxrden => pld10grxrden,
pld10grxdispclr => pld10grxdispclr,
pld10grxclrerrblkcnt => pld10grxclrerrblkcnt,
pld10grxclrbercount => pld10grxclrbercount,
pld10grxprbserrclr => pld10grxprbserrclr,
pld10grxbitslip => pld10grxbitslip,
pld8grxurstpma => pld8grxurstpma,
pld8grxurstpcs => pld8grxurstpcs,
pld8gcmpfifourst => pld8gcmpfifourst,
pld8gphfifourstrx => pld8gphfifourstrx,
pld8gencdt => pld8gencdt,
pld8ga1a2size => pld8ga1a2size,
pld8gbitslip => pld8gbitslip,
pld8grdenablermf => pld8grdenablermf,
pld8gwrenablermf => pld8gwrenablermf,
pld8gpldrxclk => pld8gpldrxclk,
pld8gpolinvrx => pld8gpolinvrx,
pld8gbitlocreven => pld8gbitlocreven,
pld8gbytereven => pld8gbytereven,
pld8gbytordpld => pld8gbytordpld,
pld8gwrdisablerx => pld8gwrdisablerx,
pld8grdenablerx => pld8grdenablerx,
pldgen3rxrstn => pldgen3rxrstn,
pldrxclkslipin => pldrxclkslipin,
pld8gpldextrain => pld8gpldextrain,
clockinfrom10gpcs => clockinfrom10gpcs,
pcs10grxdatavalid => pcs10grxdatavalid,
datainfrom10gpcs => datainfrom10gpcs,
pcs10grxcontrol => pcs10grxcontrol,
pcs10grxempty => pcs10grxempty,
pcs10grxpempty => pcs10grxpempty,
pcs10grxpfull => pcs10grxpfull,
pcs10grxoflwerr => pcs10grxoflwerr,
pcs10grxalignval => pcs10grxalignval,
pcs10grxblklock => pcs10grxblklock,
pcs10grxhiber => pcs10grxhiber,
pcs10grxframelock => pcs10grxframelock,
pcs10grxrdpossts => pcs10grxrdpossts,
pcs10grxrdnegsts => pcs10grxrdnegsts,
pcs10grxskipins => pcs10grxskipins,
pcs10grxrxframe => pcs10grxrxframe,
pcs10grxpyldins => pcs10grxpyldins,
pcs10grxsyncerr => pcs10grxsyncerr,
pcs10grxscrmerr => pcs10grxscrmerr,
pcs10grxskiperr => pcs10grxskiperr,
pcs10grxdiagerr => pcs10grxdiagerr,
pcs10grxsherr => pcs10grxsherr,
pcs10grxmfrmerr => pcs10grxmfrmerr,
pcs10grxcrc32err => pcs10grxcrc32err,
pcs10grxdiagstatus => pcs10grxdiagstatus,
datainfrom8gpcs => datainfrom8gpcs,
clockinfrom8gpcs => clockinfrom8gpcs,
pcs8gbisterr => pcs8gbisterr,
pcs8grcvdclkpmab => pcs8grcvdclkpmab,
pcs8gsignaldetectout => pcs8gsignaldetectout,
pcs8gbistdone => pcs8gbistdone,
pcs8grlvlt => pcs8grlvlt,
pcs8gfullrmf => pcs8gfullrmf,
pcs8gemptyrmf => pcs8gemptyrmf,
pcs8gfullrx => pcs8gfullrx,
pcs8gemptyrx => pcs8gemptyrx,
pcs8ga1a2k1k2flag => pcs8ga1a2k1k2flag,
pcs8gbyteordflag => pcs8gbyteordflag,
pcs8gwaboundary => pcs8gwaboundary,
pcs8grxdatavalid => pcs8grxdatavalid,
pcs8grxsynchdr => pcs8grxsynchdr,
pcs8grxblkstart => pcs8grxblkstart,
pmaclkdiv33txorrx => pmaclkdiv33txorrx,
emsippcsrxclkin => emsippcsrxclkin,
emsippcsrxreset => emsippcsrxreset,
emsippcsrxctrl => emsippcsrxctrl,
pmarxplllock => pmarxplllock,
pldrxpmarstbin => pldrxpmarstbin,
rrxblocksel => rrxblocksel,
rrxemsip => rrxemsip,
emsipenabledusermode => emsipenabledusermode,
pcs10grxfifoinsert => pcs10grxfifoinsert,
pld8gsyncsmeninput => pld8gsyncsmeninput,
pcs10grxfifodel => pcs10grxfifodel,
dataouttopld => dataouttopld,
pld10grxclkout => pld10grxclkout,
pld10grxdatavalid => pld10grxdatavalid,
pld10grxcontrol => pld10grxcontrol,
pld10grxempty => pld10grxempty,
pld10grxpempty => pld10grxpempty,
pld10grxpfull => pld10grxpfull,
pld10grxoflwerr => pld10grxoflwerr,
pld10grxalignval => pld10grxalignval,
pld10grxblklock => pld10grxblklock,
pld10grxhiber => pld10grxhiber,
pld10grxframelock => pld10grxframelock,
pld10grxrdpossts => pld10grxrdpossts,
pld10grxrdnegsts => pld10grxrdnegsts,
pld10grxskipins => pld10grxskipins,
pld10grxrxframe => pld10grxrxframe,
pld10grxpyldins => pld10grxpyldins,
pld10grxsyncerr => pld10grxsyncerr,
pld10grxscrmerr => pld10grxscrmerr,
pld10grxskiperr => pld10grxskiperr,
pld10grxdiagerr => pld10grxdiagerr,
pld10grxsherr => pld10grxsherr,
pld10grxmfrmerr => pld10grxmfrmerr,
pld10grxcrc32err => pld10grxcrc32err,
pld10grxdiagstatus => pld10grxdiagstatus,
pld8grxclkout => pld8grxclkout,
pld8gbisterr => pld8gbisterr,
pld8grcvdclkpmab => pld8grcvdclkpmab,
pld8gsignaldetectout => pld8gsignaldetectout,
pld8gbistdone => pld8gbistdone,
pld8grlvlt => pld8grlvlt,
pld8gfullrmf => pld8gfullrmf,
pld8gemptyrmf => pld8gemptyrmf,
pld8gfullrx => pld8gfullrx,
pld8gemptyrx => pld8gemptyrx,
pld8ga1a2k1k2flag => pld8ga1a2k1k2flag,
pld8gbyteordflag => pld8gbyteordflag,
pld8gwaboundary => pld8gwaboundary,
pld8grxdatavalid => pld8grxdatavalid,
pld8grxsynchdr => pld8grxsynchdr,
pld8grxblkstart => pld8grxblkstart,
pcs10grxpldclk => pcs10grxpldclk,
pcs10grxpldrstn => pcs10grxpldrstn,
pcs10grxalignen => pcs10grxalignen,
pcs10grxalignclr => pcs10grxalignclr,
pcs10grxrden => pcs10grxrden,
pcs10grxdispclr => pcs10grxdispclr,
pcs10grxclrerrblkcnt => pcs10grxclrerrblkcnt,
pcs10grxclrbercount => pcs10grxclrbercount,
pcs10grxprbserrclr => pcs10grxprbserrclr,
pcs10grxbitslip => pcs10grxbitslip,
pcs8grxurstpma => pcs8grxurstpma,
pcs8grxurstpcs => pcs8grxurstpcs,
pcs8gcmpfifourst => pcs8gcmpfifourst,
pcs8gphfifourstrx => pcs8gphfifourstrx,
pcs8gencdt => pcs8gencdt,
pcs8ga1a2size => pcs8ga1a2size,
pcs8gbitslip => pcs8gbitslip,
pcs8grdenablermf => pcs8grdenablermf,
pcs8gwrenablermf => pcs8gwrenablermf,
pcs8gpldrxclk => pcs8gpldrxclk,
pcs8gpolinvrx => pcs8gpolinvrx,
pcs8gbitlocreven => pcs8gbitlocreven,
pcs8gbytereven => pcs8gbytereven,
pcs8gbytordpld => pcs8gbytordpld,
pcs8gwrdisablerx => pcs8gwrdisablerx,
pcs8grdenablerx => pcs8grdenablerx,
pcs8gpldextrain => pcs8gpldextrain,
pcsgen3rxrstn => pcsgen3rxrstn,
pldrxclkslipout => pldrxclkslipout,
pldclkdiv33txorrx => pldclkdiv33txorrx,
emsiprxdata => emsiprxdata,
emsippcsrxclkout => emsippcsrxclkout,
emsippcsrxstatus => emsippcsrxstatus,
pldrxpmarstbout => pldrxpmarstbout,
pldrxplllock => pldrxplllock,
pld10grxfifodel => pld10grxfifodel,
pldrxiqclkout => pldrxiqclkout,
pld10grxfifoinsert => pld10grxfifoinsert,
pcs8gsyncsmenoutput => pcs8gsyncsmenoutput
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_tx_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_tx_pcs_pma_interface";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrom10gpcs : in std_logic_vector(39 downto 0);
pcs10gtxclkiqout : in std_logic;
pcsgen3txclkiqout : in std_logic;
datainfromgen3pcs : in std_logic_vector(31 downto 0);
pcs8gtxclkiqout : in std_logic;
datainfrom8gpcs : in std_logic_vector(19 downto 0);
pmaclkdiv33lcin : in std_logic;
pmatxlcplllockin : in std_logic;
pmatxcmuplllockin : in std_logic;
rtxblocksel : in std_logic_vector(1 downto 0);
pcsgen3gen3datasel : in std_logic;
pldtxpmasyncp : in std_logic;
dataouttopma : out std_logic_vector(39 downto 0);
pmatxclkout : out std_logic;
clockoutto10gpcs : out std_logic;
clockoutto8gpcs : out std_logic;
pmaclkdiv33lcout : out std_logic;
pcs10gclkdiv33lc : out std_logic;
pmatxlcplllockout : out std_logic;
pmatxcmuplllockout : out std_logic;
pmatxpmasyncp : out std_logic
);
end stratixv_hssi_tx_pcs_pma_interface;
architecture behavior of stratixv_hssi_tx_pcs_pma_interface is
component stratixv_hssi_tx_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_tx_pcs_pma_interface";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrom10gpcs : in std_logic_vector(39 downto 0);
pcs10gtxclkiqout : in std_logic;
pcsgen3txclkiqout : in std_logic;
datainfromgen3pcs : in std_logic_vector(31 downto 0);
pcs8gtxclkiqout : in std_logic;
datainfrom8gpcs : in std_logic_vector(19 downto 0);
pmaclkdiv33lcin : in std_logic;
pmatxlcplllockin : in std_logic;
pmatxcmuplllockin : in std_logic;
rtxblocksel : in std_logic_vector(1 downto 0);
pcsgen3gen3datasel : in std_logic;
pldtxpmasyncp : in std_logic;
dataouttopma : out std_logic_vector(39 downto 0);
pmatxclkout : out std_logic;
clockoutto10gpcs : out std_logic;
clockoutto8gpcs : out std_logic;
pmaclkdiv33lcout : out std_logic;
pcs10gclkdiv33lc : out std_logic;
pmatxlcplllockout : out std_logic;
pmatxcmuplllockout : out std_logic;
pmatxpmasyncp : out std_logic
);
end component;
begin
inst : stratixv_hssi_tx_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
selectpcs => selectpcs
)
port map (
clockinfrompma => clockinfrompma,
datainfrom10gpcs => datainfrom10gpcs,
pcs10gtxclkiqout => pcs10gtxclkiqout,
pcsgen3txclkiqout => pcsgen3txclkiqout,
datainfromgen3pcs => datainfromgen3pcs,
pcs8gtxclkiqout => pcs8gtxclkiqout,
datainfrom8gpcs => datainfrom8gpcs,
pmaclkdiv33lcin => pmaclkdiv33lcin,
pmatxlcplllockin => pmatxlcplllockin,
pmatxcmuplllockin => pmatxcmuplllockin,
rtxblocksel => rtxblocksel,
pcsgen3gen3datasel => pcsgen3gen3datasel,
pldtxpmasyncp => pldtxpmasyncp,
dataouttopma => dataouttopma,
pmatxclkout => pmatxclkout,
clockoutto10gpcs => clockoutto10gpcs,
clockoutto8gpcs => clockoutto8gpcs,
pmaclkdiv33lcout => pmaclkdiv33lcout,
pcs10gclkdiv33lc => pcs10gclkdiv33lc,
pmatxlcplllockout => pmatxlcplllockout,
pmatxcmuplllockout => pmatxcmuplllockout,
pmatxpmasyncp => pmatxpmasyncp
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_tx_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_tx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false"
);
port (
datainfrompld : in std_logic_vector(63 downto 0);
pld10gtxpldclk : in std_logic;
pld10gtxpldrstn : in std_logic;
pld10gtxdatavalid : in std_logic;
pld10gtxcontrol : in std_logic_vector(8 downto 0);
pld10gtxbitslip : in std_logic_vector(6 downto 0);
pld10gtxdiagstatus : in std_logic_vector(1 downto 0);
pld10gtxwordslip : in std_logic;
pld10gtxbursten : in std_logic;
pld8gpldtxclk : in std_logic;
pld8gpolinvtx : in std_logic;
pld8grevloopbk : in std_logic;
pld8gwrenabletx : in std_logic;
pld8grddisabletx : in std_logic;
pld8gphfifoursttx : in std_logic;
pld8gtxboundarysel : in std_logic_vector(4 downto 0);
pld8gtxdatavalid : in std_logic_vector(3 downto 0);
pld8gtxsynchdr : in std_logic_vector(1 downto 0);
pld8gtxblkstart : in std_logic_vector(3 downto 0);
pldgen3txrstn : in std_logic;
pld8gtxurstpcs : in std_logic;
clockinfrom10gpcs : in std_logic;
pcs10gtxempty : in std_logic;
pcs10gtxpempty : in std_logic;
pcs10gtxpfull : in std_logic;
pcs10gtxfull : in std_logic;
pcs10gtxframe : in std_logic;
pcs10gtxburstenexe : in std_logic;
pcs10gtxwordslipexe : in std_logic;
pcs8gfulltx : in std_logic;
pcs8gemptytx : in std_logic;
clockinfrom8gpcs : in std_logic;
pmaclkdiv33lc : in std_logic;
emsiptxdata : in std_logic_vector(63 downto 0);
emsippcstxclkin : in std_logic_vector(2 downto 0);
emsippcstxreset : in std_logic_vector(5 downto 0);
emsippcstxctrl : in std_logic_vector(43 downto 0);
pmatxlcplllock : in std_logic;
pmatxcmuplllock : in std_logic;
pldtxpmarstbin : in std_logic;
pldlccmurstbin : in std_logic;
rtxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10gextraout : in std_logic_vector(3 downto 0);
pldtxpmasyncpin : in std_logic;
pcs10gtxfifoinsert : in std_logic;
pcs10gtxfifodel : in std_logic;
pld10gextrain : in std_logic_vector(3 downto 0);
pld10gtxclkout : out std_logic;
pld10gtxempty : out std_logic;
pld10gtxpempty : out std_logic;
pld10gtxpfull : out std_logic;
pld10gtxfull : out std_logic;
pld10gtxframe : out std_logic;
pld10gtxburstenexe : out std_logic;
pld10gtxwordslipexe : out std_logic;
pld8gfulltx : out std_logic;
pld8gemptytx : out std_logic;
pld8gtxclkout : out std_logic;
pcs10gtxpldclk : out std_logic;
pcs10gtxpldrstn : out std_logic;
pcs10gtxdatavalid : out std_logic;
dataoutto10gpcs : out std_logic_vector(63 downto 0);
pcs10gtxcontrol : out std_logic_vector(8 downto 0);
pcs10gtxbitslip : out std_logic_vector(6 downto 0);
pcs10gtxdiagstatus : out std_logic_vector(1 downto 0);
pcs10gtxwordslip : out std_logic;
pcs10gtxbursten : out std_logic;
pcs8gtxurstpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(43 downto 0);
pcs8gpldtxclk : out std_logic;
pcs8gpolinvtx : out std_logic;
pcs8grevloopbk : out std_logic;
pcs8gwrenabletx : out std_logic;
pcs8grddisabletx : out std_logic;
pcs8gphfifoursttx : out std_logic;
pcs8gtxboundarysel : out std_logic_vector(4 downto 0);
pcs8gtxdatavalid : out std_logic_vector(3 downto 0);
pcs8gtxsynchdr : out std_logic_vector(1 downto 0);
pcs8gtxblkstart : out std_logic_vector(3 downto 0);
pcsgen3txrstn : out std_logic;
pldclkdiv33lc : out std_logic;
emsippcstxclkout : out std_logic_vector(2 downto 0);
emsippcstxstatus : out std_logic_vector(16 downto 0);
pldtxpmarstbout : out std_logic;
pldlccmurstbout : out std_logic;
pldtxlcplllock : out std_logic;
pldtxcmuplllock : out std_logic;
pldtxiqclkout : out std_logic;
pcs10gextrain : out std_logic_vector(3 downto 0);
pld10gtxfifodel : out std_logic;
pldtxpmasyncpout : out std_logic;
pld10gtxfifoinsert : out std_logic;
pld10gextraout : out std_logic_vector(3 downto 0)
);
end stratixv_hssi_tx_pld_pcs_interface;
architecture behavior of stratixv_hssi_tx_pld_pcs_interface is
component stratixv_hssi_tx_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_tx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false"
);
port (
datainfrompld : in std_logic_vector(63 downto 0);
pld10gtxpldclk : in std_logic;
pld10gtxpldrstn : in std_logic;
pld10gtxdatavalid : in std_logic;
pld10gtxcontrol : in std_logic_vector(8 downto 0);
pld10gtxbitslip : in std_logic_vector(6 downto 0);
pld10gtxdiagstatus : in std_logic_vector(1 downto 0);
pld10gtxwordslip : in std_logic;
pld10gtxbursten : in std_logic;
pld8gpldtxclk : in std_logic;
pld8gpolinvtx : in std_logic;
pld8grevloopbk : in std_logic;
pld8gwrenabletx : in std_logic;
pld8grddisabletx : in std_logic;
pld8gphfifoursttx : in std_logic;
pld8gtxboundarysel : in std_logic_vector(4 downto 0);
pld8gtxdatavalid : in std_logic_vector(3 downto 0);
pld8gtxsynchdr : in std_logic_vector(1 downto 0);
pld8gtxblkstart : in std_logic_vector(3 downto 0);
pldgen3txrstn : in std_logic;
pld8gtxurstpcs : in std_logic;
clockinfrom10gpcs : in std_logic;
pcs10gtxempty : in std_logic;
pcs10gtxpempty : in std_logic;
pcs10gtxpfull : in std_logic;
pcs10gtxfull : in std_logic;
pcs10gtxframe : in std_logic;
pcs10gtxburstenexe : in std_logic;
pcs10gtxwordslipexe : in std_logic;
pcs8gfulltx : in std_logic;
pcs8gemptytx : in std_logic;
clockinfrom8gpcs : in std_logic;
pmaclkdiv33lc : in std_logic;
emsiptxdata : in std_logic_vector(63 downto 0);
emsippcstxclkin : in std_logic_vector(2 downto 0);
emsippcstxreset : in std_logic_vector(5 downto 0);
emsippcstxctrl : in std_logic_vector(43 downto 0);
pmatxlcplllock : in std_logic;
pmatxcmuplllock : in std_logic;
pldtxpmarstbin : in std_logic;
pldlccmurstbin : in std_logic;
rtxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10gextraout : in std_logic_vector(3 downto 0);
pldtxpmasyncpin : in std_logic;
pcs10gtxfifoinsert : in std_logic;
pcs10gtxfifodel : in std_logic;
pld10gextrain : in std_logic_vector(3 downto 0);
pld10gtxclkout : out std_logic;
pld10gtxempty : out std_logic;
pld10gtxpempty : out std_logic;
pld10gtxpfull : out std_logic;
pld10gtxfull : out std_logic;
pld10gtxframe : out std_logic;
pld10gtxburstenexe : out std_logic;
pld10gtxwordslipexe : out std_logic;
pld8gfulltx : out std_logic;
pld8gemptytx : out std_logic;
pld8gtxclkout : out std_logic;
pcs10gtxpldclk : out std_logic;
pcs10gtxpldrstn : out std_logic;
pcs10gtxdatavalid : out std_logic;
dataoutto10gpcs : out std_logic_vector(63 downto 0);
pcs10gtxcontrol : out std_logic_vector(8 downto 0);
pcs10gtxbitslip : out std_logic_vector(6 downto 0);
pcs10gtxdiagstatus : out std_logic_vector(1 downto 0);
pcs10gtxwordslip : out std_logic;
pcs10gtxbursten : out std_logic;
pcs8gtxurstpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(43 downto 0);
pcs8gpldtxclk : out std_logic;
pcs8gpolinvtx : out std_logic;
pcs8grevloopbk : out std_logic;
pcs8gwrenabletx : out std_logic;
pcs8grddisabletx : out std_logic;
pcs8gphfifoursttx : out std_logic;
pcs8gtxboundarysel : out std_logic_vector(4 downto 0);
pcs8gtxdatavalid : out std_logic_vector(3 downto 0);
pcs8gtxsynchdr : out std_logic_vector(1 downto 0);
pcs8gtxblkstart : out std_logic_vector(3 downto 0);
pcsgen3txrstn : out std_logic;
pldclkdiv33lc : out std_logic;
emsippcstxclkout : out std_logic_vector(2 downto 0);
emsippcstxstatus : out std_logic_vector(16 downto 0);
pldtxpmarstbout : out std_logic;
pldlccmurstbout : out std_logic;
pldtxlcplllock : out std_logic;
pldtxcmuplllock : out std_logic;
pldtxiqclkout : out std_logic;
pcs10gextrain : out std_logic_vector(3 downto 0);
pld10gtxfifodel : out std_logic;
pldtxpmasyncpout : out std_logic;
pld10gtxfifoinsert : out std_logic;
pld10gextraout : out std_logic_vector(3 downto 0)
);
end component;
begin
inst : stratixv_hssi_tx_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
is_10g_0ppm => is_10g_0ppm,
is_8g_0ppm => is_8g_0ppm
)
port map (
datainfrompld => datainfrompld,
pld10gtxpldclk => pld10gtxpldclk,
pld10gtxpldrstn => pld10gtxpldrstn,
pld10gtxdatavalid => pld10gtxdatavalid,
pld10gtxcontrol => pld10gtxcontrol,
pld10gtxbitslip => pld10gtxbitslip,
pld10gtxdiagstatus => pld10gtxdiagstatus,
pld10gtxwordslip => pld10gtxwordslip,
pld10gtxbursten => pld10gtxbursten,
pld8gpldtxclk => pld8gpldtxclk,
pld8gpolinvtx => pld8gpolinvtx,
pld8grevloopbk => pld8grevloopbk,
pld8gwrenabletx => pld8gwrenabletx,
pld8grddisabletx => pld8grddisabletx,
pld8gphfifoursttx => pld8gphfifoursttx,
pld8gtxboundarysel => pld8gtxboundarysel,
pld8gtxdatavalid => pld8gtxdatavalid,
pld8gtxsynchdr => pld8gtxsynchdr,
pld8gtxblkstart => pld8gtxblkstart,
pldgen3txrstn => pldgen3txrstn,
pld8gtxurstpcs => pld8gtxurstpcs,
clockinfrom10gpcs => clockinfrom10gpcs,
pcs10gtxempty => pcs10gtxempty,
pcs10gtxpempty => pcs10gtxpempty,
pcs10gtxpfull => pcs10gtxpfull,
pcs10gtxfull => pcs10gtxfull,
pcs10gtxframe => pcs10gtxframe,
pcs10gtxburstenexe => pcs10gtxburstenexe,
pcs10gtxwordslipexe => pcs10gtxwordslipexe,
pcs8gfulltx => pcs8gfulltx,
pcs8gemptytx => pcs8gemptytx,
clockinfrom8gpcs => clockinfrom8gpcs,
pmaclkdiv33lc => pmaclkdiv33lc,
emsiptxdata => emsiptxdata,
emsippcstxclkin => emsippcstxclkin,
emsippcstxreset => emsippcstxreset,
emsippcstxctrl => emsippcstxctrl,
pmatxlcplllock => pmatxlcplllock,
pmatxcmuplllock => pmatxcmuplllock,
pldtxpmarstbin => pldtxpmarstbin,
pldlccmurstbin => pldlccmurstbin,
rtxemsip => rtxemsip,
emsipenabledusermode => emsipenabledusermode,
pcs10gextraout => pcs10gextraout,
pldtxpmasyncpin => pldtxpmasyncpin,
pcs10gtxfifoinsert => pcs10gtxfifoinsert,
pcs10gtxfifodel => pcs10gtxfifodel,
pld10gextrain => pld10gextrain,
pld10gtxclkout => pld10gtxclkout,
pld10gtxempty => pld10gtxempty,
pld10gtxpempty => pld10gtxpempty,
pld10gtxpfull => pld10gtxpfull,
pld10gtxfull => pld10gtxfull,
pld10gtxframe => pld10gtxframe,
pld10gtxburstenexe => pld10gtxburstenexe,
pld10gtxwordslipexe => pld10gtxwordslipexe,
pld8gfulltx => pld8gfulltx,
pld8gemptytx => pld8gemptytx,
pld8gtxclkout => pld8gtxclkout,
pcs10gtxpldclk => pcs10gtxpldclk,
pcs10gtxpldrstn => pcs10gtxpldrstn,
pcs10gtxdatavalid => pcs10gtxdatavalid,
dataoutto10gpcs => dataoutto10gpcs,
pcs10gtxcontrol => pcs10gtxcontrol,
pcs10gtxbitslip => pcs10gtxbitslip,
pcs10gtxdiagstatus => pcs10gtxdiagstatus,
pcs10gtxwordslip => pcs10gtxwordslip,
pcs10gtxbursten => pcs10gtxbursten,
pcs8gtxurstpcs => pcs8gtxurstpcs,
dataoutto8gpcs => dataoutto8gpcs,
pcs8gpldtxclk => pcs8gpldtxclk,
pcs8gpolinvtx => pcs8gpolinvtx,
pcs8grevloopbk => pcs8grevloopbk,
pcs8gwrenabletx => pcs8gwrenabletx,
pcs8grddisabletx => pcs8grddisabletx,
pcs8gphfifoursttx => pcs8gphfifoursttx,
pcs8gtxboundarysel => pcs8gtxboundarysel,
pcs8gtxdatavalid => pcs8gtxdatavalid,
pcs8gtxsynchdr => pcs8gtxsynchdr,
pcs8gtxblkstart => pcs8gtxblkstart,
pcsgen3txrstn => pcsgen3txrstn,
pldclkdiv33lc => pldclkdiv33lc,
emsippcstxclkout => emsippcstxclkout,
emsippcstxstatus => emsippcstxstatus,
pldtxpmarstbout => pldtxpmarstbout,
pldlccmurstbout => pldlccmurstbout,
pldtxlcplllock => pldtxlcplllock,
pldtxcmuplllock => pldtxcmuplllock,
pldtxiqclkout => pldtxiqclkout,
pcs10gextrain => pcs10gextrain,
pld10gtxfifodel => pld10gtxfifodel,
pldtxpmasyncpout => pldtxpmasyncpout,
pld10gtxfifoinsert => pld10gtxfifoinsert,
pld10gextraout => pld10gextraout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_10g_rx_pcs is
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
dis_signal_ok : string := "dis_signal_ok_dis";
gb_rx_idwidth : string := "idwidth_32";
gb_rx_odwidth : string := "odwidth_66";
bit_reverse : string := "bit_reverse_dis";
gb_sel_mode : string := "internal";
lpbk_mode : string := "lpbk_dis";
test_mode : string := "test_off";
blksync_bypass : string := "blksync_bypass_dis";
blksync_pipeln : string := "blksync_pipeln_dis";
blksync_knum_sh_cnt_prelock : string := "int";
blksync_knum_sh_cnt_postlock : string := "int";
blksync_enum_invalid_sh_cnt : string := "int";
blksync_bitslip_wait_cnt : string := "int";
bitslip_wait_cnt_user : string := "int";
blksync_bitslip_type : string := "bitslip_comb";
blksync_bitslip_wait_type : string := "bitslip_match";
dispchk_bypass : string := "dispchk_bypass_dis";
dispchk_rd_level : string := "dispchk_rd_level_min";
dispchk_rd_level_user : string := "int";
dispchk_pipeln : string := "dispchk_pipeln_dis";
descrm_bypass : string := "descrm_bypass_en";
descrm_mode : string := "async";
frmsync_bypass : string := "frmsync_bypass_dis";
frmsync_pipeln : string := "frmsync_pipeln_dis";
frmsync_mfrm_length : string := "int";
frmsync_mfrm_length_user : string := "int";
frmsync_knum_sync : string := "int";
frmsync_enum_sync : string := "int";
frmsync_enum_scrm : string := "int";
frmsync_flag_type : string := "all_framing_words";
dec_64b66b_10g_mode : string := "dec_64b66b_10g_mode_en";
dec_64b66b_rxsm_bypass : string := "dec_64b66b_rxsm_bypass_dis";
rx_sm_bypass : string := "rx_sm_bypass_dis";
rx_sm_pipeln : string := "rx_sm_pipeln_dis";
rx_sm_hiber : string := "rx_sm_hiber_en";
ber_xus_timer_window : string := "int";
ber_bit_err_total_cnt : string := "int";
crcchk_bypass : string := "crcchk_bypass_dis";
crcchk_pipeln : string := "crcchk_pipeln_dis";
crcflag_pipeln : string := "crcflag_pipeln_dis";
crcchk_init : string := "crcchk_init_user_setting";
crcchk_init_user : bit_vector := B"11111111111111111111111111111111";
crcchk_inv : string := "crcchk_inv_dis";
force_align : string := "force_align_dis";
align_del : string := "align_del_en";
control_del : bit_vector := B"11110000";
rxfifo_mode : string := "phase_comp";
master_clk_sel : string := "master_rx_pma_clk";
rd_clk_sel : string := "rd_rx_pma_clk";
gbexp_clken : string := "gbexp_clk_dis";
prbs_clken : string := "prbs_clk_dis";
blksync_clken : string := "blksync_clk_dis";
dispchk_clken : string := "dispchk_clk_dis";
descrm_clken : string := "descrm_clk_dis";
frmsync_clken : string := "frmsync_clk_dis";
dec64b66b_clken : string := "dec64b66b_clk_dis";
ber_clken : string := "ber_clk_dis";
rand_clken : string := "rand_clk_dis";
crcchk_clken : string := "crcchk_clk_dis";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
rxfifo_pempty : string := "pempty_default";
rxfifo_pfull : string := "pfull_default";
rxfifo_full : string := "full_default";
rxfifo_empty : string := "pempty_default";
bitslip_mode : string := "bitslip_dis";
fast_path : string := "fast_path_dis";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_rx_clk_out";
channel_number : integer := 0;
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
test_bus_mode : string := "tx"
);
port (
bercount : out std_logic_vector(5 downto 0);
errorblockcount : out std_logic_vector(7 downto 0);
pcsstatus : out std_logic_vector(0 downto 0);
randomerrorcount : out std_logic_vector(15 downto 0);
prbserrorlatch : out std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rxpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33txorrx : in std_logic_vector(0 downto 0);
rxpmadatavalid : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
rxpldclk : in std_logic_vector(0 downto 0);
rxpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
rxalignen : in std_logic_vector(0 downto 0);
rxalignclr : in std_logic_vector(0 downto 0);
rxrden : in std_logic_vector(0 downto 0);
rxdisparityclr : in std_logic_vector(0 downto 0);
rxclrerrorblockcount : in std_logic_vector(0 downto 0);
rxclrbercount : in std_logic_vector(0 downto 0);
rxbitslip : in std_logic_vector(0 downto 0);
rxprbserrorclr : in std_logic_vector(0 downto 0);
rxclkout : out std_logic_vector(0 downto 0);
rxclkiqout : out std_logic_vector(0 downto 0);
rxdatavalid : out std_logic_vector(0 downto 0);
rxfifoempty : out std_logic_vector(0 downto 0);
rxfifopartialempty : out std_logic_vector(0 downto 0);
rxfifopartialfull : out std_logic_vector(0 downto 0);
rxfifofull : out std_logic_vector(0 downto 0);
rxalignval : out std_logic_vector(0 downto 0);
rxblocklock : out std_logic_vector(0 downto 0);
rxsyncheadererror : out std_logic_vector(0 downto 0);
rxhighber : out std_logic_vector(0 downto 0);
rxframelock : out std_logic_vector(0 downto 0);
rxrdpossts : out std_logic_vector(0 downto 0);
rxrdnegsts : out std_logic_vector(0 downto 0);
rxskipinserted : out std_logic_vector(0 downto 0);
rxrxframe : out std_logic_vector(0 downto 0);
rxpayloadinserted : out std_logic_vector(0 downto 0);
rxsyncworderror : out std_logic_vector(0 downto 0);
rxscramblererror : out std_logic_vector(0 downto 0);
rxskipworderror : out std_logic_vector(0 downto 0);
rxdiagnosticerror : out std_logic_vector(0 downto 0);
rxmetaframeerror : out std_logic_vector(0 downto 0);
rxcrc32error : out std_logic_vector(0 downto 0);
rxdiagnosticstatus : out std_logic_vector(1 downto 0);
rxdata : out std_logic_vector(63 downto 0);
rxcontrol : out std_logic_vector(9 downto 0);
accumdisparity : out std_logic_vector(8 downto 0);
loopbackdatain : in std_logic_vector(39 downto 0);
rxpmadata : in std_logic_vector(39 downto 0);
rxtestdata : out std_logic_vector(19 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_10g_rx_pcs;
architecture behavior of stratixv_hssi_10g_rx_pcs is
component stratixv_hssi_10g_rx_pcs_encrypted
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
dis_signal_ok : string := "dis_signal_ok_dis";
gb_rx_idwidth : string := "idwidth_32";
gb_rx_odwidth : string := "odwidth_66";
bit_reverse : string := "bit_reverse_dis";
gb_sel_mode : string := "internal";
lpbk_mode : string := "lpbk_dis";
test_mode : string := "test_off";
blksync_bypass : string := "blksync_bypass_dis";
blksync_pipeln : string := "blksync_pipeln_dis";
blksync_knum_sh_cnt_prelock : string := "int";
blksync_knum_sh_cnt_postlock : string := "int";
blksync_enum_invalid_sh_cnt : string := "int";
blksync_bitslip_wait_cnt : string := "int";
bitslip_wait_cnt_user : string := "int";
blksync_bitslip_type : string := "bitslip_comb";
blksync_bitslip_wait_type : string := "bitslip_match";
dispchk_bypass : string := "dispchk_bypass_dis";
dispchk_rd_level : string := "dispchk_rd_level_min";
dispchk_rd_level_user : string := "int";
dispchk_pipeln : string := "dispchk_pipeln_dis";
descrm_bypass : string := "descrm_bypass_en";
descrm_mode : string := "async";
frmsync_bypass : string := "frmsync_bypass_dis";
frmsync_pipeln : string := "frmsync_pipeln_dis";
frmsync_mfrm_length : string := "int";
frmsync_mfrm_length_user : string := "int";
frmsync_knum_sync : string := "int";
frmsync_enum_sync : string := "int";
frmsync_enum_scrm : string := "int";
frmsync_flag_type : string := "all_framing_words";
dec_64b66b_10g_mode : string := "dec_64b66b_10g_mode_en";
dec_64b66b_rxsm_bypass : string := "dec_64b66b_rxsm_bypass_dis";
rx_sm_bypass : string := "rx_sm_bypass_dis";
rx_sm_pipeln : string := "rx_sm_pipeln_dis";
rx_sm_hiber : string := "rx_sm_hiber_en";
ber_xus_timer_window : string := "int";
ber_bit_err_total_cnt : string := "int";
crcchk_bypass : string := "crcchk_bypass_dis";
crcchk_pipeln : string := "crcchk_pipeln_dis";
crcflag_pipeln : string := "crcflag_pipeln_dis";
crcchk_init : string := "crcchk_init_user_setting";
crcchk_init_user : bit_vector := B"11111111111111111111111111111111";
crcchk_inv : string := "crcchk_inv_dis";
force_align : string := "force_align_dis";
align_del : string := "align_del_en";
control_del : bit_vector := B"11110000";
rxfifo_mode : string := "phase_comp";
master_clk_sel : string := "master_rx_pma_clk";
rd_clk_sel : string := "rd_rx_pma_clk";
gbexp_clken : string := "gbexp_clk_dis";
prbs_clken : string := "prbs_clk_dis";
blksync_clken : string := "blksync_clk_dis";
dispchk_clken : string := "dispchk_clk_dis";
descrm_clken : string := "descrm_clk_dis";
frmsync_clken : string := "frmsync_clk_dis";
dec64b66b_clken : string := "dec64b66b_clk_dis";
ber_clken : string := "ber_clk_dis";
rand_clken : string := "rand_clk_dis";
crcchk_clken : string := "crcchk_clk_dis";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
rxfifo_pempty : string := "pempty_default";
rxfifo_pfull : string := "pfull_default";
rxfifo_full : string := "full_default";
rxfifo_empty : string := "pempty_default";
bitslip_mode : string := "bitslip_dis";
fast_path : string := "fast_path_dis";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_rx_clk_out";
channel_number : integer := 0;
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
test_bus_mode : string := "tx"
);
port (
bercount : out std_logic_vector(5 downto 0);
errorblockcount : out std_logic_vector(7 downto 0);
pcsstatus : out std_logic_vector(0 downto 0);
randomerrorcount : out std_logic_vector(15 downto 0);
prbserrorlatch : out std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rxpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33txorrx : in std_logic_vector(0 downto 0);
rxpmadatavalid : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
rxpldclk : in std_logic_vector(0 downto 0);
rxpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
rxalignen : in std_logic_vector(0 downto 0);
rxalignclr : in std_logic_vector(0 downto 0);
rxrden : in std_logic_vector(0 downto 0);
rxdisparityclr : in std_logic_vector(0 downto 0);
rxclrerrorblockcount : in std_logic_vector(0 downto 0);
rxclrbercount : in std_logic_vector(0 downto 0);
rxbitslip : in std_logic_vector(0 downto 0);
rxprbserrorclr : in std_logic_vector(0 downto 0);
rxclkout : out std_logic_vector(0 downto 0);
rxclkiqout : out std_logic_vector(0 downto 0);
rxdatavalid : out std_logic_vector(0 downto 0);
rxfifoempty : out std_logic_vector(0 downto 0);
rxfifopartialempty : out std_logic_vector(0 downto 0);
rxfifopartialfull : out std_logic_vector(0 downto 0);
rxfifofull : out std_logic_vector(0 downto 0);
rxalignval : out std_logic_vector(0 downto 0);
rxblocklock : out std_logic_vector(0 downto 0);
rxsyncheadererror : out std_logic_vector(0 downto 0);
rxhighber : out std_logic_vector(0 downto 0);
rxframelock : out std_logic_vector(0 downto 0);
rxrdpossts : out std_logic_vector(0 downto 0);
rxrdnegsts : out std_logic_vector(0 downto 0);
rxskipinserted : out std_logic_vector(0 downto 0);
rxrxframe : out std_logic_vector(0 downto 0);
rxpayloadinserted : out std_logic_vector(0 downto 0);
rxsyncworderror : out std_logic_vector(0 downto 0);
rxscramblererror : out std_logic_vector(0 downto 0);
rxskipworderror : out std_logic_vector(0 downto 0);
rxdiagnosticerror : out std_logic_vector(0 downto 0);
rxmetaframeerror : out std_logic_vector(0 downto 0);
rxcrc32error : out std_logic_vector(0 downto 0);
rxdiagnosticstatus : out std_logic_vector(1 downto 0);
rxdata : out std_logic_vector(63 downto 0);
rxcontrol : out std_logic_vector(9 downto 0);
accumdisparity : out std_logic_vector(8 downto 0);
loopbackdatain : in std_logic_vector(39 downto 0);
rxpmadata : in std_logic_vector(39 downto 0);
rxtestdata : out std_logic_vector(19 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_10g_rx_pcs_encrypted
generic map (
prot_mode => prot_mode,
sup_mode => sup_mode,
dis_signal_ok => dis_signal_ok,
gb_rx_idwidth => gb_rx_idwidth,
gb_rx_odwidth => gb_rx_odwidth,
bit_reverse => bit_reverse,
gb_sel_mode => gb_sel_mode,
lpbk_mode => lpbk_mode,
test_mode => test_mode,
blksync_bypass => blksync_bypass,
blksync_pipeln => blksync_pipeln,
blksync_knum_sh_cnt_prelock => blksync_knum_sh_cnt_prelock,
blksync_knum_sh_cnt_postlock => blksync_knum_sh_cnt_postlock,
blksync_enum_invalid_sh_cnt => blksync_enum_invalid_sh_cnt,
blksync_bitslip_wait_cnt => blksync_bitslip_wait_cnt,
bitslip_wait_cnt_user => bitslip_wait_cnt_user,
blksync_bitslip_type => blksync_bitslip_type,
blksync_bitslip_wait_type => blksync_bitslip_wait_type,
dispchk_bypass => dispchk_bypass,
dispchk_rd_level => dispchk_rd_level,
dispchk_rd_level_user => dispchk_rd_level_user,
dispchk_pipeln => dispchk_pipeln,
descrm_bypass => descrm_bypass,
descrm_mode => descrm_mode,
frmsync_bypass => frmsync_bypass,
frmsync_pipeln => frmsync_pipeln,
frmsync_mfrm_length => frmsync_mfrm_length,
frmsync_mfrm_length_user => frmsync_mfrm_length_user,
frmsync_knum_sync => frmsync_knum_sync,
frmsync_enum_sync => frmsync_enum_sync,
frmsync_enum_scrm => frmsync_enum_scrm,
frmsync_flag_type => frmsync_flag_type,
dec_64b66b_10g_mode => dec_64b66b_10g_mode,
dec_64b66b_rxsm_bypass => dec_64b66b_rxsm_bypass,
rx_sm_bypass => rx_sm_bypass,
rx_sm_pipeln => rx_sm_pipeln,
rx_sm_hiber => rx_sm_hiber,
ber_xus_timer_window => ber_xus_timer_window,
ber_bit_err_total_cnt => ber_bit_err_total_cnt,
crcchk_bypass => crcchk_bypass,
crcchk_pipeln => crcchk_pipeln,
crcflag_pipeln => crcflag_pipeln,
crcchk_init => crcchk_init,
crcchk_init_user => crcchk_init_user,
crcchk_inv => crcchk_inv,
force_align => force_align,
align_del => align_del,
control_del => control_del,
rxfifo_mode => rxfifo_mode,
master_clk_sel => master_clk_sel,
rd_clk_sel => rd_clk_sel,
gbexp_clken => gbexp_clken,
prbs_clken => prbs_clken,
blksync_clken => blksync_clken,
dispchk_clken => dispchk_clken,
descrm_clken => descrm_clken,
frmsync_clken => frmsync_clken,
dec64b66b_clken => dec64b66b_clken,
ber_clken => ber_clken,
rand_clken => rand_clken,
crcchk_clken => crcchk_clken,
wrfifo_clken => wrfifo_clken,
rdfifo_clken => rdfifo_clken,
rxfifo_pempty => rxfifo_pempty,
rxfifo_pfull => rxfifo_pfull,
rxfifo_full => rxfifo_full,
rxfifo_empty => rxfifo_empty,
bitslip_mode => bitslip_mode,
fast_path => fast_path,
stretch_num_stages => stretch_num_stages,
stretch_en => stretch_en,
iqtxrx_clkout_sel => iqtxrx_clkout_sel,
channel_number => channel_number,
frmgen_diag_word => frmgen_diag_word,
frmgen_scrm_word => frmgen_scrm_word,
frmgen_skip_word => frmgen_skip_word,
frmgen_sync_word => frmgen_sync_word,
test_bus_mode => test_bus_mode
)
port map (
bercount => bercount,
errorblockcount => errorblockcount,
pcsstatus => pcsstatus,
randomerrorcount => randomerrorcount,
prbserrorlatch => prbserrorlatch,
txpmaclk => txpmaclk,
rxpmaclk => rxpmaclk,
pmaclkdiv33txorrx => pmaclkdiv33txorrx,
rxpmadatavalid => rxpmadatavalid,
hardresetn => hardresetn,
rxpldclk => rxpldclk,
rxpldrstn => rxpldrstn,
refclkdig => refclkdig,
rxalignen => rxalignen,
rxalignclr => rxalignclr,
rxrden => rxrden,
rxdisparityclr => rxdisparityclr,
rxclrerrorblockcount => rxclrerrorblockcount,
rxclrbercount => rxclrbercount,
rxbitslip => rxbitslip,
rxprbserrorclr => rxprbserrorclr,
rxclkout => rxclkout,
rxclkiqout => rxclkiqout,
rxdatavalid => rxdatavalid,
rxfifoempty => rxfifoempty,
rxfifopartialempty => rxfifopartialempty,
rxfifopartialfull => rxfifopartialfull,
rxfifofull => rxfifofull,
rxalignval => rxalignval,
rxblocklock => rxblocklock,
rxsyncheadererror => rxsyncheadererror,
rxhighber => rxhighber,
rxframelock => rxframelock,
rxrdpossts => rxrdpossts,
rxrdnegsts => rxrdnegsts,
rxskipinserted => rxskipinserted,
rxrxframe => rxrxframe,
rxpayloadinserted => rxpayloadinserted,
rxsyncworderror => rxsyncworderror,
rxscramblererror => rxscramblererror,
rxskipworderror => rxskipworderror,
rxdiagnosticerror => rxdiagnosticerror,
rxmetaframeerror => rxmetaframeerror,
rxcrc32error => rxcrc32error,
rxdiagnosticstatus => rxdiagnosticstatus,
rxdata => rxdata,
rxcontrol => rxcontrol,
accumdisparity => accumdisparity,
loopbackdatain => loopbackdatain,
rxpmadata => rxpmadata,
rxtestdata => rxtestdata,
syncdatain => syncdatain
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_10g_tx_pcs is
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
ctrl_plane_bonding : string := "individual";
master_clk_sel : string := "master_tx_pma_clk";
wr_clk_sel : string := "wr_tx_pma_clk";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
frmgen_clken : string := "frmgen_clk_dis";
crcgen_clken : string := "crcgen_clk_dis";
enc64b66b_txsm_clken : string := "enc64b66b_txsm_clk_dis";
scrm_clken : string := "scrm_clk_dis";
dispgen_clken : string := "dispgen_clk_dis";
prbs_clken : string := "prbs_clk_dis";
sqwgen_clken : string := "sqwgen_clk_dis";
gbred_clken : string := "gbred_clk_dis";
gb_tx_idwidth : string := "idwidth_50";
gb_tx_odwidth : string := "odwidth_32";
txfifo_mode : string := "phase_comp";
txfifo_pempty : string := "pempty_default";
txfifo_pfull : string := "pfull_default";
txfifo_empty : string := "empty_default";
txfifo_full : string := "full_default";
frmgen_bypass : string := "frmgen_bypass_dis";
frmgen_pipeln : string := "frmgen_pipeln_dis";
frmgen_mfrm_length : string := "frmgen_mfrm_length_min";
frmgen_mfrm_length_user : string := "int";
frmgen_pyld_ins : string := "frmgen_pyld_ins_dis";
sh_err : string := "sh_err_dis";
frmgen_burst : string := "frmgen_burst_dis";
frmgen_wordslip : string := "frmgen_wordslip_dis";
crcgen_bypass : string := "crcgen_bypass_dis";
crcgen_init : string := "crcgen_init_user_setting";
crcgen_init_user : bit_vector := B"11111111111111111111111111111111";
crcgen_inv : string := "crcgen_inv_dis";
crcgen_err : string := "crcgen_err_dis";
enc_64b66b_10g_mode : string := "enc_64b66b_10g_mode_en";
enc_64b66b_txsm_bypass : string := "enc_64b66b_txsm_bypass_dis";
tx_sm_bypass : string := "tx_sm_bypass_dis";
tx_sm_pipeln : string := "tx_sm_pipeln_dis";
scrm_bypass : string := "scrm_bypass_dis";
test_mode : string := "test_off";
pseudo_random : string := "all_0";
pseudo_seed_a : string := "pseudo_seed_a_user_setting";
pseudo_seed_a_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
pseudo_seed_b : string := "pseudo_seed_b_user_setting";
pseudo_seed_b_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
bit_reverse : string := "bit_reverse_dis";
scrm_seed : string := "scram_seed_user_setting";
scrm_seed_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
scrm_mode : string := "async";
dispgen_bypass : string := "dispgen_bypass_dis";
dispgen_err : string := "dispgen_err_dis";
dispgen_pipeln : string := "dispgen_pipeln_dis";
gb_sel_mode : string := "internal";
sq_wave : string := "sq_wave_4";
bitslip_en : string := "bitslip_dis";
fastpath : string := "fastpath_dis";
distup_bypass_pipeln : string := "distup_bypass_pipeln_dis";
distup_master : string := "distup_master_en";
distdwn_bypass_pipeln : string := "distdwn_bypass_pipeln_dis";
distdwn_master : string := "distdwn_master_en";
compin_sel : string := "compin_master";
comp_cnt : string := "comp_cnt_00";
indv : string := "indv_en";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_tx_pma_clk";
channel_number : integer := 0;
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
test_bus_mode : string := "tx";
lpm_type : string := "stratixv_hssi_10g_tx_pcs"
);
port (
txpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33lc : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
txpldclk : in std_logic_vector(0 downto 0);
txpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txdatavalid : in std_logic_vector(0 downto 0);
txbitslip : in std_logic_vector(6 downto 0);
txdiagnosticstatus : in std_logic_vector(1 downto 0);
txwordslip : in std_logic_vector(0 downto 0);
txbursten : in std_logic_vector(0 downto 0);
txdisparityclr : in std_logic_vector(0 downto 0);
txclkout : out std_logic_vector(0 downto 0);
txclkiqout : out std_logic_vector(0 downto 0);
txfifoempty : out std_logic_vector(0 downto 0);
txfifopartialempty : out std_logic_vector(0 downto 0);
txfifopartialfull : out std_logic_vector(0 downto 0);
txfifofull : out std_logic_vector(0 downto 0);
txframe : out std_logic_vector(0 downto 0);
txburstenexe : out std_logic_vector(0 downto 0);
txwordslipexe : out std_logic_vector(0 downto 0);
distupindv : in std_logic_vector(0 downto 0);
distdwnindv : in std_logic_vector(0 downto 0);
distupinwren : in std_logic_vector(0 downto 0);
distdwninwren : in std_logic_vector(0 downto 0);
distupinrden : in std_logic_vector(0 downto 0);
distdwninrden : in std_logic_vector(0 downto 0);
distupoutdv : out std_logic_vector(0 downto 0);
distdwnoutdv : out std_logic_vector(0 downto 0);
distupoutwren : out std_logic_vector(0 downto 0);
distdwnoutwren : out std_logic_vector(0 downto 0);
distupoutrden : out std_logic_vector(0 downto 0);
distdwnoutrden : out std_logic_vector(0 downto 0);
txtestdata : out std_logic_vector(19 downto 0);
txdata : in std_logic_vector(63 downto 0);
txcontrol : in std_logic_vector(8 downto 0);
loopbackdataout : out std_logic_vector(39 downto 0);
txpmadata : out std_logic_vector(39 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_10g_tx_pcs;
architecture behavior of stratixv_hssi_10g_tx_pcs is
component stratixv_hssi_10g_tx_pcs_encrypted
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
ctrl_plane_bonding : string := "individual";
master_clk_sel : string := "master_tx_pma_clk";
wr_clk_sel : string := "wr_tx_pma_clk";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
frmgen_clken : string := "frmgen_clk_dis";
crcgen_clken : string := "crcgen_clk_dis";
enc64b66b_txsm_clken : string := "enc64b66b_txsm_clk_dis";
scrm_clken : string := "scrm_clk_dis";
dispgen_clken : string := "dispgen_clk_dis";
prbs_clken : string := "prbs_clk_dis";
sqwgen_clken : string := "sqwgen_clk_dis";
gbred_clken : string := "gbred_clk_dis";
gb_tx_idwidth : string := "idwidth_50";
gb_tx_odwidth : string := "odwidth_32";
txfifo_mode : string := "phase_comp";
txfifo_pempty : string := "pempty_default";
txfifo_pfull : string := "pfull_default";
txfifo_empty : string := "empty_default";
txfifo_full : string := "full_default";
frmgen_bypass : string := "frmgen_bypass_dis";
frmgen_pipeln : string := "frmgen_pipeln_dis";
frmgen_mfrm_length : string := "frmgen_mfrm_length_min";
frmgen_mfrm_length_user : string := "int";
frmgen_pyld_ins : string := "frmgen_pyld_ins_dis";
sh_err : string := "sh_err_dis";
frmgen_burst : string := "frmgen_burst_dis";
frmgen_wordslip : string := "frmgen_wordslip_dis";
crcgen_bypass : string := "crcgen_bypass_dis";
crcgen_init : string := "crcgen_init_user_setting";
crcgen_init_user : bit_vector := B"11111111111111111111111111111111";
crcgen_inv : string := "crcgen_inv_dis";
crcgen_err : string := "crcgen_err_dis";
enc_64b66b_10g_mode : string := "enc_64b66b_10g_mode_en";
enc_64b66b_txsm_bypass : string := "enc_64b66b_txsm_bypass_dis";
tx_sm_bypass : string := "tx_sm_bypass_dis";
tx_sm_pipeln : string := "tx_sm_pipeln_dis";
scrm_bypass : string := "scrm_bypass_dis";
test_mode : string := "test_off";
pseudo_random : string := "all_0";
pseudo_seed_a : string := "pseudo_seed_a_user_setting";
pseudo_seed_a_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
pseudo_seed_b : string := "pseudo_seed_b_user_setting";
pseudo_seed_b_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
bit_reverse : string := "bit_reverse_dis";
scrm_seed : string := "scram_seed_user_setting";
scrm_seed_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
scrm_mode : string := "async";
dispgen_bypass : string := "dispgen_bypass_dis";
dispgen_err : string := "dispgen_err_dis";
dispgen_pipeln : string := "dispgen_pipeln_dis";
gb_sel_mode : string := "internal";
sq_wave : string := "sq_wave_4";
bitslip_en : string := "bitslip_dis";
fastpath : string := "fastpath_dis";
distup_bypass_pipeln : string := "distup_bypass_pipeln_dis";
distup_master : string := "distup_master_en";
distdwn_bypass_pipeln : string := "distdwn_bypass_pipeln_dis";
distdwn_master : string := "distdwn_master_en";
compin_sel : string := "compin_master";
comp_cnt : string := "comp_cnt_00";
indv : string := "indv_en";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_tx_pma_clk";
channel_number : integer := 0;
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
test_bus_mode : string := "tx";
lpm_type : string := "stratixv_hssi_10g_tx_pcs"
);
port (
txpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33lc : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
txpldclk : in std_logic_vector(0 downto 0);
txpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txdatavalid : in std_logic_vector(0 downto 0);
txbitslip : in std_logic_vector(6 downto 0);
txdiagnosticstatus : in std_logic_vector(1 downto 0);
txwordslip : in std_logic_vector(0 downto 0);
txbursten : in std_logic_vector(0 downto 0);
txdisparityclr : in std_logic_vector(0 downto 0);
txclkout : out std_logic_vector(0 downto 0);
txclkiqout : out std_logic_vector(0 downto 0);
txfifoempty : out std_logic_vector(0 downto 0);
txfifopartialempty : out std_logic_vector(0 downto 0);
txfifopartialfull : out std_logic_vector(0 downto 0);
txfifofull : out std_logic_vector(0 downto 0);
txframe : out std_logic_vector(0 downto 0);
txburstenexe : out std_logic_vector(0 downto 0);
txwordslipexe : out std_logic_vector(0 downto 0);
distupindv : in std_logic_vector(0 downto 0);
distdwnindv : in std_logic_vector(0 downto 0);
distupinwren : in std_logic_vector(0 downto 0);
distdwninwren : in std_logic_vector(0 downto 0);
distupinrden : in std_logic_vector(0 downto 0);
distdwninrden : in std_logic_vector(0 downto 0);
distupoutdv : out std_logic_vector(0 downto 0);
distdwnoutdv : out std_logic_vector(0 downto 0);
distupoutwren : out std_logic_vector(0 downto 0);
distdwnoutwren : out std_logic_vector(0 downto 0);
distupoutrden : out std_logic_vector(0 downto 0);
distdwnoutrden : out std_logic_vector(0 downto 0);
txtestdata : out std_logic_vector(19 downto 0);
txdata : in std_logic_vector(63 downto 0);
txcontrol : in std_logic_vector(8 downto 0);
loopbackdataout : out std_logic_vector(39 downto 0);
txpmadata : out std_logic_vector(39 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_10g_tx_pcs_encrypted
generic map (
prot_mode => prot_mode,
sup_mode => sup_mode,
ctrl_plane_bonding => ctrl_plane_bonding,
master_clk_sel => master_clk_sel,
wr_clk_sel => wr_clk_sel,
wrfifo_clken => wrfifo_clken,
rdfifo_clken => rdfifo_clken,
frmgen_clken => frmgen_clken,
crcgen_clken => crcgen_clken,
enc64b66b_txsm_clken => enc64b66b_txsm_clken,
scrm_clken => scrm_clken,
dispgen_clken => dispgen_clken,
prbs_clken => prbs_clken,
sqwgen_clken => sqwgen_clken,
gbred_clken => gbred_clken,
gb_tx_idwidth => gb_tx_idwidth,
gb_tx_odwidth => gb_tx_odwidth,
txfifo_mode => txfifo_mode,
txfifo_pempty => txfifo_pempty,
txfifo_pfull => txfifo_pfull,
txfifo_empty => txfifo_empty,
txfifo_full => txfifo_full,
frmgen_bypass => frmgen_bypass,
frmgen_pipeln => frmgen_pipeln,
frmgen_mfrm_length => frmgen_mfrm_length,
frmgen_mfrm_length_user => frmgen_mfrm_length_user,
frmgen_pyld_ins => frmgen_pyld_ins,
sh_err => sh_err,
frmgen_burst => frmgen_burst,
frmgen_wordslip => frmgen_wordslip,
crcgen_bypass => crcgen_bypass,
crcgen_init => crcgen_init,
crcgen_init_user => crcgen_init_user,
crcgen_inv => crcgen_inv,
crcgen_err => crcgen_err,
enc_64b66b_10g_mode => enc_64b66b_10g_mode,
enc_64b66b_txsm_bypass => enc_64b66b_txsm_bypass,
tx_sm_bypass => tx_sm_bypass,
tx_sm_pipeln => tx_sm_pipeln,
scrm_bypass => scrm_bypass,
test_mode => test_mode,
pseudo_random => pseudo_random,
pseudo_seed_a => pseudo_seed_a,
pseudo_seed_a_user => pseudo_seed_a_user,
pseudo_seed_b => pseudo_seed_b,
pseudo_seed_b_user => pseudo_seed_b_user,
bit_reverse => bit_reverse,
scrm_seed => scrm_seed,
scrm_seed_user => scrm_seed_user,
scrm_mode => scrm_mode,
dispgen_bypass => dispgen_bypass,
dispgen_err => dispgen_err,
dispgen_pipeln => dispgen_pipeln,
gb_sel_mode => gb_sel_mode,
sq_wave => sq_wave,
bitslip_en => bitslip_en,
fastpath => fastpath,
distup_bypass_pipeln => distup_bypass_pipeln,
distup_master => distup_master,
distdwn_bypass_pipeln => distdwn_bypass_pipeln,
distdwn_master => distdwn_master,
compin_sel => compin_sel,
comp_cnt => comp_cnt,
indv => indv,
stretch_num_stages => stretch_num_stages,
stretch_en => stretch_en,
iqtxrx_clkout_sel => iqtxrx_clkout_sel,
channel_number => channel_number,
frmgen_sync_word => frmgen_sync_word,
frmgen_scrm_word => frmgen_scrm_word,
frmgen_skip_word => frmgen_skip_word,
frmgen_diag_word => frmgen_diag_word,
test_bus_mode => test_bus_mode,
lpm_type => lpm_type
)
port map (
txpmaclk => txpmaclk,
pmaclkdiv33lc => pmaclkdiv33lc,
hardresetn => hardresetn,
txpldclk => txpldclk,
txpldrstn => txpldrstn,
refclkdig => refclkdig,
txdatavalid => txdatavalid,
txbitslip => txbitslip,
txdiagnosticstatus => txdiagnosticstatus,
txwordslip => txwordslip,
txbursten => txbursten,
txdisparityclr => txdisparityclr,
txclkout => txclkout,
txclkiqout => txclkiqout,
txfifoempty => txfifoempty,
txfifopartialempty => txfifopartialempty,
txfifopartialfull => txfifopartialfull,
txfifofull => txfifofull,
txframe => txframe,
txburstenexe => txburstenexe,
txwordslipexe => txwordslipexe,
distupindv => distupindv,
distdwnindv => distdwnindv,
distupinwren => distupinwren,
distdwninwren => distdwninwren,
distupinrden => distupinrden,
distdwninrden => distdwninrden,
distupoutdv => distupoutdv,
distdwnoutdv => distdwnoutdv,
distupoutwren => distupoutwren,
distdwnoutwren => distdwnoutwren,
distupoutrden => distupoutrden,
distdwnoutrden => distdwnoutrden,
txtestdata => txtestdata,
txdata => txdata,
txcontrol => txcontrol,
loopbackdataout => loopbackdataout,
txpmadata => txpmadata,
syncdatain => syncdatain
);
end behavior;
------------------------------------------------------------------------------------
-- This is the HSSI Simulation Atom Model Encryption wrapper for the AVMM Interface
-- Entity Name : stratixv_hssi_avmm_interface
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_avmm_interface is
generic (
num_ch0_atoms : integer := 0;
num_ch1_atoms : integer := 0;
num_ch2_atoms : integer := 0
);
port (
avmmrstn : in std_logic_vector(0 downto 0);
avmmclk : in std_logic_vector(0 downto 0);
avmmwrite : in std_logic_vector(0 downto 0);
avmmread : in std_logic_vector(0 downto 0);
avmmbyteen : in std_logic_vector(1 downto 0);
avmmaddress : in std_logic_vector(10 downto 0);
avmmwritedata : in std_logic_vector(15 downto 0);
blockselect : in std_logic_vector(90-1 downto 0);
readdatachnl : in std_logic_vector(90*16-1 downto 0);
avmmreaddata : out std_logic_vector(15 downto 0);
clkchnl : out std_logic_vector(0 downto 0);
rstnchnl : out std_logic_vector(0 downto 0);
writedatachnl : out std_logic_vector(15 downto 0);
regaddrchnl : out std_logic_vector(10 downto 0);
writechnl : out std_logic_vector(0 downto 0);
readchnl : out std_logic_vector(0 downto 0);
byteenchnl : out std_logic_vector(1 downto 0);
-- The following ports are not modelled. They exist to match the avmm interface atom interface
refclkdig : in std_logic_vector(0 downto 0);
avmmreservedin : in std_logic_vector(0 downto 0);
avmmreservedout : out std_logic_vector(0 downto 0);
dpriorstntop : out std_logic_vector(0 downto 0);
dprioclktop : out std_logic_vector(0 downto 0);
mdiodistopchnl : out std_logic_vector(0 downto 0);
dpriorstnmid : out std_logic_vector(0 downto 0);
dprioclkmid : out std_logic_vector(0 downto 0);
mdiodismidchnl : out std_logic_vector(0 downto 0);
dpriorstnbot : out std_logic_vector(0 downto 0);
dprioclkbot : out std_logic_vector(0 downto 0);
mdiodisbotchnl : out std_logic_vector(0 downto 0);
dpriotestsitopchnl : out std_logic_vector(3 downto 0);
dpriotestsimidchnl : out std_logic_vector(3 downto 0);
dpriotestsibotchnl : out std_logic_vector(3 downto 0);
-- The following ports belong to pm_adce and pm_tst_mux blocks in the PMA
pmatestbus : out std_logic_vector(23 downto 0);
pmatestbussel : in std_logic_vector(11 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
interfacesel : in std_logic_vector(0 downto 0);
sershiftload : in std_logic_vector(0 downto 0)
);
end stratixv_hssi_avmm_interface;
architecture behavior of stratixv_hssi_avmm_interface is
component stratixv_hssi_avmm_interface_encrypted
generic (
num_ch0_atoms : integer := 0;
num_ch1_atoms : integer := 0;
num_ch2_atoms : integer := 0
);
port (
avmmrstn : in std_logic_vector(0 downto 0);
avmmclk : in std_logic_vector(0 downto 0);
avmmwrite : in std_logic_vector(0 downto 0);
avmmread : in std_logic_vector(0 downto 0);
avmmbyteen : in std_logic_vector(1 downto 0);
avmmaddress : in std_logic_vector(10 downto 0);
avmmwritedata : in std_logic_vector(15 downto 0);
blockselect : in std_logic_vector(90-1 downto 0);
readdatachnl : in std_logic_vector(90*16-1 downto 0);
avmmreaddata : out std_logic_vector(15 downto 0);
clkchnl : out std_logic_vector(0 downto 0);
rstnchnl : out std_logic_vector(0 downto 0);
writedatachnl : out std_logic_vector(15 downto 0);
regaddrchnl : out std_logic_vector(10 downto 0);
writechnl : out std_logic_vector(0 downto 0);
readchnl : out std_logic_vector(0 downto 0);
byteenchnl : out std_logic_vector(1 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
avmmreservedin : in std_logic_vector(0 downto 0);
avmmreservedout : out std_logic_vector(0 downto 0);
dpriorstntop : out std_logic_vector(0 downto 0);
dprioclktop : out std_logic_vector(0 downto 0);
mdiodistopchnl : out std_logic_vector(0 downto 0);
dpriorstnmid : out std_logic_vector(0 downto 0);
dprioclkmid : out std_logic_vector(0 downto 0);
mdiodismidchnl : out std_logic_vector(0 downto 0);
dpriorstnbot : out std_logic_vector(0 downto 0);
dprioclkbot : out std_logic_vector(0 downto 0);
mdiodisbotchnl : out std_logic_vector(0 downto 0);
dpriotestsitopchnl : out std_logic_vector(3 downto 0);
dpriotestsimidchnl : out std_logic_vector(3 downto 0);
dpriotestsibotchnl : out std_logic_vector(3 downto 0);
pmatestbus : out std_logic_vector(23 downto 0);
pmatestbussel : in std_logic_vector(11 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
interfacesel : in std_logic_vector(0 downto 0);
sershiftload : in std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_avmm_interface_encrypted
generic map (
num_ch0_atoms => num_ch0_atoms,
num_ch1_atoms => num_ch1_atoms,
num_ch2_atoms => num_ch2_atoms
)
port map (
avmmrstn => avmmrstn ,
avmmclk => avmmclk ,
avmmwrite => avmmwrite ,
avmmread => avmmread ,
avmmbyteen => avmmbyteen ,
avmmaddress => avmmaddress ,
avmmwritedata => avmmwritedata ,
blockselect => blockselect ,
readdatachnl => readdatachnl ,
avmmreaddata => avmmreaddata ,
clkchnl => clkchnl ,
rstnchnl => rstnchnl ,
writedatachnl => writedatachnl ,
regaddrchnl => regaddrchnl ,
writechnl => writechnl ,
readchnl => readchnl ,
byteenchnl => byteenchnl ,
refclkdig => refclkdig ,
avmmreservedin => avmmreservedin ,
avmmreservedout => avmmreservedout ,
dpriorstntop => dpriorstntop ,
dprioclktop => dprioclktop ,
mdiodistopchnl => mdiodistopchnl ,
dpriorstnmid => dpriorstnmid ,
dprioclkmid => dprioclkmid ,
mdiodismidchnl => mdiodismidchnl ,
dpriorstnbot => dpriorstnbot ,
dprioclkbot => dprioclkbot ,
mdiodisbotchnl => mdiodisbotchnl ,
dpriotestsitopchnl => dpriotestsitopchnl ,
dpriotestsimidchnl => dpriotestsimidchnl ,
dpriotestsibotchnl => dpriotestsibotchnl ,
pmatestbus => pmatestbus ,
pmatestbussel => pmatestbussel ,
scanmoden => scanmoden ,
scanshiftn => scanshiftn ,
interfacesel => interfacesel ,
sershiftload => sershiftload
);
end behavior;
| gpl-3.0 | 0f97fde324282d380563686c39ec145a | 0.537878 | 3.279931 | false | false | false | false |
alvieboy/xtc-base | sim.vhd | 1 | 3,086 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package sim is
procedure hexread(L : inout line; value:out bit_vector);
procedure hexread(L : inout line; value:out std_logic_vector);
function ishex(c : character) return boolean;
end package;
package body sim is
procedure char2hex(C: character; result: out bit_vector(3 downto 0);
good: out boolean; report_error: in boolean) is
begin
good := true;
case C is
when '0' => result := x"0";
when '1' => result := x"1";
when '2' => result := X"2";
when '3' => result := X"3";
when '4' => result := X"4";
when '5' => result := X"5";
when '6' => result := X"6";
when '7' => result := X"7";
when '8' => result := X"8";
when '9' => result := X"9";
when 'A' => result := X"A";
when 'B' => result := X"B";
when 'C' => result := X"C";
when 'D' => result := X"D";
when 'E' => result := X"E";
when 'F' => result := X"F";
when 'a' => result := X"A";
when 'b' => result := X"B";
when 'c' => result := X"C";
when 'd' => result := X"D";
when 'e' => result := X"E";
when 'f' => result := X"F";
when others =>
if report_error then
assert false report
"hexread error: read a '" & C & "', expected a hex character (0-F).";
end if;
good := false;
end case;
end;
procedure hexread(L:inout line; value:out bit_vector) is
variable OK: boolean;
variable C: character;
constant NE: integer := value'length/4; --'
variable BV: bit_vector(0 to value'length-1); --'
variable S: string(1 to NE-1);
begin
if value'length mod 4 /= 0 then --'
assert false report
"hexread Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(L,C);
exit when ((C /= ' ') and (C /= CR) and (C /= HT));
end loop;
char2hex(C, BV(0 to 3), OK, false);
if not OK then
return;
end if;
read(L, S, OK);
-- if not OK then
-- assert false report "hexread Error: Failed to read the STRING";
-- return;
-- end if;
for I in 1 to NE-1 loop
char2hex(S(I), BV(4*I to 4*I+3), OK, false);
if not OK then
return;
end if;
end loop;
value := BV;
end hexread;
procedure hexread(L:inout line; value:out std_ulogic_vector) is
variable tmp: bit_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := TO_X01(tmp);
end hexread;
procedure hexread(L:inout line; value:out std_logic_vector) is
variable tmp: std_ulogic_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := std_logic_vector(tmp);
end hexread;
function ishex(c:character) return boolean is
variable tmp : bit_vector(3 downto 0);
variable OK : boolean;
begin
char2hex(C, tmp, OK, false);
return OK;
end ishex;
end ; | bsd-3-clause | 2742126d1c05d142bf760c013a9e1894 | 0.536941 | 3.22466 | false | false | false | false |
alvieboy/xtc-base | decode.vhd | 1 | 7,753 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity decode is
port (
clk: in std_logic;
rst: in std_logic;
-- Input for previous stages
fui: in fetch_output_type;
-- Output for next stages
duo: out decode_output_type;
busy: out std_logic;
freeze: in std_logic;
flush: in std_logic;
jump: in std_logic;
dual: out std_logic;
jumpmsb: in std_logic
);
end entity decode;
architecture behave of decode is
signal dr: decode_regs_type;
signal dec: opdec_type;
signal opcode_high: std_logic_vector(15 downto 0);
signal opcode_low: std_logic_vector(15 downto 0);
-- signal pc_lsb: boolean;
begin
opcode_high <= fui.opcode(31 downto 16) when fui.inverted='0' else fui.opcode(15 downto 0);
opcode_low <= fui.opcode(15 downto 0) when fui.inverted='0' else fui.opcode(31 downto 16);
duo.r <= dr;
opdecoder: entity work.opdec
port map (
opcode_high => opcode_high,
opcode_low => opcode_low,
priv => fui.r.priv,
dec => dec
);
process(fui, dr, clk, rst, dec, freeze, jump, jumpmsb, flush, opcode_high,opcode_low)
variable dw: decode_regs_type;
--variable op: decoded_opcode_type;
variable opc1,opc2: std_logic_vector(15 downto 0);
variable rd1,rd2: std_logic;
variable ra1,ra2: regaddress_type;
--variable src: sourcedest_type;
variable dreg0, dreg1: regaddress_type;
variable alu_op: alu_op_type;
variable imm16: std_logic_vector(15 downto 0);
variable imm8: std_logic_vector(7 downto 0);
variable imm_fill: std_logic_vector(31 downto 0);
variable sr: std_logic_vector(2 downto 0);
variable opcdelta: std_logic_vector(2 downto 0);
variable can_issue_both: boolean;
--variable is_pc_lsb: boolean;
variable reg_source0, reg_source1: reg_source_type;
variable regwe :std_logic;
variable sprwe: std_logic;
variable prepost: std_logic;
variable macc: memory_access_type;
variable memory_access: std_logic;
variable memory_write: std_logic;
variable modify_flags: boolean;
--variable compositeloadimm: compositeloadimmtype;
variable jump: std_logic_vector(1 downto 0);
variable condition_clause: condition_type;
variable alu2_imreg: std_logic;
variable alu2_samereg: std_logic;
--variable no_reg_conflict: boolean;
--variable flags_source: flagssource_type;
variable pc: word_type;
variable imflag: std_logic;
variable invert_alu: boolean;
variable except_return: boolean;
variable blocks1: std_logic;
variable blocks2: std_logic;
variable is_jump: boolean;
begin
dw := dr;
busy <= '0';
dual <= '0';
rd1 := '0';
rd2 := '0';
--can_issue_both := false;
modify_flags:=false;
jump := (others => 'X');
--jump_clause := JUMP_NONE;
--no_reg_conflict := true;
imflag := '0';
-- TODO: save power, only enable RB that need..
rd1 := dec.rd1;
rd2 := dec.rd2;
ra1 := dec.sreg1;
ra2 := dec.sreg2; -- Preload DREG for some insns
imm16 := dec.imm8h & dec.imm8l;
imm8 := dec.imm8l;
pc := fui.r.pc;
sr := dec.sr;
jump := dec.jump;
--condition_clause := dec.condition;
except_return:=dec.except_return;
dw.cop_id := dec.cop_id;
dw.cop_reg := dec.cop_reg;
alu_op := dec.alu_op;
reg_source0 := dec.reg_source;
reg_source1 := dec.reg_source;
dreg0 := dec.dreg;
dreg1 := dec.dreg;
blocks1 := dec.blocks;
blocks2 := dec.blocks;
macc := dec.macc;
memory_access := dec.memory_access;
memory_write := dec.memory_write;
modify_flags := dec.modify_flags;
if dec.modify_gpr then
regwe:='1';
else
regwe:='0';
end if;
if dec.modify_spr then
sprwe :='1';
else
sprwe :='0';
end if;
imflag := dec.imflag;
if freeze='0' then
dw.valid := fui.valid;
end if;
if fui.valid='1' and freeze='0' then
dw.rd1 := rd1;
dw.rd2 := rd2;
dw.sra1 := ra1;
dw.sra2 := ra2;
dw.sprwe := sprwe;
dw.pc := pc;
dw.npc := fui.npc;
dw.fpc := fui.npc + 2;
if dr.imflag='0' then
dw.imreg := (others => '0');
dw.tpc := pc;
end if;
case dec.loadimm is
when LOAD8 =>
if dr.imflag='1' then
-- Shift.
dw.imreg(31 downto 8) := dr.imreg(23 downto 0);
dw.imreg(7 downto 0) := unsigned(imm8);
else
dw.imreg(31 downto 8) := (others => imm8(7));
dw.imreg(7 downto 0) := unsigned(imm8);
end if;
when LOAD16 =>
if dr.imflag='0' then
dw.imreg(31 downto 15) := (others => imm16(15));
dw.imreg(14 downto 0) := unsigned(imm16(14 downto 0));
else
dw.imreg(31 downto 16) := dr.imreg(15 downto 0);
dw.imreg(15 downto 0) := unsigned(imm16(15 downto 0));
end if;
when LOAD24 =>
dw.imreg(31 downto 24) := (others => dec.imm24(23));
dw.imreg(23 downto 0) := unsigned(dec.imm24);
when LOAD0 =>
-- Keep imm
when others =>
--dw.imreg := (others => '0');
end case;
dw.imflag := imflag;
dw.enable_alu := dec.enable_alu;
dw.ismult := dec.ismult;
dw.alu_op := alu_op;
dw.alu_source := dec.alu_source;
dw.wb_is_data_address := '0';
dw.cop_en := dec.cop_en;
dw.cop_wr := dec.cop_wr;
dw.macc := macc;
dw.sr := sr;
dw.memory_access := memory_access;
dw.memory_write := memory_write;
dw.modify_flags := modify_flags;
dw.blocks := blocks1 or blocks2;
dw.dreg := dreg0;
dw.reg_source := reg_source0;
dw.regwe := regwe;
dw.priv := dec.priv;
dw.jump := jump;
dw.except_return:= except_return;
dw.use_carry := dec.use_carry;
-- Preserve condition from E24 extension (imm)
if dr.imflag='0' then
dw.condition_clause := dec.condition;
end if;
dw.opcode := opcode_high;
dw.opcode_low := opcode_low;
dw.dual := dec.extended;
dw.decoded := dec.op;
dw.is_jump := dec.is_jump;
else
busy <= freeze;
end if;
if rst='1' or flush='1' then
dw.valid := '0';
--dw.delay_slot := false;
dw.imflag := '0';
dw.regwe := '0';
dw.rd1 := '0';
dw.rd2 := '0';
dw.ismult:= '0';
dw.blocks := '0';
dw.cop_en := '0';
dw.cop_wr := '0';
dw.priv := '0';
dw.sprwe := '0';
dw.is_jump := false;
dw.memory_access := '0';
dw.memory_write := '0';
dw.enable_alu := '0';
dw.use_carry := '0';
dw.modify_flags := false;
end if;
if dec.extended then
dual <= '1';
end if;
-- fast-forward register access
duo.rd1 <= rd1;
duo.rd2 <= rd2;
duo.sra1 <= ra1;
duo.sra2 <= ra2;
if rising_edge(clk) then
dr <= dw;
end if;
-- synthesis translate_off
--dbg_can_issue_both <= can_issue_both;
--dbg_compositeloadimm <= compositeloadimm;
-- synthesis translate_on
end process;
end behave;
| bsd-3-clause | 66e7ca5da0de0bfada41ed5537db94a2 | 0.529343 | 3.388549 | false | false | false | false |
alvieboy/xtc-base | xtc_top_ppro.vhd | 1 | 4,542 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity xtc_top_ppro is
port (
CLK: in std_logic;
-- Connection to the main SPI flash
--SPI_SCK: out std_logic;
--SPI_MISO: in std_logic;
--SPI_MOSI: out std_logic;
--SPI_CS: out std_logic;
-- WING connections
--WING_A: inout std_logic_vector(15 downto 0);
--WING_B: inout std_logic_vector(15 downto 0);
--WING_C: inout std_logic_vector(15 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic
--DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
-- DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
-- DRAM_CAS_N : OUT STD_LOGIC;
-- DRAM_CKE : OUT STD_LOGIC;
-- DRAM_CLK : OUT STD_LOGIC;
-- DRAM_CS_N : OUT STD_LOGIC;
-- DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
-- DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
-- DRAM_RAS_N : OUT STD_LOGIC;
-- DRAM_WE_N : OUT STD_LOGIC;
-- The LED
--LED: out std_logic
);
end entity xtc_top_ppro;
architecture behave of xtc_top_ppro is
component uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 2);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component;
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clkout2x: out std_logic;
rstout: out std_logic
);
end component;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal clkgen_rst: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
component xtc_top_bram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type
);
end component;
signal wb_read: std_logic_vector(31 downto 0);
signal wb_write: std_logic_vector(31 downto 0);
signal wb_address: std_logic_vector(31 downto 0);
signal wb_tag_i: std_logic_vector(31 downto 0);
signal wb_tag_o: std_logic_vector(31 downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal wb_int: std_logic;
signal wb_stall: std_logic;
signal wb_clk_i_2x: std_ulogic;
begin
cpu: xtc_top_bram
port map (
wb_syscon.clk => wb_clk_i,
wb_syscon.rst => wb_rst_i,
-- Master wishbone interface
iowbi.ack => wb_ack,
iowbi.dat => wb_read,
iowbi.tag => wb_tag_i,
iowbi.int => wb_int,
iowbi.stall => '0',
iowbo.dat => wb_write,
iowbo.adr => wb_address,
iowbo.cyc => wb_cyc,
iowbo.tag => wb_tag_o,
iowbo.stb => wb_stb,
iowbo.sel => wb_sel,
iowbo.we => wb_we
);
-- Simple tag generator
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_cyc='1' and wb_stb='1' and wb_ack='0' then
wb_tag_o <= wb_tag_i;
end if;
end if;
end process;
myuart: uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => wb_read,
wb_dat_i => wb_write,
wb_adr_i => wb_address(31 downto 2),
wb_we_i => wb_we,
wb_cyc_i => wb_cyc,
wb_stb_i => wb_stb,
wb_ack_o => wb_ack,
wb_inta_o => wb_int,
tx => txd,
rx => rxd
);
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
-- rstgen: zpuino_serialreset
-- generic map (
-- SYSTEM_CLOCK_MHZ => 96
-- )
-- port map (
-- clk => sysclk,
-- rx => rx,
-- rstin => clkgen_rst,
-- rstout => sysrst
-- );
sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => '0' ,
clkout => sysclk,
clkout2x => wb_clk_i_2x,
rstout => clkgen_rst
);
end behave;
| bsd-3-clause | c9162832ec8b08fbd3478b94a8f50e20 | 0.538529 | 2.92278 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneii_atoms.vhd | 1 | 329,449 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneii_pllpack;
package body cycloneii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneii_dffe : entity is TRUE;
end cycloneii_dffe;
-- architecture body --
architecture behave of cycloneii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneii_mux21 : entity is TRUE;
end cycloneii_mux21;
architecture AltVITAL of cycloneii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_mux41 : entity is TRUE;
end cycloneii_mux41;
architecture AltVITAL of cycloneii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneii_atom_pack.all;
-- entity declaration --
entity cycloneii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneii_and1 : entity is TRUE;
end cycloneii_and1;
-- architecture body --
architecture AltVITAL of cycloneii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
----------------------------------------------------------------------------
-- Module Name : cycloneii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneii_atom_pack.all;
ENTITY cycloneii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneii_ram_register;
ARCHITECTURE reg_arch OF cycloneii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneii_atom_pack.all;
ENTITY cycloneii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneii_atom_pack.all;
USE work.cycloneii_ram_register;
USE work.cycloneii_ram_pulse_generator;
ENTITY cycloneii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneii_ram_block;
ARCHITECTURE block_arch OF cycloneii_ram_block IS
COMPONENT cycloneii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= '1' WHEN (port_a_disable_ce_on_input_registers = "on") ELSE ena0;
active_b_in <= '1' WHEN (port_b_disable_ce_on_input_registers = "on") ELSE
ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : cycloneii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : cycloneii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
stall => wire_gnd,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : cycloneii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : cycloneii_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : cycloneii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : cycloneii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : cycloneii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : cycloneii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : cycloneii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : cycloneii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= '1' WHEN (port_a_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= '1' WHEN (port_b_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneii_jtag
--
-- Description : CycloneII JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_jtag is
generic (
lpm_type : string := "cycloneii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneii_jtag;
architecture architecture_jtag of cycloneii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneii_crcblock
--
-- Description : CycloneII CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end cycloneii_crcblock;
architecture architecture_crcblock of cycloneii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
-------------------------------------------------------------------
--
-- Entity Name : cycloneii_asmiblock
--
-- Description : CycloneII ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_asmiblock is
generic (
lpm_type : string := "cycloneii_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
end cycloneii_asmiblock;
architecture architecture_asmiblock of cycloneii_asmiblock is
begin
process(dclkin, scein, sdoin, oe)
begin
end process;
end architecture_asmiblock; -- end of cycloneii_asmiblock
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneii_m_cntr
--
-- Description : Timing simulation model for the M counter. M is the loop
-- feedback counter of the CycloneII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneii_m_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneii_m_cntr;
ARCHITECTURE behave of cycloneii_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneii_n_cntr
--
-- Description : Timing simulation model for the N counter. N is the
-- input counter of the CycloneII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneii_n_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneii_n_cntr;
ARCHITECTURE behave of cycloneii_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on PLL input clk. This edge will be ignored." severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the CycloneII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneii_scale_cntr;
ARCHITECTURE behave of cycloneii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneii_pll_reg;
ARCHITECTURE behave of cycloneii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneii_pll
--
-- Description : Timing simulation model for the CycloneII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 6 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneii_atom_pack.all;
USE work.cycloneii_pllpack.all;
USE work.cycloneii_m_cntr;
USE work.cycloneii_n_cntr;
USE work.cycloneii_scale_cntr;
USE work.cycloneii_dffe;
USE work.cycloneii_pll_reg;
ENTITY cycloneii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "manual";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
-- LVDS mode parameters
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneii_pll";
-- Simulation only generics
family_name : string := "CycloneII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
testclearlock : in std_logic := '0';
sbdin : in std_logic := '0';
clk : out std_logic_vector(2 downto 0);
locked : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
sbdout : out std_logic
);
END cycloneii_pll;
ARCHITECTURE vital_pll of cycloneii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 5) := (OTHERS => 0);
signal c_high_val : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val : int_array(0 to 5) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 5) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 5);
-- old values
signal c_high_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 5);
-- hold registers
signal c_high_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 5);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
signal sig_c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal sig_c_hi_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_orig : int_array(0 to 5) := (OTHERS => 0);
--signal i_clk5_counter : string(1 to 2) := "c5";
--signal i_clk4_counter : string(1 to 2) := "c4";
--signal i_clk3_counter : string(1 to 2) := "c3";
--signal i_clk2_counter : string(1 to 2) := "c2";
--signal i_clk1_counter : string(1 to 2) := "c1";
--signal i_clk0_counter : string(1 to 2) := "c0";
signal i_clk5_counter : integer := 5;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT GPP_SCAN_CHAIN : integer := 174;
CONSTANT FAST_SCAN_CHAIN : integer := 75;
CONSTANT GATE_LOCK_CYCLES : integer := 7;
CONSTANT cntrs : str_array(5 downto 0) := (" C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (57, 16, 36, 5);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (18, 13, 8, 2);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (6, 12, 30, 36, 52, 57, 72, 77, 92, 96, 110, 114, 127, 131, 144, 148);
CONSTANT loop_filter_r_arr : str_array1(0 to 39) := (" 1.000000", " 1.500000", " 2.000000", " 2.500000", " 3.000000", " 3.500000", " 4.000000", " 4.500000", " 5.000000", " 5.500000", " 6.000000", " 6.500000", " 7.000000", " 7.500000", " 8.000000", " 8.500000", " 9.000000", " 9.500000", "10.000000", "10.500000", "11.000000", "11.500000", "12.000000", "12.500000", "13.000000", "13.500000", "14.000000", "14.500000", "15.000000", "15.500000", "16.000000", "16.500000", "17.000000", "17.500000", "18.000000", "18.500000", "19.000000", "19.500000", "20.000000", "20.500000");
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal c_clk : std_logic_array(0 to 5);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_tap : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_out_last_value : std_logic_vector(7 downto 0);
signal vco_tap_last_value : std_logic_vector(7 downto 0);
-- signals to assign values to counter params
signal m_val : int_array(0 to 1) := (OTHERS => 1);
signal n_val : int_array(0 to 1) := (OTHERS => 1);
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 9) := " ";
-- old values
signal m_val_old : int_array(0 to 1) := (OTHERS => 1);
signal n_val_old : int_array(0 to 1) := (OTHERS => 1);
signal m_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 9) := " ";
signal num_output_cntrs : integer := 6;
signal scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal sclkout0_tmp : std_logic;
signal sclkout1_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanread_ipd : std_logic;
signal scanwrite_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
-- registered signals
signal scanread_reg : std_logic := '0';
signal scanwrite_reg : std_logic := '0';
signal scanwrite_enabled : std_logic := '0';
signal gated_scanclk : std_logic := '1';
signal inclk_c0_dly1 : std_logic := '0';
signal inclk_c0_dly2 : std_logic := '0';
signal inclk_c0_dly3 : std_logic := '0';
signal inclk_c0_dly4 : std_logic := '0';
signal inclk_c0_dly5 : std_logic := '0';
signal inclk_c0_dly6 : std_logic := '0';
signal inclk_c1_dly1 : std_logic := '0';
signal inclk_c1_dly2 : std_logic := '0';
signal inclk_c1_dly3 : std_logic := '0';
signal inclk_c1_dly4 : std_logic := '0';
signal inclk_c1_dly5 : std_logic := '0';
signal inclk_c1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "c0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal ext_fbk_cntr_index : integer := 0;
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandone_tmp : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 5);
signal inclk_m_from_vco : std_logic;
signal inclk_sclkout0_from_vco : std_logic;
signal inclk_sclkout1_from_vco : std_logic;
--signal tap0_is_active : boolean := true;
signal sig_quiet_time : time := 0 ps;
signal sig_slowest_clk_old : time := 0 ps;
signal sig_slowest_clk_new : time := 0 ps;
signal sig_m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
COMPONENT cycloneii_m_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneii_n_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
fbin_ipd <= '0';
scanclk_ipd <= '0';
scanread_ipd <= '0';
scandata_ipd <= '0';
scanwrite_ipd <= '0';
inclk_m <= refclk when m_test_source = 1 else
'0' when m_test_source = 2 else
'0' when m_test_source = 3 else
clk0_tmp when operation_mode = "external_feedback" and feedback_source = "clk0" else
clk1_tmp when operation_mode = "external_feedback" and feedback_source = "clk1" else
clk2_tmp when operation_mode = "external_feedback" and feedback_source = "clk2" else
clk3_tmp when operation_mode = "external_feedback" and feedback_source = "clk3" else
clk4_tmp when operation_mode = "external_feedback" and feedback_source = "clk4" else
clk5_tmp when operation_mode = "external_feedback" and feedback_source = "clk5" else
inclk_m_from_vco;
ext_fbk_cntr_high <= c_high_val(ext_fbk_cntr_index);
ext_fbk_cntr_low <= c_low_val(ext_fbk_cntr_index);
ext_fbk_cntr_ph <= c_ph_val(ext_fbk_cntr_index);
ext_fbk_cntr_initial <= c_initial_val(ext_fbk_cntr_index);
ext_fbk_cntr_mode <= c_mode_val(ext_fbk_cntr_index);
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
pll_in_test_mode <= true when m_test_source = 1 or c0_test_source = 1 or
c0_test_source = 2 or c1_test_source = 1 or
c1_test_source = 2 or c2_test_source = 1 or
c2_test_source = 2 else
false;
m1 : cycloneii_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val(0),
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and switch_over_on_lossclk = "on" and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
else
end if;
else
end if;
end process;
process (inclk_sclkout0_from_vco)
begin
sclkout0_tmp <= inclk_sclkout0_from_vco;
end process;
process (inclk_sclkout1_from_vco)
begin
sclkout1_tmp <= inclk_sclkout1_from_vco;
end process;
n1 : cycloneii_n_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val(0),
modulus => n_val(0));
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 2 else
'0' when c0_test_source = 3 else
inclk_c_from_vco(0);
c0 : cycloneii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 2 else
'0' when c1_test_source = 3 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 2 else
'0' when c2_test_source = 3 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= clkin when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= '0' when (pll_type = "fast") else
clkin when (c4_test_source = 0) else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= '0' when (pll_type = "fast") else
clkin when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : cycloneii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c0_dly1 <= inclk_c0 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c0_dly2 <= inclk_c0_dly1;
inclk_c0_dly3 <= inclk_c0_dly2;
inclk_c0_dly4 <= inclk_c0_dly3;
inclk_c0_dly5 <= inclk_c0_dly4;
inclk_c0_dly6 <= inclk_c0_dly5;
inclk_c1_dly1 <= inclk_c1 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c1_dly2 <= inclk_c1_dly1;
inclk_c1_dly3 <= inclk_c1_dly2;
inclk_c1_dly4 <= inclk_c1_dly3;
inclk_c1_dly5 <= inclk_c1_dly4;
inclk_c1_dly6 <= inclk_c1_dly5;
process(inclk_c0_dly6, inclk_c1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0_dly6'event and inclk_c0_dly6 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0_dly6'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0_dly6'event and inclk_c0_dly6 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1_dly6'event and inclk_c1_dly6 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1_dly6'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1_dly6'event and inclk_c1_dly6 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "c0") then
enable0_tmp <= c0_tmp;
elsif (enable0_counter = "c1") then
enable0_tmp <= c1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "c0") then
enable1_tmp <= c0_tmp;
elsif (enable1_counter = "c1") then
enable1_tmp <= c1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (sim_gate_lock_device_behavior = "on") then
if (count = gate_lock_counter) then
output := '1';
end if;
elsif (count = GATE_LOCK_CYCLES) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT family_name & " PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val(0));
write (buf, string'(" ( "));
write (buf, n_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val(0));
write (buf, string'(" ( "));
write (buf, m_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
if (ss > 0) then
write (buf, string'(" M2 modulus = "));
write (buf, m_val(1));
write (buf, string'(" ( "));
write (buf, m_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" N2 modulus = "));
write (buf, n_val(1));
write (buf, string'(" ( "));
write (buf, n_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
end if;
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, sig_c_low_val_tmp(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
process (scanwrite_enabled, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), vco_tap, fbclk, scanclk_ipd, gated_scanclk)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable n_fast : std_logic_vector(1 downto 0);
variable c_high_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
variable c_mode_val_tmp : str_array(0 to 5);
variable m_ph_val_tmp : integer := 0;
variable m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_m2 : integer;
variable i_n2 : integer;
variable i_ss : integer;
variable i_c_high : int_array(0 to 5);
variable i_c_low : int_array(0 to 5);
variable i_c_initial : int_array(0 to 5);
variable i_c_ph : int_array(0 to 5);
variable i_c_mode : str_array(0 to 5);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 2) := "c0";
variable clk1_cntr : string(1 to 2) := "c1";
variable clk2_cntr : string(1 to 2) := "c2";
variable clk3_cntr : string(1 to 2) := "c3";
variable clk4_cntr : string(1 to 2) := "c4";
variable clk5_cntr : string(1 to 2) := "c5";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable tmp_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable m_lo, m_hi : std_logic_vector(4 downto 0);
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable got_first_gated_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable scanclk_period : time := 0 ps;
variable current_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable Tviol_scanread_scanclk : std_ulogic := '0';
variable Tviol_scanwrite_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanread_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanwrite_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
if (refclk_int > (refclk_int * max_modulus / m_mod)) then
q_period := refclk_int * 1 ps;
else
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(2) = '0') then
index := 0;
elsif (arg(2) = '1') then
index := 1;
elsif (arg(2) = '2') then
index := 2;
elsif (arg(2) = '3') then
index := 3;
elsif (arg(2) = '4') then
index := 4;
else index := 5;
end if;
return index;
end extract_cntr_index;
begin
if (init) then
if (m = 0) then
clk5_cntr := "c5";
clk4_cntr := "c4";
clk3_cntr := "c3";
clk2_cntr := "c2";
clk1_cntr := "c1";
clk0_cntr := "c0";
else
clk5_cntr := clk5_counter;
clk4_cntr := clk4_counter;
clk3_cntr := clk3_counter;
clk2_cntr := clk2_counter;
clk1_cntr := clk1_counter;
clk0_cntr := clk0_counter;
end if;
if (operation_mode = "external_feedback") then
if (feedback_source = "clk0") then
fbk_cntr := clk0_cntr;
elsif (feedback_source = "clk1") then
fbk_cntr := clk1_cntr;
elsif (feedback_source = "clk2") then
fbk_cntr := clk2_cntr;
elsif (feedback_source = "clk3") then
fbk_cntr := clk3_cntr;
elsif (feedback_source = "clk4") then
fbk_cntr := clk4_cntr;
elsif (feedback_source = "clk5") then
fbk_cntr := clk5_cntr;
else
fbk_cntr := "c0";
end if;
if (fbk_cntr = "c0") then
fbk_cntr_index := 0;
elsif (fbk_cntr = "c1") then
fbk_cntr_index := 1;
elsif (fbk_cntr = "c2") then
fbk_cntr_index := 2;
elsif (fbk_cntr = "c3") then
fbk_cntr_index := 3;
elsif (fbk_cntr = "c4") then
fbk_cntr_index := 4;
elsif (fbk_cntr = "c5") then
fbk_cntr_index := 5;
end if;
ext_fbk_cntr <= fbk_cntr;
ext_fbk_cntr_index <= fbk_cntr_index;
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
if (((pll_type = "fast") or (pll_type = "lvds")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (i_c_mode(fbk_cntr_index) = "bypass") then
output_count := 1;
else
output_count := i_c_high(fbk_cntr_index) + i_c_low(fbk_cntr_index);
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val(0) <= i_n;
m_val(0) <= i_m;
m_val(1) <= m2;
n_val(1) <= n2;
if (i_m = 1) then
m_mode_val(0) <= "bypass";
else
m_mode_val(0) <= " ";
end if;
if (m2 = 1) then
m_mode_val(1) <= "bypass";
end if;
if (i_n = 1) then
n_mode_val(0) <= "bypass";
end if;
if (n2 = 1) then
n_mode_val(1) <= "bypass";
end if;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
m_val_tmp := m_val;
for i in 0 to 5 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds") then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_tmp(i) := i_c_ph(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
lfc_val <= loop_filter_c;
lfr_val <= loop_filter_r;
cp_curr_val <= charge_pump_current;
if (pll_type = "fast") then
scan_chain_length := FAST_SCAN_CHAIN;
end if;
-- initialize the scan_chain contents
-- CP/LF bits
scan_data(11 downto 0) <= "000000000000";
for i in 0 to 3 loop
if (pll_type = "fast" or pll_type = "lvds") then
if (fpll_loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
else
if (loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
end if;
end loop;
for i in 0 to 15 loop
if (charge_pump_curr_arr(i) = charge_pump_current) then
scan_data(3 downto 0) <= int2bin(i, 4);
end if;
end loop;
for i in 0 to 39 loop
if (loop_filter_r_arr(i) = loop_filter_r) then
if (i >= 16 and i <= 23) then
scan_data(9 downto 4) <= int2bin((i+8), 6);
elsif (i >= 24 and i <= 31) then
scan_data(9 downto 4) <= int2bin((i+16), 6);
elsif (i >= 32) then
scan_data(9 downto 4) <= int2bin((i+24), 6);
else
scan_data(9 downto 4) <= int2bin(i, 6);
end if;
end if;
end loop;
if (pll_type = "fast" or pll_type = "lvds") then
scan_data(21 downto 12) <= "0000000000"; -- M, C3-C0 ph
-- C0-C3 high
scan_data(25 downto 22) <= int2bin(i_c_high(0), 4);
scan_data(35 downto 32) <= int2bin(i_c_high(1), 4);
scan_data(45 downto 42) <= int2bin(i_c_high(2), 4);
scan_data(55 downto 52) <= int2bin(i_c_high(3), 4);
-- C0-C3 low
scan_data(30 downto 27) <= int2bin(i_c_low(0), 4);
scan_data(40 downto 37) <= int2bin(i_c_low(1), 4);
scan_data(50 downto 47) <= int2bin(i_c_low(2), 4);
scan_data(60 downto 57) <= int2bin(i_c_low(3), 4);
-- C0-C3 mode
for i in 0 to 3 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(26 + (10*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
else
scan_data(26 + (10*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
end if;
end loop;
-- M
if (i_m = 1) then
scan_data(66) <= '1';
scan_data(71) <= '0';
scan_data(65 downto 62) <= "0000";
scan_data(70 downto 67) <= "0000";
else
scan_data(66) <= '0'; -- set BYPASS bit to 0
scan_data(70 downto 67) <= int2bin(i_m/2, 4); -- set M low
if (i_m rem 2 = 0) then
-- M is an even no. : set M high = low,
-- set odd/even bit to 0
scan_data(65 downto 62) <= int2bin(i_m/2, 4);
scan_data(71) <= '0';
else -- M is odd : M high = low + 1
scan_data(65 downto 62) <= int2bin((i_m/2) + 1, 4);
scan_data(71) <= '1';
end if;
end if;
-- N
scan_data(73 downto 72) <= int2bin(i_n, 2);
if (i_n = 1) then
scan_data(74) <= '1';
scan_data(73 downto 72) <= "00";
end if;
else -- PLL type is auto or enhanced
scan_data(25 downto 12) <= "00000000000000"; -- M, C5-C0 ph
-- C0-C5 high
scan_data(123 downto 116) <= int2bin(i_c_high(0), 8);
scan_data(105 downto 98) <= int2bin(i_c_high(1), 8);
scan_data(87 downto 80) <= int2bin(i_c_high(2), 8);
scan_data(69 downto 62) <= int2bin(i_c_high(3), 8);
scan_data(51 downto 44) <= int2bin(i_c_high(4), 8);
scan_data(33 downto 26) <= int2bin(i_c_high(5), 8);
-- C0-C5 low
scan_data(132 downto 125) <= int2bin(i_c_low(0), 8);
scan_data(114 downto 107) <= int2bin(i_c_low(1), 8);
scan_data(96 downto 89) <= int2bin(i_c_low(2), 8);
scan_data(78 downto 71) <= int2bin(i_c_low(3), 8);
scan_data(60 downto 53) <= int2bin(i_c_low(4), 8);
scan_data(42 downto 35) <= int2bin(i_c_low(5), 8);
-- C0-C5 mode
for i in 0 to 5 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(124 - (18*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
else
scan_data(124 - (18*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
end if;
end loop;
-- M/M2
scan_data(142 downto 134) <= int2bin(i_m, 9);
scan_data(143) <= '0';
scan_data(152 downto 144) <= int2bin(m2, 9);
scan_data(153) <= '0';
if (i_m = 1) then
scan_data(143) <= '1';
scan_data(142 downto 134) <= "000000000";
end if;
if (m2 = 1) then
scan_data(153) <= '1';
scan_data(152 downto 144) <= "000000000";
end if;
-- N/N2
scan_data(162 downto 154) <= int2bin(i_n, 9);
scan_data(172 downto 164) <= int2bin(n2, 9);
if (i_n = 1) then
scan_data(163) <= '1';
scan_data(162 downto 154) <= "000000000";
end if;
if (n2 = 1) then
scan_data(173) <= '1';
scan_data(172 downto 164) <= "000000000";
end if;
end if;
if (pll_type = "fast" or pll_type = "lvds") then
num_output_cntrs <= 4;
else
num_output_cntrs <= 6;
end if;
init := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '0') then
-- falling edge : deassert scandone
scandone_tmp <= transport '0' after (1.5 * scanclk_period);
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '1') then
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
reconfig_err <= false;
-- make temporary copy of scan_data for processing
tmp_scan_data := scan_data;
-- save old values
lfc_old <= lfc_val;
lfr_old <= lfr_val;
cp_curr_old <= cp_curr_val;
-- CP
-- Bits 0-3 : all values are legal
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(scan_data(3 downto 0)));
-- LF Resistance : bits 4-9
-- values from 010000 - 010111, 100000 - 100111,
-- 110000 - 110111 are illegal
lfr_tmp := tmp_scan_data(9 downto 4);
lfr_int := alt_conv_integer(lfr_tmp);
if (((lfr_int >= 16) and (lfr_int <= 23)) or
((lfr_int >= 32) and (lfr_int <= 39)) or
((lfr_int >= 48) and (lfr_int <= 55))) then
reconfig_err <= true;
ASSERT false REPORT "Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000-001111, 011000-011111, 101000-101111 and 111000-111111. Reconfiguration may not work." severity warning;
else
if (lfr_int >= 56) then
lfr_int := lfr_int - 24;
elsif ((lfr_int >= 40) and (lfr_int <= 47)) then
lfr_int := lfr_int - 16;
elsif ((lfr_int >= 24) and (lfr_int <= 31)) then
lfr_int := lfr_int - 8;
end if;
lfr_val <= loop_filter_r_arr(lfr_int);
end if;
-- LF Capacitance : bits 10,11 : all values are legal
lfc_tmp := scan_data(11 downto 10);
if (pll_type = "fast" or pll_type = "lvds") then
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(lfc_tmp));
else
lfc_val <= loop_filter_c_arr(alt_conv_integer(lfc_tmp));
end if;
-- cntrs c0-c5
-- save old values for display info.
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
m_ph_val_old <= m_ph_val;
c_high_val_old <= c_high_val;
c_low_val_old <= c_low_val;
c_ph_val_old <= c_ph_val;
c_mode_val_old <= c_mode_val;
-- first the M counter phase : bit order same for fast and GPP
if (scan_data(12) = '0') then
-- do nothing
elsif (scan_data(12) = '1' and scan_data(13) = '1') then
m_ph_val_tmp := m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7) then
m_ph_val_tmp := 0;
end if;
elsif (scan_data(12) = '1' and scan_data(13) = '0') then
m_ph_val_tmp := m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0) then
m_ph_val_tmp := 7;
end if;
else
reconfig_err <= true;
ASSERT false REPORT "Illegal values for M counter phase tap. Reconfiguration may not work." severity warning;
end if;
-- read the fast PLL bits
if (pll_type = "fast" or pll_type = "lvds") then
-- C3-C0 phase bits
for i in 3 downto 0 loop
start_bit := 14 + ((3-i)*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
-- C0-C3 counter moduli
for i in 0 to 3 loop
start_bit := 22 + (i*10);
if (tmp_scan_data(start_bit + 4) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high_fast := tmp_scan_data(start_bit+3 downto start_bit);
low_fast := tmp_scan_data(start_bit+8 downto start_bit+5);
if (tmp_scan_data(start_bit+3 downto start_bit) = "0000") then
c_high_val_tmp(i) := 16;
else
c_high_val_tmp(i) := alt_conv_integer(high_fast);
end if;
if (tmp_scan_data(start_bit+8 downto start_bit+5) = "0000") then
c_low_val_tmp(i) := 16;
else
c_low_val_tmp(i) := alt_conv_integer(low_fast);
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- M
-- some temporary storage
if (tmp_scan_data(65 downto 62) = "0000") then
m_hi := "10000";
else
m_hi := "0" & tmp_scan_data(65 downto 62);
end if;
if (tmp_scan_data(70 downto 67) = "0000") then
m_lo := "10000";
else
m_lo := "0" & tmp_scan_data(70 downto 67);
end if;
m_val_tmp(0) := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
if (tmp_scan_data(66) = '1') then
if (tmp_scan_data(71) = '1') then
-- this will turn off the M counter : error
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work." severity warning;
else -- M counter is being bypassed
if (m_mode_val(0) /= "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(0) := 1;
m_mode_val(0) <= "bypass";
end if;
else
if (m_mode_val(0) = "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched BYPASS mode to enabled. PLL may lose lock." severity warning;
end if;
m_mode_val(0) <= " ";
if (tmp_scan_data(71) = '1') then
-- odd : check for duty cycle, if not 50% -- error
if (alt_conv_integer(m_hi) - alt_conv_integer(m_lo) /= 1) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
else -- even
if (alt_conv_integer(m_hi) /= alt_conv_integer(m_lo)) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
-- N
is_error := false;
n_fast := tmp_scan_data(73 downto 72);
n_val(0) <= alt_conv_integer(n_fast);
if (tmp_scan_data(74) /= '1') then
if (alt_conv_integer(n_fast) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for N counter. Instead the counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_fast) = 0) then
n_val(0) <= 4;
ASSERT FALSE REPORT "N Modulus = " &int2str(4)& " " severity note;
end if;
if (not is_error) then
if (n_mode_val(0) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_fast))& "). PLL may lose lock." severity warning;
else
ASSERT FALSE REPORT "N modulus = " &int2str(alt_conv_integer(n_fast))& " "severity note;
end if;
n_mode_val(0) <= " ";
end if;
elsif (tmp_scan_data(74) = '1') then
if (tmp_scan_data(72) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(0) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(0) <= 1;
n_mode_val(0) <= "bypass";
end if;
end if;
else -- GENERAL PURPOSE PLL
for i in 0 to 5 loop
start_bit := 116 - (i*18);
if (tmp_scan_data(start_bit + 8) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high := tmp_scan_data(start_bit + 7 downto start_bit);
low := tmp_scan_data(start_bit+16 downto start_bit+9);
if (tmp_scan_data(start_bit+7 downto start_bit) = "00000000") then
c_high_val_tmp(i) := 256;
else
c_high_val_tmp(i) := alt_conv_integer(high);
end if;
if (tmp_scan_data(start_bit+16 downto start_bit+9) = "00000000") then
c_low_val_tmp(i) := 256;
else
c_low_val_tmp(i) := alt_conv_integer(low);
end if;
end loop;
-- the phase taps
for i in 0 to 5 loop
start_bit := 14 + (i*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- cntrs M/M2
for i in 0 to 1 loop
start_bit := 134 + (i*10);
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
m_tmp := tmp_scan_data(start_bit+8 downto start_bit);
m_val_tmp(i) := alt_conv_integer(m_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(m_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(i)& "counter. Instead " &ss_cntrs(i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (tmp_scan_data(start_bit+8 downto start_bit) = "000000000") then
m_val_tmp(i) := 512;
end if;
if (not is_error) then
if (m_mode_val(i) = "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(m_tmp))& "). PLL may lose lock." severity warning;
else
end if;
m_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val(i) /= "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(i) := 1;
m_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (m_mode_val(0) /= m_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for M/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
sig_m_val_tmp <= m_val_tmp;
-- cntrs N/N2
for i in 0 to 1 loop
start_bit := 154 + i*10;
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
n_tmp := tmp_scan_data(start_bit+8 downto start_bit);
n_val(i) <= alt_conv_integer(n_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(n_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(2+i)& "counter. Instead " &ss_cntrs(2+i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_tmp) = 0) then
n_val(i) <= 512;
end if;
if (not is_error) then
if (n_mode_val(i) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_tmp))& "). PLL may lose lock." severity warning;
else
end if;
n_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(2+i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(i) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(i) <= 1;
n_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (n_mode_val(0) /= n_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for N/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
slowest_clk_old := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0),
c_high_val(1)+c_low_val(1), c_mode_val(1),
c_high_val(2)+c_low_val(2), c_mode_val(2),
c_high_val(3)+c_low_val(3), c_mode_val(3),
c_high_val(4)+c_low_val(4), c_mode_val(4),
c_high_val(5)+c_low_val(5), c_mode_val(5),
sig_refclk_period, m_val(0));
slowest_clk_new := slowest_clk(c_high_val_tmp(0)+c_low_val_tmp(0), c_mode_val_tmp(0),
c_high_val_tmp(1)+c_low_val_tmp(1), c_mode_val_tmp(1),
c_high_val_tmp(2)+c_low_val_tmp(2), c_mode_val_tmp(2),
c_high_val_tmp(3)+c_low_val_tmp(3), c_mode_val_tmp(3),
c_high_val_tmp(4)+c_low_val_tmp(4), c_mode_val_tmp(4),
c_high_val_tmp(5)+c_low_val_tmp(5), c_mode_val_tmp(5),
sig_refclk_period, m_val_tmp(0));
if (slowest_clk_new > slowest_clk_old) then
quiet_time := slowest_clk_new;
else
quiet_time := slowest_clk_old;
end if;
sig_quiet_time <= quiet_time;
sig_slowest_clk_old <= slowest_clk_old;
sig_slowest_clk_new <= slowest_clk_new;
tmp_rem := (quiet_time/1 ps) rem (scanclk_period/ 1 ps);
scanclk_cycles := (quiet_time/1 ps) / (scanclk_period/1 ps);
if (tmp_rem /= 0) then
scanclk_cycles := scanclk_cycles + 1;
end if;
scandone_tmp <= transport '1' after ((scanclk_cycles+1)*scanclk_period - (scanclk_period/2));
end if;
if (scanwrite_enabled = '1') then
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (c_clk(0)'event and c_clk(0) = '1') then
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
c0_rising_edge_transfer_done := true;
end if;
if (c_clk(1)'event and c_clk(1) = '1') then
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
c1_rising_edge_transfer_done := true;
end if;
if (c_clk(2)'event and c_clk(2) = '1') then
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
c2_rising_edge_transfer_done := true;
end if;
if (c_clk(3)'event and c_clk(3) = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (c_clk(4)'event and c_clk(4) = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (c_clk(5)'event and c_clk(5) = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
end if;
if (c_clk(0)'event and c_clk(0) = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (c_clk(1)'event and c_clk(1) = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (c_clk(2)'event and c_clk(2) = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (c_clk(3)'event and c_clk(3) = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (c_clk(4)'event and c_clk(4) = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (c_clk(5)'event and c_clk(5) = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanwrite_enabled = '1') then
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x) and vco_tap(x) = '0') then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = x) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end loop;
end if;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
if (areset_ipd = '1') then
c_ph_val <= i_c_ph;
c_ph_val_tmp := i_c_ph;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
end if;
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x)) then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
inclk_c_from_vco(i) <= vco_tap(x);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
end if;
end loop;
if (m_ph_val = x) then
inclk_m_from_vco <= vco_tap(x);
end if;
vco_tap_last_value(x) <= vco_tap(x);
end if;
end loop;
if (scanclk_ipd'event and scanclk_ipd = '0') then
-- enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end if;
if (scanread_reg = '1') then
gated_scanclk <= transport scanclk_ipd and scanread_reg;
else
gated_scanclk <= transport '1';
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
-- register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk) then
scanclk_period := now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
-- reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd = '0' and scanread_reg = '1') then
got_first_scanclk := false;
got_first_gated_scanclk := false;
end if;
scanclk_last_rising_edge := now;
end if;
if (gated_scanclk'event and gated_scanclk = '1' and now > 0 ps) then
if (not got_first_gated_scanclk) then
got_first_gated_scanclk := true;
end if;
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
end process;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-1) when (pll_type = "fast" or pll_type = "lvds") else scan_data(GPP_SCAN_CHAIN-1);
SCHEDULE : process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, vco_out)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable pll_is_disabled : boolean := false;
variable next_vco_sched_time : time := 0 ps;
variable tap0_is_active : boolean := true;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val(0) * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
pll_is_in_reset := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
if (ena_ipd = '1' and not stop_vco and next_vco_sched_time <= now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
pll_is_disabled := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
if (ena_ipd'event and ena_ipd = '1') then
assert false report family_name & " PLL is enabled" severity note;
pll_is_disabled := false;
if (areset_ipd /= '1' and not stop_vco and next_vco_sched_time < now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- illegal value on areset_ipd
if (areset_ipd'event and areset_ipd = 'X') then
assert false report "Illegal value 'X' detected on ARESET input" severity warning;
end if;
if (areset_ipd = '1' or ena_ipd = '0' or stop_vco) then
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
-- first_schedule := true;
-- vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
-- reset all counter phase taps to POF programmed values
end if;
if (schedule_vco'event and areset_ipd /= '1' and ena_ipd /= '0' and (not stop_vco) and now > 0 ps) then
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val(0);
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val(0) * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * ext_fbk_cntr_modulus);
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_M := (m_initial_val - 1) * ext_fbk_cntr_modulus * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_M := initial_delay/1 ps + fbk_phase;
end if;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap0
vco_out(0) <= transport vco_val after sched_time;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap 0
vco_out(0) <= transport vco_val after sched_time;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
next_vco_sched_time := now + sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- now schedule the other taps with the appropriate phase-shift
if (vco_out(0)'event) then
for k in 1 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_out(0) after phase_shift(k);
end loop;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped : do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
-- check which vco_tap has event
for x in 0 to 7 loop
if (vco_out(x) /= vco_out_last_value(x)) then
-- TAP X has event
if (x = 0 and areset_ipd = '0' and ena_ipd = '1' and sig_stop_vco = '0') then
if (vco_out(0) = '1') then
tap0_is_active := true;
end if;
if (tap0_is_active) then
vco_tap(0) <= vco_out(0);
end if;
elsif (tap0_is_active) then
vco_tap(x) <= vco_out(x);
end if;
if (sig_stop_vco = '1') then
vco_tap(x) <= '0';
end if;
vco_out_last_value(x) <= vco_out(x);
end if;
end loop;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
end process SCHEDULE;
clk0_tmp <= c_clk(i_clk0_counter);
clk(0) <= clk0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk(1) <= clk1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk(2) <= clk2_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk4_tmp <= c_clk(i_clk4_counter);
clk5_tmp <= c_clk(i_clk5_counter);
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneii_routing_wire
--
-- Description : CycloneII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
ENTITY cycloneii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_routing_wire : entity is TRUE;
end cycloneii_routing_wire;
ARCHITECTURE behave of cycloneii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
---------------------------------------------------------------------
--
-- Entity Name : cycloneii_lcell_ff
--
-- Description : Cyclone II LCELL_FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
use work.cycloneii_and1;
entity cycloneii_lcell_ff is
generic (
x_on_violation : string := "on";
lpm_type : string := "cycloneii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_sdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_sdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
sdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_lcell_ff : entity is TRUE;
end cycloneii_lcell_ff;
architecture vital_lcell_ff of cycloneii_lcell_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal datain_dly : std_logic;
signal sdata_ipd : std_logic;
signal sdata_dly : std_logic;
signal sdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
dataindelaybuffer: cycloneii_and1
port map(IN1 => datain_ipd,
Y => datain_dly);
sdatadelaybuffer: cycloneii_and1
port map(IN1 => sdata_ipd,
Y => sdata_dly);
sdatadelaybuffer1: cycloneii_and1
port map(IN1 => sdata_dly,
Y => sdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (sdata_ipd, sdata, tipd_sdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, datain_dly, sdata_dly1,
sclr_ipd, sload_ipd, aclr_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sdata_clk,
TimingData => TimingData_sdata_clk,
TestSignal => sdata_ipd,
TestSignalName => "SDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sdata_clk_noedge_posedge,
SetupLow => tsetup_sdata_clk_noedge_posedge,
HoldHigh => thold_sdata_clk_noedge_posedge,
HoldLow => thold_sdata_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_sdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (aclr_ipd = '1')) then
iregout := '0';
elsif (violation = 'X' and x_on_violation = "on") then
iregout := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iregout := '0';
elsif (sload_ipd = '1') then
iregout := sdata_dly1;
else
iregout := datain_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => iregout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (sdata_ipd'last_event, tpd_sdata_regout, TRUE),
2 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
---------------------------------------------------------------------
--
-- Entity Name : cycloneii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
lpm_type : string := "cycloneii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_lcell_comb : entity is TRUE;
end cycloneii_lcell_comb;
architecture vital_lcell_comb of cycloneii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
--
--
-- CYCLONEII_ASYNCH_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_asynch_io is
generic(
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
use_differential_input : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_padio_differentialout : VitalDelayType01 := DefPropDelay01;
tpd_differentialin_combout : VitalDelayType01 := DefPropDelay01;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tipd_differentialin : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in STD_LOGIC;
differentialin : in STD_LOGIC;
differentialout : out STD_LOGIC;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneii_asynch_io : entity is TRUE;
end cycloneii_asynch_io;
architecture behave of cycloneii_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal differentialin_ipd: std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (differentialin_ipd, differentialin, tipd_differentialin);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, differentialin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable differentialout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout_differentialin_or_pad : std_logic;
variable differentialout_tmp : std_logic;
begin
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
if (use_differential_input = "true") then
tmp_combout_differentialin_or_pad := differentialin_ipd;
else
tmp_combout_differentialin_or_pad := tmp_combout;
end if;
if (operation_mode = "input" or operation_mode = "bidir") then
differentialout_tmp := padio_ipd;
else
differentialout_tmp := 'X';
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout_differentialin_or_pad,
Paths => (1 => (padio_ipd'last_event, tpd_padio_combout, use_differential_input = "false"),
2 => (differentialin_ipd'last_event, tpd_differentialin_combout, use_differential_input = "true")),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => differentialout,
OutSignalName => "differentialout",
OutTemp => differentialout_tmp,
Paths => (1 => (padio_ipd'last_event, tpd_padio_differentialout, TRUE)),
GlitchData => differentialout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- CYCLONEII_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
use work.cycloneii_asynch_io;
use work.cycloneii_dffe;
use work.cycloneii_mux21;
entity cycloneii_io is
generic (
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
use_differential_input : string := "false";
lpm_type : string := "cycloneii_io";
input_power_up : string := "low");
port (
datain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '1';
linkin : in std_logic := '0';
differentialin : in std_logic := '0';
differentialout : out std_logic;
linkout : out std_logic;
combout : out std_logic;
regout : out std_logic;
padio : inout std_logic
);
end cycloneii_io;
architecture structure of cycloneii_io is
component cycloneii_asynch_io
generic(
operation_mode : string := "input";
open_drain_output : string := "false";
use_differential_input : STRING := "false";
bus_hold : string := "false");
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
regin : in std_logic;
differentialin : in STD_LOGIC;
differentialout : out STD_LOGIC;
padio : inout STD_LOGIC;
combout: out STD_LOGIC;
regout : out STD_LOGIC);
end component;
component cycloneii_dffe
generic(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end component;
component cycloneii_mux21
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
end component;
signal is_bidir_or_output : std_logic;
signal out_reg_clk_ena, oe_reg_clk_ena : std_logic;
signal tmp_oe_reg_out, tmp_input_reg_out, tmp_output_reg_out : std_logic;
signal inreg_sreset_is_used, outreg_sreset_is_used, oereg_sreset_is_used : std_logic;
signal inreg_sreset, outreg_sreset, oereg_sreset : std_logic;
signal in_reg_aclr, in_reg_apreset : std_logic;
signal oe_reg_aclr, oe_reg_apreset, oe_reg_sel : std_logic;
signal out_reg_aclr, out_reg_apreset, out_reg_sel : std_logic;
signal input_reg_pu_low, output_reg_pu_low, oe_reg_pu_low : std_logic;
signal inreg_D, outreg_D, oereg_D : std_logic;
signal tmp_datain, tmp_oe : std_logic;
signal iareset, isreset : std_logic;
signal inreg_mux_sel, outreg_mux_sel, oereg_mux_sel : std_logic;
signal input_dffe_aclr, input_dffe_apreset, output_dffe_aclr, output_dffe_apreset : std_logic;
signal oe_dffe_aclr, oe_dffe_apreset : std_logic;
signal pad_or_differentialin : std_logic;
begin
is_bidir_or_output <= '1' WHEN (operation_mode = "bidir" OR operation_mode = "output") ELSE '0';
input_reg_pu_low <= '0' WHEN input_power_up = "low" ELSE '1';
output_reg_pu_low <= '0' WHEN output_power_up = "low" ELSE '1';
oe_reg_pu_low <= '0' WHEN oe_power_up = "low" ELSE '1';
out_reg_sel <= '1' WHEN output_register_mode = "register" ELSE '0';
oe_reg_sel <= '1' WHEN oe_register_mode = "register" ELSE '0';
iareset <= (NOT areset) WHEN ( areset = '1' OR areset = '0') ELSE '1';
isreset <= sreset WHEN ( areset = '1' OR areset = '0') ELSE '0';
-- output registere signals
out_reg_aclr <= iareset WHEN output_async_reset = "clear" ELSE '1';
out_reg_apreset <= iareset WHEN output_async_reset = "preset" ELSE '1';
outreg_sreset_is_used <= '0' WHEN output_sync_reset = "none" ELSE '1';
outreg_sreset <= '0' WHEN output_sync_reset = "clear" ELSE '1';
-- oe register signals
oe_reg_aclr <= iareset WHEN oe_async_reset = "clear" ELSE '1';
oe_reg_apreset <= iareset WHEN oe_async_reset = "preset" ELSE '1';
oereg_sreset_is_used <= '0' WHEN oe_sync_reset = "none" ELSE '1';
oereg_sreset <= '0' WHEN oe_sync_reset = "clear" ELSE '1';
-- input register signals
in_reg_aclr <= iareset WHEN input_async_reset = "clear" ELSE '1';
in_reg_apreset <= iareset WHEN input_async_reset = "preset" ELSE '1';
inreg_sreset_is_used <= '0' WHEN input_sync_reset = "none" ELSE '1';
inreg_sreset <= '0' WHEN input_sync_reset = "clear" ELSE '1';
-- oe and output register clock enable signals
out_reg_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_reg_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
-- input register
inreg_mux_sel <= isreset AND inreg_sreset_is_used;
input_dffe_aclr <= in_reg_aclr AND devclrn AND (input_reg_pu_low OR devpor);
input_dffe_apreset <= in_reg_apreset AND ( (NOT input_reg_pu_low) OR devpor);
-- differentialin
pad_or_differentialin <= differentialin WHEN use_differential_input = "true" ELSE padio;
inreg_D_mux : cycloneii_mux21
port map ( A => pad_or_differentialin,
B => inreg_sreset,
S => inreg_mux_sel,
MO=> inreg_D);
input_reg : cycloneii_dffe
port map (D => inreg_D,
CLRN => input_dffe_aclr,
PRN => input_dffe_apreset,
CLK => inclk,
ENA => inclkena,
Q => tmp_input_reg_out);
-- output register
outreg_mux_sel <= isreset AND outreg_sreset_is_used;
output_dffe_aclr <= out_reg_aclr AND devclrn AND (output_reg_pu_low OR devpor);
output_dffe_apreset <= out_reg_apreset AND ( (NOT output_reg_pu_low) OR devpor);
outreg_D_mux : cycloneii_mux21
port map ( A => datain,
B => outreg_sreset,
S => outreg_mux_sel,
MO=> outreg_D);
output_reg : cycloneii_dffe
port map (D => outreg_D,
CLRN => output_dffe_aclr,
PRN => output_dffe_apreset,
CLK => outclk,
ENA => out_reg_clk_ena,
Q => tmp_output_reg_out);
-- oe register
oereg_mux_sel <= isreset AND oereg_sreset_is_used;
oe_dffe_aclr <= oe_reg_aclr AND devclrn AND (oe_reg_pu_low OR devpor);
oe_dffe_apreset <= oe_reg_apreset AND ( (NOT oe_reg_pu_low) OR devpor);
oereg_D_mux : cycloneii_mux21
port map ( A => oe,
B => oereg_sreset,
S => oereg_mux_sel,
MO=> oereg_D);
oe_reg : cycloneii_dffe
port map (D => oereg_D,
CLRN => oe_dffe_aclr,
PRN => oe_dffe_apreset,
CLK => outclk,
ENA => oe_reg_clk_ena,
Q => tmp_oe_reg_out);
-- asynchrous block
tmp_oe <= tmp_oe_reg_out WHEN oe_reg_sel = '1' ELSE oe;
tmp_datain <= tmp_output_reg_out WHEN (is_bidir_or_output = '1' AND out_reg_sel = '1') ELSE datain;
asynch_inst : cycloneii_asynch_io
generic map (OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
USE_DIFFERENTIAL_INPUT => use_differential_input,
BUS_HOLD => bus_hold)
port map (datain => tmp_datain,
oe => tmp_oe,
regin => tmp_input_reg_out,
differentialin => differentialin,
differentialout => differentialout,
padio => padio,
combout => combout,
regout => regout);
end structure;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone II CLK DELAY CTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_clk_delay_ctrl is
generic (
behavioral_sim_delay : integer := 0;
delay_chain : STRING := "54";
delay_chain_mode : STRING := "static";
uses_calibration : STRING := "false";
use_new_style_dq_detection : STRING := "false";
tan_delay_under_delay_ctrl_signal : STRING := "unused";
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
lpm_type : STRING := "cycloneii_clk_delay_ctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_clkout : VitalDelayType01 := DefPropDelay01;
tpd_pllcalibrateclkdelayedin_clkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01;
tipd_pllcalibrateclkdelayedin : VitalDelayType01 := DefPropDelay01
);
port (
clk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
disablecalibration : in std_logic := '1';
pllcalibrateclkdelayedin: in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
clkout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_clk_delay_ctrl : entity is TRUE;
end cycloneii_clk_delay_ctrl;
architecture vital_clk_delay_ctrl of cycloneii_clk_delay_ctrl is
attribute VITAL_LEVEL0 of vital_clk_delay_ctrl : architecture is TRUE;
type cycloneii_clkdlyctrl_int_vec is array (natural range <>) of integer;
signal clk_ipd : std_logic;
signal delayctrlin_ipd : std_logic_vector(5 downto 0);
signal disablecalibration_ipd : std_logic;
signal pllcalibrateclkdelayedin_ipd : std_logic := '0';
signal dqs_dynamic_dly_si : integer := 0;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (delayctrlin_ipd(0), delayctrlin(0), tipd_delayctrlin(0));
VitalWireDelay (delayctrlin_ipd(1), delayctrlin(1), tipd_delayctrlin(1));
VitalWireDelay (delayctrlin_ipd(2), delayctrlin(2), tipd_delayctrlin(2));
VitalWireDelay (delayctrlin_ipd(3), delayctrlin(3), tipd_delayctrlin(3));
VitalWireDelay (delayctrlin_ipd(4), delayctrlin(4), tipd_delayctrlin(4));
VitalWireDelay (delayctrlin_ipd(5), delayctrlin(5), tipd_delayctrlin(5));
VitalWireDelay (disablecalibration_ipd, disablecalibration, tipd_disablecalibration);
VitalWireDelay (pllcalibrateclkdelayedin_ipd, pllcalibrateclkdelayedin, tipd_pllcalibrateclkdelayedin);
end block;
-- generate dynamic delay table and dynamic delay
process(delayctrlin_ipd)
variable init : boolean := true;
variable i : natural := 0;
variable w_index_l : integer := 0;
variable sim_dly_all : std_logic_vector(2047 downto 0) := (OTHERS => '0');
variable dly_table : cycloneii_clkdlyctrl_int_vec(63 downto 0) := (OTHERS => 0);
variable dly_index : integer := 0;
begin
if (init) then
sim_dly_all := delay_ctrl_sim_delay_63_48 & delay_ctrl_sim_delay_47_32 & delay_ctrl_sim_delay_31_16 & delay_ctrl_sim_delay_15_0;
while ( i < 64 ) loop
w_index_l := 32*i;
dly_table(i) := conv_integer(sim_dly_all((w_index_l + 31) downto w_index_l));
i := i + 1;
end loop;
init := false;
end if;
dly_index := conv_integer(delayctrlin_ipd);
if (dly_index >= 0 and dly_index < 64) then
dqs_dynamic_dly_si <= dly_table(dly_index);
end if;
end process;
VITAL: process(clk_ipd, pllcalibrateclkdelayedin_ipd, disablecalibration_ipd)
variable clkout_VitalGlitchData : VitalGlitchDataType;
variable clkout_delay : VitalDelayType01 := (0 ps, 0 ps);
variable use_calib_clk : std_logic := '0';
variable clkout_tmp : std_logic := '0';
begin
if ((uses_calibration = "true") and (disablecalibration_ipd = '0')) then
use_calib_clk := '1';
clkout_tmp := pllcalibrateclkdelayedin_ipd;
clkout_delay := tpd_pllcalibrateclkdelayedin_clkout;
else
use_calib_clk := '0';
clkout_tmp := clk_ipd;
if (delay_chain_mode = "static") then
clkout_delay := tpd_clk_clkout; -- contains behavioral_sim_delay in timing sim
for i in clkout_delay'range loop
clkout_delay(i) := clkout_delay(i) + (behavioral_sim_delay * 1 ps);
end loop;
elsif (delay_chain_mode = "dynamic") then
clkout_delay := (0 ps, 0 ps);
for i in clkout_delay'range loop
clkout_delay(i) := clkout_delay(i) + (dqs_dynamic_dly_si * 1 ps);
end loop;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => clkout_tmp,
Paths => (0 => (pllcalibrateclkdelayedin_ipd'last_event, clkout_delay, use_calib_clk = '1'),
1 => (clk_ipd'last_event, clkout_delay, use_calib_clk = '0')),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_clk_delay_ctrl;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone II CLK DELAY Calibration CTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLK_DELAY_CAL_CTRL ATOM Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
entity cycloneii_clk_delay_cal_ctrl is
generic (
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
lpm_type : STRING := "cycloneii_clk_delay_cal_ctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_plldataclk_calibratedata : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_calibratedata : VitalDelayType01 := DefPropDelay01;
tpd_pllcalibrateclk_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
tipd_plldataclk : VitalDelayType01 := DefPropDelay01;
tipd_pllcalibrateclk : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01
);
port (
plldataclk : in std_logic := '0';
pllcalibrateclk : in std_logic := '0';
disablecalibration : in std_logic := '1';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
calibratedata : out std_logic;
pllcalibrateclkdelayedout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_clk_delay_cal_ctrl : entity is TRUE;
end cycloneii_clk_delay_cal_ctrl;
architecture vital_clk_delay_cal_ctrl of cycloneii_clk_delay_cal_ctrl is
attribute VITAL_LEVEL0 of vital_clk_delay_cal_ctrl : architecture is TRUE;
type cycloneii_clkdlycal_int_vec is array (natural range <>) of integer;
signal plldataclk_ipd : std_logic := '0';
signal pllcalibrateclk_ipd : std_logic := '0';
signal delayctrlin_ipd : std_logic_vector(5 downto 0) := "000000";
signal disablecalibration_ipd : std_logic := '0';
signal cal_clk_prev : std_logic := 'X';
signal cal_data_prev : std_logic := 'X';
signal by2_areset : std_logic := '0';
signal cal_clk_by2_s : std_logic := '0';
signal cal_data_by2_s : std_logic := '0';
signal dqs_dynamic_dly_si : integer := 0;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (plldataclk_ipd, plldataclk, tipd_plldataclk);
VitalWireDelay (pllcalibrateclk_ipd, pllcalibrateclk, tipd_pllcalibrateclk);
VitalWireDelay (delayctrlin_ipd(0), delayctrlin(0), tipd_delayctrlin(0));
VitalWireDelay (delayctrlin_ipd(1), delayctrlin(1), tipd_delayctrlin(1));
VitalWireDelay (delayctrlin_ipd(2), delayctrlin(2), tipd_delayctrlin(2));
VitalWireDelay (delayctrlin_ipd(3), delayctrlin(3), tipd_delayctrlin(3));
VitalWireDelay (delayctrlin_ipd(4), delayctrlin(4), tipd_delayctrlin(4));
VitalWireDelay (delayctrlin_ipd(5), delayctrlin(5), tipd_delayctrlin(5));
VitalWireDelay (disablecalibration_ipd, disablecalibration, tipd_disablecalibration);
end block;
-- generate dynamic delay table and dynamic delay
process(delayctrlin_ipd)
variable init : boolean := true;
variable i : natural := 0;
variable w_index_l : integer := 0;
variable sim_dly_all : std_logic_vector(2047 downto 0) := (OTHERS => '0');
variable dly_table : cycloneii_clkdlycal_int_vec(63 downto 0) := (OTHERS => 0);
variable dly_index : integer := 0;
begin
if (init) then
i := 0;
sim_dly_all := delay_ctrl_sim_delay_63_48 & delay_ctrl_sim_delay_47_32 & delay_ctrl_sim_delay_31_16 & delay_ctrl_sim_delay_15_0;
while ( i < 64 ) loop
w_index_l := 32*i;
dly_table(i) := conv_integer(sim_dly_all((w_index_l + 31) downto w_index_l));
i := i + 1;
end loop;
init := false;
end if;
dly_index := conv_integer(delayctrlin_ipd);
if (dly_index >= 0 and dly_index < 64) then
dqs_dynamic_dly_si <= dly_table(dly_index);
end if;
end process;
-- internal clocks
by2_areset <= disablecalibration_ipd or (NOT devclrn) or (NOT devpor);
process(pllcalibrateclk_ipd, by2_areset)
begin
if (by2_areset = '1' and by2_areset'event) then
cal_clk_prev <= 'X';
cal_clk_by2_s <= '0';
elsif (by2_areset /= '1' and pllcalibrateclk_ipd'event) then
cal_clk_prev <= pllcalibrateclk_ipd;
if (pllcalibrateclk_ipd = '1' and cal_clk_prev /= 'X') then
cal_clk_by2_s <= not cal_clk_by2_s;
end if;
end if;
end process;
process(plldataclk_ipd, by2_areset)
begin
if (by2_areset = '1' and by2_areset'event) then
cal_data_by2_s <= '0';
cal_data_prev <= 'X';
elsif (by2_areset /= '1' and plldataclk_ipd'event) then
cal_data_prev <= plldataclk_ipd;
if (plldataclk_ipd = '1' and cal_data_prev /= 'X') then
cal_data_by2_s <= not cal_data_by2_s;
end if;
end if;
end process;
-- timing and delay
VITAL: process(plldataclk_ipd, pllcalibrateclk_ipd, by2_areset, cal_data_by2_s, cal_clk_by2_s)
variable calibratedata_VitalGlitchData : VitalGlitchDataType;
variable pllcalibrateclkdelayedout_VitalGlitchData : VitalGlitchDataType;
variable calclkout_delay : VitalDelayType01 := (0 ps, 0 ps);
begin
calclkout_delay := (0 ps, 0 ps); -- included in delay chain
for i in calclkout_delay'range loop
calclkout_delay(i) := calclkout_delay(i) + (dqs_dynamic_dly_si * 1 ps);
end loop;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => calibratedata,
OutSignalName => "calibratedata",
OutTemp => cal_data_by2_s,
Paths => (0 => (by2_areset'last_event, tpd_disablecalibration_calibratedata, (by2_areset = '1')),
1 => (plldataclk_ipd'last_event, tpd_plldataclk_calibratedata, (by2_areset = '0'))),
GlitchData => calibratedata_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => pllcalibrateclkdelayedout,
OutSignalName => "pllcalibrateclkdelayedout",
OutTemp => cal_clk_by2_s,
Paths => (0 => (by2_areset'last_event, calclkout_delay, (by2_areset = '1')),
1 => (pllcalibrateclk_ipd'last_event, calclkout_delay, (by2_areset = '0'))),
GlitchData => pllcalibrateclkdelayedout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_clk_delay_cal_ctrl;
-----------------------------------------------------------------------
--
-- Module Name : cycloneii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneii_atom_pack.all;
ENTITY cycloneii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneii_mac_data_reg;
ARCHITECTURE vital_cycloneii_mac_data_reg OF cycloneii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneii_atom_pack.all;
ENTITY cycloneii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneii_mac_sign_reg;
ARCHITECTURE cycloneii_mac_sign_reg OF cycloneii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneii_atom_pack.all;
ENTITY cycloneii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneii_mac_mult_internal;
ARCHITECTURE vital_cycloneii_mac_mult_internal OF cycloneii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneii_atom_pack.all;
USE work.cycloneii_mac_data_reg;
USE work.cycloneii_mac_sign_reg;
USE work.cycloneii_mac_mult_internal;
ENTITY cycloneii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneii_mac_mult;
ARCHITECTURE vital_cycloneii_mac_mult OF cycloneii_mac_mult IS
COMPONENT cycloneii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneii_atom_pack.all;
ENTITY cycloneii_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneii_mac_out;
ARCHITECTURE vital_cycloneii_mac_out OF cycloneii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneii_mac_out;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
ENTITY cycloneii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_ena_reg : entity is TRUE;
end cycloneii_ena_reg;
ARCHITECTURE behave of cycloneii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone II CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneii_atom_pack.all;
use work.cycloneii_ena_reg;
entity cycloneii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneii_clkctrl : entity is TRUE;
end cycloneii_clkctrl;
architecture vital_clkctrl of cycloneii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg_out
);
ena_out <= cereg_out WHEN (ena_register_mode = "falling edge") ELSE ena_ipd;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
| gpl-3.0 | e4fb2f06501a8750f35074dc76e44200 | 0.495989 | 3.885745 | false | false | false | false |
thoralt/KCVGA | FPGA/FIFO_testbench.vhd | 1 | 4,192 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FIFO_testbench IS
END FIFO_testbench;
ARCHITECTURE behavior OF FIFO_testbench IS
-- inputs
SIGNAL clk : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC := '0';
SIGNAL wr_en : STD_LOGIC := '0';
SIGNAL wr_data : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_en : STD_LOGIC := '0';
-- outputs
SIGNAL rd_data : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL empty : STD_LOGIC;
SIGNAL full : STD_LOGIC;
-- clock period definitions
CONSTANT clk_period : TIME := 10 ns;
BEGIN
-- instantiate the Unit Under Test (UUT)
uut : ENTITY work.FIFO GENERIC
MAP (
RAM_WIDTH => 4,
RAM_DEPTH => 5
) PORT MAP
(
clk => clk,
rst => rst,
wr_en => wr_en,
wr_data => wr_data,
rd_en => rd_en,
rd_data => rd_data,
empty => empty,
full => full
);
-- clock process definitions
clk_process : PROCESS
BEGIN
clk <= '0';
WAIT FOR clk_period/2;
clk <= '1';
WAIT FOR clk_period/2;
END PROCESS;
-- stimulus process
stim_proc : PROCESS
BEGIN
-- hold reset state for 100 ns.
WAIT FOR 100 ns;
rst <= '1';
WAIT FOR clk_period * 10;
rst <= '0';
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "1100";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0011";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "1111";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0000";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0001";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "1010";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "1010";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "1010";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
WAIT;
END PROCESS;
END;
| mit | ca6a2a0e4e62ac446b1f766acf41507d | 0.430582 | 3.543533 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_dmem_ctrl.vhd | 1 | 8,275 | -------------------------------------------------------------------------------
--
-- The Data memory controller.
--
-- $Id: t400_dmem_ctrl.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_dmem_ctrl is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
dmem_op_i : in dmem_op_t;
b_op_i : in b_op_t;
dec_data_i : in dec_data_t;
a_i : in dw_t;
q_high_i : in dw_t;
b_o : out b_t;
-- Data Memory Interface --------------------------------------------------
dm_addr_o : out dm_addr_t;
dm_data_i : in dw_t;
dm_data_o : out dw_t;
dm_we_o : out std_logic
);
end t400_dmem_ctrl;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_dmem_ctrl is
signal br_q : unsigned(br_range_t);
signal bd_q : unsigned(bd_range_t);
begin
-----------------------------------------------------------------------------
-- Process b_reg
--
-- Purpose:
-- Implements the B register.
--
b_reg: process (ck_i, por_i)
begin
if por_i then
br_q <= (others => '0');
bd_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
br_q <= (others => '0');
bd_q <= (others => '0');
elsif ck_en_i then
case b_op_i is
-- Set Bd from accumulator ------------------------------------------
when B_SET_BD =>
bd_q <= unsigned(a_i);
-- Set Br from accumulator ------------------------------------------
when B_SET_BR =>
br_q <= unsigned(a_i(1 downto 0));
-- Set Br and Bd from decoder data ----------------------------------
when B_SET_B =>
br_q <= unsigned(dec_data_i(br_range_t));
bd_q <= unsigned(dec_data_i(bd_range_t));
-- Set Br and Bd from decoder data, increment value for Bd ----------
when B_SET_B_INC =>
br_q <= unsigned(dec_data_i(br_range_t));
bd_q <= unsigned(dec_data_i(bd_range_t)) + 1;
-- XOR Br with decoder data -----------------------------------------
when B_XOR_BR =>
br_q <= br_q xor unsigned(dec_data_i(br_range_t));
-- Increment Bd -----------------------------------------------------
when B_INC_BD =>
bd_q <= bd_q + 1;
-- Increment Bd -----------------------------------------------------
when B_DEC_BD =>
bd_q <= bd_q - 1;
when others =>
null;
end case;
end if;
end if;
end process b_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_mux
--
-- Purpose:
-- Multiplexes the data for writing to the memory.
--
data_mux: process (dmem_op_i,
br_q, bd_q,
a_i,
q_high_i,
dec_data_i,
dm_data_i,
ck_en_i)
variable dm_addr_v : dm_addr_t;
variable dm_data_v : dw_t;
variable dm_we_v : std_logic;
variable bd_v : std_logic_vector(2 downto 0);
begin
-- default assignment
dm_addr_v(br_range_t) := std_logic_vector(br_q);
dm_addr_v(bd_range_t) := std_logic_vector(bd_q);
dm_data_v := (others => '0');
dm_we_v := '0';
case dmem_op_i is
-- Read data memory, indexed by B ---------------------------------------
when DMEM_RB =>
null;
-- Write data memory, indexed by B, source is Q -------------------------
when DMEM_WB_SRC_Q =>
dm_we_v := '1';
dm_data_v := q_high_i;
-- Write data memory, indexed by B, source is decoder data --------------
when DMEM_WB_SRC_DEC =>
dm_we_v := '1';
dm_data_v := dec_data_i(bd_range_t);
-- Write data memory, indexed by B, source is accumulator ---------------
when DMEM_WB_SRC_A =>
dm_we_v := '1';
dm_data_v := a_i;
-- Read data memory, indexed by decoder data ----------------------------
when DMEM_RDEC =>
dm_addr_v := dec_data_i(br_range_t'high downto 0);
-- Write data memory, indexed by decoder data, source is accumulator ----
when DMEM_WDEC_SRC_A =>
dm_we_v := '1';
dm_addr_v := dec_data_i(br_range_t'high downto 0);
dm_data_v := a_i;
-- Write data memory, indexed by B, set bit -----------------------------
when DMEM_WB_SET_BIT =>
dm_we_v := '1';
dm_data_v := dm_data_i or dec_data_i(dw_range_t);
-- Write data memory, indexed by B, reset bit ---------------------------
when DMEM_WB_RES_BIT =>
dm_we_v := '1';
dm_data_v := dm_data_i and not dec_data_i(dw_range_t);
when others =>
null;
end case;
-- adjust address vector for 41xL family members
if opt_type_g = t400_opt_type_410_c then
dm_addr_v := '0' & dm_addr_v(br_range_t) &
dm_addr_v(bd_range_t'high-1 downto 0);
end if;
dm_addr_o <= dm_addr_v;
if ck_en_i then
dm_we_o <= dm_we_v;
else
dm_we_o <= '0';
end if;
dm_data_o <= dm_data_v;
end process data_mux;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
b_o(br_range_t) <= std_logic_vector(br_q);
b_o(bd_range_t) <= std_logic_vector(bd_q);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 28d08df17ebf0f66fb1195ab009ecadc | 0.477462 | 3.934855 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/uart_fifo.vhd | 1 | 7,020 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: uart_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY uart_fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END uart_fifo;
ARCHITECTURE SYN OF uart_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(23 DOWNTO 0);
usedw <= sub_wire3(8 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "MAX 10",
lpm_numwords => 512,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 24,
lpm_widthu => 9,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2,
usedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "24"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "24"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: usedw 0 0 9 0 OUTPUT NODEFVAL "usedw[8..0]"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
-- Retrieval info: CONNECT: usedw 0 0 9 0 @usedw 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| apache-2.0 | 24dd73d8dc203fe5cc7fd512941d9d34 | 0.664957 | 3.522328 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cyclone_components.vhd | 1 | 25,219 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cyclone_atom_pack.all;
package cyclone_components is
--
-- cyclone_lcell
--
COMPONENT cyclone_lcell
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "cyclone_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
--
-- cyclone_ram_block
--
COMPONENT cyclone_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "cyclone_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cyclone_pll
--
COMPONENT cyclone_pll
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "cyclone_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
family_name : string := "Cyclone";
skip_vco : string := "off";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END COMPONENT;
--
-- cyclone_jtag
--
COMPONENT cyclone_jtag
generic (
lpm_type : string := "cyclone_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cyclone_crcblock
--
COMPONENT cyclone_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cyclone_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cyclone_routing_wire
--
COMPONENT cyclone_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cyclone_io
--
COMPONENT cyclone_io
generic (
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
lpm_type : STRING := "cyclone_io"
);
port (
datain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
padio : inout std_logic
);
END COMPONENT;
--
-- cyclone_asmiblock
--
COMPONENT cyclone_asmiblock
generic (
lpm_type : string := "cyclone_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
END COMPONENT;
end cyclone_components;
| gpl-3.0 | 1d6cee23b667a6096bd4978296d70359 | 0.409215 | 4.383626 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_xlconcat_0_0/sim/base_zynq_design_xlconcat_0_0.vhd | 1 | 7,853 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY base_zynq_design_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END base_zynq_design_xlconcat_0_0;
ARCHITECTURE base_zynq_design_xlconcat_0_0_arch OF base_zynq_design_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT xlconcat;
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 1,
NUM_PORTS => 1
)
PORT MAP (
In0 => In0,
In1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END base_zynq_design_xlconcat_0_0_arch;
| gpl-3.0 | 4848cee951056ecf4460095664c86cb9 | 0.632752 | 3.371833 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/pci32lite/pcidec.vhd | 1 | 7,981 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: pcidec.vhd |
--| |
--| Project: pci32tLite |
--| |
--| Description: PCI decoder and PCI signals loader. |
--| * LoaD signals: "ad" -> adr, cbe -> cmd. |
--| * Decode memory and configuration space. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pcidec is
generic (
BARS : string := "1BARMEM"
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
-- pci
ad_i : in std_logic_vector(31 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
idsel_i : in std_logic;
-- control
bar0_i : in std_logic_vector(31 downto 9);
memEN_i : in std_logic;
ioEN_i : in std_logic;
pciadrLD_i : in std_logic;
adrcfg_o : out std_logic;
adrmem_o : out std_logic;
adr_o : out std_logic_vector(24 downto 0);
cmd_o : out std_logic_vector(3 downto 0)
);
end pcidec;
architecture rtl of pcidec is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal adr : std_logic_vector(31 downto 0);
signal cmd : std_logic_vector(3 downto 0);
signal idsel_s : std_logic;
signal a1 : std_logic;
signal a0 : std_logic;
begin
--+-------------------------------------------------------------------------+
--| Load PCI Signals |
--+-------------------------------------------------------------------------+
PCILD: process( rst_i, clk_i, ad_i, cbe_i, idsel_i )
begin
if( rst_i = '1' ) then
adr <= ( others => '1' );
cmd <= ( others => '1' );
idsel_s <= '0';
elsif( rising_edge(clk_i) ) then
if ( pciadrLD_i = '1' ) then
adr <= ad_i;
cmd <= cbe_i;
idsel_s <= idsel_i;
end if;
end if;
end process PCILD;
--+-------------------------------------------------------------------------+
--| Decoder |
--+-------------------------------------------------------------------------+
barmem_g: if (BARS="1BARMEM") generate
adrmem_o <= '1' when ( ( memEN_i = '1' )
and ( adr(31 downto 25) = bar0_i(31 downto 25) )
and ( adr(1 downto 0) = "00" )
and ( cmd(3 downto 1) = "011" ) )
else '0';
end generate;
bario_g: if (BARS="1BARIO") generate
adrmem_o <= '1' when ( ( ioEN_i = '1' )
and ( adr(31 downto 16) = "0000000000000000")
and ( adr(15 downto 9) = bar0_i(15 downto 9) )
and ( cmd(3 downto 1) = "001" ) )
else '0';
end generate;
adrcfg_o <= '1' when ( ( idsel_s = '1' )
and ( adr(1 downto 0) = "00" )
and ( cmd(3 downto 1) = "101" ) )
else '0';
--+-------------------------------------------------------------------------+
--| Adresses WB A(1)/A(0) |
--+-------------------------------------------------------------------------+
barmema1a0_g: if (BARS="1BARMEM") generate
a1 <= cbe_i(1) and cbe_i(0);
a0 <= cbe_i(2) and cbe_i(0);
end generate;
barioa1a0_g: if (BARS="1BARIO") generate
a1 <= adr(1);
a0 <= adr(0);
end generate;
--+-------------------------------------------------------------------------+
--| Other outs |
--+-------------------------------------------------------------------------+
adr_o <= adr(24 downto 2) & a1 & a0;
cmd_o <= cmd;
end rtl;
| gpl-3.0 | 9f871b1ef28cd7794278823a5b1e0d3f | 0.269014 | 5.808588 | false | false | false | false |
alvieboy/xtc-base | wb_master_np_to_slave_p.vhd | 1 | 2,049 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end entity wb_master_np_to_slave_p;
architecture behave of wb_master_np_to_slave_p is
type state_type is ( idle, wait_for_ack );
signal state: state_type;
begin
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
state <= idle;
else
case state is
when idle =>
if m_wb_cyc_i='1' and m_wb_stb_i='1' and s_wb_stall_i='0' then
state <= wait_for_ack;
end if;
when wait_for_ack =>
if s_wb_ack_i='1' then
state <= idle;
end if;
when others =>
end case;
end if;
end if;
end process;
s_wb_stb_o <= m_wb_stb_i when state=idle else '0';
s_wb_dat_o <= m_wb_dat_i;
s_wb_adr_o <= m_wb_adr_i;
s_wb_sel_o <= m_wb_sel_i;
s_wb_cti_o <= m_wb_cti_i;
s_wb_we_o <= m_wb_we_i;
s_wb_cyc_o <= m_wb_cyc_i;
m_wb_dat_o <= s_wb_dat_i;
m_wb_ack_o <= s_wb_ack_i;
end behave;
| bsd-3-clause | f21ba0c97c2ed176f7582ca9aab09358 | 0.594924 | 2.48665 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiv_pcie_hip_components.vhd | 1 | 71,791 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package CYCLONEIV_PCIE_HIP_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function alpha_tolower (given_string : string) return string;
-- GENERIC utility functions END
--
-- cycloneiv_pciehip_pciexp_dcfiforam
--
COMPONENT cycloneiv_pciehip_pciexp_dcfiforam
GENERIC (
addr_width : INTEGER := 4;
data_width : INTEGER := 32
);
PORT (
data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
wrclock : IN STD_LOGIC;
rdclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiv_hssi_pcie_hip
--
COMPONENT cycloneiv_hssi_pcie_hip
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrpl : VitalDelayType01 := DefpropDelay01;
tipd_bistscanen : VitalDelayType01 := DefpropDelay01;
tipd_bistscanin : VitalDelayType01 := DefpropDelay01;
tipd_bisttesten : VitalDelayType01 := DefpropDelay01;
tipd_coreclkin : VitalDelayType01 := DefpropDelay01;
tipd_corecrst : VitalDelayType01 := DefpropDelay01;
tipd_corepor : VitalDelayType01 := DefpropDelay01;
tipd_corerst : VitalDelayType01 := DefpropDelay01;
tipd_coresrst : VitalDelayType01 := DefpropDelay01;
tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cplpending : VitalDelayType01 := DefpropDelay01;
tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01;
tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01;
tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01;
tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01;
tipd_dlreqwake : VitalDelayType01 := DefpropDelay01;
tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01;
tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01;
tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01;
tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01;
tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmirden : VitalDelayType01 := DefpropDelay01;
tipd_lmiwren : VitalDelayType01 := DefpropDelay01;
tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanen : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanin : VitalDelayType01 := DefpropDelay01;
tipd_pclkcentral : VitalDelayType01 := DefpropDelay01;
tipd_pclkch0 : VitalDelayType01 := DefpropDelay01;
tipd_phyrst : VitalDelayType01 := DefpropDelay01;
tipd_physrst : VitalDelayType01 := DefpropDelay01;
tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pldclk : VitalDelayType01 := DefpropDelay01;
tipd_pldrst : VitalDelayType01 := DefpropDelay01;
tipd_pldsrst : VitalDelayType01 := DefpropDelay01;
tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanen : VitalDelayType01 := DefpropDelay01;
tipd_scanmoden : VitalDelayType01 := DefpropDelay01;
tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappintasts : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmevent : VitalDelayType01 := DefpropDelay01;
tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01;
tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01;
tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_type : STRING := "cycloneiv_hssi_pcie_hip";
advanced_errors : STRING := "false";
allow_rx_valid_empty : STRING := "false"; -- july3,2008
bar0_64bit_mem_space : STRING := "true";
bar0_io_space : STRING := "false";
bar0_prefetchable : STRING := "true";
bar0_size_mask : INTEGER := 32;
bar1_64bit_mem_space : STRING := "false";
bar1_io_space : STRING := "false";
bar1_prefetchable : STRING := "false";
bar1_size_mask : INTEGER := 4;
bar2_64bit_mem_space : STRING := "false";
bar2_io_space : STRING := "false";
bar2_prefetchable : STRING := "false";
bar2_size_mask : INTEGER := 4;
bar3_64bit_mem_space : STRING := "false";
bar3_io_space : STRING := "false";
bar3_prefetchable : STRING := "false";
bar3_size_mask : INTEGER := 4;
bar4_64bit_mem_space : STRING := "false";
bar4_io_space : STRING := "false";
bar4_prefetchable : STRING := "false";
bar4_size_mask : INTEGER := 4;
bar5_64bit_mem_space : STRING := "false";
bar5_io_space : STRING := "false";
bar5_prefetchable : STRING := "false";
bar5_size_mask : INTEGER := 4;
bar_io_window_size : STRING := "NONE";
bar_prefetchable : INTEGER := 0;
base_address : INTEGER := 0;
bridge_port_ssid_support : STRING := "false";
bridge_port_vga_enable : STRING := "false";
bypass_cdc : STRING := "false";
bypass_tl : STRING := "false";
class_code : INTEGER := 16711680;
completion_timeout : STRING := "ABCD";
core_clk_divider : INTEGER := 1;
core_clk_source : STRING := "PLL_FIXED_CLK";
credit_buffer_allocation_aux : STRING := "BALANCED";
deemphasis_enable : STRING := "false";
device_address : INTEGER := 0;
device_id : INTEGER := 1;
device_number : INTEGER := 0;
diffclock_nfts_count : INTEGER := 128;
disable_async_l2_logic : STRING := "false"; -- july2,2008
disable_cdc_clk_ppm : STRING := "true";
disable_device_number_mismatch : STRING := "false";
disable_link_x2_support : STRING := "false";
disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
dll_active_report_support : STRING := "false";
ei_delay_powerdown_count : INTEGER := 10;
eie_before_nfts_count : INTEGER := 4;
enable_adapter_half_rate_mode : STRING := "false";
enable_ch0_pclk_out : STRING := "false";
enable_completion_timeout_disable : STRING := "true";
enable_coreclk_out_half_rate : STRING := "false";
enable_d1pm_support : STRING := "false";
enable_d2pm_support : STRING := "false";
enable_ecrc_check : STRING := "false";
enable_ecrc_gen : STRING := "false";
enable_function_msi_support : STRING := "true";
enable_function_msix_support : STRING := "false";
enable_gen2_core : STRING := "true";
enable_hip_x1_loopback : STRING := "false";
enable_l1_aspm : STRING := "false";
enable_msi_64bit_addressing : STRING := "true";
enable_msi_masking : STRING := "false";
enable_rcv0buf_a_we : STRING := "true";
enable_rcv0buf_b_re : STRING := "true";
enable_rcv0buf_output_regs : STRING := "false";
enable_rcv1buf_a_we : STRING := "true";
enable_rcv1buf_b_re : STRING := "true";
enable_rcv1buf_output_regs : STRING := "false";
enable_retrybuf_a_we : STRING := "true";
enable_retrybuf_b_re : STRING := "true";
enable_retrybuf_ecc : STRING := "false"; -- ww12
enable_retrybuf_output_regs : STRING := "false";
enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx0buf_ecc : STRING := "false"; -- ww12
enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx1buf_ecc : STRING := "false"; -- ww12
enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx_buffer_checking : STRING := "false";
enable_rx_ei_l0s_exit_refined : STRING := "false";
enable_rx_reordering : STRING := "true";
enable_slot_register : STRING := "false";
endpoint_l0_latency : INTEGER := 0;
endpoint_l1_latency : INTEGER := 0;
expansion_base_address_register : INTEGER := 0;
extend_tag_field : STRING := "false";
fc_init_timer : INTEGER := 1024;
flow_control_timeout_count : INTEGER := 200;
flow_control_update_count : INTEGER := 30;
gen2_diffclock_nfts_count : INTEGER := 255;
gen2_lane_rate_mode : STRING := "false";
gen2_sameclock_nfts_count : INTEGER := 255;
hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
iei_logic : STRING := "IEI_IIIS";
indicator : INTEGER := 7;
l01_entry_latency : INTEGER := 31;
l0_exit_latency_diffclock : INTEGER := 6;
l0_exit_latency_sameclock : INTEGER := 6;
l1_exit_latency_diffclock : INTEGER := 0;
l1_exit_latency_sameclock : INTEGER := 0;
lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000";
low_priority_vc : INTEGER := 0;
max_link_width : INTEGER := 4;
max_payload_size : INTEGER := 2;
maximum_current : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
millisecond_cycle_count : INTEGER := 0;
mram_bist_settings : STRING := "";
msi_function_count : INTEGER := 2;
msix_pba_bir : INTEGER := 0;
msix_pba_offset : INTEGER := 0;
msix_table_bir : INTEGER := 0;
msix_table_offset : INTEGER := 0;
msix_table_size : INTEGER := 0;
no_command_completed : STRING := "true";
no_soft_reset : STRING := "false";
pcie_mode : STRING := "SHARED_MODE";
pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
port_link_number : INTEGER := 1;
port_address : INTEGER := 0;
register_pipe_signals : STRING := "false";
retry_buffer_last_active_address : INTEGER := 2047;
retry_buffer_memory_settings : INTEGER := 0;
revision_id : INTEGER := 1;
rx0_adap_fifo_full_value : INTEGER := 9;
rx1_adap_fifo_full_value : INTEGER := 9;
rx_cdc_full_value : INTEGER := 12;
rx_idl_os_count : INTEGER := 0;
rx_ptr0_nonposted_dpram_max : INTEGER := 0;
rx_ptr0_nonposted_dpram_min : INTEGER := 0;
rx_ptr0_posted_dpram_max : INTEGER := 0;
rx_ptr0_posted_dpram_min : INTEGER := 0;
rx_ptr1_nonposted_dpram_max : INTEGER := 0;
rx_ptr1_nonposted_dpram_min : INTEGER := 0;
rx_ptr1_posted_dpram_max : INTEGER := 0;
rx_ptr1_posted_dpram_min : INTEGER := 0;
sameclock_nfts_count : INTEGER := 128;
single_rx_detect : INTEGER := 0;
skp_os_schedule_count : INTEGER := 0;
slot_number : INTEGER := 0;
slot_power_limit : INTEGER := 0;
slot_power_scale : INTEGER := 0;
ssid : INTEGER := 0;
ssvid : INTEGER := 0;
subsystem_device_id : INTEGER := 1;
subsystem_vendor_id : INTEGER := 4466;
surprise_down_error_support : STRING := "false";
tx0_adap_fifo_full_value : INTEGER := 11;
tx1_adap_fifo_full_value : INTEGER := 11;
tx_cdc_full_value : INTEGER := 12;
tx_cdc_stop_dummy_full_value : INTEGER := 11;
use_crc_forwarding : STRING := "false";
vc0_clk_enable : STRING := "true";
vc0_rx_buffer_memory_settings : INTEGER := 0;
vc0_rx_flow_ctrl_compl_data : INTEGER := 448;
vc0_rx_flow_ctrl_compl_header : INTEGER := 112;
vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc0_rx_flow_ctrl_posted_data : INTEGER := 360;
vc0_rx_flow_ctrl_posted_header : INTEGER := 50;
vc1_clk_enable : STRING := "false";
vc1_rx_buffer_memory_settings : INTEGER := 0;
vc1_rx_flow_ctrl_compl_data : INTEGER := 448;
vc1_rx_flow_ctrl_compl_header : INTEGER := 112;
vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc1_rx_flow_ctrl_posted_data : INTEGER := 360;
vc1_rx_flow_ctrl_posted_header : INTEGER := 50;
vc_arbitration : INTEGER := 1;
vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
vendor_id : INTEGER := 4466
);
PORT (
bistenrcv0 : IN STD_LOGIC := '0';
bistenrcv1 : IN STD_LOGIC := '0';
bistenrpl : IN STD_LOGIC := '0';
bistscanen : IN STD_LOGIC := '0';
bistscanin : IN STD_LOGIC := '0';
bisttesten : IN STD_LOGIC := '0';
coreclkin : IN STD_LOGIC := '0';
corecrst : IN STD_LOGIC := '0';
corepor : IN STD_LOGIC := '0';
corerst : IN STD_LOGIC := '0';
coresrst : IN STD_LOGIC := '0';
cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
cplpending : IN STD_LOGIC := '0';
dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0');
dlaspmcr0 : IN STD_LOGIC := '0';
dlcomclkreg : IN STD_LOGIC := '0';
dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0');
dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlinhdllp : IN STD_LOGIC := '1';
dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlrequpfc : IN STD_LOGIC := '0';
dlreqwake : IN STD_LOGIC := '0';
dlrxecrcchk : IN STD_LOGIC := '0';
dlsndupfc : IN STD_LOGIC := '0';
dltxcfgextsy : IN STD_LOGIC := '0';
dltxreqpm : IN STD_LOGIC := '0';
dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0');
lmirden : IN STD_LOGIC := '0';
lmiwren : IN STD_LOGIC := '0';
mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
mramhiptestenable : IN STD_LOGIC := '0';
mramregscanen : IN STD_LOGIC := '0';
mramregscanin : IN STD_LOGIC := '0';
pclkcentral : IN STD_LOGIC := '0';
pclkch0 : IN STD_LOGIC := '0';
phyrst : IN STD_LOGIC := '0';
physrst : IN STD_LOGIC := '0';
phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
pldclk : IN STD_LOGIC := '0';
pldrst : IN STD_LOGIC := '0';
pldsrst : IN STD_LOGIC := '0';
pllfixedclk : IN STD_LOGIC := '0';
rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxmaskvc0 : IN STD_LOGIC := '0';
rxmaskvc1 : IN STD_LOGIC := '0';
rxreadyvc0 : IN STD_LOGIC := '0';
rxreadyvc1 : IN STD_LOGIC := '0';
rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
scanen : IN STD_LOGIC := '0';
scanmoden : IN STD_LOGIC := '0';
swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0');
tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappintasts : IN STD_LOGIC := '0';
tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappmsireq : IN STD_LOGIC := '0';
tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpmauxpwr : IN STD_LOGIC := '0';
tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
tlpmetocr : IN STD_LOGIC := '0';
tlpmevent : IN STD_LOGIC := '0';
tlslotclkcfg : IN STD_LOGIC := '0';
txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txeopvc00 : IN STD_LOGIC := '0';
txeopvc01 : IN STD_LOGIC := '0';
txeopvc10 : IN STD_LOGIC := '0';
txeopvc11 : IN STD_LOGIC := '0';
txerrvc0 : IN STD_LOGIC := '0';
txerrvc1 : IN STD_LOGIC := '0';
txsopvc00 : IN STD_LOGIC := '0';
txsopvc01 : IN STD_LOGIC := '0';
txsopvc10 : IN STD_LOGIC := '0';
txsopvc11 : IN STD_LOGIC := '0';
txvalidvc0 : IN STD_LOGIC := '0';
txvalidvc1 : IN STD_LOGIC := '0';
bistdonearcv0 : OUT STD_LOGIC;
bistdonearcv1 : OUT STD_LOGIC;
bistdonearpl : OUT STD_LOGIC;
bistdonebrcv0 : OUT STD_LOGIC;
bistdonebrcv1 : OUT STD_LOGIC;
bistdonebrpl : OUT STD_LOGIC;
bistpassrcv0 : OUT STD_LOGIC;
bistpassrcv1 : OUT STD_LOGIC;
bistpassrpl : OUT STD_LOGIC;
bistscanoutrcv0 : OUT STD_LOGIC;
bistscanoutrcv1 : OUT STD_LOGIC;
bistscanoutrpl : OUT STD_LOGIC;
clrrxpath : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataenablen : OUT STD_LOGIC;
derrcorextrcv0 : OUT STD_LOGIC;
derrcorextrcv1 : OUT STD_LOGIC;
derrcorextrpl : OUT STD_LOGIC;
derrrpl : OUT STD_LOGIC;
dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dlackrequpfc : OUT STD_LOGIC;
dlacksndupfc : OUT STD_LOGIC;
dlcurrentdeemp : OUT STD_LOGIC;
dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dldllreq : OUT STD_LOGIC;
dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlerrphy : OUT STD_LOGIC;
dllinkautobdwstatus : OUT STD_LOGIC;
dllinkbdwmngstatus : OUT STD_LOGIC;
dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlrpbufemp : OUT STD_LOGIC;
dlrstentercompbit : OUT STD_LOGIC;
dlrsttxmarginfield : OUT STD_LOGIC;
dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
dlrxvalpm : OUT STD_LOGIC;
dltxackpm : OUT STD_LOGIC;
dlup : OUT STD_LOGIC;
dlupexit : OUT STD_LOGIC;
dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC;
dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
ev128ns : OUT STD_LOGIC;
ev1us : OUT STD_LOGIC;
extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0);
gen2rate : OUT STD_LOGIC;
gen2rategnd : OUT STD_LOGIC;
hotrstexit : OUT STD_LOGIC;
intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
l2exit : OUT STD_LOGIC;
laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
linkup : OUT STD_LOGIC;
lmiack : OUT STD_LOGIC;
lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
ltssml0state : OUT STD_LOGIC;
mramregscanout : OUT STD_LOGIC;
powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0);
resetstatus : OUT STD_LOGIC;
rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxeopvc00 : OUT STD_LOGIC;
rxeopvc01 : OUT STD_LOGIC;
rxeopvc10 : OUT STD_LOGIC;
rxeopvc11 : OUT STD_LOGIC;
rxerrvc0 : OUT STD_LOGIC;
rxerrvc1 : OUT STD_LOGIC;
rxfifoemptyvc0 : OUT STD_LOGIC;
rxfifoemptyvc1 : OUT STD_LOGIC;
rxfifofullvc0 : OUT STD_LOGIC;
rxfifofullvc1 : OUT STD_LOGIC;
rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxsopvc00 : OUT STD_LOGIC;
rxsopvc01 : OUT STD_LOGIC;
rxsopvc10 : OUT STD_LOGIC;
rxsopvc11 : OUT STD_LOGIC;
rxvalidvc0 : OUT STD_LOGIC;
rxvalidvc1 : OUT STD_LOGIC;
r2cerr0ext : OUT STD_LOGIC;
serrout : OUT STD_LOGIC;
successspeednegoint : OUT STD_LOGIC;
swdnwake : OUT STD_LOGIC;
swuphotrst : OUT STD_LOGIC;
testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
tlappintaack : OUT STD_LOGIC;
tlappmsiack : OUT STD_LOGIC;
tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
tlcfgctlwr : OUT STD_LOGIC;
tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0);
tlcfgstswr : OUT STD_LOGIC;
tlpmetosr : OUT STD_LOGIC;
txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txfifoemptyvc0 : OUT STD_LOGIC;
txfifoemptyvc1 : OUT STD_LOGIC;
txfifofullvc0 : OUT STD_LOGIC;
txfifofullvc1 : OUT STD_LOGIC;
txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
txreadyvc0 : OUT STD_LOGIC;
txreadyvc1 : OUT STD_LOGIC;
wakeoen : OUT STD_LOGIC
);
END COMPONENT;
end cycloneiv_pcie_hip_components;
package body CYCLONEIV_PCIE_HIP_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
end CYCLONEIV_PCIE_HIP_COMPONENTS;
| gpl-3.0 | cb2ba3d9c01f6c0f4a2db420ebca5ecd | 0.522781 | 4.300665 | false | false | false | false |
alvieboy/xtc-base | mux32_2.vhd | 1 | 468 | library ieee;
use ieee.std_logic_1164.all;
entity mux32_2 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
sel: in std_logic;
o: out std_logic_vector(31 downto 0)
);
end entity mux32_2;
architecture behave of mux32_2 is
begin
process(i0,i1,sel)
begin
case sel is
when '0' => o <= i0;
when '1' => o <= i1;
when others => o <= (others => 'X');
end case;
end process;
end behave;
| bsd-3-clause | 73716ad99d2119edfa6835be38fa1de6 | 0.600427 | 2.853659 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneive_components.vhd | 1 | 37,941 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneive_atom_pack.all;
package cycloneive_components is
--
-- cycloneive_lcell_comb
--
COMPONENT cycloneive_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneive_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneive_routing_wire
--
COMPONENT cycloneive_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneive_pll
--
COMPONENT cycloneive_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneive_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
family_name : string := "Cycloneive";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneive_ff
--
COMPONENT cycloneive_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneive_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- cycloneive_ram_block
--
COMPONENT cycloneive_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneive_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneive_mac_mult
--
COMPONENT cycloneive_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneive_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_mac_out
--
COMPONENT cycloneive_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneive_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_io_ibuf
--
COMPONENT cycloneive_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneive_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- cycloneive_io_obuf
--
COMPONENT cycloneive_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneive_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneive_ddio_oe
--
COMPONENT cycloneive_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneive_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_ddio_out
--
COMPONENT cycloneive_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneive_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneive_pseudo_diff_out
--
COMPONENT cycloneive_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneive_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneive_io_pad
--
COMPONENT cycloneive_io_pad
GENERIC (
lpm_type : string := "cycloneive_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- cycloneive_clkctrl
--
COMPONENT cycloneive_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneive_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- cycloneive_rublock
--
COMPONENT cycloneive_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneive_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneive_apfcontroller
--
COMPONENT cycloneive_apfcontroller
generic
(
lpm_type: string := "cycloneive_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
END COMPONENT;
--
-- cycloneive_termination
--
COMPONENT cycloneive_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneive_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- cycloneive_jtag
--
COMPONENT cycloneive_jtag
generic (
lpm_type : string := "cycloneive_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneive_crcblock
--
COMPONENT cycloneive_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneive_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneive_oscillator
--
COMPONENT cycloneive_oscillator
generic
(
lpm_type: string := "cycloneive_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
END COMPONENT;
end cycloneive_components;
| gpl-3.0 | 23f8351db705eff468e9fe3b050583b8 | 0.474711 | 4.334133 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiv_hssi_components.vhd | 1 | 79,371 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package CYCLONEIV_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function rx_top_basic_width (channel_width : integer) return integer;
function rx_top_num_of_basic (channel_width : integer) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function alpha_tolower (given_string : string) return string;
function cycloneiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string;
function cycloneiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer;
function cycloneiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- cycloneiv_hssi_tx_pma
--
COMPONENT cycloneiv_hssi_tx_pma
GENERIC (
enable_diagnostic_loopback : STRING := "false";
enable_reverse_serial_loopback : STRING := "false";
enable_txclkout_loopback : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_tx_pma";
channel_number : INTEGER := 0;
common_mode : STRING := "0.65V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
logical_channel_address : INTEGER := 0;
preemp_tap_1 : INTEGER := 0;
protocol_hint : STRING := "basic";
effective_data_rate : STRING := "unused";
rx_detect : INTEGER := 0;
serialization_factor : INTEGER := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_rx_detect : STRING := "false";
vod_selection : INTEGER := 0
);
PORT (
cgbpowerdn : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
detectrxpowerdown : IN STD_LOGIC := '0';
diagnosticlpbkin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
fastrefclk0in : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC := '0';
refclk0inpulse : IN STD_LOGIC := '0';
reverselpbkin : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
txpmareset : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- cycloneiv_hssi_rx_pma
--
COMPONENT cycloneiv_hssi_rx_pma
GENERIC (
lpm_type : STRING := "cycloneiv_hssi_rx_pma";
allow_serial_loopback : STRING := "false";
channel_number : INTEGER := 0;
common_mode : STRING := "0.82V";
deserialization_factor : INTEGER := 8;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_local_divider : STRING := "false";
enable_dpa_shift : STRING := "false";
enable_initial_phase_selection : STRING := "false";
enable_pd_counter_accumulate_mode : STRING := "false";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
eq_dc_gain : INTEGER := 0;
eq_setting : INTEGER := 1;
force_signal_detect : STRING := "true";
initial_phase_value : INTEGER := 0;
logical_channel_address : INTEGER := 0;
offset_cancellation : INTEGER := 0;
pi_frequency_selector : INTEGER := 0;
ppm_gen1_2_xcnt_en : INTEGER := 1;
ppm_post_eidle : INTEGER := 0;
pd1_counter_setting : INTEGER := 5;
pd2_counter_setting : INTEGER := 5;
pd_rising_edge_only : STRING := "false";
phase_step_add_setting : INTEGER := 2;
phase_step_sub_setting : INTEGER := 1;
ppmselect : INTEGER := 0;
protocol_hint : STRING := "basic";
effective_data_rate : STRING := "unused";
send_reverse_serial_loopback_data : STRING := "false";
send_reverse_serial_loopback_recovered_clk : STRING := "false";
signal_detect_hysteresis : INTEGER := 4;
signal_detect_hysteresis_valid_threshold : INTEGER := 1;
signal_detect_loss_threshold : INTEGER := 1;
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
loop_1_digital_filter : INTEGER := 8;
enable_second_order_loop : STRING := "false"
);
PORT (
crupowerdn : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
deserclock : IN STD_LOGIC := '0';
dpashift : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
rxpmareset : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
testbussel : IN STD_LOGIC_VECTOR(3 DOWNTO 0):= (others => '0');
analogtestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clockout : OUT STD_LOGIC;
datastrobeout : OUT STD_LOGIC;
diagnosticlpbkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locktorefout : OUT STD_LOGIC;
recoverdataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
signaldetect : OUT STD_LOGIC
);
END COMPONENT;
--
-- cycloneiv_hssi_tx_pcs
--
COMPONENT cycloneiv_hssi_tx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01;
tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_freezptr : VitalDelayType01 := DefpropDelay01;
tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01;
tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_pipetxswing : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "cycloneiv_hssi_tx_pcs";
allow_polarity_inversion : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none"; -- none, x8, x4
channel_number : INTEGER := 0;
channel_width : INTEGER := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL=
datapath_protocol : STRING := "basic"; --replaced by protocol_hint
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none"; -- legacy, new, none
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6>
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "true";
enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL=
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "incremental";
use_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "core_clk" -- INT_CLK // int_clk
);
PORT (
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0');
coreclk : IN STD_LOGIC := '0';
ctrlenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); --fix_width
forceelecidle : IN STD_LOGIC := '0';
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
invpol : IN STD_LOGIC := '0';
localrefclk : IN STD_LOGIC := '0';
phfiforddisable : IN STD_LOGIC := '0';
phfiforeset : IN STD_LOGIC := '0';
phfifowrenable : IN STD_LOGIC := '1';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipestatetransdone : IN STD_LOGIC := '0';
pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
xgmctrl : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hiptxclkout : OUT STD_LOGIC;
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfiforddisableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenableout : OUT STD_LOGIC;
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rdenablesync : OUT STD_LOGIC;
txdetectrx : OUT STD_LOGIC;
xgmctrlenable : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiv_hssi_rx_pcs
--
COMPONENT cycloneiv_hssi_rx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_alignstatussync : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_elecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_enabyteord : VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hippowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_parallelfdbk : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipepowerstate : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_recoveredclk : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01;
tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena : VitalDelayType01 := DefpropDelay01;
tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01;
tipd_rxfound : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_signaldetected : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_byteorderalignstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_pipestatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "cycloneiv_hssi_rx_pcs";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- <true/false>;
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode
byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165
cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : INTEGER := 0;
cdrctrl_min_lock_to_ref_cycle : INTEGER := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none"; -- <none, x4, x8>;
channel_number : INTEGER := 0; -- <integer 0-3>;
channel_width : INTEGER := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
clk2_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
clk_pd_enable : STRING := "false"; --ww47_cram_p1
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic"; -- <basic/pipe/xaui> replaced by protocol_hint
dec_8b_10b_compatibility_mode : STRING := "true";
dec_8b_10b_mode : STRING := "none"; -- <normal/cascaded/none>;
deskew_pattern : STRING := "1100111100"; -- K28.3
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_num_com_detect : INTEGER := 0;
enable_bit_reversal : STRING := "false";
enable_self_test_mode : STRING := "false";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : INTEGER := 0; -- <integer 0-3>;
insert_pad_on_underflow : STRING := "false";
logical_channel_address : INTEGER := 0;
num_align_code_groups_in_ordered_set : INTEGER := 1; -- <integer 0-3>;
num_align_cons_good_data : INTEGER := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : INTEGER := 4; -- <Integer 1-256>;
num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
phystatus_delay : INTEGER := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : INTEGER := 13;
rate_match_empty_threshold : INTEGER := 5;
rate_match_fifo_mode : STRING := "false"; -- <normal/cascaded/generic/cascaded_generic/none> in s2gx, bool in s4gx;
rate_match_full_threshold : INTEGER := 20;
rate_match_insert_threshold : INTEGER := 11;
rate_match_ordered_set_based : STRING := "false"; -- <integer 10 or 20>;
rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern_size : INTEGER := 10; -- <integer 10 or 20>;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : INTEGER := 7;
rd_clk_mux_select : STRING := "int clock"; -- <INT_CLK, CORE_CLK>;
recovered_clk_mux_select : STRING := "recovered clock"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
reset_clock_output_during_digital_reset : STRING := "false";
run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : INTEGER := 32;
rxstatus_error_report_mode : INTEGER := 0;
self_test_mode : STRING := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
test_bus_sel : INTEGER := 0;
use_alignment_state_machine : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"
);
PORT (
a1a2size : IN STD_LOGIC := '0';
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
bitslip : IN STD_LOGIC := '0';
cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr
coreclk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); --NEW: updated width
digitalreset : IN STD_LOGIC := '0';
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
fifordin : IN STD_LOGIC := '0';
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch
invpol : IN STD_LOGIC := '0';
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
phfifordenable : IN STD_LOGIC := '1';
phfiforeset : IN STD_LOGIC := '0';
phfifowrdisable : IN STD_LOGIC := '0';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en
quadreset : IN STD_LOGIC := '0';
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
rmfifordena : IN STD_LOGIC := '0';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '0';
rxdetectvalid : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
signaldetected : IN STD_LOGIC := '0';
xauidelcondmet : IN STD_LOGIC := '0';
xauififoovr : IN STD_LOGIC := '0';
xauiinsertincomplete : IN STD_LOGIC := '0';
xauilatencycomp : IN STD_LOGIC := '0';
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins ---
wareset : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0');
a1a2sizeout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a1detect : OUT STD_LOGIC;
a2detect : OUT STD_LOGIC;
adetectdeskew : OUT STD_LOGIC;
alignstatussyncout : OUT STD_LOGIC;
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD?
cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR.
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
ctrldetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- new in 6.1
disperr : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
errdetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
fifordout : OUT STD_LOGIC;
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0)
hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid
hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle
hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0)
k1detect : OUT STD_LOGIC;
k2detect : OUT STD_LOGIC;
patterndetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifounderflow : OUT STD_LOGIC;
phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipephydonestatus : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rdalign : OUT STD_LOGIC;
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
runningdisp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
signaldetect : OUT STD_LOGIC;
syncstatus : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
xauidelcondmetout : OUT STD_LOGIC;
xauififoovrout : OUT STD_LOGIC;
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
pipestatetransdoneout : OUT STD_LOGIC
);
END COMPONENT;
--
-- cycloneiv_hssi_cmu
--
COMPONENT cycloneiv_hssi_cmu
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanclk : VitalDelayType01 := DefpropDelay01;
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_scanmode : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_txcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01;
tipd_scanshift : VitalDelayType01 := DefpropDelay01;
tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01;
tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "cycloneiv_hssi_cmu";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
coreclk_out_gated_by_quad_reset : STRING := "false"; -- cycloneiv_new
devaddr : INTEGER := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
portaddr : INTEGER := 1;
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx_xaui_sm_backward_compatible_enable : STRING := "false";
select_refclk_dig : STRING := "false"; -- cycloneiv_new
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "int clock";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_coreclk_out_post_divider : STRING := "false"; -- cycloneiv_new
use_deskew_fifo : STRING := "false";
rx_logical_to_physical_mapping : INTEGER := 0;
tx_logical_to_physical_mapping : INTEGER := 0;
pll_logical_to_physical_mapping : INTEGER := 0;
rx0_logical_to_physical_mapping : INTEGER := 0;
rx1_logical_to_physical_mapping : INTEGER := 1;
rx2_logical_to_physical_mapping : INTEGER := 2;
rx3_logical_to_physical_mapping : INTEGER := 3;
tx0_logical_to_physical_mapping : INTEGER := 0;
tx1_logical_to_physical_mapping : INTEGER := 1;
tx2_logical_to_physical_mapping : INTEGER := 2;
tx3_logical_to_physical_mapping : INTEGER := 3;
sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps
sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs
);
PORT (
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
fixedclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47
quadreset : IN STD_LOGIC := '0';
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rdenablesync : IN STD_LOGIC := '0';
recovclk : IN STD_LOGIC := '0';
refclkdig : IN STD_LOGIC := '0'; -- cycloneiv_new
rxanalogreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxcoreclk : IN STD_LOGIC := '0';
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0');
rxphfifordenable : IN STD_LOGIC := '0';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0');
rxpowerdown : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
scanclk : IN STD_LOGIC := '0';
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(1999 DOWNTO 0) := (others => '0');
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0');
alignstatus : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; -- stnngray_new
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpriodisableout : OUT STD_LOGIC;
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
quadresetout : OUT STD_LOGIC;
refclkout : OUT STD_LOGIC; -- cycloneiv_new
rxanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcrupowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0);
testout : OUT STD_LOGIC_VECTOR(2399 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiv_hssi_calibration_block
--
COMPONENT cycloneiv_hssi_calibration_block
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_clk : VitalDelayType01 := DefpropDelay01;
lpm_type : string := "cycloneiv_hssi_calibration_block";
cont_cal_mode : string := "false";
enable_rx_cal_tw : string := "false";
enable_tx_cal_tw : string := "false";
migrated_from_prev_family : string := "false";
rtest : string := "false";
rx_cal_wt_value : integer := 0;
send_rx_cal_status : string := "true";
tx_cal_wt_value : integer := 1);
PORT (
clk : IN std_logic := '0';
powerdn : IN std_logic := '0';
testctrl : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
nonusertocmu : OUT std_logic
);
END COMPONENT;
end cycloneiv_hssi_components;
package body CYCLONEIV_HSSI_COMPONENTS is
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function rx_top_basic_width (channel_width : integer) return integer is
variable basic_width : integer;
begin
if (channel_width mod 10 = 0) then
basic_width := 10;
else
basic_width := 8;
end if;
return(basic_width);
end rx_top_basic_width;
function rx_top_num_of_basic (channel_width : integer) return integer is
variable num_of_basic : integer;
begin
if (channel_width mod 10 = 0) then
num_of_basic := channel_width/10;
else
num_of_basic := channel_width/8;
end if;
return(num_of_basic);
end rx_top_num_of_basic;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
function cycloneiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is
begin
CASE ph_fifo_xn_select IS
WHEN 0 => RETURN ph_fifo_xn_mapping0;
WHEN 1 => RETURN ph_fifo_xn_mapping1;
WHEN 2 => RETURN ph_fifo_xn_mapping2;
WHEN OTHERS => RETURN "none";
END CASE;
end cycloneiv_tx_pcs_mph_fifo_xn_mapping;
function cycloneiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end cycloneiv_tx_pcs_mphfifo_index;
function cycloneiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end cycloneiv_tx_pcs_miqp_phfifo_index;
end CYCLONEIV_HSSI_COMPONENTS;
| gpl-3.0 | e6fe7eca65dc3edf87c987fd912c0ea3 | 0.492006 | 4.481452 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiv_atoms.vhd | 1 | 936,517 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixiv_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixiv_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixiv_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiv_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixiv_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixiv_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixiv_pllpack;
package body stratixiv_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixiv_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiv_dffe : entity is TRUE;
end stratixiv_dffe;
-- architecture body --
architecture behave of stratixiv_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixiv_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixiv_mux21 : entity is TRUE;
end stratixiv_mux21;
architecture AltVITAL of stratixiv_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiv_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_mux41 : entity is TRUE;
end stratixiv_mux41;
architecture AltVITAL of stratixiv_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiv_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiv_atom_pack.all;
-- entity declaration --
entity stratixiv_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiv_and1 : entity is TRUE;
end stratixiv_and1;
-- architecture body --
architecture AltVITAL of stratixiv_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : stratixiv_jtag
--
-- Description : Stratix JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_jtag is
generic (
lpm_type : string := "stratixiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixiv_jtag;
architecture architecture_jtag of stratixiv_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixiv_crcblock
--
-- Description : Stratix CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_crcblock is
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiv_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratixiv_crcblock;
architecture architecture_crcblock of stratixiv_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratixiv_lcell_comb
--
-- Description : STRATIXIV LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_lcell_comb : entity is TRUE;
end stratixiv_lcell_comb;
architecture vital_lcell_comb of stratixiv_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : stratixiv_routing_wire
--
-- Description : STRATIXIV Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_routing_wire : entity is TRUE;
end stratixiv_routing_wire;
ARCHITECTURE behave of stratixiv_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixiv_lvds_tx_reg : ENTITY is TRUE;
END stratixiv_lvds_tx_reg;
ARCHITECTURE vital_stratixiv_lvds_tx_reg of stratixiv_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_stratixiv_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiv_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiv_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the STRATIXIV
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE std.textio.all;
ENTITY stratixiv_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixiv_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixiv_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiv_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE std.textio.all;
ENTITY stratixiv_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixiv_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixiv_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiv_lvds_transmitter
--
-- Description : Timing simulation model for the STRATIXIV LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) STRATIXIV_lvds_tx_parallel_register and
-- 3) STRATIXIV_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE std.textio.all;
USE work.stratixiv_lvds_tx_parallel_register;
USE work.stratixiv_lvds_tx_out_block;
USE work.stratixiv_lvds_tx_reg;
ENTITY stratixiv_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- STRATIXIV
tx_output_path_delay_engineering_bits : Integer := -1; -- STRATIXIV
enable_dpaclk_to_lvdsout : string := "off"; -- STRATIXIV
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiv_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- STRATIXIV
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- STRATIXIV
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- STRATIXIV
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixiv_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixiv_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;-- STRATIXIV
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixiv_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixiv_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixiv_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);-- STRATIXIV
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixiv_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixiv_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixiv_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd, -- STRATIXIV
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then-- STRATIXIV
dataout_tmp := dpaclkin_ipd;-- STRATIXIV
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then -- STRATIXIV
VitalPathDelay01 ( -- STRATIXIV
OutSignal => dataout, -- STRATIXIV
OutSignalName => "DATAOUT", -- STRATIXIV
OutTemp => dataout_tmp, -- STRATIXIV
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)), -- STRATIXIV
GlitchData => dataout_VitalGlitchData, -- STRATIXIV
Mode => DefGlitchMode, -- STRATIXIV
XOn => XOn, -- STRATIXIV
MsgOn => MsgOn ); -- STRATIXIV
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--
--
-- STRATIXIV_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiv_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end stratixiv_rublock;
architecture architecture_rublock of stratixiv_rublock is
begin
end architecture_rublock;
----------------------------------------------------------------------------
-- Module Name : stratixiv_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixiv_ram_register;
ARCHITECTURE reg_arch OF stratixiv_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixiv_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiv_ram_pulse_generator:ENTITY IS TRUE;
END stratixiv_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiv_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE work.stratixiv_ram_register;
USE work.stratixiv_ram_pulse_generator;
ENTITY stratixiv_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixiv_ram_block;
ARCHITECTURE block_arch OF stratixiv_ram_block IS
COMPONENT stratixiv_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiv_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : stratixiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : stratixiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : stratixiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : stratixiv_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixiv_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixiv_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : stratixiv_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : stratixiv_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : stratixiv_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixiv_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixiv_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixiv_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : stratixiv_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : stratixiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : stratixiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : stratixiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : stratixiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : stratixiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : stratixiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : stratixiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixiv_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixiv_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiv_ff
--
-- Description : STRATIXIV FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_and1;
entity stratixiv_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_ff : entity is TRUE;
end stratixiv_ff;
architecture vital_lcell_ff of stratixiv_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixiv_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: stratixiv_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: stratixiv_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: stratixiv_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for STRATIXIV CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXIV_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_clkselect is
generic (
lpm_type : STRING := "stratixiv_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_clkselect : entity is TRUE;
end stratixiv_clkselect;
architecture vital_clkselect of stratixiv_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- stratixiv_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiv_atom_pack.all;
-- entity declaration --
entity stratixiv_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiv_and2 : entity is TRUE;
end stratixiv_and2;
-- architecture body --
architecture AltVITAL of stratixiv_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiv_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_ena_reg : entity is TRUE;
end stratixiv_ena_reg;
ARCHITECTURE behave of stratixiv_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for STRATIXIV CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXIV_CLKENA Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_ena_reg;
use work.stratixiv_and2;
entity stratixiv_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiv_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_clkena : entity is TRUE;
end stratixiv_clkena;
architecture vital_clkena of stratixiv_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component stratixiv_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component stratixiv_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : stratixiv_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : stratixiv_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : stratixiv_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : stratixiv_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Module Name : stratixiv_mlab_cell_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_mlab_cell_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiv_mlab_cell_pulse_generator:ENTITY IS TRUE;
END stratixiv_mlab_cell_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiv_mlab_cell_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE work.stratixiv_mlab_cell_pulse_generator;
ENTITY stratixiv_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiv_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END stratixiv_mlab_cell;
ARCHITECTURE block_arch OF stratixiv_mlab_cell IS
COMPONENT stratixiv_mlab_cell_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
-- -------- internal signals ---------
-- Write address
SIGNAL write_address : INTEGER := 0;
SIGNAL read_address : INTEGER := 0;
-- pulses
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
SIGNAL mask_vector : mask_write := (
normal => (OTHERS => '0'),
inverse => (OTHERS => 'X')
);
-- output
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_write IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END LOOP;
RETURN mask;
END get_mask;
SIGNAL clk0_ipd : STD_LOGIC;
SIGNAL ena0_ipd : STD_LOGIC;
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0';
BEGIN
-- interconnect delays
WireDelay : BLOCK
BEGIN
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
END GENERATE;
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
END GENERATE;
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
END BLOCK;
-- setup/hold checks
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd,clk0_ipd,ena0_ipd)
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
BEGIN
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_enable,
TimingData => TimingData_clk_enable,
TestSignal => ena0_ipd,
TestSignalName => "ena0",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_ena0_clk0_noedge_posedge,
SetupLow => tsetup_ena0_clk0_noedge_posedge,
HoldHigh => thold_ena0_clk0_noedge_posedge,
HoldLow => thold_ena0_clk0_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_address,
TimingData => TimingData_clk_address,
TestSignal => portaaddr_ipd,
TestSignalName => "portaaddr",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
HoldLow => thold_portaaddr_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_bemasks,
TimingData => TimingData_clk_bemasks,
TestSignal => portabyteenamasks_ipd,
TestSignalName => "portabyteenamasks",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
END PROCESS setup_hold_checks;
-- latch CE signal
PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
-- output path delay
PROCESS (portbaddr_ipd)
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
CQDelay := SelectDelay(
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
);
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
END PROCESS;
-- memory initialization
init_mem <= TRUE;
write_clock <= NOT clk0_ipd;
write_address <= alt_conv_integer(portaaddr_ipd);
-- Write pulse generation (neg edge)
wpgen_a : stratixiv_mlab_cell_pulse_generator
PORT MAP (
clk => write_clock,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (portabyteenamasks_ipd)
VARIABLE mask : mask_write;
BEGIN
IF (portabyteenamasks_ipd'EVENT) THEN
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
mask_vector <= mask;
END IF;
END PROCESS mask_create;
mem_rw : PROCESS (init_mem, write_pulse)
-- mem init
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_word_type;
BEGIN
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
END LOOP;
mem(write_address) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(normal)(i) = '0') THEN
mem(write_address)(i) <= portadatain(i);
mem_data_p(i) := portadatain(i);
ELSIF (mask_vector(inverse)(i) = 'X') THEN
mem(write_address)(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS mem_rw;
-- Continuous read
portbdataout <= mem(read_address);
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiv_io_ibuf
--
-- Description : STRATIXIV IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END stratixiv_io_ibuf;
ARCHITECTURE arch OF stratixiv_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiv_io_obuf
--
-- Description : STRATIXIV IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiv_io_obuf;
ARCHITECTURE arch OF stratixiv_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
SIGNAL parallelterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
g2 :for i in parallelterminationcontrol'range generate
VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : stratixiv_ddio_in
--
-- Description : STRATIXIV DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiv_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiv_ddio_in;
ARCHITECTURE arch OF stratixiv_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiv_ddio_oe
--
-- Description : STRATIXIV DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiv_ddio_oe;
ARCHITECTURE arch OF stratixiv_ddio_oe IS
component stratixiv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : stratixiv_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiv_ddio_out
--
-- Description : STRATIXIV DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiv_ddio_out;
ARCHITECTURE arch OF stratixiv_ddio_out IS
component stratixiv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : stratixiv_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: stratixiv_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY stratixiv_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END stratixiv_rt_sm;
ARCHITECTURE stratixiv_rt_sm_rtl OF stratixiv_rt_sm IS
CONSTANT STRATIXIV_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT STRATIXIV_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT STRATIXIV_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT STRATIXIV_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT STRATIXIV_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT STRATIXIV_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT STRATIXIV_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT STRATIXIV_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT STRATIXIV_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= STRATIXIV_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN STRATIXIV_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= STRATIXIV_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIV_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIV_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= STRATIXIV_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIV_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= STRATIXIV_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIV_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= STRATIXIV_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= STRATIXIV_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIV_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIV_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIV_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIV_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN STRATIXIV_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIV_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIV_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIV_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN STRATIXIV_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN STRATIXIV_RTOCT_DONE =>
next_state <= STRATIXIV_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= STRATIXIV_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END stratixiv_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: stratixiv_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY stratixiv_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END stratixiv_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF stratixiv_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiv_termination
--
-- Description : STRATIXIV Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiv_atom_pack.all;
USE WORK.stratixiv_termination_aux_clock_div;
USE WORK.stratixiv_rt_sm;
ENTITY stratixiv_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END stratixiv_termination;
ARCHITECTURE stratixiv_oct_arch OF stratixiv_termination IS
COMPONENT stratixiv_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiv_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : stratixiv_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : stratixiv_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END stratixiv_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiv_termination_logic
--
-- Description : STRATIXIV Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiv_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END stratixiv_termination_logic;
ARCHITECTURE stratixiv_oct_logic_arch OF stratixiv_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END stratixiv_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package stratixiv_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end stratixiv_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiv_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end stratixiv_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiv_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiv_dll_gray_encoder;
ARCHITECTURE stratixiv_dll_gray_encoder_arch OF stratixiv_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END stratixiv_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiv_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiv_dll_gray_decoder;
ARCHITECTURE stratixiv_dll_gray_decoder_arch OF stratixiv_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END stratixiv_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiv_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_dll_gray_decoder;
ENTITY stratixiv_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END stratixiv_ddr_delay_chain_s;
ARCHITECTURE stratixiv_ddr_delay_chain_s_arch OF stratixiv_ddr_delay_chain_s IS
COMPONENT stratixiv_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : stratixiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END stratixiv_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiv_ddr_io_reg : entity is TRUE;
end stratixiv_ddr_io_reg;
architecture vital_stratixiv_ddr_io_reg of stratixiv_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_stratixiv_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiv_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : STRATIXIV_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_pllpack.all;
use work.stratixiv_atom_ddr_pack.all;
use work.stratixiv_dll_gray_encoder;
ENTITY stratixiv_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiv_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END stratixiv_dll;
ARCHITECTURE vital_tgxdll of stratixiv_dll is
COMPONENT stratixiv_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in stratixiv
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in stratixiv
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in stratixiv
signal pc_comp_range : integer := 0; -- new in stratixiv
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : stratixiv_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in stratixiv
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_tgxdll;
-------------------------------------------------------------------------------
--
-- Entity Name : STRATIXIV_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
USE work.stratixiv_pllpack.all;
use work.stratixiv_atom_ddr_pack.all;
use work.stratixiv_dll_gray_encoder;
use work.stratixiv_dll_gray_decoder;
ENTITY stratixiv_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiv_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END stratixiv_dll_offset_ctrl;
ARCHITECTURE vital_tgxoffset of stratixiv_dll_offset_ctrl is
COMPONENT stratixiv_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiv_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : stratixiv_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : stratixiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : stratixiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : stratixiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_tgxoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_dll_gray_decoder;
ENTITY stratixiv_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiv_dqs_delay_chain_arch OF stratixiv_dqs_delay_chain IS
-- component section
COMPONENT stratixiv_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : stratixiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : stratixiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiv_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_dqs_enable IS
GENERIC (
lpm_type : string := "stratixiv_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE stratixiv_dqs_enable_arch OF stratixiv_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiv_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_ddr_io_reg;
use work.stratixiv_ddr_delay_chain_s;
ENTITY stratixiv_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE stratixiv_dqs_enable_ctrl_arch OF stratixiv_dqs_enable_ctrl IS
-- component section
COMPONENT stratixiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : stratixiv_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : stratixiv_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : stratixiv_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : stratixiv_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiv_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiv_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiv_delay_chain_arch OF stratixiv_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END stratixiv_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_ddr_delay_chain_s;
ENTITY stratixiv_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE stratixiv_io_clock_divider_arch OF stratixiv_io_clock_divider IS
-- component section
COMPONENT stratixiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END stratixiv_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_ddr_io_reg;
use work.stratixiv_ddr_delay_chain_s;
ENTITY stratixiv_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiv_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE stratixiv_output_phase_alignment_arch OF stratixiv_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT stratixiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : stratixiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : stratixiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiv_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_ddr_io_reg;
use work.stratixiv_ddr_delay_chain_s;
ENTITY stratixiv_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE stratixiv_input_phase_alignment_arch OF stratixiv_input_phase_alignment IS
-- component section
COMPONENT stratixiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : stratixiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiv_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
use work.stratixiv_ddr_io_reg;
ENTITY stratixiv_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiv_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiv_half_rate_input_arch OF stratixiv_half_rate_input IS
-- component section
component stratixiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : stratixiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END stratixiv_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiv_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiv_io_config_arch OF stratixiv_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiv_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiv_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiv_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiv_dqs_config_arch OF stratixiv_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiv_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiv_mac_bit_register --
-- Description: STRATIXIV MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiv_mac_bit_register;
ARCHITECTURE arch OF stratixiv_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiv_mac_register --
-- Description: STRATIXIV MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END stratixiv_mac_register;
ARCHITECTURE arch OF stratixiv_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiv_mac_multiplier --
-- Description: STRATIXIV MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END stratixiv_mac_multiplier;
ARCHITECTURE arch OF stratixiv_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiv_mac_mult_atom --
-- Description: Simulation model for stratixiv mac mult atom. --
-- This model instantiates the following components. --
-- 1.stratixiv_mac_bit_register. --
-- 2.stratixiv_mac_register. --
-- 3.stratixiv_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiv_mac_mult;
ARCHITECTURE arch OF stratixiv_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT stratixiv_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiv_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiv_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : stratixiv_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : stratixiv_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : stratixiv_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : stratixiv_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_fsa_isse --
-- Description: STRATIXIV first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END stratixiv_fsa_isse;
ARCHITECTURE arch OF stratixiv_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_first_stage_add_sub --
-- Description: STRATIXIV First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiv_first_stage_add_sub;
ARCHITECTURE arch OF stratixiv_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_second_stage_add_accum --
-- Description: STRATIXIV Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END stratixiv_second_stage_add_accum;
ARCHITECTURE arch OF stratixiv_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_round_block --
-- Description: STRATIXIV round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiv_round_block;
ARCHITECTURE arch OF stratixiv_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_saturate_block --
-- Description: STRATIXIV saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END stratixiv_saturate_block;
ARCHITECTURE arch OF stratixiv_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
IF (round = '1') THEN
max(i) <= 'X';
min(i) <= 'X';
ELSE
max(i) <= '1';
min(i) <= '0';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
IF (round = '1') THEN
min(conv_integer(datain_width) - round_width) <= '1';
ELSE
min(0) <= '1';
END IF;
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_round_saturate_block --
-- Description: STRATIXIV round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.stratixiv_round_block. --
-- 2.stratixiv_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END stratixiv_round_saturate_block;
ARCHITECTURE arch OF stratixiv_round_saturate_block IS
COMPONENT stratixiv_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiv_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : stratixiv_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : stratixiv_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_rotate_shift_block --
-- Description: STRATIXIV roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiv_rotate_shift_block;
ARCHITECTURE arch OF stratixiv_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiv_carry_chain_adder --
-- Description: STRATIXIV carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END stratixiv_carry_chain_adder;
ARCHITECTURE arch OF stratixiv_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiv_mac_out_atom --
-- Description: Simulation model for stratixiv mac out atom --
-- This model instantiates the following components --
-- 1.stratixiv_mac_bit_register --
-- 2.stratixiv_mac_register --
-- 3.stratixiv_fsa_isse --
-- 4.stratixiv_first_stage_add_sub --
-- 5.stratixiv_second_stage_add_accum --
-- 6.stratixiv_round_saturate_block --
-- 7.stratixiv_rotate_shift_block --
-- 8.stratixiv_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiv_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiv_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END stratixiv_mac_out;
ARCHITECTURE arch OF stratixiv_mac_out IS
COMPONENT stratixiv_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiv_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiv_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiv_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiv_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiv_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiv_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiv_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : stratixiv_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : stratixiv_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : stratixiv_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : stratixiv_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : stratixiv_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : stratixiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : stratixiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : stratixiv_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : stratixiv_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : stratixiv_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : stratixiv_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : stratixiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : stratixiv_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : stratixiv_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : stratixiv_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : stratixiv_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : stratixiv_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : stratixiv_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : stratixiv_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : stratixiv_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : stratixiv_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : stratixiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : stratixiv_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : stratixiv_io_pad
-- Description : Simulation model for stratixiv IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiv_io_pad IS
GENERIC (
lpm_type : string := "stratixiv_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END stratixiv_io_pad;
ARCHITECTURE arch OF stratixiv_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiv_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the STRATIXIV PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiv_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixiv_mn_cntr;
ARCHITECTURE behave of stratixiv_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiv_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the STRATIXIV PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiv_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixiv_scale_cntr;
ARCHITECTURE behave of stratixiv_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiv_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixiv_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixiv_pll_reg;
ARCHITECTURE behave of stratixiv_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiv_pll
--
-- Description : Timing simulation model for the STRATIXIV PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixiv_atom_pack.all;
USE work.stratixiv_pllpack.all;
USE work.stratixiv_mn_cntr;
USE work.stratixiv_scale_cntr;
USE work.stratixiv_dffe;
USE work.stratixiv_pll_reg;
-- New Features : The list below outlines key new features in STRATIXIV:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY stratixiv_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiv_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "STRATIXIV";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END stratixiv_pll;
ARCHITECTURE vital_pll of stratixiv_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT stratixiv_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiv_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiv_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixiv_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : stratixiv_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : stratixiv_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : stratixiv_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixiv_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixiv_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixiv_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixiv_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixiv_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : stratixiv_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : stratixiv_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : stratixiv_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : stratixiv_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiv_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiv_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : stratixiv_asmiblock
--
-- Description : STRATIXIV ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_asmiblock is
generic (
lpm_type : string := "stratixiv_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end stratixiv_asmiblock;
architecture architecture_asmiblock of stratixiv_asmiblock is
begin
end architecture_asmiblock; -- end of stratixiv_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixiv_lvds_reg;
ARCHITECTURE vital_stratixiv_lvds_reg of stratixiv_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiv_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiv_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixiv_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE work.stratixiv_lvds_rx_fifo_sync_ram;
ENTITY stratixiv_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiv_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixiv_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixiv_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixiv_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE work.stratixiv_lvds_reg;
ENTITY stratixiv_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixiv_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixiv_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixiv_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixiv_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixiv_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_lvds_rx_deser
--
-- Description : Timing simulation model for the stratixiv LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiv_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixiv_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the stratixiv LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
ENTITY stratixiv_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiv_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixiv_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiv_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixiv_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END stratixiv_pclk_divider;
ARCHITECTURE arch OF stratixiv_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiv_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiv_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END stratixiv_select_ini_phase_dpaclk;
ARCHITECTURE trans OF stratixiv_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiv_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiv_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END stratixiv_dpa_retime_block;
ARCHITECTURE trans OF stratixiv_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiv_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.stratixiv_dpa_retime_block;
ENTITY stratixiv_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END stratixiv_dpa_block;
ARCHITECTURE trans OF stratixiv_dpa_block IS
COMPONENT stratixiv_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : stratixiv_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiv_LVDS_RECEIVER
--
-- Description : Timing simulation model for the stratixiv LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixiv_lvds_rx_fifo
-- 2) stratixiv_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixiv_lvds_rx_parallel_reg
-- 5) stratixiv_pclk_divider
-- 6) stratixiv_select_ini_phase_dpaclk
-- 7) stratixiv_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiv_atom_pack.all;
USE work.stratixiv_lvds_rx_bitslip;
USE work.stratixiv_lvds_rx_fifo;
USE work.stratixiv_lvds_rx_deser;
USE work.stratixiv_lvds_rx_parallel_reg;
USE work.stratixiv_lvds_reg;
USE work.stratixiv_pclk_divider;
USE work.stratixiv_select_ini_phase_dpaclk;
USE work.stratixiv_dpa_block;
ENTITY stratixiv_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiv_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiv_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixiv_lvds_receiver IS
COMPONENT stratixiv_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiv_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiv_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiv_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiv_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiv_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT stratixiv_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiv_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal in_reg_data_dly : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
signal ini_dpa_clk_dly : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
process(in_reg_data)
begin
if(dpaswitch_ipd = '1') then
if(rx_input_path_delay_engineering_bits = 1) then
in_reg_data_dly <= TRANSPORT in_reg_data after 60 ps;
elsif(rx_input_path_delay_engineering_bits = 2) then
in_reg_data_dly <= TRANSPORT in_reg_data after 120 ps;
elsif(rx_input_path_delay_engineering_bits = 3) then
in_reg_data_dly <= TRANSPORT in_reg_data after 180 ps;
else
in_reg_data_dly <= in_reg_data;
end if;
else
in_reg_data_dly <= in_reg_data;
end if;
end process;
xhdl_12 <= devclrn OR devpor;
process(ini_dpa_clk)
begin
ini_dpa_clk_dly <= ini_dpa_clk;
end process;
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixiv_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : stratixiv_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: stratixiv_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : stratixiv_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => ini_dpa_clk_dly,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixiv_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: stratixiv_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: stratixiv_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : stratixiv_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : stratixiv_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" ) else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : stratixiv_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : stratixiv_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixiv_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: stratixiv_pseudo_diff_out --
--Description: Simulation model for STRATIXIV Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiv_pseudo_diff_out;
ARCHITECTURE arch OF stratixiv_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : stratixiv_bias_logic
--
-- Description : STRATIXIV Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiv_bias_logic : ENTITY IS TRUE;
end stratixiv_bias_logic;
ARCHITECTURE vital_bias_logic of stratixiv_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : stratixiv_bias_generator
--
-- Description : STRATIXIV Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiv_bias_generator : ENTITY IS TRUE;
end stratixiv_bias_generator;
ARCHITECTURE vital_bias_generator of stratixiv_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 202;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : stratixiv_bias_block
--
-- Description : STRATIXIV Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
ENTITY stratixiv_bias_block IS
GENERIC (
lpm_type : string := "stratixiv_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiv_bias_block : ENTITY IS TRUE;
end stratixiv_bias_block;
ARCHITECTURE vital_bias_block of stratixiv_bias_block IS
COMPONENT stratixiv_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT stratixiv_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : stratixiv_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : stratixiv_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : stratixiv_tsdblock
--
-- Description : STRATIXIV TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiv_atom_pack.all;
entity stratixiv_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiv_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end stratixiv_tsdblock;
architecture architecture_tsdblock of stratixiv_tsdblock is
begin
end architecture_tsdblock; -- end of stratixiv_tsdblock
| gpl-3.0 | a0010a197f0209889877fcde193dba86 | 0.469212 | 4.156331 | false | false | false | false |
alvieboy/xtc-base | insnqueue.vhd | 1 | 2,773 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity insnqueue is
port (
rst: in std_logic;
clkw: in std_logic;
din: in std_logic_vector(15 downto 0);
en: in std_logic;
clr: in std_logic;
full: out std_logic;
clkr: in std_logic;
pop: in std_logic;
dualpop: in std_logic;
dout0: out std_logic_vector(15 downto 0);
dout1: out std_logic_vector(15 downto 0);
empty: out std_logic;
dvalid: out std_logic
);
end entity;
architecture behave of insnqueue is
constant QUEUESIZE: integer := 8;
signal rdptr, wrptr, rdptrplus: integer range 0 to QUEUESIZE-1;
subtype insntype is std_logic_vector(15 downto 0);
type queuetype is array(0 to QUEUESIZE-1) of insntype;
signal qq: queuetype;
signal dvalid_int: std_logic;
begin
-- process(clkr)
-- begin
-- if rising_edge(clkr) then
process(rdptr,rdptrplus,qq)
begin
dout0 <= qq(rdptr);
dout1 <= qq(rdptrplus);
end process;
-- end if;
-- end process;
empty <= '1' when rdptr=wrptr else '0';
process(rdptr,wrptr)
begin
full <= '0';
if wrptr=QUEUESIZE-1 then
if rdptr=0 then
full <= '1';
end if;
else
if rdptr-wrptr=1 then
full<='1';
end if;
end if;
dvalid_int <= '0';
-- Now, how many items ?
if rdptr>wrptr then
dvalid_int <= '1';
elsif rdptr<wrptr then
if wrptr-rdptr>1 then
dvalid_int<='1';
end if;
end if;
end process;
process(rdptr)
begin
if rdptr=QUEUESIZE-1 then
rdptrplus <= 0;
else
rdptrplus <= rdptr+1;
end if;
end process;
process(clkw)
begin
if rising_edge(clkw) then
if rst='1' then
wrptr <= 0;
else
if clr='1' then
wrptr<=rdptr;
else
if en='1' then
qq(wrptr)<=din;
if wrptr=QUEUESIZE-1 then
wrptr<=0;
else
wrptr<=wrptr+1;
end if;
end if;
end if;
end if;
end if;
end process;
process(clkr)
begin
if rising_edge(clkr) then
if rst='1' then
rdptr<=0;
dvalid<='0';
else
if pop='1' then
if dualpop='0' then
if rdptr=QUEUESIZE-1 then
rdptr<=0;
else
rdptr<=rdptr+1;
end if;
else
if rdptr=QUEUESIZE-1 then
rdptr<=1;
elsif rdptr=QUEUESIZE-2 then
rdptr<=0;
else
rdptr<=rdptr+2;
end if;
end if;
end if;
dvalid <= dvalid_int;
end if;
end if;
end process;
end behave;
| bsd-3-clause | 82618c23d48d6bb55f3edfc3863afe42 | 0.520375 | 3.532484 | false | false | false | false |
thoralt/KCVGA | FPGA/KCVIDEO_INTERFACE.vhd | 1 | 16,948 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.std_logic_unsigned."+";
USE IEEE.std_logic_unsigned."-";
USE IEEE.std_logic_unsigned."=";
USE IEEE.std_logic_unsigned."<";
USE IEEE.std_logic_unsigned.">";
USE IEEE.std_logic_unsigned."<=";
USE IEEE.std_logic_unsigned.">=";
ENTITY KCVIDEO_INTERFACE IS PORT
(
CLK : IN STD_LOGIC; -- master clock input 108 MHz
KC_CLK : IN STD_LOGIC; -- external video clock 7.09 MHz
R : IN STD_LOGIC; -- red pixel color
G : IN STD_LOGIC; -- green pixel color
B : IN STD_LOGIC; -- blue pixel color
EZ : IN STD_LOGIC; -- foreground/background bit
EX : IN STD_LOGIC; -- intensity bit
HSYNC : IN STD_LOGIC; -- horizontal sync input
VSYNC : IN STD_LOGIC; -- vertical sync input
nRESET : IN STD_LOGIC; -- reset input
FIFO_WR : OUT STD_LOGIC; -- SRAM FIFO write output
FIFO_FULL : IN STD_LOGIC; -- SRAM FIFO full input
FRAMESYNC : IN STD_LOGIC; -- start of frame from VGA module for screensaver
DATA_OUT : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); -- SRAM pixel data
SRAM_ADDR : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address
SRAM_ADDR_WR : OUT STD_LOGIC
);
END KCVIDEO_INTERFACE;
ARCHITECTURE Behavioral OF KCVIDEO_INTERFACE IS
SIGNAL counter : INTEGER RANGE 0 TO 320;
SIGNAL prescaler : INTEGER RANGE 0 TO 1;
SIGNAL FRAMESYNC_EDGE_DETECTOR : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
DATA_OUT <= "11010";
PROCESS (CLK, nRESET)
BEGIN
IF nRESET = '0' THEN
FRAMESYNC_EDGE_DETECTOR <= (OTHERS => '0');
FIFO_WR <= '0';
prescaler <= 0;
-- elsif rising_edge(CLK) then
-- SRAM_ADDR_WR <= '0';
--
-- if counter > 0 then
-- if prescaler = 0 then
-- FIFO_WR <= '1';
-- prescaler <= 1;
-- else
-- prescaler <= 0;
-- FIFO_WR <= '0';
-- counter <= counter - 1;
-- end if;
-- end if;
--
-- if FRAMESYNC_EDGE_DETECTOR = "01" then
-- SRAM_ADDR <= (others => '0');
-- SRAM_ADDR_WR <= '1';
-- counter <= 3;
-- end if;
--
-- FRAMESYNC_EDGE_DETECTOR <= FRAMESYNC_EDGE_DETECTOR(0) & FRAMESYNC;
END IF;
END PROCESS;
END Behavioral;
---- screensaver position after reset
--constant LOGO_X : integer := 0;
--constant LOGO_Y : integer := 42;
--
---- screensaver dimensions
--constant LOGO_W : integer := 128;
--constant LOGO_H : integer := 128;
--
---- X and Y position of incoming pixel data
--signal X : STD_LOGIC_VECTOR(10 downto 0) := (others => '0');
--signal Y : STD_LOGIC_VECTOR(10 downto 0) := (others => '0');
--
---- current SRAM address
--signal A : STD_LOGIC_VECTOR(16 downto 0);
--
---- edge detectors and filters for clock, HSYNC, VSYNC
--signal KC_CLK_edge_detector : STD_LOGIC_VECTOR(2 downto 0);
--signal KC_CLK_glitch_filter : STD_LOGIC_VECTOR(3 downto 0);
--signal HSYNC_edge_detector : STD_LOGIC_VECTOR(2 downto 0);
--signal HSYNC_glitch_filter : STD_LOGIC_VECTOR(7 downto 0);
--signal VSYNC_edge_detector : STD_LOGIC_VECTOR(2 downto 0);
--signal VSYNC_glitch_filter : STD_LOGIC_VECTOR(7 downto 0);
--
---- internal frame start flag, gets set on falling edge of VSYNC
--signal FRAME_START : STD_LOGIC;
--
---- current screensaver data address
--signal SCREENSAVER_ROM_ADDRESS: STD_LOGIC_VECTOR(13 downto 0);
--
---- screensaver position and movement
--signal LOGO_POSITION_X : STD_LOGIC_VECTOR(8 downto 0);
--signal LOGO_POSITION_Y : STD_LOGIC_VECTOR(7 downto 0);
--signal LOGO_DIRECTION_X : STD_LOGIC;
--signal LOGO_DIRECTION_Y : STD_LOGIC;
--
---- gets set after screensaver has been completely written to SRAM
--signal SCREENSAVER_DONE : STD_LOGIC;
--
---- counter for screensaver activation
--signal TIMEOUT : STD_LOGIC_VECTOR(27 downto 0) := (others => '0');
--
--signal SCREENSAVER_ROM_DATA: STD_LOGIC;
--
--type INTERFACE_STATE is (STATE1, STATE2, STATE3, STATE4);
--signal current_state: INTERFACE_STATE := STATE1;
--signal PIXEL: STD_LOGIC_VECTOR(4 downto 0);
--signal blink: STD_LOGIC;
-- i_SCREENSAVER_ROM: entity SCREENSAVER_ROM port map(
-- CLK => CLK,
-- ADDR => SCREENSAVER_ROM_ADDRESS,
-- DATA => SCREENSAVER_ROM_DATA
-- );
-- SRAM_ADDR <= A;
-- SRAM_ADDR_WR <= '1';
-- A <= A + 107;
-- PIXEL <= PIXEL + 1;
-- counter <= 0;
-- if counter < 320 then
---- if counter = 0 then
---- SRAM_ADDR <= A;
---- SRAM_ADDR_WR <= '1';
---- end if;
--
-- if current_state = STATE1 then
-- if counter = 0 then
-- DATA_OUT <= "11010";
-- else
-- DATA_OUT <= "00000";
-- end if;
---- DATA_OUT <= PIXEL;
-- FIFO_WR <= '1';
-- current_state <= STATE2;
-- elsif current_state = STATE2 then
-- FIFO_WR <= '0';
-- current_state <= STATE1;
-- counter <= counter + 1;
-- end if;
--
---- TIMEOUT <= TIMEOUT + 1;
---- if TIMEOUT = 54000000 then
---- TIMEOUT <= (others => '0');
---- if blink = '0' then
---- blink <= '1';
---- PIXEL <= "11010";
---- else
---- blink <= '0';
---- PIXEL <= (others => '0');
---- end if;
---- end if;
--
-- end if;
-- process(CLK, nRESET, R, G, B, EZ, EX)
-- variable color : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
-- variable KC_CLK_filtered : STD_LOGIC;
-- variable HSYNC_filtered : STD_LOGIC;
-- variable VSYNC_filtered : STD_LOGIC;
-- begin
-- -- assign video inputs to color variable for easier access
-- color(0) := not(B);
-- color(1) := not(R);
-- color(2) := not(G);
-- color(3) := not(EX); -- intensity
-- color(4) := EZ; -- foreground/background
--
-- if nRESET = '0' then
-- LOGO_POSITION_X <= STD_LOGIC_VECTOR(to_unsigned(LOGO_X, 9));
-- LOGO_POSITION_Y <= STD_LOGIC_VECTOR(to_unsigned(LOGO_Y, 8));
-- KC_CLK_edge_detector <= (others => '0');
-- HSYNC_edge_detector <= (others => '0');
-- VSYNC_edge_detector <= (others => '0');
-- SCREENSAVER_ROM_ADDRESS <= (others => '0');
-- A <= (others => '1');
-- TIMEOUT <= (others => '0');
-- prescaler <= '0';
--
-- elsif rising_edge(CLK) then
-- FIFO_WR <= '0';
--
-- -------------------------------------------------------------------
-- -- screensaver timeout and movement
-- -------------------------------------------------------------------
-- -- only execute screensaver if no input data was available for more
-- -- than 216 000 000 cycles (2 seconds)
-- if not(TIMEOUT = 216000000) then
-- TIMEOUT <= TIMEOUT + 1;
-- else
-- -- move logo on every VGA frame start
-- if FRAMESYNC = '1' then
-- SCREENSAVER_DONE <= '0';
-- if LOGO_DIRECTION_X = '1' then
-- -- move in positive X direction
-- if LOGO_POSITION_X + LOGO_W < 319 then
-- LOGO_POSITION_X <= LOGO_POSITION_X + 1;
-- else
-- LOGO_DIRECTION_X <= '0';
-- end if;
-- else
-- -- move in negative X direction
-- if LOGO_POSITION_X > 0 then
-- LOGO_POSITION_X <= LOGO_POSITION_X - 1;
-- else
-- LOGO_DIRECTION_X <= '1';
-- end if;
-- end if;
--
-- if LOGO_DIRECTION_Y = '1' then
-- -- move in positive Y direction
-- if LOGO_POSITION_Y + LOGO_H < 255 then
-- LOGO_POSITION_Y <= LOGO_POSITION_Y + 1;
-- else
-- LOGO_DIRECTION_Y <= '0';
-- end if;
-- else
-- -- move in negative Y direction
-- if LOGO_POSITION_Y > 0 then
-- LOGO_POSITION_Y <= LOGO_POSITION_Y - 1;
-- else
-- LOGO_DIRECTION_Y <= '1';
-- end if;
-- end if;
-- end if;
--
-- -- prescaler: only execute every second cycle because ROM needs
-- -- one additional cycle to deliver next pixel
-- prescaler <= not(prescaler);
--
-- -- write screen saver pixels to RAM
-- if SCREENSAVER_DONE = '0' and FIFO_FULL = '0' and prescaler = '1' then
--
-- -- insert logo at position LOGO_POSITION_X, LOGO_POSITION_Y
-- if X >= LOGO_POSITION_X and X < LOGO_POSITION_X+STD_LOGIC_VECTOR(to_unsigned(LOGO_W, 9))
-- and Y >= LOGO_POSITION_Y and Y < LOGO_POSITION_Y+STD_LOGIC_VECTOR(to_unsigned(LOGO_H, 8)) then
-- if SCREENSAVER_ROM_DATA = '1' then
-- color := "11111";
-- else
-- color := "00001";
-- end if;
--
-- -- increment internal ROM address
-- SCREENSAVER_ROM_ADDRESS <= SCREENSAVER_ROM_ADDRESS + 1;
-- else
---- color := LOGO_BG;
-- color := "00000";
-- end if;
--
-- -- stuff current pixel into dataword
-- if pixel = pixel1 then
-- DATA_OUT(4 downto 0) <= color;
-- pixel <= pixel2;
-- elsif pixel = pixel2 then
-- DATA_OUT(9 downto 5) <= color;
-- pixel <= pixel3;
-- else
-- DATA_OUT(14 downto 10) <= color;
-- -- current dataword is now complete
-- -- -> set address bits in upper 16 bits
-- DATA_OUT(31 downto 15) <= A;
-- -- write to FIFO
-- FIFO_WR <= '1';
-- A <= A + 1;
-- pixel <= pixel1;
-- end if;
--
-- -- update X and Y counters
-- -- write 321 pixels per line because 321 is divisible by
-- -- 3 and we need to fill the last dataword completely
-- -- -> use one dummy pixel
-- if not(X = 320) then
-- X <= X + 1;
-- else
-- X <= (others => '0');
-- pixel <= pixel1;
-- if not(Y = 255) then
-- Y <= Y + 1;
-- else
-- Y <= (others => '0');
-- A <= (others => '0');
-- SCREENSAVER_ROM_ADDRESS <= (others => '0');
-- SCREENSAVER_DONE <= '1';
-- end if;
-- end if;
-- end if;
-- end if;
--
-- -------------------------------------------------------------------
-- -- external video sampling
-- -------------------------------------------------------------------
-- -- check for falling edge on KC_CLK
-- -- Normally, the data in the target device is valid on
-- -- the _rising_ clock edge. Since we have inserted a small
-- -- shift register for synchronization and edge detection,
-- -- data is now valid on the first _falling_ edge after
-- -- falling HSYNC.
-- if KC_CLK_edge_detector(2 downto 1) = "10" then
-- -- write 321 pixels per line because 321 is divisible by 3 and
-- -- we need to fill the last dataword completely
-- -- -> use one dummy pixel
-- if X < 321 and Y < 256
-- then
-- -- stuff current pixel into dataword
-- if pixel = pixel1 then
-- DATA_OUT(4 downto 0) <= color;
-- pixel <= pixel2;
-- elsif pixel = pixel2 then
-- DATA_OUT(9 downto 5) <= color;
-- pixel <= pixel3;
-- else
-- DATA_OUT(14 downto 10) <= color;
-- -- current dataword is now complete
-- -- -> set address bits in upper 16 bits
-- DATA_OUT(31 downto 15) <= A;
--
-- -- write to FIFO
-- -- skip dataword if FIFO is full (can't happen if
-- -- SRAM_INTERFACE and VGA_OUTPUT is behaving correctly)
-- if FIFO_FULL = '0' then
-- FIFO_WR <= '1';
-- end if;
-- pixel <= pixel1;
-- A <= A + 1;
-- end if;
-- X <= X + 1;
-- end if;
-- end if;
--
-- -- check for falling edge on HSYNC
-- if HSYNC_edge_detector(2 downto 1) = "10" then
-- if FRAME_START = '1' then
-- Y <= (others => '0');
-- A <= (others => '0');
-- SCREENSAVER_ROM_ADDRESS <= (others => '0');
-- FRAME_START <= '0';
-- else
-- Y <= Y + 1;
-- end if;
-- X <= (others => '0');
-- pixel <= pixel1;
-- end if;
--
-- -- check for falling edge on VSYNC
-- if VSYNC_edge_detector(2 downto 1) = "10" then
-- FRAME_START <= '1';
-- TIMEOUT <= (others => '0');
-- end if;
--
-- -- glitch filter, necessary due to capacitive coupling of some
-- -- signal lines
-- -- (does not delay falling edge, only delays rising edge)
-- -- only accepts H level if it persists for more than 4 or 8 clock cycles
-- KC_CLK_glitch_filter <= KC_CLK_glitch_filter(2 downto 0) & KC_CLK;
-- HSYNC_glitch_filter <= HSYNC_glitch_filter(6 downto 0) & HSYNC;
-- VSYNC_glitch_filter <= VSYNC_glitch_filter(6 downto 0) & VSYNC;
-- if KC_CLK_glitch_filter = "1111" then
-- KC_CLK_filtered := '1';
-- else
-- KC_CLK_filtered := '0';
-- end if;
-- if HSYNC_glitch_filter = "11111111" then
-- HSYNC_filtered := '1';
-- else
-- HSYNC_filtered := '0';
-- end if;
-- if VSYNC_glitch_filter = "11111111" then
-- VSYNC_filtered := '1';
-- else
-- VSYNC_filtered := '0';
-- end if;
--
-- -- shift left edge detectors, concatenate filtered input
-- -- signals on LSB side
-- KC_CLK_edge_detector <= KC_CLK_edge_detector(1 downto 0) & KC_CLK_filtered;
-- HSYNC_edge_detector <= HSYNC_edge_detector(1 downto 0) & HSYNC_filtered;
-- VSYNC_edge_detector <= VSYNC_edge_detector(1 downto 0) & VSYNC_filtered;
--
-- end if;
-- end process;
| mit | 42512f97c6b0c91486ac1d0ec4133977 | 0.416922 | 4.22012 | false | false | false | false |
alvieboy/xtc-base | fetchdata.vhd | 1 | 3,905 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity fetchdata is
port (
clk: in std_logic;
rst: in std_logic;
-- Register access
r1_en: out std_logic;
r1_addr: out regaddress_type;
r1_read: in word_type_std;
-- Register access
r2_en: out std_logic;
r2_addr: out regaddress_type;
r2_read: in word_type_std;
w_addr: out regaddress_type;
w_en: out std_logic;
-- Input for previous stages
dui: in decode_output_type;
freeze: in std_logic;
flush: in std_logic;
refetch: in std_logic;
clrhold: in std_logic;
executed: in boolean;
-- Output for next stages
fduo: out fetchdata_output_type
);
end entity fetchdata;
architecture behave of fetchdata is
signal fdr: fetchdata_regs_type;
begin
fduo.r <= fdr;
fduo.rr1 <= r1_read;
fduo.rr2 <= r2_read;
fduo.alufwa <= fdr.alufwa;
fduo.alufwb <= fdr.alufwb;
syncfetch: if FETCHDATA_STAGE generate
process(dui,clk,rst,fdr,flush,freeze, refetch, executed, clrhold)
variable fdw: fetchdata_regs_type;
begin
fdw := fdr;
fduo.valid <= fdr.drq.valid;-- or (fdr.waiting and not refetch);
if freeze='0' then
fdw.drq := dui.r;
fdw.rd1q := dui.r.rd1;
fdw.rd2q := dui.r.rd2;
if dui.r.valid='1' then
fdw.hold := dui.r.ismult;
end if;
-- Forwarding control
fdw.alu:='0';
fdw.alufwa:='0';
fdw.alufwb:='0';
if ( dui.r.reg_source = reg_source_alu ) then
if dui.r.regwe='1' then
fdw.alu:='1';
fdw.dreg := dui.r.dreg;
end if;
end if;
if (fdr.alu='1' and dui.r.sra1=fdr.dreg and executed and fdr.dreg/="0000") then
fdw.alufwa:='1';
end if;
if (fdr.alu='1' and dui.r.sra2=fdr.dreg and executed and fdr.dreg/="0000") then
fdw.alufwb:='1';
end if;
if flush='1' then
fdw.drq.valid:='0';
fdw.alu:='0';
end if;
end if;
fdw.waiting:='0';
if refetch='1' then
if freeze='0' then
fdw.drq.valid := '0';
fdw.waiting:='1';
end if;
end if;
if freeze='1' or flush='1' then
r1_en <= '0';
r2_en <= '0';
else
r1_en <= dui.r.rd1;
r2_en <= dui.r.rd2;
end if;
r1_addr <= dui.r.sra1;
r2_addr <= dui.r.sra2;
w_addr <= dui.r.dreg;
w_en <= dui.r.regwe;
if clrhold='1' then
fdw.hold := '0';
if dui.r.valid='1' then
fdw.hold := dui.r.ismult;
end if;
-- REMOVE ME.....
--fdw.drq.enable_alu := '0';
end if;
if flush='1' or refetch='1' then
fdw.hold := '0';
end if;
if rst='1' then
fdw.drq.valid := '0';
fdw.hold := '0';
fdw.alu := '0';
fdw.alufwa := '0';
fdw.alufwb := '0';
fdw.waiting := '0';
fdw.rd1q := '0';
fdw.rd2q := '0';
end if;
if rising_edge(clk) then
fdr <= fdw;
end if;
end process;
end generate;
asyncfetch: if not FETCHDATA_STAGE generate
fdr.drq <= dui.r;
process(fdr,refetch, dui)
begin
if refetch='1' then
r1_en <= '1';
r2_en <= '1';
--r3_en <= '1';
--r4_en <= '1';
r1_addr <= fdr.drq.sra1;
r2_addr <= fdr.drq.sra2;
--r3_addr <= fdr.drq.sra3;
--r4_addr <= fdr.drq.sra4;
else
r1_en <= dui.rd1;
r2_en <= dui.rd2;
--r3_en <= dui.rd3;
--r4_en <= dui.rd4;
r1_addr <= dui.sra1;
r2_addr <= dui.sra2;
--r3_addr <= dui.sra3;
--r4_addr <= dui.sra4;
end if;
end process;
end generate;
end behave;
| bsd-3-clause | d22f17c8fce72a4344401f912340f20d | 0.497311 | 2.912006 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixgx_mf_components.vhd | 1 | 12,006 | --
-- Copyright (C) 1988-2005 Altera Corporation
--
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
-- other associated documentation or information provided by Altera or a
-- partner under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, net list, support information,
-- device programming or simulation file, or any other related
-- documentation or information is prohibited for any other purpose,
-- including, but not limited to modification, reverse engineering, de-
-- compiling, or use with any other silicon devices, unless such use is
-- explicitly licensed under a separate agreement with Altera or a
-- megafunction partner. Title to the intellectual property, including
-- patents, copyrights, trademarks, trade secrets, or maskworks, embodied
-- in any such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information provided by Altera or a megafunction partner, remains with
-- Altera, the megafunction partner, or their respective licensors. No
-- other licenses, including any licenses needed under any third party's
-- intellectual property, are provided herein.
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- ALtera Stratix GX Altgxb Megafunction Component Declaration File
--
library ieee;
use ieee.std_logic_1164.all;
use work.pllpack1.all;
package stratixgx_mf_components is
component altgxb
generic (
operation_mode : string := "DUPLEX";
loopback_mode : string := "NONE";
reverse_loopback_mode : string := "NONE";
protocol : string := "CUSTOM";
number_of_channels : integer := 20;
number_of_quads : integer := 1;
channel_width : positive := 20;
pll_inclock_period : integer := 20000;
data_rate : integer := 0;
data_rate_remainder : integer := 0;
rx_data_rate : integer := 0;
rx_data_rate_remainder : integer := 0;
use_8b_10b_mode : string := "OFF";
use_double_data_mode : string := "OFF";
dwidth_factor : integer := 1;
-- RX Mode
disparity_mode : string := "OFF";
cru_inclock_period : integer := 0; -- Units in ps
run_length : integer := 128;
run_length_enable : string := "OFF";
use_channel_align : string := "OFF";
use_auto_bit_slip : string := "OFF";
use_rate_match_fifo : string := "OFF";
use_symbol_align : string := "OFF";
align_pattern : string := "X";
align_pattern_length : integer := 0;
infiniband_invalid_code : integer := 0;
clk_out_mode_reference : string := "ON";
-- TX Mode
use_fifo_mode : string := "ON";
intended_device_family : string := "STRATIXGX";
force_disparity_mode : string := "OFF";
lpm_type : string := "altgxb";
tx_termination : integer := 0;
-- Quartus 2.2 New Parameters
-- common
use_self_test_mode : string := "OFF";
self_test_mode : integer := 0;
-- Quartus 5.0 New Parameters
allow_gxb_merging : string := "OFF";
-- Receiver
use_equalizer_ctrl_signal : string := "OFF";
equalizer_ctrl_setting : integer := 0;
signal_threshold_select : integer := 80;
rx_bandwidth_type : string := "NEW_MEDIUM";
rx_enable_dc_coupling : string := "OFF";
use_vod_ctrl_signal : string := "OFF";
vod_ctrl_setting : integer := 1000;
use_preemphasis_ctrl_signal : string := "OFF";
preemphasis_ctrl_setting : integer := 0;
use_phase_shift : string := "ON";
pll_bandwidth_type : string := "LOW";
pll_use_dc_coupling : string := "OFF";
rx_ppm_setting : integer := 1000;
use_generic_fifo : string := "OFF";
use_rx_cruclk : string := "OFF";
use_rx_clkout : string := "OFF";
use_rx_coreclk : string := "OFF";
use_tx_coreclk : string := "OFF";
instantiate_transmitter_pll : string := "OFF";
consider_instantiate_transmitter_pll_param : string := "OFF";
rx_force_signal_detect : string := "OFF";
flip_rx_out : string := "OFF";
flip_tx_in : string := "OFF";
add_generic_fifo_we_synch_register : string := "OFF";
consider_enable_tx_8b_10b_i1i2_generation : string := "OFF";
enable_tx_8b_10b_i1i2_generation : string := "OFF";
for_engineering_sample_device : string := "ON";
device_family : string := ""
);
port (
inclk : in std_logic_vector(number_of_quads-1 downto 0) := (others => '0');
rx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
pll_areset : in std_logic_vector(number_of_quads-1 downto 0):= (others => '0');
rx_cruclk : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '0');
rx_in : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
rx_bitslip : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_enacdet : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_we : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_re : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_slpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_a1a2size : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_equalizerctrl : in std_logic_vector(number_of_channels * 3 -1 downto 0) := (others => '0');
rx_locktorefclk : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
rx_locktodata : in std_logic_vector(number_of_channels -1 downto 0) := (others => '0');
tx_in : in std_logic_vector(channel_width * number_of_channels-1 downto 0) := (others => '0');
tx_coreclk : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
tx_aclr : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
tx_ctrlenable : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
tx_forcedisparity : in std_logic_vector(dwidth_factor * number_of_channels-1 downto 0) := (others => '0');
tx_srlpbk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
tx_vodctrl : in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
tx_preemphasisctrl: in std_logic_vector(number_of_channels * 3-1 downto 0) := (others => '0');
-- XGM Input ports, common for Both Rx and Tx Mode
txdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
rxdigitalreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
rxanalogreset : in std_logic_vector(number_of_channels - 1 downto 0) := (others => '0');
pllenable : in std_logic_vector(number_of_quads - 1 downto 0) := (others => '1');
pll_locked : out std_logic_vector(number_of_quads-1 downto 0);
coreclk_out : out std_logic_vector(number_of_quads-1 downto 0);
rx_out : out std_logic_vector(get_rx_channel_width(use_generic_fifo,
clk_out_mode_reference, channel_width) * number_of_channels-1 downto 0);
rx_clkout : out std_logic_vector(number_of_channels-1 downto 0);
rx_locked : out std_logic_vector(number_of_channels-1 downto 0);
rx_freqlocked : out std_logic_vector(number_of_channels-1 downto 0);
rx_rlv : out std_logic_vector(number_of_channels-1 downto 0);
rx_syncstatus : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_patterndetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_ctrldetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_errdetect : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_disperr : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
rx_signaldetect : out std_logic_vector(number_of_channels-1 downto 0);
-- rx_fifoempty : out std_logic_vector(number_of_channels-1 downto 0);
-- rx_fifofull : out std_logic_vector(number_of_channels-1 downto 0);
rx_fifoalmostempty: out std_logic_vector(number_of_channels-1 downto 0);
rx_fifoalmostfull : out std_logic_vector(number_of_channels-1 downto 0);
rx_channelaligned : out std_logic_vector(number_of_quads-1 downto 0);
rx_bisterr : out std_logic_vector(number_of_channels-1 downto 0);
rx_bistdone : out std_logic_vector(number_of_channels-1 downto 0);
rx_a1a2sizeout : out std_logic_vector(get_rx_dwidth_factor(use_generic_fifo,
clk_out_mode_reference, dwidth_factor) * number_of_channels-1 downto 0);
tx_out : out std_logic_vector(number_of_channels-1 downto 0)
);
end component;
end stratixgx_mf_components;
| gpl-3.0 | b13bcb9355276e0e0d8dc2c57e50bbea | 0.509828 | 4.255938 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriagx_components.vhd | 1 | 50,871 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriagx_atom_pack.all;
package arriagx_components is
--
-- arriagx_ram_block
--
COMPONENT arriagx_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriagx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriagx_jtag
--
COMPONENT arriagx_jtag
generic (
lpm_type : string := "arriagx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- arriagx_crcblock
--
COMPONENT arriagx_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "arriagx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriagx_asmiblock
--
COMPONENT arriagx_asmiblock
generic (
lpm_type : string := "arriagx_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
END COMPONENT;
--
-- arriagx_lcell_ff
--
COMPONENT arriagx_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "arriagx_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- arriagx_lcell_comb
--
COMPONENT arriagx_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "arriagx_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- arriagx_clkctrl
--
COMPONENT arriagx_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriagx_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- arriagx_io
--
COMPONENT arriagx_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "arriagx_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
END COMPONENT;
--
-- arriagx_pll
--
COMPONENT arriagx_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriagx_pll";
family_name : string := "StratixIIGXLITE";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- arriagx_mac_mult
--
COMPONENT arriagx_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "arriagx_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_mac_out
--
COMPONENT arriagx_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "arriagx_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
saturate1 : IN std_logic := '0';
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_lvds_transmitter
--
COMPONENT arriagx_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriagx_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- arriagx_lvds_receiver
--
COMPONENT arriagx_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "arriagx_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_dll
--
COMPONENT arriagx_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "arriagx_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_rublock
--
COMPONENT arriagx_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriagx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- arriagx_termination
--
COMPONENT arriagx_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "arriagx_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- arriagx_routing_wire
--
COMPONENT arriagx_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
end arriagx_components;
| gpl-3.0 | e0f2ec02eeadebe7b7548fc711f91529 | 0.476106 | 4.23925 | false | false | false | false |
EPiCS/reconos | pcores/reconos_memif_mmu_zynq_v1_00_a/hdl/vhdl/reconos_memif_mmu_zynq.vhd | 2 | 11,465 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory management unit enables virtual address
-- support. Therefore it performs page table walks,
-- manages a TLB for faster translation and handles
-- page fault via the proc control unit.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_memif_mmu_zynq_v1_00_a;
use reconos_memif_mmu_zynq_v1_00_a.tlb;
entity reconos_memif_mmu_zynq is
generic (
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_TLB_SIZE : integer := 128
);
port (
-- Input FIFO ports from the HWTs (via burst converter and transaction control)
CTRL_FIFO_In_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_In_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_In_Empty : in std_logic;
CTRL_FIFO_In_RE : out std_logic;
-- Output FIFO ports to memory controller
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Seperate control and data FIFOs (emulated) for page table walks
CTRL_FIFO_Mmu_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : out std_logic;
CTRL_FIFO_Mmu_RE : in std_logic;
MEMIF_FIFO_Mmu_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : out std_logic;
MEMIF_FIFO_Mmu_WE : in std_logic;
-- MMU ports
MMU_Pgf : out std_logic;
MMU_Fault_addr : out std_logic_vector(31 downto 0);
MMU_Retry : in std_logic;
MMU_Pgd : in std_logic_vector(31 downto 0);
MMU_Tlb_Hits : out std_logic_vector(31 downto 0);
MMU_Tlb_Misses : out std_logic_vector(31 downto 0);
MMU_Clk : in std_logic;
MMU_Rst : in std_logic;
DEBUG_DATA : out std_logic_vector(203 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of MMU_Clk : signal is "Clk";
attribute SIGIS of MMU_Rst : signal is "Rst";
end entity reconos_memif_mmu_zynq;
architecture implementation of reconos_memif_mmu_zynq is
constant C_MEMIF_CMD_WIDTH : integer := C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH;
signal ctrl_in_re : std_logic;
signal ctrl_out_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_out_fill : std_logic_vector(15 downto 0);
signal ctrl_out_empty : std_logic;
signal ctrl_mmu_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_mmu_fill : std_logic_vector(15 downto 0);
signal ctrl_mmu_empty : std_logic;
-- MMU signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR,
READ_L1_ENTRY_0, READ_L1_ENTRY_1, READ_L1_ENTRY_2,
READ_L2_ENTRY_0, READ_L2_ENTRY_1, READ_L2_ENTRY_2,
WRITE_CMD, WRITE_ADDR, PAGE_FAULT);
signal state : STATE_TYPE;
signal pgf : std_logic;
signal tlb_hits : std_logic_vector(31 downto 0);
signal tlb_misses : std_logic_vector(31 downto 0);
-- these signals contain the received request data unchanged
signal ctrl_cmd : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal l1_table_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table
signal l1_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table entry
signal l2_table_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table
signal l2_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table entry
signal small_page_addr : std_logic_vector(31 downto 0); -- page table entry
signal physical_addr : std_logic_vector(31 downto 0); -- physical address
signal tlb_hit : std_logic;
signal tlb_tag : std_logic_vector(19 downto 0);
signal tlb_do : std_logic_vector(19 downto 0);
signal tlb_di : std_logic_vector(19 downto 0);
signal tlb_we : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
DEBUG_DATA(0) <= '1' when state = WAIT_REQUEST else '0';
DEBUG_DATA(1) <= '1' when state = READ_CMD else '0';
DEBUG_DATA(2) <= '1' when state = READ_ADDR else '0';
DEBUG_DATA(3) <= '1' when state = READ_L1_ENTRY_0 else '0';
DEBUG_DATA(4) <= '1' when state = READ_L1_ENTRY_1 else '0';
DEBUG_DATA(5) <= '1' when state = READ_L1_ENTRY_2 else '0';
DEBUG_DATA(6) <= '1' when state = READ_L2_ENTRY_0 else '0';
DEBUG_DATA(7) <= '1' when state = READ_L2_ENTRY_1 else '0';
DEBUG_DATA(8) <= '1' when state = READ_L2_ENTRY_2 else '0';
DEBUG_DATA(9) <= '1' when state = WRITE_CMD else '0';
DEBUG_DATA(10) <= '1' when state = WRITE_ADDR else '0';
DEBUG_DATA(11) <= '1' when state = PAGE_FAULT else '0';
DEBUG_DATA(203 downto 172) <= l1_table_addr;
DEBUG_DATA(171 downto 140) <= l1_descriptor_addr;
DEBUG_DATA(139 downto 108) <= l2_table_addr;
DEBUG_DATA(107 downto 76) <= l2_descriptor_addr;
DEBUG_DATA(75 downto 44) <= small_page_addr;
DEBUG_DATA(43 downto 12) <= physical_addr;
clk <= MMU_Clk;
rst <= MMU_Rst;
CTRL_FIFO_In_RE <= ctrl_in_re;
CTRL_FIFO_Out_Data <= ctrl_out_data;
CTRL_FIFO_Out_Fill <= ctrl_out_fill;
CTRL_FIFO_Out_Empty <= ctrl_out_empty;
CTRL_FIFO_Mmu_Data <= ctrl_mmu_data;
CTRL_FIFO_Mmu_Fill <= ctrl_mmu_fill;
CTRL_FIFO_Mmu_Empty <= ctrl_mmu_empty;
MEMIF_FIFO_Mmu_Rem <= X"1111";
MEMIF_FIFO_Mmu_Full <= '0';
MMU_Pgf <= pgf;
MMU_Fault_Addr <= ctrl_addr;
MMU_Tlb_Hits <= tlb_hits;
MMU_Tlb_Misses <= tlb_misses;
-- some address calculations based on the page table architecture
-- for detailed information look into the TRM on page 80
l1_table_addr <= MMU_Pgd;
l1_descriptor_addr <= l1_table_addr(31 downto 14) & ctrl_addr(31 downto 20) & "00";
l2_descriptor_addr <= l2_table_addr(31 downto 10) & ctrl_addr(19 downto 12) & "00";
physical_addr <= small_page_addr(31 downto 12) & ctrl_addr(11 downto 0);
mmu_proc : process(clk,rst) is
begin
if rst = '1' then
state <= WAIT_REQUEST;
ctrl_cmd <= (others => '0');
ctrl_length <= (others => '0');
ctrl_addr <= (others => '0');
ctrl_out_empty <= '1';
ctrl_out_fill <= (others => '0');
ctrl_out_data <= (others => '0');
ctrl_in_re <= '0';
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= (others => '0');
ctrl_mmu_data <= (others => '0');
pgf <= '0';
tlb_hits <= (others => '0');
tlb_misses <= (others => '0');
elsif rising_edge(clk) then
tlb_we <= '0';
case state is
when WAIT_REQUEST =>
-- start reading if there are 2 word in FIFO
--if CTRL_FIFO_In_Empty = '0' and CTRL_FIFO_In_Fill >= X"0001" then
ctrl_in_re <= '1';
state <= READ_CMD;
--end if;
when READ_CMD =>
-- read cmd and length
if CTRL_FIFO_In_Empty = '0' then
ctrl_cmd <= CTRL_FIFO_In_Data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
end if;
when READ_ADDR =>
-- read address
if CTRL_FIFO_In_Empty = '0' then
ctrl_addr <= CTRL_FIFO_In_Data;
ctrl_in_re <= '0';
state <= READ_L1_ENTRY_0;
end if;
when READ_L1_ENTRY_0 =>
if tlb_hit = '1' then
small_page_addr(31 downto 12) <= tlb_do;
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_hits <= tlb_hits + 1;
state <= WRITE_CMD;
else
-- write command to memory controller
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l1_descriptor_addr;
tlb_misses <= tlb_misses + 1;
state <= READ_L1_ENTRY_1;
end if;
end if;
when READ_L1_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L1_ENTRY_2;
end if;
when READ_L1_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
l2_table_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1 downto 0) = "00" then
pgf <= '1';
state <= PAGE_FAULT;
else
state <= READ_L2_ENTRY_0;
end if;
end if;
when READ_L2_ENTRY_0 =>
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l2_descriptor_addr;
state <= READ_L2_ENTRY_1;
end if;
when READ_L2_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L2_ENTRY_2;
end if;
when READ_L2_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
small_page_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1 downto 0) = "00" then
pgf <= '1';
state <= PAGE_FAULT;
else
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_we <= '1';
state <= WRITE_CMD;
end if;
end if;
when WRITE_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_fill <= X"0000";
ctrl_out_data <= physical_addr;
state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_empty <= '1';
ctrl_out_fill <= X"0000";
state <= WAIT_REQUEST;
end if;
when PAGE_FAULT =>
pgf <= '0';
if MMU_Retry = '1' then
pgf <= '0';
state <= READ_L1_ENTRY_0;
end if;
end case;
end if;
end process mmu_proc;
tlb_tag <= ctrl_addr(31 downto 12);
tlb_di <= small_page_addr(31 downto 12);
tlb_gen : if C_TLB_SIZE > 0 generate
tlb : entity reconos_memif_mmu_zynq_v1_00_a.tlb
generic map (
C_TLB_SIZE => C_TLB_SIZE,
C_TAG_SIZE => 20,
C_DATA_SIZE => 20
)
port map (
TLB_Tag => tlb_tag,
TLB_DI => tlb_di,
TLB_DO => tlb_do,
TLB_WE => tlb_we,
TLB_Hit => tlb_hit,
TLB_Clk => clk,
TLB_Rst => rst
);
end generate;
end architecture implementation;
| gpl-2.0 | af0da433d6e828af7892f6b966b80897 | 0.571441 | 2.895681 | false | false | false | false |
alvieboy/xtc-base | xtc.vhd | 1 | 15,615 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity xtc is
port (
wb_syscon: in wb_syscon_type;
-- Master wishbone interface
wbo: out wb_mosi_type;
wbi: in wb_miso_type;
-- ROM wb interface
romwbo: out wb_mosi_type;
romwbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
break: out std_logic;
intack: out std_logic;
rstreq: out std_logic;
edbg: in memory_debug_type
);
end xtc;
architecture behave of xtc is
signal fuo: fetch_output_type;
signal duo: decode_output_type;
signal fduo: fetchdata_output_type;
signal euo: execute_output_type;
signal muo: memory_output_type;
signal rbw1_addr: regaddress_type;
signal rbw1_wr: std_logic_vector(31 downto 0);
signal rbw1_we: std_logic;
signal rbw1_en: std_logic;
signal rbw2_addr: regaddress_type;
signal rbw2_wr: std_logic_vector(31 downto 0);
signal rbw2_we: std_logic := '0';
signal rbw2_en: std_logic := '0';
signal rb1_addr: regaddress_type;
signal rb1_en: std_logic;
signal rb1_rd: std_logic_vector(31 downto 0);
signal rb2_addr: regaddress_type;
signal rb2_en: std_logic;
signal rb2_rd: std_logic_vector(31 downto 0);
signal jumpaddr: word_type;
signal cache_valid: std_logic;
signal dcache_flush: std_logic;
signal dcache_inflush: std_logic;
signal icache_flush: std_logic;
signal icache_abort: std_logic;
signal cache_data: std_logic_vector(31 downto 0);
signal cache_address: std_logic_vector(31 downto 0);
signal cache_strobe: std_logic;
signal cache_enable: std_logic;
signal cache_stall: std_logic;
signal cache_seq: std_logic;
signal cache_nseq: std_logic;
signal decode_freeze: std_logic;
signal w_en: std_logic;
signal w_addr: regaddress_type;
signal memory_busy: std_logic;
signal execute_busy: std_logic;
signal wb_busy: std_logic;
signal refetch: std_logic;
signal dual: std_logic;
signal allvalid: std_logic;
signal notallvalid: std_logic;
signal e_busy: std_logic;
--signal refetch_registers: std_logic;
signal freeze_decoder: std_logic;
signal executed: boolean;
component tracer is
port (
clk: in std_logic;
dbgi: in execute_debug_type
);
end component tracer;
signal dbg: execute_debug_type;
signal mdbg: memory_debug_type;
signal cifo: copifo;
signal cifi: copifi;
signal co: copo_a;
signal ci: copi_a;
signal mwbi: wb_miso_type;
signal mwbo: wb_mosi_type;
signal immu_tlbw: std_logic:='0';
signal immu_tlbv: tlb_entry_type;
signal immu_tlba: std_logic_vector(2 downto 0):="000";
signal immu_context: std_logic_vector(5 downto 0):=(others => '0');
signal immu_paddr: std_logic_vector(31 downto 0);
signal immu_valid: std_logic;
signal immu_enabled: std_logic:='1';
signal cache_tag: std_logic_vector(31 downto 0);
signal dcache_accesstype: std_logic_vector(1 downto 0);
signal flushfd: std_logic;
signal clrhold: std_logic;
signal internalfault: std_logic;
signal pipeline_internalfault: std_logic;
signal busycnt: unsigned (31 downto 0);
signal proten: std_logic;
signal protw: std_logic_vector(31 downto 0);
signal rstreq_i: std_logic;
signal fflags: std_logic_vector(31 downto 0);
signal intin: std_logic_vector(31 downto 0);
signal trappc: std_logic_vector(31 downto 0);
signal trapaddr: std_logic_vector(31 downto 0);
signal trapbase: std_logic_vector(31 downto 0);
signal istrap: std_logic;
begin
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if pipeline_internalfault='1' then
fflags(0) <= execute_busy;
fflags(1) <= notallvalid;
fflags(2) <= freeze_decoder;
fflags(3) <= wb_busy;
fflags(4) <= memory_busy;
fflags(5) <= dbg.hold;
fflags(6) <= dbg.multvalid;
fflags(7) <= dbg.trap;
end if;
end if;
end process;
rstreq_i<= pipeline_internalfault ;
rstreq <= rstreq_i;
-- synthesis translate_off
trc: tracer
port map (
clk => wb_syscon.clk,
dbgi => dbg
);
-- synthesis translate_on
-- Register bank.
rbe: entity work.regbank_3p
generic map (
ADDRESS_BITS => 5,
ZEROSIZE => 4
)
port map (
clk => wb_syscon.clk,
rb1_en => rb1_en,
rb1_addr=> rb1_addr,
rb1_rd => rb1_rd,
rb2_en => rb2_en,
rb2_addr=> rb2_addr,
rb2_rd => rb2_rd,
rb3_en => rbw1_en,
rb3_we => rbw1_we,
rb3_addr=> rbw1_addr,
rb3_wr => rbw1_wr
);
cache: if INSTRUCTION_CACHE generate
cache: entity work.icache
generic map (
ADDRESS_HIGH => 31
)
port map (
syscon => wb_syscon,
valid => cache_valid,
data => cache_data,
address => cache_address,
strobe => cache_strobe,
stall => cache_stall,
enable => cache_enable,
flush => icache_flush,
abort => icache_abort,
seq => cache_seq,
tag => cache_tag,
tagen => immu_enabled,
mwbi => romwbi,
mwbo => romwbo
);
mmub: if MMU_ENABLED generate
cache_tag <= immu_paddr;
immuinst: entity work.mmu
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
addr => cache_address,
ctx => immu_context,
en => cache_strobe,
tlbw => immu_tlbw,
tlba => immu_tlba,
tlbv => immu_tlbv,
paddr => immu_paddr,
valid => immu_valid,
pw => open,
pr => open,
px => open,
ps => open
);
end generate;
end generate;
--romwbo.we<='0';
nocache: if not INSTRUCTION_CACHE generate
-- Hack... we need to provide a solution for ACK being held low
-- when no pipelined transaction exists
-- For now, the romram is hacked to do it.
--nopipe: if not EXTRA_PIPELINE generate
cache_valid <= romwbi.ack;
cache_data <= romwbi.dat;
romwbo.adr <= cache_address;
romwbo.stb <= cache_strobe;
romwbo.cyc <= cache_enable;
cache_stall <= romwbi.stall;
--end generate;
end generate;
fetch_unit: entity work.fetch
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Connection to ROM
stall => cache_stall,
valid => cache_valid,
address => cache_address,
read => cache_data,
enable => cache_enable,
strobe => cache_strobe,
abort => icache_abort,
seq => cache_seq,
nseq => cache_nseq,
freeze => decode_freeze,
jump => euo.jump,
jumppriv => euo.jumppriv,
jumpaddr => euo.r.jumpaddr,
dual => dual,
-- Outputs for next stages
fuo => fuo
);
decode_unit: entity work.decode
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Input from fetch unit
fui => fuo,
-- Outputs for next stages
duo => duo,
busy => decode_freeze,
freeze => freeze_decoder,
dual => dual,
flush => euo.jump, -- DELAY SLOT when fetchdata is passthrough
jump => euo.jump,
jumpmsb => euo.r.jumpaddr(1)
);
freeze_decoder <= execute_busy or notallvalid;
flushfd <= euo.jump or euo.trap;
fetchdata_unit: entity work.fetchdata
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
r1_en => rb1_en,
r1_addr => rb1_addr,
r1_read => rb1_rd,
r2_en => rb2_en,
r2_addr => rb2_addr,
r2_read => rb2_rd,
freeze => execute_busy,
flush => flushfd,-- euo.jump, -- DELAY SLOT
refetch => notallvalid, --refetch_registers,--execute_busy,-- TEST TEST: was refetch,
w_addr => w_addr,
w_en => w_en,
executed => executed,
clrhold => euo.clrhold,
-- Input from decode unit
dui => duo,
-- Outputs for next stages
fduo => fduo
);
busycheck: block
signal dirtyReg: regaddress_type;
signal dirty: std_logic;
signal v1,v2,v3: std_logic;
signal isBlocking: std_logic;
signal canProceed: std_logic;
begin
v1 <= '0' when dirty='1' and rb1_en='1' and rb1_addr=dirtyReg else '1';
v2 <= '0' when dirty='1' and rb2_en='1' and rb2_addr=dirtyReg else '1';
v3 <= '0' when dirty='1' and w_en='1' and w_addr=dirtyReg else '1';
isBlocking <= '1' when duo.r.valid='1' and ( duo.r.blocks='1' )
and execute_busy='0' and euo.jump='0'
and allvalid='1' and euo.trap='0'
else '0';
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
dirty <= '0';
dirtyReg <= (others => '0'); -- X
else
if isBlocking='1' and dirty='0' then -- and duo.r.sra2/="0000"
dirty <= '1';
dirtyReg <= duo.r.sra2;
end if;
-- Memory reads clear flags.
if muo.mregwe='1' and dirty='1' then
-- TODO here: why not use only the memory wb, rather than all wb ?
if (dirtyReg=muo.mreg) then
dirty <= '0';
dirtyReg <= (others => 'X');
--if (dirtyReg /= muo.mreg) then
-- report "Omg.. clearing reg " &hstr(muo.mreg) & ", but dirty register is "&hstr(dirtyReg) severity failure;
end if;
end if;
if muo.fault='1' then
dirty <= '0';
end if;
end if;
end if;
end process;
canProceed <= '0' when (dirty='1' and duo.r.valid='1' and duo.r.blocks='1') else '1';
allvalid <= v1 and v2 and v3 and canProceed;
notallvalid <= not allvalid;
end block;
execute_busy <= e_busy;
executed <= euo.executed;
execute_unit: entity work.execute
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
busy => e_busy,
mem_busy => memory_busy,
wb_busy => wb_busy,
refetch => refetch,
int => wbi.int,
nmi => nmi,
nmiack => nmiack,
intline => x"00",
-- Input from fetchdata unit
fdui => fduo,
-- Outputs for next stages
euo => euo,
-- Input from memory unit (spr update)
mui => muo,
-- COP
co => cifo,
ci => cifi,
-- Trap
trappc => trappc,
istrap => istrap,
trapbase => trapbase,
-- Debug
dbgo => dbg
);
-- MMU cop
copmmuinst: entity work.cop_mmu
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
tlbw => immu_tlbw,
tlba => immu_tlba,
tlbv => immu_tlbv,
mmuen => immu_enabled,
proten => proten,
protw => protw,
dbgi => dbg,
mdbgi => mdbg,--edbg,
fflags => fflags,
ci => ci(1),
co => co(1)
);
coparbinst: entity work.cop_arb
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
cfi => cifo,
cfo => cifi,
ci => co,
co => ci
);
-- MMU cop
copsysinst: entity work.cop_sys
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
icache_flush => icache_flush,
dcache_flush => dcache_flush,
dcache_inflush => dcache_inflush,
int_in => x"00000000",
trappc => trappc,
trapaddr => trapaddr,
istrap => istrap,
trapbase => trapbase,
--intacken => '0',
ci => ci(0),
co => co(0)
);
dcachegen: if DATA_CACHE generate
dcache_accesstype <= ACCESS_NOCACHE when mwbo.adr(31)='1' else
ACCESS_WT;
dcacheinst: entity work.dcache
generic map (
ADDRESS_HIGH => 31,
CACHE_MAX_BITS => 13, -- 8 Kb
CACHE_LINE_SIZE_BITS => 6 -- 64 bytes
)
port map (
syscon => wb_syscon,
ci.data => mwbo.dat,
ci.address => mwbo.adr,
ci.strobe => mwbo.stb,
ci.we => mwbo.we,
ci.wmask => mwbo.sel,
ci.enable => mwbo.cyc,
ci.tag => mwbo.tag,
ci.flush => dcache_flush,
ci.accesstype => dcache_accesstype,
co.in_flush => dcache_inflush,
co.data => mwbi.dat,
co.stall => mwbi.stall,
co.valid => mwbi.ack,
co.tag => mwbi.tag,
co.err => mwbi.err,
mwbi => wbi,
mwbo => wbo
);
end generate;
nodcache: if not DATA_CACHE generate
wbo<=mwbo;
mwbi<=wbi;
end generate;
memory_unit: entity work.memory
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Memory interface
wb_ack_i => mwbi.ack,
wb_err_i => mwbi.err,
wb_dat_i => mwbi.dat,
wb_dat_o => mwbo.dat,
wb_adr_o => mwbo.adr,
wb_cyc_o => mwbo.cyc,
wb_stb_o => mwbo.stb,
wb_sel_o => mwbo.sel,
wb_tag_o => mwbo.tag,
wb_tag_i => mwbi.tag,
wb_we_o => mwbo.we,
wb_stall_i => mwbi.stall,
dbgo => mdbg,
refetch => refetch,
busy => memory_busy,
proten => proten,
protw => protw,
-- Input for previous stages
eui => euo,
-- Output for next stages
muo => muo
);
writeback_unit: entity work.writeback
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
busy => wb_busy,
r0_en => rbw1_en,
r0_we => rbw1_we,
r0_addr => rbw1_addr,
r0_write => rbw1_wr,
r1_en => rbw2_en,
r1_we => rbw2_we,
r1_addr => rbw2_addr,
r1_write => rbw2_wr,
--r_read => rbw_rd,
-- Input from previous stage
mui => muo,
eui => euo -- for fast register write
);
faultcheck: if FAULTCHECKS generate
-- Internal pipeline fault...
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
busycnt<=(others =>'0');
else
if execute_busy='1' or notallvalid='1' or freeze_decoder='1' then
busycnt<=busycnt+1;
else
busycnt<=(others =>'0');
end if;
end if;
end if;
end process;
pipeline_internalfault<='1' when busycnt > 65535 else '0';
end generate;
nofaultchecks: if not FAULTCHECKS generate
pipeline_internalfault<='0';
end generate;
-- synthesis translate_off
process
begin
wait on muo.internalfault;
if muo.internalfault'event and muo.internalfault='1' then
wait until rising_edge(wb_syscon.clk);
wait until rising_edge(wb_syscon.clk);
report "Internal memory fault" severity failure;
end if;
end process;
-- synthesis translate_on
end behave;
| bsd-3-clause | b3fcd6786da5db8e0b419dcaa045c0d1 | 0.534806 | 3.357343 | false | false | false | false |
alvieboy/xtc-base | wb_master_p_to_slave_np.vhd | 1 | 1,496 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity wb_master_p_to_slave_np is
port (
syscon: in wb_syscon_type;
-- Master signals
mwbi: in wb_mosi_type;
mwbo: out wb_miso_type;
-- Slave signals
swbi: in wb_miso_type;
swbo: out wb_mosi_type
);
end entity wb_master_p_to_slave_np;
architecture behave of wb_master_p_to_slave_np is
type state_type is ( idle, wait_for_ack );
signal state: state_type;
signal wo: wb_mosi_type;
begin
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
state <= idle;
mwbo.stall <= '0';
wo.cyc<='0';
else
case state is
when idle =>
if mwbi.cyc='1' and mwbi.stb='1' then
state <= wait_for_ack;
wo <= mwbi;
mwbo.stall <= '1';
end if;
when wait_for_ack =>
if swbi.ack='1' or swbi.err='1' then
wo.cyc <= '0';
wo.stb <= '0';
mwbo.stall <= '0';
state <= idle;
end if;
when others =>
end case;
end if;
end if;
end process;
swbo.stb <= wo.stb;-- when state=idle else '1';
swbo.dat <= wo.dat;
swbo.adr <= wo.adr;
swbo.sel <= wo.sel;
swbo.tag <= wo.tag;
swbo.we <= wo.we;
swbo.cyc <= wo.cyc;
mwbo.dat <= swbi.dat;
mwbo.ack <= swbi.ack;
mwbo.err <= swbi.err;
mwbo.tag <= swbi.tag;
end behave;
| bsd-3-clause | 3f76445dedde5e5abf3e8247d50b84e9 | 0.56016 | 2.849524 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_pmem_ctrl.vhd | 1 | 6,691 | ------------------------------------------------------------------------------
--
-- The Program memory controller.
--
-- $Id: t400_pmem_ctrl.vhd,v 1.3 2006-05-28 15:32:40 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_pmem_ctrl is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
a_i : in dw_t;
m_i : in dw_t;
-- Control Interface ------------------------------------------------------
op_i : in pc_op_t;
dec_data_i : in dec_data_t;
-- Stack Interface --------------------------------------------------------
pc_o : out pc_t;
pc_i : in pc_t;
-- Program Memory Interface -----------------------------------------------
pm_addr_o : out pc_t
);
end t400_pmem_ctrl;
library ieee;
use ieee.numeric_std.all;
-- pragma translate_off
use work.tb_pack.tb_pc_s;
-- pragma translate_on
architecture rtl of t400_pmem_ctrl is
signal pc_q : pc_t;
signal last_pc_s : pc_t;
begin
-----------------------------------------------------------------------------
-- Determine last program counter address
-----------------------------------------------------------------------------
last_pc_s <= to_unsigned(16#1ff#, pc_t'length)
when opt_type_g = t400_opt_type_410_c else
to_unsigned(16#3ff#, pc_t'length);
-----------------------------------------------------------------------------
-- Process pc
--
-- Purpose:
-- Implements the program counter.
--
pc: process (ck_i, por_i)
begin
if por_i then
pc_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
pc_q <= (others => '0');
elsif ck_en_i then
-- determine PC update mode
case op_i is
-- increment program counter ----------------------------------------
when PC_INC_PC =>
if pc_q = last_pc_s then
-- roll over
pc_q <= (others => '0');
else
pc_q <= pc_q + 1;
end if;
-- Load lower 6 bits from program memory data -----------------------
when PC_LOAD_6 =>
pc_q(5 downto 0) <= unsigned(dec_data_i(5 downto 0));
-- Load lower 7 bits from program memory data -----------------------
when PC_LOAD_7 =>
pc_q(6 downto 0) <= unsigned(dec_data_i(6 downto 0));
-- Load lower 8 bits from program memory data -----------------------
when PC_LOAD_8 =>
pc_q(7 downto 0) <= unsigned(dec_data_i(7 downto 0));
-- Load all bits from program memory data ---------------------------
when PC_LOAD =>
pc_q <= unsigned(dec_data_i);
-- pop program counter from stack -----------------------------------
when PC_POP =>
pc_q <= pc_i;
-- update program counter for LQID instruction ----------------------
when PC_LOAD_A_M =>
pc_q(7 downto 4) <= unsigned(a_i);
pc_q(3 downto 0) <= unsigned(m_i);
-- load interrupt vector --------------------------------------------
when PC_INT =>
if opt_type_g = t400_opt_type_420_c then
-- load address 0x100, i.e. skip first instruction at
-- vector address 0x0ff which has to be a NOP :-)
pc_q <= (8 => '1', others => '0');
end if;
when others =>
null;
end case;
end if;
end if;
end process pc;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-- instrument interrupt testbench
tb_pc_s <= pc_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
pc_o <= pc_q;
pm_addr_o <= pc_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/27 19:16:52 arniml
-- interrupt functionality added
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | d6f29ee2581a0ae1a3663249d8e1f1a3 | 0.490809 | 4.434062 | false | false | false | false |
freecores/t400 | rtl/vhdl/system/t410.vhd | 1 | 7,367 | -------------------------------------------------------------------------------
--
-- T410 system toplevel.
--
-- $Id: t410.vhd,v 1.2 2008-08-23 11:19:20 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t410 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t410;
use work.t400_system_comp_pack.t410_notri;
architecture struct of t410 is
signal io_l_from_t410_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t410_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_to_t410_s,
io_g_from_t410_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
signal gnd_s : std_logic;
begin
gnd_s <= '0';
-----------------------------------------------------------------------------
-- T410 without tri-states
-----------------------------------------------------------------------------
t410_notri_b : t410_notri
generic map (
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => t400_opt_cko_crystal_c,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => gnd_s,
io_l_i => io_l_b,
io_l_o => io_l_from_t410_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t410_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_b,
io_g_o => io_g_from_t410_s,
io_g_en_o => io_g_en_s,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t410_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 3 downto 0 generate
io_d_o(idx) <= io_d_from_t410_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 3 downto 0 generate
io_g_b(idx) <= io_g_from_t410_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2006/06/11 22:18:28 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 647f8a3d3156b40496a4acfd4137e751 | 0.531424 | 2.985008 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_core.vhd | 1 | 17,528 | -------------------------------------------------------------------------------
--
-- T400 Microcontroller Core
--
-- $Id: t400_core.vhd,v 1.12 2008-08-23 11:19:17 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t400_core is
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
por_n_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
pm_addr_o : out std_logic_vector(9 downto 0);
pm_data_i : in std_logic_vector(7 downto 0);
dm_addr_o : out std_logic_vector(5 downto 0);
dm_we_o : out std_logic;
dm_data_o : out std_logic_vector(3 downto 0);
dm_data_i : in std_logic_vector(3 downto 0);
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t400_core;
use work.t400_pack.all;
use work.t400_comp_pack.all;
architecture struct of t400_core is
signal ck_en_s : boolean;
signal por_s : boolean;
signal res_s : boolean;
signal phi1_s : std_logic;
signal out_en_s : boolean;
signal in_en_s : boolean;
signal icyc_en_s : boolean;
signal pm_addr_s : pc_t;
signal a_s : dw_t;
signal dec_data_s : dec_data_t;
signal pc_to_stack_s,
pc_from_stack_s : pc_t;
signal q_s : byte_t;
signal b_s : b_t;
signal c_s,
carry_s : std_logic;
signal sio_s : dw_t;
signal pc_op_s : pc_op_t;
signal stack_op_s : stack_op_t;
signal dmem_op_s : dmem_op_t;
signal b_op_s : b_op_t;
signal skip_op_s : skip_op_t;
signal alu_op_s : alu_op_t;
signal io_l_op_s : io_l_op_t;
signal io_d_op_s : io_d_op_t;
signal io_g_op_s : io_g_op_t;
signal io_in_op_s : io_in_op_t;
signal sio_op_s : sio_op_t;
signal is_lbi_s : boolean;
signal en_s : dw_t;
signal skip_s,
skip_lbi_s : boolean;
signal tim_c_s : boolean;
signal in_s : dw_t;
signal int_s : boolean;
signal io_g_s : std_logic_vector(io_g_i'range);
signal cs_n_s,
rd_n_s,
wr_n_s : std_logic;
begin
ck_en_s <= ck_en_i = '1';
por_s <= por_n_i = '0';
io_g_s <= to_X01(io_g_i);
-----------------------------------------------------------------------------
-- Clock generator
-----------------------------------------------------------------------------
clkgen_b : t400_clkgen
generic map (
opt_ck_div_g => opt_ck_div_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
phi1_o => phi1_s,
out_en_o => out_en_s,
in_en_o => in_en_s,
icyc_en_o => icyc_en_s
);
-----------------------------------------------------------------------------
-- Reset module
-----------------------------------------------------------------------------
reset_b : t400_reset
port map (
ck_i => ck_i,
icyc_en_i => icyc_en_s,
por_i => por_s,
reset_n_i => reset_n_i,
res_o => res_s
);
-----------------------------------------------------------------------------
-- Program memory controller
-----------------------------------------------------------------------------
pmem_ctrl_b : t400_pmem_ctrl
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
a_i => a_s,
m_i => dm_data_i,
op_i => pc_op_s,
dec_data_i => dec_data_s,
pc_o => pc_to_stack_s,
pc_i => pc_from_stack_s,
pm_addr_o => pm_addr_s
);
--
pm_addr_o <= std_logic_vector(pm_addr_s);
-----------------------------------------------------------------------------
-- Data memory controller
-----------------------------------------------------------------------------
dmem_ctrl_b : t400_dmem_ctrl
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
dmem_op_i => dmem_op_s,
b_op_i => b_op_s,
dec_data_i => dec_data_s,
a_i => a_s,
q_high_i => q_s(7 downto 4),
b_o => b_s,
dm_addr_o => dm_addr_o,
dm_data_i => dm_data_i,
dm_data_o => dm_data_o,
dm_we_o => dm_we_o
);
-----------------------------------------------------------------------------
-- Decoder
-----------------------------------------------------------------------------
decoder_b : t400_decoder
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
out_en_i => out_en_s,
in_en_i => in_en_s,
icyc_en_i => icyc_en_s,
pc_op_o => pc_op_s,
stack_op_o => stack_op_s,
dmem_op_o => dmem_op_s,
b_op_o => b_op_s,
skip_op_o => skip_op_s,
alu_op_o => alu_op_s,
io_l_op_o => io_l_op_s,
io_d_op_o => io_d_op_s,
io_g_op_o => io_g_op_s,
io_in_op_o => io_in_op_s,
sio_op_o => sio_op_s,
dec_data_o => dec_data_s,
en_o => en_s,
skip_i => skip_s,
skip_lbi_i => skip_lbi_s,
is_lbi_o => is_lbi_s,
int_i => int_s,
pm_addr_i => pm_addr_s,
pm_data_i => pm_data_i
);
-----------------------------------------------------------------------------
-- Skip logic
-----------------------------------------------------------------------------
skip_b : t400_skip
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
op_i => skip_op_s,
dec_data_i => dec_data_s,
carry_i => carry_s,
c_i => c_s,
bd_i => b_s(bd_range_t),
is_lbi_i => is_lbi_s,
skip_o => skip_s,
skip_lbi_o => skip_lbi_s,
a_i => a_s,
m_i => dm_data_i,
g_i => io_g_s,
tim_c_i => tim_c_s
);
-----------------------------------------------------------------------------
-- ALU
-----------------------------------------------------------------------------
alu_b : t400_alu
generic map (
opt_cko_g => opt_cko_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
cko_i => cko_i,
op_i => alu_op_s,
m_i => dm_data_i,
dec_data_i => dec_data_s,
q_low_i => q_s(3 downto 0),
b_i => b_s,
g_i => io_g_s,
in_i => in_s,
sio_i => sio_s,
a_o => a_s,
carry_o => carry_s,
c_o => c_s
);
-----------------------------------------------------------------------------
-- Stack module
-----------------------------------------------------------------------------
stack_b : t400_stack
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
op_i => stack_op_s,
pc_i => pc_to_stack_s,
pc_o => pc_from_stack_s
);
-----------------------------------------------------------------------------
-- IO L module
-----------------------------------------------------------------------------
cs_n_s <= io_in_i(2);
rd_n_s <= io_in_i(1);
wr_n_s <= io_in_i(3);
--
io_l_b : t400_io_l
generic map (
opt_out_type_7_g => opt_l_out_type_7_g,
opt_out_type_6_g => opt_l_out_type_6_g,
opt_out_type_5_g => opt_l_out_type_5_g,
opt_out_type_4_g => opt_l_out_type_4_g,
opt_out_type_3_g => opt_l_out_type_3_g,
opt_out_type_2_g => opt_l_out_type_2_g,
opt_out_type_1_g => opt_l_out_type_1_g,
opt_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => opt_microbus_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
in_en_i => in_en_s,
op_i => io_l_op_s,
en2_i => en_s(2),
m_i => dm_data_i,
a_i => a_s,
pm_data_i => pm_data_i,
q_o => q_s,
cs_n_i => cs_n_s,
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
io_l_i => io_l_i,
io_l_o => io_l_o,
io_l_en_o => io_l_en_o
);
-----------------------------------------------------------------------------
-- IO D module
-----------------------------------------------------------------------------
io_d_b : t400_io_d
generic map (
opt_out_type_3_g => opt_d_out_type_3_g,
opt_out_type_2_g => opt_d_out_type_2_g,
opt_out_type_1_g => opt_d_out_type_1_g,
opt_out_type_0_g => opt_d_out_type_0_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
op_i => io_d_op_s,
bd_i => b_s(bd_range_t),
io_d_o => io_d_o,
io_d_en_o => io_d_en_o
);
-----------------------------------------------------------------------------
-- IO G module
-----------------------------------------------------------------------------
io_g_b : t400_io_g
generic map (
opt_out_type_3_g => opt_g_out_type_3_g,
opt_out_type_2_g => opt_g_out_type_2_g,
opt_out_type_1_g => opt_g_out_type_1_g,
opt_out_type_0_g => opt_g_out_type_0_g,
opt_microbus_g => opt_microbus_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
cs_n_i => cs_n_s,
wr_n_i => wr_n_s,
op_i => io_g_op_s,
m_i => dm_data_i,
dec_data_i => dec_data_s,
io_g_o => io_g_o,
io_g_en_o => io_g_en_o
);
-----------------------------------------------------------------------------
-- IO IN module
-----------------------------------------------------------------------------
use_in: if opt_type_g = t400_opt_type_420_c generate
io_in_b : t400_io_in
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
icyc_en_i => icyc_en_s,
in_en_i => in_en_s,
op_i => io_in_op_s,
en1_i => en_s(1),
io_in_i => io_in_i,
in_o => in_s,
int_o => int_s
);
end generate;
no_in: if opt_type_g /= t400_opt_type_420_c generate
in_s <= (others => '0');
int_s <= false;
end generate;
-----------------------------------------------------------------------------
-- SIO module
-----------------------------------------------------------------------------
sio_b : t400_sio
generic map (
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
phi1_i => phi1_s,
out_en_i => out_en_s,
in_en_i => in_en_s,
op_i => sio_op_s,
en0_i => en_s(0),
en3_i => en_s(3),
a_i => a_s,
c_i => c_s,
sio_o => sio_s,
si_i => si_i,
so_o => so_o,
so_en_o => so_en_o,
sk_o => sk_o,
sk_en_o => sk_en_o
);
-----------------------------------------------------------------------------
-- Timer module
-----------------------------------------------------------------------------
use_tim: if opt_type_g = t400_opt_type_420_c or
opt_type_g = t400_opt_type_421_c generate
timer_b : t400_timer
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
icyc_en_i => icyc_en_s,
op_i => skip_op_s,
c_o => tim_c_s
);
end generate;
notim: if opt_type_g /= t400_opt_type_420_c and
opt_type_g /= t400_opt_type_421_c generate
tim_c_s <= false;
end generate;
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.11 2008/05/01 19:51:12 arniml
-- removed obsolete signals
--
-- Revision 1.10 2006/06/11 13:34:39 arniml
-- Fix bug:
-- "Timer skipped in T421 configuration"
-- The generate block that instantiates the timer module considers
-- now t400_opt_type_421_x as well.
--
-- Revision 1.9 2006/06/06 00:33:56 arniml
-- remove note about limitations
--
-- Revision 1.8 2006/06/05 20:34:21 arniml
-- use dedicated microbus cs/rd/wr strobes
--
-- Revision 1.7 2006/06/05 14:19:15 arniml
-- connect microbus control signals to IO L
--
-- Revision 1.6 2006/05/27 19:11:33 arniml
-- updates for interrupt support
--
-- Revision 1.5 2006/05/23 01:13:56 arniml
-- use to_X01 for G input
--
-- Revision 1.4 2006/05/22 00:03:29 arniml
-- io_in added
--
-- Revision 1.3 2006/05/21 21:47:40 arniml
-- route cko to ALU for INIL instruction
--
-- Revision 1.2 2006/05/20 02:48:17 arniml
-- timer module included
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | f347aedddfa154a1b4499b81cb353cdb | 0.435988 | 3.035152 | false | false | false | false |
alvieboy/xtc-base | wbmux2.vhd | 1 | 2,232 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end entity wbmux2;
architecture behave of wbmux2 is
signal select_zero: std_logic;
begin
select_zero<='1' when m_wbi.adr(select_line)='0' else '0';
s0_wbo.dat <= m_wbi.dat;
s0_wbo.adr <= m_wbi.adr;
s0_wbo.stb <= m_wbi.stb;
s0_wbo.we <= m_wbi.we;
s0_wbo.sel <= m_wbi.sel;
s0_wbo.tag <= m_wbi.tag;
s0_wbo.cti <= m_wbi.cti;
s0_wbo.bte <= m_wbi.bte;
s1_wbo.dat <= m_wbi.dat;
s1_wbo.adr <= m_wbi.adr;
s1_wbo.stb <= m_wbi.stb;
s1_wbo.we <= m_wbi.we;
s1_wbo.sel <= m_wbi.sel;
s1_wbo.tag <= m_wbi.tag;
s1_wbo.cti <= m_wbi.cti;
s1_wbo.bte <= m_wbi.bte;
process(m_wbi.cyc,select_zero)
begin
if m_wbi.cyc='0' then
s0_wbo.cyc<='0';
s1_wbo.cyc<='0';
else
s0_wbo.cyc<=select_zero;
s1_wbo.cyc<=not select_zero;
end if;
end process;
process(select_zero,s1_wbi.stall,s0_wbi.stall)
begin
if select_zero='0' then
m_wbo.stall<=s1_wbi.stall;
else
m_wbo.stall<=s0_wbi.stall;
end if;
end process;
-- Process responses from both slaves.
-- USE ONLY IN SIMULATION FOR NOW!!!!!
process(s0_wbi,s1_wbi)
variable sel: std_logic_vector(1 downto 0);
begin
sel := s1_wbi.ack & s0_wbi.ack;
case sel is
when "00" =>
m_wbo.ack<='0';
m_wbo.err<='0';
m_wbo.dat<=(others => 'X');
m_wbo.tag<=(others => 'X');
when "01" =>
m_wbo.ack<='1';
m_wbo.err<=s0_wbi.err;
m_wbo.dat<=s0_wbi.dat;
m_wbo.tag<=s0_wbi.tag;
when "10" =>
m_wbo.ack<='1';
m_wbo.dat<=s1_wbi.dat;
m_wbo.err<=s1_wbi.err;
m_wbo.tag<=s1_wbi.tag;
when others =>
m_wbo.ack<='1';
m_wbo.err<='1';
m_wbo.dat<=(others => 'X');
m_wbo.tag<=(others => 'X');
end case;
end process;
end behave;
| bsd-3-clause | 513056396d48630db4fd323b528f5f99 | 0.582885 | 2.428727 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiv_components.vhd | 1 | 104,262 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiv_atom_pack.all;
package stratixiv_components is
--
-- stratixiv_jtag
--
COMPONENT stratixiv_jtag
generic (
lpm_type : string := "stratixiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratixiv_crcblock
--
COMPONENT stratixiv_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiv_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixiv_lcell_comb
--
COMPONENT stratixiv_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- stratixiv_routing_wire
--
COMPONENT stratixiv_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- stratixiv_lvds_transmitter
--
COMPONENT stratixiv_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- STRATIXIV
tx_output_path_delay_engineering_bits : Integer := -1; -- STRATIXIV
enable_dpaclk_to_lvdsout : string := "off"; -- STRATIXIV
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiv_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- STRATIXIV
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- STRATIXIV
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- STRATIXIV
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- stratixiv_rublock
--
COMPONENT stratixiv_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiv_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixiv_ram_block
--
COMPONENT stratixiv_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_ff
--
COMPONENT stratixiv_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- stratixiv_clkselect
--
COMPONENT stratixiv_clkselect
generic (
lpm_type : STRING := "stratixiv_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- stratixiv_clkena
--
COMPONENT stratixiv_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiv_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- stratixiv_mlab_cell
--
COMPONENT stratixiv_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiv_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_io_ibuf
--
COMPONENT stratixiv_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_io_obuf
--
COMPONENT stratixiv_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_ddio_in
--
COMPONENT stratixiv_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiv_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_ddio_oe
--
COMPONENT stratixiv_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_ddio_out
--
COMPONENT stratixiv_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_termination
--
COMPONENT stratixiv_termination
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END COMPONENT;
--
-- stratixiv_termination_logic
--
COMPONENT stratixiv_termination_logic
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiv_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
--
-- stratixiv_dll
--
COMPONENT stratixiv_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiv_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dll_offset_ctrl
--
COMPONENT stratixiv_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiv_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_dqs_delay_chain
--
COMPONENT stratixiv_dqs_delay_chain
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
test_enable : string := "false";
test_select : integer := 0;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dqs_enable
--
COMPONENT stratixiv_dqs_enable
GENERIC (
lpm_type : string := "stratixiv_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dqs_enable_ctrl
--
COMPONENT stratixiv_dqs_enable_ctrl
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_delay_chain
--
COMPONENT stratixiv_delay_chain
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiv_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_io_clock_divider
--
COMPONENT stratixiv_io_clock_divider
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_output_phase_alignment
--
COMPONENT stratixiv_output_phase_alignment
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiv_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_input_phase_alignment
--
COMPONENT stratixiv_input_phase_alignment
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_half_rate_input
--
COMPONENT stratixiv_half_rate_input
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiv_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_io_config
--
COMPONENT stratixiv_io_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiv_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dqs_config
--
COMPONENT stratixiv_dqs_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiv_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_mac_mult
--
COMPONENT stratixiv_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_mac_out
--
COMPONENT stratixiv_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiv_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_io_pad
--
COMPONENT stratixiv_io_pad
GENERIC (
lpm_type : string := "stratixiv_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- stratixiv_pll
--
COMPONENT stratixiv_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiv_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "STRATIXIV";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- stratixiv_asmiblock
--
COMPONENT stratixiv_asmiblock
generic (
lpm_type : string := "stratixiv_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- stratixiv_lvds_receiver
--
COMPONENT stratixiv_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiv_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_pseudo_diff_out
--
COMPONENT stratixiv_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_bias_block
--
COMPONENT stratixiv_bias_block
GENERIC (
lpm_type : string := "stratixiv_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
END COMPONENT;
--
-- stratixiv_tsdblock
--
COMPONENT stratixiv_tsdblock
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiv_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
END COMPONENT;
end stratixiv_components;
| gpl-3.0 | 496861750802dd18c01a4a24adc10a06 | 0.479974 | 4.337563 | false | false | false | false |
google/myelin-acorn-electron-hardware | serial_sd_adapter/cpld/serial_sd_adapter.vhd | 1 | 13,325 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- This implements a fast serial port with help from an AVR. It also includes
-- some code from spi_sd_card.vhd to support MMFS (bit-banged SD card interface)
-- and UPURS (bit-banged serial)
entity serial_sd_adapter is
Port (
-- Pins that connect to the Electron bus
elk_D : inout std_logic_vector(7 downto 0);
elk_nINFC : in std_logic;
elk_A7 : in std_logic;
elk_A6 : in std_logic;
elk_A5 : in std_logic;
elk_A4 : in std_logic;
elk_A2 : in std_logic;
elk_A1 : in std_logic;
elk_A0 : in std_logic;
elk_nRST : in std_logic;
elk_RnW : in std_logic;
elk_PHI0 : in std_logic;
-- Pins that would normally connect to the Raspberry Pi,
-- but are repurposed here for SPI to the AVR, SPI to the
-- SD card, and serial for UPURS.
-- AVR interface: MISO, MOSI, SCK, /SS, INT.
-- The first four are a standard SPI port, with the AVR as
-- controller and CPLD as peripheral. INT is an output from the CPLD
-- that goes high when we have a byte to send to the AVR.
--
-- Future plans:
--
-- * Add a clock line so the AVR can provide a 2 or 4MHz clock
-- to the CPLD. 4M/35 = 114.285kHz, which is probably within
-- UPURS's acceptable range. See below.
-- SD interface: MISO, MOSI, SCK, /SS
-- UPURS interface: RXD, TXD
-- This mostly works for the UPURS suite of tools when attached
-- to an AVR running upurs_usb_port.ino (in this repo), but
-- is unreliable against HostFS:UPURS. An interesting experiment
-- might be to handle the serial port in the CPLD (with the AVR
-- providing a 2MHz or 4MHz clock for timing).
-- We could use the AVR's 64MHz PLL clock divided by 139, which
-- would give us 115108 Hz * 4, i.e. just about perfect to drive
-- the UART. OC4A and /OC4A are PC6 (D5) and PC7 (D13). See
-- comments in serial_sd_mcu.ino for more detail.
-- (Alternatively we can provide the entire serial port, ignore
-- the rate entirely, and just clock a shift register when we get
-- a read or write, but that wouldn't work with unmodified UPURS.)
-- Pins without comments below are unused.
tube_A0 : out std_logic; -- avr MISO
tube_A1 : out std_logic; -- serial TXD
tube_A2 : in std_logic; -- serial RXD
tube_D : inout std_logic_vector(7 downto 0);
-- D0 = sd MISO
-- D1 = avr /SD_SS
-- D2 = avr /SS = /SD_SEL
-- D3
-- D4 = avr SCK
-- D5 = sd /SS
-- D6 = sd MOSI
-- D7 = sd SCK
tube_nRST : out std_logic; -- serial RTS
tube_nTUBE : out std_logic; -- avr INT (1 when we want attention from the AVR)
tube_RnW : in std_logic; -- avr MOSI
tube_PHI0 : in std_logic
);
end serial_sd_adapter;
architecture Behavioural of serial_sd_adapter is
---- Globals ----
signal A_lower : std_logic_vector(7 downto 0);
---- Fast SPI port (peripheral, for AVR) ----
signal avr_MOSI : std_logic; -- input from AVR
signal avr_MISO : std_logic; -- output to AVR
signal avr_SCK : std_logic; -- input from AVR
signal avr_nSS : std_logic; -- input from AVR
signal avr_INT : std_logic; -- output to AVR
signal avr_nSD_SEL : std_logic; -- input from AVR
signal nAVR_SPI : std_logic; -- '0' when A = &FCA0;
signal nAVR_SPI_STATUS : std_logic; -- '0' when A = &FCA1;
-- we use a toggle synchronizer to know if the buffer is full or empty.
-- RECEPTION FROM AVR TO CPLD+ELK:
-- on the avr side, it's safe to receive a byte if avr_RXD_state = elk_RXD_state_sync
-- on the elk side, it's safe to read a byte if elk_RXD_state != avr_RXD_state_sync
-- we just use a single flip flop to synchronize in each case, because there's always
-- a longish settling time.
-- TRANSMISSION FROM ELK+CPLD TO AVR:
-- it's safe to accept a byte from the elk for transmission if elk_TXD_state == avr_TXD_state_sync
-- it's safe to transmit a byte to the avr if avr_TXD_state != elk_TXD_state_sync
signal avr_RXD_state : std_logic := '0'; -- toggles whenever the CPLD receives a byte from the AVR
signal avr_RXD_state_sync : std_logic := '0'; -- avr_RXD_state synchronized to elk_PHI0
signal elk_RXD_state : std_logic := '0'; -- toggles when the elk reads a byte
signal elk_RXD_state_sync : std_logic := '0'; -- elk_RXD_state synchronized to avr_SCK
signal avr_TXD_state : std_logic := '0'; -- toggles whenever the CPLD sends a byte to the AVR
signal avr_TXD_state_sync : std_logic := '0'; -- avr_TXD_state synchronized to elk_PHI0
signal elk_TXD_state : std_logic := '0'; -- toggles when the elk writes a byte
signal elk_TXD_state_sync : std_logic := '0'; -- elk_TXD_state synchronized to avr_SCK
signal avr_RXD : std_logic_vector(7 downto 0); -- byte received from AVR
signal avr_TXD : std_logic_vector(7 downto 0); -- next byte to transmit / being transmitted to AVR
-- signals used during an SPI transaction
signal avr_spi_SHIFT : std_logic_vector(7 downto 0); -- SPI shift register
signal avr_spi_bit_count : std_logic_vector(3 downto 0); -- SPI bit counter for transfers
signal avr_spi_receiving : std_logic := '0'; -- copy bits into avr_RXD and toggle avr_RXD_state when done
signal avr_spi_transmitting : std_logic := '0'; -- toggle avr_TXD_state when done
---- Serial port ----
signal TXD : std_logic := '1'; -- output from CPLD/Electron
signal RXD : std_logic; -- input to CPLD/Electron
signal RTS : std_logic := '1'; -- request for data from PC
signal CTS : std_logic; -- PC is allowing us to send
signal invert_serial : std_logic := '0'; -- invert serial port for UPURS
-- chip selects
signal nSERIAL_IO : std_logic; -- '0' when A = &FCB1
---- SPI (controller, for SD card) ---
signal MOSI : std_logic := '1';
signal MISO : std_logic;
signal SCK : std_logic := '1';
signal nSS : std_logic := '0';
---- Plus 1 workalike registers ----
-- chip selects
signal nDATA : std_logic; -- '0' when A = &FC71
signal nSTATUS : std_logic; -- '0' when A = &FC72
begin
-- mappings to actual pins
avr_MOSI <= tube_RnW;
tube_A0 <= 'Z' when avr_nSS = '1' else
MISO when avr_nSD_SEL = '0' else
avr_MISO;
avr_SCK <= tube_D(4);
avr_nSS <= tube_D(2);
avr_nSD_SEL <= tube_D(2);
tube_nTUBE <= avr_INT;
tube_D(5) <= avr_nSS when avr_nSD_SEL = '0' else nSS;
tube_D(6) <= avr_MOSI when avr_nSD_SEL = '0' else MOSI;
tube_D(7) <= avr_SCK when avr_nSD_SEL = '0' else SCK;
MISO <= tube_D(0);
tube_A1 <= TXD; -- tx output
RXD <= tube_A2; -- rx input
tube_nRST <= RTS; -- permit remote station to send when RTS=1
CTS <= '1'; -- assume we can always send to the remote station
-- address comparison convenience (note missing A3 in elk_pi_tube_direct r1)
A_lower <= elk_A7 & elk_A6 & elk_A5 & elk_A4 & '0' & elk_A2 & elk_A1 & elk_A0;
---- Fast SPI peripheral for AVR ---
nAVR_SPI <= '0' when (elk_nINFC = '0' and A_lower = x"A0") else '1';
nAVR_SPI_STATUS <= '0' when (elk_nINFC = '0' and A_lower = x"A1") else '1';
avr_INT <= '1' when (elk_TXD_state /= avr_TXD_state_sync) else '0';
---- Bit-banged serial port for UPURS ---
nSERIAL_IO <= '0' when (elk_nINFC = '0' and A_lower = x"B1") else '1';
---- Plus 1 parallel port emulation ----
nDATA <= '0' when (elk_nINFC = '0' and A_lower = x"71") else '1';
nSTATUS <= '0' when (elk_nINFC = '0' and A_lower = x"72") else '1';
---- Data bus ----
elk_D <=
-- AVR SPI data
avr_RXD when (nAVR_SPI = '0' and elk_RnW = '1') else
-- AVR SPI status
"000000" & (elk_TXD_state xnor avr_TXD_state_sync) & (elk_RXD_state xor avr_RXD_state_sync)
when (nAVR_SPI_STATUS = '0' and elk_RnW = '1') else
-- Serial port
(RXD xor invert_serial) & "11111" & CTS & "1" when (nSERIAL_IO = '0' and elk_RnW = '1') else
-- Plus 1 parallel port
MISO & "0000000" when (nSTATUS = '0' and elk_RnW = '1') else
-- default
"ZZZZZZZZ";
-- AVR SPI clock domain
process (avr_nSS, avr_SCK)
begin
-- RISING EDGE of avr_SCK: read avr_MOSI
if avr_nSS = '1' then
-- asynchronous reset (must not happen on an avr_SCK edge)
avr_spi_bit_count <= x"0";
elsif rising_edge(avr_SCK) then
-- increment the count each time
avr_spi_bit_count <= std_logic_vector(unsigned(avr_spi_bit_count) + 1);
-- clock in a bit, depending on avr_spi_bit_count
if avr_spi_bit_count = x"0" then
-- synchronize elk_RXD_state and elk_TXD_state
elk_RXD_state_sync <= elk_RXD_state;
elk_TXD_state_sync <= elk_TXD_state;
elsif avr_spi_bit_count = x"6" then
-- SPI is big-endian, so we want to ignore incoming bits 0-5.
-- bit 6 (1) tells us if the remote wants to send a byte
avr_spi_receiving <= (
avr_MOSI -- '1' if the remote has a byte for us
and (avr_RXD_state xnor elk_RXD_state_sync) -- '1' if we have room in our buffer
);
elsif avr_spi_bit_count = x"7" then
-- bit 7 (0) tells us if the remote is capable of receiving a byte
avr_spi_transmitting <= (
avr_MOSI -- '1' if the remote has buffer space
and (avr_TXD_state xor elk_TXD_state_sync) -- '1' if we have a byte to transmit
);
-- copy avr_TXD into the shift register if it's safe
if avr_TXD_state /= elk_TXD_state_sync then
avr_spi_SHIFT <= avr_TXD;
end if;
elsif avr_spi_bit_count(3) = '1' then
-- clock in a bit if we have buffer space
avr_spi_SHIFT <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
if avr_spi_bit_count = x"F" then
if avr_spi_receiving = '1' then
avr_RXD_state <= not avr_RXD_state;
avr_RXD <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
end if;
if avr_spi_transmitting = '1' then
avr_TXD_state <= not avr_TXD_state;
end if;
end if;
end if;
end if;
-- FALLING EDGE of avr_SCK: write avr_MISO
if avr_nSS = '1' then
elsif falling_edge(avr_SCK) then
-- We always update MISO on an avr_SCK falling edge.
if avr_spi_bit_count = x"6" then
-- '1' if we have a byte to send to the AVR
avr_MISO <= avr_TXD_state xor elk_TXD_state_sync;
elsif avr_spi_bit_count = x"7" then
-- '1' if we can accept a byte from the AVR
avr_MISO <= avr_RXD_state xnor elk_RXD_state_sync;
elsif avr_spi_bit_count(3) = '1' then
avr_MISO <= avr_spi_SHIFT(7);
end if;
end if;
end process;
-- Electron clock domain
process (elk_PHI0)
begin
if falling_edge(elk_PHI0) then
-- AVR SPI registers
avr_RXD_state_sync <= avr_RXD_state;
avr_TXD_state_sync <= avr_TXD_state;
if nAVR_SPI = '0' and elk_RnW = '0' and elk_TXD_state = avr_TXD_state_sync then
-- we're writing to the TXD register
avr_TXD <= elk_D;
elk_TXD_state <= not elk_TXD_state;
end if;
if nAVR_SPI = '0' and elk_RnW = '1' and elk_RXD_state /= avr_RXD_state_sync then
-- the electron just read avr_RXD
elk_RXD_state <= not elk_RXD_state;
end if;
if nAVR_SPI_STATUS = '0' and elk_RnW = '0' then
-- we never write to the status register
end if;
-- Serial port: Electron is writing RTS and TXD bits
if nSERIAL_IO = '0' and elk_RnW = '0' then
RTS <= elk_D(6);
TXD <= elk_D(0) xor invert_serial;
end if;
-- Bit-banged SPI
if nDATA = '0' and elk_RnW = '0' then
-- handle write to &FC71
MOSI <= elk_D(0);
SCK <= elk_D(1);
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | df82d5f3c97b3f82a2f8cc23bdacf77a | 0.570432 | 3.480021 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratix_components.vhd | 1 | 32,343 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratix_atom_pack.all;
package stratix_components is
--
-- stratix_lcell
--
COMPONENT stratix_lcell
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "stratix_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
--
-- stratix_io
--
COMPONENT stratix_io
GENERIC (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
extend_oe_disable : string := "false";
sim_dll_phase_shift : string := "0";
sim_dqs_input_frequency : string := "10000 ps";
lpm_type : string := "stratix_io"
);
PORT (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
delayctrlin : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsundelayedout : out std_logic;
padio : inout std_logic
);
END COMPONENT;
--
-- stratix_mac_mult
--
COMPONENT stratix_mac_mult
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratix_mac_mult"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector((dataa_width+datab_width)-1 downto 0);
scanouta : out std_logic_vector(dataa_width-1 downto 0);
scanoutb : out std_logic_vector(datab_width-1 downto 0)
);
END COMPONENT;
--
-- stratix_mac_out
--
COMPONENT stratix_mac_out
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 36;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
overflow_programmable_invert : std_logic := '0';
data_out_programmable_invert : std_logic_vector(71 downto 0) := (OTHERS => '0');
lpm_hint : string := "true";
lpm_type : string := "stratix_mac_out"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (dataout_width-1 downto 0);
accoverflow : out std_logic
);
END COMPONENT;
--
-- stratix_ram_block
--
COMPONENT stratix_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "stratix_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratix_lvds_transmitter
--
COMPONENT stratix_lvds_transmitter
GENERIC (
channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
lpm_type : string := "stratix_lvds_transmitter";
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
--
-- stratix_lvds_receiver
--
COMPONENT stratix_lvds_receiver
GENERIC (
channel_width : integer := 1;
use_enable1 : String := "false";
lpm_type : string := "stratix_lvds_receiver";
InstancePath : String := "*"
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
enable1 : in std_logic := '0';
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
--
-- stratix_pll
--
COMPONENT stratix_pll
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "stratix_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
scan_chain_mif_file : string := "";
family_name : string := "Stratix";
skip_vco : string := "off";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END COMPONENT;
--
-- stratix_dll
--
COMPONENT stratix_dll
GENERIC ( input_frequency : string := "10000 ps";
phase_shift : string := "0";
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5;
lpm_type : string := "stratix_dll";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
delayctrlout : OUT std_logic
);
END COMPONENT;
--
-- stratix_jtag
--
COMPONENT stratix_jtag
generic (
lpm_type : string := "stratix_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratix_crcblock
--
COMPONENT stratix_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratix_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratix_rublock
--
COMPONENT stratix_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratix_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- stratix_routing_wire
--
COMPONENT stratix_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
end stratix_components;
| gpl-3.0 | 500d23292af149f5a01f992956ad603c | 0.427882 | 4.211328 | false | false | false | false |
EPiCS/reconos | demos/matrixmul/hw/hwt_matrixmul_v2_00_a/hdl/vhdl/hwt_matrixmul.vhd | 2 | 14,885 | ------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hwt_matrixmul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_matrixmul;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture implementation of hwt_matrixmul is
type STATE_TYPE is (
STATE_GET_ADDR2MADDRS,
STATE_READ_MADDRS,
STATE_READ_MATRIX_B,
STATE_READ_MATRIX_ROW_FROM_A,
STATE_MULTIPLY_MATRIX_ROW,
STATE_WRITE_MATRIX_ROW_TO_C,
STATE_ACK,
STATE_THREAD_EXIT
);
component matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_WE : out std_logic
);
end component;
--constant C_LINE_LEN_MATRIX : integer := 128;
-- Use the following line for testing purposes.
constant C_LINE_LEN_MATRIX : integer := 4;
-- const for matrixes A and C
constant C_LOCAL_RAM_SIZE_MATRIX_A_C : integer := C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_A_C);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_A_C;
type LOCAL_MEMORY_TYPE_MATRIX_A_C is array(0 to C_LOCAL_RAM_SIZE_MATRIX_A_C - 1) of std_logic_vector(31 downto 0);
-- const for matrix B
constant C_LOCAL_RAM_SIZE_MATRIX_B : integer := C_LINE_LEN_MATRIX*C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_B);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_B;
type LOCAL_MEMORY_TYPE_MATRIX_B is array(0 to C_LOCAL_RAM_SIZE_MATRIX_B - 1) of std_logic_vector(31 downto 0);
-- communication with microblaze core
constant C_MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant C_MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal ignore : std_logic_vector(31 downto 0);
-- maddr is an acronym for "matrix address" (address that points to a matrix)
constant C_MADDRS : integer := 3;
type MADDR_BOX_TYPE is array(0 to C_MADDRS-1) of std_logic_vector(31 downto 0);
-- container for adresses pointing to the first element of matrixes A, B and C
signal maddrs : MADDR_BOX_TYPE;
-- points to pointers to the matrixes
signal addr2maddrs : std_logic_vector(31 downto 0);
-- temporary signals
signal temp_addr_A : std_logic_vector(31 downto 0);
signal temp_addr_C : std_logic_vector(31 downto 0);
-- fsm state
signal state : STATE_TYPE;
-- additional data for memif interfaces
signal len_data_MATRIX_A_C : std_logic_vector(23 downto 0);
signal len_data_MATRIX_B : std_logic_vector(23 downto 0);
-- osif, memif and different local BRAM interfaces
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram_A : i_ram_t;
signal o_ram_A : o_ram_t;
signal i_ram_B : i_ram_t;
signal o_ram_B : o_ram_t;
signal i_ram_C : i_ram_t;
signal o_ram_C : o_ram_t;
signal o_RAM_A_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_A_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_WE_reconos : std_logic;
signal i_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal o_RAM_B_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_WE_reconos : std_logic;
signal i_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_WE_reconos : std_logic;
signal i_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal i_RAM_A_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal i_RAM_B_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_WE_mul : std_logic;
shared variable local_ram_a : LOCAL_MEMORY_TYPE_MATRIX_A_C;
shared variable local_ram_b : LOCAL_MEMORY_TYPE_MATRIX_B;
shared variable local_ram_c : LOCAL_MEMORY_TYPE_MATRIX_A_C;
signal multiplier_start : std_logic;
signal multiplier_done : std_logic;
signal clk, rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local BRAM read and write access
local_ram_ctrl_1 : process (clk) is
begin
if (clk'event and clk = '1') then
if (o_RAM_A_WE_reconos = '1') then
local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_reconos))) := o_RAM_A_Data_reconos;
end if;
if (o_RAM_B_WE_reconos = '1') then
local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_reconos))) := o_RAM_B_Data_reconos;
end if;
if (o_RAM_C_WE_reconos = '0') then
i_RAM_C_Data_reconos <= local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAM_C_WE_mul = '1') then
local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_mul))) := o_RAM_C_Data_mul;
else
i_RAM_A_Data_mul <= local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_mul)));
i_RAM_B_Data_mul <= local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_mul)));
end if;
end if;
end process;
-- the matrix multiplication module
matrixmultiplier_i : matrixmultiplier
generic map(
G_LINE_LEN_MATRIX => C_LINE_LEN_MATRIX,
G_RAM_DATA_WIDTH => 32,
G_RAM_SIZE_MATRIX_A_C => C_LOCAL_RAM_SIZE_MATRIX_A_C,
G_RAM_ADDR_WIDTH_MATRIX_A_C => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C,
G_RAM_SIZE_MATRIX_B => C_LOCAL_RAM_SIZE_MATRIX_B,
G_RAM_ADDR_WIDTH_MATRIX_B => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B
)
port map(
clk => clk,
reset => rst,
start => multiplier_start,
done => multiplier_done,
o_RAM_A_Addr => o_RAM_A_Addr_mul,
i_RAM_A_Data => i_RAM_A_Data_mul,
o_RAM_B_Addr => o_RAM_B_Addr_mul,
i_RAM_B_Data => i_RAM_B_Data_mul,
o_RAM_C_Addr => o_RAM_C_Addr_mul,
o_RAM_C_Data => o_RAM_C_Data_mul,
o_RAM_C_WE => o_RAM_C_WE_mul
);
-- setup interfaces (FIFOs, FSL,...)
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram_A,
o_ram_A,
o_RAM_A_Addr_reconos_2,
o_RAM_A_WE_reconos,
o_RAM_A_Data_reconos,
i_RAM_A_Data_reconos
);
ram_setup (
i_ram_B,
o_ram_B,
o_RAM_B_Addr_reconos_2,
o_RAM_B_WE_reconos,
o_RAM_B_Data_reconos,
i_RAM_B_Data_reconos
);
ram_setup (
i_ram_C,
o_ram_C,
o_RAM_C_Addr_reconos_2,
o_RAM_C_WE_reconos,
o_RAM_C_Data_reconos,
i_RAM_C_Data_reconos
);
o_RAM_A_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_A_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
o_RAM_B_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1) <= o_RAM_B_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B ) to 31);
o_RAM_C_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_C_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
reconos_fsm : process(clk, rst, o_osif, o_memif, o_ram_a, o_ram_b, o_ram_c) is
variable done : boolean;
variable addr_pos : integer;
variable calculated_rows : integer;
begin
if (rst = '1') then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram_A);
ram_reset(o_ram_B);
ram_reset(o_ram_C);
multiplier_start <= '0';
done := false;
calculated_rows := 0;
len_data_MATRIX_A_C <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C, 24);
len_data_MATRIX_B <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B , 24);
-- important to know:
-- maddrs(0) = C, maddrs(1) = B, maddrs(2) = A
addr2maddrs <= (others => '0');
addr_pos := C_MADDRS - 1;
for i in 0 to (C_MADDRS - 1) loop
maddrs(i) <= (others => '0');
end loop;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
elsif (clk'event and clk = '1') then
case state is
-- Get address pointing to the addresses pointing to the 3 matrixes via FSL.
when STATE_GET_ADDR2MADDRS =>
osif_mbox_get(i_osif, o_osif, C_MBOX_RECV, addr2maddrs, done);
if (done) then
if (addr2maddrs = x"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
addr2maddrs <= addr2maddrs(31 downto 2) & "00";
addr_pos := C_MADDRS - 1;
state <= STATE_READ_MADDRS;
end if;
end if;
-- Read addresses pointing to input matrixes A, B and output matrix C from main memory.
when STATE_READ_MADDRS =>
memif_read_word(i_memif, o_memif, addr2maddrs, maddrs(addr_pos), done);
if done then
if (addr_pos = 0) then
state <= STATE_READ_MATRIX_B;
else
addr_pos := addr_pos - 1;
addr2maddrs <= conv_std_logic_vector(unsigned(addr2maddrs) + 4, 32);
end if;
end if;
-- Read matrix B from main memory.
when STATE_READ_MATRIX_B =>
memif_read(i_ram_B, o_ram_B, i_memif, o_memif, maddrs(1), X"00000000", len_data_MATRIX_B, done);
if done then
temp_addr_A <= maddrs(2);
temp_addr_C <= maddrs(0);
state <= STATE_READ_MATRIX_ROW_FROM_A;
end if;
-- Read a row of matrix A.
when STATE_READ_MATRIX_ROW_FROM_A =>
memif_read(i_ram_A, o_ram_A, i_memif, o_memif, temp_addr_A, X"00000000", len_data_MATRIX_A_C, done);
if done then
multiplier_start <= '1';
state <= STATE_MULTIPLY_MATRIX_ROW;
end if;
-- Multiply row of matrix A with matrix B.
when STATE_MULTIPLY_MATRIX_ROW =>
multiplier_start <= '0';
if (multiplier_done = '1') then
calculated_rows := calculated_rows + 1;
state <= STATE_WRITE_MATRIX_ROW_TO_C;
end if;
-- Write multiplication result (row of matrix C) to main memory.
when STATE_WRITE_MATRIX_ROW_TO_C =>
memif_write(i_ram_C, o_ram_C, i_memif, o_memif, X"00000000", temp_addr_C, len_data_MATRIX_A_C, done);
if (done) then
if (calculated_rows < C_LINE_LEN_MATRIX) then
-- Calculate new temporary addresses
-- => to fetch next matrix row of matrix A
-- => to store calculated values to next matrix row of matrix C
temp_addr_A <= conv_std_logic_vector(unsigned(temp_addr_A) + C_LINE_LEN_MATRIX*4, 32);
temp_addr_C <= conv_std_logic_vector(unsigned(temp_addr_C) + C_LINE_LEN_MATRIX*4, 32);
state <= STATE_READ_MATRIX_ROW_FROM_A;
else
state <= STATE_ACK;
end if;
end if;
-- We finished calculating matrix multiplication A * B = C.
when STATE_ACK =>
osif_mbox_put(i_osif, o_osif, C_MBOX_SEND, maddrs(addr_pos), ignore, done);
if (done) then
calculated_rows := 0;
addr_pos := C_MADDRS - 1;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
end if;
-- Terminate hardware thread.
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif, o_osif);
end case;
end if;
end process;
end architecture implementation;
| gpl-2.0 | 2e901fe61814416c5dd9b9c8b5a0b5ab | 0.612026 | 2.668998 | false | false | false | false |
freecores/t400 | rtl/tech/generic/generic_ram_ena.vhd | 1 | 3,184 | -------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM with enable.
--
-- $Id: generic_ram_ena.vhd,v 1.3 2008-04-27 22:13:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity generic_ram_ena is
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
ena_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end generic_ram_ena;
library ieee;
use ieee.numeric_std.all;
architecture rtl of generic_ram_ena is
type mem_t is array (natural range 0 to 2**addr_width_g-1) of
std_logic_vector(d_i'range);
signal mem_q : mem_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
begin
mem: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if ena_i = '1' then
if we_i = '1' then
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;
d_o <= mem_q(to_integer(unsigned(a_i)));
end if;
end if;
end process mem;
end rtl;
| gpl-2.0 | 7c0cb49477b598954a1ac1062050298f | 0.661746 | 3.854722 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/altera_lnsim_components.vhd | 1 | 35,629 | -- Copyright (C) 1991-2010 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
library ieee;
use ieee.std_logic_1164.all;
package altera_lnsim_components is
component altera_pll
generic(
reference_clock_frequency: string := "0 ps";
pll_type : string := "General";
number_of_clocks: integer := 1;
operation_mode : string := "internal feedback";
deserialization_factor: integer := 4;
data_rate : integer := 0;
clock_switchover_mode: string := "Auto";
clock_switchover_delay: integer := 3;
sim_additional_refclk_cycles_to_lock: integer := 0;
output_clock_frequency0: string := "0 ps";
phase_shift0 : string := "0 ps";
duty_cycle0 : integer := 50;
output_clock_frequency1: string := "0 ps";
phase_shift1 : string := "0 ps";
duty_cycle1 : integer := 50;
output_clock_frequency2: string := "0 ps";
phase_shift2 : string := "0 ps";
duty_cycle2 : integer := 50;
output_clock_frequency3: string := "0 ps";
phase_shift3 : string := "0 ps";
duty_cycle3 : integer := 50;
output_clock_frequency4: string := "0 ps";
phase_shift4 : string := "0 ps";
duty_cycle4 : integer := 50;
output_clock_frequency5: string := "0 ps";
phase_shift5 : string := "0 ps";
duty_cycle5 : integer := 50;
output_clock_frequency6: string := "0 ps";
phase_shift6 : string := "0 ps";
duty_cycle6 : integer := 50;
output_clock_frequency7: string := "0 ps";
phase_shift7 : string := "0 ps";
duty_cycle7 : integer := 50;
output_clock_frequency8: string := "0 ps";
phase_shift8 : string := "0 ps";
duty_cycle8 : integer := 50;
output_clock_frequency9: string := "0 ps";
phase_shift9 : string := "0 ps";
duty_cycle9 : integer := 50;
output_clock_frequency10: string := "0 ps";
phase_shift10 : string := "0 ps";
duty_cycle10 : integer := 50;
output_clock_frequency11: string := "0 ps";
phase_shift11 : string := "0 ps";
duty_cycle11 : integer := 50;
output_clock_frequency12: string := "0 ps";
phase_shift12 : string := "0 ps";
duty_cycle12 : integer := 50;
output_clock_frequency13: string := "0 ps";
phase_shift13 : string := "0 ps";
duty_cycle13 : integer := 50;
output_clock_frequency14: string := "0 ps";
phase_shift14 : string := "0 ps";
duty_cycle14 : integer := 50;
output_clock_frequency15: string := "0 ps";
phase_shift15 : string := "0 ps";
duty_cycle15 : integer := 50;
output_clock_frequency16: string := "0 ps";
phase_shift16 : string := "0 ps";
duty_cycle16 : integer := 50;
output_clock_frequency17: string := "0 ps";
phase_shift17 : string := "0 ps";
duty_cycle17 : integer := 50
);
port(
refclk : in std_logic;
fbclk : in std_logic;
rst : in std_logic;
outclk : out std_logic_vector(number_of_clocks - 1 downto 0);
fboutclk : out std_logic;
locked : out std_logic;
zdbfbclk : inout std_logic
);
end component;
component generic_pll
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0
);
port(
refclk : in std_logic;
rst : in std_logic := '0';
fbclk : in std_logic;
writerefclkdata : in std_logic_vector(63 downto 0) := (others => '0');
writeoutclkdata : in std_logic_vector(63 downto 0) := (others => '0');
writephaseshiftdata : in std_logic_vector(63 downto 0) := (others => '0');
writedutycycledata : in std_logic_vector(63 downto 0) := (others => '0');
outclk : out std_logic;
locked : out std_logic;
fboutclk : out std_logic;
readrefclkdata : out std_logic_vector(63 downto 0);
readoutclkdata : out std_logic_vector(63 downto 0);
readphaseshiftdata : out std_logic_vector(63 downto 0);
readdutycycledata : out std_logic_vector(63 downto 0)
);
end component;
component generic_cdr
generic(
reference_clock_frequency: string := "0 ps";
output_clock_frequency: string := "0 ps"
);
port(
extclk : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
ppmlock : in std_logic;
refclk : in std_logic;
rst : in std_logic;
sd : in std_logic;
rxp : in std_logic;
clk90bdes : out std_logic;
clk270bdes : out std_logic;
clklow : out std_logic;
deven : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pfdmodelock : out std_logic;
rxplllock : out std_logic
);
end component;
COMPONENT generic_m20k
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
ecc_pipeline_stage_enabled : STRING := "false";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 2;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
bist_ena : STRING := "false";
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock : STRING := "clock1";
port_b_read_enable_clock : STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : STRING := "stratixv_ram_block";
lpm_hint : STRING := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : STRING := "";
mem_init1 : STRING := "";
mem_init2 : STRING := "";
mem_init3 : STRING := "";
mem_init4 : STRING := "";
mem_init5 : STRING := "";
mem_init6 : STRING := "";
mem_init7 : STRING := "";
mem_init8 : STRING := "";
mem_init9 : STRING := "";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
nerror : IN STD_LOGIC := '1';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT generic_m10k
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
ecc_pipeline_stage_enabled : STRING := "false";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 2;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
bist_ena : STRING := "false";
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock : STRING := "clock1";
port_b_read_enable_clock : STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : STRING := "arriav_ram_block";
lpm_hint : STRING := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : STRING := "";
mem_init1 : STRING := "";
mem_init2 : STRING := "";
mem_init3 : STRING := "";
mem_init4 : STRING := "";
connectivity_checking : STRING := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
nerror : IN STD_LOGIC := '1';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT generic_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "stratixv_lutram";
lpm_hint : STRING := "true";
mem_init0 : STRING := "";
mixed_port_feed_through_mode : STRING := "new"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
clr : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
component altera_functions
end component;
component generic_mux
port(
din : in std_logic_vector(63 downto 0);
sel : in std_logic_vector(5 downto 0);
dout : out std_logic_vector
);
end component;
component generic_device_pll
generic(
reference_clock_frequency : string := "0 ps";
output_clock_frequency : string := "0 ps";
forcelock : string := "false";
nreset_invert : string := "false";
pll_enable : string := "true";
pll_fbclk_mux_1 : string := "glb";
pll_fbclk_mux_2 : string := "fb_1";
pll_m_cnt_bypass_en : string := "false";
pll_m_cnt_hi_div : integer := 1;
pll_m_cnt_in_src : string := "ph_mux_clk";
pll_m_cnt_lo_div : integer := 1;
pll_n_cnt_bypass_en : string := "false";
pll_n_cnt_hi_div : integer := 1;
pll_n_cnt_lo_div : integer := 1;
pll_vco_ph0_en : string := "false";
pll_vco_ph1_en : string := "false";
pll_vco_ph2_en : string := "false";
pll_vco_ph3_en : string := "false";
pll_vco_ph4_en : string := "false";
pll_vco_ph5_en : string := "false";
pll_vco_ph6_en : string := "false";
pll_vco_ph7_en : string := "false"
);
port(
coreclkfb : in std_logic;
fbclkfpll : in std_logic;
lvdsfbin : in std_logic;
nresync : in std_logic;
pfden : in std_logic;
refclkin : in std_logic;
zdb : in std_logic;
fbclk : out std_logic;
fblvdsout : out std_logic;
lock : out std_logic;
vcoph : out std_logic_vector(7 downto 0)
);
end component;
component altera_mult_add
GENERIC (
extra_latency : INTEGER := 0;
dedicated_multiplier_circuitry : STRING := "AUTO";
dsp_block_balancing : STRING := "AUTO";
selected_device_family : STRING := "Stratix V";
lpm_type : STRING := "altmult_add";
lpm_hint : STRING := "UNUSED";
width_a : INTEGER := 1;
input_register_a0 : STRING := "CLOCK0";
input_aclr_a0 : STRING := "ACLR0";
input_source_a0 : STRING := "DATAA";
input_register_a1 : STRING := "CLOCK0";
input_aclr_a1 : STRING := "ACLR0";
input_source_a1 : STRING := "DATAA";
input_register_a2 : STRING := "CLOCK0";
input_aclr_a2 : STRING := "ACLR0";
input_source_a2 : STRING := "DATAA";
input_register_a3 : STRING := "CLOCK0";
input_aclr_a3 : STRING := "ACLR0";
input_source_a3 : STRING := "DATAA";
width_b : INTEGER := 1;
input_register_b0 : STRING := "CLOCK0";
input_aclr_b0 : STRING := "ACLR0";
input_source_b0 : STRING := "DATAB";
input_register_b1 : STRING := "CLOCK0";
input_aclr_b1 : STRING := "ACLR0";
input_source_b1 : STRING := "DATAB";
input_register_b2 : STRING := "CLOCK0";
input_aclr_b2 : STRING := "ACLR0";
input_source_b2 : STRING := "DATAB";
input_register_b3 : STRING := "CLOCK0";
input_aclr_b3 : STRING := "ACLR0";
input_source_b3 : STRING := "DATAB";
width_c : INTEGER := 1;
input_register_c0 : STRING := "CLOCK0";
input_aclr_c0 : STRING := "ACLR0";
input_register_c1 : STRING := "CLOCK0";
input_aclr_c1 : STRING := "ACLR0";
input_register_c2 : STRING := "CLOCK0";
input_aclr_c2 : STRING := "ACLR0";
input_register_c3 : STRING := "CLOCK0";
input_aclr_c3 : STRING := "ACLR0";
width_result : INTEGER := 34;
output_register : STRING := "CLOCK0";
output_aclr : STRING := "ACLR3";
port_signa : STRING := "PORT_CONNECTIVITY";
representation_a : STRING := "UNSIGNED";
signed_register_a : STRING := "CLOCK0";
signed_aclr_a : STRING := "ACLR0";
signed_pipeline_register_a : STRING := "CLOCK0";
signed_pipeline_aclr_a : STRING := "ACLR3";
port_signb : STRING := "PORT_CONNECTIVITY";
representation_b : STRING := "UNSIGNED";
signed_register_b : STRING := "CLOCK0";
signed_aclr_b : STRING := "ACLR0";
signed_pipeline_register_b : STRING := "CLOCK0";
signed_pipeline_aclr_b : STRING := "ACLR3";
number_of_multipliers : INTEGER := 1;
multiplier1_direction : STRING := "UNUSED";
multiplier3_direction : STRING := "UNUSED";
multiplier_register0 : STRING := "CLOCK0";
multiplier_aclr0 : STRING := "ACLR3";
multiplier_register1 : STRING := "CLOCK0";
multiplier_aclr1 : STRING := "ACLR3";
multiplier_register2 : STRING := "CLOCK0";
multiplier_aclr2 : STRING := "ACLR3";
multiplier_register3 : STRING := "CLOCK0";
multiplier_aclr3 : STRING := "ACLR3";
port_addnsub1 : STRING := "PORT_CONNECTIVITY";
addnsub_multiplier_register1 : STRING := "CLOCK0";
addnsub_multiplier_aclr1 : STRING := "ACLR3";
addnsub_multiplier_pipeline_register1 : STRING := "CLOCK0";
addnsub_multiplier_pipeline_aclr1 : STRING := "ACLR3";
port_addnsub3 : STRING := "PORT_CONNECTIVITY";
addnsub_multiplier_register3 : STRING := "CLOCK0";
addnsub_multiplier_aclr3 : STRING := "ACLR3";
addnsub_multiplier_pipeline_register3 : STRING := "CLOCK0";
addnsub_multiplier_pipeline_aclr3 : STRING := "ACLR3";
adder1_rounding : STRING := "NO";
addnsub1_round_register : STRING := "CLOCK0";
addnsub1_round_aclr : STRING := "ACLR3";
addnsub1_round_pipeline_register : STRING := "CLOCK0";
addnsub1_round_pipeline_aclr : STRING := "ACLR3";
adder3_rounding : STRING := "NO";
addnsub3_round_register : STRING := "CLOCK0";
addnsub3_round_aclr : STRING := "ACLR3";
addnsub3_round_pipeline_register : STRING := "CLOCK0";
addnsub3_round_pipeline_aclr : STRING := "ACLR3";
multiplier01_rounding : STRING := "NO";
mult01_round_register : STRING := "CLOCK0";
mult01_round_aclr : STRING := "ACLR3";
multiplier23_rounding : STRING := "NO";
mult23_round_register : STRING := "CLOCK0";
mult23_round_aclr : STRING := "ACLR3";
width_msb : INTEGER := 17;
output_rounding : STRING := "NO";
output_round_type : STRING := "NEAREST_INTEGER";
output_round_register : STRING := "UNREGISTERED";
output_round_aclr : STRING := "NONE";
output_round_pipeline_register : STRING := "UNREGISTERED";
output_round_pipeline_aclr : STRING := "NONE";
chainout_rounding : STRING := "NO";
chainout_round_register : STRING := "UNREGISTERED";
chainout_round_aclr : STRING := "NONE";
chainout_round_pipeline_register : STRING := "UNREGISTERED";
chainout_round_pipeline_aclr : STRING := "NONE";
chainout_round_output_register : STRING := "UNREGISTERED";
chainout_round_output_aclr : STRING := "NONE";
multiplier01_saturation : STRING := "NO";
mult01_saturation_register : STRING := "CLOCK0";
mult01_saturation_aclr : STRING := "ACLR3";
multiplier23_saturation : STRING := "NO";
mult23_saturation_register : STRING := "CLOCK0";
mult23_saturation_aclr : STRING := "ACLR3";
port_mult0_is_saturated : STRING := "UNUSED";
port_mult1_is_saturated : STRING := "UNUSED";
port_mult2_is_saturated : STRING := "UNUSED";
port_mult3_is_saturated : STRING := "UNUSED";
width_saturate_sign : INTEGER := 1;
output_saturation : STRING := "NO";
port_output_is_overflow : STRING := "PORT_UNUSED";
output_saturate_type : STRING := "ASYMMETRIC";
output_saturate_register : STRING := "UNREGISTERED";
output_saturate_aclr : STRING := "NONE";
output_saturate_pipeline_register : STRING := "UNREGISTERED";
output_saturate_pipeline_aclr : STRING := "NONE";
chainout_saturation : STRING := "NO";
port_chainout_sat_is_overflow : STRING := "PORT_UNUSED";
chainout_saturate_register : STRING := "UNREGISTERED";
chainout_saturate_aclr : STRING := "NONE";
chainout_saturate_pipeline_register : STRING := "UNREGISTERED";
chainout_saturate_pipeline_aclr : STRING := "NONE";
chainout_saturate_output_register : STRING := "UNREGISTERED";
chainout_saturate_output_aclr : STRING := "NONE";
scanouta_register : STRING := "UNREGISTERED";
scanouta_aclr : STRING := "NONE";
width_chainin : INTEGER := 1;
chainout_adder : STRING := "NO";
chainout_register : STRING := "UNREGISTERED";
chainout_aclr : STRING := "ACLR3";
zero_chainout_output_register : STRING := "UNREGISTERED";
zero_chainout_output_aclr : STRING := "NONE";
shift_mode : STRING := "NO";
rotate_register : STRING := "UNREGISTERED";
rotate_aclr : STRING := "NONE";
rotate_pipeline_register : STRING := "UNREGISTERED";
rotate_pipeline_aclr : STRING := "NONE";
rotate_output_register : STRING := "UNREGISTERED";
rotate_output_aclr : STRING := "NONE";
shift_right_register : STRING := "UNREGISTERED";
shift_right_aclr : STRING := "NONE";
shift_right_pipeline_register : STRING := "UNREGISTERED";
shift_right_pipeline_aclr : STRING := "NONE";
shift_right_output_register : STRING := "UNREGISTERED";
shift_right_output_aclr : STRING := "NONE";
zero_loopback_register : STRING := "UNREGISTERED";
zero_loopback_aclr : STRING := "NONE";
zero_loopback_pipeline_register : STRING := "UNREGISTERED";
zero_loopback_pipeline_aclr : STRING := "NONE";
zero_loopback_output_register : STRING := "UNREGISTERED";
zero_loopback_output_aclr : STRING := "NONE";
accumulator : STRING := "NO";
accum_direction : STRING := "ADD";
loadconst_value : INTEGER := 0;
accum_sload_register : STRING := "UNREGISTERED";
accum_sload_aclr : STRING := "NONE";
accum_sload_pipeline_register : STRING := "UNREGISTERED";
accum_sload_pipeline_aclr : STRING := "NONE";
loadconst_control_register : STRING := "CLOCK0";
loadconst_control_aclr : STRING := "ACLR0";
systolic_delay1 : STRING := "UNREGISTERED";
systolic_delay3 : STRING := "UNREGISTERED";
systolic_aclr1 : STRING := "NONE";
systolic_aclr3 : STRING := "NONE";
preadder_mode : STRING := "SIMPLE";
preadder_direction_0 : STRING := "ADD";
preadder_direction_1 : STRING := "ADD";
preadder_direction_2 : STRING := "ADD";
preadder_direction_3 : STRING := "ADD";
width_coef : INTEGER := 1;
coefsel0_register : STRING := "CLOCK0";
coefsel0_aclr : STRING := "ACLR0";
coefsel1_register : STRING := "CLOCK0";
coefsel1_aclr : STRING := "ACLR0";
coefsel2_register : STRING := "CLOCK0";
coefsel2_aclr : STRING := "ACLR0";
coefsel3_register : STRING := "CLOCK0";
coefsel3_aclr : STRING := "ACLR0";
coef0_0 : INTEGER := 0;
coef0_1 : INTEGER := 0;
coef0_2 : INTEGER := 0;
coef0_3 : INTEGER := 0;
coef0_4 : INTEGER := 0;
coef0_5 : INTEGER := 0;
coef0_6 : INTEGER := 0;
coef0_7 : INTEGER := 0;
coef1_0 : INTEGER := 0;
coef1_1 : INTEGER := 0;
coef1_2 : INTEGER := 0;
coef1_3 : INTEGER := 0;
coef1_4 : INTEGER := 0;
coef1_5 : INTEGER := 0;
coef1_6 : INTEGER := 0;
coef1_7 : INTEGER := 0;
coef2_0 : INTEGER := 0;
coef2_1 : INTEGER := 0;
coef2_2 : INTEGER := 0;
coef2_3 : INTEGER := 0;
coef2_4 : INTEGER := 0;
coef2_5 : INTEGER := 0;
coef2_6 : INTEGER := 0;
coef2_7 : INTEGER := 0;
coef3_0 : INTEGER := 0;
coef3_1 : INTEGER := 0;
coef3_2 : INTEGER := 0;
coef3_3 : INTEGER := 0;
coef3_4 : INTEGER := 0;
coef3_5 : INTEGER := 0;
coef3_6 : INTEGER := 0;
coef3_7 : INTEGER := 0
);
PORT (
dataa : IN STD_LOGIC_VECTOR(width_a * number_of_multipliers - 1 downto 0);
datab : IN STD_LOGIC_VECTOR(width_b * number_of_multipliers - 1 downto 0);
datac : IN STD_LOGIC_VECTOR(width_c - 1 downto 0);
scanina : IN STD_LOGIC_VECTOR(width_a - 1 downto 0);
scaninb : IN STD_LOGIC_VECTOR(width_b - 1 downto 0);
sourcea : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0);
sourceb : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0);
clock3 : IN STD_LOGIC;
clock2 : IN STD_LOGIC;
clock1 : IN STD_LOGIC;
clock0 : IN STD_LOGIC;
aclr3 : IN STD_LOGIC;
aclr2 : IN STD_LOGIC;
aclr1 : IN STD_LOGIC;
aclr0 : IN STD_LOGIC;
ena3 : IN STD_LOGIC;
ena2 : IN STD_LOGIC;
ena1 : IN STD_LOGIC;
ena0 : IN STD_LOGIC;
signa : IN STD_LOGIC;
signb : IN STD_LOGIC;
addnsub1 : IN STD_LOGIC;
addnsub3 : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(width_result - 1 downto 0);
scanouta : OUT STD_LOGIC_VECTOR(width_a - 1 downto 0);
scanoutb : OUT STD_LOGIC_VECTOR(width_b - 1 downto 0);
mult01_round : IN STD_LOGIC;
mult23_round : IN STD_LOGIC;
mult01_saturation : IN STD_LOGIC;
mult23_saturation : IN STD_LOGIC;
addnsub1_round : IN STD_LOGIC;
addnsub3_round : IN STD_LOGIC;
mult0_is_saturated : OUT STD_LOGIC;
mult1_is_saturated : OUT STD_LOGIC;
mult2_is_saturated : OUT STD_LOGIC;
mult3_is_saturated : OUT STD_LOGIC;
output_round : IN STD_LOGIC;
chainout_round : IN STD_LOGIC;
output_saturate : IN STD_LOGIC;
chainout_saturate : IN STD_LOGIC;
overflow : OUT STD_LOGIC;
chainout_sat_overflow : OUT STD_LOGIC;
chainin : IN STD_LOGIC_VECTOR(width_chainin - 1 downto 0);
zero_chainout : IN STD_LOGIC;
rotate : IN STD_LOGIC;
shift_right : IN STD_LOGIC;
zero_loopback : IN STD_LOGIC;
accum_sload : IN STD_LOGIC;
coefsel0 : IN STD_LOGIC_VECTOR(2 downto 0);
coefsel1 : IN STD_LOGIC_VECTOR(2 downto 0);
coefsel2 : IN STD_LOGIC_VECTOR(2 downto 0);
coefsel3 : IN STD_LOGIC_VECTOR(2 downto 0)
);
end component;
end altera_lnsim_components;
| gpl-3.0 | b22478530a1a8e6180a706fb891d5425 | 0.51677 | 3.34859 | false | false | false | false |
shvorin/pcie-emu | hdllib/emu/emu_top128.vhd | 1 | 3,926 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
-- Toplevel module with empty interface used for emulation via GHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.util.all;
use work.tlp_package.all;
use work.tlp128;
entity emu_top128 is
end emu_top128;
architecture emu_top128 of emu_top128 is
constant period : time := 1 ns;
signal clk, reset : std_logic;
-- rx
signal rx_data : tlp128.data_t;
signal rx_dvalid : std_logic;
signal rx_sop, rx_eop, ej_ready : std_logic;
--
-- tx
signal tx_data : tlp128.data_t;
signal tx_dvalid : std_logic;
-- data representation for foreing calls
type foreign_tlp128_data_t is array (integer range 0 to 3) of integer;
function wrap(data : tlp128.data_t) return foreign_tlp128_data_t is
variable result : foreign_tlp128_data_t;
begin
for i in result'range loop
result(i) := conv_integer(data(32*(i+1) - 1 downto 32*i));
end loop;
return result;
end;
function unwrap(a : foreign_tlp128_data_t) return tlp128.data_t is
variable result : tlp128.data_t;
begin
for i in a'range loop
result(32*(i+1) - 1 downto 32*i) := conv_std_logic_vector(a(i), 32);
end loop;
return result;
end;
-- About linking with foreign functions see
-- http://ghdl.free.fr/ghdl/Restrictions-on-foreign-declarations.html
procedure line128_up(tx_dvalid : std_logic;
ej_ready : std_logic;
foreign_tx_data : foreign_tlp128_data_t)
is
begin
assert false severity failure;
end;
attribute foreign of line128_up : procedure is "VHPIDIRECT line128_up";
-- NB: corresponding C prototype is: void line128_down(struct scalar_params *, uint32_t arr[8])
procedure line128_down(
-- scalar parameters
rx_dvalid : out std_logic;
rx_sop, rx_eop : out std_logic;
ej_ready : out std_logic;
-- composite parameter(s)
foreign_rx_data : out foreign_tlp128_data_t)
is
begin
assert false severity failure;
end;
attribute foreign of line128_down : procedure is "VHPIDIRECT line128_down";
begin
cg : entity work.clock_gen
generic map (period)
port map (clk, reset);
app : tlp128.io
port map (
clk => clk,
reset => reset,
-- rx
rx_data => rx_data,
rx_dvalid => rx_dvalid,
rx_sop => rx_sop,
rx_eop => rx_eop,
-- tx
tx_data => tx_data,
tx_dvalid => tx_dvalid,
ej_ready => ej_ready);
data_down : process (clk, reset)
variable v_rx_dvalid, v_rx_sop, v_rx_eop, v_ej_ready : std_logic;
variable foreign_rx_data : foreign_tlp128_data_t;
begin
if reset = '1' then
rx_data <= (others => '0');
rx_dvalid <= '0';
rx_sop <= '0';
rx_eop <= '0';
ej_ready <= '0';
elsif rising_edge(clk) then
line128_down(v_rx_dvalid, v_rx_sop, v_rx_eop, v_ej_ready, foreign_rx_data);
rx_data <= unwrap(foreign_rx_data);
rx_dvalid <= v_rx_dvalid;
rx_sop <= v_rx_sop;
rx_eop <= v_rx_eop;
ej_ready <= v_ej_ready;
end if;
end process;
data_up : process (clk)
begin
if rising_edge(clk) then
-- NB: also looping back ej_ready
line128_up(tx_dvalid, ej_ready, wrap(tx_data));
end if;
end process;
end emu_top128;
| bsd-3-clause | 53f5159b34e322aa88cb3662ec03b08e | 0.549669 | 3.536937 | false | false | false | false |
alvieboy/xtc-base | alu_a.vhd | 1 | 4,245 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity alu is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
y: out unsigned(31 downto 0);
op: in alu_op_type;
en: in std_logic;
ci: in std_logic;
cen: in std_logic; -- Carry enable
busy: out std_logic;
valid: out std_logic;
co: out std_logic;
zero: out std_logic;
ovf: out std_logic;
sign: out std_logic
);
end entity;
architecture behave of alu is
signal alu_a, alu_b, alu_r: unsigned(32 downto 0);
signal alu_add_r, alu_sub_r: unsigned(32 downto 0);
signal carryext: unsigned (32 downto 0);
signal modify_flags: boolean;
component mult is
port (
clk: in std_logic;
rst: in std_logic;
lhs: in signed(31 downto 0);
rhs: in signed(31 downto 0);
en: in std_logic;
m: out signed(31 downto 0);
y: out signed(31 downto 0);
valid: out std_logic; -- Multiplication valid
comp: out std_logic -- Computing
);
end component;
component shifter is
port (
a: in unsigned(31 downto 0);
b: in unsigned(4 downto 0);
o: out unsigned(31 downto 0);
left: in std_logic;
arith:in std_logic
);
end component;
signal mult_en: std_logic;
signal mult_a: signed(31 downto 0);
signal mult_b: signed(31 downto 0);
signal mult_r: signed(31 downto 0);
signal mult_y: signed(31 downto 0);
signal mult_busy: std_logic;
signal mult_valid: std_logic;
signal shift_arith: std_logic;
signal shift_out: unsigned(31 downto 0);
signal shift_left: std_logic;
begin
mulen: if MULT_ENABLED generate
valid <= mult_valid;
multiplier: mult
port map (
clk => clk,
rst => rst,
lhs => mult_a,
rhs => mult_b,
en => mult_en,
m => mult_r,
y => mult_y,
valid => mult_valid,
comp => mult_busy
);
end generate;
muldis: if not MULT_ENABLED generate
mult_r <= (others => 'X');
mult_y <= (others => 'X');
mult_valid <= '0';
mult_busy <= '0';
end generate;
shifter_inst: shifter
port map (
a => alu_a(31 downto 0),
b => alu_b(4 downto 0),
o => shift_out,
left => shift_left,
arith => shift_arith
);
busy <= mult_busy;
alu_a <= '0' & a;
alu_b <= '0' & b;
mult_a <= signed(a);
mult_b <= signed(b);
carryext(32 downto 1) <= (others => '0');
carryext(0) <= ci when cen='1' else '0';--op=ALU_ADDC or op=ALU_SUBB else '0';
alu_add_r <= alu_a + alu_b + carryext;
alu_sub_r <= alu_a - alu_b - carryext;
mult_en <= '1' when op=ALU_MUL and en='1' else '0';
process(alu_add_r, carryext, alu_a, alu_b, alu_sub_r, op, mult_valid, mult_r,shift_out,mult_y)
begin
shift_left <= 'X';
shift_arith <= 'X';
case op is
when ALU_ADD => -- | ALU_ADDRI |ALU_ADDC =>
alu_r <= alu_add_r;
when ALU_SUB => --| ALU_CMP | ALU_SUBB =>
alu_r <= alu_sub_r;
when ALU_AND => alu_r <= alu_a and alu_b;
when ALU_OR => alu_r <= alu_a or alu_b;
--when ALU_NOT => alu_r <= not alu_a;
when ALU_XOR => alu_r <= alu_a xor alu_b;
when ALU_SEXTB => alu_r(7 downto 0) <= alu_a(7 downto 0);
alu_r(32 downto 8) <= (others => alu_a(7));
when ALU_SEXTS => alu_r(15 downto 0) <= alu_a(15 downto 0);
alu_r(32 downto 16) <= (others => alu_a(15));
when ALU_SHL =>
shift_arith<='X';
shift_left<='1';
alu_r <= 'X' & shift_out;
when ALU_SRA =>
shift_arith<='1';
shift_left<='0';
alu_r <= 'X' & shift_out;
when ALU_SRL =>
shift_arith<='0';
shift_left<='0';
alu_r <= 'X' & shift_out;
when ALU_MUL =>
alu_r <= mult_y(31) & unsigned(mult_r);
when others => alu_r <= (others =>'X');
end case;
-- if mult_valid='1' then
-- alu_r <= mult_y(31) & unsigned(mult_r);
-- end if;
end process;
y <= unsigned(mult_y);
o <= alu_r(31 downto 0);
co <= alu_sub_r(32);
sign <= alu_sub_r(31);
zero <= '1' when alu_sub_r(31 downto 0)=x"00000000" else '0';
end behave;
| bsd-3-clause | b94d00fdd1f4c93f165347d14d952ff3 | 0.552886 | 2.949965 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_reset.vhd | 1 | 4,603 | -------------------------------------------------------------------------------
--
-- The reset generation unit.
--
-- $Id: t400_reset.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_reset is
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
icyc_en_i : in boolean;
por_i : in boolean;
-- Reset Interface --------------------------------------------------------
reset_n_i : in std_logic;
res_o : out boolean
);
end t400_reset;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_reset is
type res_state_t is (IDLE,
RES1, RES2,
RES_ACTIVE);
signal res_state_q : res_state_t;
signal res_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process res_fsm
--
-- Purpose:
-- Implements the reset timing/controlling FSM.
-- User's Guide chapter 2.3 requires that reset_n_i has to be low for
-- at least 3 instruction cycle times until it initializes the CPU.
--
res_fsm: process (ck_i, por_i)
begin
if por_i then
res_state_q <= IDLE;
res_q <= false;
elsif ck_i'event and ck_i = '1' then
res_q <= false;
if icyc_en_i then
case res_state_q is
when IDLE =>
if reset_n_i = '0' then
res_state_q <= RES1;
end if;
when RES1 =>
if reset_n_i = '0' then
res_state_q <= RES2;
else
res_state_q <= IDLE;
end if;
when RES2 =>
if reset_n_i = '0' then
res_state_q <= RES_ACTIVE;
else
res_state_q <= IDLE;
end if;
when RES_ACTIVE =>
res_q <= true;
if reset_n_i = '1' then
res_state_q <= IDLE;
end if;
when others =>
res_state_q <= IDLE;
end case;
end if;
end if;
end process res_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
res_o <= res_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 3f4a13df29dff5f310b2f43214935c0a | 0.521834 | 4.557426 | false | false | false | false |
alvieboy/xtc-base | taint.vhd | 1 | 1,838 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity taint is
generic (
COUNT: integer := 16
);
port (
clk: in std_logic;
rst: in std_logic;
req1_en: in std_logic;
req1_r: in regaddress_type;
req2_en: in std_logic;
req2_r: in regaddress_type;
ready: out std_logic;
set_en: in std_logic;
set_r: in regaddress_type;
clr_en: in std_logic;
clr_r: in regaddress_type;
taint: out std_logic_vector(COUNT-1 downto 0)
);
end taint;
architecture behave of taint is
signal t: std_logic_vector(COUNT-1 downto 0);
signal req1_ok: std_logic;
signal req2_ok: std_logic;
begin
process(req1_en, req1_r, clr_en, clr_r)
variable idx: integer range 0 to COUNT-1;
begin
if req1_en='0' then
req1_ok<='1';
else
idx := to_integer(unsigned(req1_r));
if clr_en='1' and clr_r=req1_r then
req1_ok <= '1';
else
req1_ok <= t(idx);
end if;
end if;
end process;
process(req2_en, req2_r, clr_en, clr_r)
variable idx: integer range 0 to COUNT-1;
begin
if req2_en='0' then
req2_ok<='1';
else
idx := to_integer(unsigned(req2_r));
if clr_en='1' and clr_r=req2_r then
req2_ok <= '1';
else
req2_ok <= t(idx);
end if;
end if;
end process;
ready <= req1_ok and req2_ok;
process(clk)
variable idxs,idxc: integer range 0 to COUNT-1;
begin
if rising_edge(clk) then
if rst='1' then
t <= (others => '1');
else
idxs := to_integer(unsigned(set_r));
idxc := to_integer(unsigned(clr_r));
if set_en='1' then
t(idxs) <= '0';
end if;
if clr_en='1' then
t(idxc) <= '1';
end if;
end if;
end if;
end process;
end behave; | bsd-3-clause | fa984ee0e786228e3ff54e4a9fa0eb64 | 0.569641 | 2.858476 | false | false | false | false |
Nepta/fsm-generator | machine_etat_template.vhd | 1 | 803 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity #entity# is
port(
clk, resetn: in std_logic;
#inputs#
#outputs#
);
end entity;
architecture #architecture# of #entity# is
type state is (#states#);
signal current_state, next_state : state;
begin
evolution : process(current_state,#inputs_signals#) is
begin
next_state <= current_state;
case current_state is
#evol_states#
end case;
end process;
actions: process(current_state) is
begin
#default_outputs#
case current_state is
#actions#
when others => null;
end case;
end process;
synchronisation: process(clk, resetn) is
begin
if resetn = '0' then
current_state <= #initial_state#;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
end architecture;
| gpl-3.0 | d4ccff9d6d6ee3522d85a1f912a20fd7 | 0.703611 | 3.007491 | false | false | false | false |
Shadytel/Computer | Emulator/FPGA/InputController.vhd | 1 | 5,303 | ----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 21:31:08 09/24/2011
-- Design Name:
-- Module Name: InputController - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
library work;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InputController is
Port(
clk: in std_logic;
RAMwrite: out std_logic;
RAMread: out std_logic;
MicroCodeCLK: out std_logic;
MicroCodeEN: out std_logic;
Data: out std_logic_vector(11 downto 0);
Addr: out std_logic_vector(11 downto 0);
outNibble: out std_logic_vector(3 downto 0);
sw: in std_logic_vector(7 downto 0);
RAWbtn : in std_logic_vector(3 downto 0)
);
end InputController;
--Sw7 High= Run, Low=Step 1 microcode on btn0
--Sw6 High=AllowRun , Low=Edit
--Sw5 Nibble Select High= Upper, Low=Middle
--Sw4 Nibble Select High= other, Low=Lower
--Sw3:0 1 Nibble
--Btn 3: Stores Nibble
--Btn 2: Stores Word
--Btn 1: Increments memory counter
--Btn 0: Run 1 step
architecture Behavioral of InputController is
signal cnt : std_logic_vector(24 downto 0) := "0000000000000000000000000";
signal word: std_logic_vector(11 downto 0) := "000000000000";
signal loc: std_logic_vector(11 downto 0) := "000000000000";
signal btn: std_logic_vector(3 downto 0) := "0000";
signal step: std_logic :='0';
signal cooldown: std_logic :='0';
signal cooldown2: std_logic :='0';
signal cooldown3: std_logic :='0';
signal cooldown4: std_logic :='0';
alias running is sw(7);
--alias step is btn(0);
alias nibble is sw(3 downto 0);
component Debouncer
Port (
CLK : in STD_LOGIC;
x : in STD_LOGIC;
DBx : out STD_LOGIC
);
end component;
begin
db1: Debouncer
port map (
CLK => CLK, -- Clock
X => RAWbtn(0),
DBx => btn(0)
);
db2: Debouncer port map (
CLK => CLK, -- Clock
X => RAWbtn(1),
DBx => btn(1)
);
db3: Debouncer port map (
CLK => CLK, -- Clock
X => RAWbtn(2),
DBx => btn(2)
);
db4: Debouncer port map (
CLK => CLK, -- Clock
X => RAWbtn(3),
DBx => btn(3)
);
step <= btn(0);
-- process(cnt)
-- begin
-- if(cnt(24 downto 23) = "00") then
-- Data <= "ZZZZZZZZZZZZ";
-- Addr <= "ZZZZZZZZZZZZ";
-- RAMread <= 'Z';
-- RAMwrite <= 'Z';
-- MicroCodeCLK <= '1';
-- else
-- MicroCodeCLK <= '0';
-- end if;
-- end process;
--MicroCodeEN <= sw(6);
process (clk, sw, btn, loc, step, word, cooldown, nibble, running, cooldown2, cooldown3, cooldown4, cnt)
begin
if rising_edge(clk) then
if(sw(6) = '0') then
MicroCodeCLK <= '0';
MicroCodeEN <= '0';
if(btn(3) = '0' and cooldown4 = '0') then
if(sw(5 downto 4) = "00") then
word(3 downto 0) <= sw(3 downto 0);
outNibble <= sw(3 downto 0);
elsif(sw(5 downto 4) = "01") then
word(7 downto 4) <= sw(3 downto 0);
outNibble <= sw(3 downto 0);
elsif(sw(5 downto 4) = "11") then
word(11 downto 8) <= sw(3 downto 0);
outNibble <= sw(3 downto 0);
end if;
cooldown4 <= '1';
elsif(btn(3) = '1') then
cooldown4 <= '0';
end if;
if(btn(1) = '0' and cooldown2 = '0') then
loc <= loc + "000000000001";
cooldown2 <= '1';
elsif(btn(1) = '1') then
cooldown2 <= '0';
end if;
if(btn(0) = '1' and cooldown3 = '0') then
loc <= loc - "000000000001";
cooldown3 <= '1';
elsif(btn(0) = '0') then
cooldown3 <= '0';
end if;
Addr <= loc;
if(btn(2) = '1' and cooldown = '0') then
Data <= word;
RAMread <= '0';
RAMWrite <= '1';
cooldown <= '1';
elsif(btn(2) = '0') then
cooldown <= '0';
RAMWrite <= '0';
RAMread <= '1';
Data <= "ZZZZZZZZZZZZ";
end if;
--end if;
else
Data <= "ZZZZZZZZZZZZ";
Addr <= "ZZZZZZZZZZZZ";
RAMWrite <= 'Z';
RAMread <= 'Z';
MicroCodeEN <= '1';
-- if(btn(0) = '0' and cooldown3 = '0') then
-- MicroCodeCLK <= '1';
-- cooldown3 <= '1';
-- elsif(btn(0) = '1') then
-- cooldown3 <= '0';
-- end if;
if(sw(7) = '1') then
cnt <= cnt + "0000000000000000000000001";
if(cnt = "1111111111111111111111111") then
MicroCodeCLK <= '1';
end if;
else
if(btn(0) = '1' and cooldown3 = '0' ) then
MicroCodeCLK <= '1';
cooldown3 <= '1';
elsif(btn(0) = '0') then
cooldown3 <= '0';
end if;
end if;
end if;
end if;
if(clk = '0') then
MicroCodeCLK <= '0';
-- if(cooldown = '0') then
-- Data <= "ZZZZZZZZZZZZ";
-- end if;
end if;
end process;
end Behavioral;
| bsd-3-clause | b6a920948db0977da59d8c61e0f07e88 | 0.547049 | 2.941209 | false | false | false | false |
EPiCS/reconos | pcores/reconos_memif_memory_controller_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 14,772 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF Memory controller - Controller impl
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory controller connects the memory subsystem of
-- ReconOS to the memory bus of the system as an AXI
-- master.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
-- Memory controller parameters
C_MEMIF_FIFO_WIDTH : integer := 32;
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_USE_MMU_PORT : boolean := true;
-- Bus protocol parameters, do not add to or delete
C_MST_NATIVE_DATA_WIDTH : integer := 32;
C_LENGTH_WIDTH : integer := 12;
C_MST_AWIDTH : integer := 32
);
port (
-- Memory controller ports
MEMIF_FIFO_Hwt2Mem_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Hwt2Mem_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Empty : in std_logic;
MEMIF_FIFO_Hwt2Mem_RE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mem2Hwt_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Full : in std_logic;
MEMIF_FIFO_Mem2Hwt_WE : out std_logic;
CTRL_FIFO_Hwt_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Hwt_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Hwt_Empty : in std_logic;
CTRL_FIFO_Hwt_RE : out std_logic;
MEMIF_FIFO_Mmu_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : in std_logic;
MEMIF_FIFO_Mmu_WE : out std_logic;
CTRL_FIFO_Mmu_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : in std_logic;
CTRL_FIFO_Mmu_RE : out std_logic;
MEMCTRL_Clk : in std_logic;
MEMCTRL_Rst : in std_logic;
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
ip2bus_mstrd_req : out std_logic;
ip2bus_mstwr_req : out std_logic;
ip2bus_mst_addr : out std_logic_vector(C_MST_AWIDTH-1 downto 0);
ip2bus_mst_be : out std_logic_vector((C_MST_NATIVE_DATA_WIDTH/8)-1 downto 0);
ip2bus_mst_length : out std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
ip2bus_mst_type : out std_logic;
ip2bus_mst_lock : out std_logic;
ip2bus_mst_reset : out std_logic;
bus2ip_mst_cmdack : in std_logic;
bus2ip_mst_cmplt : in std_logic;
bus2ip_mst_error : in std_logic;
bus2ip_mst_rearbitrate : in std_logic;
bus2ip_mst_cmd_timeout : in std_logic;
bus2ip_mstrd_d : in std_logic_vector(C_MST_NATIVE_DATA_WIDTH-1 downto 0);
bus2ip_mstrd_rem : in std_logic_vector((C_MST_NATIVE_DATA_WIDTH)/8-1 downto 0);
bus2ip_mstrd_sof_n : in std_logic;
bus2ip_mstrd_eof_n : in std_logic;
bus2ip_mstrd_src_rdy_n : in std_logic;
bus2ip_mstrd_src_dsc_n : in std_logic;
ip2bus_mstrd_dst_rdy_n : out std_logic;
ip2bus_mstrd_dst_dsc_n : out std_logic;
ip2bus_mstwr_d : out std_logic_vector(C_MST_NATIVE_DATA_WIDTH-1 downto 0);
ip2bus_mstwr_rem : out std_logic_vector((C_MST_NATIVE_DATA_WIDTH)/8-1 downto 0);
ip2bus_mstwr_src_rdy_n : out std_logic;
ip2bus_mstwr_src_dsc_n : out std_logic;
ip2bus_mstwr_sof_n : out std_logic;
ip2bus_mstwr_eof_n : out std_logic;
bus2ip_mstwr_dst_rdy_n : in std_logic;
bus2ip_mstwr_dst_dsc_n : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of MEMCTRL_Clk : signal is "Clk";
attribute SIGIS of ip2bus_mst_reset : signal is "Rst";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
attribute SIGIS of MEMCTRL_Rst : signal is "Rst";
end entity user_logic;
architecture implementation of user_logic is
constant C_MEMIF_CMD_WIDTH : integer := C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH;
type STATE_TYPE is (WAIT_REQUEST,READ_CMD,READ_ADDR,WAIT_FILL,WAIT_REM,
PERF_WRITE_0,PERF_WRITE_1,PERF_WRITE_2,
PERF_READ_0,PERF_READ_1,PERF_READ_2,
WAIT_CMPLT);
signal state : STATE_TYPE;
signal port_select : std_logic;
signal count : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_fifo_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_fifo_empty : std_logic;
signal ctrl_fifo_re : std_logic;
signal memif_fifo_in_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
signal memif_fifo_in_fill : std_logic_vector(15 downto 0);
signal memif_fifo_in_empty : std_logic;
signal memif_fifo_in_re : std_logic;
signal memif_fifo_out_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
signal memif_fifo_out_rem : std_logic_vector(15 downto 0);
signal memif_fifo_out_full : std_logic;
signal memif_fifo_out_we : std_logic;
signal ctrl_cmd : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_length_fifo : std_logic_vector(15 downto 0);
signal axi_read_req : std_logic;
signal axi_write_req : std_logic;
signal axi_addr : std_logic_vector(31 downto 0);
signal axi_length : std_logic_vector(C_LENGTH_WIDTH - 1 downto 0);
signal axi_cmdack : std_logic;
signal axi_cmplt : std_logic;
signal axi_wr_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
signal axi_wr_sof : std_logic;
signal axi_wr_eof : std_logic;
signal axi_wr_src_rdy : std_logic;
signal axi_wr_dst_rdy : std_logic;
signal axi_wr_dst_dsc : std_logic;
signal axi_rd_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
signal axi_rd_sof : std_logic;
signal axi_rd_eof : std_logic;
signal axi_rd_src_rdy : std_logic;
signal axi_rd_src_dsc : std_logic;
signal axi_rd_dst_rdy : std_logic;
signal abort : std_logic;
signal clk : std_logic;
signal rst, rst_bus : std_logic;
begin
clk <= MEMCTRL_Clk;
rst <= MEMCTRL_Rst;
rst_bus <= not Bus2IP_Resetn;
-- drive constant bus signals
ip2bus_mstwr_src_dsc_n <= '1';
ip2bus_mstrd_dst_dsc_n <= '1';
ip2bus_mstwr_rem <= (others => '0');
ip2bus_mst_be <= (others => '1');
ip2bus_mst_type <= '1'; -- (always burst)
ip2bus_mst_lock <= '0';
ip2bus_mst_reset <= '0';
-- drive output ports and internal signals
ip2bus_mstrd_req <= axi_read_req;
ip2bus_mstwr_req <= axi_write_req;
ip2bus_mst_addr <= axi_addr;
ip2bus_mst_length <= axi_length;
axi_cmdack <= bus2ip_mst_cmdack;
axi_cmplt <= bus2ip_mst_cmplt;
ip2bus_mstwr_d <= axi_wr_data;
ip2bus_mstwr_sof_n <= not axi_wr_sof;
ip2bus_mstwr_eof_n <= not axi_wr_eof;
ip2bus_mstwr_src_rdy_n <= not axi_wr_src_rdy;
axi_wr_dst_rdy <= not bus2ip_mstwr_dst_rdy_n;
axi_wr_dst_dsc <= not bus2ip_mstwr_dst_dsc_n;
axi_rd_data <= bus2ip_mstrd_d;
axi_rd_sof <= not bus2ip_mstrd_sof_n;
axi_rd_eof <= not bus2ip_mstrd_eof_n;
axi_rd_src_rdy <= not bus2ip_mstrd_src_rdy_n;
axi_rd_src_dsc <= not bus2ip_mstrd_src_dsc_n;
ip2bus_mstrd_dst_rdy_n <= not axi_rd_dst_rdy;
ctrl_length_fifo <= ctrl_length(17 downto 2) - 1;
-- driving sof and eof dependent on count
axi_wr_sof <= '1' when or_reduce(count) = '0' else '0';
axi_wr_eof <= '1' when count = ctrl_length - 4 else '0';
-- multiplex port 1 (MMU) and port 2 (HWT)
port_mux_proc : process(port_select,
CTRL_FIFO_Mmu_Data,CTRL_FIFO_Hwt_Data,
CTRL_FIFO_Mmu_Empty,CTRL_FIFO_Hwt_Empty,
ctrl_fifo_re,memif_fifo_in_re,
memif_fifo_out_data,memif_fifo_out_we,
MEMIF_FIFO_Mmu_Rem,MEMIF_FIFO_Mmu_Full,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_Fill,MEMIF_FIFO_Hwt2Mem_Empty,
MEMIF_FIFO_Mem2Hwt_Rem,MEMIF_FIFO_Mem2Hwt_Full) is
begin
ctrl_fifo_data <= (others => '0');
ctrl_fifo_empty <= '1';
CTRL_FIFO_Mmu_RE <= '0';
CTRL_FIFO_Hwt_RE <= '0';
memif_fifo_in_data <= (others => '0');
memif_fifo_in_fill <= (others => '0');
memif_fifo_in_empty <= '0';
MEMIF_FIFO_Hwt2Mem_RE <= '0';
memif_fifo_out_rem <= (others => '0');
memif_fifo_out_full <= '0';
MEMIF_FIFO_Mem2Hwt_Data <= (others => '0');
MEMIF_FIFO_Mem2Hwt_WE <= '0';
MEMIF_FIFO_Mmu_Data <= (others => '0');
MEMIF_FIFO_Mmu_WE <= '0';
if port_select = '0' then
ctrl_fifo_data <= CTRL_FIFO_Mmu_Data;
ctrl_fifo_empty <= CTRL_FIFO_Mmu_Empty;
CTRL_FIFO_Mmu_RE <= ctrl_fifo_re;
memif_fifo_out_rem <= MEMIF_FIFO_Mmu_Rem;
memif_fifo_out_full <= MEMIF_FIFO_Mmu_Full;
MEMIF_FIFO_Mmu_Data <= memif_fifo_out_data;
MEMIF_FIFO_Mmu_WE <= memif_fifo_out_we;
else
ctrl_fifo_data <= CTRL_FIFO_Hwt_Data;
ctrl_fifo_empty <= CTRL_FIFO_Hwt_Empty;
CTRL_FIFO_Hwt_RE <= ctrl_fifo_re;
memif_fifo_out_rem <= MEMIF_FIFO_Mem2Hwt_Rem;
memif_fifo_out_full <= MEMIF_FIFO_Mem2Hwt_Full;
MEMIF_FIFO_Mem2Hwt_Data <= memif_fifo_out_data;
MEMIF_FIFO_Mem2Hwt_WE <= memif_fifo_out_we;
memif_fifo_in_data <= MEMIF_FIFO_Hwt2Mem_Data;
memif_fifo_in_fill <= MEMIF_FIFO_Hwt2Mem_Fill;
memif_fifo_in_empty <= MEMIF_FIFO_Hwt2Mem_Empty;
MEMIF_FIFO_Hwt2Mem_RE <= memif_fifo_in_re;
end if;
end process port_mux_proc;
-- drive in/out FIFO RE/WE signals
fifo_rd_proc : process(state,
axi_wr_dst_rdy,memif_fifo_in_data,
axi_rd_src_rdy,axi_rd_data) is
begin
memif_fifo_in_re <= '0';
axi_wr_data <= (others => '0');
memif_fifo_out_we <= '0';
memif_fifo_out_data <= (others => '0');
if state = PERF_WRITE_2 and abort = '0' then
memif_fifo_in_re <= axi_wr_dst_rdy;
axi_wr_data <= memif_fifo_in_data;
end if;
if state = PERF_READ_2 and abort = '0' then
memif_fifo_out_we <= axi_rd_src_rdy;
memif_fifo_out_data <= axi_rd_data;
end if;
end process fifo_rd_proc;
mem_proc : process(clk,rst_bus) is
begin
if rst_bus = '1' then
state <= WAIT_REQUEST;
axi_read_req <= '0';
axi_write_req <= '0';
axi_addr <= (others => '0');
axi_length <= (others => '0');
axi_wr_src_rdy <= '0';
axi_rd_dst_rdy <= '0';
ctrl_fifo_re <= '0';
port_select <= '1';
count <= (others => '0');
elsif rising_edge(clk) then
if rst = '1' then
abort <= '1';
end if;
case state is
when WAIT_REQUEST =>
if CTRL_FIFO_Mmu_Empty = '0' AND C_USE_MMU_PORT then
port_select <= '0';
ctrl_fifo_re <= '1';
state <= READ_CMD;
elsif CTRL_FIFO_Hwt_Empty = '0' then
port_select <= '1';
ctrl_fifo_re <= '1';
state <= READ_CMD;
end if;
if abort = '1' or rst = '1' then
ctrl_fifo_re <= '0';
state <= WAIT_REQUEST;
end if;
abort <= '0';
when READ_CMD =>
ctrl_cmd <= ctrl_fifo_data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= ctrl_fifo_data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
if abort = '1' or rst = '1' then
ctrl_fifo_re <= '0';
state <= WAIT_REQUEST;
end if;
when READ_ADDR =>
if ctrl_fifo_empty = '0' then
ctrl_addr <= ctrl_fifo_data;
ctrl_fifo_re <= '0';
if ctrl_cmd(C_MEMIF_CMD_WIDTH - 1) = '1' then
state <= WAIT_FILL;
else
state <= WAIT_REM;
end if;
end if;
if abort = '1' or rst = '1' then
ctrl_fifo_re <= '0';
state <= WAIT_REQUEST;
end if;
when WAIT_FILL =>
if memif_fifo_in_empty = '0' and memif_fifo_in_fill >= ctrl_length_fifo then
state <= PERF_WRITE_0;
end if;
if abort = '1' or rst = '1' then
state <= WAIT_REQUEST;
end if;
when WAIT_REM =>
if memif_fifo_out_full = '0' and memif_fifo_out_rem >= ctrl_length_fifo then
state <= PERF_READ_0;
end if;
if abort = '1' or rst = '1' then
ctrl_fifo_re <= '0';
state <= WAIT_REQUEST;
end if;
-- preparing for transfer
when PERF_WRITE_0 =>
axi_addr <= ctrl_addr;
axi_length <= ctrl_length(C_LENGTH_WIDTH - 1 downto 2) & "00";
axi_write_req <= '1';
count <= (others => '0');
state <= PERF_WRITE_1;
-- waiting for cmdack
when PERF_WRITE_1 =>
if axi_cmdack = '1' then
axi_write_req <= '0';
axi_wr_src_rdy <= '1';
state <= PERF_WRITE_2;
end if;
-- performing transfer
when PERF_WRITE_2 =>
if axi_wr_dst_rdy = '1' then
count <= count + 4;
if count = ctrl_length - 4 then
axi_wr_src_rdy <= '0';
state <= WAIT_CMPLT;
end if;
end if;
-- preparing for transfer
when PERF_READ_0 =>
axi_addr <= ctrl_addr;
axi_length <= ctrl_length(C_LENGTH_WIDTH - 1 downto 2) & "00";
axi_read_req <= '1';
count <= (others => '0');
state <= PERF_READ_1;
-- waiting for cmdack
when PERF_READ_1 =>
if axi_cmdack = '1' then
axi_read_req <= '0';
axi_rd_dst_rdy <= '1';
state <= PERF_READ_2;
end if;
when PERF_READ_2 =>
if axi_rd_src_rdy = '1' then
count <= count + 4;
if count = ctrl_length - 4 then
axi_rd_dst_rdy <= '0';
state <= WAIT_CMPLT;
end if;
end if;
-- waiting for completion
when WAIT_CMPLT =>
if axi_cmplt = '1' then
state <= WAIT_REQUEST;
end if;
end case;
end if;
end process mem_proc;
end implementation;
| gpl-2.0 | 5fe72290b384a838b1081a5ad53c43a3 | 0.5699 | 2.814596 | false | false | false | false |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_phy_alt_mem_phy_seq.vhd | 1 | 647,873 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr3_int_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr3_int_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr3_int_phy_alt_mem_phy_record_pkg;
--
package body ddr3_int_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr3_int_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr3_int_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
package ddr3_int_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
package body ddr3_int_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 8;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr3_int_phy_alt_mem_phy_iram_ram;
--
entity ddr3_int_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr3_int_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr3_int_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr3_int_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr3_int_phy_alt_mem_phy_admin;
--
use work.ddr3_int_phy_alt_mem_phy_mmi;
--
use work.ddr3_int_phy_alt_mem_phy_iram;
--
use work.ddr3_int_phy_alt_mem_phy_dgrb;
--
use work.ddr3_int_phy_alt_mem_phy_dgwb;
--
use work.ddr3_int_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr3_int_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr3_int_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr3_int_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr3_int_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr3_int_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr3_int_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr3_int_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-3.0 | a89dc7ce53668fb41bf8572b18ea6c4d | 0.441648 | 4.425543 | false | false | false | false |
freecores/t400 | rtl/vhdl/system/t410_notri.vhd | 1 | 8,733 | -------------------------------------------------------------------------------
--
-- T410/411 controller toplevel without tri-states.
--
-- $Id: t410_notri.vhd,v 1.4 2008-08-23 11:19:20 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t410_notri is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t410_notri;
use work.t400_core_comp_pack.t400_core;
use work.t400_tech_comp_pack.t400_por;
use work.t400_tech_comp_pack.generic_ram_ena;
architecture struct of t410_notri is
component t410_rom
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(8 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end component;
signal por_n_s : std_logic;
signal pm_addr_s : std_logic_vector(9 downto 0);
signal pm_data_s : std_logic_vector(7 downto 0);
signal dm_addr_s : std_logic_vector(5 downto 0);
signal dm_we_s : std_logic;
signal dm_data_to_core_s,
dm_data_from_core_s : std_logic_vector(3 downto 0);
signal gnd4_s : std_logic_vector(3 downto 0);
begin
gnd4_s <= (others => '0');
-----------------------------------------------------------------------------
-- T400 core
-----------------------------------------------------------------------------
core_b : t400_core
generic map (
opt_type_g => t400_opt_type_410_c,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => t400_opt_no_microbus_c,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
por_n_i => por_n_s,
reset_n_i => reset_n_i,
cko_i => cko_i,
pm_addr_o => pm_addr_s,
pm_data_i => pm_data_s,
dm_addr_o => dm_addr_s,
dm_we_o => dm_we_s,
dm_data_o => dm_data_from_core_s,
dm_data_i => dm_data_to_core_s,
io_l_i => io_l_i,
io_l_o => io_l_o,
io_l_en_o => io_l_en_o,
io_d_o => io_d_o,
io_d_en_o => io_d_en_o,
io_g_i => io_g_i,
io_g_o => io_g_o,
io_g_en_o => io_g_en_o,
io_in_i => gnd4_s,
si_i => si_i,
so_o => so_o,
so_en_o => so_en_o,
sk_o => sk_o,
sk_en_o => sk_en_o
);
-----------------------------------------------------------------------------
-- Program memory
-----------------------------------------------------------------------------
pmem_b : t410_rom
port map (
ck_i => ck_i,
addr_i => pm_addr_s(8 downto 0),
data_o => pm_data_s
);
-----------------------------------------------------------------------------
-- Data memory
-----------------------------------------------------------------------------
dmem_b : generic_ram_ena
generic map (
addr_width_g => 5,
data_width_g => 4
)
port map (
clk_i => ck_i,
a_i => dm_addr_s(4 downto 0),
we_i => dm_we_s,
ena_i => ck_en_i,
d_i => dm_data_from_core_s,
d_o => dm_data_to_core_s
);
-----------------------------------------------------------------------------
-- Power-on reset circuit
-----------------------------------------------------------------------------
por_b : t400_por
generic map (
delay_g => 4,
cnt_width_g => 2
)
port map (
clk_i => ck_i,
por_n_o => por_n_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2006/06/05 20:03:11 arniml
-- include generic_ram_ena
--
-- Revision 1.2 2006/05/08 02:36:38 arniml
-- hand-down clock divider option
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | eaf4c9896d78f63eda2ab3e0a624529b | 0.526623 | 3.005162 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiv_atoms.vhd | 1 | 365,662 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiv_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiv_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiv_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiv_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiv_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiv_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiv_pllpack;
package body cycloneiv_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiv_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiv_dffe : entity is TRUE;
end cycloneiv_dffe;
-- architecture body --
architecture behave of cycloneiv_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiv_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiv_mux21 : entity is TRUE;
end cycloneiv_mux21;
architecture AltVITAL of cycloneiv_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiv_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiv_mux41 : entity is TRUE;
end cycloneiv_mux41;
architecture AltVITAL of cycloneiv_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiv_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiv_atom_pack.all;
-- entity declaration --
entity cycloneiv_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiv_and1 : entity is TRUE;
end cycloneiv_and1;
-- architecture body --
architecture AltVITAL of cycloneiv_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiv_lcell_comb : entity is TRUE;
end cycloneiv_lcell_comb;
architecture vital_lcell_comb of cycloneiv_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_routing_wire
--
-- Description : Cyclone IV GX Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiv_routing_wire : entity is TRUE;
end cycloneiv_routing_wire;
ARCHITECTURE behave of cycloneiv_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_ff
--
-- Description : Cyclone IV GX FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
use work.cycloneiv_and1;
entity cycloneiv_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiv_ff : entity is TRUE;
end cycloneiv_ff;
architecture vital_lcell_ff of cycloneiv_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiv_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiv_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiv_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiv_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiv_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiv_ram_register;
ARCHITECTURE reg_arch OF cycloneiv_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiv_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiv_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiv_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiv_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiv_atom_pack.all;
USE work.cycloneiv_ram_register;
USE work.cycloneiv_ram_pulse_generator;
ENTITY cycloneiv_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiv_ram_block;
ARCHITECTURE block_arch OF cycloneiv_ram_block IS
COMPONENT cycloneiv_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiv_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiv_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiv_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiv_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiv_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiv_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiv_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiv_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiv_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiv_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiv_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiv_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiv_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiv_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiv_mac_data_reg;
ARCHITECTURE vital_cycloneiv_mac_data_reg OF cycloneiv_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiv_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiv_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiv_mac_sign_reg;
ARCHITECTURE cycloneiv_mac_sign_reg OF cycloneiv_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiv_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiv_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiv_mac_mult_internal;
ARCHITECTURE vital_cycloneiv_mac_mult_internal OF cycloneiv_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiv_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiv_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiv_atom_pack.all;
USE work.cycloneiv_mac_data_reg;
USE work.cycloneiv_mac_sign_reg;
USE work.cycloneiv_mac_mult_internal;
ENTITY cycloneiv_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiv_mac_mult;
ARCHITECTURE vital_cycloneiv_mac_mult OF cycloneiv_mac_mult IS
COMPONENT cycloneiv_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiv_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiv_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiv_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiv_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiv_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiv_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiv_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiv_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiv_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiv_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiv_mac_out;
ARCHITECTURE vital_cycloneiv_mac_out OF cycloneiv_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiv_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_io_ibuf
--
-- Description : Cyclone IV GX IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiv_io_ibuf;
ARCHITECTURE arch OF cycloneiv_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_io_obuf
--
-- Description : Cyclone IV GX IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiv_io_obuf;
ARCHITECTURE arch OF cycloneiv_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_ddio_oe
--
-- Description : Cyclone IV GX DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiv_ddio_oe;
ARCHITECTURE arch OF cycloneiv_ddio_oe IS
component cycloneiv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiv_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_latch
--
-- Description : Cyclone IV GX latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiv_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiv_latch : entity is TRUE;
end cycloneiv_latch;
architecture vital_latch of cycloneiv_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_negedge,
SetupLow => tsetup_d_ena_noedge_negedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiv_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiv_ddio_out
--
-- Description : Cyclone IV GX DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiv_ddio_out;
ARCHITECTURE arch OF cycloneiv_ddio_out IS
component cycloneiv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiv_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiv_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiv_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiv_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiv_io_pad
-- Description : Simulation model for cycloneiv IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiv_io_pad IS
GENERIC (
lpm_type : string := "cycloneiv_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiv_io_pad;
ARCHITECTURE arch OF cycloneiv_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiv_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiv_ena_reg : entity is TRUE;
end cycloneiv_ena_reg;
ARCHITECTURE behave of cycloneiv_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiv_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEIV_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
use work.cycloneiv_ena_reg;
entity cycloneiv_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiv_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiv_clkctrl : entity is TRUE;
end cycloneiv_clkctrl;
architecture vital_clkctrl of cycloneiv_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiv_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal outclk_tmp : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiv_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiv_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_tmp <= ena_out AND clkmux_out;
-- output path
process (inclk_ipd,outclk_tmp)
variable outclk_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLK",
OutTemp => outclk_tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkctrl;
----------------------------------------------------------------------------------
--Module Name: cycloneiv_pseudo_diff_out --
--Description: Simulation model for Cyclone IV GX Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
ENTITY cycloneiv_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiv_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiv_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--
--
-- CYCLONEIV_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
sim_init_config_is_application : string := "false";
sim_init_watchdog_enabled : string := "false";
operation_mode : string := "active_serial_remote";
lpm_type : string := "cycloneiv_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiv_rublock;
architecture architecture_rublock of cycloneiv_rublock is
begin
end architecture_rublock;
--------------------------------------------------------------------
--
-- Module Name : cycloneiv_termination
--
-- Description : Cyclone IV GX Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiv_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiv_termination;
ARCHITECTURE cycloneiv_termination_arch OF cycloneiv_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiv_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiv_jtag
--
-- Description : Cyclone IV GX JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_jtag is
generic (
lpm_type : string := "cycloneiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiv_jtag;
architecture architecture_jtag of cycloneiv_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiv_crcblock
--
-- Description : Cyclone IV GX CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiv_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiv_crcblock;
architecture architecture_crcblock of cycloneiv_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--
--
-- CYCLONEIV_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_oscillator is
generic
(
lpm_type: string := "cycloneiv_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
observableoutputport: out std_logic;
clkout : out std_logic
);
end cycloneiv_oscillator;
architecture architecture_oscillator of cycloneiv_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
--
--
-- CYCLONEIV_CONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiv_atom_pack.all;
entity cycloneiv_controller is
generic
(
lpm_type: string := "cycloneiv_controller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiv_controller;
architecture architecture_apfcontroller of cycloneiv_controller is
begin
end architecture_apfcontroller;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiv_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone IV GX PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiv_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiv_mn_cntr;
ARCHITECTURE behave of cycloneiv_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiv_post_divider
--
-- Description : Timing simulation model that models the icdrclk output.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiv_post_divider is
GENERIC ( dpa_divider : integer := 1
);
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic
);
END cycloneiv_post_divider;
ARCHITECTURE behave of cycloneiv_post_divider is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable modules : integer := 0;
variable init : boolean := true;
begin
if (init = true) then
if (dpa_divider = 0) then
modules := 1;
else
modules := dpa_divider;
end if;
init := false;
end if;
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modules) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiv_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone IV GX PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiv_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiv_scale_cntr;
ARCHITECTURE behave of cycloneiv_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--BEGIN MF PORTING DELETE
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiv_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiv_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiv_pll_reg;
ARCHITECTURE behave of cycloneiv_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--END MF PORTING DELETE
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiv_pll
--
-- Description : Timing simulation model for the Cyclone IV GX PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiv_atom_pack.all;
USE work.cycloneiv_pllpack.all;
USE work.cycloneiv_mn_cntr;
USE work.cycloneiv_scale_cntr;
USE work.cycloneiv_dffe;
USE work.cycloneiv_pll_reg;
ENTITY cycloneiv_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
feedback_source : integer := 0;
feedback_external_loop_divider : string := "false";
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 1;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiv_pll";
lpm_hint : string := "unused";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone IV GX";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fref : out std_logic;
icdrclk : out std_logic
);
END cycloneiv_pll;
ARCHITECTURE vital_pll of cycloneiv_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min * (vco_post_scale/2);
signal i_vco_max : integer := vco_max * (vco_post_scale/2);
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal icdr_clk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiv_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiv_post_divider
GENERIC ( dpa_divider : integer := 0
);
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiv_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiv_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiv_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiv_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiv_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
d1 : cycloneiv_post_divider
generic map ( dpa_divider => dpa_divider)
port map (
clk => inclk_m_from_vco,
reset => areset_ipd,
cout => icdr_clk);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiv_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiv_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiv_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiv_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiv_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable i_clk4_cntr : integer := 4;
variable i_clk3_cntr : integer := 3;
variable i_clk2_cntr : integer := 2;
variable i_clk1_cntr : integer := 1;
variable i_clk0_cntr : integer := 0;
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
variable clk_index : integer := 0;
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk0_cntr := extract_cntr_index(clk0_cntr);
i_clk1_cntr := extract_cntr_index(clk1_cntr);
i_clk2_cntr := extract_cntr_index(clk2_cntr);
i_clk3_cntr := extract_cntr_index(clk3_cntr);
i_clk4_cntr := extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
elsif ((dpa_multiply_by /= 0) and (dpa_divide_by /= 0)) then
i_n := dpa_divide_by;
i_m := dpa_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
if ((compensate_clock = "iqtxrxclk") and (m /= 0)) then
case feedback_source is
when 0 => clk_index := i_clk0_cntr;
when 1 => clk_index := i_clk1_cntr;
when 2 => clk_index := i_clk2_cntr;
when 3 => clk_index := i_clk3_cntr;
when 4 => clk_index := i_clk4_cntr;
when others =>
ASSERT FALSE
REPORT "Invalid feedback_source value (" & int2str(feedback_source) & ")!"
SEVERITY ERROR;
end case;
if(feedback_external_loop_divider = "true") then
m_val <= i_m * (i_c_high(clk_index) + i_c_low(clk_index)) * 2;
m_val_tmp := i_m * (i_c_high(clk_index) + i_c_low(clk_index)) * 2;
else
m_val <= i_m * (i_c_high(clk_index) + i_c_low(clk_index));
m_val_tmp := i_m * (i_c_high(clk_index) + i_c_low(clk_index));
end if;
else
m_val <= i_m;
m_val_tmp := i_m;
end if;
n_val <= i_n;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' ; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0' AFTER scanclk_period;
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= vco_max/2;
i_vco_min <= vco_min/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiv_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiv_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable time_resolution : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
if (lpm_hint = "time_resolution=100fs") then
time_resolution := 100 fs;
elsif (lpm_hint = "time_resolution=10fs") then
time_resolution := 10 fs;
elsif (lpm_hint = "time_resolution=fs") then
time_resolution := 1 fs;
else
time_resolution := 1 ps;
end if;
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/time_resolution) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/time_resolution) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/time_resolution + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/time_resolution) loop
total_pull_back := total_pull_back - refclk_period/time_resolution;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * time_resolution);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * time_resolution);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after time_resolution;
my_rem := (m_times_vco_period/time_resolution) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/time_resolution)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * time_resolution;
high_time := (tmp_vco_per/2) * time_resolution;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + time_resolution;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
fref <= refclk;
icdrclk <= icdr_clk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
| gpl-3.0 | 206c58ca2f4fa6004cb4d902a64a27b5 | 0.464093 | 4.167658 | false | false | false | false |
alvieboy/xtc-base | xtcpkg.vhd | 1 | 15,891 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
package xtcpkg is
constant INSTRUCTION_CACHE: boolean := true;
constant DATA_CACHE: boolean := true;
constant MMU_ENABLED: boolean := false;
constant MULT_ENABLED: boolean := true;
constant EXTRA_PIPELINE: boolean := false;
constant FETCHDATA_STAGE: boolean := true;
constant DEBUG_OPCODES: boolean := false;
constant DEBUG_MEMORY: boolean := false;
constant ENABLE_SHIFTER: boolean := true;
constant IO_REGISTER_INPUTS: boolean := true;
constant TRACECLOCK: boolean := false;
constant RESETADDRESS: unsigned(31 downto 0) := x"40000000";
-- Enable low-memory protection.
constant LOWPROTECTENABLE: boolean := false;
-- Enable bus/pipeline fault checks.
constant FAULTCHECKS: boolean := true;
-- Enable instruction/memory tracer.
constant TRACER_ENABLED: boolean := false;
subtype opcode_type is std_logic_vector(15 downto 0);
subtype dual_opcode_type is std_logic_vector(31 downto 0);
subtype word_type is unsigned(31 downto 0);
subtype word_type_std is std_logic_vector(31 downto 0);
subtype regaddress_type is std_logic_vector(4 downto 0); -- Includes supervisor bit
type alu_source_type is (
alu_source_reg,
alu_source_immed
);
type alu_op_type is (
ALU_ADD,
ALU_ADDC,
ALU_SUB,
ALU_SUBB,
ALU_AND,
ALU_OR,
ALU_XOR,
ALU_ADDRI,
ALU_CMP,
ALU_SRA,
ALU_SRL,
ALU_SHL,
ALU_NOT,
ALU_MUL,
ALU_SEXTB,
ALU_SEXTS
);
constant SR_Y: std_logic_vector(2 downto 0) := "001";
constant SR_CCSR: std_logic_vector(2 downto 0) := "011";
constant SR_INTPC: std_logic_vector(2 downto 0) := "100";
constant SR_INTM: std_logic_vector(2 downto 0) := "101";
type decoded_opcode_type is (
O_NOP,
O_IM,
O_LIMR,
O_ADDI,
O_ADDRI,
O_CMPI,
O_ALU,
O_ST,
O_LD,
-- Branch instructions
O_BR,
O_JMP,
O_JMPE,
O_SEXTB,
O_SEXTS,
-- COP
O_COPR,
O_COPW,
O_RSPR,
O_WSPR,
-- Regbank
O_RDUSR,
O_WRUSR,
-- Misc
O_SWI,
-- Errors
O_ABORT
);
type memory_access_type is (
M_WORD,
M_BYTE,
M_HWORD,
M_SPR,
M_WORD_POSTINC,
M_BYTE_POSTINC,
M_HWORD_POSTINC,
M_SPR_POSTINC
);
type loadimmtype is (
LOADNONE,
LOAD0,
LOAD8,
LOAD16,
LOAD24
);
type reg_source_type is (
reg_source_alu,
--reg_source_memory,
--reg_source_imm,
reg_source_spr,
reg_source_pcnext,
reg_source_cop
);
constant JUMP_RI_PCREL: std_logic_vector(1 downto 0) := "00";
constant JUMP_I_PCREL: std_logic_vector(1 downto 0) := "01";
constant JUMP_RI_ABS: std_logic_vector(1 downto 0) := "11";
type condition_type is (
CONDITION_UNCONDITIONAL,
CONDITION_NE,
CONDITION_E,
CONDITION_G,
CONDITION_GE,
CONDITION_L,
CONDITION_LE,
CONDITION_UG,
CONDITION_UGE,
CONDITION_UL,
CONDITION_ULE,
CONDITION_S,
CONDITION_NS
);
type opdec_type is record
modify_gpr: boolean; -- Modifies GPR
--modify_mem: boolean; -- Modifies memory (write)
modify_spr: boolean; -- Modifies (loads) SPR
alu_op: alu_op_type; -- ALU1 operation
opcode: opcode_type; -- The fetched opcode
--opcode_ext: boolean; -- Extended opcode
sreg1: regaddress_type; -- Source GPR
sreg2: regaddress_type; -- Source GPR
dreg: regaddress_type; -- Destination GPR
is_indirect: boolean; -- Indirect operation
modify_flags: boolean;
macc: memory_access_type; -- Memory access type
memory_access: std_logic; -- Bool for memory access (read or write)
memory_write: std_logic; -- Bool for write
rd1: std_logic; -- Read enable for GPR0
rd2: std_logic; -- Read enable for GPR1
reg_source: reg_source_type;
condition: condition_type;
enable_alu: std_logic;
imflag: std_logic;
blocks: std_logic;
ismult: std_logic;
extended: boolean;
alu_source: alu_source_type;
use_carry: std_logic;
-- IMMediate helpers
imm8l: std_logic_vector(7 downto 0);
imm8h: std_logic_vector(7 downto 0);
imm24: std_logic_vector(23 downto 0);
-- Special reg
sr: std_logic_vector(2 downto 0);
loadimm: loadimmtype;
op: decoded_opcode_type;
jump: std_logic_vector(1 downto 0);
--jump_clause: jumpcond_type;
is_jump: boolean;
except_return: boolean;
cop_en: std_logic;
cop_wr: std_logic;
cop_id: std_logic_vector(1 downto 0);
cop_reg: std_logic_vector(3 downto 0);
priv: std_logic;
targetzero: std_logic;
end record;
type fetchunit_state_type is ( running, jumping, aligning );
type fetch_regs_type is record
pc, fpc: word_type;
state: fetchunit_state_type;
unaligned: std_logic;
unaligned_jump: std_logic;
invert_readout: std_logic;
seq: std_logic;
priv: std_logic;
qopc: std_logic_vector(15 downto 0);
end record;
type fetch_output_type is record
r: fetch_regs_type;
opcode: dual_opcode_type;
valid: std_logic;
bothvalid:std_logic;
inverted: std_logic;
internalfault: std_logic;
npc: word_type;
end record;
type decode_regs_type is record
decoded: decoded_opcode_type;
valid: std_logic;
rd1, rd2: std_logic;
sra1, sra2: regaddress_type;
opcode: std_logic_vector(15 downto 0);
opcode_low: std_logic_vector(15 downto 0);
dual: boolean;
--dra: regaddress_type;
-- Target writeback registers
reg_source: reg_source_type;
regwe: std_logic;
dreg: regaddress_type;
targetzero: std_logic;
--reg_source1: reg_source_type;
--regwe1: std_logic;
--dreg1: regaddress_type;
sprwe: std_logic;
blocks: std_logic;
--blocks2: std_logic;
-- FLAGS and flags source
modify_flags: boolean;
--op: decoded_opcode_type;
alu_op: alu_op_type;
use_carry: std_logic;
enable_alu: std_logic;
--swap_target_reg:std_logic;
memory_write: std_logic;
memory_access: std_logic;
--la_offset: unsigned(31 downto 0);
macc: memory_access_type;
wb_is_data_address: std_logic; -- Writeback is data pointer, not alu result
npc: word_type;
fpc: word_type;
pc: word_type;
tpc: word_type; -- Trap PC. Might point to the IMM instruction
condition_clause: condition_type;
alu_source: alu_source_type;
ismult: std_logic;
-- IMMediate helpers
--imm12: std_logic_vector(11 downto 0);
--imm8: std_logic_vector(7 downto 0);
--imm4: std_logic_vector(3 downto 0);
is_jump: boolean;
jump: std_logic_vector(1 downto 0);
--jump_clause: jumpcond_type;
except_return: boolean;
--delay_slot: boolean;
--extended: boolean;
imreg: unsigned(31 downto 0);
imflag: std_logic;
opcode_q: std_logic_vector(15 downto 0);
sr: std_logic_vector(2 downto 0);
cop_en: std_logic;
cop_wr: std_logic;
cop_id: std_logic_vector(1 downto 0);
cop_reg: std_logic_vector(3 downto 0);
priv: std_logic;
-- synthesis translate_off
strasm: string(1 to 50);
-- synthesis translate_on
end record;
type decode_output_type is record
-- Fast-forward
rd1, rd2: std_logic;
sra1, sra2: regaddress_type;
r: decode_regs_type;
end record;
type fetchdata_regs_type is record
drq: decode_regs_type;
rd1q,rd2q: std_logic;
alu: std_logic;
waiting: std_logic;
alufwa: std_logic;
alufwb: std_logic;
hold: std_logic;
dreg: regaddress_type;
end record;
type fetchdata_output_type is record
r: fetchdata_regs_type;
rr1,rr2: word_type_std; -- Register data
valid: std_logic;
alufwa: std_logic;
alufwb: std_logic;
end record;
type execute_regs_type is record
valid: std_logic;
wb_is_data_address: std_logic;
-- Own
psr: unsigned(31 downto 0); -- Processor Status register
spsr: unsigned(31 downto 0); -- Saved Processor Status register
alur: unsigned(31 downto 0);
sr: std_logic_vector(2 downto 0);
dreg: regaddress_type;
regwe: std_logic;
reg_source: reg_source_type;
jump: std_logic;
jumppriv: std_logic;
jumpaddr: word_type;
--trapvector: word_type;
--trappc: word_type;
scratch: word_type;
y: word_type;
npc: word_type;
sprval: word_type;
trapq: std_logic;
innmi: std_logic;
delayslot: std_logic;
end record;
type execute_output_type is record
r: execute_regs_type;
-- Async stuff for writeback
reg_source: reg_source_type;
dreg: regaddress_type;
regwe: std_logic;
executed: boolean;
sr: std_logic_vector(2 downto 0);
alur: word_type;
imreg: word_type;
sprval: word_type;
sprwe: std_logic;
npc: word_type;
mwreg: regaddress_type; -- Memory writeback register
macc: memory_access_type;
data_write: std_logic_vector(31 downto 0);
data_address: std_logic_vector(31 downto 0);
data_access: std_logic;
data_writeenable: std_logic;
cop: std_logic_vector(31 downto 0);
jump: std_logic;
jumppriv: std_logic;
trap: std_logic;
flush: std_logic;
clrreg: std_logic;
clrhold: std_logic;
end record;
type memory_state_type is (
midle,
mbusy
);
type memory_regs_type is record
dreg: regaddress_type;
state: memory_state_type;
regwe: std_logic;
sprwe: std_logic;
macc: memory_access_type;
wb_dat: std_logic_vector(31 downto 0);
wb_adr: std_logic_vector(31 downto 0);
wb_we: std_logic;
wb_cyc: std_logic;
wb_stb: std_logic;
wb_tago: std_logic_vector(31 downto 0);
wb_sel: std_logic_vector(3 downto 0);
fault: std_logic;
pc: word_type;
faddr: std_logic_vector(31 downto 0);
nreq: unsigned(2 downto 0); -- Number of outstanding requests
end record;
type memory_output_type is record
r: memory_regs_type;
mdata: std_logic_vector(31 downto 0);
mreg: regaddress_type;
mregwe: std_logic;
msprwe: std_logic;
fault: std_logic;
internalfault: std_logic;
end record;
type execute_debug_type is record
opcode1: std_logic_vector(15 downto 0);
opcode2: std_logic_vector(15 downto 0);
pc: word_type;
dual: boolean;
valid: boolean;
executed: boolean;
lhs: word_type;
rhs: word_type;
trap: std_logic;
dbgen: std_logic;
hold: std_logic;
multvalid: std_logic;
end record;
type memory_debug_type is record
strobe: std_logic;
write: std_logic;
address: word_type;
pc: word_type;
data: word_type;
faddr: word_type;
end record memory_debug_type;
type tlb_entry_type is record
pagesize: std_logic_vector(1 downto 0);
ctx: std_logic_vector(0 downto 0);
paddr: std_logic_vector(31 downto 12);
vaddr: std_logic_vector(31 downto 12);
flags: std_logic_vector(3 downto 0);
end record;
type copi is record
reg: std_logic_vector(3 downto 0);
data: std_logic_vector(31 downto 0);
wr: std_logic;
en: std_logic;
end record;
type copo is record
data: std_logic_vector(31 downto 0);
valid: std_logic;
fault: std_logic;
end record;
type copo_a is array(0 to 3) of copo;
type copi_a is array(0 to 3) of copi;
type copifo is record
id: std_logic_vector(1 downto 0);
o: copi;
end record;
type copifi is record
i: copo;
end record;
constant DontCareValue: std_logic := 'X';
function opcode_txt_pad(strin: in string) return string;
function regname(r: in regaddress_type) return string;
subtype slot_id is std_logic_vector(15 downto 0);
type slot_wbi is array(0 to 15) of wb_miso_type;
type slot_wbo is array(0 to 15) of wb_mosi_type;
type slot_ids is array(0 to 15) of slot_id;
constant ACCESS_WB_WA: std_logic_vector(1 downto 0) := "00";
constant ACCESS_WT: std_logic_vector(1 downto 0) := "01";
constant ACCESS_WB_NA: std_logic_vector(1 downto 0) := "10";
constant ACCESS_NOCACHE: std_logic_vector(1 downto 0) := "11";
type dcache_in_type is record
data: std_logic_vector(31 downto 0);
address: std_logic_vector(31 downto 0);
tag: std_logic_vector(31 downto 0);
accesstype: std_logic_vector(1 downto 0);
strobe: std_logic;
we: std_logic;
wmask: std_logic_vector(3 downto 0);
enable: std_logic;
flush: std_logic;
end record;
type dcache_out_type is record
valid: std_logic;
data: std_logic_vector(31 downto 0);
tag: std_logic_vector(31 downto 0);
stall: std_logic;
in_flush: std_logic;
err: std_logic;
end record;
end xtcpkg;
package body xtcpkg is
function opcode_txt_pad(strin: in string) return string is
variable ret: string(1 to 25);
begin
for i in 1 to 25 loop
ret(i):=' ';
end loop;
ret(1 to strin'LENGTH):=strin;
return ret;
end function;
function regname(r: in regaddress_type) return string is
variable tmp: string(1 to 4);
begin
case r is
when "00000" => tmp := "UR0 ";
when "00001" => tmp := "UR1 ";
when "00010" => tmp := "UR2 ";
when "00011" => tmp := "UR3 ";
when "00100" => tmp := "UR4 ";
when "00101" => tmp := "UR5 ";
when "00110" => tmp := "UR6 ";
when "00111" => tmp := "UR7 ";
when "01000" => tmp := "UR8 ";
when "01001" => tmp := "UR9 ";
when "01010" => tmp := "UR10";
when "01011" => tmp := "UR11";
when "01100" => tmp := "UR12";
when "01101" => tmp := "UR13";
when "01110" => tmp := "UR14";
when "01111" => tmp := "UR15";
when "10000" => tmp := "SR0 ";
when "10001" => tmp := "SR1 ";
when "10010" => tmp := "SR2 ";
when "10011" => tmp := "SR3 ";
when "10100" => tmp := "SR4 ";
when "10101" => tmp := "SR5 ";
when "10110" => tmp := "SR6 ";
when "10111" => tmp := "SR7 ";
when "11000" => tmp := "SR8 ";
when "11001" => tmp := "SR9 ";
when "11010" => tmp := "SR10";
when "11011" => tmp := "SR11";
when "11100" => tmp := "SR12";
when "11101" => tmp := "SR13";
when "11110" => tmp := "SR14";
when "11111" => tmp := "SR15";
when others => tmp := "SR? ";
end case;
return tmp;
end function;
end;
| bsd-3-clause | 0eb3dd1d975c70bd5ace885e31d796eb | 0.562205 | 3.372453 | false | false | false | false |
keith-epidev/md2x | build/code/modn.vhdl | 1 | 1,061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_lib.all;
entity modn is
generic(
n:integer := 4
);
port (
clk : in std_logic;
inc: in std_logic;
enable: in std_logic;
reset: in std_logic;
overflow: out std_logic;
output : out std_logic_vector(f_log2(n)-1 downto 0)
);
end modn;
architecture arch of modn is
signal count: std_logic_vector(f_log2(n)-1 downto 0);
signal overflow_buffer: std_logic;
begin
output <= count;
overflow <= overflow_buffer;
counter:process(clk, inc) begin
if(clk'event and clk = '1')then
if(reset = '1') then
overflow_buffer <= '0';
count <= (others=>'0');
else
if(inc = '1') then
if(enable = '1') then
if(count < std_logic_vector(to_unsigned(n-1,count'length))) then
overflow_buffer <= '0';
count <= std_logic_vector(unsigned(count) + 1);
else
overflow_buffer <= '1';
count <= (others=>'0');
end if;
end if;
end if;
end if;
if(overflow_buffer = '1')then
overflow_buffer <= '0';
end if;
end if;
end process;
end arch;
| gpl-2.0 | 6c0208c57686493dd794ba98a56ae372 | 0.632422 | 2.659148 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_mnemonic_pack-p.vhd | 1 | 11,742 | -------------------------------------------------------------------------------
--
-- $Id: t400_mnemonic_pack-p.vhd,v 1.1 2008-05-01 19:52:37 arniml Exp $
--
-- Copyright (c) 2008, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
use work.t400_pack.byte_t;
package t400_mnemonic_pack is
-- Mnemonics ----------------------------------------------------------------
type mnemonic_t is (-- Arithmetic instructions
MN_ASC,
MN_ADD,
MN_ADT,
MN_AISC,
MN_CASC,
MN_CLRA,
MN_COMP,
MN_NOP,
MN_C,
MN_XOR,
-- Transfer of control instructions
MN_JID,
MN_JMP,
MN_JP_JSRP,
MN_JSR,
MN_RET,
MN_RETSK,
-- Memory reference instructions
MN_LD,
MN_LDD_XAD,
MN_LQID,
MN_RMB,
MN_SMB,
MN_STII,
MN_X,
MN_XDS,
MN_XIS,
-- Register reference instructions
MN_CAB,
MN_CBA,
MN_LBI,
MN_XABR,
-- Test instructions
MN_SKC,
MN_SKE,
MN_SKMBZ,
MN_SKT,
-- Input/output instructions
MN_EXT,
MN_XAS);
type mnemonic_rec_t is
record
mnemonic : mnemonic_t;
multi_byte : boolean;
end record;
function decode_opcode_f(opcode : in byte_t;
opt_type : in integer) return
mnemonic_rec_t;
end t400_mnemonic_pack;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.t400_opt_type_410_c;
package body t400_mnemonic_pack is
function decode_opcode_f(opcode : in byte_t;
opt_type : in integer) return
mnemonic_rec_t is
variable t41x_type_v : boolean;
variable mnemonic_v : mnemonic_t;
variable multi_byte_v : boolean;
variable result_v : mnemonic_rec_t;
begin
-- default assignment
mnemonic_v := MN_NOP;
multi_byte_v := false;
-- determine type
t41x_type_v := opt_type = t400_opt_type_410_c;
case opcode is
-- Mnemonic ASC----------------------------------------------------------
when "00110000" =>
mnemonic_v := MN_ASC;
-- Mnemonic ADD ---------------------------------------------------------
when "00110001" =>
mnemonic_v := MN_ADD;
-- Mnemonic ADT ---------------------------------------------------------
when "01001010" =>
if not t41x_type_v then
mnemonic_v := MN_ADT;
end if;
-- Mnemonic AISC --------------------------------------------------------
when "01010001" | "01010010" | "01010011" |
"01010100" | "01010101" | "01010110" | "01010111" |
"01011000" | "01011001" | "01011010" | "01011011" |
"01011100" | "01011101" | "01011110" | "01011111" =>
mnemonic_v := MN_AISC;
-- Mnemonic CASC --------------------------------------------------------
when "00010000" =>
if not t41x_type_v then
mnemonic_v := MN_CASC;
end if;
-- Mnemonic CLRA --------------------------------------------------------
when "00000000" =>
mnemonic_v := MN_CLRA;
-- Mnemonic COMP --------------------------------------------------------
when "01000000" =>
mnemonic_v := MN_COMP;
-- Mnemonic NOP ---------------------------------------------------------
when "01000100" =>
mnemonic_v := MN_NOP;
-- Mnemonic C -----------------------------------------------------------
when "00110010" | -- RC
"00100010" => -- SC
mnemonic_v := MN_C;
-- Mnemonic XOR ---------------------------------------------------------
when "00000010" =>
mnemonic_v := MN_XOR;
-- Mnemonic JID ---------------------------------------------------------
when "11111111" =>
mnemonic_v := MN_JID;
-- Mnemonic JMP ---------------------------------------------------------
when "01100000" | "01100001" | "01100010" | "01100011" =>
mnemonic_v := MN_JMP;
multi_byte_v := true;
-- Mnemonic JP_JSRP -----------------------------------------------------
when "10000000" | "10000001" | "10000010" | "10000011" |
"10000100" | "10000101" | "10000110" | "10000111" |
"10001000" | "10001001" | "10001010" | "10001011" |
"10001100" | "10001101" | "10001110" | "10001111" |
"10010000" | "10010001" | "10010010" | "10010011" |
"10010100" | "10010101" | "10010110" | "10010111" |
"10011000" | "10011001" | "10011010" | "10011011" |
"10011100" | "10011101" | "10011110" | "10011111" |
"10100000" | "10100001" | "10100010" | "10100011" |
"10100100" | "10100101" | "10100110" | "10100111" |
"10101000" | "10101001" | "10101010" | "10101011" |
"10101100" | "10101101" | "10101110" | "10101111" |
"10110000" | "10110001" | "10110010" | "10110011" |
"10110100" | "10110101" | "10110110" | "10110111" |
"10111000" | "10111001" | "10111010" | "10111011" |
"10111100" | "10111101" | "10111110" |
"11000000" | "11000001" | "11000010" | "11000011" |
"11000100" | "11000101" | "11000110" | "11000111" |
"11001000" | "11001001" | "11001010" | "11001011" |
"11001100" | "11001101" | "11001110" | "11001111" |
"11010000" | "11010001" | "11010010" | "11010011" |
"11010100" | "11010101" | "11010110" | "11010111" |
"11011000" | "11011001" | "11011010" | "11011011" |
"11011100" | "11011101" | "11011110" | "11011111" |
"11100000" | "11100001" | "11100010" | "11100011" |
"11100100" | "11100101" | "11100110" | "11100111" |
"11101000" | "11101001" | "11101010" | "11101011" |
"11101100" | "11101101" | "11101110" | "11101111" |
"11110000" | "11110001" | "11110010" | "11110011" |
"11110100" | "11110101" | "11110110" | "11110111" |
"11111000" | "11111001" | "11111010" | "11111011" |
"11111100" | "11111101" | "11111110" =>
mnemonic_v := MN_JP_JSRP;
-- Mnemonic JSR ---------------------------------------------------------
when "01101000" | "01101001" | "01101010" | "01101011" =>
mnemonic_v := MN_JSR;
multi_byte_v := true;
-- Mnemonic RET ---------------------------------------------------------
when "01001000" =>
mnemonic_v := MN_RET;
-- Mnemonic RETSK -------------------------------------------------------
when "01001001" =>
mnemonic_v := MN_RETSK;
-- Mnemonic LD ----------------------------------------------------------
when "00000101" | "00010101" | "00100101" | "00110101" =>
mnemonic_v := MN_LD;
-- Mnemonic LDD_XAD -----------------------------------------------------
when "00100011" =>
mnemonic_v := MN_LDD_XAD;
multi_byte_v := true;
-- Mnemonic LQID --------------------------------------------------------
when "10111111" =>
mnemonic_v := MN_LQID;
-- Mnemonic RMB ---------------------------------------------------------
when "01001100" | "01000101" | "01000010" | "01000011" =>
mnemonic_v := MN_RMB;
-- Mnemonic SMB ---------------------------------------------------------
when "01001101" | "01000111" | "01000110" | "01001011" =>
mnemonic_v := MN_SMB;
-- Mnemonic STII --------------------------------------------------------
when "01110000" | "01110001" | "01110010" | "01110011" |
"01110100" | "01110101" | "01110110" | "01110111" |
"01111000" | "01111001" | "01111010" | "01111011" |
"01111100" | "01111101" | "01111110" | "01111111" =>
mnemonic_v := MN_STII;
-- Mnemonic X -----------------------------------------------------------
when "00000110" | "00010110" | "00100110" | "00110110" =>
mnemonic_v := MN_X;
-- Mnemonic XDS ---------------------------------------------------------
when "00000111" | "00010111" | "00100111" | "00110111" =>
mnemonic_v := MN_XDS;
-- Mnemonic XIS ---------------------------------------------------------
when "00000100" | "00010100" | "00100100" | "00110100" =>
mnemonic_v := MN_XIS;
-- Mnemonic CAB ---------------------------------------------------------
when "01010000" =>
mnemonic_v := MN_CAB;
-- Mnemonic CBA ---------------------------------------------------------
when "01001110" =>
mnemonic_v := MN_CBA;
-- Mnemonic LBI ---------------------------------------------------------
when "00001000" | "00001001" | "00001010" | "00001011" |
"00001100" | "00001101" | "00001110" | "00001111" |
"00011000" | "00011001" | "00011010" | "00011011" |
"00011100" | "00011101" | "00011110" | "00011111" |
"00101000" | "00101001" | "00101010" | "00101011" |
"00101100" | "00101101" | "00101110" | "00101111" |
"00111000" | "00111001" | "00111010" | "00111011" |
"00111100" | "00111101" | "00111110" | "00111111" =>
mnemonic_v := MN_LBI;
-- Mnemonic XABR --------------------------------------------------------
when "00010010" =>
if not t41x_type_v then
mnemonic_v := MN_XABR;
end if;
-- Mnemonic SKC ---------------------------------------------------------
when "00100000" =>
mnemonic_v := MN_SKC;
-- Mnemonic SKE ---------------------------------------------------------
when "00100001" =>
mnemonic_v := MN_SKE;
-- Mnemonic SKMBZ -------------------------------------------------------
when "00000001" | "00010001" | "00000011" | "00010011" =>
mnemonic_v := MN_SKMBZ;
-- Mnemonic SKT ---------------------------------------------------------
when "01000001" =>
if not t41x_type_v then
mnemonic_v := MN_SKT;
end if;
-- Mnemonic XAS ---------------------------------------------------------
when "01001111" =>
mnemonic_v := MN_XAS;
-- Mnemonic EXT ---------------------------------------------------------
when "00110011" =>
mnemonic_v := MN_EXT;
multi_byte_v := true;
when others =>
null;
end case;
result_v.mnemonic := mnemonic_v;
result_v.multi_byte := multi_byte_v;
return result_v;
end;
end t400_mnemonic_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 1b3d7ea8e9f005ffc4a1ce5e260da999 | 0.370806 | 4.822177 | false | false | false | false |
AnttiLukats/opl3_fpga | fpga/modules/clks/ip/clk_gen/clk_gen_funcsim.vhdl | 2 | 7,651 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Sun Mar 8 22:11:52 2015
-- Host : edinburgh running 64-bit Ubuntu 14.10
-- Command : write_vhdl -force -mode funcsim
-- /media/sf_D_DRIVE/Users/Greg/git/opl3_fpga/fpga/modules/clks/ip/clk_gen/clk_gen_funcsim.vhdl
-- Design : clk_gen
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_gen_clk_gen_clk_wiz is
port (
clk125 : in STD_LOGIC;
clk : out STD_LOGIC;
clk_locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_gen_clk_gen_clk_wiz : entity is "clk_gen_clk_wiz";
end clk_gen_clk_gen_clk_wiz;
architecture STRUCTURE of clk_gen_clk_gen_clk_wiz is
signal clk125_clk_gen : STD_LOGIC;
signal clk_clk_gen : STD_LOGIC;
signal clkfbout_clk_gen : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk125,
O => clk125_clk_gen
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_clk_gen,
O => clk
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "HIGH",
CLKFBOUT_MULT_F => 53.375000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 8.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 87.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 6,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_clk_gen,
CLKFBOUT => clkfbout_clk_gen,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk125_clk_gen,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_clk_gen,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => clk_locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_gen is
port (
clk125 : in STD_LOGIC;
clk : out STD_LOGIC;
clk_locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_gen : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_gen : entity is "clk_gen,clk_wiz_v5_1,{component_name=clk_gen,use_phase_alignment=false,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_gen;
architecture STRUCTURE of clk_gen is
begin
inst: entity work.clk_gen_clk_gen_clk_wiz
port map (
clk => clk,
clk125 => clk125,
clk_locked => clk_locked
);
end STRUCTURE;
| lgpl-3.0 | a78e7405e2a0e037ce4b871df8396c32 | 0.623056 | 3.275257 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/hardcopyiv_hssi_components.vhd | 1 | 127,661 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package HARDCOPYIV_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function rx_top_basic_width (channel_width : integer) return integer;
function rx_top_num_of_basic (channel_width : integer) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function alpha_tolower (given_string : string) return string;
function hardcopyiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string;
function hardcopyiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer;
function hardcopyiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- hardcopyiv_hssi_clock_divider
--
COMPONENT hardcopyiv_hssi_clock_divider
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_refclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchdonein :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_clk0in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_vcobypassin : VitalDelayType01 := DefpropDelay01;
tipd_clk1in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchbaseclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdig : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(100 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "hardcopyiv_hssi_clock_divider";
channel_num : INTEGER := 0;
coreclk_out_gated_by_quad_reset : STRING := "false";
data_rate : INTEGER := 0;
divide_by : INTEGER := 4;
divider_type : STRING := "CHANNEL_REGULAR";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
enable_refclk_out : STRING := "false";
inclk_select : INTEGER := 0;
logical_channel_address : INTEGER := 0;
pre_divide_by : INTEGER := 1;
rate_switch_base_clk_in_select : INTEGER := 0;
rate_switch_done_in_select : INTEGER := 0;
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
refclkin_select : INTEGER := 0;
select_local_rate_switch_base_clock : STRING := "false";
select_local_rate_switch_done : STRING := "true"; -- shawn
select_local_refclk : STRING := "false";
select_refclk_dig : STRING := "false";
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0;
sim_refclkout_phase_shift : INTEGER := 0;
use_coreclk_out_post_divider : STRING := "false";
use_refclk_post_divider : STRING := "false";
use_vco_bypass : STRING := "false"
);
PORT (
clk0in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
clk1in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(100 - 1 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchbaseclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rateswitchdonein : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclkdig : IN STD_LOGIC := '0';
refclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
vcobypassin : IN STD_LOGIC := '0';
analogfastrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogfastrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkpulse : OUT STD_LOGIC;
analogrefclkpulseshifted : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(100 - 1 DOWNTO 0);
rateswitchbaseclock : OUT STD_LOGIC;
rateswitchdone : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
refclkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- hardcopyiv_hssi_pll
--
COMPONENT hardcopyiv_hssi_pll
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_earlyeios : VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk : VitalDelayType01 := DefpropDelay01;
tipd_pfdfbclk : VitalDelayType01 := DefpropDelay01;
tipd_powerdown : VitalDelayType01 := DefpropDelay01;
tipd_inclk :VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tpd_inclk_clk : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "hardcopyiv_hssi_pll";
auto_settings : STRING := "true";
bandwidth_type : STRING := "Auto";
base_data_rate : STRING := "unused";
channel_num : INTEGER := 0;
charge_pump_current_bits : INTEGER := 0;
charge_pump_mode_bits : INTEGER := 0;
charge_pump_test_enable : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
fast_lock_control : STRING := "false";
inclk0_input_period : INTEGER := 0;
inclk1_input_period : INTEGER := 0;
inclk2_input_period : INTEGER := 0;
inclk3_input_period : INTEGER := 0;
inclk4_input_period : INTEGER := 0;
inclk5_input_period : INTEGER := 0;
inclk6_input_period : INTEGER := 0;
inclk7_input_period : INTEGER := 0;
inclk8_input_period : INTEGER := 0;
inclk9_input_period : INTEGER := 0;
input_clock_frequency : STRING := "unused";
logical_channel_address : INTEGER := 0;
logical_tx_pll_number : INTEGER := 0;
loop_filter_c_bits : INTEGER := 0;
loop_filter_r_bits : INTEGER := 0;
m : INTEGER := 0;
n : INTEGER := 0;
pd_charge_pump_current_bits : INTEGER := 0;
pd_loop_filter_r_bits : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
pfd_fb_select : STRING := "internal";
pll_type : STRING := "Auto";
protocol_hint : STRING := "basic";
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
sim_is_negative_ppm_drift : STRING := "false";
sim_net_ppm_variation : INTEGER := 0;
test_charge_pump_current_down : STRING := "false";
test_charge_pump_current_up : STRING := "false";
use_refclk_pin : STRING := "false";
vco_data_rate : INTEGER := 0;
vco_divide_by : INTEGER := 0;
vco_range : STRING := "low";
vco_multiply_by : INTEGER := 0;
vco_post_scale : INTEGER := 0;
vco_tuning_bits : INTEGER := 0;
volt_reg_control_bits : INTEGER := 0;
volt_reg_output_bits : INTEGER := 0;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0;
PARAM_DELAY : INTEGER := 0
);
PORT (
areset : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
earlyeios : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 - 1 DOWNTO 0) := (others => '0');
inclk : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
locktorefclk : IN STD_LOGIC := '1';
pfdfbclk : IN STD_LOGIC := '0';
powerdown : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
clk : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locked : OUT STD_LOGIC;
pfdfbclkout : OUT STD_LOGIC;
pfdrefclkout : OUT STD_LOGIC;
vcobypassout : OUT STD_LOGIC
);
END COMPONENT;
--
-- hardcopyiv_hssi_tx_pma
--
COMPONENT hardcopyiv_hssi_tx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_datain :VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(20 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0inpulse : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_pclk : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_fastrefclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_refclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk4inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_rxdetecten : VitalDelayType01 := DefpropDelay01;
tipd_refclk1inpulse : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpmareset : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revserialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_refclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxpowerdown : VitalDelayType01 := DefpropDelay01;
tipd_refclk3inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdetectclk : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "hardcopyiv_hssi_tx_pma";
analog_power : STRING := "1.5V";
channel_number : INTEGER := 9999;
channel_type : STRING := "auto";
clkin_select : INTEGER := 0; -- 9999; out of bound in loading
clkmux_delay : STRING := "false";
common_mode : STRING := "0.6V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_reverse_serial_loopback : STRING := "false";
logical_channel_address : INTEGER := 0;
logical_protocol_hint_0 : STRING := "basic";
logical_protocol_hint_1 : STRING := "basic";
logical_protocol_hint_2 : STRING := "basic";
logical_protocol_hint_3 : STRING := "basic";
low_speed_test_select : INTEGER := 9999;
physical_clkin0_mapping : STRING := "x1";
physical_clkin1_mapping : STRING := "x4";
physical_clkin2_mapping : STRING := "xn_top";
physical_clkin3_mapping : STRING := "xn_bottom";
physical_clkin4_mapping : STRING := "hypertransport";
preemp_pretap : INTEGER := 0;
preemp_pretap_inv : STRING := "false";
preemp_tap_1 : INTEGER := 0;
preemp_tap_1_a : INTEGER := 0;
preemp_tap_1_b : INTEGER := 0;
preemp_tap_1_c : INTEGER := 0;
preemp_tap_2 : INTEGER := 0;
preemp_tap_2_inv : STRING := "false";
protocol_hint : STRING := "basic";
rx_detect : INTEGER := 9999;
serialization_factor : INTEGER := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_pclk : STRING := "false";
use_pma_direct : STRING := "false";
use_rx_detect : STRING := "false";
use_ser_double_data_mode : STRING := "false";
vod_selection : INTEGER := 0;
vod_selection_a : INTEGER := 0;
vod_selection_b : INTEGER := 0;
vod_selection_c : INTEGER := 0;
vod_selection_d : INTEGER := 0
);
PORT (
datain : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(20 - 1 DOWNTO 0) := (others => '0');
detectrxpowerdown : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(11 - 1 DOWNTO 0) := (others => '0');
fastrefclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN STD_LOGIC := '0';
pclk : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk0inpulse : IN STD_LOGIC := '0';
refclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk1inpulse : IN STD_LOGIC := '0';
refclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk2inpulse : IN STD_LOGIC := '0';
refclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk3inpulse : IN STD_LOGIC := '0';
refclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
refclk4inpulse : IN STD_LOGIC := '0';
revserialfdbk : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
txpmareset : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dftout : OUT STD_LOGIC_VECTOR(6 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- hardcopyiv_hssi_rx_pma
--
COMPONENT hardcopyiv_hssi_rx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_rxpmareset : VitalDelayType01 := DefpropDelay01;
tipd_plllocked : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_ignorephslck : VitalDelayType01 := DefpropDelay01;
tipd_locktoref : VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_adcestandby : VitalDelayType01 := DefpropDelay01;
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken : VitalDelayType01 := DefpropDelay01;
tipd_adcereset : VitalDelayType01 := DefpropDelay01;
tipd_deserclock :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_locktodata : VitalDelayType01 := DefpropDelay01;
tipd_freqlock : VitalDelayType01 := DefpropDelay01;
tipd_offsetcancellationen : VitalDelayType01 := DefpropDelay01;
tipd_testbussel :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoverdatain :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_seriallpbkin : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_adaptcapture : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "hardcopyiv_hssi_rx_pma";
adaptive_equalization_mode : STRING := "none";
allow_serial_loopback : STRING := "false";
allow_vco_bypass : INTEGER := 0;
analog_power : STRING := "1.4V";
channel_number : INTEGER := 0;
channel_type : STRING := "auto";
common_mode : STRING := "0.82V";
deserialization_factor : INTEGER := 8;
dfe_piclk_bandwidth : INTEGER := 0;
dfe_piclk_phase : INTEGER := 0;
dfe_piclk_sel : INTEGER := 0;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
eq_adapt_seq_control : INTEGER := 0;
eq_dc_gain : INTEGER := 0;
eq_max_gradient_control : INTEGER := 0;
eqa_ctrl : INTEGER := 0;
eqb_ctrl : INTEGER := 0;
eqc_ctrl : INTEGER := 0;
eqd_ctrl : INTEGER := 0;
eqv_ctrl : INTEGER := 0;
eyemon_bandwidth : INTEGER := 0;
force_signal_detect : STRING := "true";
ignore_lock_detect : STRING := "false";
logical_channel_address : INTEGER := 0;
low_speed_test_select : INTEGER := 0;
offset_cancellation : INTEGER := 0;
ppm_gen1_2_xcnt_en : INTEGER := 1;
ppm_post_eidle : INTEGER := 0;
ppmselect : INTEGER := 0;
protocol_hint : STRING := "basic";
send_direct_reverse_serial_loopback : STRING := "None";
signal_detect_hysteresis : INTEGER := 4;
signal_detect_hysteresis_valid_threshold : INTEGER := 2;
signal_detect_loss_threshold : INTEGER := 3;
termination : STRING := "OCT 100 Ohms";
use_deser_double_data_width : STRING := "false";
use_external_termination : STRING := "false";
use_pma_direct : STRING := "false";
PARAM_DELAY : INTEGER := 0
);
PORT (
adaptcapture : IN STD_LOGIC := '0';
adcepowerdn : IN STD_LOGIC := '0';
adcereset : IN STD_LOGIC := '0';
adcestandby : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
deserclock : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(38 - 1 DOWNTO 0) := (others => '0');
freqlock : IN STD_LOGIC := '0';
ignorephslck : IN STD_LOGIC := '0';
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
offsetcancellationen : IN STD_LOGIC := '0';
plllocked : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
recoverdatain : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rxpmareset : IN STD_LOGIC := '0';
seriallpbken : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
testbussel : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
adaptdone : OUT STD_LOGIC;
analogtestbus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dataoutfull : OUT STD_LOGIC_VECTOR(20 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
locktorefout : OUT STD_LOGIC;
ppmdetectclkrel : OUT STD_LOGIC;
recoverdataout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
revserialfdbkout : OUT STD_LOGIC;
signaldetect : OUT STD_LOGIC
);
END COMPONENT;
--
-- hardcopyiv_hssi_tx_pcs
--
COMPONENT hardcopyiv_hssi_tx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01;
tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_freezptr : VitalDelayType01 := DefpropDelay01;
tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01;
tipd_pipetxswing : VitalDelayType01 := DefpropDelay01;
tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "hardcopyiv_hssi_tx_pcs";
allow_polarity_inversion : STRING := "false";
auto_spd_self_switch_enable : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none"; -- none, x8, x4
channel_number : INTEGER := 0;
channel_width : INTEGER := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL=
datapath_protocol : STRING := "basic"; --replaced by protocol_hint
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none"; -- legacy, new, none
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6>
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_symbol_swap : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "true";
enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none";
ph_fifo_xn_mapping1 : STRING := "none";
ph_fifo_xn_mapping2 : STRING := "none";
ph_fifo_xn_select : INTEGER := 9999;
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL=
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "incremental";
use_double_data_mode : STRING := "false";
use_serializer_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "core_clk"; -- INT_CLK // int_clk
use_top_quad_as_mater : STRING := "true"; -- NEW_PARAM todo: select top/bottom to provide phfifo pointers
dprio_width : INTEGER := 150
);
PORT (
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0');
coreclk : IN STD_LOGIC := '0';
ctrlenable : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
datain : IN STD_LOGIC_VECTOR(39 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(43 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); --fix_width
forcedispcompliance : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
freezptr : IN STD_LOGIC := '0';
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
hiptxdeemph : IN STD_LOGIC := '0';
hiptxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
invpol : IN STD_LOGIC := '0';
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
localrefclk : IN STD_LOGIC := '0';
phfifobyteserdisable : IN STD_LOGIC := '0';
phfifoptrsreset : IN STD_LOGIC := '0';
phfiforddisable : IN STD_LOGIC := '0';
phfiforeset : IN STD_LOGIC := '0';
phfifowrenable : IN STD_LOGIC := '1';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifoxnbottombytesel : IN STD_LOGIC := '0';
phfifoxnbottomrdclk : IN STD_LOGIC := '0';
phfifoxnbottomrdenable : IN STD_LOGIC := '0';
phfifoxnbottomwrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxntopbytesel : IN STD_LOGIC := '0';
phfifoxntoprdclk : IN STD_LOGIC := '0';
phfifoxntoprdenable : IN STD_LOGIC := '0';
phfifoxntopwrenable : IN STD_LOGIC := '0';
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
pipestatetransdone : IN STD_LOGIC := '0';
pipetxdeemph : IN STD_LOGIC := '0'; --NEW; RTL=txdeemph;
pipetxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); --NEW; RTL=txmargin[2:0]
pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0'; --NEW, RTL=rate
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
xgmctrl : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hiptxclkout : OUT STD_LOGIC;
iqpphfifobyteselout : OUT STD_LOGIC;
iqpphfifordclkout : OUT STD_LOGIC;
iqpphfifordenableout : OUT STD_LOGIC;
iqpphfifowrenableout : OUT STD_LOGIC;
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifooverflow : OUT STD_LOGIC;
phfifordclkout : OUT STD_LOGIC;
phfiforddisableout : OUT STD_LOGIC;
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenableout : OUT STD_LOGIC;
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rateswitchout : OUT STD_LOGIC;
rdenablesync : OUT STD_LOGIC;
txdetectrx : OUT STD_LOGIC;
xgmctrlenable : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiv_hssi_rx_pcs
--
COMPONENT hardcopyiv_hssi_rx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_phfifox8bytesel : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_parallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidlerateswitch : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerstate :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_alignstatussync : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_hippowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk : VitalDelayType01 := DefpropDelay01;
tipd_enabyteord : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable : VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01;
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnptrsreset :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_signaldetected : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_autospdxnconfigsel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoveredclk : VitalDelayType01 := DefpropDelay01;
tipd_hiprateswitch : VitalDelayType01 := DefpropDelay01;
tipd_phfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_elecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_iqpautospdxnspgchg :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_rxfound :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_autospdxnspdchg :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "hardcopyiv_hssi_rx_pcs";
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- <true/false>;
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
auto_spd_self_switch_enable : STRING := "false";
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_double_data_mode_mask_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode
byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165
cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : INTEGER := 0;
cdrctrl_min_lock_to_ref_cycle : INTEGER := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none"; -- <none, x4, x8>;
channel_number : INTEGER := 0; -- <integer 0-3>;
channel_width : INTEGER := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
clk2_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
clk_pd_enable : STRING := "false"; --ww47_cram_p1
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic"; -- <basic/pipe/xaui> replaced by protocol_hint
dec_8b_10b_compatibility_mode : STRING := "true";
dec_8b_10b_mode : STRING := "none"; -- <normal/cascaded/none>;
dec_8b_10b_polarity_inv_enable : STRING := "false";
deskew_pattern : STRING := "1100111100"; -- K28.3
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_k_detect : STRING := "false";
elec_idle_num_com_detect : INTEGER := 0;
enable_bit_reversal : STRING := "false";
enable_deep_align : STRING := "false";
enable_deep_align_byte_swap : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_true_complement_match_in_word_align : STRING := "true";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : INTEGER := 0; -- <integer 0-3>;
insert_pad_on_underflow : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false"; -- b165
num_align_code_groups_in_ordered_set : INTEGER := 1; -- <integer 0-3>;
num_align_cons_good_data : INTEGER := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : INTEGER := 4; -- <Integer 1-256>;
num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num
ph_fifo_disable : STRING := "false";
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping1 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping2 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_select : INTEGER := 9999;
phystatus_delay : INTEGER := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_hip_enable : STRING := "false"; --NEW_PARAM todo: remove
pma_done_count : INTEGER := 53392; --ww47_cram_p1
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
rate_match_almost_empty_threshold : INTEGER := 11; -- <integer 0-15>;
rate_match_almost_full_threshold : INTEGER := 13; -- <integer 0-15>;
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : INTEGER := 13;
rate_match_empty_threshold : INTEGER := 5;
rate_match_fifo_mode : STRING := "false"; -- <normal/cascaded/generic/cascaded_generic/none> in s2gx, bool in s4gx;
rate_match_full_threshold : INTEGER := 20;
rate_match_insert_threshold : INTEGER := 11;
rate_match_ordered_set_based : STRING := "false"; -- <integer 10 or 20>;
rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern_size : INTEGER := 10; -- <integer 10 or 20>;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : INTEGER := 7;
rd_clk_mux_select : STRING := "int_clk"; -- <INT_CLK, CORE_CLK>;
recovered_clk_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
reset_clock_output_during_digital_reset : STRING := "false";
run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : INTEGER := 32;
rxstatus_error_report_mode : INTEGER := 0;
self_test_mode : STRING := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
test_bus_sel : INTEGER := 0;
use_alignment_state_machine : STRING := "false";
use_deserializer_double_data_mode : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
use_rising_edge_triggered_pattern_align : STRING := "false"; -- <true/false>; //83 para: new=23 rem=40
enable_phfifo_bypass : STRING := "false"
);
PORT (
a1a2size : IN STD_LOGIC := '0';
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
autospdxnconfigsel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- config_sel_centrl, quad_up, quad_down
autospdxnspdchg : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- From CMU.spped-change_centrl, rx3(up), rx0(down)
bitslip : IN STD_LOGIC := '0';
cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr
coreclk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); --NEW: updated width
digitalreset : IN STD_LOGIC := '0';
disablefifordin : IN STD_LOGIC := '0';
disablefifowrin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
fifordin : IN STD_LOGIC := '0';
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch
hiprateswitch : IN STD_LOGIC := '0'; -- hip_rate
invpol : IN STD_LOGIC := '0';
iqpautospdxnspgchg : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- speed_change_in_pipe_quad_up, down
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnptrsreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- reset_pc_ptrs_in_pipe_quad_up, down
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rd_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnwrclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rx_div2_sync_in_pipe_quad_up, down
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
phfifordenable : IN STD_LOGIC := '1';
phfiforeset : IN STD_LOGIC := '0';
phfifowrdisable : IN STD_LOGIC := '0';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifox8bytesel : IN STD_LOGIC := '0';
phfifox8rdenable : IN STD_LOGIC := '0';
phfifox8wrclk : IN STD_LOGIC := '0';
phfifox8wrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rx_we_in_centrl, quad_up, quad_down
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to both RX & TX.
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rd_enable_in_centrl, quad_up, quad_down
phfifoxnwrclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to RX.
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- wr_enable_in_centrl, quad_up, quad_down
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
rmfifordena : IN STD_LOGIC := '0';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '0';
rxdetectvalid : IN STD_LOGIC := '0';
rxelecidlerateswitch : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
signaldetected : IN STD_LOGIC := '0';
wareset : IN STD_LOGIC := '0'; -- new in 9.1
xauidelcondmet : IN STD_LOGIC := '0';
xauififoovr : IN STD_LOGIC := '0';
xauiinsertincomplete : IN STD_LOGIC := '0';
xauilatencycomp : IN STD_LOGIC := '0';
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins ---
a1a2sizeout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
adetectdeskew : OUT STD_LOGIC;
alignstatussyncout : OUT STD_LOGIC;
autospdrateswitchout : OUT STD_LOGIC;
autospdspdchgout : OUT STD_LOGIC; --ww47_out speed_chang_out_pipe
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD?
cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR.
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
ctrldetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- new in 6.1
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
disablefifordout : OUT STD_LOGIC;
disablefifowrout : OUT STD_LOGIC;
disperr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
errdetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
fifordout : OUT STD_LOGIC;
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0)
hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid
hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle
hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0)
iqpphfifobyteselout : OUT STD_LOGIC; --ww47_out rx_we_out_pipe
iqpphfifoptrsresetout : OUT STD_LOGIC; --ww47_out reset_pc_pters_out_pipe
iqpphfifordenableout : OUT STD_LOGIC; --ww47_out rd_enable_pipe_out
iqpphfifowrclkout : OUT STD_LOGIC; --ww47_out rx_div2_sync_out_pipe
iqpphfifowrenableout : OUT STD_LOGIC; --ww47_out wr_enable_out_pipe
k1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
k2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
patterndetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifobyteserdisableout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifooverflow : OUT STD_LOGIC;
phfifoptrsresetout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifounderflow : OUT STD_LOGIC;
phfifowrclkout : OUT STD_LOGIC;
phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifowrenableout : OUT STD_LOGIC;
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipephydonestatus : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
pipestatetransdoneout : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
rdalign : OUT STD_LOGIC;
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifoalmostempty : OUT STD_LOGIC;
rmfifoalmostfull : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
runningdisp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
signaldetect : OUT STD_LOGIC;
syncstatus : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
xauidelcondmetout : OUT STD_LOGIC;
xauififoovrout : OUT STD_LOGIC;
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END COMPONENT;
--
-- hardcopyiv_hssi_cmu
--
COMPONENT hardcopyiv_hssi_cmu
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanclk : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchdonein : VitalDelayType01 := DefpropDelay01;
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpllreset : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdividerdprioin : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_scanmode : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_cmuplldprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_txcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cmudividerdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01;
tipd_scanshift : VitalDelayType01 := DefpropDelay01;
tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01;
tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "hardcopyiv_hssi_cmu";
analog_test_bus_enable : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
bonded_quad_mode : STRING := "none";
bypass_bandgap : STRING := "false";
central_test_bus_select : INTEGER := 0;
cmu_type : STRING := "regular";
devaddr : INTEGER := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
migrated_from_prev_family : STRING := "false";
num_con_align_chars_for_align : INTEGER := 4;
num_con_errors_for_align_loss : INTEGER := 2;
num_con_good_data_for_align_approach : INTEGER := 3;
offset_all_errors_align : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pma_done_count : INTEGER := 0;
portaddr : INTEGER := 1;
rx0_auto_spd_self_switch_enable : STRING := "false";
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_phfifo_wait_cnt : INTEGER := 0;
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx_master_direction : STRING := "none";
rx_xaui_sm_backward_compatible_enable : STRING := "false";
test_mode : STRING := "false";
tx0_auto_spd_self_switch_enable : STRING := "false";
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_ph_fifo_reg_mode : STRING := "false";
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "int clock";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx_master_direction : STRING := "none";
tx_pll0_used_as_rx_cdr : STRING := "false";
tx_pll1_used_as_rx_cdr : STRING := "false";
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_deskew_fifo : STRING := "false";
vcceh_voltage : STRING := "3.0V";
vcceh_voltage_user_specified_auto : STRING := "true";
protocol_hint : STRING := "basic";
clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1";
cmu_divider0_inclk0_physical_mapping : STRING := "pll0";
cmu_divider0_inclk1_physical_mapping : STRING := "pll1";
cmu_divider0_inclk2_physical_mapping : STRING := "x4";
cmu_divider0_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider0_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider1_inclk0_physical_mapping : STRING := "pll0";
cmu_divider1_inclk1_physical_mapping : STRING := "pll1";
cmu_divider1_inclk2_physical_mapping : STRING := "x4";
cmu_divider1_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider1_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider2_inclk0_physical_mapping : STRING := "pll0";
cmu_divider2_inclk1_physical_mapping : STRING := "pll1";
cmu_divider2_inclk2_physical_mapping : STRING := "x4";
cmu_divider2_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider2_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider3_inclk0_physical_mapping : STRING := "pll0";
cmu_divider3_inclk1_physical_mapping : STRING := "pll1";
cmu_divider3_inclk2_physical_mapping : STRING := "x4";
cmu_divider3_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider3_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider4_inclk0_physical_mapping : STRING := "pll0";
cmu_divider4_inclk1_physical_mapping : STRING := "pll1";
cmu_divider4_inclk2_physical_mapping : STRING := "x4";
cmu_divider4_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider4_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider5_inclk0_physical_mapping : STRING := "pll0";
cmu_divider5_inclk1_physical_mapping : STRING := "pll1";
cmu_divider5_inclk2_physical_mapping : STRING := "x4";
cmu_divider5_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider5_inclk4_physical_mapping : STRING := "xn_b";
pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll0_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll0_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll0_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll0_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll0_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll0_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll1_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll1_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll1_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll1_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll1_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll1_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll2_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll2_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll2_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll2_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll2_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll2_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll3_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll3_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll3_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll3_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll3_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll3_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll4_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll4_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll4_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll4_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll4_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll4_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll5_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll5_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll5_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll5_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll5_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll5_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll0_logical_to_physical_mapping : INTEGER := 0;
pll1_logical_to_physical_mapping : INTEGER := 1;
pll2_logical_to_physical_mapping : INTEGER := 2;
pll3_logical_to_physical_mapping : INTEGER := 3;
pll4_logical_to_physical_mapping : INTEGER := 4;
pll5_logical_to_physical_mapping : INTEGER := 5;
refclk_divider0_logical_to_physical_mapping : INTEGER := 0;
refclk_divider1_logical_to_physical_mapping : INTEGER := 1;
rx0_logical_to_physical_mapping : INTEGER := 0;
rx1_logical_to_physical_mapping : INTEGER := 1;
rx2_logical_to_physical_mapping : INTEGER := 2;
rx3_logical_to_physical_mapping : INTEGER := 3;
rx4_logical_to_physical_mapping : INTEGER := 4;
rx5_logical_to_physical_mapping : INTEGER := 5;
tx0_logical_to_physical_mapping : INTEGER := 0;
tx1_logical_to_physical_mapping : INTEGER := 1;
tx2_logical_to_physical_mapping : INTEGER := 2;
tx3_logical_to_physical_mapping : INTEGER := 3;
tx4_logical_to_physical_mapping : INTEGER := 4;
tx5_logical_to_physical_mapping : INTEGER := 5;
tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps
sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs
);
PORT (
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (others => '0');
fixedclk : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
lccmurtestbussel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchdonein : IN STD_LOGIC := '0';
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rdenablesync : IN STD_LOGIC := '0';
recovclk : IN STD_LOGIC := '0';
refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
rxanalogreset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxclk : IN STD_LOGIC := '0';
rxcoreclk : IN STD_LOGIC := '0';
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0');
rxphfifordenable : IN STD_LOGIC := '0';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
rxpowerdown : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (others => '0');
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(9999 DOWNTO 0) := (others => '0');
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txpllreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
txpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
alignstatus : OUT STD_LOGIC;
autospdx4configsel : OUT STD_LOGIC;
autospdx4rateswitchout : OUT STD_LOGIC;
autospdx4spdchg : OUT STD_LOGIC;
clkdivpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpriodisableout : OUT STD_LOGIC;
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
extra10gout : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
lccmutestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
phfifiox4ptrsreset : OUT STD_LOGIC;
pllpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pllresetout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
quadresetout : OUT STD_LOGIC;
refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxadcepowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxadceresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcrupowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcruresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
testout : OUT STD_LOGIC_VECTOR(6999 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiv_hssi_calibration_block
--
COMPONENT hardcopyiv_hssi_calibration_block
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_clk : VitalDelayType01 := DefpropDelay01;
lpm_type : string := "hardcopyiv_hssi_calibration_block";
cont_cal_mode : string := "false";
enable_rx_cal_tw : string := "false";
enable_tx_cal_tw : string := "false";
migrated_from_prev_family : string := "false";
rtest : string := "false";
rx_cal_wt_value : integer := 0;
send_rx_cal_status : string := "true";
tx_cal_wt_value : integer := 1);
PORT (
clk : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
powerdn : IN std_logic := '0';
testctrl : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
nonusertocmu : OUT std_logic);
END COMPONENT;
--
-- hardcopyiv_hssi_refclk_divider
--
COMPONENT hardcopyiv_hssi_refclk_divider
GENERIC (
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
enable_divider : STRING := "false";
lpm_type : STRING := "hardcopyiv_hssi_refclk_divider";
refclk_coupling_termination : STRING := "dc_coupling_external_termination";
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
inclk : IN STD_LOGIC:= '0';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
end hardcopyiv_hssi_components;
package body HARDCOPYIV_HSSI_COMPONENTS is
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function rx_top_basic_width (channel_width : integer) return integer is
variable basic_width : integer;
begin
if (channel_width mod 10 = 0) then
basic_width := 10;
else
basic_width := 8;
end if;
return(basic_width);
end rx_top_basic_width;
function rx_top_num_of_basic (channel_width : integer) return integer is
variable num_of_basic : integer;
begin
if (channel_width mod 10 = 0) then
num_of_basic := channel_width/10;
else
num_of_basic := channel_width/8;
end if;
return(num_of_basic);
end rx_top_num_of_basic;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
function hardcopyiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is
begin
CASE ph_fifo_xn_select IS
WHEN 0 => RETURN ph_fifo_xn_mapping0;
WHEN 1 => RETURN ph_fifo_xn_mapping1;
WHEN 2 => RETURN ph_fifo_xn_mapping2;
WHEN OTHERS => RETURN "none";
END CASE;
end hardcopyiv_tx_pcs_mph_fifo_xn_mapping;
function hardcopyiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end hardcopyiv_tx_pcs_mphfifo_index;
function hardcopyiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end hardcopyiv_tx_pcs_miqp_phfifo_index;
end HARDCOPYIV_HSSI_COMPONENTS;
| gpl-3.0 | 2d900f732f97e09eb10dad59fa5297ee | 0.500035 | 4.28292 | false | false | false | false |
google/myelin-acorn-electron-hardware | emulated_keyboard/prototype_cpld/emulated_keyboard.vhd | 1 | 8,101 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- This is part of a converter project that allows using a PS/2 keyboard on a BBC Master.
-- It's inspired by a similar project by Prime on the Stardot forums, which uses an MT8816
-- crosspoint switch to provide a *very* hardware-accurate emulation. This project uses
-- a CPLD instead, with knowledge of how the keyboard encoder IC on the Master works, to
-- implement it with hardware I already happen to have at home :)
-- It shouldn't be too hard to adapt this to provide a keyboard interface for an Electron,
-- which connects the keyboard directly to the address bus, connects BREAK to /RST, and
-- has four ULA inputs for the keyboard rows, plus one for CAPS LOCK.
-- The BBC Micro works slightly differently, including the keyboard encoder logic
-- on the keyboard PCB itself, so that would require some more changes.
entity emulated_keyboard is
Port (
-- nKBEN: '0' means col_idx is the column being polled, '1' means free running mode
nkben : in std_logic;
-- column index, taken straight from PL7
col_idx : in std_logic_vector(3 downto 0);
-- column inputs from keyboard encoder IC
-- On the encoder, these are open collector outputs, so they
-- need pullups, or the CPLD will see random input.
--col_input : in std_logic_vector(12 downto 0);
-- row outputs to keyboard encoder IC; these are pulled up to
-- 5V on the BBC Master motherboard
row_output : inout std_logic_vector(7 downto 0);
-- BREAK output to system /RESET (pulled up to 5V).
break_output : inout std_logic;
-- SPI pins to talk to whatever's giving us keyboard information
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic := '0'
);
end emulated_keyboard;
architecture Behavioural of emulated_keyboard is
-- SPI buffer
signal spi_buf : std_logic_vector(17 downto 0) := (others => '0');
-- SPI bit counter
signal spi_count : std_logic_vector(4 downto 0) := (others => '0');
-- value to match on the column inputs
signal col_match_1 : std_logic_vector(3 downto 0) := "0011";
signal col_match_2 : std_logic_vector(3 downto 0) := (others => '1');
-- value to output on row outputs when a match occurs
signal row_value_1 : std_logic_vector(2 downto 0) := "100";
signal row_value_2 : std_logic_vector(2 downto 0) := (others => '1');
-- '1' when SHIFT is pressed
signal shift_pressed : std_logic := '0';
-- '1' when CTRL is pressed
signal ctrl_pressed : std_logic := '0';
-- '1' when BREAK is pressed
signal break_pressed : std_logic := '0';
-- '1' when the column input matches col_match_1 or col_match_2, respectively
signal match_1 : std_logic;
signal match_2 : std_logic;
-- '1' when at least one key is pressed
signal have_keypress : std_logic;
-- index of currently strobed column
--signal col_idx : std_logic_vector(3 downto 0);
begin
-- set col_idx to the index of the column currently pulled low by the keyboard encoder, plus one.
-- one column will be low at a time, so we can just use multi-input NAND for this.
-- when no column is being strobed, col_idx will equal "0000".
-- when column 0 is being strobed, it will be "0001". for column 12, "1101".
--col_idx(3) <=
-- not (col_input(12) and col_input(11) and col_input(10) and col_input(9) and col_input(8) and col_input(7));
--col_idx(2) <=
-- not (col_input(12) and col_input(11) and col_input(6) and col_input(5) and col_input(4) and col_input(3));
--col_idx(1) <=
-- not (col_input(10) and col_input(9) and col_input(6) and col_input(5) and col_input(2) and col_input(1));
--col_idx(0) <=
-- not (col_input(12) and col_input(10) and col_input(8) and col_input(6) and col_input(4) and col_input(2) and col_input(0));
-- have_keypress = '1' when at least one key is pressed (except shift/ctrl/break)
have_keypress <= '0' when (col_match_1 = "1111" and col_match_2 = "1111") else '1';
-- match_1 and match_2 are '1' when their associated column is strobed by the keyboard encoder
match_1 <= '1' when col_idx = col_match_1 else '0';
match_2 <= '1' when col_idx = col_match_2 else '0';
-- pull row outputs low when their columns are matched
row_output(0) <= '0' when
(nkben = '1' and have_keypress = '1')
or (nkben = '0' and (
(match_1 = '1' and row_value_1 = "000") or (match_2 = '1' and row_value_2 = "000")
)
) else 'Z';
row_output(1) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "001") or (match_2 = '1' and row_value_2 = "001")
) else 'Z';
row_output(2) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "010") or (match_2 = '1' and row_value_2 = "010")
) else 'Z';
row_output(3) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "011") or (match_2 = '1' and row_value_2 = "011")
) else 'Z';
row_output(4) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "100") or (match_2 = '1' and row_value_2 = "100")
) else 'Z';
row_output(5) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "101") or (match_2 = '1' and row_value_2 = "101")
) else 'Z';
row_output(6) <= '0' when nkben = '0' and (
(match_1 = '1' and row_value_1 = "110") or (match_2 = '1' and row_value_2 = "110")
) else 'Z';
-- shift and ctrl are special; they have diodes for anti-ghosting
row_output(7) <= '0' when (col_idx = "0001" and ctrl_pressed = '1')
or (col_idx = "0000" and shift_pressed = '1') else 'Z';
-- break is handled separately
break_output <= '0' when break_pressed = '1' else 'Z';
-- SPI interface:
-- - Idle with spi_sel high
-- - Bring spi_sel low to start transaction
-- - Clock in 24 bits on spi_miso (data read on rising edge)
-- - 4 column bits (index of column to match, for key 1)
-- - 1 unused bit
-- - 3 row bits (index of row to return, for key 1)
-- - 4 column bits (index of column to match, for key 2)
-- - 1 unused bit
-- - 3 row bits (index of row to return, for key 2)
-- - SHIFT state (1 = pressed)
-- - CTRL state (1 = pressed)
-- - BREAK state (1 = pressed)
-- - 5 unused bits
-- - Data is copied into registers on 24th rising edge on spi_clk
-- - Return spi_sel high to end transaction / reset for next time
process (spi_clk)
begin
spi_miso <= '0'; -- unused
if spi_sel = '1' then
spi_count <= "00000";
elsif rising_edge(spi_clk) then
spi_buf <= spi_buf(16 downto 0) & spi_mosi;
spi_count <= std_logic_vector(unsigned(spi_count) + 1);
-- copy when we get the 19th bit
if spi_count = "10010" then
col_match_1 <= spi_buf(17 downto 14);
row_value_1 <= spi_buf(12 downto 10);
col_match_2 <= spi_buf(9 downto 6);
row_value_2 <= spi_buf(4 downto 2);
shift_pressed <= spi_buf(1);
ctrl_pressed <= spi_buf(0);
break_pressed <= spi_mosi;
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 5057fe222a0930440b5fcab701ef0102 | 0.603135 | 3.386706 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiiils_components.vhd | 1 | 38,186 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiiils_atom_pack.all;
package cycloneiiils_components is
--
-- cycloneiiils_lcell_comb
--
COMPONENT cycloneiiils_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiiils_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_routing_wire
--
COMPONENT cycloneiiils_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_pll
--
COMPONENT cycloneiiils_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiiils_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
family_name : string := "Cyclone III LS";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_ff
--
COMPONENT cycloneiiils_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiiils_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_ram_block
--
COMPONENT cycloneiiils_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiiils_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiiils_mac_mult
--
COMPONENT cycloneiiils_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiiils_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiiils_mac_out
--
COMPONENT cycloneiiils_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiiils_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiiils_io_ibuf
--
COMPONENT cycloneiiils_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiiils_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- cycloneiiils_io_obuf
--
COMPONENT cycloneiiils_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiiils_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiiils_ddio_oe
--
COMPONENT cycloneiiils_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiiils_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiiils_ddio_out
--
COMPONENT cycloneiiils_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiiils_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiiils_pseudo_diff_out
--
COMPONENT cycloneiiils_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiiils_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiiils_io_pad
--
COMPONENT cycloneiiils_io_pad
GENERIC (
lpm_type : string := "cycloneiiils_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- cycloneiiils_clkctrl
--
COMPONENT cycloneiiils_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiiils_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_rublock
--
COMPONENT cycloneiiils_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiiils_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_controller
--
COMPONENT cycloneiiils_controller
generic (
lpm_type : string := "cycloneiiils_controller"
);
port (
nceout : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_termination
--
COMPONENT cycloneiiils_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiiils_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- cycloneiiils_jtag
--
COMPONENT cycloneiiils_jtag
generic (
lpm_type : string := "cycloneiiils_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneiiils_crcblock
--
COMPONENT cycloneiiils_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiiils_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
cyclecomplete : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiiils_oscillator
--
COMPONENT cycloneiiils_oscillator
generic
(
lpm_type: string := "cycloneiiils_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout1: out std_logic;
observableoutputport: out std_logic;
clkout : out std_logic
);
END COMPONENT;
end cycloneiiils_components;
| gpl-3.0 | 5c4fc1db42ff3cdf269cbc39b9729313 | 0.476143 | 4.317241 | false | false | false | false |
migueljiarr/RV32I | src/right_arith_XLEN_barrel_shifter.vhd | 1 | 1,366 | library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity right_arith_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end right_arith_XLEN_barrel_shifter;
architecture structural of right_arith_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= i(31) & i(31 downto 1);
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= i(31) & i(31) & s1(31 downto 2);
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= i(31) & i(31) & i(31) & i(31) & s2(31 downto 4);
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & s3(31 downto 8);
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & i(31) & s4(31 downto 16);
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
| mit | 318ddbd5a475ffe365420ec286132bb3 | 0.583455 | 2.335043 | false | false | false | false |
alvieboy/xtc-base | wishbonepkg.vhd | 1 | 1,479 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wishbonepkg is
constant CTI_CYCLE_CLASSIC: std_logic_vector(2 downto 0) := "000";
constant CTI_CYCLE_CONSTADDR: std_logic_vector(2 downto 0) := "001";
constant CTI_CYCLE_INCRADDR: std_logic_vector(2 downto 0) := "010";
constant CTI_CYCLE_ENDOFBURST: std_logic_vector(2 downto 0) := "111";
constant BTE_BURST_LINEAR: std_logic_vector(1 downto 0) := "00";
constant BTE_BURST_4BEATWRAP: std_logic_vector(1 downto 0) := "01";
constant BTE_BURST_8BEATWRAP: std_logic_vector(1 downto 0) := "10";
constant BTE_BURST_16BEATWRAP: std_logic_vector(1 downto 0) := "11";
type wb_miso_type is record
ack: std_logic;
dat: std_logic_vector(31 downto 0);
tag: std_logic_vector(31 downto 0);
int: std_logic;
err: std_logic;
rty: std_logic;
stall: std_logic;
end record;
type wb_mosi_type is record
dat: std_logic_vector(31 downto 0);
adr: std_logic_vector(31 downto 0);
tag: std_logic_vector(31 downto 0);
cyc: std_logic;
stb: std_logic;
sel: std_logic_vector(3 downto 0);
cti: std_logic_vector(2 downto 0);
bte: std_logic_vector(1 downto 0);
we: std_logic;
-- Not in wishbone standard
--bse: std_logic_vector(5 downto 0); -- Burst size extension
end record;
type wb_syscon_type is record
clk: std_logic;
rst: std_logic;
end record;
end wishbonepkg;
| bsd-3-clause | 5a38a545bbaecd2c423331633303a391 | 0.64503 | 3 | false | false | false | false |
freecores/t400 | syn/t421/xc3s1000/rom_t42x.vhd | 2 | 25,960 | -- This file was generated with hex2rom written by Daniel Wallner
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity rom_t42x is
port(
Clk : in std_logic;
A : in std_logic_vector(9 downto 0);
D : out std_logic_vector(7 downto 0)
);
end rom_t42x;
architecture rtl of rom_t42x is
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
case to_integer(unsigned(A)) is
when 000000 => D <= "01000100"; -- 0x0000
when 000001 => D <= "00110011"; -- 0x0001
when 000002 => D <= "01011001"; -- 0x0002
when 000003 => D <= "00110011"; -- 0x0003
when 000004 => D <= "01010110"; -- 0x0004
when 000005 => D <= "01111000"; -- 0x0005
when 000006 => D <= "00111100"; -- 0x0006
when 000007 => D <= "00110011"; -- 0x0007
when 000008 => D <= "00111110"; -- 0x0008
when 000009 => D <= "00000000"; -- 0x0009
when 000010 => D <= "00010010"; -- 0x000A
when 000011 => D <= "01010000"; -- 0x000B
when 000012 => D <= "00110011"; -- 0x000C
when 000013 => D <= "00111110"; -- 0x000D
when 000014 => D <= "00000000"; -- 0x000E
when 000015 => D <= "01010010"; -- 0x000F
when 000016 => D <= "01010000"; -- 0x0010
when 000017 => D <= "00110011"; -- 0x0011
when 000018 => D <= "00111110"; -- 0x0012
when 000019 => D <= "01110111"; -- 0x0013
when 000020 => D <= "00110011"; -- 0x0014
when 000021 => D <= "00111110"; -- 0x0015
when 000022 => D <= "01010000"; -- 0x0016
when 000023 => D <= "00110011"; -- 0x0017
when 000024 => D <= "00111010"; -- 0x0018
when 000025 => D <= "00000000"; -- 0x0019
when 000026 => D <= "01010000"; -- 0x001A
when 000027 => D <= "00110011"; -- 0x001B
when 000028 => D <= "00111010"; -- 0x001C
when 000029 => D <= "01001101"; -- 0x001D
when 000030 => D <= "00110011"; -- 0x001E
when 000031 => D <= "00111010"; -- 0x001F
when 000032 => D <= "01000111"; -- 0x0020
when 000033 => D <= "00110011"; -- 0x0021
when 000034 => D <= "00111010"; -- 0x0022
when 000035 => D <= "01001100"; -- 0x0023
when 000036 => D <= "01000011"; -- 0x0024
when 000037 => D <= "00000101"; -- 0x0025
when 000038 => D <= "01010000"; -- 0x0026
when 000039 => D <= "00110011"; -- 0x0027
when 000040 => D <= "00111010"; -- 0x0028
when 000041 => D <= "00010101"; -- 0x0029
when 000042 => D <= "00100011"; -- 0x002A
when 000043 => D <= "10000000"; -- 0x002B
when 000044 => D <= "01011111"; -- 0x002C
when 000045 => D <= "00100011"; -- 0x002D
when 000046 => D <= "00000000"; -- 0x002E
when 000047 => D <= "00000110"; -- 0x002F
when 000048 => D <= "00110011"; -- 0x0030
when 000049 => D <= "00111010"; -- 0x0031
when 000050 => D <= "00000101"; -- 0x0032
when 000051 => D <= "01001010"; -- 0x0033
when 000052 => D <= "00000111"; -- 0x0034
when 000053 => D <= "00000111"; -- 0x0035
when 000054 => D <= "00110011"; -- 0x0036
when 000055 => D <= "00111110"; -- 0x0037
when 000056 => D <= "01110101"; -- 0x0038
when 000057 => D <= "01001110"; -- 0x0039
when 000058 => D <= "01010011"; -- 0x003A
when 000059 => D <= "00000111"; -- 0x003B
when 000060 => D <= "00110011"; -- 0x003C
when 000061 => D <= "00111010"; -- 0x003D
when 000062 => D <= "00000111"; -- 0x003E
when 000063 => D <= "00100011"; -- 0x003F
when 000064 => D <= "00000000"; -- 0x0040
when 000065 => D <= "00110011"; -- 0x0041
when 000066 => D <= "00111110"; -- 0x0042
when 000067 => D <= "01010100"; -- 0x0043
when 000068 => D <= "00000110"; -- 0x0044
when 000069 => D <= "00110011"; -- 0x0045
when 000070 => D <= "00111010"; -- 0x0046
when 000071 => D <= "00000000"; -- 0x0047
when 000072 => D <= "01000000"; -- 0x0048
when 000073 => D <= "00000010"; -- 0x0049
when 000074 => D <= "00000100"; -- 0x004A
when 000075 => D <= "00100011"; -- 0x004B
when 000076 => D <= "00000000"; -- 0x004C
when 000077 => D <= "01011000"; -- 0x004D
when 000078 => D <= "00100011"; -- 0x004E
when 000079 => D <= "00000000"; -- 0x004F
when 000080 => D <= "00100001"; -- 0x0050
when 000081 => D <= "00110011"; -- 0x0051
when 000082 => D <= "10010010"; -- 0x0052
when 000083 => D <= "00110011"; -- 0x0053
when 000084 => D <= "00111110"; -- 0x0054
when 000085 => D <= "00100001"; -- 0x0055
when 000086 => D <= "00011111"; -- 0x0056
when 000087 => D <= "01000110"; -- 0x0057
when 000088 => D <= "00100001"; -- 0x0058
when 000089 => D <= "01000010"; -- 0x0059
when 000090 => D <= "00100001"; -- 0x005A
when 000091 => D <= "01001011"; -- 0x005B
when 000092 => D <= "00100001"; -- 0x005C
when 000093 => D <= "00100011"; -- 0x005D
when 000094 => D <= "00000000"; -- 0x005E
when 000095 => D <= "00110110"; -- 0x005F
when 000096 => D <= "00100011"; -- 0x0060
when 000097 => D <= "10010001"; -- 0x0061
when 000098 => D <= "00010100"; -- 0x0062
when 000099 => D <= "00110011"; -- 0x0063
when 000100 => D <= "00101010"; -- 0x0064
when 000101 => D <= "00000110"; -- 0x0065
when 000102 => D <= "00000000"; -- 0x0066
when 000103 => D <= "00110000"; -- 0x0067
when 000104 => D <= "00100010"; -- 0x0068
when 000105 => D <= "00100000"; -- 0x0069
when 000106 => D <= "00100011"; -- 0x006A
when 000107 => D <= "00000000"; -- 0x006B
when 000108 => D <= "00000110"; -- 0x006C
when 000109 => D <= "00110011"; -- 0x006D
when 000110 => D <= "00111010"; -- 0x006E
when 000111 => D <= "00000000"; -- 0x006F
when 000112 => D <= "00110000"; -- 0x0070
when 000113 => D <= "00000110"; -- 0x0071
when 000114 => D <= "00110011"; -- 0x0072
when 000115 => D <= "00111010"; -- 0x0073
when 000116 => D <= "00110011"; -- 0x0074
when 000117 => D <= "00111100"; -- 0x0075
when 000118 => D <= "00000111"; -- 0x0076
when 000119 => D <= "00110011"; -- 0x0077
when 000120 => D <= "00101100"; -- 0x0078
when 000121 => D <= "00110011"; -- 0x0079
when 000122 => D <= "00111010"; -- 0x007A
when 000123 => D <= "00100101"; -- 0x007B
when 000124 => D <= "00110011"; -- 0x007C
when 000125 => D <= "00111010"; -- 0x007D
when 000126 => D <= "00110101"; -- 0x007E
when 000127 => D <= "00110011"; -- 0x007F
when 000128 => D <= "00111010"; -- 0x0080
when 000129 => D <= "00110001"; -- 0x0081
when 000130 => D <= "00000110"; -- 0x0082
when 000131 => D <= "00100010"; -- 0x0083
when 000132 => D <= "00100011"; -- 0x0084
when 000133 => D <= "00000000"; -- 0x0085
when 000134 => D <= "00010000"; -- 0x0086
when 000135 => D <= "00100000"; -- 0x0087
when 000136 => D <= "00000110"; -- 0x0088
when 000137 => D <= "00110011"; -- 0x0089
when 000138 => D <= "00111010"; -- 0x008A
when 000139 => D <= "00000000"; -- 0x008B
when 000140 => D <= "01010011"; -- 0x008C
when 000141 => D <= "00000110"; -- 0x008D
when 000142 => D <= "00100010"; -- 0x008E
when 000143 => D <= "00100000"; -- 0x008F
when 000144 => D <= "00000110"; -- 0x0090
when 000145 => D <= "00110011"; -- 0x0091
when 000146 => D <= "00111010"; -- 0x0092
when 000147 => D <= "00110010"; -- 0x0093
when 000148 => D <= "00100000"; -- 0x0094
when 000149 => D <= "00000110"; -- 0x0095
when 000150 => D <= "00110011"; -- 0x0096
when 000151 => D <= "00111010"; -- 0x0097
when 000152 => D <= "00001111"; -- 0x0098
when 000153 => D <= "00011110"; -- 0x0099
when 000154 => D <= "00110011"; -- 0x009A
when 000155 => D <= "10100111"; -- 0x009B
when 000156 => D <= "00110011"; -- 0x009C
when 000157 => D <= "00111010"; -- 0x009D
when 000158 => D <= "00110011"; -- 0x009E
when 000159 => D <= "00101100"; -- 0x009F
when 000160 => D <= "00110011"; -- 0x00A0
when 000161 => D <= "00111010"; -- 0x00A1
when 000162 => D <= "00000110"; -- 0x00A2
when 000163 => D <= "00110011"; -- 0x00A3
when 000164 => D <= "00111010"; -- 0x00A4
when 000165 => D <= "00110011"; -- 0x00A5
when 000166 => D <= "01100001"; -- 0x00A6
when 000167 => D <= "01001111"; -- 0x00A7
when 000168 => D <= "00000000"; -- 0x00A8
when 000169 => D <= "01010111"; -- 0x00A9
when 000170 => D <= "00110011"; -- 0x00AA
when 000171 => D <= "00000001"; -- 0x00AB
when 000172 => D <= "00000110"; -- 0x00AC
when 000173 => D <= "00110011"; -- 0x00AD
when 000174 => D <= "00111010"; -- 0x00AE
when 000175 => D <= "00110011"; -- 0x00AF
when 000176 => D <= "00010001"; -- 0x00B0
when 000177 => D <= "00000110"; -- 0x00B1
when 000178 => D <= "00110011"; -- 0x00B2
when 000179 => D <= "00111010"; -- 0x00B3
when 000180 => D <= "00110011"; -- 0x00B4
when 000181 => D <= "00000011"; -- 0x00B5
when 000182 => D <= "00000110"; -- 0x00B6
when 000183 => D <= "00110011"; -- 0x00B7
when 000184 => D <= "00111010"; -- 0x00B8
when 000185 => D <= "00110011"; -- 0x00B9
when 000186 => D <= "00010011"; -- 0x00BA
when 000187 => D <= "00000110"; -- 0x00BB
when 000188 => D <= "00110011"; -- 0x00BC
when 000189 => D <= "00111010"; -- 0x00BD
when 000190 => D <= "00110011"; -- 0x00BE
when 000191 => D <= "00100001"; -- 0x00BF
when 000192 => D <= "00000110"; -- 0x00C0
when 000193 => D <= "00110011"; -- 0x00C1
when 000194 => D <= "00111010"; -- 0x00C2
when 000195 => D <= "00110011"; -- 0x00C3
when 000196 => D <= "01010000"; -- 0x00C4
when 000197 => D <= "00110011"; -- 0x00C5
when 000198 => D <= "00100001"; -- 0x00C6
when 000199 => D <= "00000110"; -- 0x00C7
when 000200 => D <= "00110011"; -- 0x00C8
when 000201 => D <= "00111010"; -- 0x00C9
when 000202 => D <= "00000001"; -- 0x00CA
when 000203 => D <= "00000110"; -- 0x00CB
when 000204 => D <= "00110011"; -- 0x00CC
when 000205 => D <= "00111010"; -- 0x00CD
when 000206 => D <= "00010001"; -- 0x00CE
when 000207 => D <= "00000110"; -- 0x00CF
when 000208 => D <= "00110011"; -- 0x00D0
when 000209 => D <= "00111010"; -- 0x00D1
when 000210 => D <= "00000011"; -- 0x00D2
when 000211 => D <= "00000110"; -- 0x00D3
when 000212 => D <= "00110011"; -- 0x00D4
when 000213 => D <= "00111010"; -- 0x00D5
when 000214 => D <= "00110011"; -- 0x00D6
when 000215 => D <= "00101001"; -- 0x00D7
when 000216 => D <= "00110011"; -- 0x00D8
when 000217 => D <= "00101000"; -- 0x00D9
when 000218 => D <= "00100001"; -- 0x00DA
when 000219 => D <= "00010110"; -- 0x00DB
when 000220 => D <= "00110011"; -- 0x00DC
when 000221 => D <= "00111010"; -- 0x00DD
when 000222 => D <= "00110011"; -- 0x00DE
when 000223 => D <= "00101001"; -- 0x00DF
when 000224 => D <= "00000110"; -- 0x00E0
when 000225 => D <= "00010011"; -- 0x00E1
when 000226 => D <= "00110011"; -- 0x00E2
when 000227 => D <= "00111110"; -- 0x00E3
when 000228 => D <= "00110011"; -- 0x00E4
when 000229 => D <= "01010001"; -- 0x00E5
when 000230 => D <= "00111010"; -- 0x00E6
when 000231 => D <= "00110011"; -- 0x00E7
when 000232 => D <= "01010000"; -- 0x00E8
when 000233 => D <= "01000100"; -- 0x00E9
when 000234 => D <= "00110011"; -- 0x00EA
when 000235 => D <= "00101001"; -- 0x00EB
when 000236 => D <= "00000110"; -- 0x00EC
when 000237 => D <= "00000001"; -- 0x00ED
when 000238 => D <= "00110011"; -- 0x00EE
when 000239 => D <= "00111110"; -- 0x00EF
when 000240 => D <= "01000100"; -- 0x00F0
when 000241 => D <= "01001111"; -- 0x00F1
when 000242 => D <= "00000110"; -- 0x00F2
when 000243 => D <= "00110011"; -- 0x00F3
when 000244 => D <= "00111010"; -- 0x00F4
when 000245 => D <= "00001111"; -- 0x00F5
when 000246 => D <= "01110111"; -- 0x00F6
when 000247 => D <= "01111110"; -- 0x00F7
when 000248 => D <= "01110101"; -- 0x00F8
when 000249 => D <= "01111100"; -- 0x00F9
when 000250 => D <= "01110011"; -- 0x00FA
when 000251 => D <= "01111010"; -- 0x00FB
when 000252 => D <= "01110001"; -- 0x00FC
when 000253 => D <= "01111000"; -- 0x00FD
when 000254 => D <= "01111111"; -- 0x00FE
when 000255 => D <= "01110110"; -- 0x00FF
when 000256 => D <= "01111101"; -- 0x0100
when 000257 => D <= "01110100"; -- 0x0101
when 000258 => D <= "01111011"; -- 0x0102
when 000259 => D <= "01110010"; -- 0x0103
when 000260 => D <= "01111001"; -- 0x0104
when 000261 => D <= "01110000"; -- 0x0105
when 000262 => D <= "00011111"; -- 0x0106
when 000263 => D <= "01110111"; -- 0x0107
when 000264 => D <= "01111110"; -- 0x0108
when 000265 => D <= "01110101"; -- 0x0109
when 000266 => D <= "01111100"; -- 0x010A
when 000267 => D <= "01110011"; -- 0x010B
when 000268 => D <= "01111010"; -- 0x010C
when 000269 => D <= "01110001"; -- 0x010D
when 000270 => D <= "01111000"; -- 0x010E
when 000271 => D <= "01111111"; -- 0x010F
when 000272 => D <= "01110110"; -- 0x0110
when 000273 => D <= "01111101"; -- 0x0111
when 000274 => D <= "01110100"; -- 0x0112
when 000275 => D <= "01111011"; -- 0x0113
when 000276 => D <= "01110010"; -- 0x0114
when 000277 => D <= "01111001"; -- 0x0115
when 000278 => D <= "01110000"; -- 0x0116
when 000279 => D <= "00101111"; -- 0x0117
when 000280 => D <= "01110111"; -- 0x0118
when 000281 => D <= "01111110"; -- 0x0119
when 000282 => D <= "01110101"; -- 0x011A
when 000283 => D <= "01111100"; -- 0x011B
when 000284 => D <= "01110011"; -- 0x011C
when 000285 => D <= "01111010"; -- 0x011D
when 000286 => D <= "01110001"; -- 0x011E
when 000287 => D <= "01111000"; -- 0x011F
when 000288 => D <= "01111111"; -- 0x0120
when 000289 => D <= "01110110"; -- 0x0121
when 000290 => D <= "01111101"; -- 0x0122
when 000291 => D <= "01110100"; -- 0x0123
when 000292 => D <= "01111011"; -- 0x0124
when 000293 => D <= "01110010"; -- 0x0125
when 000294 => D <= "01111001"; -- 0x0126
when 000295 => D <= "01110000"; -- 0x0127
when 000296 => D <= "00111111"; -- 0x0128
when 000297 => D <= "01110111"; -- 0x0129
when 000298 => D <= "01111110"; -- 0x012A
when 000299 => D <= "01110101"; -- 0x012B
when 000300 => D <= "01111100"; -- 0x012C
when 000301 => D <= "01110011"; -- 0x012D
when 000302 => D <= "01111010"; -- 0x012E
when 000303 => D <= "01110001"; -- 0x012F
when 000304 => D <= "01111000"; -- 0x0130
when 000305 => D <= "01111111"; -- 0x0131
when 000306 => D <= "01110110"; -- 0x0132
when 000307 => D <= "01111101"; -- 0x0133
when 000308 => D <= "01110100"; -- 0x0134
when 000309 => D <= "01111011"; -- 0x0135
when 000310 => D <= "01110010"; -- 0x0136
when 000311 => D <= "01111001"; -- 0x0137
when 000312 => D <= "01110000"; -- 0x0138
when 000313 => D <= "00001111"; -- 0x0139
when 000314 => D <= "00110011"; -- 0x013A
when 000315 => D <= "00111010"; -- 0x013B
when 000316 => D <= "00000101"; -- 0x013C
when 000317 => D <= "00000100"; -- 0x013D
when 000318 => D <= "00110011"; -- 0x013E
when 000319 => D <= "00111010"; -- 0x013F
when 000320 => D <= "00000101"; -- 0x0140
when 000321 => D <= "00000100"; -- 0x0141
when 000322 => D <= "00110011"; -- 0x0142
when 000323 => D <= "00111010"; -- 0x0143
when 000324 => D <= "00000101"; -- 0x0144
when 000325 => D <= "00000100"; -- 0x0145
when 000326 => D <= "00110011"; -- 0x0146
when 000327 => D <= "00111010"; -- 0x0147
when 000328 => D <= "00000101"; -- 0x0148
when 000329 => D <= "00000100"; -- 0x0149
when 000330 => D <= "00110011"; -- 0x014A
when 000331 => D <= "00111010"; -- 0x014B
when 000332 => D <= "00000101"; -- 0x014C
when 000333 => D <= "00000100"; -- 0x014D
when 000334 => D <= "00110011"; -- 0x014E
when 000335 => D <= "00111010"; -- 0x014F
when 000336 => D <= "00000101"; -- 0x0150
when 000337 => D <= "00000100"; -- 0x0151
when 000338 => D <= "00110011"; -- 0x0152
when 000339 => D <= "00111010"; -- 0x0153
when 000340 => D <= "00000101"; -- 0x0154
when 000341 => D <= "00000100"; -- 0x0155
when 000342 => D <= "00110011"; -- 0x0156
when 000343 => D <= "00111010"; -- 0x0157
when 000344 => D <= "00000101"; -- 0x0158
when 000345 => D <= "00000100"; -- 0x0159
when 000346 => D <= "00110011"; -- 0x015A
when 000347 => D <= "00111010"; -- 0x015B
when 000348 => D <= "00000101"; -- 0x015C
when 000349 => D <= "00000100"; -- 0x015D
when 000350 => D <= "00110011"; -- 0x015E
when 000351 => D <= "00111010"; -- 0x015F
when 000352 => D <= "00000101"; -- 0x0160
when 000353 => D <= "00000100"; -- 0x0161
when 000354 => D <= "00110011"; -- 0x0162
when 000355 => D <= "00111010"; -- 0x0163
when 000356 => D <= "00000101"; -- 0x0164
when 000357 => D <= "00000100"; -- 0x0165
when 000358 => D <= "00110011"; -- 0x0166
when 000359 => D <= "00111010"; -- 0x0167
when 000360 => D <= "00000101"; -- 0x0168
when 000361 => D <= "00000100"; -- 0x0169
when 000362 => D <= "00110011"; -- 0x016A
when 000363 => D <= "00111010"; -- 0x016B
when 000364 => D <= "00000101"; -- 0x016C
when 000365 => D <= "00000100"; -- 0x016D
when 000366 => D <= "00110011"; -- 0x016E
when 000367 => D <= "00111010"; -- 0x016F
when 000368 => D <= "00000101"; -- 0x0170
when 000369 => D <= "00000100"; -- 0x0171
when 000370 => D <= "00110011"; -- 0x0172
when 000371 => D <= "00111010"; -- 0x0173
when 000372 => D <= "00000101"; -- 0x0174
when 000373 => D <= "00000100"; -- 0x0175
when 000374 => D <= "00110011"; -- 0x0176
when 000375 => D <= "00111010"; -- 0x0177
when 000376 => D <= "00000101"; -- 0x0178
when 000377 => D <= "00000100"; -- 0x0179
when 000378 => D <= "01000100"; -- 0x017A
when 000379 => D <= "00011111"; -- 0x017B
when 000380 => D <= "00110011"; -- 0x017C
when 000381 => D <= "00111010"; -- 0x017D
when 000382 => D <= "00000101"; -- 0x017E
when 000383 => D <= "00000100"; -- 0x017F
when 000384 => D <= "00110011"; -- 0x0180
when 000385 => D <= "00111010"; -- 0x0181
when 000386 => D <= "00000101"; -- 0x0182
when 000387 => D <= "00000100"; -- 0x0183
when 000388 => D <= "00110011"; -- 0x0184
when 000389 => D <= "00111010"; -- 0x0185
when 000390 => D <= "00000101"; -- 0x0186
when 000391 => D <= "00000100"; -- 0x0187
when 000392 => D <= "00110011"; -- 0x0188
when 000393 => D <= "00111010"; -- 0x0189
when 000394 => D <= "00000101"; -- 0x018A
when 000395 => D <= "00000100"; -- 0x018B
when 000396 => D <= "00110011"; -- 0x018C
when 000397 => D <= "00111010"; -- 0x018D
when 000398 => D <= "00000101"; -- 0x018E
when 000399 => D <= "00000100"; -- 0x018F
when 000400 => D <= "00110011"; -- 0x0190
when 000401 => D <= "00111010"; -- 0x0191
when 000402 => D <= "00000101"; -- 0x0192
when 000403 => D <= "00000100"; -- 0x0193
when 000404 => D <= "00110011"; -- 0x0194
when 000405 => D <= "00111010"; -- 0x0195
when 000406 => D <= "00000101"; -- 0x0196
when 000407 => D <= "00000100"; -- 0x0197
when 000408 => D <= "00110011"; -- 0x0198
when 000409 => D <= "00111010"; -- 0x0199
when 000410 => D <= "00000101"; -- 0x019A
when 000411 => D <= "00000100"; -- 0x019B
when 000412 => D <= "00110011"; -- 0x019C
when 000413 => D <= "00111010"; -- 0x019D
when 000414 => D <= "00000101"; -- 0x019E
when 000415 => D <= "00000100"; -- 0x019F
when 000416 => D <= "00110011"; -- 0x01A0
when 000417 => D <= "00111010"; -- 0x01A1
when 000418 => D <= "00000101"; -- 0x01A2
when 000419 => D <= "00000100"; -- 0x01A3
when 000420 => D <= "00110011"; -- 0x01A4
when 000421 => D <= "00111010"; -- 0x01A5
when 000422 => D <= "00000101"; -- 0x01A6
when 000423 => D <= "00000100"; -- 0x01A7
when 000424 => D <= "00110011"; -- 0x01A8
when 000425 => D <= "00111010"; -- 0x01A9
when 000426 => D <= "00000101"; -- 0x01AA
when 000427 => D <= "00000100"; -- 0x01AB
when 000428 => D <= "00110011"; -- 0x01AC
when 000429 => D <= "00111010"; -- 0x01AD
when 000430 => D <= "00000101"; -- 0x01AE
when 000431 => D <= "00000100"; -- 0x01AF
when 000432 => D <= "00110011"; -- 0x01B0
when 000433 => D <= "00111010"; -- 0x01B1
when 000434 => D <= "00000101"; -- 0x01B2
when 000435 => D <= "00000100"; -- 0x01B3
when 000436 => D <= "00110011"; -- 0x01B4
when 000437 => D <= "00111010"; -- 0x01B5
when 000438 => D <= "00000101"; -- 0x01B6
when 000439 => D <= "00000100"; -- 0x01B7
when 000440 => D <= "00110011"; -- 0x01B8
when 000441 => D <= "00111010"; -- 0x01B9
when 000442 => D <= "00000101"; -- 0x01BA
when 000443 => D <= "00000100"; -- 0x01BB
when 000444 => D <= "01000100"; -- 0x01BC
when 000445 => D <= "00101111"; -- 0x01BD
when 000446 => D <= "00110011"; -- 0x01BE
when 000447 => D <= "00111010"; -- 0x01BF
when 000448 => D <= "00000101"; -- 0x01C0
when 000449 => D <= "00000100"; -- 0x01C1
when 000450 => D <= "00110011"; -- 0x01C2
when 000451 => D <= "00111010"; -- 0x01C3
when 000452 => D <= "00000101"; -- 0x01C4
when 000453 => D <= "00000100"; -- 0x01C5
when 000454 => D <= "00110011"; -- 0x01C6
when 000455 => D <= "00111010"; -- 0x01C7
when 000456 => D <= "00000101"; -- 0x01C8
when 000457 => D <= "00000100"; -- 0x01C9
when 000458 => D <= "00110011"; -- 0x01CA
when 000459 => D <= "00111010"; -- 0x01CB
when 000460 => D <= "00000101"; -- 0x01CC
when 000461 => D <= "00000100"; -- 0x01CD
when 000462 => D <= "00110011"; -- 0x01CE
when 000463 => D <= "00111010"; -- 0x01CF
when 000464 => D <= "00000101"; -- 0x01D0
when 000465 => D <= "00000100"; -- 0x01D1
when 000466 => D <= "00110011"; -- 0x01D2
when 000467 => D <= "00111010"; -- 0x01D3
when 000468 => D <= "00000101"; -- 0x01D4
when 000469 => D <= "00000100"; -- 0x01D5
when 000470 => D <= "00110011"; -- 0x01D6
when 000471 => D <= "00111010"; -- 0x01D7
when 000472 => D <= "00000101"; -- 0x01D8
when 000473 => D <= "00000100"; -- 0x01D9
when 000474 => D <= "00110011"; -- 0x01DA
when 000475 => D <= "00111010"; -- 0x01DB
when 000476 => D <= "00000101"; -- 0x01DC
when 000477 => D <= "00000100"; -- 0x01DD
when 000478 => D <= "00110011"; -- 0x01DE
when 000479 => D <= "00111010"; -- 0x01DF
when 000480 => D <= "00000101"; -- 0x01E0
when 000481 => D <= "00000100"; -- 0x01E1
when 000482 => D <= "00110011"; -- 0x01E2
when 000483 => D <= "00111010"; -- 0x01E3
when 000484 => D <= "00000101"; -- 0x01E4
when 000485 => D <= "00000100"; -- 0x01E5
when 000486 => D <= "00110011"; -- 0x01E6
when 000487 => D <= "00111010"; -- 0x01E7
when 000488 => D <= "00000101"; -- 0x01E8
when 000489 => D <= "00000100"; -- 0x01E9
when 000490 => D <= "00110011"; -- 0x01EA
when 000491 => D <= "00111010"; -- 0x01EB
when 000492 => D <= "00000101"; -- 0x01EC
when 000493 => D <= "00000100"; -- 0x01ED
when 000494 => D <= "00110011"; -- 0x01EE
when 000495 => D <= "00111010"; -- 0x01EF
when 000496 => D <= "00000101"; -- 0x01F0
when 000497 => D <= "00000100"; -- 0x01F1
when 000498 => D <= "00110011"; -- 0x01F2
when 000499 => D <= "00111010"; -- 0x01F3
when 000500 => D <= "00000101"; -- 0x01F4
when 000501 => D <= "00000100"; -- 0x01F5
when 000502 => D <= "00110011"; -- 0x01F6
when 000503 => D <= "00111010"; -- 0x01F7
when 000504 => D <= "00000101"; -- 0x01F8
when 000505 => D <= "00000100"; -- 0x01F9
when 000506 => D <= "00110011"; -- 0x01FA
when 000507 => D <= "00111010"; -- 0x01FB
when 000508 => D <= "00000101"; -- 0x01FC
when 000509 => D <= "00000100"; -- 0x01FD
when 000510 => D <= "01000100"; -- 0x01FE
when 000511 => D <= "00111111"; -- 0x01FF
when 000512 => D <= "00110011"; -- 0x0200
when 000513 => D <= "00111010"; -- 0x0201
when 000514 => D <= "00000101"; -- 0x0202
when 000515 => D <= "00000100"; -- 0x0203
when 000516 => D <= "00110011"; -- 0x0204
when 000517 => D <= "00111010"; -- 0x0205
when 000518 => D <= "00000101"; -- 0x0206
when 000519 => D <= "00000100"; -- 0x0207
when 000520 => D <= "00110011"; -- 0x0208
when 000521 => D <= "00111010"; -- 0x0209
when 000522 => D <= "00000101"; -- 0x020A
when 000523 => D <= "00000100"; -- 0x020B
when 000524 => D <= "00110011"; -- 0x020C
when 000525 => D <= "00111010"; -- 0x020D
when 000526 => D <= "00000101"; -- 0x020E
when 000527 => D <= "00000100"; -- 0x020F
when 000528 => D <= "00110011"; -- 0x0210
when 000529 => D <= "00111010"; -- 0x0211
when 000530 => D <= "00000101"; -- 0x0212
when 000531 => D <= "00000100"; -- 0x0213
when 000532 => D <= "00110011"; -- 0x0214
when 000533 => D <= "00111010"; -- 0x0215
when 000534 => D <= "00000101"; -- 0x0216
when 000535 => D <= "00000100"; -- 0x0217
when 000536 => D <= "00110011"; -- 0x0218
when 000537 => D <= "00111010"; -- 0x0219
when 000538 => D <= "00000101"; -- 0x021A
when 000539 => D <= "00000100"; -- 0x021B
when 000540 => D <= "00110011"; -- 0x021C
when 000541 => D <= "00111010"; -- 0x021D
when 000542 => D <= "00000101"; -- 0x021E
when 000543 => D <= "00000100"; -- 0x021F
when 000544 => D <= "00110011"; -- 0x0220
when 000545 => D <= "00111010"; -- 0x0221
when 000546 => D <= "00000101"; -- 0x0222
when 000547 => D <= "00000100"; -- 0x0223
when 000548 => D <= "00110011"; -- 0x0224
when 000549 => D <= "00111010"; -- 0x0225
when 000550 => D <= "00000101"; -- 0x0226
when 000551 => D <= "00000100"; -- 0x0227
when 000552 => D <= "00110011"; -- 0x0228
when 000553 => D <= "00111010"; -- 0x0229
when 000554 => D <= "00000101"; -- 0x022A
when 000555 => D <= "00000100"; -- 0x022B
when 000556 => D <= "00110011"; -- 0x022C
when 000557 => D <= "00111010"; -- 0x022D
when 000558 => D <= "00000101"; -- 0x022E
when 000559 => D <= "00000100"; -- 0x022F
when 000560 => D <= "00110011"; -- 0x0230
when 000561 => D <= "00111010"; -- 0x0231
when 000562 => D <= "00000101"; -- 0x0232
when 000563 => D <= "00000100"; -- 0x0233
when 000564 => D <= "00110011"; -- 0x0234
when 000565 => D <= "00111010"; -- 0x0235
when 000566 => D <= "00000101"; -- 0x0236
when 000567 => D <= "00000100"; -- 0x0237
when 000568 => D <= "00110011"; -- 0x0238
when 000569 => D <= "00111010"; -- 0x0239
when 000570 => D <= "00000101"; -- 0x023A
when 000571 => D <= "00000100"; -- 0x023B
when 000572 => D <= "00110011"; -- 0x023C
when 000573 => D <= "00111010"; -- 0x023D
when 000574 => D <= "00000101"; -- 0x023E
when 000575 => D <= "00000100"; -- 0x023F
when 000576 => D <= "01000100"; -- 0x0240
when 000577 => D <= "01100010"; -- 0x0241
when 000578 => D <= "01000001"; -- 0x0242
when others => D <= "--------";
end case;
end if;
end process;
end;
| gpl-2.0 | e6725a0d5ea6bbfaa2e67a45153e675f | 0.570146 | 2.622752 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/hdl/base_zynq_design.vhd | 1 | 150,913 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Wed Aug 26 21:30:37 2015
--Host : localhost.localdomain running 64-bit CentOS release 6.7 (Final)
--Command : generate_target base_zynq_design.bd
--Design : base_zynq_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1R5MXF4 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1R5MXF4;
architecture STRUCTURE of m00_couplers_imp_1R5MXF4 is
component base_zynq_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component base_zynq_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(8 downto 0) <= auto_pc_to_m00_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= auto_pc_to_m00_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component base_zynq_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_19312F is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_19312F;
architecture STRUCTURE of m01_couplers_imp_19312F is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_m01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_m01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_m01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_m01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(12 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(12 downto 0);
M_AXI_arburst(1 downto 0) <= m01_couplers_to_m01_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= m01_couplers_to_m01_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= m01_couplers_to_m01_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= m01_couplers_to_m01_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= m01_couplers_to_m01_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(12 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(12 downto 0);
M_AXI_awburst(1 downto 0) <= m01_couplers_to_m01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= m01_couplers_to_m01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= m01_couplers_to_m01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= m01_couplers_to_m01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= m01_couplers_to_m01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= m01_couplers_to_m01_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rlast(0) <= m01_couplers_to_m01_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(12 downto 0) <= S_AXI_araddr(12 downto 0);
m01_couplers_to_m01_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m01_couplers_to_m01_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m01_couplers_to_m01_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m01_couplers_to_m01_couplers_ARLOCK(0) <= S_AXI_arlock(0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(12 downto 0) <= S_AXI_awaddr(12 downto 0);
m01_couplers_to_m01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m01_couplers_to_m01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m01_couplers_to_m01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m01_couplers_to_m01_couplers_AWLOCK(0) <= S_AXI_awlock(0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RLAST(0) <= M_AXI_rlast(0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WLAST(0) <= S_AXI_wlast(0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1UTISAU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1UTISAU;
architecture STRUCTURE of s00_couplers_imp_1UTISAU is
component base_zynq_design_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component base_zynq_design_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_pc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(11 downto 0) <= auto_pc_to_s00_couplers_ARID(11 downto 0);
M_AXI_arlen(7 downto 0) <= auto_pc_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_pc_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(11 downto 0) <= auto_pc_to_s00_couplers_AWID(11 downto 0);
M_AXI_awlen(7 downto 0) <= auto_pc_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_pc_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast <= auto_pc_to_s00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BID(11 downto 0) <= M_AXI_bid(11 downto 0);
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RID(11 downto 0) <= M_AXI_rid(11 downto 0);
auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component base_zynq_design_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arid(11 downto 0) => auto_pc_to_s00_couplers_ARID(11 downto 0),
m_axi_arlen(7 downto 0) => auto_pc_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_pc_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_pc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awid(11 downto 0) => auto_pc_to_s00_couplers_AWID(11 downto 0),
m_axi_awlen(7 downto 0) => auto_pc_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_pc_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_pc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_pc_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bid(11 downto 0) => auto_pc_to_s00_couplers_BID(11 downto 0),
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rid(11 downto 0) => auto_pc_to_s00_couplers_RID(11 downto 0),
m_axi_rlast => auto_pc_to_s00_couplers_RLAST,
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wlast => auto_pc_to_s00_couplers_WLAST,
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_zynq_design_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M01_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M01_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M01_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M01_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end base_zynq_design_processing_system7_0_axi_periph_0;
architecture STRUCTURE of base_zynq_design_processing_system7_0_axi_periph_0 is
component base_zynq_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component base_zynq_design_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC;
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARBURST : STD_LOGIC_VECTOR ( 3 downto 2 );
signal xbar_to_m01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_ARLEN : STD_LOGIC_VECTOR ( 15 downto 8 );
signal xbar_to_m01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWBURST : STD_LOGIC_VECTOR ( 3 downto 2 );
signal xbar_to_m01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_AWLEN : STD_LOGIC_VECTOR ( 15 downto 8 );
signal xbar_to_m01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
signal NLW_xbar_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
signal NLW_xbar_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
signal NLW_xbar_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M00_AXI_arvalid <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
M00_AXI_awaddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M00_AXI_awvalid <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
M00_AXI_bready <= m00_couplers_to_processing_system7_0_axi_periph_BREADY;
M00_AXI_rready <= m00_couplers_to_processing_system7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_processing_system7_0_axi_periph_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(12 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(12 downto 0);
M01_AXI_arburst(1 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0);
M01_AXI_arcache(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0);
M01_AXI_arlen(7 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0);
M01_AXI_arlock(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARLOCK(0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M01_AXI_arsize(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(12 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(12 downto 0);
M01_AXI_awburst(1 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0);
M01_AXI_awcache(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0);
M01_AXI_awlen(7 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0);
M01_AXI_awlock(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWLOCK(0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M01_AXI_awsize(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wlast(0) <= m01_couplers_to_processing_system7_0_axi_periph_WLAST(0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready;
m00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready;
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid;
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid;
m00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready;
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RLAST(0) <= M01_AXI_rlast(0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_1R5MXF4
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready => m00_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m00_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready => m00_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m00_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m00_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_19312F
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(12 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(12 downto 0),
M_AXI_arburst(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0),
M_AXI_arlock(0) => m01_couplers_to_processing_system7_0_axi_periph_ARLOCK(0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arsize(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(12 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(12 downto 0),
M_AXI_awburst(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0),
M_AXI_awlock(0) => m01_couplers_to_processing_system7_0_axi_periph_AWLOCK(0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awsize(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rlast(0) => m01_couplers_to_processing_system7_0_axi_periph_RLAST(0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wlast(0) => m01_couplers_to_processing_system7_0_axi_periph_WLAST(0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(12 downto 0) => xbar_to_m01_couplers_ARADDR(44 downto 32),
S_AXI_arburst(1 downto 0) => xbar_to_m01_couplers_ARBURST(3 downto 2),
S_AXI_arcache(3 downto 0) => xbar_to_m01_couplers_ARCACHE(7 downto 4),
S_AXI_arlen(7 downto 0) => xbar_to_m01_couplers_ARLEN(15 downto 8),
S_AXI_arlock(0) => xbar_to_m01_couplers_ARLOCK(1),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => xbar_to_m01_couplers_ARSIZE(5 downto 3),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(12 downto 0) => xbar_to_m01_couplers_AWADDR(44 downto 32),
S_AXI_awburst(1 downto 0) => xbar_to_m01_couplers_AWBURST(3 downto 2),
S_AXI_awcache(3 downto 0) => xbar_to_m01_couplers_AWCACHE(7 downto 4),
S_AXI_awlen(7 downto 0) => xbar_to_m01_couplers_AWLEN(15 downto 8),
S_AXI_awlock(0) => xbar_to_m01_couplers_AWLOCK(1),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => xbar_to_m01_couplers_AWSIZE(5 downto 3),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rlast(0) => xbar_to_m01_couplers_RLAST(0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wlast(0) => xbar_to_m01_couplers_WLAST(1),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1UTISAU
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0),
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast => s00_couplers_to_xbar_WLAST,
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component base_zynq_design_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(3 downto 2) => xbar_to_m01_couplers_ARBURST(3 downto 2),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(7 downto 4) => xbar_to_m01_couplers_ARCACHE(7 downto 4),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(15 downto 8) => xbar_to_m01_couplers_ARLEN(15 downto 8),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(1) => xbar_to_m01_couplers_ARLOCK(1),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(7 downto 4) => NLW_xbar_m_axi_arqos_UNCONNECTED(7 downto 4),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(7 downto 4) => NLW_xbar_m_axi_arregion_UNCONNECTED(7 downto 4),
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(5 downto 3) => xbar_to_m01_couplers_ARSIZE(5 downto 3),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(3 downto 2) => xbar_to_m01_couplers_AWBURST(3 downto 2),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(7 downto 4) => xbar_to_m01_couplers_AWCACHE(7 downto 4),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awlen(15 downto 8) => xbar_to_m01_couplers_AWLEN(15 downto 8),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(1) => xbar_to_m01_couplers_AWLOCK(1),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(7 downto 4) => NLW_xbar_m_axi_awqos_UNCONNECTED(7 downto 4),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(7 downto 4) => NLW_xbar_m_axi_awregion_UNCONNECTED(7 downto 4),
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(5 downto 3) => xbar_to_m01_couplers_AWSIZE(5 downto 3),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rlast(1) => xbar_to_m01_couplers_RLAST(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(1) => xbar_to_m01_couplers_WLAST(1),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST,
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_zynq_design is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end base_zynq_design;
architecture STRUCTURE of base_zynq_design is
component base_zynq_design_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component base_zynq_design_processing_system7_0_0;
component base_zynq_design_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component base_zynq_design_axi_gpio_0_0;
component base_zynq_design_blk_mem_gen_0_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component base_zynq_design_blk_mem_gen_0_0;
component base_zynq_design_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component base_zynq_design_axi_bram_ctrl_0_0;
component base_zynq_design_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component base_zynq_design_rst_processing_system7_0_100M_0;
component base_zynq_design_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component base_zynq_design_xlconcat_0_0;
signal GND_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_CLK : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_EN : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_RST : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_gpio_0_ip2intc_irpt : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_CLK1 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_blk_mem_gen_0_addra_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 13 );
signal NLW_processing_system7_0_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of axi_bram_ctrl_0 : label is "byte 0x40000000 32 > base_zynq_design blk_mem_gen_0";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of axi_bram_ctrl_0 : label is "yes";
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of processing_system7_0 : label is "ARM > base_zynq_design axi_bram_ctrl_0";
attribute KEEP_HIERARCHY of processing_system7_0 : label is "yes";
begin
axi_gpio_0_GPIO2_TRI_I(4 downto 0) <= btns_5bits_tri_i(4 downto 0);
leds_8bits_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_bram_ctrl_0: component base_zynq_design_axi_bram_ctrl_0_0
port map (
bram_addr_a(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
bram_clk_a => axi_bram_ctrl_0_BRAM_PORTA_CLK,
bram_en_a => axi_bram_ctrl_0_BRAM_PORTA_EN,
bram_rddata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
bram_rst_a => axi_bram_ctrl_0_BRAM_PORTA_RST,
bram_we_a(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0),
bram_wrdata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(12 downto 0),
s_axi_arburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARCACHE(3 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARLEN(7 downto 0),
s_axi_arlock => processing_system7_0_axi_periph_M01_AXI_ARLOCK(0),
s_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
s_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_arsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_awaddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(12 downto 0),
s_axi_awburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWLEN(7 downto 0),
s_axi_awlock => processing_system7_0_axi_periph_M01_AXI_AWLOCK(0),
s_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_awsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rlast => processing_system7_0_axi_periph_M01_AXI_RLAST,
s_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wlast => processing_system7_0_axi_periph_M01_AXI_WLAST(0),
s_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0)
);
axi_gpio_0: component base_zynq_design_axi_gpio_0_0
port map (
gpio2_io_i(4 downto 0) => axi_gpio_0_GPIO2_TRI_I(4 downto 0),
gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
ip2intc_irpt => axi_gpio_0_ip2intc_irpt,
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID
);
blk_mem_gen_0: component base_zynq_design_blk_mem_gen_0_0
port map (
addra(31 downto 13) => NLW_blk_mem_gen_0_addra_UNCONNECTED(31 downto 13),
addra(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
clka => axi_bram_ctrl_0_BRAM_PORTA_CLK,
dina(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
douta(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
ena => axi_bram_ctrl_0_BRAM_PORTA_EN,
rsta => axi_bram_ctrl_0_BRAM_PORTA_RST,
wea(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0)
);
processing_system7_0: component base_zynq_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
DMA0_ACLK => processing_system7_0_FCLK_CLK1,
DMA0_DAREADY => GND_1,
DMA0_DATYPE(1 downto 0) => NLW_processing_system7_0_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_processing_system7_0_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => GND_1,
DMA0_DRREADY => NLW_processing_system7_0_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1) => GND_1,
DMA0_DRTYPE(0) => GND_1,
DMA0_DRVALID => GND_1,
DMA2_ACLK => processing_system7_0_FCLK_CLK1,
DMA2_DAREADY => GND_1,
DMA2_DATYPE(1 downto 0) => NLW_processing_system7_0_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_processing_system7_0_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => GND_1,
DMA2_DRREADY => NLW_processing_system7_0_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1) => GND_1,
DMA2_DRTYPE(0) => GND_1,
DMA2_DRVALID => GND_1,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_CLK1 => processing_system7_0_FCLK_CLK1,
FCLK_CLK2 => NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FCLK_RESET1_N => NLW_processing_system7_0_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_processing_system7_0_FCLK_RESET2_N_UNCONNECTED,
I2C1_SCL_I => GND_1,
I2C1_SCL_O => NLW_processing_system7_0_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_processing_system7_0_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => GND_1,
I2C1_SDA_O => NLW_processing_system7_0_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_processing_system7_0_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => xlconcat_0_dout(0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.base_zynq_design_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(12 downto 0),
M01_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARBURST(1 downto 0),
M01_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARCACHE(3 downto 0),
M01_AXI_arlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARLEN(7 downto 0),
M01_AXI_arlock(0) => processing_system7_0_axi_periph_M01_AXI_ARLOCK(0),
M01_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARSIZE(2 downto 0),
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(12 downto 0),
M01_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWBURST(1 downto 0),
M01_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWCACHE(3 downto 0),
M01_AXI_awlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWLEN(7 downto 0),
M01_AXI_awlock(0) => processing_system7_0_axi_periph_M01_AXI_AWLOCK(0),
M01_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWSIZE(2 downto 0),
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rlast(0) => processing_system7_0_axi_periph_M01_AXI_RLAST,
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wlast(0) => processing_system7_0_axi_periph_M01_AXI_WLAST(0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_50M: component base_zynq_design_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
xlconcat_0: component base_zynq_design_xlconcat_0_0
port map (
In0(0) => axi_gpio_0_ip2intc_irpt,
dout(0) => xlconcat_0_dout(0)
);
end STRUCTURE;
| gpl-3.0 | 219968508e04e4b2acfa96b3a238ae1b | 0.679053 | 2.822386 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneive_atoms.vhd | 1 | 361,466 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneive_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneive_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneive_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneive_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneive_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneive_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneive_pllpack;
package body cycloneive_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneive_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneive_dffe : entity is TRUE;
end cycloneive_dffe;
-- architecture body --
architecture behave of cycloneive_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneive_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneive_mux21 : entity is TRUE;
end cycloneive_mux21;
architecture AltVITAL of cycloneive_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneive_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneive_mux41 : entity is TRUE;
end cycloneive_mux41;
architecture AltVITAL of cycloneive_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneive_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneive_atom_pack.all;
-- entity declaration --
entity cycloneive_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneive_and1 : entity is TRUE;
end cycloneive_and1;
-- architecture body --
architecture AltVITAL of cycloneive_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneive_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneive_lcell_comb : entity is TRUE;
end cycloneive_lcell_comb;
architecture vital_lcell_comb of cycloneive_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_routing_wire
--
-- Description : Cycloneive Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
ENTITY cycloneive_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneive_routing_wire : entity is TRUE;
end cycloneive_routing_wire;
ARCHITECTURE behave of cycloneive_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneive_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cycloneive PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneive_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneive_mn_cntr;
ARCHITECTURE behave of cycloneive_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneive_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cycloneive PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneive_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneive_scale_cntr;
ARCHITECTURE behave of cycloneive_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneive_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneive_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneive_pll_reg;
ARCHITECTURE behave of cycloneive_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneive_pll
--
-- Description : Timing simulation model for the Cycloneive PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneive_atom_pack.all;
USE work.cycloneive_pllpack.all;
USE work.cycloneive_mn_cntr;
USE work.cycloneive_scale_cntr;
USE work.cycloneive_dffe;
USE work.cycloneive_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIVE:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneive_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneive_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cycloneive";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneive_pll;
ARCHITECTURE vital_pll of cycloneive_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneive_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneive_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneive_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneive_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneive_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneive_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneive_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneive_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneive_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneive_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneive_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneive_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneive_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_ff
--
-- Description : Cycloneive FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
use work.cycloneive_and1;
entity cycloneive_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneive_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneive_ff : entity is TRUE;
end cycloneive_ff;
architecture vital_lcell_ff of cycloneive_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneive_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneive_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneive_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneive_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneive_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneive_atom_pack.all;
ENTITY cycloneive_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneive_ram_register;
ARCHITECTURE reg_arch OF cycloneive_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneive_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneive_atom_pack.all;
ENTITY cycloneive_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneive_ram_pulse_generator:ENTITY IS TRUE;
END cycloneive_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneive_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneive_atom_pack.all;
USE work.cycloneive_ram_register;
USE work.cycloneive_ram_pulse_generator;
ENTITY cycloneive_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneive_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneive_ram_block;
ARCHITECTURE block_arch OF cycloneive_ram_block IS
COMPONENT cycloneive_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneive_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneive_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneive_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneive_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneive_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneive_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneive_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneive_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneive_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneive_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneive_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneive_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneive_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneive_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneive_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneive_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneive_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneive_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneive_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneive_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneive_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneive_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneive_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneive_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneive_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneive_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneive_atom_pack.all;
ENTITY cycloneive_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneive_mac_data_reg;
ARCHITECTURE vital_cycloneive_mac_data_reg OF cycloneive_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneive_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneive_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneive_atom_pack.all;
ENTITY cycloneive_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneive_mac_sign_reg;
ARCHITECTURE cycloneive_mac_sign_reg OF cycloneive_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneive_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneive_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneive_atom_pack.all;
ENTITY cycloneive_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneive_mac_mult_internal;
ARCHITECTURE vital_cycloneive_mac_mult_internal OF cycloneive_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneive_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneive_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneive_atom_pack.all;
USE work.cycloneive_mac_data_reg;
USE work.cycloneive_mac_sign_reg;
USE work.cycloneive_mac_mult_internal;
ENTITY cycloneive_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneive_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneive_mac_mult;
ARCHITECTURE vital_cycloneive_mac_mult OF cycloneive_mac_mult IS
COMPONENT cycloneive_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneive_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneive_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneive_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneive_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneive_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneive_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneive_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneive_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneive_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneive_atom_pack.all;
ENTITY cycloneive_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneive_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneive_mac_out;
ARCHITECTURE vital_cycloneive_mac_out OF cycloneive_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneive_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_io_ibuf
--
-- Description : Cycloneive IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
ENTITY cycloneive_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneive_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneive_io_ibuf;
ARCHITECTURE arch OF cycloneive_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_io_obuf
--
-- Description : Cycloneive IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
ENTITY cycloneive_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneive_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneive_io_obuf;
ARCHITECTURE arch OF cycloneive_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_ddio_oe
--
-- Description : Cycloneive DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneive_atom_pack.all;
ENTITY cycloneive_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneive_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneive_ddio_oe;
ARCHITECTURE arch OF cycloneive_ddio_oe IS
component cycloneive_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneive_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_latch
--
-- Description : Cyclone III latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneive_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneive_latch : entity is TRUE;
end cycloneive_latch;
architecture vital_latch of cycloneive_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_negedge,
SetupLow => tsetup_d_ena_noedge_negedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneive_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneive_ddio_out
--
-- Description : Cycloneive DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneive_atom_pack.all;
ENTITY cycloneive_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneive_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneive_ddio_out;
ARCHITECTURE arch OF cycloneive_ddio_out IS
component cycloneive_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneive_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneive_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneive_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneive_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneive_pseudo_diff_out --
--Description: Simulation model for Cycloneive Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
ENTITY cycloneive_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneive_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneive_pseudo_diff_out;
ARCHITECTURE arch OF cycloneive_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneive_io_pad
-- Description : Simulation model for cycloneive IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneive_io_pad IS
GENERIC (
lpm_type : string := "cycloneive_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneive_io_pad;
ARCHITECTURE arch OF cycloneive_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneive_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
ENTITY cycloneive_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneive_ena_reg : entity is TRUE;
end cycloneive_ena_reg;
ARCHITECTURE behave of cycloneive_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneive_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEIVE_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
use work.cycloneive_ena_reg;
entity cycloneive_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneive_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneive_clkctrl : entity is TRUE;
end cycloneive_clkctrl;
architecture vital_clkctrl of cycloneive_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneive_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal outclk_tmp : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneive_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneive_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_tmp <= ena_out AND clkmux_out;
-- output path
process (inclk_ipd,outclk_tmp)
variable outclk_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLK",
OutTemp => outclk_tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkctrl;
--
--
-- CYCLONEIVE_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneive_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneive_rublock;
architecture architecture_rublock of cycloneive_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIVE_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_apfcontroller is
generic
(
lpm_type: string := "cycloneive_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneive_apfcontroller;
architecture architecture_apfcontroller of cycloneive_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneive_termination
--
-- Description : Cycloneive Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneive_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneive_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneive_termination;
ARCHITECTURE cycloneive_termination_arch OF cycloneive_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneive_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneive_jtag
--
-- Description : Cycloneive JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_jtag is
generic (
lpm_type : string := "cycloneive_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneive_jtag;
architecture architecture_jtag of cycloneive_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneive_crcblock
--
-- Description : Cycloneive CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneive_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end cycloneive_crcblock;
architecture architecture_crcblock of cycloneive_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--
--
-- CYCLONEIVE_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneive_atom_pack.all;
entity cycloneive_oscillator is
generic
(
lpm_type: string := "cycloneive_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneive_oscillator;
architecture architecture_oscillator of cycloneive_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
| gpl-3.0 | a91664c4f225e1d3edb17dc26d32c5d2 | 0.464572 | 4.168581 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/main_to_elk.vhd | 1 | 3,427 | -- Copyright 2018 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Adapter component so that elk_interface doesn't have to deal directly with
-- the ext_* signals on the cpu_socket_expansion board.
entity main_to_elk is
port (
-- 55-116MHz clock for FPGA's internal flash
fast_clock : in std_logic;
debug_uart_txd : out std_logic;
debug_a : out std_logic;
debug_b : out std_logic;
ext_uart_rxd : in std_logic;
ext_uart_txd : out std_logic;
-- connections to the cpu_socket_expansion board
ext_A : in std_logic_vector(15 downto 0);
ext_D : inout std_logic_vector(7 downto 0);
ext_GP0 : in std_logic; -- PHI2
ext_GP1 : out std_logic; -- n_global_enable
ext_GP2 : in std_logic; -- 16MHz
ext_GP3 : out std_logic; -- dbuf_nOE
ext_GP4 : out std_logic; -- n_accessing_shadow_ram
ext_GP5 : out std_logic; -- n_cpu_is_external
ext_GP6 : in std_logic; -- RnW
ext_GP7 : in std_logic; -- nRESET
ext_GP8 : in std_logic; -- READY
ext_GP9 : in std_logic; -- /NMI
ext_GP10 : in std_logic; -- /IRQ
ext_GP11 : out std_logic := '1'; -- dbuf_driven_by_cpu
ext_GP12 : in std_logic
);
end main_to_elk;
architecture rtl of main_to_elk is
component elk_interface is
port (
debug_uart_txd : out std_logic;
debug_a : out std_logic;
debug_b : out std_logic;
ext_uart_rxd : in std_logic;
ext_uart_txd : out std_logic;
fast_clock : in std_logic; -- pass through for FPGA's internal flash
elk_A : in std_logic_vector(15 downto 0);
elk_D : inout std_logic_vector(7 downto 0);
elk_PHI0 : in std_logic;
elk_16MHz : in std_logic;
elk_nEN : out std_logic; -- global enable
elk_nDBUF_OE : out std_logic; -- /OE for DBUF chip
elk_nSHADOW : out std_logic; -- '0' when shadowing memory
elk_nCPU_IS_EXTERNAL : out std_logic; -- '0' for external cpu
elk_RnW : in std_logic; -- input
elk_nRESET : in std_logic; -- input
elk_READY : in std_logic; -- input
elk_nNMI : in std_logic; -- input
elk_nIRQ : in std_logic; -- input
elk_CPU_DBUF : out std_logic -- '0' when we're driving the bus, '1' when the cpu is
);
end component;
begin
exp0: component elk_interface port map (
debug_uart_txd => debug_uart_txd,
debug_a => debug_a,
debug_b => debug_b,
ext_uart_txd => ext_uart_txd,
ext_uart_rxd => ext_uart_rxd,
fast_clock => fast_clock,
elk_A => ext_A,
elk_D => ext_D,
elk_PHI0 => ext_GP0,
elk_nEN => ext_GP1,
elk_16MHz => ext_GP2,
elk_nDBUF_OE => ext_GP3,
elk_nSHADOW => ext_GP4,
elk_nCPU_IS_EXTERNAL => ext_GP5,
elk_RnW => ext_GP6,
elk_nRESET => ext_GP7,
elk_READY => ext_GP8,
elk_nNMI => ext_GP9,
elk_nIRQ => ext_GP10,
elk_CPU_DBUF => ext_GP11
);
end rtl;
| apache-2.0 | bc045ff0bbb6196b997f5f8aed635b55 | 0.630581 | 3.032743 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/maxv_atoms.vhd | 1 | 132,836 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package maxv_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE maxv_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end maxv_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body maxv_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end maxv_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package maxv_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end maxv_pllpack;
package body maxv_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end maxv_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxv_atom_pack.all;
entity maxv_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of maxv_dffe : entity is TRUE;
end maxv_dffe;
-- architecture body --
architecture behave of maxv_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- maxv_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxv_atom_pack.all;
entity maxv_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of maxv_mux21 : entity is TRUE;
end maxv_mux21;
architecture AltVITAL of maxv_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- maxv_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxv_atom_pack.all;
entity maxv_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of maxv_mux41 : entity is TRUE;
end maxv_mux41;
architecture AltVITAL of maxv_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- maxv_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxv_atom_pack.all;
-- entity declaration --
entity maxv_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of maxv_and1 : entity is TRUE;
end maxv_and1;
-- architecture body --
architecture AltVITAL of maxv_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : maxv_jtag
--
-- Description : MAXV JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.maxv_atom_pack.all;
entity maxv_jtag is
generic (
lpm_type : string := "maxv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end maxv_jtag;
architecture architecture_jtag of maxv_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : maxv_crcblock
--
-- Description : MAXV CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.maxv_atom_pack.all;
entity maxv_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "maxv_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end maxv_crcblock;
architecture architecture_crcblock of maxv_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for MAXV Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : maxv_asynch_lcell
--
-- Description : VHDL simulation model for the asynchnous submodule of
-- MAXV Lcell.
--
-- Outputs : Asynchnous LUT function of MAXV Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.maxv_atom_pack.all;
ENTITY maxv_asynch_lcell is
GENERIC (
lms : std_logic_vector(15 downto 0) := "1111111111111111";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
attribute VITAL_LEVEL0 of maxv_asynch_lcell : ENTITY is TRUE;
END maxv_asynch_lcell;
ARCHITECTURE vital_le of maxv_asynch_lcell is
attribute VITAL_LEVEL1 of vital_le : ARCHITECTURE is TRUE;
signal dataa_ipd : std_ulogic;
signal datab_ipd : std_ulogic;
signal datac_ipd : std_ulogic;
signal datad_ipd : std_ulogic;
signal inverta_ipd : std_ulogic;
signal cin_ipd : std_ulogic;
signal cin0_ipd : std_ulogic;
signal cin1_ipd : std_ulogic;
-- operation_mode --> mode(0) - normal=1 arithemtic=0
-- sum_lutc_cin --> mode(1) - lutc=1 cin=0
-- sum_lutc_qfbk --> mode(2) - qfbk=1 mode1=0
-- cin_used --> mode(3) - true=1 false=0
-- cin0_used --> mode(4) - true=1 false=0
-- cin1_used --> mode(5) - true=1 false=0
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
VitalWireDelay (inverta_ipd, inverta, tipd_inverta);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, mode,
cin_ipd, cin0_ipd, cin1_ipd, inverta_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_ulogic;
variable tmp_cout : std_ulogic;
variable tmp_cout0 : std_ulogic;
variable tmp_cout1 : std_ulogic;
variable tmp_regin : std_ulogic;
variable lutb : std_ulogic;
variable cintmp : std_ulogic;
variable invertsig : std_ulogic := '0';
variable cinsel : std_ulogic;
variable cinsig : std_ulogic;
variable cin01sel : std_ulogic;
variable luta : std_ulogic;
variable lutc : std_ulogic;
variable lutd : std_ulogic;
variable datacsig : std_ulogic;
variable lms_var : std_logic_vector(15 downto 0) := "1111111111111111";
begin
lms_var := lms;
cinsel := (cin_ipd and mode(3)) or
(inverta_ipd and (not mode(3)));
cin01sel := (cin1_ipd and cinsel) or
(cin0_ipd and (not cinsel));
cintmp := (cin_ipd and mode(0)) or
((not mode(0)) and mode(3) and cin_ipd) or
((not mode(0)) and (not mode(3)) and inverta_ipd);
cinsig := (cintmp and ((not mode(4)) and (not mode(5)))) or
(cin01sel and (mode(4) or mode(5)));
datacsig := (datac_ipd and mode(1)) or
(cinsig and (not mode(1)));
luta := dataa_ipd XOR inverta_ipd;
lutb := datab_ipd;
lutc := (qfbkin and mode(2)) or
(datacsig and (not mode(2)));
lutd := (datad_ipd and mode(0)) or (not mode(0));
tmp_combout := VitalMUX(data => lms_var,
dselect => (lutd,
lutc,
lutb,
luta)
);
tmp_cout0 := VitalMUX(data => lms_var,
dselect => ('0',
cin0_ipd,
lutb,
luta)
);
tmp_cout1 := VitalMUX(data => lms_var,
dselect => ('0',
cin1_ipd,
lutb,
luta)
);
tmp_cout := VitalMux2(VitalMux2(tmp_cout1,
tmp_cout0,
cin_ipd),
VitalMux2(tmp_cout1,
tmp_cout0,
inverta_ipd),
mode(3)
);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_combout, (mode(2) = '1'))),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01
(
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_regin, (mode(2) = '1'))),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => tmp_cout0,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => tmp_cout1,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_le;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : maxv_lcell_register
--
-- Description : VHDL simulation model for the register submodule of
-- MAXV Lcell.
--
-- Outputs : Registered output of MAXV Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxv_atom_pack.all;
ENTITY maxv_lcell_register is
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_regout : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_qfbkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (clk : in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
attribute VITAL_LEVEL0 of maxv_lcell_register : ENTITY is TRUE;
end maxv_lcell_register;
ARCHITECTURE vital_le_reg of maxv_lcell_register is
attribute VITAL_LEVEL1 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd : std_ulogic := '1';
signal sload_ipd : std_ulogic := '0';
signal aload_ipd : std_ulogic := '0';
signal datac_ipd : std_ulogic := '0';
signal regcascin_ipd : std_ulogic := '0';
signal clk_ipd : std_ulogic := '0';
signal aclr_ipd : std_ulogic := '0';
signal sclr_ipd : std_ulogic := '0';
constant maxv_regtab : VitalStateTableType := (
-- CLK ACLR D D1 D2 EN Aload Sclr Sload Casc Synch Qp Q
( x, H, x, x, x, x, x, x, x, x, x, x, L ), -- Areset
( x, x, x, L, x, x, H, x, x, x, x, x, L ), -- Aload
( x, x, x, H, x, x, H, x, x, x, x, x, H ), -- Aload
( x, x, x, x, x, x, H, x, x, x, x, x, U ), -- Aload
( x, x, x, x, x, L, x, x, x, x, x, x, S ), -- Q=Q
( R, x, x, x, x, H, x, H, x, x, H, x, L ), -- Sreset
( R, x, x, L, x, H, x, x, H, x, H, x, L ), -- Sload
( R, x, x, H, x, H, x, x, H, x, H, x, H ), -- Sload
( R, x, x, x, x, H, x, x, H, x, H, x, U ), -- Sload
( R, x, x, x, L, H, x, x, x, H, x, x, L ), -- Cascade
( R, x, x, x, H, H, x, x, x, H, x, x, H ), -- Cascade
( R, x, x, x, x, H, x, x, x, H, x, x, U ), -- Cascade
( R, x, L, x, x, H, x, x, x, x, H, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, H, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, H, x, U ), -- Datain
( R, x, L, x, x, H, x, x, x, x, x, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, x, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, x, x, U ), -- Datain
( x, x, x, x, x, x, x, x, x, x, x, x, S )); -- Q=Q
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (regcascin_ipd, regcascin, tipd_regcascin);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, aload_ipd, datac_ipd,
regcascin_ipd, datain, sclr_ipd, ena_ipd,
sload_ipd, cena, xonv, smode)
variable Tviol_regcascin_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_regcascin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbkout_VitalGlitchData : VitalGlitchDataType;
-- variables for 'X' generation
variable Tviolation : std_ulogic := '0';
variable tmp_regout : STD_ULOGIC := '0';
variable PreviousData : STD_LOGIC_VECTOR(0 to 10);
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_regcascin_clk,
TimingData => TimingData_regcascin_clk,
TestSignal => regcascin_ipd,
TestSignalName => "REGCASCIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_regcascin_clk_noedge_posedge,
SetupLow => tsetup_regcascin_clk_noedge_posedge,
HoldHigh => thold_regcascin_clk_noedge_posedge,
HoldLow => thold_regcascin_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr_ipd) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
end if;
-------------------------
-- Functionality Section
-------------------------
Tviolation := Tviol_regcascin_clk or Tviol_datain_clk or
Tviol_datac_clk or Tviol_ena_clk or
Tviol_sclr_clk or Tviol_sload_clk;
VitalStateTable (
Result => tmp_regout,
PreviousDataIn => PreviousData,
StateTable => maxv_regtab,
DataIn => (CLK_ipd, ACLR_ipd, datain, datac_ipd,
regcascin_ipd, ENA_ipd, aload_ipd, sclr_ipd,
sload_ipd, cena, smode)
);
tmp_regout := (xonv AND Tviolation) XOR tmp_regout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbkout,
OutSignalName => "QFBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbkout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_qfbkout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_qfbkout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_qfbkout_posedge, TRUE)),
GlitchData => qfbkout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : maxv_lcell
--
-- Description : VHDL simulation model for MAXV Lcell.
--
-- Outputs : Output of MAXV Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxv_atom_pack.all;
use work.maxv_asynch_lcell;
use work.maxv_lcell_register;
ENTITY maxv_lcell is
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "maxv_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end maxv_lcell;
ARCHITECTURE vital_le_atom of maxv_lcell is
signal dffin : std_logic;
signal qfbkin : std_logic;
signal mode : std_logic_vector(5 downto 0);
COMPONENT maxv_asynch_lcell
GENERIC (
lms : std_logic_vector(15 downto 0);
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01
);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end COMPONENT;
COMPONENT maxv_lcell_register
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (
clk :in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
end COMPONENT;
signal aclr1, xonv, cena, smode : std_logic ;
begin
aclr1 <= aclr or (not devclrn) or (not devpor);
cena <= '1' when (register_cascade_mode = "on") else '0';
xonv <= '1' when (x_on_violation = "on") else '0';
smode <= '1' when (synch_mode = "on") else '0';
mode(0) <= '1' when operation_mode = "normal" else
'0'; -- operation_mode = "arithmetic"
mode(1) <= '1' when sum_lutc_input = "datac" else
'0' ; -- sum_lutc_input = "cin"
mode(2) <= '1' when sum_lutc_input = "qfbk" else
'0'; -- sum_lutc_input = "cin" or "datac"
mode(3) <= '1' when cin_used = "true" else
'0'; -- cin_used = "false"
mode(4) <= '1' when cin0_used = "true" else
'0'; -- cin0_used = "false"
mode(5) <= '1' when cin1_used = "true" else
'0'; -- cin1_used = "false"
lecomb: maxv_asynch_lcell
GENERIC map (
lms => str_to_bin(lut_mask)
)
PORT map (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
qfbkin => qfbkin,
inverta => map_x_to_0(inverta),
cin => cin,
cin0 => cin0,
cin1 => cin1,
mode => mode,
combout => combout,
cout => cout,
cout0 => cout0,
cout1 => cout1,
regin => dffin
);
lereg: maxv_lcell_register
PORT map (
clk => clk,
datain => dffin,
datac => datac,
smode => smode,
regcascin => regcascin,
aclr => aclr1,
aload => aload,
sclr => sclr,
sload => sload,
ena => ena,
cena => cena,
xonv => xonv,
regout => regout,
qfbkout => qfbkin
);
end vital_le_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- MAXV UFM ATOM
--
--
--/////////////////////////////////////////////////////////////////////////////
-- MODULE DECLARATION
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use std.textio.all;
use work.maxv_atom_pack.all;
entity maxv_ufm is
generic (
-- PARAMETER DECLARATION
address_width : integer := 9;
init_file : string := "none";
lpm_type : string := "maxv_ufm";
mem1 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem2 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem3 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem4 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem5 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem6 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem7 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem8 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem9 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem10 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem11 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem12 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem13 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem14 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem15 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem16 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
osc_sim_setting : integer := 180000; -- default osc frequency to 5.56MHz
program_time : integer := 1600000; -- default program_time is 1600ns
erase_time : integer := 500000000; -- default erase time is 500us
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_program_busy_posedge: VitalDelayType01 := DefPropDelay01;
tpd_erase_busy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_drclk_drdout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_oscena_osc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_sbdin_sbdout : VitalDelayType01 := DefPropDelay01;
tsetup_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_program_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_erase_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_program_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_erase_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_program_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_erase_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_program_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_erase_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tipd_program : VitalDelayType01 := DefPropDelay01;
tipd_erase : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01;
tipd_arclk : VitalDelayType01 := DefPropDelay01;
tipd_arshft : VitalDelayType01 := DefPropDelay01;
tipd_ardin : VitalDelayType01 := DefPropDelay01;
tipd_drclk : VitalDelayType01 := DefPropDelay01;
tipd_drshft : VitalDelayType01 := DefPropDelay01;
tipd_drdin : VitalDelayType01 := DefPropDelay01;
tipd_sbdin : VitalDelayType01 := DefPropDelay01
);
port (
program : in std_logic := '0';
erase : in std_logic := '0';
oscena : in std_logic;
arclk : in std_logic;
arshft : in std_logic;
ardin : in std_logic;
drclk : in std_logic;
drshft : in std_logic;
drdin : in std_logic := '0';
sbdin : in std_logic := '0';
devclrn : in std_logic := '1'; -- simulation only port
devpor : in std_logic := '1'; -- simulation only port
ctrl_bgpbusy : in std_logic := '0'; -- simulation only port, to control
-- and emulate the output
-- behaviour of bgpbusy
busy : out std_logic;
osc : out std_logic := 'X';
drdout : out std_logic;
sbdout : out std_logic;
bgpbusy : out std_logic);
END maxv_ufm;
architecture behave of maxv_ufm is
-- CONSTANT DECLARATION
constant WIDTHDATA : integer := 16;
constant SECTOR0_RANGE : integer := (2**(address_width-1));
constant SECTOR_SIZE : integer := (WIDTHDATA * (2**(address_width-1)));
-- TYPE DECLARATION
type ufm_memory is array ((2**address_width)-1 downto 0) of std_logic_vector(WIDTHDATA-1 downto 0);
-- SIGNAL DECLARATION
signal addr_reg : std_logic_vector(address_width - 1 downto 0) := (OTHERS => '0');
signal data_reg : std_logic_vector((WIDTHDATA - 1) downto 0) := (OTHERS => 'X');
signal storage_output : std_logic_vector((WIDTHDATA - 1) downto 0) := (OTHERS => '1');
signal int_osc : std_logic := 'X';
signal program_pulse : std_logic := '0';
signal erase_pulse : std_logic := '0';
signal sys_busy : std_logic;
signal i : integer;
signal j : integer;
signal numwords : integer;
signal program_ipd : std_logic;
signal erase_ipd : std_logic;
signal oscena_ipd : std_logic;
signal arclk_ipd : std_logic;
signal arshft_ipd : std_logic;
signal ardin_ipd : std_logic;
signal drclk_ipd : std_logic;
signal drshft_ipd : std_logic;
signal drdin_ipd : std_logic;
signal sbdin_ipd : std_logic;
signal program_reg : std_logic;
signal erase_reg : std_logic;
signal busy_tmp : std_logic;
-- FUNCTION DECLARATION
-- convert std_logic_vector to integer
function convert_to_int(arg : in std_logic_vector) return integer is
variable result : integer := 0;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end convert_to_int;
begin
bgpbusy <= ctrl_bgpbusy; -- No delay necessary as for simulation only
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (program_ipd, program, tipd_program);
VitalWireDelay (erase_ipd, erase, tipd_erase);
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
VitalWireDelay (arclk_ipd, arclk, tipd_arclk);
VitalWireDelay (arshft_ipd, arshft, tipd_arshft);
VitalWireDelay (ardin_ipd, ardin, tipd_ardin);
VitalWireDelay (drclk_ipd, drclk, tipd_drclk);
VitalWireDelay (drshft_ipd, drshft, tipd_drshft);
VitalWireDelay (drdin_ipd, drdin, tipd_drdin);
VitalWireDelay (sbdin_ipd, sbdin, tipd_sbdin);
end block;
VITAL_sbdin : process (sbdin_ipd)
variable sbdout_tmp : std_logic;
variable sbdout_VitalGlitchData : VitalGlitchDataType;
begin
sbdout <= sbdin_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => sbdout,
OutSignalName => "SBDOUT",
OutTemp => sbdout_tmp,
Paths => (0 => (sbdin_ipd'last_event, tpd_sbdin_sbdout, TRUE)),
GlitchData => sbdout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Produce oscillation clock to UFM
VITAL_oscena : process (oscena_ipd, int_osc)
variable osc_VitalGlitchData : VitalGlitchDataType;
variable first_warning : boolean := true;
variable TOSCMN_PW : time := 90000 ps; --pulse width of osc - default to 1/2 of osc period
variable need_init : boolean := true;
begin
if (need_init = true) then
if (osc_sim_setting /= 0) then
TOSCMN_PW := (osc_sim_setting / 2) * 1 ps;
need_init := false;
end if;
end if;
if (oscena_ipd = '1') then
if (first_warning = true) then
assert FALSE
report "UFM oscillator can operate at any frequency between 3.33MHz to 5.56Mhz."
severity NOTE;
first_warning := false;
end if;
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after TOSCMN_PW;
else
int_osc <= '0' after TOSCMN_PW;
end if;
else
int_osc <= '1' after TOSCMN_PW;
end if;
VitalPathDelay01 (
OutSignal => osc,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_osc_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Shift address from LSB to MSB when arshft is '1'; else increment address.
-- (Using block statement to avoid race condition warning; therefore, the
-- order of assignments must be taken care to ensure correct behaviour)
VITAL_arclk : process (arclk_ipd, arshft_ipd, ardin_ipd, sys_busy, devclrn, devpor)
variable addr_reg_var : std_logic_vector(address_width-1 downto 0) := (OTHERS => '0');
variable Tviol_arshft_arclk : std_ulogic := '0';
variable Tviol_ardin_arclk : std_ulogic := '0';
variable TimingData_arshft_arclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ardin_arclk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- setup and hold time verification on ARSHFT
VitalSetupHoldCheck (
Violation => Tviol_arshft_arclk,
TimingData => TimingData_arshft_arclk,
TestSignal => arshft_ipd,
TestSignalName => "arshft",
RefSignal => arclk_ipd,
RefSignalName => "arclk",
SetupHigh => tsetup_arshft_arclk_noedge_posedge,
SetupLow => tsetup_arshft_arclk_noedge_posedge,
HoldHigh => thold_arshft_arclk_noedge_posedge,
HoldLow => thold_arshft_arclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Arshft VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setup and hold time verification on ARDIN
VitalSetupHoldCheck (
Violation => Tviol_ardin_arclk,
TimingData => TimingData_ardin_arclk,
TestSignal => ardin_ipd,
TestSignalName => "ardin",
RefSignal => arclk_ipd,
RefSignalName => "arclk",
SetupHigh => tsetup_ardin_arclk_noedge_posedge,
SetupLow => tsetup_ardin_arclk_noedge_posedge,
HoldHigh => thold_ardin_arclk_noedge_posedge,
HoldLow => thold_ardin_arclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Ardin VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
-- The behaviour of ARSHFT and ARDIN
if ((devpor = '0') or (devclrn = '0')) then
addr_reg_var := (OTHERS => '0');
elsif (arclk_ipd'event and arclk_ipd = '1' and sys_busy = '0') then
if (address_width /= 9) then
assert false
report "address_width parameter must be equal to 9."
severity error;
end if;
if (arshft_ipd = '1') then
for i in address_width-1 downto 1 loop
addr_reg_var(i) := addr_reg(i-1);
end loop;
addr_reg_var(0) := ardin_ipd;
else
addr_reg_var := addr_reg_var + '1';
end if;
end if;
addr_reg <= addr_reg_var;
end process;
-- Shift data from LSB to MSB when drshft is '1'; else load new data.
VITAL_drclk : process (drclk_ipd, drshft_ipd, drdin_ipd, sys_busy, devclrn, devpor)
variable drdout_tmp : std_logic;
variable data_reg_var : std_logic_vector((WIDTHDATA - 1) downto 0) := (OTHERS => 'X');
variable Tviol_drshft_drclk : std_ulogic := '0';
variable Tviol_drdin_drclk : std_ulogic := '0';
variable TimingData_drshft_drclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_drdin_drclk : VitalTimingDataType := VitalTimingDataInit;
variable drdout_VitalGlitchData : VitalGlitchDataType;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- setup and hold time verification on DRSHFT
VitalSetupHoldCheck (
Violation => Tviol_drshft_drclk,
TimingData => TimingData_drshft_drclk,
TestSignal => drshft_ipd,
TestSignalName => "drshft",
RefSignal => drclk_ipd,
RefSignalName => "drclk",
SetupHigh => tsetup_drshft_drclk_noedge_posedge,
SetupLow => tsetup_drshft_drclk_noedge_posedge,
HoldHigh => thold_drshft_drclk_noedge_posedge,
HoldLow => thold_drshft_drclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Drshft VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setup and hold time verification on DRDIN
VitalSetupHoldCheck (
Violation => Tviol_drdin_drclk,
TimingData => TimingData_drdin_drclk,
TestSignal => drdin_ipd,
TestSignalName => "drdin",
RefSignal => drclk_ipd,
RefSignalName => "drclk",
SetupHigh => tsetup_drdin_drclk_noedge_posedge,
SetupLow => tsetup_drdin_drclk_noedge_posedge,
HoldHigh => thold_drdin_drclk_noedge_posedge,
HoldLow => thold_drdin_drclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Drdin VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
-- The behaviour of DRSHFT and DRDIN
if ((devpor = '0') or (devclrn = '0')) then
data_reg_var := (OTHERS => '0');
elsif (drclk_ipd'EVENT AND drclk_ipd = '1' and sys_busy = '0') then
if (drshft_ipd = '1') then
for j in WIDTHDATA-1 downto 1 loop
data_reg_var(j) := data_reg(j - 1);
end loop;
data_reg_var(0) := drdin_ipd;
else
data_reg_var := storage_output;
end if;
end if;
data_reg <= data_reg_var;
drdout_tmp := data_reg_var((WIDTHDATA - 1));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => drdout,
OutSignalName => "drdout",
OutTemp => drdout_tmp,
Paths => (0 => (InputChangeTime => drclk_ipd'last_event,
PathDelay => tpd_drclk_drdout_posedge,
PathCondition => (drclk_ipd = '1'))),
GlitchData => drdout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
REG_PROG_ERASE : process (int_osc)
begin
if(int_osc'event and int_osc = '1') then
program_reg <= program_ipd;
erase_reg <= erase_ipd;
end if;
end process;
VITAL_program_erase : process (program_ipd, erase_ipd, program_reg, erase_reg, drclk_ipd, arclk_ipd, oscena_ipd)
variable Tviol_erase_arclk : std_ulogic := '0';
variable Tviol_program_drclk : std_ulogic := '0';
variable Tviol_oscena_program : std_ulogic := '0';
variable Tviol_oscena_erase : std_ulogic := '0';
variable TimingData_erase_arclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_program_drclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_oscena_erase : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_oscena_program : VitalTimingDataType := VitalTimingDataInit;
variable TPPMX : time := 1600000 ps;
variable TEPMX : time := 500000000 ps;
variable need_init: boolean := true;
begin
if (need_init = true) then
if (program_time /= 0) then
TPPMX := (program_time * 1 ps);
end if;
if (erase_time /= 0) then
TEPMX := (erase_time/1000) * 1 ps;
end if;
need_init := false;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- hold time verification on DRCLK
VitalSetupHoldCheck (
Violation => Tviol_program_drclk,
TimingData => TimingData_program_drclk,
TestSignal => program_ipd,
TestSignalName => "program",
RefSignal => drclk_ipd,
RefSignalName => "drclk",
HoldHigh => thold_program_drclk_noedge_posedge,
HoldLow => thold_program_drclk_noedge_posedge,
RefTransition => '/',
HeaderMsg => "/UFM Program to Drclk VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- hold time verification on ARCLK
VitalSetupHoldCheck (
Violation => Tviol_erase_arclk,
TimingData => TimingData_erase_arclk,
TestSignal => erase_ipd,
TestSignalName => "erase",
RefSignal => arclk_ipd,
RefSignalName => "arclk",
HoldHigh => thold_erase_arclk_noedge_posedge,
HoldLow => thold_erase_arclk_noedge_posedge,
RefTransition => '/',
HeaderMsg => "/UFM Erase to Arclk VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setuphold check for oscena vs program
VitalSetupHoldCheck (
Violation => Tviol_oscena_program,
TimingData => TimingData_oscena_program,
TestSignal => oscena_ipd,
TestSignalName => "oscena",
RefSignal => program_ipd,
RefSignalName => "program",
SetupHigh => tsetup_oscena_program_noedge_posedge,
SetupLow => tsetup_oscena_program_noedge_posedge,
HoldHigh => thold_oscena_program_noedge_negedge,
HoldLow => thold_oscena_program_noedge_negedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM OSCENA to PROGRAM VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setuphold check for oscena vs erase
VitalSetupHoldCheck (
Violation => Tviol_oscena_erase,
TimingData => TimingData_oscena_erase,
TestSignal => oscena_ipd,
TestSignalName => "oscena",
RefSignal => erase_ipd,
RefSignalName => "erase",
SetupHigh => tsetup_oscena_erase_noedge_posedge,
SetupLow => tsetup_oscena_erase_noedge_posedge,
HoldHigh => thold_oscena_erase_noedge_negedge,
HoldLow => thold_oscena_erase_noedge_negedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM OSCENA to ERASE VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
-- Pulse to indicate programming UFM for maxinum time of
-- TPPMX
if (program_reg'event and program_reg = '1') then
if (sys_busy = '0' and program_pulse = '0') then
program_pulse <= '1';
program_pulse <= transport '0' after TPPMX;
end if;
elsif (erase_reg'event and erase_reg = '1') then
-- Pulse to indicate erasing UFM for maxinum time of
-- TEPMX
if (sys_busy = '0' and erase_pulse = '0') then
erase_pulse <= '1';
erase_pulse <= transport '0' after (TEPMX * 1000);
end if;
end if;
end process;
-- Insert timing delay for Erase and Program to Busy
VITAL_pulse : process(program_pulse, erase_pulse, program_ipd, erase_ipd, busy_tmp)
variable Tviol_program_busy : std_ulogic := '0';
variable Tviol_erase_busy : std_ulogic := '0';
variable TimingData_program_busy : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_erase_busy : VitalTimingDataType := VitalTimingDataInit;
variable busy_VitalGlitchData : VitalGlitchDataType;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- hold time verification on PROGRAM from BUSY's falling edge
VitalSetupHoldCheck (
Violation => Tviol_program_busy,
TimingData => TimingData_program_busy,
TestSignal => program_ipd,
TestSignalName => "program",
RefSignal => busy_tmp,
RefSignalName => "busy",
HoldHigh => thold_program_busy_noedge_negedge,
HoldLow => thold_program_busy_noedge_negedge,
RefTransition => '/',
HeaderMsg => "/UFM Busy to Program VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- hold time verification on ERASE from BUSY's falling edge
VitalSetupHoldCheck (
Violation => Tviol_erase_busy,
TimingData => TimingData_erase_busy,
TestSignal => erase_ipd,
TestSignalName => "erase",
RefSignal => busy_tmp,
RefSignalName => "busy",
HoldHigh => thold_erase_busy_noedge_negedge,
HoldLow => thold_erase_busy_noedge_negedge,
RefTransition => '/',
HeaderMsg => "/UFM Busy to Erase VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
sys_busy <= busy_tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => busy,
OutSignalName => "busy",
OutTemp => busy_tmp,
Paths => (0 => (InputChangeTime => erase_ipd'last_event,
PathDelay => tpd_erase_busy_posedge,
PathCondition => (erase_pulse = '1')),
1 => (InputChangeTime => program_ipd'last_event,
PathDelay => tpd_program_busy_posedge,
PathCondition => (program_pulse = '1'))),
GlitchData => busy_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
VITAL_busy : process(program_pulse, erase_pulse)
begin
busy_tmp <= program_pulse or erase_pulse;
end process;
-- MEMORY PROCESSING BLOCK
MEMORY: process(program_pulse, erase_pulse, addr_reg)
variable ufm_storage : ufm_memory; -- UFM sector0 and sector1
variable ufm_initf_sec0 : std_logic_vector((SECTOR_SIZE-1) downto 0) := (OTHERS=>'1');
variable ufm_initf_sec1 : std_logic_vector((SECTOR_SIZE-1) downto 0) := (OTHERS=>'1');
variable init_word0 : std_logic_vector ((WIDTHDATA - 1) downto 0);
variable init_word1 : std_logic_vector ((WIDTHDATA - 1) downto 0);
variable storage_init : boolean := false;
variable i : integer := 0;
variable k : integer := 0;
variable mem_cnt : integer := 0;
variable bit_cnt : integer := 0;
begin
-- INITIALIZE --
if NOT(storage_init) then
-- INITIALIZE TO 1; UFM content is initially all 1's
for i in ufm_storage'low to ufm_storage'high loop
ufm_storage(i) := (OTHERS => '1');
end loop;
if (init_file = "none") then
assert FALSE
report "Not using any memory initialization file."
severity WARNING;
else
-- initialize UFM from memory initialization file (*.mif or *.hex)
-- the contents of the memory initialization file are passed in via the
-- mem* parameters
ufm_initf_sec0(SECTOR_SIZE-1 downto 0) := (mem8 & mem7 & mem6 & mem5 &
mem4 & mem3 & mem2 & mem1);
ufm_initf_sec1(SECTOR_SIZE-1 downto 0) := (mem16 & mem15 & mem14 & mem13 &
mem12 & mem11 & mem10 & mem9);
for mem_cnt in 1 to SECTOR0_RANGE loop
for bit_cnt in 0 to (WIDTHDATA-1) loop
init_word0(bit_cnt) := ufm_initf_sec0(((mem_cnt-1)*WIDTHDATA) + bit_cnt);
init_word1(bit_cnt) := ufm_initf_sec1(((mem_cnt-1)*WIDTHDATA) + bit_cnt);
end loop;
ufm_storage(mem_cnt-1) := init_word0;
ufm_storage((mem_cnt-1) + SECTOR0_RANGE) := init_word1;
end loop;
end if;
storage_init := TRUE;
end if; -- if NOT(storage_init)
-- MEMORY FUNCTION --
-- Programming data into the UFM
if (program_pulse'EVENT and program_pulse = '1') then
ufm_storage(convert_to_int(addr_reg)) := data_reg and
ufm_storage(convert_to_int(addr_reg));
elsif (erase_pulse'EVENT and erase_pulse = '1') then
-- Erasing data from selected sector of UFM
if (addr_reg(address_width - 1) = '0') then
for k in 0 to (SECTOR0_RANGE - 1) loop
ufm_storage(k) := (others => '1');
end loop;
else
for k in SECTOR0_RANGE to (SECTOR0_RANGE * 2 - 1) loop
ufm_storage(k) := (others => '1');
end loop;
end if;
end if;
storage_output <= ufm_storage(convert_to_int(addr_reg)) ;
end process; -- memory
END behave;
--
--
-- MAXV_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxv_atom_pack.all;
entity maxv_io is
generic(
lpm_type : STRING := "maxv_io";
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01
);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
padio : inout STD_LOGIC;
combout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of maxv_io : entity is TRUE;
end maxv_io;
architecture behave of maxv_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal oe_ipd : std_logic;
signal padio_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_logic;
variable tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
begin
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --for autotest
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
---------------------------------------------------------------------
--
-- Entity Name : maxv_routing_wire
--
-- Description : StratixII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxv_atom_pack.all;
ENTITY maxv_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of maxv_routing_wire : entity is TRUE;
end maxv_routing_wire;
ARCHITECTURE behave of maxv_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
| gpl-3.0 | 2c5fc52c9cdda153efe5b3b6273f126a | 0.500346 | 4.084748 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriagx_hssi_components.vhd | 1 | 66,224 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package ARRIAGX_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- arriagx_hssi_refclk_divider
--
COMPONENT arriagx_hssi_refclk_divider
GENERIC (
enable_divider : STRING := "true";
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
refclk_coupling_termination : STRING := "dc_coupling_external_termination"; -- new in 5.1 SP1
dprio_config_mode : INTEGER := 0; -- 6.1
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
inclk : IN STD_LOGIC;
dprioin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
--
-- arriagx_hssi_cmu_clock_divider
--
COMPONENT arriagx_hssi_cmu_clock_divider
GENERIC (
inclk_select : integer := 0;
use_vco_bypass : string := "false";
use_digital_refclk_post_divider : string := "false";
use_coreclk_out_post_divider : string := "false";
divide_by : integer := 4;
enable_refclk_out : string := "true";
enable_pclk_x8_out : string := "false";
select_neighbor_pclk : string := "false";
coreclk_out_gated_by_quad_reset: string := "false";
select_refclk_dig : string := "false";
dprio_config_mode : INTEGER := 0; -- 6.1
tipd_clk : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pclkin : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayArrayType01(29 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_powerdn : VitalDelayType01 := DefPropDelay01;
tipd_quadreset : VitalDelayType01 := DefPropDelay01;
tipd_refclkdig : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanshift : VitalDelayType01 := DefPropDelay01;
tipd_scanmode : VitalDelayType01 := DefPropDelay01;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_clk_coreclkout : VitalDelayType01 := DefPropDelay01;
tpd_clk_pclkx8out : VitalDelayType01 := DefPropDelay01;
tpd_pclkin_coreclkout : VitalDelayType01 := DefPropDelay01;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_digitalrefclkout_phase_shift : INTEGER := 0;
sim_pclkx8out_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
pclkin : IN STD_LOGIC := '0';
dprioin : IN STD_LOGIC_VECTOR(29 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN STD_LOGIC := '1';
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
refclkdig : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS => '0');
scanshift : IN STD_LOGIC := '0';
scanmode : IN STD_LOGIC := '0';
vcobypassin : IN STD_LOGIC := '0';
analogrefclkout : OUT STD_LOGIC;
analogfastrefclkout : OUT STD_LOGIC;
digitalrefclkout : OUT STD_LOGIC;
pclkx8out : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(29 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0));
END COMPONENT;
--
-- arriagx_hssi_calibration_block
--
COMPONENT arriagx_hssi_calibration_block
GENERIC (
use_continuous_calibration_mode: string := "false";
rx_calibration_write_test_value: integer := 0;
tx_calibration_write_test_value: integer := 0;
enable_rx_calibration_test_write: string := "false";
enable_tx_calibration_test_write: string := "false";
send_rx_calibration_status : string := "true");
PORT (
clk : IN std_logic := '0';
powerdn : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;
--
-- arriagx_hssi_cmu_pll
--
COMPONENT arriagx_hssi_cmu_pll
GENERIC (
inclk0_period : INTEGER := 0; -- time period in ps
inclk1_period : INTEGER := 0;
inclk2_period : INTEGER := 0;
inclk3_period : INTEGER := 0;
inclk4_period : INTEGER := 0;
inclk5_period : INTEGER := 0;
inclk6_period : INTEGER := 0;
inclk7_period : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
multiply_by : INTEGER := 1;
divide_by : INTEGER := 1;
low_speed_test_sel : INTEGER := 0;
pll_type : STRING := "normal"; -- normal,fast,auto
charge_pump_current_test_enable : INTEGER := 0;
vco_range : STRING := "low";
loop_filter_resistor_control : INTEGER := 0;
loop_filter_ripple_capacitor_control : INTEGER := 0;
use_default_charge_pump_current_selection : STRING := "false";
use_default_charge_pump_supply_vccm_vod_control : STRING := "false";
pll_number : INTEGER := 0; -- PLL 0-2
charge_pump_current_control : INTEGER := 0;
up_down_control_percent : INTEGER := 0;
charge_pump_tristate_enable : STRING := "false";
enable_pll_cascade : STRING := "false"; -- 6.1
dprio_config_mode : INTEGER := 0; -- 6.1
protocol_hint : STRING := "basic"; -- 6.1
remapped_to_new_loop_filter_charge_pump_settings : STRING := "false";
tipd_clk : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_pllreset : VitalDelayType01 := DefPropDelay01;
tipd_pllpowerdn : VitalDelayType01 := DefPropDelay01;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0
);
PORT (
clk : IN std_logic_vector(7 DOWNTO 0);
dprioin : IN std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN std_logic := '1';
pllreset : IN std_logic := '0';
pllpowerdn : IN std_logic := '0';
clkout : OUT std_logic;
locked : OUT std_logic;
dprioout : OUT std_logic_vector(39 DOWNTO 0);
fbclkout : OUT std_logic;
vcobypassout : OUT std_logic);
END COMPONENT;
--
-- arriagx_hssi_central_management_unit
--
COMPONENT arriagx_hssi_central_management_unit
GENERIC (
in_xaui_mode : string := "false";
portaddr : integer := 1; -- 1-based
devaddr : integer := 1; -- 1-based
bonded_quad_mode : string := "none";
use_deskew_fifo : string := "false";
num_con_errors_for_align_loss : integer := 2;
num_con_good_data_for_align_approach: integer := 3;
num_con_align_chars_for_align : integer := 4;
offset_all_errors_align : string := "false";
dprio_config_mode : INTEGER := 0; -- 6.1
rx_dprio_width : INTEGER := 800; -- 6.1
tx_dprio_width : INTEGER := 400; -- 6.1
lpm_type : string := "arriagx_hssi_central_management_unit";
rx0_cru_clock0_physical_mapping: string := "refclk0";
rx0_cru_clock1_physical_mapping: string := "refclk1";
rx0_cru_clock2_physical_mapping: string := "iq0";
rx0_cru_clock3_physical_mapping: string := "iq1";
rx0_cru_clock4_physical_mapping: string := "iq2";
rx0_cru_clock5_physical_mapping: string := "iq3";
rx0_cru_clock6_physical_mapping: string := "iq4";
rx0_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx0_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx1_cru_clock0_physical_mapping: string := "refclk0";
rx1_cru_clock1_physical_mapping: string := "refclk1";
rx1_cru_clock2_physical_mapping: string := "iq0";
rx1_cru_clock3_physical_mapping: string := "iq1";
rx1_cru_clock4_physical_mapping: string := "iq2";
rx1_cru_clock5_physical_mapping: string := "iq3";
rx1_cru_clock6_physical_mapping: string := "iq4";
rx1_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx1_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx2_cru_clock0_physical_mapping: string := "refclk0";
rx2_cru_clock1_physical_mapping: string := "refclk1";
rx2_cru_clock2_physical_mapping: string := "iq0";
rx2_cru_clock3_physical_mapping: string := "iq1";
rx2_cru_clock4_physical_mapping: string := "iq2";
rx2_cru_clock5_physical_mapping: string := "iq3";
rx2_cru_clock6_physical_mapping: string := "iq4";
rx2_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx2_cru_clock8_physical_mapping: string := "cmu_div_clk";
rx3_cru_clock0_physical_mapping: string := "refclk0";
rx3_cru_clock1_physical_mapping: string := "refclk1";
rx3_cru_clock2_physical_mapping: string := "iq0";
rx3_cru_clock3_physical_mapping: string := "iq1";
rx3_cru_clock4_physical_mapping: string := "iq2";
rx3_cru_clock5_physical_mapping: string := "iq3";
rx3_cru_clock6_physical_mapping: string := "iq4";
rx3_cru_clock7_physical_mapping: string := "pld_cru_clk";
rx3_cru_clock8_physical_mapping: string := "cmu_div_clk";
tx0_pll_fast_clk0_physical_mapping: string := "pll0";
tx0_pll_fast_clk1_physical_mapping: string := "pll1";
tx1_pll_fast_clk0_physical_mapping: string := "pll0";
tx1_pll_fast_clk1_physical_mapping: string := "pll1";
tx2_pll_fast_clk0_physical_mapping: string := "pll0";
tx2_pll_fast_clk1_physical_mapping: string := "pll1";
tx3_pll_fast_clk0_physical_mapping: string := "pll0";
tx3_pll_fast_clk1_physical_mapping: string := "pll1";
pll0_inclk0_logical_to_physical_mapping: string := "iq0";
pll0_inclk1_logical_to_physical_mapping: string := "iq1";
pll0_inclk2_logical_to_physical_mapping: string := "iq2";
pll0_inclk3_logical_to_physical_mapping: string := "iq3";
pll0_inclk4_logical_to_physical_mapping: string := "iq4";
pll0_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll0_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll0_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
pll1_inclk0_logical_to_physical_mapping: string := "iq0";
pll1_inclk1_logical_to_physical_mapping: string := "iq1";
pll1_inclk2_logical_to_physical_mapping: string := "iq2";
pll1_inclk3_logical_to_physical_mapping: string := "iq3";
pll1_inclk4_logical_to_physical_mapping: string := "iq4";
pll1_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll1_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll1_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
pll2_inclk0_logical_to_physical_mapping: string := "iq0";
pll2_inclk1_logical_to_physical_mapping: string := "iq1";
pll2_inclk2_logical_to_physical_mapping: string := "iq2";
pll2_inclk3_logical_to_physical_mapping: string := "iq3";
pll2_inclk4_logical_to_physical_mapping: string := "iq4";
pll2_inclk5_logical_to_physical_mapping: string := "pld_clk";
pll2_inclk6_logical_to_physical_mapping: string := "clkrefclk0";
pll2_inclk7_logical_to_physical_mapping: string := "clkrefclk1";
cmu_divider_inclk0_physical_mapping: string := "pll0";
cmu_divider_inclk1_physical_mapping: string := "pll1";
cmu_divider_inclk2_physical_mapping: string := "pll2";
rx0_logical_to_physical_mapping: integer := 0;
rx1_logical_to_physical_mapping: integer := 1;
rx2_logical_to_physical_mapping: integer := 2;
rx3_logical_to_physical_mapping: integer := 3;
tx0_logical_to_physical_mapping: integer := 0;
tx1_logical_to_physical_mapping: integer := 1;
tx2_logical_to_physical_mapping: integer := 2;
tx3_logical_to_physical_mapping: integer := 3;
pll0_logical_to_physical_mapping: integer := 0;
pll1_logical_to_physical_mapping: integer := 1;
pll2_logical_to_physical_mapping: integer := 2;
refclk_divider0_logical_to_physical_mapping: integer := 0;
refclk_divider1_logical_to_physical_mapping: integer := 1;
sim_dump_dprio_internal_reg_at_time: integer := 0;
sim_dump_filename: string := "sim_dprio_dump.txt";
analog_test_bus_enable: string := "false";
bypass_bandgap: string := "true";
central_test_bus_select: integer := 5;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_dpclk: VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable: VitalDelayType01 := DefpropDelay01;
tipd_dprioin: VitalDelayType01 := DefpropDelay01;
tipd_dprioload: VitalDelayType01 := DefpropDelay01;
tipd_fixedclk: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_quadenable: VitalDelayType01 := DefpropDelay01;
tipd_quadreset: VitalDelayType01 := DefpropDelay01;
tipd_rxanalogreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxclk: VitalDelayType01 := DefpropDelay01;
tipd_rxdigitalreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxpowerdown: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_txclk: VitalDelayType01 := DefpropDelay01;
tipd_txdigitalreset: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
adet : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
cmudividerdprioin : IN std_logic_vector(29 DOWNTO 0) := (OTHERS => '0');
cmuplldprioin : IN std_logic_vector(119 DOWNTO 0) := (OTHERS => '0');
dpclk : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic := '0';
dprioload : IN std_logic := '0';
fixedclk : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
quadenable : IN std_logic := '1';
quadreset : IN std_logic := '0';
rdalign : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rdenablesync : IN std_logic := '1';
recovclk : IN std_logic := '0';
refclkdividerdprioin : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
rxanalogreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxclk : IN std_logic := '0';
rxctrl : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdatain : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxdprioin : IN std_logic_vector(rx_dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
rxpowerdown : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
syncstatus : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txclk : IN std_logic := '0';
txctrl : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txdatain : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
txdigitalreset : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
txdprioin : IN std_logic_vector(tx_dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
alignstatus : OUT std_logic;
clkdivpowerdn : OUT std_logic;
cmudividerdprioout : OUT std_logic_vector(29 DOWNTO 0);
cmuplldprioout : OUT std_logic_vector(119 DOWNTO 0);
dpriodisableout : OUT std_logic;
dpriooe : OUT std_logic;
dprioout : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic;
pllresetout : OUT std_logic_vector(2 DOWNTO 0);
pllpowerdn : OUT std_logic_vector(2 DOWNTO 0);
quadresetout : OUT std_logic;
refclkdividerdprioout : OUT std_logic_vector(1 DOWNTO 0);
rxadcepowerdn : OUT std_logic_vector(3 DOWNTO 0);
rxadceresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxcruresetout : OUT std_logic_vector(3 DOWNTO 0);
rxcrupowerdn : OUT std_logic_vector(3 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0);
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdprioout : OUT std_logic_vector(rx_dprio_width - 1 DOWNTO 0);
rxibpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0);
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
txdetectrxpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txdividerpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txobpowerdn : OUT std_logic_vector(3 DOWNTO 0);
txdprioout : OUT std_logic_vector(tx_dprio_width - 1 DOWNTO 0);
digitaltestout : OUT std_logic_vector(9 DOWNTO 0)
);
END COMPONENT;
--
-- arriagx_hssi_receiver
--
COMPONENT arriagx_hssi_receiver
GENERIC (
adaptive_equalization_mode : string := "none"; -- <continuous/stopped/none>;
align_loss_sync_error_num : integer := 4; -- <integer 0-7>;// wordalign
align_ordered_set_based : string := "false"; -- <true/false>;
align_pattern : string := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : integer := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only: string := "false"; -- <true/false>;
allow_align_polarity_inversion : string := "false"; -- <true/false>;
allow_pipe_polarity_inversion : string := "false"; -- <true/false>;
allow_serial_loopback : string := "false"; -- <true/false>;
bandwidth_mode : integer := 0; -- <integer 0-3>;
bit_slip_enable : string := "false"; -- <true/false>;
byte_order_pad_pattern : string := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : string := "0101111100"; -- <10-bit binary string>;
byte_ordering_mode : string := "none"; -- <none/pattern-based/syncstatus-based>;
channel_number : integer := 0; -- <integer 0-3>;
channel_bonding : string := "none"; -- <none, x4, x8>;
channel_width : integer := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : string := "recvd_clk"; -- <recvd_clk, master_clk, local_refclk, digital_refclk>;
clk2_mux_select : string := "recvd_clk"; -- <recvd_clk, local_refclk, digital_refclk, core_clk>;
cru_clock_select : integer := 0; -- <CRUCLK<n> where n is 0 through 7 >
cru_divide_by : integer := 1; -- <1,2,4>;
cru_multiply_by : integer := 10; -- <1,2,4,5,8,10,16,20,25>;
cru_pre_divide_by : integer := 1; -- <1,2,4,8>;
cruclk0_period : integer := 10000; -- in ps
cruclk1_period : integer := 10000; -- in ps
cruclk2_period : integer := 10000; -- in ps
cruclk3_period : integer := 10000; -- in ps
cruclk4_period : integer := 10000; -- in ps
cruclk5_period : integer := 10000; -- in ps
cruclk6_period : integer := 10000; -- in ps
cruclk7_period : integer := 10000; -- in ps
datapath_protocol : string := "basic"; -- <basic/pipe/xaui>;
dec_8b_10b_compatibility_mode : string := "true"; -- <true/false>;
dec_8b_10b_mode : string := "none"; -- <normal/cascaded/none>;
deskew_pattern : string := "1100111100"; -- K28.3
disable_auto_idle_insertion : string := "false"; -- <true/false>;
disable_ph_low_latency_mode : string := "false"; -- <true/false>;
disable_running_disp_in_word_align: string := "false"; -- <true/false>;
disallow_kchar_after_pattern_ordered_set: string := "false"; -- <true/false>;
dprio_mode : string := "none"; -- <none/pma_electricals/full>;
enable_bit_reversal : string := "false"; -- <true/false>;
enable_byte_order_control_sig : string := "false"; -- <true/false>;
enable_dc_coupling : string := "false"; -- <true/false>;
enable_deep_align : string := "false"; -- <true/false>;
enable_deep_align_byte_swap : string := "false"; -- <true/false>;
enable_lock_to_data_sig : string := "false"; -- <true/false>;
enable_lock_to_refclk_sig : string := "true"; -- <true/false>;
enable_self_test_mode : string := "false"; -- <true/false>;
enable_true_complement_match_in_word_align: string := "true"; -- <true/false>;
eq_adapt_seq_control : integer := 0; -- <integer 0-3>;
eq_max_gradient_control : integer := 0; -- <integer 0-7>;
equalizer_ctrl_a : integer := 0; -- <integer 0-7>;
equalizer_ctrl_b : integer := 0; -- < integer 0-7>;
equalizer_ctrl_c : integer := 0; -- < integer 0-7>;
equalizer_ctrl_d : integer := 0; -- < integer 0-7>;
equalizer_ctrl_v : integer := 0; -- < integer 0-7>;
equalizer_dc_gain : integer := 0; -- <integer 0-3>;
force_freq_det_high : string := "false"; -- <true/false>;
force_freq_det_low : string := "false"; -- <true/false>;
force_signal_detect : string := "false"; -- <true/false>;
force_signal_detect_dig : string := "false"; -- <true/false>;
ignore_lock_detect : string := "false"; -- <true/false>;
infiniband_invalid_code : integer := 0; -- <integer 0-3>;
insert_pad_on_underflow : string := "false";
num_align_code_groups_in_ordered_set: integer := 1; -- <integer 0-3>;
num_align_cons_good_data : integer := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : integer := 4; -- <Integer 1-256>;
phystatus_reset_toggle : string := "false"; -- new in 6.0 - default false
ppmselect : integer := 20; -- <integer 0-63>;
prbs_all_one_detect : string := "false"; -- <true/false>;
rate_match_almost_empty_threshold: integer := 11; -- <integer 0-15>;
rate_match_almost_full_threshold: integer := 13; -- <integer 0-15>;
rate_match_back_to_back : string := "false"; -- <true/false>;
rate_match_fifo_mode : string := "none"; -- <normal/cascaded/generic/cascaded_generic/none>;
rate_match_ordered_set_based : string := "false";
rate_match_pattern_size : integer := 10; -- <integer 10 or 20>;
rate_match_pattern1 : string := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : string := "00000000000010111100"; -- <20-bit binary string>;
rate_match_skip_set_based : string := "false"; -- <true/false>;
rd_clk_mux_select : string := "int_clk"; -- <int_clk, core_clk>;
recovered_clk_mux_select : string := "recvd_clk"; -- <recvd_clk, local_refclk, digital_refclk>;
reset_clock_output_during_digital_reset: string := "false"; -- <true/false>;
run_length : integer := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : string := "false"; -- <true/false>;
rx_detect_bypass : string := "false";
self_test_mode : string := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
send_direct_reverse_serial_loopback: string := "false"; -- <true/false>;
signal_detect_threshold : integer := 0; -- <integer 0-7 (actual values determined after PE char)>;
termination : string := "OCT_100_OHMS"; -- new in 5.1 SP1
use_align_state_machine : string := "false"; -- <true/false>;
use_deserializer_double_data_mode: string := "false"; -- <true/false>;
use_deskew_fifo : string := "false"; -- <true/false>;
use_double_data_mode : string := "false"; -- <true/false>;
use_parallel_loopback : string := "false"; -- <true/false>;
use_rate_match_pattern1_only : string := "false"; -- <true/false>;
use_rising_edge_triggered_pattern_align: string := "false"; -- <true/false>;
common_mode : string := "0.9V"; -- new in 5.1 SP1
loop_filter_resistor_control : integer := 0; -- new in 6.0;
loop_filter_ripple_capacitor_control : integer := 0; -- new in 6.0;
pd_mode_charge_pump_current_control : integer := 0; -- new in 6.0;
signal_detect_hysteresis_enabled : string := "false"; -- new in 5.1 SP1
single_detect_hysteresis_enabled : string := "false"; -- new in 5.1 SP1 - used in code
use_termvoltage_signal : string := "true"; -- new in 5.1 SP1
vco_range : string := "high"; -- new in 6.0
sim_offset_cycle_count : integer := 10; -- new in 7.1 for adce
protocol_hint : string := "basic"; -- new in 6.0
dprio_config_mode : INTEGER := 0; -- 6.1
dprio_width : INTEGER := 200; -- 6.1
allow_vco_bypass : string := "false"; -- <true/false>
charge_pump_current_control : integer := 0; -- <integer 0-3>;
up_dn_mismatch_control : integer := 0; -- <integer 0-3>;
charge_pump_test_enable : string := "false"; -- <true/false>;
charge_pump_current_test_control_pos: string := "false"; -- <true/false>
charge_pump_tristate_enable : string := "false"; -- <true/false>;
low_speed_test_select : integer := 0; -- <integer 0-15>;
cru_clk_sel_during_vco_bypass : string := "refclk1"; -- <refclk1/refclk2/ext1/ext2>
test_bus_sel : integer := 0 ; -- <integer 0-7>;
enable_phfifo_bypass : string := "false";
sim_rxpll_clkout_phase_shift : integer := 0;
sim_rxpll_clkout_latency : integer := 0;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_a1a2size: VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn: VitalDelayType01 := DefpropDelay01;
tipd_adcereset: VitalDelayType01 := DefpropDelay01;
tipd_alignstatus: VitalDelayType01 := DefpropDelay01;
tipd_alignstatussync: VitalDelayType01 := DefpropDelay01;
tipd_analogreset: VitalDelayType01 := DefpropDelay01;
tipd_bitslip: VitalDelayType01 := DefpropDelay01;
tipd_coreclk: VitalDelayType01 := DefpropDelay01;
tipd_cruclk: VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
tipd_crupowerdn: VitalDelayType01 := DefpropDelay01;
tipd_crureset: VitalDelayType01 := DefpropDelay01;
tipd_datain: VitalDelayType01 := DefpropDelay01;
tipd_digitalreset: VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin: VitalDelayType01 := DefpropDelay01;
tipd_disablefifowrin: VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable: VitalDelayType01 := DefpropDelay01;
tipd_enabledeskew: VitalDelayType01 := DefpropDelay01;
tipd_enabyteord: VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign: VitalDelayType01 := DefpropDelay01;
tipd_fifordin: VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd: VitalDelayType01 := DefpropDelay01;
tipd_ibpowerdn: VitalDelayType01 := DefpropDelay01;
tipd_invpol: VitalDelayType01 := DefpropDelay01;
tipd_localrefclk: VitalDelayType01 := DefpropDelay01;
tipd_locktodata: VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk: VitalDelayType01 := DefpropDelay01;
tipd_masterclk: VitalDelayType01 := DefpropDelay01;
tipd_parallelfdbk: VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tipd_phfifordenable: VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset: VitalDelayType01 := DefpropDelay01;
tipd_phfifowrdisable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk: VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8bytesel: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk: VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable: VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity: VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown: VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_pipepowerstate: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_quadreset: VitalDelayType01 := DefpropDelay01;
tipd_refclk: VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa: VitalDelayType01 := DefpropDelay01;
tipd_revbyteorderwa: VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena: VitalDelayType01 := DefpropDelay01;
tipd_rmfiforeset: VitalDelayType01 := DefpropDelay01;
tipd_rmfifowrena: VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid: VitalDelayType01 := DefpropDelay01;
tipd_rxfound: VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_serialfdbk: VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken: VitalDelayType01 := DefpropDelay01;
tipd_termvoltage: VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tipd_testsel: VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrlin: VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain: VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
a1a2size : IN std_logic := '0';
adcepowerdn : IN std_logic := '0';
adcereset : IN std_logic := '0';
alignstatus : IN std_logic := '0';
alignstatussync : IN std_logic := '0';
analogreset : IN std_logic := '0';
bitslip : IN std_logic := '0';
coreclk : IN std_logic := '0';
cruclk : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
crupowerdn : IN std_logic := '0';
crureset : IN std_logic := '0';
datain : IN std_logic := '0';
digitalreset : IN std_logic := '0';
disablefifordin : IN std_logic := '0';
disablefifowrin : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic_vector(dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
enabledeskew : IN std_logic := '0';
enabyteord : IN std_logic := '0';
enapatternalign : IN std_logic := '0';
fifordin : IN std_logic := '0';
fiforesetrd : IN std_logic := '0';
ibpowerdn : IN std_logic := '0';
invpol : IN std_logic := '0';
localrefclk : IN std_logic := '0';
locktodata : IN std_logic := '0';
locktorefclk : IN std_logic := '0';
masterclk : IN std_logic := '0';
parallelfdbk : IN std_logic_vector(19 DOWNTO 0) := (OTHERS => '0');
phfifordenable : IN std_logic := '1';
phfiforeset : IN std_logic := '0';
phfifowrdisable : IN std_logic := '0';
phfifox4bytesel : IN std_logic := '0';
phfifox4rdenable : IN std_logic := '0';
phfifox4wrclk : IN std_logic := '0';
phfifox4wrenable : IN std_logic := '0';
phfifox8bytesel : IN std_logic := '0';
phfifox8rdenable : IN std_logic := '0';
phfifox8wrclk : IN std_logic := '0';
phfifox8wrenable : IN std_logic := '0';
pipe8b10binvpolarity : IN std_logic := '0'; -- new in rev1.2
pipepowerdown : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); -- width from 1 -> 2 in rev1.2
pipepowerstate : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); -- width change from 3 to 4 in rev1.3
quadreset : IN std_logic := '0';
refclk : IN std_logic := '0';
revbitorderwa : IN std_logic := '0';
revbyteorderwa : IN std_logic := '0';
rmfifordena : IN std_logic := '1';
rmfiforeset : IN std_logic := '0';
rmfifowrena : IN std_logic := '1';
rxdetectvalid : IN std_logic := '0';
rxfound : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
serialfdbk : IN std_logic := '0';
seriallpbken : IN std_logic := '0';
termvoltage : IN std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
testsel : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
xgmctrlin : IN std_logic := '0';
xgmdatain : IN std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
a1a2sizeout : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
a1detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
a2detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
adetectdeskew : OUT std_logic;
alignstatussyncout : OUT std_logic;
analogtestbus : OUT std_logic_vector(7 DOWNTO 0);
bistdone : OUT std_logic;
bisterr : OUT std_logic;
byteorderalignstatus : OUT std_logic;
clkout : OUT std_logic;
cmudivclkout : OUT std_logic;
ctrldetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dataoutfull : OUT std_logic_vector(63 DOWNTO 0);
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
disperr : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
dprioout : OUT std_logic_vector(dprio_width - 1 DOWNTO 0);
errdetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
fifordout : OUT std_logic;
freqlock : OUT std_logic;
k1detect : OUT std_logic_vector(rx_top_a1k1_out_width(use_deserializer_double_data_mode) - 1 DOWNTO 0);
k2detect : OUT std_logic_vector(1 DOWNTO 0);
patterndetect : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
phaselockloss : OUT std_logic;
phfifobyteselout : OUT std_logic;
phfifooverflow : OUT std_logic;
phfifordenableout : OUT std_logic;
phfifounderflow : OUT std_logic;
phfifowrclkout : OUT std_logic;
phfifowrenableout : OUT std_logic;
pipebufferstat : OUT std_logic_vector(3 DOWNTO 0);
pipedatavalid : OUT std_logic;
pipeelecidle : OUT std_logic;
pipephydonestatus : OUT std_logic;
pipestatus : OUT std_logic_vector(2 DOWNTO 0);
pipestatetransdoneout : OUT std_logic;
rdalign : OUT std_logic;
recovclkout : OUT std_logic;
revparallelfdbkdata : OUT std_logic_vector(19 DOWNTO 0);
revserialfdbkout : OUT std_logic;
rlv : OUT std_logic;
rmfifoalmostempty : OUT std_logic;
rmfifoalmostfull : OUT std_logic;
rmfifodatadeleted : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
rmfifodatainserted : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
rmfifoempty : OUT std_logic;
rmfifofull : OUT std_logic;
runningdisp : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
signaldetect : OUT std_logic;
syncstatus : OUT std_logic_vector(rx_top_ctrl_out_width(use_double_data_mode,use_deserializer_double_data_mode) - 1 DOWNTO 0);
syncstatusdeskew : OUT std_logic;
xgmctrldet : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0);
xgmdatavalid : OUT std_logic;
xgmrunningdisp : OUT std_logic);
END COMPONENT;
--
-- arriagx_hssi_transmitter
--
COMPONENT arriagx_hssi_transmitter
GENERIC (
allow_polarity_inversion : string := "false";
channel_bonding : string := "none"; -- none, x8, x4
channel_number : integer := 0;
channel_width : integer := 8;
disable_ph_low_latency_mode : string := "false";
disparity_mode : string := "none"; -- legacy, new, none
divider_refclk_select_pll_fast_clk0: string := "true";
dprio_mode : string := "none";
elec_idle_delay : integer := 5; -- new in 6.0
enable_bit_reversal : string := "false";
enable_idle_selection : string := "false";
enable_symbol_swap : string := "false";
enable_reverse_parallel_loopback: string := "false";
enable_reverse_serial_loopback : string := "false";
enable_self_test_mode : string := "false";
enc_8b_10b_compatibility_mode : string := "true";
enc_8b_10b_mode : string := "none"; -- cascade, normal, none
force_echar : string := "false";
force_kchar : string := "false";
low_speed_test_select : integer := 0;
prbs_all_one_detect : string := "false";
protocol_hint : string := "basic"; -- new in 6.0
refclk_divide_by : integer := 1;
refclk_select : string := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset: string := "false";
rxdetect_ctrl : integer := 0;
self_test_mode : string := "incremental";
serializer_clk_select : string := "local"; -- analogx4refclk, anlogx8refclk
transmit_protocol : string := "basic"; -- xaui-pipe-gige-basic?
use_double_data_mode : string := "false";
use_serializer_double_data_mode: string := "false";
wr_clk_mux_select : string := "CORE_CLK"; -- INT_CLK -- int_clk
vod_selection : integer := 0;
enable_slew_rate : string := "false";
preemp_tap_1 : integer := 0;
preemp_tap_2 : integer := 0;
preemp_pretap : integer := 0;
termination : string := "OCT_100_OHMS"; -- new in 5.1 SP1
preemp_tap_2_inv : string := "false"; -- New in rev 2.1
preemp_pretap_inv : string := "false"; -- New in rev 2.1
use_termvoltage_signal : string := "true"; -- new in 5.1 SP1
common_mode : string := "0.6V"; -- new in 5.1 SP1
analog_power : string := "1.5V"; -- new in 5.1 SP1
dprio_config_mode : INTEGER := 0; -- 6.1
dprio_width : INTEGER := 100; -- 6.1
allow_vco_bypass : string := "false";
enable_phfifo_bypass : string := "false";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: String := "*";
tipd_coreclk : VitalDelayType01 := DefPropDelay01;
tipd_ctrlenable : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefPropDelay01;
tipd_quadreset : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull : VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefPropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefPropDelay01;
tipd_analogx8fastrefclk : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefPropDelay01;
tipd_analogx8refclk : VitalDelayType01 := DefPropDelay01;
tipd_pma_width : VitalDelayType01 := DefPropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefPropDelay01;
tipd_pma_doublewidth : VitalDelayType01 := DefPropDelay01;
tipd_revparallelfdbk : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox8rdclk : VitalDelayType01 := DefPropDelay01;
tipd_obpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_termvoltage : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forceelecidle : VitalDelayType01 := DefPropDelay01;
tipd_powerdn : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefPropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dispval : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_analogx4fastrefclk : VitalDelayType01 := DefPropDelay01;
tipd_refclk : VitalDelayType01 := DefPropDelay01;
tipd_analogreset : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox8rdenable : VitalDelayType01 := DefPropDelay01;
tipd_invpol : VitalDelayType01 := DefPropDelay01;
tipd_enrevparallellpbk : VitalDelayType01 := DefPropDelay01;
tipd_digitalreset : VitalDelayType01 := DefPropDelay01;
tipd_phfifox8bytesel : VitalDelayType01 := DefPropDelay01;
tipd_dividerpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_analogx4refclk : VitalDelayType01 := DefPropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefPropDelay01;
tipd_revserialfdbk : VitalDelayType01 := DefPropDelay01;
tipd_clkin0 : VitalDelayType01 := DefPropDelay01;
tipd_clkin1 : VitalDelayType01 := DefPropDelay01;
tipd_reset : VitalDelayType01 := DefPropDelay01;
tipd_detectrxloop : VitalDelayType01 := DefPropDelay01;
tipd_pllfastclk : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdclk : VitalDelayType01 := DefPropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefPropDelay01;
tipd_detectrxpowerdn : VitalDelayType01 := DefPropDelay01;
tipd_phfiforddisable : VitalDelayType01 := DefPropDelay01;
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datainfull_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datainfull_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
analogreset : IN std_logic := '0';
analogx4fastrefclk : IN std_logic := '0';
analogx4refclk : IN std_logic := '0';
analogx8fastrefclk : IN std_logic := '0';
analogx8refclk : IN std_logic := '0';
coreclk : IN std_logic := '0';
ctrlenable : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
datainfull : IN std_logic_vector(43 DOWNTO 0) := (OTHERS => '0');
detectrxloop : IN std_logic := '0';
detectrxpowerdn : IN std_logic := '0';
digitalreset : IN std_logic := '0';
dispval : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
dividerpowerdn : IN std_logic := '0';
dpriodisable : IN std_logic := '1';
dprioin : IN std_logic_vector(dprio_width - 1 DOWNTO 0) := (OTHERS => '0');
enrevparallellpbk : IN std_logic := '0';
forcedispcompliance : IN std_logic := '0';
forcedisp : IN std_logic_vector(tx_top_ctrl_in_width(use_double_data_mode,use_serializer_double_data_mode) - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN std_logic := '0';
invpol : IN std_logic := '0';
obpowerdn : IN std_logic := '0';
phfiforddisable : IN std_logic := '0';
phfiforeset : IN std_logic := '0';
phfifowrenable : IN std_logic := '1';
phfifox4bytesel : IN std_logic := '0';
phfifox4rdclk : IN std_logic := '0';
phfifox4rdenable : IN std_logic := '0';
phfifox4wrenable : IN std_logic := '0';
phfifox8bytesel : IN std_logic := '0';
phfifox8rdclk : IN std_logic := '0';
phfifox8rdenable : IN std_logic := '0';
phfifox8wrenable : IN std_logic := '0';
pipestatetransdone : IN std_logic := '0';
pllfastclk : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
quadreset : IN std_logic := '0';
refclk : IN std_logic := '0';
revserialfdbk : IN std_logic := '0';
revparallelfdbk : IN std_logic_vector(19 DOWNTO 0) := (OTHERS => '0');
termvoltage : IN std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
vcobypassin : IN std_logic := '0'; -- PE-POF only
xgmctrl : IN std_logic := '0';
xgmdatain : IN std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
clkout : OUT std_logic;
dataout : OUT std_logic;
dprioout : OUT std_logic_vector(dprio_width - 1 DOWNTO 0);
parallelfdbkout : OUT std_logic_vector(19 DOWNTO 0);
phfifooverflow : OUT std_logic;
phfifounderflow : OUT std_logic;
phfifobyteselout : OUT std_logic;
phfifordclkout : OUT std_logic;
phfifordenableout : OUT std_logic;
phfifowrenableout : OUT std_logic;
pipepowerdownout : OUT std_logic_vector(1 DOWNTO 0);
pipepowerstateout : OUT std_logic_vector(3 DOWNTO 0);
rdenablesync : OUT std_logic;
refclkout : OUT std_logic;
rxdetectvalidout : OUT std_logic;
rxfoundout : OUT std_logic_vector(1 DOWNTO 0);
serialfdbkout : OUT std_logic;
xgmctrlenable : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
end arriagx_hssi_components;
package body ARRIAGX_HSSI_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end ARRIAGX_HSSI_COMPONENTS;
| gpl-3.0 | e375687a9bfa8fd4f8f6865f6e1afd5a | 0.550269 | 3.9209 | false | false | false | false |
alvieboy/xtc-base | xtc_top_bram.vhd | 1 | 3,466 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
use work.wishbonepkg.all;
entity xtc_top_bram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type
);
end entity;
architecture behave of xtc_top_bram is
component romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(31 downto 0);
ram_wb_dat_o: out std_logic_vector(31 downto 0);
ram_wb_tag_i: in std_logic_vector(31 downto 0);
ram_wb_tag_o: out std_logic_vector(31 downto 0);
ram_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
ram_wb_sel_i: in std_logic_vector(3 downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(31 downto 0);
rom_wb_tag_i: in std_logic_vector(31 downto 0);
rom_wb_tag_o: out std_logic_vector(31 downto 0);
rom_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end component;
signal wbo,romwbo,ramwbo,piowbo: wb_mosi_type;
signal wbi,romwbi,ramwbi,piowbi: wb_miso_type;
begin
cpu: xtc
port map (
wb_syscon => wb_syscon,
-- Master wishbone interface
wbo => wbo,
wbi => wbi,
-- ROM wb interface
romwbo => romwbo,
romwbi => romwbi,
isnmi => '0'
);
myram: romram
generic map (
BITS => 15
)
port map (
ram_wb_clk_i => wb_syscon.clk,
ram_wb_rst_i => wb_syscon.rst,
ram_wb_ack_o => ramwbi.ack,
ram_wb_dat_i => ramwbo.dat,
ram_wb_dat_o => ramwbi.dat,
ram_wb_adr_i => ramwbo.adr(14 downto 2),
ram_wb_cyc_i => ramwbo.cyc,
ram_wb_stb_i => ramwbo.stb,
ram_wb_sel_i => ramwbo.sel,
ram_wb_we_i => ramwbo.we,
ram_wb_stall_o => ramwbi.stall,
ram_wb_tag_i => ramwbo.tag,
ram_wb_tag_o => ramwbi.tag,
rom_wb_clk_i => wb_syscon.clk,
rom_wb_rst_i => wb_syscon.rst,
rom_wb_ack_o => romwbi.ack,
rom_wb_dat_o => romwbi.dat,
rom_wb_adr_i => romwbo.adr(14 downto 2),
rom_wb_cyc_i => romwbo.cyc,
rom_wb_stb_i => romwbo.stb,
rom_wb_tag_i => romwbo.tag,
rom_wb_tag_o => romwbi.tag,
rom_wb_stall_o => romwbi.stall
);
muxer: xtc_wbmux2
generic map (
select_line => 31,
address_high => 31,
address_low => 2
)
port map (
wb_syscon => wb_syscon,
-- Master
m_wbi => wbo,
m_wbo => wbi,
-- Slave 0 signals
s0_wbi => ramwbi,
s0_wbo => ramwbo,
-- Slave 1 signals
s1_wbi => piowbi,
s1_wbo => piowbo
);
ioadaptor: wb_master_p_to_slave_np
port map (
syscon => wb_syscon,
mwbo => piowbi,
mwbi => piowbo,
swbi => iowbi,
swbo => iowbo
);
end behave;
| bsd-3-clause | 2c7149ae0d679f1291a7f1f313dd131c | 0.534045 | 2.786174 | false | false | false | false |
EPiCS/reconos | pcores/reconos_osif_v1_00_a/hdl/vhdl/reconos_osif.vhd | 2 | 9,094 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - OSIF - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A AXI slave which maps the FIFOs of the HWTs to
-- registers accessible from the AXI-Bus.
-- Reg0: Read data
-- Reg1: Write data
-- Reg2: Fill - number of elements in receive-FIFO
-- Reg3: Rem - free space in send-FIFO
--
-- REMARK: Different clocks for AXI, FIFO-Rd and FIFO-Wr
-- are not supported yet. S_AXI_ACKL is used and
-- FIFO_**_Clk are just added for the future.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library reconos_osif_v1_00_a;
use reconos_osif_v1_00_a.user_logic;
entity reconos_osif is
generic (
C_NUM_FIFOS : integer := 1;
C_FIFO_WIDTH : integer := 32;
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port (
-- FIFO ports
-- ## BEGIN GENERATE LOOP ##
FIFO_S_Data_#i# : in std_logic_vector(31 downto 0);
FIFO_S_Fill_#i# : in std_logic_vector(15 downto 0);
FIFO_S_Empty_#i# : in std_logic;
FIFO_S_RE_#i# : out std_logic;
FIFO_M_Data_#i# : out std_logic_vector(31 downto 0);
FIFO_M_Rem_#i# : in std_logic_vector(15 downto 0);
FIFO_M_Full_#i# : in std_logic;
FIFO_M_WE_#i# : out std_logic;
-- ## END GENERATE LOOP ##
-- Bus protocol ports
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity reconos_osif;
architecture implementation of reconos_osif is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : entity reconos_osif_v1_00_a.user_logic
generic map (
C_NUM_FIFOS => C_NUM_FIFOS,
C_FIFO_WIDTH => C_FIFO_WIDTH,
-- Bus protocol parameters
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map (
-- FIFO ports
-- ## BEGIN GENERATE LOOP ##
FIFO_S_Data_#i# => FIFO_S_Data_#i#,
FIFO_S_Fill_#i# => FIFO_S_Fill_#i#,
FIFO_S_Empty_#i# => FIFO_S_Empty_#i#,
FIFO_S_RE_#i# => FIFO_S_RE_#i#,
FIFO_M_Data_#i# => FIFO_M_Data_#i#,
FIFO_M_Rem_#i# => FIFO_M_Rem_#i#,
FIFO_M_Full_#i# => FIFO_M_Full_#i#,
FIFO_M_WE_#i# => FIFO_M_WE_#i#,
-- ## END GENERATE LOOP ##
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_CS => ipif_Bus2IP_CS,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
-- connect internal signals
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
end implementation;
| gpl-2.0 | 9d8016727f6b66c4453b58465cfcab3b | 0.560651 | 2.809951 | false | false | false | false |
EPiCS/reconos | demos/reconf_sort_matrix/hw/hwt_matrixmul_v2_00_a/hdl/vhdl/hwt_matrixmul.vhd | 2 | 14,921 | ------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hwt_matrixmul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_matrixmul;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture implementation of hwt_matrixmul is
type STATE_TYPE is (
STATE_GET_ADDR2MADDRS,
STATE_READ_MADDRS,
STATE_READ_MATRIX_B,
STATE_READ_MATRIX_ROW_FROM_A,
STATE_MULTIPLY_MATRIX_ROW,
STATE_WRITE_MATRIX_ROW_TO_C,
STATE_ACK,
STATE_THREAD_EXIT
);
component matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_WE : out std_logic
);
end component;
constant C_LINE_LEN_MATRIX : integer := 64;
-- Use the following line for testing purposes.
--constant C_LINE_LEN_MATRIX : integer := 4;
-- const for matrixes A and C
constant C_LOCAL_RAM_SIZE_MATRIX_A_C : integer := C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_A_C);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_A_C;
type LOCAL_MEMORY_TYPE_MATRIX_A_C is array(0 to C_LOCAL_RAM_SIZE_MATRIX_A_C - 1) of std_logic_vector(31 downto 0);
-- const for matrix B
constant C_LOCAL_RAM_SIZE_MATRIX_B : integer := C_LINE_LEN_MATRIX*C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_B);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_B;
type LOCAL_MEMORY_TYPE_MATRIX_B is array(0 to C_LOCAL_RAM_SIZE_MATRIX_B - 1) of std_logic_vector(31 downto 0);
-- communication with microblaze core
constant C_MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant C_MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal ignore : std_logic_vector(31 downto 0);
-- maddr is an acronym for "matrix address" (address that points to a matrix)
constant C_MADDRS : integer := 3;
type MADDR_BOX_TYPE is array(0 to C_MADDRS-1) of std_logic_vector(31 downto 0);
-- container for adresses pointing to the first element of matrixes A, B and C
signal maddrs : MADDR_BOX_TYPE;
-- points to pointers to the matrixes
signal addr2maddrs : std_logic_vector(31 downto 0);
-- temporary signals
signal temp_addr_A : std_logic_vector(31 downto 0);
signal temp_addr_C : std_logic_vector(31 downto 0);
-- fsm state
signal state : STATE_TYPE;
-- additional data for memif interfaces
signal len_data_MATRIX_A_C : std_logic_vector(23 downto 0);
signal len_data_MATRIX_B : std_logic_vector(23 downto 0);
-- osif, memif and different local BRAM interfaces
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram_A : i_ram_t;
signal o_ram_A : o_ram_t;
signal i_ram_B : i_ram_t;
signal o_ram_B : o_ram_t;
signal i_ram_C : i_ram_t;
signal o_ram_C : o_ram_t;
signal o_RAM_A_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_A_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_WE_reconos : std_logic;
signal i_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal o_RAM_B_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_WE_reconos : std_logic;
signal i_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_WE_reconos : std_logic;
signal i_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal i_RAM_A_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal i_RAM_B_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_WE_mul : std_logic;
shared variable local_ram_a : LOCAL_MEMORY_TYPE_MATRIX_A_C;
shared variable local_ram_b : LOCAL_MEMORY_TYPE_MATRIX_B;
shared variable local_ram_c : LOCAL_MEMORY_TYPE_MATRIX_A_C;
signal multiplier_start : std_logic;
signal multiplier_done : std_logic;
signal clk, rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local BRAM read and write access
local_ram_ctrl_1 : process (clk) is
begin
if (clk'event and clk = '1') then
if (o_RAM_A_WE_reconos = '1') then
local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_reconos))) := o_RAM_A_Data_reconos;
end if;
if (o_RAM_B_WE_reconos = '1') then
local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_reconos))) := o_RAM_B_Data_reconos;
end if;
if (o_RAM_C_WE_reconos = '0') then
i_RAM_C_Data_reconos <= local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAM_C_WE_mul = '1') then
local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_mul))) := o_RAM_C_Data_mul;
else
i_RAM_A_Data_mul <= local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_mul)));
i_RAM_B_Data_mul <= local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_mul)));
end if;
end if;
end process;
-- the matrix multiplication module
matrixmultiplier_i : matrixmultiplier
generic map(
G_LINE_LEN_MATRIX => C_LINE_LEN_MATRIX,
G_RAM_DATA_WIDTH => 32,
G_RAM_SIZE_MATRIX_A_C => C_LOCAL_RAM_SIZE_MATRIX_A_C,
G_RAM_ADDR_WIDTH_MATRIX_A_C => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C,
G_RAM_SIZE_MATRIX_B => C_LOCAL_RAM_SIZE_MATRIX_B,
G_RAM_ADDR_WIDTH_MATRIX_B => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B
)
port map(
clk => clk,
reset => rst,
start => multiplier_start,
done => multiplier_done,
o_RAM_A_Addr => o_RAM_A_Addr_mul,
i_RAM_A_Data => i_RAM_A_Data_mul,
o_RAM_B_Addr => o_RAM_B_Addr_mul,
i_RAM_B_Data => i_RAM_B_Data_mul,
o_RAM_C_Addr => o_RAM_C_Addr_mul,
o_RAM_C_Data => o_RAM_C_Data_mul,
o_RAM_C_WE => o_RAM_C_WE_mul
);
-- setup interfaces (FIFOs, FSL,...)
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram_A,
o_ram_A,
o_RAM_A_Addr_reconos_2,
o_RAM_A_WE_reconos,
o_RAM_A_Data_reconos,
i_RAM_A_Data_reconos
);
ram_setup (
i_ram_B,
o_ram_B,
o_RAM_B_Addr_reconos_2,
o_RAM_B_WE_reconos,
o_RAM_B_Data_reconos,
i_RAM_B_Data_reconos
);
ram_setup (
i_ram_C,
o_ram_C,
o_RAM_C_Addr_reconos_2,
o_RAM_C_WE_reconos,
o_RAM_C_Data_reconos,
i_RAM_C_Data_reconos
);
o_RAM_A_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_A_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
o_RAM_B_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1) <= o_RAM_B_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B ) to 31);
o_RAM_C_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_C_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
reconos_fsm : process(clk, rst, o_osif, o_memif, o_ram_a, o_ram_b, o_ram_c) is
variable done : boolean;
variable addr_pos : integer;
variable calculated_rows : integer;
begin
if (rst = '1') then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram_A);
ram_reset(o_ram_B);
ram_reset(o_ram_C);
multiplier_start <= '0';
done := false;
calculated_rows := 0;
len_data_MATRIX_A_C <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C, 24);
len_data_MATRIX_B <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B , 24);
-- important to know:
-- maddrs(0) = C, maddrs(1) = B, maddrs(2) = A
addr2maddrs <= (others => '0');
addr_pos := C_MADDRS - 1;
for i in 0 to (C_MADDRS - 1) loop
maddrs(i) <= (others => '0');
end loop;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
elsif (clk'event and clk = '1') then
case state is
-- Get address pointing to the addresses pointing to the 3 matrixes via FSL.
when STATE_GET_ADDR2MADDRS =>
osif_mbox_get(i_osif, o_osif, C_MBOX_RECV, addr2maddrs, done);
if (done) then
if (addr2maddrs = x"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
addr2maddrs <= addr2maddrs(31 downto 2) & "00";
addr_pos := C_MADDRS - 1;
state <= STATE_READ_MADDRS;
end if;
end if;
-- Read addresses pointing to input matrixes A, B and output matrix C from main memory.
when STATE_READ_MADDRS =>
memif_read_word(i_memif, o_memif, addr2maddrs, maddrs(addr_pos), done);
if done then
if (addr_pos = 0) then
state <= STATE_READ_MATRIX_B;
else
addr_pos := addr_pos - 1;
addr2maddrs <= conv_std_logic_vector(unsigned(addr2maddrs) + 4, 32);
end if;
end if;
-- Read matrix B from main memory.
when STATE_READ_MATRIX_B =>
memif_read(i_ram_B, o_ram_B, i_memif, o_memif, maddrs(1), X"00000000", len_data_MATRIX_B, done);
if done then
temp_addr_A <= maddrs(2);
temp_addr_C <= maddrs(0);
state <= STATE_READ_MATRIX_ROW_FROM_A;
end if;
-- Read a row of matrix A.
when STATE_READ_MATRIX_ROW_FROM_A =>
memif_read(i_ram_A, o_ram_A, i_memif, o_memif, temp_addr_A, X"00000000", len_data_MATRIX_A_C, done);
if done then
multiplier_start <= '1';
state <= STATE_MULTIPLY_MATRIX_ROW;
end if;
-- Multiply row of matrix A with matrix B.
when STATE_MULTIPLY_MATRIX_ROW =>
multiplier_start <= '0';
if (multiplier_done = '1') then
calculated_rows := calculated_rows + 1;
state <= STATE_WRITE_MATRIX_ROW_TO_C;
end if;
-- Write multiplication result (row of matrix C) to main memory.
when STATE_WRITE_MATRIX_ROW_TO_C =>
memif_write(i_ram_C, o_ram_C, i_memif, o_memif, X"00000000", temp_addr_C, len_data_MATRIX_A_C, done);
if (done) then
if (calculated_rows < C_LINE_LEN_MATRIX) then
-- Calculate new temporary addresses
-- => to fetch next matrix row of matrix A
-- => to store calculated values to next matrix row of matrix C
temp_addr_A <= conv_std_logic_vector(unsigned(temp_addr_A) + C_LINE_LEN_MATRIX*4, 32);
temp_addr_C <= conv_std_logic_vector(unsigned(temp_addr_C) + C_LINE_LEN_MATRIX*4, 32);
state <= STATE_READ_MATRIX_ROW_FROM_A;
else
state <= STATE_ACK;
end if;
end if;
-- We finished calculating matrix multiplication A * B = C.
when STATE_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, C_MBOX_SEND, maddrs(addr_pos), ignore, done);
if (done) then
calculated_rows := 0;
addr_pos := C_MADDRS - 1;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
end if;
-- Terminate hardware thread.
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif, o_osif);
end case;
end if;
end process;
end architecture implementation;
| gpl-2.0 | 58e63430f3d2ebdfe04d4ce5617a879a | 0.611956 | 2.667799 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cyclone_atoms.vhd | 1 | 333,962 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cyclone_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cyclone_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cyclone_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cyclone_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cyclone_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cyclone_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cyclone_pllpack;
package body cyclone_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cyclone_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cyclone_atom_pack.all;
entity cyclone_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cyclone_dffe : entity is TRUE;
end cyclone_dffe;
-- architecture body --
architecture behave of cyclone_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cyclone_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cyclone_atom_pack.all;
entity cyclone_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cyclone_mux21 : entity is TRUE;
end cyclone_mux21;
architecture AltVITAL of cyclone_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cyclone_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cyclone_atom_pack.all;
entity cyclone_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cyclone_mux41 : entity is TRUE;
end cyclone_mux41;
architecture AltVITAL of cyclone_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cyclone_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cyclone_atom_pack.all;
-- entity declaration --
entity cyclone_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cyclone_and1 : entity is TRUE;
end cyclone_and1;
-- architecture body --
architecture AltVITAL of cyclone_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for CYCLONE Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_asynch_lcell
--
-- Description : VHDL simulation model for the asynchnous submodule of
-- Cyclone Lcell.
--
-- Outputs : Asynchnous LUT function of Cyclone Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cyclone_atom_pack.all;
ENTITY cyclone_asynch_lcell is
GENERIC (
lms : std_logic_vector(15 downto 0) := "1111111111111111";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
attribute VITAL_LEVEL0 of cyclone_asynch_lcell : ENTITY is TRUE;
END cyclone_asynch_lcell;
ARCHITECTURE vital_le of cyclone_asynch_lcell is
attribute VITAL_LEVEL1 of vital_le : ARCHITECTURE is TRUE;
signal dataa_ipd : std_ulogic;
signal datab_ipd : std_ulogic;
signal datac_ipd : std_ulogic;
signal datad_ipd : std_ulogic;
signal inverta_ipd : std_ulogic;
signal cin_ipd : std_ulogic;
signal cin0_ipd : std_ulogic;
signal cin1_ipd : std_ulogic;
-- operation_mode --> mode(0) - normal=1 arithemtic=0
-- sum_lutc_cin --> mode(1) - lutc=1 cin=0
-- sum_lutc_qfbk --> mode(2) - qfbk=1 mode1=0
-- cin_used --> mode(3) - true=1 false=0
-- cin0_used --> mode(4) - true=1 false=0
-- cin1_used --> mode(5) - true=1 false=0
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
VitalWireDelay (inverta_ipd, inverta, tipd_inverta);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, mode,
cin_ipd, cin0_ipd, cin1_ipd, inverta_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_ulogic;
variable tmp_cout : std_ulogic;
variable tmp_cout0 : std_ulogic;
variable tmp_cout1 : std_ulogic;
variable tmp_regin : std_ulogic;
variable lutb : std_ulogic;
variable cintmp : std_ulogic;
variable invertsig : std_ulogic := '0';
variable cinsel : std_ulogic;
variable cinsig : std_ulogic;
variable cin01sel : std_ulogic;
variable luta : std_ulogic;
variable lutc : std_ulogic;
variable lutd : std_ulogic;
variable datacsig : std_ulogic;
variable lms_var : std_logic_vector(15 downto 0) := "1111111111111111";
begin
lms_var := lms;
cinsel := (cin_ipd and mode(3)) or
(inverta_ipd and (not mode(3)));
cin01sel := (cin1_ipd and cinsel) or
(cin0_ipd and (not cinsel));
cintmp := (cin_ipd and mode(0)) or
((not mode(0)) and mode(3) and cin_ipd) or
((not mode(0)) and (not mode(3)) and inverta_ipd);
cinsig := (cintmp and ((not mode(4)) and (not mode(5)))) or
(cin01sel and (mode(4) or mode(5)));
datacsig := (datac_ipd and mode(1)) or
(cinsig and (not mode(1)));
luta := dataa_ipd XOR inverta_ipd;
lutb := datab_ipd;
lutc := (qfbkin and mode(2)) or
(datacsig and (not mode(2)));
lutd := (datad_ipd and mode(0)) or (not mode(0));
tmp_combout := VitalMUX(data => lms_var,
dselect => (lutd,
lutc,
lutb,
luta)
);
tmp_cout0 := VitalMUX(data => lms_var,
dselect => ('0',
cin0_ipd,
lutb,
luta)
);
tmp_cout1 := VitalMUX(data => lms_var,
dselect => ('0',
cin1_ipd,
lutb,
luta)
);
tmp_cout := VitalMux2(VitalMux2(tmp_cout1,
tmp_cout0,
cin_ipd),
VitalMux2(tmp_cout1,
tmp_cout0,
inverta_ipd),
mode(3)
);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_combout, (mode(2) = '1'))),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01
(
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_regin, (mode(2) = '1'))),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => tmp_cout0,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => tmp_cout1,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_le;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_lcell_register
--
-- Description : VHDL simulation model for the register submodule of
-- Cyclone Lcell.
--
-- Outputs : Registered output of Cyclone Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cyclone_atom_pack.all;
ENTITY cyclone_lcell_register is
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_regout : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_qfbkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (clk : in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
attribute VITAL_LEVEL0 of cyclone_lcell_register : ENTITY is TRUE;
end cyclone_lcell_register;
ARCHITECTURE vital_le_reg of cyclone_lcell_register is
attribute VITAL_LEVEL1 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd : std_ulogic := '1';
signal sload_ipd : std_ulogic := '0';
signal aload_ipd : std_ulogic := '0';
signal datac_ipd : std_ulogic := '0';
signal regcascin_ipd : std_ulogic := '0';
signal clk_ipd : std_ulogic := '0';
signal aclr_ipd : std_ulogic := '0';
signal sclr_ipd : std_ulogic := '0';
constant cyclone_regtab : VitalStateTableType := (
-- CLK ACLR D D1 D2 EN Aload Sclr Sload Casc Synch Qp Q
( x, H, x, x, x, x, x, x, x, x, x, x, L ), -- Areset
( x, x, x, L, x, x, H, x, x, x, x, x, L ), -- Aload
( x, x, x, H, x, x, H, x, x, x, x, x, H ), -- Aload
( x, x, x, x, x, x, H, x, x, x, x, x, U ), -- Aload
( x, x, x, x, x, L, x, x, x, x, x, x, S ), -- Q=Q
( R, x, x, x, x, H, x, H, x, x, H, x, L ), -- Sreset
( R, x, x, L, x, H, x, x, H, x, H, x, L ), -- Sload
( R, x, x, H, x, H, x, x, H, x, H, x, H ), -- Sload
( R, x, x, x, x, H, x, x, H, x, H, x, U ), -- Sload
( R, x, x, x, L, H, x, x, x, H, x, x, L ), -- Cascade
( R, x, x, x, H, H, x, x, x, H, x, x, H ), -- Cascade
( R, x, x, x, x, H, x, x, x, H, x, x, U ), -- Cascade
( R, x, L, x, x, H, x, x, x, x, H, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, H, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, H, x, U ), -- Datain
( R, x, L, x, x, H, x, x, x, x, x, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, x, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, x, x, U ), -- Datain
( x, x, x, x, x, x, x, x, x, x, x, x, S )); -- Q=Q
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (regcascin_ipd, regcascin, tipd_regcascin);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, aload_ipd, datac_ipd,
regcascin_ipd, datain, sclr_ipd, ena_ipd,
sload_ipd, cena, xonv, smode)
variable Tviol_regcascin_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_regcascin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbkout_VitalGlitchData : VitalGlitchDataType;
-- variables for 'X' generation
variable Tviolation : std_ulogic := '0';
variable tmp_regout : STD_ULOGIC := '0';
variable PreviousData : STD_LOGIC_VECTOR(0 to 10);
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_regcascin_clk,
TimingData => TimingData_regcascin_clk,
TestSignal => regcascin_ipd,
TestSignalName => "REGCASCIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_regcascin_clk_noedge_posedge,
SetupLow => tsetup_regcascin_clk_noedge_posedge,
HoldHigh => thold_regcascin_clk_noedge_posedge,
HoldLow => thold_regcascin_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr_ipd) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
end if;
-------------------------
-- Functionality Section
-------------------------
Tviolation := Tviol_regcascin_clk or Tviol_datain_clk or
Tviol_datac_clk or Tviol_ena_clk or
Tviol_sclr_clk or Tviol_sload_clk;
VitalStateTable (
Result => tmp_regout,
PreviousDataIn => PreviousData,
StateTable => cyclone_regtab,
DataIn => (CLK_ipd, ACLR_ipd, datain, datac_ipd,
regcascin_ipd, ENA_ipd, aload_ipd, sclr_ipd,
sload_ipd, cena, smode)
);
tmp_regout := (xonv AND Tviolation) XOR tmp_regout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbkout,
OutSignalName => "QFBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbkout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_qfbkout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_qfbkout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_qfbkout_posedge, TRUE)),
GlitchData => qfbkout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_lcell
--
-- Description : VHDL simulation model for Cyclone Lcell.
--
-- Outputs : Output of Cyclone Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cyclone_atom_pack.all;
use work.cyclone_asynch_lcell;
use work.cyclone_lcell_register;
ENTITY cyclone_lcell is
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "cyclone_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end cyclone_lcell;
ARCHITECTURE vital_le_atom of cyclone_lcell is
signal dffin : std_logic;
signal qfbkin : std_logic;
signal mode : std_logic_vector(5 downto 0);
COMPONENT cyclone_asynch_lcell
GENERIC (
lms : std_logic_vector(15 downto 0);
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01
);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end COMPONENT;
COMPONENT cyclone_lcell_register
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (
clk :in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
end COMPONENT;
signal aclr1, xonv, cena, smode : std_logic ;
begin
aclr1 <= aclr or (not devclrn) or (not devpor);
cena <= '1' when (register_cascade_mode = "on") else '0';
xonv <= '1' when (x_on_violation = "on") else '0';
smode <= '1' when (synch_mode = "on") else '0';
mode(0) <= '1' when operation_mode = "normal" else
'0'; -- operation_mode = "arithmetic"
mode(1) <= '1' when sum_lutc_input = "datac" else
'0' ; -- sum_lutc_input = "cin"
mode(2) <= '1' when sum_lutc_input = "qfbk" else
'0'; -- sum_lutc_input = "cin" or "datac"
mode(3) <= '1' when cin_used = "true" else
'0'; -- cin_used = "false"
mode(4) <= '1' when cin0_used = "true" else
'0'; -- cin0_used = "false"
mode(5) <= '1' when cin1_used = "true" else
'0'; -- cin1_used = "false"
lecomb: cyclone_asynch_lcell
GENERIC map (
lms => str_to_bin(lut_mask)
)
PORT map (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
qfbkin => qfbkin,
inverta => map_x_to_0(inverta),
cin => cin,
cin0 => cin0,
cin1 => cin1,
mode => mode,
combout => combout,
cout => cout,
cout0 => cout0,
cout1 => cout1,
regin => dffin
);
lereg: cyclone_lcell_register
PORT map (
clk => clk,
datain => dffin,
datac => datac,
smode => smode,
regcascin => regcascin,
aclr => aclr1,
aload => aload,
sclr => sclr,
sload => sload,
ena => ena,
cena => cena,
xonv => xonv,
regout => regout,
qfbkout => qfbkin
);
end vital_le_atom;
----------------------------------------------------------------------------
-- Module Name : cyclone_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cyclone_atom_pack.all;
ENTITY cyclone_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cyclone_ram_register;
ARCHITECTURE reg_arch OF cyclone_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cyclone_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cyclone_atom_pack.all;
ENTITY cyclone_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cyclone_ram_pulse_generator:ENTITY IS TRUE;
END cyclone_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cyclone_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cyclone_atom_pack.all;
USE work.cyclone_ram_register;
USE work.cyclone_ram_pulse_generator;
ENTITY cyclone_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "cyclone_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cyclone_ram_block;
ARCHITECTURE block_arch OF cyclone_ram_block IS
COMPONENT cyclone_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cyclone_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= ena0;
active_b_in <= ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : cyclone_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : cyclone_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cyclone_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : cyclone_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cyclone_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cyclone_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : cyclone_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : cyclone_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cyclone_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cyclone_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cyclone_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : cyclone_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : cyclone_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : cyclone_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : cyclone_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : cyclone_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cyclone_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cyclone_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_m_cntr
--
-- Description : Timing simulation model for the M counter. This is a
-- model for the loop feedback counter of the Cyclone PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cyclone_m_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0);
END cyclone_m_cntr;
ARCHITECTURE behave of cyclone_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_n_cntr
--
-- Description : Timing simulation model for the N counter. This is a
-- model for the input counter of the Cyclone PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cyclone_n_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END cyclone_n_cntr;
ARCHITECTURE behave of cyclone_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on Cyclone PLL input clk. This edge will be ignored" severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge and (clk_last_valid_value /= clk)) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the L0, L1, G0, G1, G2, G3, E0,
-- E1, E2 and E3 output counters of the Cyclone PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cyclone_scale_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
initial : IN integer;
high : IN integer;
low : IN integer;
mode : IN string := "bypass";
time_delay : IN integer;
ph_tap : IN natural;
cout : OUT std_logic);
END cyclone_scale_cntr;
ARCHITECTURE behave of cyclone_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 0;
variable first_rising_edge : boolean := false;
variable high_reg : integer := 0;
variable low_reg : integer := 0;
variable init : boolean := true;
variable high_cnt_xfer_done : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 0;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (init) then
init := false;
high_reg := high;
low_reg := low;
end if;
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
elsif (not first_rising_edge) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high_reg*2) + 1)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (mode = " odd" and (count = high_reg*2)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (count = (high_reg + low_reg)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
if (high_reg /= high) then
high_cnt_xfer_done := true;
high_reg := high;
end if;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cyclone_pll_reg is
PORT ( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic);
end cyclone_pll_reg;
ARCHITECTURE behave of cyclone_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_pll
--
-- Description : Timing simulation model for the Cyclone StratixGX PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cyclone_atom_pack.all;
USE work.cyclone_pllpack.all;
USE work.cyclone_m_cntr;
USE work.cyclone_n_cntr;
USE work.cyclone_scale_cntr;
USE work.cyclone_dffe;
USE work.cyclone_pll_reg;
ENTITY cyclone_pll is
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "cyclone_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
-- LVDS mode parameters
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
-- Simulation only generics
family_name : string := "Cyclone";
skip_vco : string := "off";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
-- lvds specific ports
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END cyclone_pll;
ARCHITECTURE vital_pll of cyclone_pll is
-- internal advanced parameter signals
signal i_vco_min : natural;
signal i_vco_max : natural;
signal i_vco_center : natural;
signal i_pfd_min : natural;
signal i_pfd_max : natural;
signal l0_ph_val : natural;
signal l1_ph_val : natural;
signal g0_ph_val : natural;
signal g1_ph_val : natural;
signal g2_ph_val : natural;
signal g3_ph_val : natural;
signal e0_ph_val : natural;
signal e1_ph_val : natural;
signal e2_ph_val : natural;
signal e3_ph_val : natural;
signal i_extclk3_counter : string(1 to 2) := "e3";
signal i_extclk2_counter : string(1 to 2) := "e2";
signal i_extclk1_counter : string(1 to 2) := "e1";
signal i_extclk0_counter : string(1 to 2) := "e0";
signal i_clk5_counter : string(1 to 2) := "l1";
signal i_clk4_counter : string(1 to 2) := "l0";
signal i_clk3_counter : string(1 to 2) := "g3";
signal i_clk2_counter : string(1 to 2) := "g2";
signal i_clk1_counter : string(1 to 2) := "g1";
signal i_clk0_counter : string(1 to 2) := "g0";
signal i_charge_pump_current : natural;
signal i_loop_filter_r : natural;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT EGPP_SCAN_CHAIN : integer := 289;
CONSTANT GPP_SCAN_CHAIN : integer := 193;
CONSTANT TRST : time := 5000 ps;
CONSTANT TRSTCLK : time := 5000 ps;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal l0_clk : std_logic;
signal l1_clk : std_logic;
signal g0_clk : std_logic;
signal g1_clk : std_logic;
signal g2_clk : std_logic;
signal g3_clk : std_logic;
signal e0_clk : std_logic;
signal e1_clk : std_logic;
signal e2_clk : std_logic;
signal e3_clk : std_logic;
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal m_val_tmp : integer := 1;
signal m2_val : integer := 1;
signal n_val : integer := 1;
signal n_val_tmp : integer := 1;
signal n2_val : integer := 1;
signal m_time_delay_val, n_time_delay_val : integer := 0;
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal l0_initial_val : integer := l0_initial;
signal l1_initial_val : integer := l1_initial;
signal l0_high_val : integer := l0_high;
signal l1_high_val : integer := l1_high;
signal l0_low_val : integer := l0_low;
signal l1_low_val : integer := l1_low;
signal l0_mode_val : string(1 to 6) := "bypass";
signal l1_mode_val : string(1 to 6) := "bypass";
signal l0_time_delay_val : integer := l0_time_delay;
signal l1_time_delay_val : integer := l1_time_delay;
signal g0_initial_val : integer := g0_initial;
signal g1_initial_val : integer := g1_initial;
signal g2_initial_val : integer := g2_initial;
signal g3_initial_val : integer := g3_initial;
signal g0_high_val : integer := g0_high;
signal g1_high_val : integer := g1_high;
signal g2_high_val : integer := g2_high;
signal g3_high_val : integer := g3_high;
signal g0_mode_val : string(1 to 6) := "bypass";
signal g1_mode_val : string(1 to 6) := "bypass";
signal g2_mode_val : string(1 to 6) := "bypass";
signal g3_mode_val : string(1 to 6) := "bypass";
signal g0_low_val : integer := g0_low;
signal g1_low_val : integer := g1_low;
signal g2_low_val : integer := g2_low;
signal g3_low_val : integer := g3_low;
signal g0_time_delay_val : integer := g0_time_delay;
signal g1_time_delay_val : integer := g1_time_delay;
signal g2_time_delay_val : integer := g2_time_delay;
signal g3_time_delay_val : integer := g3_time_delay;
signal e0_initial_val : integer := e0_initial;
signal e1_initial_val : integer := e1_initial;
signal e2_initial_val : integer := e2_initial;
signal e3_initial_val : integer := e3_initial;
signal e0_high_val : integer := e0_high;
signal e1_high_val : integer := e1_high;
signal e2_high_val : integer := e2_high;
signal e3_high_val : integer := e3_high;
signal e0_low_val : integer := e0_low;
signal e1_low_val : integer := e1_low;
signal e2_low_val : integer := e2_low;
signal e3_low_val : integer := e3_low;
signal e0_time_delay_val : integer := e0_time_delay;
signal e1_time_delay_val : integer := e1_time_delay;
signal e2_time_delay_val : integer := e2_time_delay;
signal e3_time_delay_val : integer := e3_time_delay;
signal e0_mode_val : string(1 to 6) := "bypass";
signal e1_mode_val : string(1 to 6) := "bypass";
signal e2_mode_val : string(1 to 6) := "bypass";
signal e3_mode_val : string(1 to 6) := "bypass";
signal m_mode_val : string(1 to 6) := " ";
signal m2_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal n2_mode_val : string(1 to 6) := " ";
signal cntr_e0_initial : integer := 1;
signal cntr_e1_initial : integer := 1;
signal cntr_e2_initial : integer := 1;
signal cntr_e3_initial : integer := 1;
signal ext_fbk_delay : integer := 0;
signal cntr_e0_delay : integer := 0;
signal cntr_e1_delay : integer := 0;
signal cntr_e2_delay : integer := 0;
signal cntr_e3_delay : integer := 0;
signal transfer : std_logic := '0';
signal scan_data : std_logic_vector(288 downto 0) := (OTHERS => '0');
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
signal ena4 : std_logic;
signal ena5 : std_logic;
signal extena0 : std_logic;
signal extena1 : std_logic;
signal extena2 : std_logic;
signal extena3 : std_logic;
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal extclk0_tmp : std_logic;
signal extclk1_tmp : std_logic;
signal extclk2_tmp : std_logic;
signal extclk3_tmp : std_logic;
signal not_clk0_tmp : std_logic;
signal not_clk1_tmp : std_logic;
signal not_clk2_tmp : std_logic;
signal not_clk3_tmp : std_logic;
signal not_clk4_tmp : std_logic;
signal not_clk5_tmp : std_logic;
signal not_extclk0_tmp : std_logic;
signal not_extclk1_tmp : std_logic;
signal not_extclk2_tmp : std_logic;
signal not_extclk3_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal quiet_period_violation : boolean := false;
signal reconfig_err : boolean := false;
signal scanclr_violation : boolean := false;
signal scanclr_clk_violation : boolean := false;
signal inclk_l0 : std_logic;
signal inclk_l1 : std_logic;
signal inclk_g0 : std_logic;
signal inclk_g1 : std_logic;
signal inclk_g2 : std_logic;
signal inclk_g3 : std_logic;
signal inclk_e0 : std_logic;
signal inclk_e1 : std_logic;
signal inclk_e2 : std_logic;
signal inclk_e3 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal comparator_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal clkena0_ipd : std_logic;
signal clkena1_ipd : std_logic;
signal clkena2_ipd : std_logic;
signal clkena3_ipd : std_logic;
signal clkena4_ipd : std_logic;
signal clkena5_ipd : std_logic;
signal extclkena0_ipd : std_logic;
signal extclkena1_ipd : std_logic;
signal extclkena2_ipd : std_logic;
signal extclkena3_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanaclr_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal lvds_dffa_clk : std_logic;
signal lvds_dffb_clk : std_logic;
signal lvds_dffc_clk : std_logic;
signal lvds_dffd_clk : std_logic;
signal dffa_out : std_logic := '0';
signal dffb_out : std_logic := '0';
signal dffc_out : std_logic := '0';
signal dffd_out : std_logic := '0';
signal nce_temp : std_logic := '0';
signal nce_l0 : std_logic := '0';
signal nce_l1 : std_logic := '0';
signal inclk_l0_dly1 : std_logic := '0';
signal inclk_l0_dly2 : std_logic := '0';
signal inclk_l0_dly3 : std_logic := '0';
signal inclk_l0_dly4 : std_logic := '0';
signal inclk_l0_dly5 : std_logic := '0';
signal inclk_l0_dly6 : std_logic := '0';
signal inclk_l1_dly1 : std_logic := '0';
signal inclk_l1_dly2 : std_logic := '0';
signal inclk_l1_dly3 : std_logic := '0';
signal inclk_l1_dly4 : std_logic := '0';
signal inclk_l1_dly5 : std_logic := '0';
signal inclk_l1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal sig_current_clock : string(1 to 6);
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal sig_curr_clock : string(1 to 6) := primary_clock;
signal scan_chain_length : integer := GPP_SCAN_CHAIN;
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_delay : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "e0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal sdataout_trig : std_logic := '0';
signal sdataout_rst_trig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal done_with_param_calc : boolean := false;
COMPONENT cyclone_m_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0 );
END COMPONENT;
COMPONENT cyclone_n_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END COMPONENT;
COMPONENT cyclone_scale_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
time_delay : IN integer := 0;
ph_tap : IN natural );
END COMPONENT;
COMPONENT cyclone_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cyclone_pll_reg
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (clkena0_ipd, clkena(0), tipd_clkena(0));
VitalWireDelay (clkena1_ipd, clkena(1), tipd_clkena(1));
VitalWireDelay (clkena2_ipd, clkena(2), tipd_clkena(2));
VitalWireDelay (clkena3_ipd, clkena(3), tipd_clkena(3));
VitalWireDelay (clkena4_ipd, clkena(4), tipd_clkena(4));
VitalWireDelay (clkena5_ipd, clkena(5), tipd_clkena(5));
VitalWireDelay (extclkena0_ipd, extclkena(0), tipd_extclkena(0));
VitalWireDelay (extclkena1_ipd, extclkena(1), tipd_extclkena(1));
VitalWireDelay (extclkena2_ipd, extclkena(2), tipd_extclkena(2));
VitalWireDelay (extclkena3_ipd, extclkena(3), tipd_extclkena(3));
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanaclr_ipd, scanaclr, tipd_scanaclr);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (comparator_ipd, comparator, tipd_comparator);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
-- User to Advanced parameter conversion
i_extclk3_counter <= "e3" when m=0 else extclk3_counter;
i_extclk2_counter <= "e2" when m=0 else extclk2_counter;
i_extclk1_counter <= "e1" when m=0 else extclk1_counter;
i_extclk0_counter <= "e0" when m=0 else extclk0_counter;
i_clk5_counter <= "l1" when m=0 else clk5_counter;
i_clk4_counter <= "l0" when m=0 else clk4_counter;
i_clk3_counter <= "g3" when m=0 else clk3_counter;
i_clk2_counter <= "g2" when m=0 else clk2_counter;
i_clk1_counter <= "g1" when m=0 else clk1_counter;
i_clk0_counter <= "l0" when m=0 and pll_type = "lvds" else
"g0" when m=0 else clk0_counter;
-- end parameter conversion
inclk_m <= extclk0_tmp when operation_mode = "external_feedback" and feedback_source = "extclk0" else
extclk1_tmp when operation_mode = "external_feedback" and feedback_source = "extclk1" else
extclk2_tmp when operation_mode = "external_feedback" and feedback_source = "extclk2" else
extclk3_tmp when operation_mode = "external_feedback" and feedback_source = "extclk3" else
vco_out(m_ph_val);
ext_fbk_cntr <= "e0" when (feedback_source = "extclk0" and extclk0_counter = "e0") or (feedback_source = "extclk1" and extclk1_counter = "e0") or (feedback_source = "extclk2" and extclk2_counter = "e0") or (feedback_source = "extclk3" and extclk3_counter = "e0") else
"e1" when (feedback_source = "extclk0" and extclk0_counter = "e1") or (feedback_source = "extclk1" and extclk1_counter = "e1") or (feedback_source = "extclk2" and extclk2_counter = "e1") or (feedback_source = "extclk3" and extclk3_counter = "e1") else
"e2" when (feedback_source = "extclk0" and extclk0_counter = "e2") or (feedback_source = "extclk1" and extclk1_counter = "e2") or (feedback_source = "extclk2" and extclk2_counter = "e2") or (feedback_source = "extclk3" and extclk3_counter = "e2") else
"e3" when (feedback_source = "extclk0" and extclk0_counter = "e3") or (feedback_source = "extclk1" and extclk1_counter = "e3") or (feedback_source = "extclk2" and extclk2_counter = "e3") or (feedback_source = "extclk3" and extclk3_counter = "e3") else
"e0";
ext_fbk_cntr_high <= e0_high_val when ext_fbk_cntr = "e0" else
e1_high_val when ext_fbk_cntr = "e1" else
e2_high_val when ext_fbk_cntr = "e2" else
e3_high_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_low <= e0_low_val when ext_fbk_cntr = "e0" else
e1_low_val when ext_fbk_cntr = "e1" else
e2_low_val when ext_fbk_cntr = "e2" else
e3_low_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_delay <= e0_time_delay_val when ext_fbk_cntr = "e0" else
e1_time_delay_val when ext_fbk_cntr = "e1" else
e2_time_delay_val when ext_fbk_cntr = "e2" else
e3_time_delay_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_ph <= e0_ph_val when ext_fbk_cntr = "e0" else
e1_ph_val when ext_fbk_cntr = "e1" else
e2_ph_val when ext_fbk_cntr = "e2" else
e3_ph_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_initial <= e0_initial_val when ext_fbk_cntr = "e0" else
e1_initial_val when ext_fbk_cntr = "e1" else
e2_initial_val when ext_fbk_cntr = "e2" else
e3_initial_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_mode <= e0_mode_val when ext_fbk_cntr = "e0" else
e1_mode_val when ext_fbk_cntr = "e1" else
e2_mode_val when ext_fbk_cntr = "e2" else
e3_mode_val when ext_fbk_cntr = "e3" else
e0_mode_val;
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
m1 : cyclone_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay,
ph => m_ph_val );
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
n1 : cyclone_n_cntr
port map ( clk => clkin,
reset => areset_ipd,
cout => refclk,
modulus => n_val,
time_delay => n_time_delay_val);
inclk_l0 <= vco_out(l0_ph_val);
l0 : cyclone_scale_cntr
port map ( clk => inclk_l0,
reset => areset_ena_sig,
cout => l0_clk,
initial => l0_initial_val,
high => l0_high_val,
low => l0_low_val,
mode => l0_mode_val,
time_delay => l0_time_delay_val,
ph_tap => l0_ph_val);
inclk_l1 <= vco_out(l1_ph_val);
l1 : cyclone_scale_cntr
port map ( clk => inclk_l1,
reset => areset_ena_sig,
cout => l1_clk,
initial => l1_initial_val,
high => l1_high_val,
low => l1_low_val,
mode => l1_mode_val,
time_delay => l1_time_delay_val,
ph_tap => l1_ph_val);
inclk_g0 <= vco_out(g0_ph_val);
g0 : cyclone_scale_cntr
port map ( clk => inclk_g0,
reset => areset_ena_sig,
cout => g0_clk,
initial => g0_initial_val,
high => g0_high_val,
low => g0_low_val,
mode => g0_mode_val,
time_delay => g0_time_delay_val,
ph_tap => g0_ph_val);
process(g0_clk, l0_clk, l1_clk)
begin
if (g0_clk'event and g0_clk = '1') then
dffa_out <= comparator_ipd;
end if;
if (l0_clk'event and l0_clk = '1' and enable0_counter = "l0") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
if (l1_clk'event and l1_clk = '1' and enable0_counter = "l1") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
end process;
nce_temp <= (not dffc_out) and dffb_out;
nce_l0 <= dffd_out when enable0_counter = "l0" else '0';
nce_l1 <= dffd_out when enable0_counter = "l1" else '0';
inclk_g1 <= vco_out(g1_ph_val);
g1 : cyclone_scale_cntr
port map ( clk => inclk_g1,
reset => areset_ena_sig,
cout => g1_clk,
initial => g1_initial_val,
high => g1_high_val,
low => g1_low_val,
mode => g1_mode_val,
time_delay => g1_time_delay_val,
ph_tap => g1_ph_val);
inclk_g2 <= vco_out(g2_ph_val);
g2 : cyclone_scale_cntr
port map ( clk => inclk_g2,
reset => areset_ena_sig,
cout => g2_clk,
initial => g2_initial_val,
high => g2_high_val,
low => g2_low_val,
mode => g2_mode_val,
time_delay => g2_time_delay_val,
ph_tap => g2_ph_val);
inclk_g3 <= vco_out(g3_ph_val);
g3 : cyclone_scale_cntr
port map ( clk => inclk_g3,
reset => areset_ena_sig,
cout => g3_clk,
initial => g3_initial_val,
high => g3_high_val,
low => g3_low_val,
mode => g3_mode_val,
time_delay => g3_time_delay_val,
ph_tap => g3_ph_val);
inclk_e0 <= vco_out(e0_ph_val);
cntr_e0_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else e0_initial_val;
cntr_e0_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else
e0_time_delay_val;
e0 : cyclone_scale_cntr
port map ( clk => inclk_e0,
reset => areset_ena_sig,
cout => e0_clk,
initial => cntr_e0_initial,
high => e0_high_val,
low => e0_low_val,
mode => e0_mode_val,
time_delay => cntr_e0_delay,
ph_tap => e0_ph_val);
inclk_e1 <= vco_out(e1_ph_val);
cntr_e1_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else e1_initial_val;
cntr_e1_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else
e1_time_delay_val;
e1 : cyclone_scale_cntr
port map ( clk => inclk_e1,
reset => areset_ena_sig,
cout => e1_clk,
initial => cntr_e1_initial,
high => e1_high_val,
low => e1_low_val,
mode => e1_mode_val,
time_delay => cntr_e1_delay,
ph_tap => e1_ph_val);
inclk_e2 <= vco_out(e2_ph_val);
cntr_e2_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else e2_initial_val;
cntr_e2_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else
e2_time_delay_val;
e2 : cyclone_scale_cntr
port map ( clk => inclk_e2,
reset => areset_ena_sig,
cout => e2_clk,
initial => cntr_e2_initial,
high => e2_high_val,
low => e2_low_val,
mode => e2_mode_val,
time_delay => cntr_e2_delay,
ph_tap => e2_ph_val);
inclk_e3 <= vco_out(e3_ph_val);
cntr_e3_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else e3_initial_val;
cntr_e3_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else
e3_time_delay_val;
e3 : cyclone_scale_cntr
port map ( clk => inclk_e3,
reset => areset_ena_sig,
cout => e3_clk,
initial => cntr_e3_initial,
high => e3_high_val,
low => e3_low_val,
mode => e3_mode_val,
time_delay => cntr_e3_delay,
ph_tap => e3_ph_val);
inclk_l0_dly1 <= inclk_l0;
inclk_l0_dly2 <= inclk_l0_dly1;
inclk_l0_dly3 <= inclk_l0_dly2;
inclk_l0_dly4 <= inclk_l0_dly3;
inclk_l0_dly5 <= inclk_l0_dly4;
inclk_l0_dly6 <= inclk_l0_dly5;
inclk_l1_dly1 <= inclk_l1;
inclk_l1_dly2 <= inclk_l1_dly1;
inclk_l1_dly3 <= inclk_l1_dly2;
inclk_l1_dly4 <= inclk_l1_dly3;
inclk_l1_dly5 <= inclk_l1_dly4;
inclk_l1_dly6 <= inclk_l1_dly5;
process(inclk_l0_dly6, inclk_l1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable l0_got_first_rising_edge : boolean := false;
variable l0_count : integer := 1;
variable l0_tmp, l1_tmp : std_logic := '0';
variable l1_got_first_rising_edge : boolean := false;
variable l1_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
l0_count := 1;
l1_count := 1;
l0_got_first_rising_edge := false;
l1_got_first_rising_edge := false;
else
if (nce_l0 = '0') then
if (not l0_got_first_rising_edge) then
if (inclk_l0_dly6'event and inclk_l0_dly6 = '1') then
l0_got_first_rising_edge := true;
end if;
elsif (inclk_l0_dly6'event) then
l0_count := l0_count + 1;
if (l0_count = (l0_high_val + l0_low_val) * 2) then
l0_count := 1;
end if;
end if;
end if;
if (inclk_l0_dly6'event and inclk_l0_dly6 = '0') then
if (l0_count = 1) then
l0_tmp := '1';
l0_got_first_rising_edge := false;
else
l0_tmp := '0';
end if;
end if;
if (nce_l1 = '0') then
if (not l1_got_first_rising_edge) then
if (inclk_l1_dly6'event and inclk_l1_dly6 = '1') then
l1_got_first_rising_edge := true;
end if;
elsif (inclk_l1_dly6'event) then
l1_count := l1_count + 1;
if (l1_count = (l1_high_val + l1_low_val) * 2) then
l1_count := 1;
end if;
end if;
end if;
if (inclk_l1_dly6'event and inclk_l1_dly6 = '0') then
if (l1_count = 1) then
l1_tmp := '1';
l1_got_first_rising_edge := false;
else
l1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "l0") then
enable0_tmp <= l0_tmp;
elsif (enable0_counter = "l1") then
enable0_tmp <= l1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "l0") then
enable1_tmp <= l0_tmp;
elsif (enable1_counter = "l1") then
enable1_tmp <= l1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (count = gate_lock_counter) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (transfer)
variable init : boolean := true;
variable low, high : std_logic_vector(8 downto 0);
variable delay_chain : std_logic_vector(3 downto 0);
variable mn_delay_chain : std_logic_vector(0 to 3);
variable mode : string(1 to 6) := "bypass";
variable delay_val : integer := 0;
variable is_error : boolean := false;
variable buf : line;
-- user to advanced variables
variable i_m_initial : natural;
variable i_m : integer := 1;
variable i_n : natural := 1;
variable i_m2 : natural;
variable i_n2 : natural;
variable i_ss : natural;
variable i_l0_high : natural;
variable i_l1_high : natural;
variable i_g0_high : natural;
variable i_g1_high : natural;
variable i_g2_high : natural;
variable i_g3_high : natural;
variable i_e0_high : natural;
variable i_e1_high : natural;
variable i_e2_high : natural;
variable i_e3_high : natural;
variable i_l0_low : natural;
variable i_l1_low : natural;
variable i_g0_low : natural;
variable i_g1_low : natural;
variable i_g2_low : natural;
variable i_g3_low : natural;
variable i_e0_low : natural;
variable i_e1_low : natural;
variable i_e2_low : natural;
variable i_e3_low : natural;
variable i_l0_initial : natural;
variable i_l1_initial : natural;
variable i_g0_initial : natural;
variable i_g1_initial : natural;
variable i_g2_initial : natural;
variable i_g3_initial : natural;
variable i_e0_initial : natural;
variable i_e1_initial : natural;
variable i_e2_initial : natural;
variable i_e3_initial : natural;
variable i_l0_mode : string(1 to 6);
variable i_l1_mode : string(1 to 6);
variable i_g0_mode : string(1 to 6);
variable i_g1_mode : string(1 to 6);
variable i_g2_mode : string(1 to 6);
variable i_g3_mode : string(1 to 6);
variable i_e0_mode : string(1 to 6);
variable i_e1_mode : string(1 to 6);
variable i_e2_mode : string(1 to 6);
variable i_e3_mode : string(1 to 6);
variable max_neg_abs : integer := 0;
variable i_l0_time_delay : natural;
variable i_l1_time_delay : natural;
variable i_g0_time_delay : natural;
variable i_g1_time_delay : natural;
variable i_g2_time_delay : natural;
variable i_g3_time_delay : natural;
variable i_e0_time_delay : natural;
variable i_e1_time_delay : natural;
variable i_e2_time_delay : natural;
variable i_e3_time_delay : natural;
variable i_m_time_delay : natural;
variable i_n_time_delay : natural;
variable i_l0_ph : natural;
variable i_l1_ph : natural;
variable i_g0_ph : natural;
variable i_g1_ph : natural;
variable i_g2_ph : natural;
variable i_g3_ph : natural;
variable i_e0_ph : natural;
variable i_e1_ph : natural;
variable i_e2_ph : natural;
variable i_e3_ph : natural;
variable i_m_ph : natural;
variable output_count : natural;
variable new_divisor : natural;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_extclk0_mult_by : integer := 1;
variable i_extclk0_div_by : integer := 1;
variable i_extclk1_mult_by : integer := 1;
variable i_extclk1_div_by : integer := 1;
variable i_extclk2_mult_by : integer := 1;
variable i_extclk2_div_by : integer := 1;
variable i_extclk3_mult_by : integer := 1;
variable i_extclk3_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
begin
if (init) then
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
i_n := 1;
if (pll_type = "lvds") then
i_m := clk0_multiply_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
i_extclk0_mult_by,
i_extclk1_mult_by, i_extclk2_mult_by,
i_extclk3_mult_by, inclk0_input_frequency);
end if;
i_m_time_delay := maxnegabs ( str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
i_n_time_delay := mintimedelay(str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
if (pll_type = "lvds") then
i_g0_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
else
i_g0_time_delay := counter_time_delay ( str2int(clk0_time_delay),
i_m_time_delay,i_n_time_delay);
end if;
i_g1_time_delay := counter_time_delay ( str2int(clk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_g2_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_g3_time_delay := counter_time_delay ( str2int(clk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "lvds") then
i_l0_time_delay := i_g0_time_delay;
i_l1_time_delay := i_g0_time_delay;
else
i_l0_time_delay := counter_time_delay ( str2int(clk4_time_delay),
i_m_time_delay, i_n_time_delay);
i_l1_time_delay := counter_time_delay ( str2int(clk5_time_delay),
i_m_time_delay, i_n_time_delay);
end if;
i_e0_time_delay := counter_time_delay ( str2int(extclk0_time_delay),
i_m_time_delay, i_n_time_delay);
i_e1_time_delay := counter_time_delay ( str2int(extclk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_e2_time_delay := counter_time_delay ( str2int(extclk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_e3_time_delay := counter_time_delay ( str2int(extclk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(extclk0_phase_shift),
str2int(extclk1_phase_shift),
str2int(extclk2_phase_shift),
str2int(extclk3_phase_shift));
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
else
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_g1_ph := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g2_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_ph := i_g0_ph;
i_l1_ph := i_g0_ph;
else
i_l0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_l1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_e0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e2_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_high := counter_high ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_high := counter_high ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_high := counter_high ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_high := i_g0_high;
i_l1_high := i_g0_high;
else
i_l0_high := counter_high ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_high := counter_high ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_high := counter_high ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_high := counter_high ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_high := counter_high ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_high := counter_high ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (pll_type = "lvds") then
i_g0_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_low := counter_low ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_low := counter_low ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_low := counter_low ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_low := i_g0_low;
i_l1_low := i_g0_low;
else
i_l0_low := counter_low ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_low := counter_low ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_low := counter_low ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_low := counter_low ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_low := counter_low ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_low := counter_low ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
if (pll_type = "lvds") then
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
else
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_g1_initial := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g2_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_initial := i_g0_initial;
i_l1_initial := i_g0_initial;
else
i_l0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_l1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_e0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e2_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
else
i_g0_mode := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
end if;
i_g1_mode := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_g2_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_g3_mode := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
if (pll_type = "lvds") then
i_l0_mode := "bypass";
i_l1_mode := "bypass";
else
i_l0_mode := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_l1_mode := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
end if;
i_e0_mode := counter_mode(extclk0_duty_cycle, output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
i_e1_mode := counter_mode(extclk1_duty_cycle, output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
i_e2_mode := counter_mode(extclk2_duty_cycle, output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
i_e3_mode := counter_mode(extclk3_duty_cycle, output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (feedback_source = "extclk0") then
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
elsif (feedback_source = "extclk1") then
if (i_e1_mode = "bypass") then
output_count := 1;
else
output_count := i_e1_high + i_e1_low;
end if;
elsif (feedback_source = "extclk2") then
if (i_e2_mode = "bypass") then
output_count := 1;
else
output_count := i_e2_high + i_e2_low;
end if;
elsif (feedback_source = "extclk3") then
if (i_e3_mode = "bypass") then
output_count := 1;
else
output_count := i_e3_high + i_e3_low;
end if;
else -- default to e0
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_time_delay := m_time_delay;
i_n_time_delay := n_time_delay;
i_l0_time_delay := l0_time_delay;
i_l1_time_delay := l1_time_delay;
i_g0_time_delay := g0_time_delay;
i_g1_time_delay := g1_time_delay;
i_g2_time_delay := g2_time_delay;
i_g3_time_delay := g3_time_delay;
i_e0_time_delay := e0_time_delay;
i_e1_time_delay := e1_time_delay;
i_e2_time_delay := e2_time_delay;
i_e3_time_delay := e3_time_delay;
i_m_ph := m_ph;
i_l0_ph := l0_ph;
i_l1_ph := l1_ph;
i_g0_ph := g0_ph;
i_g1_ph := g1_ph;
i_g2_ph := g2_ph;
i_g3_ph := g3_ph;
i_e0_ph := e0_ph;
i_e1_ph := e1_ph;
i_e2_ph := e2_ph;
i_e3_ph := e3_ph;
i_l0_high := l0_high;
i_l1_high := l1_high;
i_g0_high := g0_high;
i_g1_high := g1_high;
i_g2_high := g2_high;
i_g3_high := g3_high;
i_e0_high := e0_high;
i_e1_high := e1_high;
i_e2_high := e2_high;
i_e3_high := e3_high;
i_l0_low := l0_low;
i_l1_low := l1_low;
i_g0_low := g0_low;
i_g1_low := g1_low;
i_g2_low := g2_low;
i_g3_low := g3_low;
i_e0_low := e0_low;
i_e1_low := e1_low;
i_e2_low := e2_low;
i_e3_low := e3_low;
i_l0_initial := l0_initial;
i_l1_initial := l1_initial;
i_g0_initial := g0_initial;
i_g1_initial := g1_initial;
i_g2_initial := g2_initial;
i_g3_initial := g3_initial;
i_e0_initial := e0_initial;
i_e1_initial := e1_initial;
i_e2_initial := e2_initial;
i_e3_initial := e3_initial;
i_l0_mode := translate_string(l0_mode);
i_l1_mode := translate_string(l1_mode);
i_g0_mode := translate_string(g0_mode);
i_g1_mode := translate_string(g1_mode);
i_g2_mode := translate_string(g2_mode);
i_g3_mode := translate_string(g3_mode);
i_e0_mode := translate_string(e0_mode);
i_e1_mode := translate_string(e1_mode);
i_e2_mode := translate_string(e2_mode);
i_e3_mode := translate_string(e3_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val_tmp <= i_n;
m_val_tmp <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
end if;
-- NOTE: m_time_delay (vco time delay) not supported for external
-- feedback mode
-- in feedback mode, m_time_delay = delay of feedback loop tap
m_time_delay_val <= i_m_time_delay;
n_time_delay_val <= i_n_time_delay;
m_ph_val <= i_m_ph;
m2_val <= m2;
n2_val <= n2;
if (m2 = 1) then
m2_mode_val <= "bypass";
end if;
if (n2 = 1) then
n2_mode_val <= "bypass";
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
m_initial_val <= 1;
m_time_delay_val <= 0;
m_ph_val <= 0;
end if;
l0_ph_val <= i_l0_ph;
l1_ph_val <= i_l1_ph;
g0_ph_val <= i_g0_ph;
g1_ph_val <= i_g1_ph;
g2_ph_val <= i_g2_ph;
g3_ph_val <= i_g3_ph;
e0_ph_val <= i_e0_ph;
e1_ph_val <= i_e1_ph;
e2_ph_val <= i_e2_ph;
e3_ph_val <= i_e3_ph;
l0_initial_val <= i_l0_initial;
l0_high_val <= i_l0_high;
l0_low_val <= i_l0_low;
l0_mode_val <= i_l0_mode;
l0_time_delay_val <= i_l0_time_delay;
l1_initial_val <= i_l1_initial;
l1_high_val <= i_l1_high;
l1_low_val <= i_l1_low;
l1_mode_val <= i_l1_mode;
l1_time_delay_val <= i_l1_time_delay;
g0_initial_val <= i_g0_initial;
g0_high_val <= i_g0_high;
g0_low_val <= i_g0_low;
g0_mode_val <= i_g0_mode;
g0_time_delay_val <= i_g0_time_delay;
g1_initial_val <= i_g1_initial;
g1_high_val <= i_g1_high;
g1_low_val <= i_g1_low;
g1_mode_val <= i_g1_mode;
g1_time_delay_val <= i_g1_time_delay;
g2_initial_val <= i_g2_initial;
g2_high_val <= i_g2_high;
g2_low_val <= i_g2_low;
g2_mode_val <= i_g2_mode;
g2_time_delay_val <= i_g2_time_delay;
g3_initial_val <= i_g3_initial;
g3_high_val <= i_g3_high;
g3_low_val <= i_g3_low;
g3_mode_val <= i_g3_mode;
g3_time_delay_val <= i_g3_time_delay;
if (scan_chain = "long") then
e0_initial_val <= i_e0_initial;
e0_high_val <= i_e0_high;
e0_low_val <= i_e0_low;
e0_mode_val <= i_e0_mode;
e0_time_delay_val <= i_e0_time_delay;
e1_initial_val <= i_e1_initial;
e1_high_val <= i_e1_high;
e1_low_val <= i_e1_low;
e1_mode_val <= i_e1_mode;
e1_time_delay_val <= i_e1_time_delay;
e2_initial_val <= i_e2_initial;
e2_high_val <= i_e2_high;
e2_low_val <= i_e2_low;
e2_mode_val <= i_e2_mode;
e2_time_delay_val <= i_e2_time_delay;
e3_initial_val <= i_e3_initial;
e3_high_val <= i_e3_high;
e3_low_val <= i_e3_low;
e3_mode_val <= i_e3_mode;
e3_time_delay_val <= i_e3_time_delay;
scan_chain_length <= EGPP_SCAN_CHAIN;
end if;
init := false;
done_with_param_calc <= true;
elsif (transfer'event and transfer = '1') then
reconfig_err <= false;
ASSERT false REPORT "Reconfiguring PLL" severity note;
if (scan_chain = "long") then
-- cntr e3
delay_chain := scan_data(287 downto 284);
if (scan_data(273) = '1') then
e3_mode_val <= "bypass";
if (scan_data(283) = '1') then
e3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(283) = '1') then
e3_mode_val <= " odd";
else
e3_mode_val <= " even";
end if;
high := scan_data(272 downto 264);
low := scan_data(282 downto 274);
e3_low_val <= alt_conv_integer(low);
e3_high_val <= alt_conv_integer(high);
-- count value of 0 is actually 512
if (alt_conv_integer(high) = 0) then
e3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e3_time_delay_val <= delay_val;
-- cntr e2
delay_chain := scan_data(263 downto 260);
if (scan_data(249) = '1') then
e2_mode_val <= "bypass";
if (scan_data(259) = '1') then
e2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(259) = '1') then
e2_mode_val <= " odd";
else
e2_mode_val <= " even";
end if;
high := scan_data(248 downto 240);
low := scan_data(258 downto 250);
e2_low_val <= alt_conv_integer(low);
e2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e2_time_delay_val <= delay_val;
-- cntr e1
delay_chain := scan_data(239 downto 236);
if (scan_data(225) = '1') then
e1_mode_val <= "bypass";
if (scan_data(235) = '1') then
e1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(235) = '1') then
e1_mode_val <= " odd";
else
e1_mode_val <= " even";
end if;
high := scan_data(224 downto 216);
low := scan_data(234 downto 226);
e1_low_val <= alt_conv_integer(low);
e1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e1_time_delay_val <= delay_val;
-- cntr e0
delay_chain := scan_data(215 downto 212);
if (scan_data(201) = '1') then
e0_mode_val <= "bypass";
if (scan_data(211) = '1') then
e0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(211) = '1') then
e0_mode_val <= " odd";
else
e0_mode_val <= " even";
end if;
high := scan_data(200 downto 192);
low := scan_data(210 downto 202);
e0_low_val <= alt_conv_integer(low);
e0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e0_time_delay_val <= delay_val;
end if;
-- cntr l1
delay_chain := scan_data(191 downto 188);
if (scan_data(177) = '1') then
l1_mode_val <= "bypass";
if (scan_data(187) = '1') then
l1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(187) = '1') then
l1_mode_val <= " odd";
else
l1_mode_val <= " even";
end if;
high := scan_data(176 downto 168);
low := scan_data(186 downto 178);
l1_low_val <= alt_conv_integer(low);
l1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l1_time_delay_val <= delay_val;
-- cntr l0
delay_chain := scan_data(167 downto 164);
if (scan_data(153) = '1') then
l0_mode_val <= "bypass";
if (scan_data(163) = '1') then
l0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(163) = '1') then
l0_mode_val <= " odd";
else
l0_mode_val <= " even";
end if;
high := scan_data(152 downto 144);
low := scan_data(162 downto 154);
l0_low_val <= alt_conv_integer(low);
l0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l0_time_delay_val <= delay_val;
-- cntr g3
delay_chain := scan_data(143 downto 140);
if (scan_data(129) = '1') then
g3_mode_val <= "bypass";
if (scan_data(139) = '1') then
g3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(139) = '1') then
g3_mode_val <= " odd";
else
g3_mode_val <= " even";
end if;
high := scan_data(128 downto 120);
low := scan_data(138 downto 130);
g3_low_val <= alt_conv_integer(low);
g3_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g3_time_delay_val <= delay_val;
-- cntr g2
delay_chain := scan_data(119 downto 116);
if (scan_data(105) = '1') then
g2_mode_val <= "bypass";
if (scan_data(115) = '1') then
g2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(115) = '1') then
g2_mode_val <= " odd";
else
g2_mode_val <= " even";
end if;
high := scan_data(104 downto 96);
low := scan_data(114 downto 106);
g2_low_val <= alt_conv_integer(low);
g2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g2_time_delay_val <= delay_val;
-- cntr g1
delay_chain := scan_data(95 downto 92);
if (scan_data(81) = '1') then
g1_mode_val <= "bypass";
if (scan_data(91) = '1') then
g1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(91) = '1') then
g1_mode_val <= " odd";
else
g1_mode_val <= " even";
end if;
high := scan_data(80 downto 72);
low := scan_data(90 downto 82);
g1_low_val <= alt_conv_integer(low);
g1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g1_time_delay_val <= delay_val;
-- cntr g0
delay_chain := scan_data(71 downto 68);
if (scan_data(57) = '1') then
g0_mode_val <= "bypass";
if (scan_data(67) = '1') then
g0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(67) = '1') then
g0_mode_val <= " odd";
else
g0_mode_val <= " even";
end if;
high := scan_data(56 downto 48);
low := scan_data(66 downto 58);
g0_low_val <= alt_conv_integer(low);
g0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g0_time_delay_val <= delay_val;
-- cntr M
is_error := false;
-- 'low' contains modulus for m_cntr(spread_spectrum disabled)
low := scan_data(32 downto 24);
m_val_tmp <= alt_conv_integer(low);
if (scan_data(33) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m_val_tmp <= 512;
end if;
if (not is_error) then
if (m_mode_val = "bypass") then
ASSERT false REPORT "M counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m_mode_val <= " ";
end if;
elsif (scan_data(33) = '1') then
if (scan_data(24) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val /= "bypass") then
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M modulus = "));
write (buf, 1);
writeline (output, buf);
m_val_tmp <= 1;
m_mode_val <= "bypass";
end if;
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
ASSERT FALSE REPORT "VCO is bypassed, setting M modulus = 1, M time delay = 0" severity note;
end if;
-- cntr M2
if (ss > 0) then
is_error := false;
low := scan_data(42 downto 34);
m2_val <= alt_conv_integer(low);
if (scan_data(43) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M2 counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m2_val <= 512;
end if;
if (not is_error) then
if (m2_mode_val = "bypass") then
ASSERT false REPORT "M2 counter switched from BYPASS mode to enabled (M2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m2_mode_val <= " ";
end if;
elsif (scan_data(43) = '1') then
if (scan_data(34) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m2_mode_val /= "bypass") then
ASSERT false REPORT "M2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M2 modulus = "));
write (buf, 1);
writeline (output, buf);
m2_val <= 1;
m2_mode_val <= "bypass";
end if;
end if;
if (m_mode_val /= m2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for M1/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(47 downto 44);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
m_time_delay_val <= delay_val;
if (skip_vco = "on") then
m_time_delay_val <= 0;
delay_val := 0;
end if;
write (buf, string'(" M time delay = "));
write (buf, delay_val);
writeline (output, buf);
-- cntr N
is_error := false;
-- 'low' contains modulus for n_cntr(spread_spectrum disabled)
low := scan_data(8 downto 0);
n_val_tmp <= alt_conv_integer(low);
if (scan_data(9) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n_val_tmp <= 512;
write (buf, string'(" N modulus = "));
write (buf, 512);
writeline (output, buf);
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
if (not is_error) then
if (n_mode_val = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n_mode_val <= " ";
end if;
elsif (scan_data(9) = '1') then
if (scan_data(0) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val /= "bypass") then
ASSERT false REPORT "N counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N modulus = "));
write (buf, 1);
writeline (output, buf);
n_val_tmp <= 1;
n_mode_val <= "bypass";
end if;
end if;
-- cntr N2
if (ss > 0) then
is_error := false;
low := scan_data(18 downto 10);
n2_val <= alt_conv_integer(low);
if (scan_data(19) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N2 counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n2_val <= 512;
end if;
if (not is_error) then
if (n2_mode_val = "bypass") then
ASSERT false REPORT "N2 counter switched from BYPASS mode to enabled (N2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n2_mode_val <= " ";
end if;
elsif (scan_data(19) = '1') then
if (scan_data(10) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n2_mode_val /= "bypass") then
ASSERT false REPORT "N2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N2 modulus = "));
write (buf, 1);
writeline (output, buf);
n2_val <= 1;
n2_mode_val <= "bypass";
end if;
end if;
if (n_mode_val /= n2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for N1/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(23 downto 20);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
n_time_delay_val <= delay_val;
write (buf, string'(" N time delay = "));
write (buf, delay_val);
writeline (output, buf);
else
if (scan_chain = "long") then
write (buf, string'(" E3 high = "));
write (buf, e3_high_val);
write (buf, string'(" , E3 low = "));
write (buf, e3_low_val);
write (buf, string'(" , E3 mode = "));
write (buf, e3_mode_val);
write (buf, string'(" , E3 time delay = "));
write (buf, e3_time_delay_val);
writeline(output, buf);
write (buf, string'(" E2 high = "));
write (buf, e2_high_val);
write (buf, string'(" , E2 low = "));
write (buf, e2_low_val);
write (buf, string'(" , E2 mode = "));
write (buf, e2_mode_val);
write (buf, string'(" , E2 time delay = "));
write (buf, e2_time_delay_val);
writeline(output, buf);
write (buf, string'(" E1 high = "));
write (buf, e1_high_val);
write (buf, string'(" , E1 low = "));
write (buf, e1_low_val);
write (buf, string'(" , E1 mode = "));
write (buf, e1_mode_val);
write (buf, string'(" , E1 time delay = "));
write (buf, e1_time_delay_val);
writeline(output, buf);
write (buf, string'(" E0 high = "));
write (buf, e0_high_val);
write (buf, string'(" , E0 low = "));
write (buf, e0_low_val);
write (buf, string'(" , E0 mode = "));
write (buf, e0_mode_val);
write (buf, string'(" , E0 time delay = "));
write (buf, e0_time_delay_val);
writeline(output, buf);
end if;
write (buf, string'(" L1 high = "));
write (buf, l1_high_val);
write (buf, string'(" , L1 low = "));
write (buf, l1_low_val);
write (buf, string'(" , L1 mode = "));
write (buf, l1_mode_val);
write (buf, string'(" , L1 time delay = "));
write (buf, l1_time_delay_val);
writeline(output, buf);
write (buf, string'(" L0 high = "));
write (buf, l0_high_val);
write (buf, string'(" , L0 low = "));
write (buf, l0_low_val);
write (buf, string'(" , L0 mode = "));
write (buf, l0_mode_val);
write (buf, string'(" , L0 time delay = "));
write (buf, l0_time_delay_val);
writeline(output, buf);
write (buf, string'(" G3 high = "));
write (buf, g3_high_val);
write (buf, string'(" , G3 low = "));
write (buf, g3_low_val);
write (buf, string'(" , G3 mode = "));
write (buf, g3_mode_val);
write (buf, string'(" , G3 time delay = "));
write (buf, g3_time_delay_val);
writeline(output, buf);
write (buf, string'(" G2 high = "));
write (buf, g2_high_val);
write (buf, string'(" , G2 low = "));
write (buf, g2_low_val);
write (buf, string'(" , G2 mode = "));
write (buf, g2_mode_val);
write (buf, string'(" , G2 time delay = "));
write (buf, g2_time_delay_val);
writeline(output, buf);
write (buf, string'(" G1 high = "));
write (buf, g1_high_val);
write (buf, string'(" , G1 low = "));
write (buf, g1_low_val);
write (buf, string'(" , G1 mode = "));
write (buf, g1_mode_val);
write (buf, string'(" , G1 time delay = "));
write (buf, g1_time_delay_val);
writeline(output, buf);
write (buf, string'(" G0 high = "));
write (buf, g0_high_val);
write (buf, string'(" , G0 low = "));
write (buf, g0_low_val);
write (buf, string'(" , G0 mode = "));
write (buf, g0_mode_val);
write (buf, string'(" , G0 time delay = "));
write (buf, g0_time_delay_val);
writeline(output, buf);
end if;
end process;
process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, inclk0_ipd, inclk1_ipd, clkswitch_ipd, done_with_param_calc)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable primary_clock_frequency : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable schedule_offset : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_ext_fbk_cntr : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable init_clks : boolean := true;
variable ext_fbk_cntr_modulus : integer := 1;
variable pll_is_in_reset : boolean := false;
-- clkswitch variables
variable other_clock_value : std_logic := '0';
variable other_clock_last_value : std_logic;
variable current_clock : string(1 to 6) := primary_clock;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (init and done_with_param_calc) then
if (pll_type = "fast") then
locked_tmp := '1';
end if;
m_val <= m_val_tmp;
n_val <= n_val_tmp;
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
-- merged from separate process
if (now = 0 ps) then
if (current_clock = "inclk1") then
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
external_switch := true;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
if (current_clock /= "inclk0") then
other_clock_value := inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event) then
if (current_clock /= "inclk1") then
other_clock_value := inclk1_ipd;
end if;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
if (current_clock = "inclk0") then
current_clk_is_bad := false;
end if;
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = "inclk1") then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_ipd'event and inclk1_ipd = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
if (current_clock = "inclk1") then
current_clk_is_bad := false;
end if;
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = "inclk0") then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if ((primary_clock = "inclk0" and clk0_is_bad = '1') or (primary_clock = "inclk1" and clk1_is_bad = '1')) then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = "inclk0") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event and current_clock = "inclk1") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_ipd;
end if;
else
clkin <= transport inclk1_ipd;
end if;
end if;
if (inclk0_ipd'event or inclk1_ipd'event) then
if ( (other_clock_value = '1') and
(other_clock_value /= other_clock_last_value) and
(switch_over_on_lossclk = "on") and
(enable_switch_over_counter = "on") and
(primary_clk_is_bad) ) then
switch_over_count := switch_over_count + 1;
end if;
if ((other_clock_value = '0') and (other_clock_value /= other_clock_last_value)) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = "inclk0") then
current_clock := "inclk1";
else
current_clock := "inclk0";
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
other_clock_last_value := other_clock_value;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
-- end -- clkswitch
if (schedule_vco'event) then
if (init_clks) then
if (primary_clock = "inclk0") then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk0_input_frequency * 1 ps;
elsif (primary_clock = "inclk1") then
refclk_period := inclk1_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk1_input_frequency * 1 ps;
end if;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
end if;
-- areset deasserted
if (areset_ipd'event and areset_ipd = '0') then
if (scandataout_tmp = '1') then
sdataout_rst_trig <= transport not sdataout_rst_trig;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
end if;
if (schedule_vco'event and (areset_ipd = '1' or ena_ipd = '0' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
schedule_offset := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or ena_ipd'event or areset_ipd'event) and areset_ipd = '0' and ena_ipd = '1' and (not stop_vco) and (now > 0 ps)) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
loop_time_delay := m_time_delay_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * (ext_fbk_cntr_modulus));
loop_time_delay := m_time_delay_val + ext_fbk_cntr_delay;
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_ext_fbk_cntr := ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier)/1 ps + fbk_phase;
while (pull_back_ext_fbk_cntr > refclk_period/1 ps) loop
pull_back_ext_fbk_cntr := pull_back_ext_fbk_cntr - refclk_period/ 1 ps;
end loop;
pull_back_M := m_time_delay_val + (m_initial_val - 1) * (ext_fbk_cntr_modulus) * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_ext_fbk_cntr := 0;
pull_back_M := initial_delay/1 ps + m_time_delay_val + fbk_phase;
end if;
total_pull_back := pull_back_M + pull_back_ext_fbk_cntr;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
ext_fbk_delay <= transport (pull_back_ext_fbk_cntr - fbk_phase) after 1 ps;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- add offset
if (schedule_offset) then
sched_time := sched_time + offset;
schedule_offset := false;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
if (sched_time > 0 ps) then
schedule_vco <= transport not schedule_vco after sched_time;
end if;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
n_val <= n_val_tmp;
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ((vco_max /= 0 and vco_min /= 0 and skip_vco = "off" and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
-- unlock
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert false report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= transport m_val_tmp after 1 ps;
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ((now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert (quiet_period_violation) report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
if (pll_type = "fast") then
locked_tmp := '0';
end if;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert (quiet_period_violation) report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped; do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
locked_tmp := 'X';
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (quiet_period_violation or reconfig_err or scanclr_violation or scanclr_clk_violation) then
lock <= '0';
if (pll_type = "fast") then
lock <= '1';
end if;
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
sig_current_clock <= current_clock;
-- signals for debugging
sig_offset <= offset;
sig_refclk_time <= refclk_time;
sig_fbclk_time <= fbclk_time;
sig_fbclk_period <= fbclk_period;
sig_vco_period_was_phase_adjusted <= vco_period_was_phase_adjusted;
sig_phase_adjust_was_scheduled <= phase_adjust_was_scheduled;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
sig_m_times_vco_period <= m_times_vco_period;
sig_new_m_times_vco_period <= new_m_times_vco_period;
sig_got_refclk_posedge <= got_refclk_posedge;
sig_got_fbclk_posedge <= got_fbclk_posedge;
sig_got_second_refclk <= got_second_refclk;
end process;
process (scanclk_ipd, scanaclr_ipd, scan_data, transfer, sdataout_trig, sdataout_rst_trig)
variable j : integer := 0;
variable pll_in_quiet_period : boolean := false;
variable start_quiet_time : time := 0 ps;
variable quiet_time : time := 0 ps;
variable scanclr_rising_time : time := 0 ps;
variable scanclr_falling_time : time := 0 ps;
variable got_first_scanclk_after_scanclr_inactive_edge : boolean := false;
variable scan_chain_being_reset : boolean := false;
function slowest_clk ( L0 : integer; L0_mode : string(1 to 6);
L1 : integer; L1_mode : string(1 to 6);
G0 : integer; G0_mode : string(1 to 6);
G1 : integer; G1_mode : string(1 to 6);
G2 : integer; G2_mode : string(1 to 6);
G3 : integer; G3_mode : string(1 to 6);
E0 : integer; E0_mode : string(1 to 6);
E1 : integer; E1_mode : string(1 to 6);
E2 : integer; E2_mode : string(1 to 6);
E3 : integer; E3_mode : string(1 to 6);
scan_chain : string;
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (L0_mode /= "bypass" and L0_mode /= " off") then
max_modulus := L0;
end if;
if (L1 > max_modulus and L1_mode /= "bypass" and L1_mode /= " off") then
max_modulus := L1;
end if;
if (G0 > max_modulus and G0_mode /= "bypass" and G0_mode /= " off") then
max_modulus := G0;
end if;
if (G1 > max_modulus and G1_mode /= "bypass" and G1_mode /= " off") then
max_modulus := G1;
end if;
if (G2 > max_modulus and G2_mode /= "bypass" and G2_mode /= " off") then
max_modulus := G2;
end if;
if (G3 > max_modulus and G3_mode /= "bypass" and G3_mode /= " off") then
max_modulus := G3;
end if;
if (scan_chain = "long") then
if (E0 > max_modulus and E0_mode /= "bypass" and E0_mode /= " off") then
max_modulus := E0;
end if;
if (E1 > max_modulus and E1_mode /= "bypass" and E1_mode /= " off") then
max_modulus := E1;
end if;
if (E2 > max_modulus and E2_mode /= "bypass" and E2_mode /= " off") then
max_modulus := E2;
end if;
if (E3 > max_modulus and E3_mode /= "bypass" and E3_mode /= " off") then
max_modulus := E3;
end if;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := ((refclk_int/m_mod) * max_modulus) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
begin
if (transfer'event) then
if (transfer = '0') then
-- clear the chain
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
elsif (scanaclr_ipd'event and scanaclr_ipd = '1') then
-- scanaclr rising
scanclr_rising_time := now;
scan_chain_being_reset := true;
elsif (scanaclr_ipd'event and scanaclr_ipd = '0') then
-- scanaclr falling
scanclr_falling_time := now;
if (scan_chain_being_reset and (now - scanclr_rising_time < TRST)) then
scanclr_violation <= true;
ASSERT false REPORT "Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is "& int2str((now - scanclr_rising_time) / 1 ps) &". The PLL may not function correctly." severity warning;
else
scanclr_violation <= false;
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
scan_chain_being_reset := false;
got_first_scanclk_after_scanclr_inactive_edge := false;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and not got_first_scanclk_after_scanclr_inactive_edge and (now - scanclr_falling_time < TRSTCLK)) then
scanclr_clk_violation <= true;
got_first_scanclk_after_scanclr_inactive_edge := true;
ASSERT false REPORT "Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is "& int2str((now - scanclr_falling_time) / 1 ps) &". Reconfiguration may not work." severity warning;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
else
pll_in_quiet_period := false;
for j in scan_chain_length-1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
if (not got_first_scanclk_after_scanclr_inactive_edge) then
got_first_scanclk_after_scanclr_inactive_edge := true;
scanclr_clk_violation <= false;
end if;
elsif (scanclk_ipd'event and scanclk_ipd = '0' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
elsif (scan_data(scan_chain_length-1) = '1') then
-- reset violation flag only after another reconfig seq.
quiet_period_violation <= false;
-- initiate transfer
transfer <= '1';
transfer <= transport '0' after 1 ps;
scandataout_tmp <= '1';
pll_in_quiet_period := true;
start_quiet_time := now;
quiet_time := slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
scan_chain, sig_refclk_period, m_val);
sdataout_trig <= transport not sdataout_trig after quiet_time;
end if;
elsif (sdataout_trig'event) then
if (areset_ipd = '0') then
scandataout_tmp <= transport '0';
end if;
elsif (sdataout_rst_trig'event) then
scandataout_tmp <= transport '0' after quiet_time;
end if;
end process;
clk0_tmp <= l0_clk when i_clk0_counter = "l0" else
l1_clk when i_clk0_counter = "l1" else
g0_clk when i_clk0_counter = "g0" else
g1_clk when i_clk0_counter = "g1" else
g2_clk when i_clk0_counter = "g2" else
g3_clk when i_clk0_counter = "g3" else
'0';
not_clk0_tmp <= not clk0_tmp;
ena0_reg : cyclone_dffe
port map ( D => clkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0_tmp,
Q => ena0 );
clk(0) <= ena0 and clk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena0 and 'X';
clk1_tmp <= l0_clk when i_clk1_counter = "l0" else
l1_clk when i_clk1_counter = "l1" else
g0_clk when i_clk1_counter = "g0" else
g1_clk when i_clk1_counter = "g1" else
g2_clk when i_clk1_counter = "g2" else
g3_clk when i_clk1_counter = "g3" else
'0';
not_clk1_tmp <= not clk1_tmp;
ena1_reg : cyclone_dffe
port map ( D => clkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk1_tmp,
Q => ena1 );
clk(1) <= ena1 and clk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena1 and 'X';
clk2_tmp <= l0_clk when i_clk2_counter = "l0" else
l1_clk when i_clk2_counter = "l1" else
g0_clk when i_clk2_counter = "g0" else
g1_clk when i_clk2_counter = "g1" else
g2_clk when i_clk2_counter = "g2" else
g3_clk when i_clk2_counter = "g3" else
'0';
not_clk2_tmp <= not clk2_tmp;
ena2_reg : cyclone_dffe
port map ( D => clkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk2_tmp,
Q => ena2 );
clk(2) <= ena2 and clk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena2 and 'X';
clk3_tmp <= l0_clk when i_clk3_counter = "l0" else
l1_clk when i_clk3_counter = "l1" else
g0_clk when i_clk3_counter = "g0" else
g1_clk when i_clk3_counter = "g1" else
g2_clk when i_clk3_counter = "g2" else
g3_clk when i_clk3_counter = "g3" else
'0';
not_clk3_tmp <= not clk3_tmp;
ena3_reg : cyclone_dffe
port map ( D => clkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk3_tmp,
Q => ena3 );
clk(3) <= ena3 and clk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena3 and 'X';
clk4_tmp <= l0_clk when i_clk4_counter = "l0" else
l1_clk when i_clk4_counter = "l1" else
g0_clk when i_clk4_counter = "g0" else
g1_clk when i_clk4_counter = "g1" else
g2_clk when i_clk4_counter = "g2" else
g3_clk when i_clk4_counter = "g3" else
'0';
not_clk4_tmp <= not clk4_tmp;
ena4_reg : cyclone_dffe
port map ( D => clkena(4),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk4_tmp,
Q => ena4 );
clk(4) <= ena4 and clk4_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena4 and 'X';
clk5_tmp <= l0_clk when i_clk5_counter = "l0" else
l1_clk when i_clk5_counter = "l1" else
g0_clk when i_clk5_counter = "g0" else
g1_clk when i_clk5_counter = "g1" else
g2_clk when i_clk5_counter = "g2" else
g3_clk when i_clk5_counter = "g3" else
'0';
not_clk5_tmp <= not clk5_tmp;
ena5_reg : cyclone_dffe
port map ( D => clkena(5),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk5_tmp,
Q => ena5 );
clk(5) <= ena5 and clk5_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena5 and 'X';
extclk0_tmp <= e0_clk when i_extclk0_counter = "e0" else
e1_clk when i_extclk0_counter = "e1" else
e2_clk when i_extclk0_counter = "e2" else
e3_clk when i_extclk0_counter = "e3" else
g0_clk when i_extclk0_counter = "g0" else
'0';
not_extclk0_tmp <= not extclk0_tmp;
extena0_reg : cyclone_dffe
port map ( D => extclkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk0_tmp,
Q => extena0 );
extclk(0) <= extena0 and extclk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena0 and 'X';
extclk1_tmp <= e0_clk when i_extclk1_counter = "e0" else
e1_clk when i_extclk1_counter = "e1" else
e2_clk when i_extclk1_counter = "e2" else
e3_clk when i_extclk1_counter = "e3" else
g0_clk when i_extclk1_counter = "g0" else
'0';
not_extclk1_tmp <= not extclk1_tmp;
extena1_reg : cyclone_dffe
port map ( D => extclkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk1_tmp,
Q => extena1 );
extclk(1) <= extena1 and extclk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena1 and 'X';
extclk2_tmp <= e0_clk when i_extclk2_counter = "e0" else
e1_clk when i_extclk2_counter = "e1" else
e2_clk when i_extclk2_counter = "e2" else
e3_clk when i_extclk2_counter = "e3" else
g0_clk when i_extclk2_counter = "g0" else
'0';
not_extclk2_tmp <= not extclk2_tmp;
extena2_reg : cyclone_dffe
port map ( D => extclkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk2_tmp,
Q => extena2 );
extclk(2) <= extena2 and extclk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena2 and 'X';
extclk3_tmp <= e0_clk when i_extclk3_counter = "e0" else
e1_clk when i_extclk3_counter = "e1" else
e2_clk when i_extclk3_counter = "e2" else
e3_clk when i_extclk3_counter = "e3" else
g0_clk when i_extclk3_counter = "g0" else
'0';
not_extclk3_tmp <= not extclk3_tmp;
extena3_reg : cyclone_dffe
port map ( D => extclkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk3_tmp,
Q => extena3 );
extclk(3) <= extena3 and extclk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena3 and 'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
scandataout <= scandataout_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_dll
--
-- Description : Simulation model for the Cyclone DLL.
--
-- Outputs : Delayctrlout output (active high) indicates when the
-- DLL locks to the incoming clock
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cyclone_atom_pack.all;
USE work.cyclone_pllpack.all;
ENTITY cyclone_dll is
GENERIC ( input_frequency : string := "10000 ps";
phase_shift : string := "0";
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5;
lpm_type : string := "cyclone_dll";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
delayctrlout : OUT std_logic
);
END cyclone_dll;
ARCHITECTURE vital_dll of cyclone_dll is
signal clk_detect : std_logic := '0';
signal clk_ipd : std_logic;
begin
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
process (clk_ipd, clk_detect)
variable got_first_rising_edge : boolean := false;
variable got_first_falling_edge : boolean := false;
variable clk_ipd_last_rising_edge : time := 0 ps;
variable clk_ipd_last_falling_edge : time := 0 ps;
variable inclk_ps : time := 0 ps;
variable duty_cycle : time := 0 ps;
variable clk_per_tolerance : time := 0 ps;
variable clk_detect_count : integer := 0;
variable start_clk_detect : boolean := false;
variable half_cycles_to_lock : integer := 0;
variable half_cycles_to_keep_lock : integer := 0;
variable violation : boolean := false;
variable dll_is_locked : std_logic := '0';
variable init : boolean := true;
variable input_freq_warn : boolean := true;
variable duty_cycle_warn : boolean := true;
begin
if (init) then
-- convert the frequency in string form to integer
inclk_ps := dqs_str2int(input_frequency) * 1 ps;
duty_cycle := inclk_ps/2;
clk_per_tolerance := inclk_ps * 0.1;
-- if sim_valid_lock = 0, dll starts out locked
if (sim_valid_lock = 0) then
dll_is_locked := '1';
end if;
init := false;
end if;
if (clk_ipd'event and clk_ipd = '1') then
if (not got_first_rising_edge) then
got_first_rising_edge := true;
half_cycles_to_lock := half_cycles_to_lock + 1;
if (sim_valid_lock > 0 and half_cycles_to_lock >= sim_valid_lock and not violation) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
-- start the internal clock that will monitor
-- the input clock
if (not start_clk_detect) then
start_clk_detect := true;
clk_detect <= '1';
end if;
else
-- reset clk_event counter
clk_detect_count := 0;
-- check for clk period violation
if ( ((now - clk_ipd_last_rising_edge) < (inclk_ps - clk_per_tolerance)) or ((now - clk_ipd_last_rising_edge) > (inclk_ps + clk_per_tolerance)) ) then
violation := true;
if (input_freq_warn) then
assert false report "Input frequency violation." severity warning;
input_freq_warn := false;
end if;
elsif ( ((now - clk_ipd_last_falling_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_falling_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (violation and dll_is_locked = '1') then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (violation) then
half_cycles_to_lock := 0;
elsif (not violation and dll_is_locked = '0') then
-- increment lock counter
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock > sim_valid_lock) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
else
half_cycles_to_keep_lock := 0;
end if;
end if;
clk_ipd_last_rising_edge := now;
elsif (clk_ipd'event and clk_ipd = '0') then
-- reset clk_event counter
clk_detect_count := 0;
got_first_falling_edge := true;
if (got_first_rising_edge) then
-- check for duty cycle violation
if ( ((now - clk_ipd_last_rising_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_rising_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (dll_is_locked = '1' and violation) then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (dll_is_locked = '1') then
half_cycles_to_keep_lock := 0;
elsif (dll_is_locked = '0' and violation) then
half_cycles_to_lock := 0;
else
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
else
-- first clk edge is falling edge, do nothing
end if;
clk_ipd_last_falling_edge := now;
else
if (clk_ipd'event) then
-- illegal value
if (got_first_rising_edge or got_first_falling_edge) then
if (dll_is_locked = '1') then
dll_is_locked := '0';
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
assert false report "Illegal value detected on input clock. DLL will lose lock." severity error;
else
-- clock started up, then went to 'X'
-- this is to weed out the 'X' at start of simulation.
assert false report "Illegal value detected on input clock." severity error;
-- reset lock counter
half_cycles_to_lock := 0;
end if;
end if;
end if;
end if;
-- ********************************************************************
-- The following block generates the internal clock that is used to
-- track loss of input clock. A counter counts events on this internal
-- clock, and is reset to 0 on event on input clock. If input clock
-- flatlines, the counter will exceed the limit and DLL will lose lock.
-- Events on internal clock are scheduled at the max. allowable input
-- clock tolerance, to allow 'sim_invalid_lock' parameter value = 1.
-- ********************************************************************
if (start_clk_detect) then
if (clk_detect'event and clk_detect /= clk_detect'last_value) then
-- increment clock event counter
clk_detect_count := clk_detect_count + 1;
if (dll_is_locked = '1') then
if (clk_detect_count > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to loss of input clock" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
clk_detect_count := 0;
start_clk_detect := false;
clk_detect <= transport '0' after inclk_ps/2;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
elsif (clk_detect_count > 10) then
assert false report "No input clock : DLL will not lock" severity warning;
clk_detect_count := 0;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
end if;
end if;
delayctrlout <= dll_is_locked;
end process;
end vital_dll;
-------------------------------------------------------------------
--
-- Entity Name : cyclone_jtag
--
-- Description : Cyclone JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cyclone_atom_pack.all;
entity cyclone_jtag is
generic (
lpm_type : string := "cyclone_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cyclone_jtag;
architecture architecture_jtag of cyclone_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cyclone_crcblock
--
-- Description : Cyclone CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cyclone_atom_pack.all;
entity cyclone_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cyclone_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end cyclone_crcblock;
architecture architecture_crcblock of cyclone_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : cyclone_routing_wire
--
-- Description : Cyclone Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cyclone_atom_pack.all;
ENTITY cyclone_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cyclone_routing_wire : entity is TRUE;
end cyclone_routing_wire;
ARCHITECTURE behave of cyclone_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_asynch_io
--
-- Description : Simulation model for asynchronous submodule of
-- Cyclone Lcell.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cyclone_atom_pack.all;
ENTITY cyclone_asynch_io is
generic (
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01
);
port (
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of cyclone_asynch_io : ENTITY is TRUE;
end cyclone_asynch_io;
ARCHITECTURE behave of cyclone_asynch_io is
attribute VITAL_LEVEL0 of behave : ARCHITECTURE is TRUE;
signal datain_ipd : std_logic;
signal oe_ipd : std_logic;
signal padio_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_logic;
variable tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
begin
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif (operation_mode = "output" or
operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then
--for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if (operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or
operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if (oe_ipd = '1') then
if (open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif (oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cyclone_io
--
-- Description : Simulation model for Cyclone IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cyclone_atom_pack.all;
use work.cyclone_asynch_io;
use work.cyclone_dffe;
use work.cyclone_mux21;
ENTITY cyclone_io is
generic (
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
lpm_type : STRING := "cyclone_io"
);
port (
datain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
padio : inout std_logic
);
end cyclone_io;
ARCHITECTURE structure of cyclone_io is
COMPONENT cyclone_asynch_io
generic(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false"
);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
regin : in std_logic;
padio : inout STD_LOGIC;
combout: out STD_LOGIC;
regout : out STD_LOGIC
);
end COMPONENT;
COMPONENT cyclone_dffe
generic(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01
);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1'
);
end COMPONENT;
COMPONENT cyclone_mux21
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end COMPONENT;
signal is_bidir_or_output : std_logic;
signal out_reg_clk_ena : std_logic;
signal oe_reg_clk_ena : std_logic;
signal tmp_oe_reg_out : std_logic;
signal tmp_input_reg_out : std_logic;
signal tmp_output_reg_out : std_logic;
signal inreg_sreset_is_used : std_logic;
signal outreg_sreset_is_used : std_logic;
signal oereg_sreset_is_used : std_logic;
signal inreg_sreset : std_logic;
signal outreg_sreset : std_logic;
signal oereg_sreset : std_logic;
signal in_reg_aclr : std_logic;
signal in_reg_apreset : std_logic;
signal oe_reg_aclr : std_logic;
signal oe_reg_apreset : std_logic;
signal oe_reg_sel : std_logic;
signal out_reg_aclr : std_logic;
signal out_reg_apreset : std_logic;
signal out_reg_sel : std_logic;
signal input_reg_pu_low : std_logic;
signal output_reg_pu_low : std_logic;
signal oe_reg_pu_low : std_logic;
signal inreg_D : std_logic;
signal outreg_D : std_logic;
signal oereg_D : std_logic;
signal tmp_datain : std_logic;
signal tmp_oe : std_logic;
signal iareset : std_logic;
signal isreset : std_logic;
signal inreg_mux_sel : std_logic;
signal outreg_mux_sel : std_logic;
signal oereg_mux_sel : std_logic;
signal input_dffe_aclr : std_logic;
signal input_dffe_apreset : std_logic;
signal output_dffe_aclr : std_logic;
signal output_dffe_apreset : std_logic;
signal oe_dffe_aclr : std_logic;
signal oe_dffe_apreset : std_logic;
begin
is_bidir_or_output <= '1' WHEN (operation_mode = "bidir" OR
operation_mode = "output")
ELSE '0';
input_reg_pu_low <= '0' WHEN input_power_up = "low" ELSE '1';
output_reg_pu_low <= '0' WHEN output_power_up = "low" ELSE '1';
oe_reg_pu_low <= '0' WHEN oe_power_up = "low" ELSE '1';
out_reg_sel <= '1' WHEN output_register_mode = "register" ELSE '0';
oe_reg_sel <= '1' WHEN oe_register_mode = "register" ELSE '0';
iareset <= (NOT areset) WHEN ( areset = '1' OR areset = '0')
ELSE '1';
isreset <= sreset WHEN ( areset = '1' OR areset = '0') ELSE '0';
-- output registere signals
out_reg_aclr <= iareset WHEN output_async_reset = "clear" ELSE '1';
out_reg_apreset <= iareset WHEN output_async_reset = "preset"
ELSE '1';
outreg_sreset_is_used <= '0' WHEN output_sync_reset = "none"
ELSE '1';
outreg_sreset <= '0' WHEN output_sync_reset = "clear" ELSE '1';
-- oe register signals
oe_reg_aclr <= iareset WHEN oe_async_reset = "clear" ELSE '1';
oe_reg_apreset <= iareset WHEN oe_async_reset = "preset" ELSE '1';
oereg_sreset_is_used <= '0' WHEN oe_sync_reset = "none" ELSE '1';
oereg_sreset <= '0' WHEN oe_sync_reset = "clear" ELSE '1';
-- input register signals
in_reg_aclr <= iareset WHEN input_async_reset = "clear" ELSE '1';
in_reg_apreset <= iareset WHEN input_async_reset = "preset"
ELSE '1';
inreg_sreset_is_used <= '0' WHEN input_sync_reset = "none" ELSE '1';
inreg_sreset <= '0' WHEN input_sync_reset = "clear" ELSE '1';
-- oe and output register clock enable signals
out_reg_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true"
ELSE outclkena;
oe_reg_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true"
ELSE outclkena;
-- input register
inreg_mux_sel <= isreset AND inreg_sreset_is_used;
input_dffe_aclr <= in_reg_aclr AND devclrn AND
(input_reg_pu_low OR devpor);
input_dffe_apreset <= in_reg_apreset AND
((NOT input_reg_pu_low) OR devpor);
inreg_D_mux : cyclone_mux21
port map (
A => padio,
B => inreg_sreset,
S => inreg_mux_sel,
MO=> inreg_D
);
input_reg : cyclone_dffe
port map (
D => inreg_D,
CLRN => input_dffe_aclr,
PRN => input_dffe_apreset,
CLK => inclk,
ENA => inclkena,
Q => tmp_input_reg_out
);
-- output register
outreg_mux_sel <= isreset AND outreg_sreset_is_used;
output_dffe_aclr <= out_reg_aclr AND devclrn AND
(output_reg_pu_low OR devpor);
output_dffe_apreset <= out_reg_apreset AND
((NOT output_reg_pu_low) OR devpor);
outreg_D_mux : cyclone_mux21
port map (
A => datain,
B => outreg_sreset,
S => outreg_mux_sel,
MO=> outreg_D
);
output_reg : cyclone_dffe
port map (
D => outreg_D,
CLRN => output_dffe_aclr,
PRN => output_dffe_apreset,
CLK => outclk,
ENA => out_reg_clk_ena,
Q => tmp_output_reg_out
);
-- oe register
oereg_mux_sel <= isreset AND oereg_sreset_is_used;
oe_dffe_aclr <= oe_reg_aclr AND devclrn AND
(oe_reg_pu_low OR devpor);
oe_dffe_apreset <= oe_reg_apreset AND
((NOT oe_reg_pu_low) OR devpor);
oereg_D_mux : cyclone_mux21
port map (
A => oe,
B => oereg_sreset,
S => oereg_mux_sel,
MO=> oereg_D
);
oe_reg : cyclone_dffe
port map (
D => oereg_D,
CLRN => oe_dffe_aclr,
PRN => oe_dffe_apreset,
CLK => outclk,
ENA => oe_reg_clk_ena,
Q => tmp_oe_reg_out
);
-- asynchrous block
tmp_oe <= tmp_oe_reg_out WHEN oe_reg_sel = '1' ELSE oe;
tmp_datain <= tmp_output_reg_out WHEN (is_bidir_or_output = '1' AND
out_reg_sel = '1')
ELSE datain;
asynch_inst : cyclone_asynch_io
generic map (
OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold
)
port map (
datain => tmp_datain,
oe => tmp_oe,
regin => tmp_input_reg_out,
padio => padio,
combout => combout,
regout => regout
);
end structure;
-------------------------------------------------------------------
--
-- Entity Name : cyclone_asmiblock
--
-- Description : Cyclone ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cyclone_atom_pack.all;
entity cyclone_asmiblock is
generic (
lpm_type : string := "cyclone_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
end cyclone_asmiblock;
architecture architecture_asmiblock of cyclone_asmiblock is
begin
process(dclkin, scein, sdoin, oe)
begin
end process;
end architecture_asmiblock; -- end of cyclone_asmiblock
| gpl-3.0 | b7fd73eb24b81377c9628a5da493ff6c | 0.485729 | 3.870901 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_opt_pack-p.vhd | 1 | 1,760 | -------------------------------------------------------------------------------
--
-- $Id: t400_opt_pack-p.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
package t400_opt_pack is
-- Chip type option ---------------------------------------------------------
constant t400_opt_type_420_c : integer := 0;
constant t400_opt_type_421_c : integer := 1;
constant t400_opt_type_410_c : integer := 2;
-- Clock divider option -----------------------------------------------------
constant t400_opt_ck_div_32_c : integer := 3;
constant t400_opt_ck_div_16_c : integer := 2;
constant t400_opt_ck_div_8_c : integer := 1;
constant t400_opt_ck_div_4_c : integer := 0;
-- CKO pin function option --------------------------------------------------
constant t400_opt_cko_crystal_c : integer := 0;
constant t400_opt_cko_gpi_c : integer := 1;
-- Output type option -------------------------------------------------------
constant t400_opt_out_type_std_c : integer := 0;
constant t400_opt_out_type_od_c : integer := 1;
constant t400_opt_out_type_led_c : integer := 2;
constant t400_opt_out_type_pp_c : integer := 3;
-- Microbus option ----------------------------------------------------------
constant t400_opt_no_microbus_c : integer := 0;
constant t400_opt_microbus_c : integer := 1;
end t400_opt_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 06ddee63c15f8fde04f3d2c602948b64 | 0.418182 | 4.074074 | false | false | false | false |
thoralt/KCVGA | FPGA/SRAM_Controller_testbench.vhd | 1 | 2,038 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SRAM_Controller_testbench IS
END SRAM_Controller_testbench;
ARCHITECTURE behavior OF SRAM_Controller_testbench IS
-- inputs
SIGNAL clk : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC := '0';
SIGNAL mem : STD_LOGIC := '0';
SIGNAL rw : STD_LOGIC := '0';
SIGNAL rd_en : STD_LOGIC := '0';
SIGNAL addr : STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL data_f2s : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- outputs
SIGNAL data_s2f : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL ready : STD_LOGIC;
-- SRAM
SIGNAL ad : STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL D : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL nWE, nOE, nCE, nBHE, nBLE : STD_LOGIC;
-- clock period definitions
CONSTANT clk_period : TIME := 10 ns;
BEGIN
-- instantiate the Unit Under Test (UUT)
uut : ENTITY work.SRAM_Controller PORT MAP
(
clk => clk,
reset => rst,
mem => mem,
rw => rw,
addr => addr,
data_f2s => data_f2s,
ready => ready,
data_s2f => data_s2f,
ad => ad,
nWE => nWE,
nOE => nOE,
nCE => nCE,
nBHE => nBHE,
nBLE => nBLE,
D => D);
-- clock process definitions
clk_process : PROCESS
BEGIN
clk <= '0';
WAIT FOR clk_period/2;
clk <= '1';
WAIT FOR clk_period/2;
END PROCESS;
-- stimulus process
stim_proc : PROCESS
BEGIN
-- hold reset state for 100 ns.
WAIT FOR 100 ns;
rst <= '1';
WAIT FOR clk_period * 5;
rst <= '0';
WAIT FOR clk_period * 1;
addr <= "10101010101010101";
rw <= '1';
mem <= '1';
WAIT FOR clk_period * 5;
mem <= '0';
WAIT FOR clk_period * 1;
addr <= "01010101010101010";
rw <= '1';
mem <= '1';
WAIT;
END PROCESS;
END;
| mit | 19be0dd4a87a2fb210dc656239fee2c8 | 0.493131 | 3.746324 | false | false | false | false |
freecores/t400 | rtl/vhdl/system/t400_system_comp_pack-p.vhd | 1 | 12,291 | -------------------------------------------------------------------------------
--
-- $Id: t400_system_comp_pack-p.vhd,v 1.6 2006-06-11 22:18:52 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
package t400_system_comp_pack is
component t410_notri
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
component t410
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end component;
component t411
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(1 downto 0);
io_g_b : inout std_logic_vector(2 downto 0)
);
end component;
component t420_notri
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
component t420
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end component;
component t421
generic (
opt_ck_div_g : integer := t400_opt_ck_div_8_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end component;
end t400_system_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2006/06/11 13:48:13 arniml
-- * t421 added
-- * fixed generic list for t420 and t420_notri
--
-- Revision 1.4 2006/06/05 20:02:46 arniml
-- use microbus generic
--
-- Revision 1.3 2006/05/23 01:16:19 arniml
-- routi CKO to t400_core
--
-- Revision 1.2 2006/05/14 22:29:33 arniml
-- t420 hierarchies added
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 564b9fc0ed0edf9d422327e39fcf721c | 0.547962 | 2.524856 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_elems.vhd | 1 | 9,392 | -------------------------------------------------------------------------------
--
-- Generic testbench elements
--
-- $Id: tb_elems.vhd,v 1.6 2006-05-27 22:48:00 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_elems is
generic (
period_g : time := 4.75 us;
d_width_g : integer := 4;
g_width_g : integer := 4
);
port (
io_l_i : in std_logic_vector(7 downto 0);
io_d_i : in std_logic_vector(d_width_g-1 downto 0);
io_g_i : in std_logic_vector(g_width_g-1 downto 0);
io_in_o : out std_logic_vector(g_width_g-1 downto 0);
so_i : in std_logic;
si_o : out std_logic;
sk_i : in std_logic;
ck_o : out std_logic
);
end tb_elems;
library ieee;
use ieee.numeric_std.all;
architecture behav of tb_elems is
signal en_ck_s : std_logic;
begin
en_ck_s <= 'H';
-----------------------------------------------------------------------------
-- Pass/fail catcher
-----------------------------------------------------------------------------
pass_fail: process (io_l_i)
type pass_fail_t is (IDLE,
GOT_0, GOT_A, GOT_5);
variable state_v : pass_fail_t := IDLE;
variable sig_v : std_logic_vector(3 downto 0);
begin
sig_v := to_X01(io_l_i(7 downto 4));
case state_v is
when IDLE =>
en_ck_s <= 'Z';
if sig_v = "0000" then
state_v := GOT_0;
end if;
when GOT_0 =>
if sig_v = "1010" then
state_v := GOT_A;
elsif sig_v /= "0000" then
state_v := IDLE;
end if;
when GOT_A =>
if sig_v = "0101" then
state_v := GOT_5;
elsif sig_v /= "1010" then
state_v := IDLE;
end if;
when GOT_5 =>
if sig_v = "0000" then
en_ck_s <= '0';
assert false
report "Simulation finished with PASS."
severity note;
elsif sig_v = "1111" then
en_ck_s <= '0';
assert false
report "Simulation finished with FAIL."
severity note;
elsif sig_v /= "0101" then
state_v := IDLE;
end if;
end case;
end process pass_fail;
-----------------------------------------------------------------------------
-- D monitor
-----------------------------------------------------------------------------
d_moni: process (io_d_i)
type d_moni_t is (IDLE,
STEP_1, STEP_2,
STEP_3, STEP_4);
variable state_v : d_moni_t := IDLE;
variable sig_v : unsigned(3 downto 0);
begin
sig_v := (others => '0');
sig_v(io_d_i'range) := unsigned(to_X01(io_d_i));
case state_v is
when IDLE =>
en_ck_s <= 'Z';
if sig_v = 1 then
state_v := STEP_1;
end if;
when STEP_1 =>
if sig_v = 2 then
state_v := STEP_2;
else
state_v := IDLE;
end if;
when STEP_2 =>
if sig_v = 4 then
state_v := STEP_3;
elsif sig_v /= 0 then
state_v := IDLE;
else
-- sim finished for 2-bit D ports
en_ck_s <= '0';
assert false
report "Simulation finished with PASS (D-Port 2 bit)."
severity note;
end if;
when STEP_3 =>
if sig_v = 8 then
state_v := STEP_4;
elsif sig_v /= 0 then
state_v := IDLE;
else
-- sim finished for 3-bit D ports
en_ck_s <= '0';
assert false
report "Simulation finished with PASS (D-Port 3 bit)."
severity note;
end if;
when STEP_4 =>
if sig_v = 15 then
-- sim finished pass for 4-bit D ports
en_ck_s <= '0';
assert false
report "Simulation finished with PASS (D-Port 4 bit)."
severity note;
elsif sig_v = 0 then
-- sim finished fail for 4-bit D ports
en_ck_s <= '0';
assert false
report "Simulation finished with FAIL (D-Port 4 bit)."
severity note;
else
state_v := IDLE;
end if;
when others =>
null;
end case;
end process d_moni;
-----------------------------------------------------------------------------
-- G monitor
-----------------------------------------------------------------------------
g_moni: process (io_g_i)
type d_moni_t is (IDLE,
STEP_1, STEP_2, STEP_3,
STEP_4);
variable state_v : d_moni_t := IDLE;
variable sig_v : unsigned(3 downto 0);
begin
sig_v := (others => '0');
sig_v(io_g_i'range) := unsigned(to_X01(io_g_i));
case state_v is
when IDLE =>
en_ck_s <= 'Z';
if sig_v = 1 then
state_v := STEP_1;
end if;
when STEP_1 =>
if sig_v = 2 then
state_v := STEP_2;
else
state_v := IDLE;
end if;
when STEP_2 =>
if sig_v = 4 then
state_v := STEP_3;
else
state_v := IDLE;
end if;
when STEP_3 =>
if sig_v = 8 then
state_v := STEP_4;
elsif sig_v /= 0 then
state_v := IDLE;
else
-- sim finished for 3-bit G ports
en_ck_s <= '0';
assert false
report "Simulation finished with PASS (G-Port 3 bit)."
severity note;
end if;
when STEP_4 =>
if sig_v /= 15 then
state_v := IDLE;
else
-- sim finished for 4-bit G ports
en_ck_s <= '0';
assert false
report "Simulation finished with PASS (G-Port 4 bit)."
severity note;
end if;
when others =>
null;
end case;
end process g_moni;
-- feed back G on IN
io_in_o <= io_g_i;
-----------------------------------------------------------------------------
-- SIO peer
-----------------------------------------------------------------------------
sio_peer: process
begin
si_o <= '0';
wait until io_l_i(4) = '0';
while io_l_i(4) = '0' loop
si_o <= so_i xor sk_i after 10 us;
wait until io_l_i'event or so_i'event or sk_i'event;
end loop;
-- now feed SO back to SI upon SK edge
loop
wait until sk_i'event and sk_i = '1';
si_o <= so_i after 10 us;
end loop;
wait;
end process sio_peer;
-----------------------------------------------------------------------------
-- Clock generator
-----------------------------------------------------------------------------
clk: process
begin
ck_o <= '0';
wait for period_g / 2;
ck_o <= '1';
wait for period_g / 2;
if to_X01(en_ck_s) /= '1' then
wait;
end if;
end process clk;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2006/05/27 19:08:53 arniml
-- add fail reporting for port d
--
-- Revision 1.4 2006/05/23 01:17:25 arniml
-- drive IN port
--
-- Revision 1.3 2006/05/18 00:24:18 arniml
-- extend D-port checks
--
-- Revision 1.2 2006/05/17 00:47:45 arniml
-- enhance G-port check for T420
--
-- Revision 1.1 2006/05/15 21:55:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 486621754694255102c2514af23fc97f | 0.485945 | 3.936295 | false | false | false | false |
alvieboy/xtc-base | uart_mv_filter.vhd | 1 | 2,412 | --
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end entity uart_mv_filter;
architecture behave of uart_mv_filter is
signal count_q: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
count_q <= (others => '0');
sout <= '0';
else
if clear='1' then
count_q <= (others => '0');
sout <= '0';
else
if enable='1' then
if sin='1' then
count_q <= count_q + 1;
end if;
end if;
if (count_q >= threshold) then
sout<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause | 34bbfc5106c9c3325610c7d1d506edf8 | 0.655058 | 3.751166 | false | false | false | false |
freecores/t400 | rtl/tech/spartan/t400_por.vhd | 1 | 3,582 | -------------------------------------------------------------------------------
--
-- T400 Core
--
-- $Id: t400_por.vhd,v 1.1 2006-05-07 01:47:51 arniml Exp $
--
-- Wrapper for technology dependent power-on reset circuitry.
--
-- Xilinx Spartan3 flavor.
--
-- Generate a reset upon power-on for specified number of clocks.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_por is
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end t400_por;
library ieee;
use ieee.numeric_std.all;
architecture spartan of t400_por is
-----------------------------------------------------------------------------
-- According to
-- "XST User Guide", Chapter 6 "VHDL Language Support", "Initial Values"
-- XST honors the initial value assigned to a flip-flop. Simple :-)
--
signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
:= to_unsigned(delay_g, cnt_width_g);
signal por_n_q : std_logic := '0';
--
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
-- Process por_cnt
--
-- Purpose:
-- Generate a power-on reset for the specified number of clocks.
--
por_cnt: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if por_cnt_q = 0 then
por_n_q <= '1';
else
por_cnt_q <= por_cnt_q - 1;
end if;
end if;
end process por_cnt;
--
-----------------------------------------------------------------------------
por_n_o <= por_n_q;
end spartan;
| gpl-2.0 | dac7d714681572715d87c7f4207b89c9 | 0.587661 | 4.422222 | false | false | false | false |
google/myelin-acorn-electron-hardware | master_updateable_megarom/cpld/master_updateable_megarom.vhd | 1 | 5,817 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity master_updateable_megarom is
Port (
D : inout std_logic_vector(7 downto 0);
bbc_A : in std_logic_vector(16 downto 0);
bbc_nCS : in std_logic;
flash_A : out std_logic_vector(18 downto 0);
--flash_nCE : out std_logic;
flash_nOE : out std_logic;
flash_nWE : out std_logic;
cpld_SCK : in std_logic;
cpld_MOSI : in std_logic;
cpld_SS : in std_logic;
cpld_MISO : out std_logic;
cpld_JP : in std_logic_vector(1 downto 0)
);
end master_updateable_megarom;
architecture Behavioural of master_updateable_megarom is
signal A : std_logic_vector(18 downto 0);
signal Dout : std_logic_vector(7 downto 0);
-- these two are set
signal allowing_bbc_access : std_logic := '1';
signal accessing_memory : std_logic := '0';
signal rnw : std_logic := '0';
-- SPI temp vars --
-- the value clocked out of D<7> on the falling SCK edge
signal last_d7 : std_logic := '0';
signal last_mosi : std_logic := '0';
-- flag to say if we're clocking through D/A/RnW or not (so we don't mess with them during the flash access period)
signal clocking_spi_data : std_logic := '0';
-- counts up to 50; need 6 bits
signal spi_bit_count : unsigned(5 downto 0) := "000000";
begin
-- We're either passing bbc_A through to flash_A, with D tristated, or we're
-- controlling both and ignoring bbc_A.
flash_A <= "00" & bbc_A when (allowing_bbc_access = '1') else A;
-- assert OE
flash_nOE <= '0' when (allowing_bbc_access = '1'
or (accessing_memory = '1' and rnw = '1')) else '1';
-- leave flash enabled all the time (TODO maybe just enable when /OE or /WE is active)
flash_nCE <= '0';
-- assert WE and D when the BBC is disabled and we're doing a memory write
flash_nWE <= '0' when (allowing_bbc_access = '0'
and (accessing_memory = '1' and rnw = '0')) else '1';
-- drive D when writing
D <= Dout when (allowing_bbc_access = '0'
and (accessing_memory = '1' and rnw = '0')) else "ZZZZZZZZ";
-- MISO always gets the last thing we clocked out of Dout
cpld_MISO <= last_d7;
process (cpld_SS, cpld_SCK)
begin
if cpld_SS = '1' then
clocking_spi_data <= '1';
accessing_memory <= '0';
spi_bit_count <= "000000";
elsif rising_edge(cpld_SCK) then
-- the master device should bring cpld_SS high between every transaction.
-- to block out the BBC and enable flash access: send 32 bits of zeros.
-- to reenable the BBC, send 32 bits of ones.
-- message format: 17 address bits, rnw, 8 data bits, 6 zeros (32 bits total) then 8 clocks to retrieve data
-- to get out of flash update mode, pass "000001" instead of the 6 zeros. (the last bit gets copied into allowing_bbc_access.)
-- we use the trailing zeros to perform the access to the flash chip.
-- the flash chip only needs a 40ns low pulse on /CE + /WE, and its read access time is 55-70ns;
-- there's another cycle time which is around 150ns also.
-- if we want the same timings as on the bbc (250ns), that means we're OK with an SPI clock up to maybe 24 MHz.
-- Example read, with RnW = 1:
-- SCK ___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___
-- MOSI X D1 X D0 X 0 X 0 X 0 X 0 X 0 X 0 X
-- MISO X D7 X D6 X ...
-- Because we have to clock D on falling edges, we're stuck doing that every time.
-- TODO switch it around so the count increments on the falling edge,
-- which lets us stop clocking as soon as we've got the last bit into D,
-- and start our memory access a half-cycle after bit 26 is in
if clocking_spi_data = '1' then
last_mosi <= cpld_MOSI;
A <= A(17 downto 0) & rnw;
rnw <= last_d7; -- change to use D(7) if we end up off by one here
end if;
-- stop clocking after the 26th bit, i.e. when count=25, and start again after bit 32
if spi_bit_count = 25 then
clocking_spi_data <= '0';
accessing_memory <= '1';
end if;
if spi_bit_count = 32 then
allowing_bbc_access <= cpld_MOSI;
accessing_memory <= '0';
clocking_spi_data <= '1';
end if;
spi_bit_count <= spi_bit_count + 1;
end if;
end process;
process (cpld_SS, cpld_SCK)
begin
if cpld_SS = '1' then
elsif falling_edge(cpld_SCK) then
if clocking_spi_data = '1' then
last_d7 <= Dout(7);
Dout <= D(6 downto 0) & last_mosi;
elsif accessing_memory = '1' and rnw = '1' then
Dout <= D;
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | c870a120b84abd3c635ecec5a5116f89 | 0.566959 | 3.769929 | false | false | false | false |
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